diff --git a/.github/workflows/examples.yml b/.github/workflows/examples.yml index ba04be2..08c0104 100644 --- a/.github/workflows/examples.yml +++ b/.github/workflows/examples.yml @@ -13,6 +13,7 @@ jobs: - "examples/gd32-arduino-blinky" - "examples/gd32-mbedos-baremetal-blinky" - "examples/gd32-spl-blinky" + - "examples/gd32-vw55x-blinky" - "examples/gd32-w51x-wifi-scan" - "examples/gd32-e503c_start-spl-blinky" - "examples/zephyr-blink" diff --git a/boards/gd32vw553k_start.json b/boards/gd32vw553k_start.json new file mode 100644 index 0000000..e8c3cf8 --- /dev/null +++ b/boards/gd32vw553k_start.json @@ -0,0 +1,50 @@ +{ + "build": { + "core": "n307fd", + "f_cpu": "160000000L", + "cpu": "rv32imac_zba_zbb_zbc_zbs_xxldspn1x", + "hwids": [ + [ + "0x0403", + "0x6010" + ] + ], + "arch_ext": "_zba_zbb_zbc_zbs_xxldspn1x", + "soc": "gd32vw55x", + "mcu": "gd32vw553kmq6", + "download": "flashxip", + "ldscript": "", + "download_modes": [ + "flashxip", + "sram" + ], + "spl_series": "GD32VW55x", + "series": "GD32VW55x" + }, + "debug": { + "jlink_device": "GD32VW553HM", + "svd_path": "GD32VW55X.svd", + "openocd_target": "gd32vw55x.cfg", + "onboard_tools": [ + "gd-link" + ] + }, + "frameworks": [ + "spl" + ], + "name": "GD32VW553K-START Board", + "upload": { + "maximum_ram_size": 294912, + "maximum_size": 2097152, + "flash_start": "0x08000000", + "sram_start": "0x20000000", + "protocol": "gdlinkcli", + "protocols": [ + "cmsis-dap", + "jlink", + "gdlinkcli" + ] + }, + "url": "https://www.gigadevice.com/product/mcu/risc-v", + "vendor": "GigaDevice" +} diff --git a/builder/frameworks/_bare.py b/builder/frameworks/_bare.py index 6cf01d5..9fdf356 100644 --- a/builder/frameworks/_bare.py +++ b/builder/frameworks/_bare.py @@ -17,6 +17,7 @@ # from SCons.Script import DefaultEnvironment +from os.path import join env = DefaultEnvironment() @@ -27,8 +28,7 @@ "-Os", # optimize for size "-ffunction-sections", # place each function in its own section "-fdata-sections", - "-Wall", - "-mthumb" + "-Wall" ], CXXFLAGS=[ @@ -44,22 +44,50 @@ LINKFLAGS=[ "-Os", - "-Wl,--gc-sections,--relax", - "-mthumb" + '-Wl,-Map="%s"' % join("${BUILD_DIR}", "${PROGNAME}.map"), + "-Wl,--gc-sections,--relax" ], LIBS=["c", "gcc", "m", "stdc++"] ) if "BOARD" in env: - env.Append( - CCFLAGS=[ - "-mcpu=%s" % env.BoardConfig().get("build.cpu") - ], - LINKFLAGS=[ - "-mcpu=%s" % env.BoardConfig().get("build.cpu") - ] - ) + board = env.BoardConfig() + is_riscv = board.get("build.mcu", "").startswith("gd32vw") + + if is_riscv: + env.Append( + CCFLAGS=[ + "-march=%s" % board.get("build.cpu"), + "-mabi=ilp32" + ], + LINKFLAGS=[ + "-march=%s" % board.get("build.cpu"), + "-mabi=ilp32", + "-nostartfiles", + "-Wl,--no-warn-rwx-segments" + ] + ) + else: #arm + env.Append( + CCFLAGS=[ + "-mcpu=%s" % board.get("build.cpu"), + "-mthumb" + ], + LINKFLAGS=[ + "-mcpu=%s" % board.get("build.cpu"), + "-mthumb" + ] + ) # copy CCFLAGS to ASFLAGS (-x assembler-with-cpp mode) env.Append(ASFLAGS=env.get("CCFLAGS", [])[:]) + +# create .lst file +env.AddPostAction( + "$BUILD_DIR/${PROGNAME}.elf", + env.VerboseAction(" ".join([ + "$OBJDUMP", "-drwC", + "$BUILD_DIR/${PROGNAME}.elf", ">", "$BUILD_DIR/${PROGNAME}.lst" + ]), "Building .pio/build/$PIOENV/${PROGNAME}.lst") +) \ No newline at end of file diff --git a/builder/frameworks/spl.py b/builder/frameworks/spl.py index ee83b2d..2f25885 100644 --- a/builder/frameworks/spl.py +++ b/builder/frameworks/spl.py @@ -32,6 +32,8 @@ env.SConscript("_bare.py") +is_riscv = board.get("build.mcu", "").startswith("gd32vw") + def get_flag_value(flag_name:str, default_val:bool): flag_val = board.get("build.%s" % flag_name, default_val) flag_val = str(flag_val).lower() in ("1", "yes", "true") @@ -143,10 +145,14 @@ def get_startup_filename(board): startup_file = f"startup_{spl_series.lower()}.S" return startup_file +if is_riscv: + core_path = join(FRAMEWORK_DIR, spl_chip_type, "cmsis", "cores", "gd32_riscv", "drivers") +else: #arm + core_path = join(FRAMEWORK_DIR, spl_chip_type, "cmsis", "cores", spl_chip_type) + env.Append( CPPPATH=[ - join(FRAMEWORK_DIR, spl_chip_type, - "cmsis", "cores", spl_chip_type), + core_path, join(FRAMEWORK_DIR, spl_chip_type, "cmsis", "startup_files"), join(FRAMEWORK_DIR, spl_chip_type, "cmsis", @@ -178,14 +184,6 @@ def get_startup_filename(board): extra_flags = board.get("build.extra_flags", "") src_filter_patterns = ["+<*>"] # could come in handy later to exclude certain files, not needed / trigger now -if "STM32F40_41xxx" in extra_flags: - src_filter_patterns += ["-"] -if "STM32F427_437xx" in extra_flags: - src_filter_patterns += ["-"] -elif "STM32F303xC" in extra_flags: - src_filter_patterns += ["-"] -elif "STM32L1XX_MD" in extra_flags: - src_filter_patterns += ["-"] libs = [] diff --git a/builder/main.py b/builder/main.py index 290dcc1..7bd2afd 100644 --- a/builder/main.py +++ b/builder/main.py @@ -104,15 +104,19 @@ def _update_max_upload_size(env): platform = env.PioPlatform() board = env.BoardConfig() +is_riscv = board.get("build.mcu", "").startswith("gd32vw") +toolchain_triple = "arm-none-eabi" if not is_riscv else "riscv64-unknown-elf" + env.Replace( - AR="arm-none-eabi-gcc-ar", - AS="arm-none-eabi-as", - CC="arm-none-eabi-gcc", - CXX="arm-none-eabi-g++", - GDB="arm-none-eabi-gdb", - OBJCOPY="arm-none-eabi-objcopy", - RANLIB="arm-none-eabi-gcc-ranlib", - SIZETOOL="arm-none-eabi-size", + AR="%s-gcc-ar" % toolchain_triple, + AS="%s-as" % toolchain_triple, + CC="%s-gcc" % toolchain_triple, + CXX="%s-g++" % toolchain_triple, + GDB="%s-gdb" % toolchain_triple, + OBJCOPY="%s-objcopy" % toolchain_triple, + OBJDUMP="%s-objdump" % toolchain_triple, + RANLIB="%s-gcc-ranlib" % toolchain_triple, + SIZETOOL="%s-size" % toolchain_triple, ARFLAGS=["rc"], diff --git a/examples/gd32-vw55x-blinky/.gitignore b/examples/gd32-vw55x-blinky/.gitignore new file mode 100644 index 0000000..b9f3806 --- /dev/null +++ b/examples/gd32-vw55x-blinky/.gitignore @@ -0,0 +1,2 @@ +.pio +.vscode diff --git a/examples/gd32-vw55x-blinky/include/README b/examples/gd32-vw55x-blinky/include/README new file mode 100644 index 0000000..194dcd4 --- /dev/null +++ b/examples/gd32-vw55x-blinky/include/README @@ -0,0 +1,39 @@ + +This directory is intended for project header files. + +A header file is a file containing C declarations and macro definitions +to be shared between several project source files. You request the use of a +header file in your project source file (C, C++, etc) located in `src` folder +by including it, with the C preprocessing directive `#include'. + +```src/main.c + +#include "header.h" + +int main (void) +{ + ... +} +``` + +Including a header file produces the same results as copying the header file +into each source file that needs it. Such copying would be time-consuming +and error-prone. With a header file, the related declarations appear +in only one place. If they need to be changed, they can be changed in one +place, and programs that include the header file will automatically use the +new version when next recompiled. The header file eliminates the labor of +finding and changing all the copies as well as the risk that a failure to +find one copy will result in inconsistencies within a program. + +In C, the usual convention is to give header files names that end with `.h'. +It is most portable to use only letters, digits, dashes, and underscores in +header file names, and at most one dot. + +Read more about using header files in official GCC documentation: + +* Include Syntax +* Include Operation +* Once-Only Headers +* Computed Includes + +https://gcc.gnu.org/onlinedocs/cpp/Header-Files.html diff --git a/examples/gd32-vw55x-blinky/lib/README b/examples/gd32-vw55x-blinky/lib/README new file mode 100644 index 0000000..6debab1 --- /dev/null +++ b/examples/gd32-vw55x-blinky/lib/README @@ -0,0 +1,46 @@ + +This directory is intended for project specific (private) libraries. +PlatformIO will compile them to static libraries and link into executable file. + +The source code of each library should be placed in a an own separate directory +("lib/your_library_name/[here are source files]"). + +For example, see a structure of the following two libraries `Foo` and `Bar`: + +|--lib +| | +| |--Bar +| | |--docs +| | |--examples +| | |--src +| | |- Bar.c +| | |- Bar.h +| | |- library.json (optional, custom build options, etc) https://docs.platformio.org/page/librarymanager/config.html +| | +| |--Foo +| | |- Foo.c +| | |- Foo.h +| | +| |- README --> THIS FILE +| +|- platformio.ini +|--src + |- main.c + +and a contents of `src/main.c`: +``` +#include +#include + +int main (void) +{ + ... +} + +``` + +PlatformIO Library Dependency Finder will find automatically dependent +libraries scanning project source files. + +More information about PlatformIO Library Dependency Finder +- https://docs.platformio.org/page/librarymanager/ldf.html diff --git a/examples/gd32-vw55x-blinky/platformio.ini b/examples/gd32-vw55x-blinky/platformio.ini new file mode 100644 index 0000000..3b5a451 --- /dev/null +++ b/examples/gd32-vw55x-blinky/platformio.ini @@ -0,0 +1,14 @@ +; PlatformIO Project Configuration File +; +; Build options: build flags, source filter +; Upload options: custom upload port, speed and extra flags +; Library options: dependencies, extra library storages +; Advanced options: extra scripting +; +; Please visit documentation for the other options and examples +; https://docs.platformio.org/page/projectconf.html + +[env:gd32vw553k_start] +platform = gd32 +board = gd32vw553k_start +framework = spl diff --git a/examples/gd32-vw55x-blinky/src/handlers.c b/examples/gd32-vw55x-blinky/src/handlers.c new file mode 100644 index 0000000..0d32939 --- /dev/null +++ b/examples/gd32-vw55x-blinky/src/handlers.c @@ -0,0 +1,263 @@ +/* + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * Copyright (c) 2024, GigaDevice Semiconductor Inc. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* This file refers the RISC-V standard, some adjustments are made according to GigaDevice chips */ + +#include "gd32vw55x.h" + +typedef struct EXC_Frame { + unsigned long ra; /* ra: x1, return address for jump */ + unsigned long tp; /* tp: x4, thread pointer */ + unsigned long t0; /* t0: x5, temporary register 0 */ + unsigned long t1; /* t1: x6, temporary register 1 */ + unsigned long t2; /* t2: x7, temporary register 2 */ + unsigned long a0; /* a0: x10, return value or function argument 0 */ + unsigned long a1; /* a1: x11, return value or function argument 1 */ + unsigned long a2; /* a2: x12, function argument 2 */ + unsigned long a3; /* a3: x13, function argument 3 */ + unsigned long a4; /* a4: x14, function argument 4 */ + unsigned long a5; /* a5: x15, function argument 5 */ + unsigned long mcause; /* mcause: machine cause csr register */ + unsigned long mepc; /* mepc: machine exception program counter csr register */ + unsigned long msubm; /* msubm: machine sub-mode csr register, nuclei customized */ +#ifndef __riscv_32e + unsigned long a6; /* a6: x16, function argument 6 */ + unsigned long a7; /* a7: x17, function argument 7 */ + unsigned long t3; /* t3: x28, temporary register 3 */ + unsigned long t4; /* t4: x29, temporary register 4 */ + unsigned long t5; /* t5: x30, temporary register 5 */ + unsigned long t6; /* t6: x31, temporary register 6 */ +#endif +} EXC_Frame_Type; + +/** + * \defgroup NMSIS_Core_IntExcNMI_Handling Interrupt and Exception and NMI Handling + * \brief Functions for interrupt, exception and nmi handle available in system_.c. + * \details + * Nuclei provide a template for interrupt, exception and NMI handling. Silicon Vendor could adapat according + * to their requirement. Silicon vendor could implement interface for different exception code and + * replace current implementation. + * + * @{ + */ +/** \brief Max exception handler number, don't include the NMI(0xFFF) one */ +#define MAX_SYSTEM_EXCEPTION_NUM 12 +/** + * \brief Store the exception handlers for each exception ID + * \note + * - This SystemExceptionHandlers are used to store all the handlers for all + * the exception codes Nuclei N/NX core provided. + * - Exception code 0 - 11, totally 12 exceptions are mapped to SystemExceptionHandlers[0:11] + * - Exception for NMI is also re-routed to exception handling(exception code 0xFFF) in startup code configuration, the handler itself is mapped to SystemExceptionHandlers[MAX_SYSTEM_EXCEPTION_NUM] + */ +static unsigned long SystemExceptionHandlers[MAX_SYSTEM_EXCEPTION_NUM + 1]; + +/** + * \brief Exception Handler Function Typedef + * \note + * This typedef is only used internal in this system_.c file. + * It is used to do type conversion for registered exception handler before calling it. + */ +typedef void (*EXC_HANDLER)(unsigned long mcause, unsigned long sp); + +void Exception_DumpFrame(unsigned long sp); + +/** + * \brief System Default Exception Handler + * \details + * This function provided a default exception and NMI handling code for all exception ids. + * By default, It will just print some information for debug, Vendor can customize it according to its requirements. + */ +static void system_default_exception_handler(unsigned long mcause, unsigned long sp) +{ + /* TODO: Uncomment this if you have implement printf function */ +// printf("MCAUSE : 0x%lx\r\n", mcause); +// printf("MDCAUSE: 0x%lx\r\n", __RV_CSR_READ(CSR_MDCAUSE)); +// printf("MEPC : 0x%lx\r\n", __RV_CSR_READ(CSR_MEPC)); +// printf("MTVAL : 0x%lx\r\n", __RV_CSR_READ(CSR_MTVAL)); + Exception_DumpFrame(sp); + while (1); +} + +/** + * \brief NMI Handler + * \details + * This function provided a NMI handling code for NMI_EXCn. + * By default, It will just print some information for debug, Vendor can customize it according to its requirements. + */ +void nmi_handler(unsigned long mcause, unsigned long sp) +{ + /* TODO: Uncomment this if you have implement printf function */ +// printf("NMI \r\n"); +// printf("MCAUSE : 0x%lx\r\n", mcause); +// printf("MDCAUSE: 0x%lx\r\n", __RV_CSR_READ(CSR_MDCAUSE)); +// printf("MEPC : 0x%lx\r\n", __RV_CSR_READ(CSR_MEPC)); +// printf("MTVAL : 0x%lx\r\n", __RV_CSR_READ(CSR_MTVAL)); + Exception_DumpFrame(sp); + while (1); +} + +/** + * \brief Initialize all the default core exception handlers + * \details + * The core exception handler for each exception id will be initialized to \ref system_default_exception_handler. + * \note + * Called in \ref _init function, used to initialize default exception handlers for all exception IDs + */ +void Exception_Init(void) +{ + for (int i = 0; i < MAX_SYSTEM_EXCEPTION_NUM + 1; i++) { + SystemExceptionHandlers[i] = (unsigned long)system_default_exception_handler; + } +} + +/** + * \brief Register an exception handler for exception code EXCn + * \details + * * For EXCn < \ref MAX_SYSTEM_EXCEPTION_NUM, it will be registered into SystemExceptionHandlers[EXCn-1]. + * * For EXCn == NMI_EXCn, it will be registered into SystemExceptionHandlers[MAX_SYSTEM_EXCEPTION_NUM]. + * \param EXCn See \ref EXCn_Type + * \param exc_handler The exception handler for this exception code EXCn + */ +void Exception_Register_EXC(uint32_t EXCn, unsigned long exc_handler) +{ + if ((EXCn < MAX_SYSTEM_EXCEPTION_NUM) && (EXCn >= 0)) { + SystemExceptionHandlers[EXCn] = exc_handler; + } else if (EXCn == NMI_EXCn) { + SystemExceptionHandlers[MAX_SYSTEM_EXCEPTION_NUM] = exc_handler; + } +} + +/** + * \brief Get current exception handler for exception code EXCn + * \details + * * For EXCn < \ref MAX_SYSTEM_EXCEPTION_NUM, it will return SystemExceptionHandlers[EXCn-1]. + * * For EXCn == NMI_EXCn, it will return SystemExceptionHandlers[MAX_SYSTEM_EXCEPTION_NUM]. + * \param EXCn See \ref EXCn_Type + * \return Current exception handler for exception code EXCn, if not found, return 0. + */ +unsigned long Exception_Get_EXC(uint32_t EXCn) +{ + if ((EXCn < MAX_SYSTEM_EXCEPTION_NUM) && (EXCn >= 0)) { + return SystemExceptionHandlers[EXCn]; + } else if (EXCn == NMI_EXCn) { + return SystemExceptionHandlers[MAX_SYSTEM_EXCEPTION_NUM]; + } else { + return 0; + } +} + +/** + * \brief Common NMI and Exception handler entry + * \details + * This function provided a command entry for NMI and exception. Silicon Vendor could modify + * this template implementation according to requirement. + * \remarks + * - RISCV provided common entry for all types of exception. This is proposed code template + * for exception entry function, Silicon Vendor could modify the implementation. + * - For the core_exception_handler template, we provided exception register function \ref Exception_Register_EXC + * which can help developer to register your exception handler for specific exception number. + */ +uint32_t core_exception_handler(unsigned long mcause, unsigned long sp) +{ + uint32_t EXCn = (uint32_t)(mcause & 0X00000fff); + EXC_HANDLER exc_handler; + + if ((EXCn < MAX_SYSTEM_EXCEPTION_NUM) && (EXCn >= 0)) { + exc_handler = (EXC_HANDLER)SystemExceptionHandlers[EXCn]; + } else if (EXCn == NMI_EXCn) { + exc_handler = (EXC_HANDLER)SystemExceptionHandlers[MAX_SYSTEM_EXCEPTION_NUM]; + } else { + exc_handler = (EXC_HANDLER)system_default_exception_handler; + } + if (exc_handler != NULL) { + exc_handler(mcause, sp); + } + return 0; +} +/** @} */ /* End of Doxygen Group NMSIS_Core_ExceptionAndNMI */ + +/** + * \brief Dump Exception Frame + * \details + * This function provided feature to dump exception frame stored in stack. + */ +void Exception_DumpFrame(unsigned long sp) +{ + EXC_Frame_Type *exc_frame = (EXC_Frame_Type *)sp; + +#ifndef __riscv_32e + /* TODO: Uncomment this if you have implement printf function */ +// printf("ra: 0x%x, tp: 0x%x, t0: 0x%x, t1: 0x%x, t2: 0x%x, t3: 0x%x, t4: 0x%x, t5: 0x%x, t6: 0x%x\n" \ +// "a0: 0x%x, a1: 0x%x, a2: 0x%x, a3: 0x%x, a4: 0x%x, a5: 0x%x, a6: 0x%x, a7: 0x%x\n" \ +// "mcause: 0x%x, mepc: 0x%x, msubm: 0x%x\n", exc_frame->ra, exc_frame->tp, exc_frame->t0, \ +// exc_frame->t1, exc_frame->t2, exc_frame->t3, exc_frame->t4, exc_frame->t5, exc_frame->t6, \ +// exc_frame->a0, exc_frame->a1, exc_frame->a2, exc_frame->a3, exc_frame->a4, exc_frame->a5, \ +// exc_frame->a6, exc_frame->a7, exc_frame->mcause, exc_frame->mepc, exc_frame->msubm); +#else + /* TODO: Uncomment this if you have implement printf function */ +// printf("ra: 0x%x, tp: 0x%x, t0: 0x%x, t1: 0x%x, t2: 0x%x\n" \ +// "a0: 0x%x, a1: 0x%x, a2: 0x%x, a3: 0x%x, a4: 0x%x, a5: 0x%x\n" \ +// "mcause: 0x%x, mepc: 0x%x, msubm: 0x%x\n", exc_frame->ra, exc_frame->tp, exc_frame->t0, \ +// exc_frame->t1, exc_frame->t2, exc_frame->a0, exc_frame->a1, exc_frame->a2, exc_frame->a3, \ +// exc_frame->a4, exc_frame->a5, exc_frame->mcause, exc_frame->mepc, exc_frame->msubm); +#endif +} + +#if 0 +/** + * \brief Initialize a specific IRQ and register the handler + * \details + * This function set vector mode, trigger mode and polarity, interrupt level and priority, + * assign handler for specific IRQn. + * \param [in] IRQn NMI interrupt handler address + * \param [in] shv \ref ECLIC_NON_VECTOR_INTERRUPT means non-vector mode, and \ref ECLIC_VECTOR_INTERRUPT is vector mode + * \param [in] trig_mode see \ref ECLIC_TRIGGER_Type + * \param [in] lvl interupt level + * \param [in] priority interrupt priority + * \param [in] handler interrupt handler, if NULL, handler will not be installed + * \return -1 means invalid input parameter. 0 means successful. + * \remarks + * - This function use to configure specific eclic interrupt and register its interrupt handler and enable its interrupt. + * - If the vector table is placed in read-only section(FLASHXIP mode), handler could not be installed + */ +int32_t ECLIC_Register_IRQ(IRQn_Type IRQn, uint8_t shv, ECLIC_TRIGGER_Type trig_mode, uint8_t lvl, uint8_t priority, void* handler) +{ + if ((IRQn > SOC_INT_MAX) || (shv > ECLIC_VECTOR_INTERRUPT) \ + || (trig_mode > ECLIC_NEGTIVE_EDGE_TRIGGER)) { + return -1; + } + + /* set interrupt vector mode */ + ECLIC_SetShvIRQ(IRQn, shv); + /* set interrupt trigger mode and polarity */ + ECLIC_SetTrigIRQ(IRQn, trig_mode); + /* set interrupt level */ + ECLIC_SetLevelIRQ(IRQn, lvl); + /* set interrupt priority */ + ECLIC_SetPriorityIRQ(IRQn, priority); + if (handler != NULL) { + /* set interrupt handler entry to vector table */ + ECLIC_SetVector(IRQn, (rv_csr_t)handler); + } + /* enable interrupt */ + ECLIC_EnableIRQ(IRQn); + return 0; +} +#endif diff --git a/examples/gd32-vw55x-blinky/src/init.c b/examples/gd32-vw55x-blinky/src/init.c new file mode 100644 index 0000000..6acc8e1 --- /dev/null +++ b/examples/gd32-vw55x-blinky/src/init.c @@ -0,0 +1,95 @@ +/* + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * Copyright (c) 2024, GigaDevice Semiconductor Inc. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* This file refers the RISC-V standard, some adjustments are made according to GigaDevice chips */ + +#include "gd32vw55x.h" + +extern void nmi_handler(unsigned long mcause, unsigned long sp); +extern void Exception_Init(void); +extern void Exception_Register_EXC(uint32_t EXCn, unsigned long exc_handler); + +/** + * \brief early init function before main + * \details + * This function is executed right before main function. + * For RISC-V gnu toolchain, _init function might not be called + * by __libc_init_array function, so we defined a new function + * to do initialization + */ +void _premain_init(void) +{ + /* TODO: Add your own initialization code here, called before main */ + /* __ICACHE_PRESENT and __DCACHE_PRESENT are defined in demosoc.h */ + EnableICache(); + + /* Initialize exception default handlers */ + Exception_Init(); + /* Initialize NMI handlers */ + Exception_Register_EXC(NMI_EXCn, (unsigned long)nmi_handler); + /* ECLIC initialization, mainly MTH and NLBIT */ + eclic_level_threshold_set(0); + eclic_priority_group_set(ECLIC_PRIGROUP_LEVEL2_PRIO2); + eclic_global_interrupt_enable(); + + /* Before enter into main, disable mcycle and minstret counter by default to save power */ + __disable_all_counter(); +} + +/** + * \brief finish function after main + * \param [in] status status code return from main + * \details + * This function is executed right after main function. + * For RISC-V gnu toolchain, _fini function might not be called + * by __libc_fini_array function, so we defined a new function + * to do initialization + */ +void _postmain_fini(int status) +{ + /* TODO: Add your own finishing code here, called after main */ +} + +/** + * \brief _init function called in __libc_init_array() + * \details + * This `__libc_init_array()` function is called during startup code, + * user need to implement this function, otherwise when link it will + * error init.c:(.text.__libc_init_array+0x26): undefined reference to `_init' + * \note + * Please use \ref _premain_init function now + */ +void _init(void) +{ + /* Don't put any code here, please use _premain_init now */ +} + +/** + * \brief _fini function called in __libc_fini_array() + * \details + * This `__libc_fini_array()` function is called when exit main. + * user need to implement this function, otherwise when link it will + * error fini.c:(.text.__libc_fini_array+0x28): undefined reference to `_fini' + * \note + * Please use \ref _postmain_fini function now + */ +void _fini(void) +{ + /* Don't put any code here, please use _postmain_fini now */ +} diff --git a/examples/gd32-vw55x-blinky/src/main.c b/examples/gd32-vw55x-blinky/src/main.c new file mode 100644 index 0000000..705a885 --- /dev/null +++ b/examples/gd32-vw55x-blinky/src/main.c @@ -0,0 +1,30 @@ +#include "gd32vw55x.h" +#include "systick.h" +#include + +#define LEDPORT GPIOB +#define LEDPIN GPIO_PIN_11 +#define LED_CLOCK RCU_GPIOB + +int main(void) +{ + systick_config(); + eclic_priority_group_set(ECLIC_PRIGROUP_LEVEL3_PRIO1); + rcu_periph_clock_enable(LED_CLOCK); + gpio_mode_set(LEDPORT, GPIO_MODE_OUTPUT, GPIO_PUPD_NONE, LEDPIN); + gpio_output_options_set(LEDPORT, GPIO_OTYPE_PP, GPIO_OSPEED_2MHZ, LEDPIN); + + while (1) + { + gpio_bit_set(LEDPORT, LEDPIN); + delay_1ms(100); + gpio_bit_reset(LEDPORT, LEDPIN); + delay_1ms(100); + } +} + +void eclic_mtip_handler(void) +{ + ECLIC_ClearPendingIRQ(CLIC_INT_TMR); + delay_decrement(); +} diff --git a/examples/gd32-vw55x-blinky/src/systick.c b/examples/gd32-vw55x-blinky/src/systick.c new file mode 100644 index 0000000..c688da0 --- /dev/null +++ b/examples/gd32-vw55x-blinky/src/systick.c @@ -0,0 +1,78 @@ +/*! + \file systick.c + \brief the systick configuration file + + \version 2024-01-16, V1.2.0, firmware for GD32VW55x +*/ + +/* + Copyright (c) 2024, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32vw55x.h" +#include "systick.h" + +volatile static uint32_t delay; + +/*! + \brief configure systick + \param[in] none + \param[out] none + \retval none +*/ +void systick_config(void) +{ + SysTimer_SetControlValue(SysTimer_MTIMECTL_CMPCLREN_Msk); + SysTimer_SetCompareValue(SystemCoreClock / 4000); + __ECLIC_SetTrigIRQ(CLIC_INT_TMR, ECLIC_POSTIVE_EDGE_TRIGGER); + eclic_irq_enable(CLIC_INT_TMR, 0, 0); +} + +/*! + \brief delay a time in milliseconds + \param[in] count: count in milliseconds + \param[out] none + \retval none +*/ +void delay_1ms(uint32_t count) +{ + delay = count; + while(0U != delay) { + } +} + +/*! + \brief delay decrement + \param[in] none + \param[out] none + \retval none +*/ +void delay_decrement(void) +{ + if(0U != delay) { + delay--; + } +} diff --git a/examples/gd32-vw55x-blinky/src/systick.h b/examples/gd32-vw55x-blinky/src/systick.h new file mode 100644 index 0000000..576b8ba --- /dev/null +++ b/examples/gd32-vw55x-blinky/src/systick.h @@ -0,0 +1,47 @@ +/*! + \file systick.h + \brief the header file of systick + + \version 2024-01-16, V1.2.0, firmware for GD32VW55x +*/ + +/* + Copyright (c) 2024, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef SYSTICK_H +#define SYSTICK_H + +#include + +/* configure systick */ +void systick_config(void); +/* delay a time in milliseconds */ +void delay_1ms(uint32_t count); +/* delay decrement */ +void delay_decrement(void); + +#endif /* SYSTICK_H */ diff --git a/examples/gd32-vw55x-blinky/test/README b/examples/gd32-vw55x-blinky/test/README new file mode 100644 index 0000000..b94d089 --- /dev/null +++ b/examples/gd32-vw55x-blinky/test/README @@ -0,0 +1,11 @@ + +This directory is intended for PlatformIO Unit Testing and project tests. + +Unit Testing is a software testing method by which individual units of +source code, sets of one or more MCU program modules together with associated +control data, usage procedures, and operating procedures, are tested to +determine whether they are fit for use. Unit testing finds problems early +in the development cycle. + +More information about PlatformIO Unit Testing: +- https://docs.platformio.org/page/plus/unit-testing.html diff --git a/examples/gd32-vw55x-blinky/test/main.cpp b/examples/gd32-vw55x-blinky/test/main.cpp new file mode 100644 index 0000000..f7a8fb6 --- /dev/null +++ b/examples/gd32-vw55x-blinky/test/main.cpp @@ -0,0 +1,23 @@ +#include +#include + +void setUp(void) { /* set stuff up here */ } +void tearDown(void) { /* clean stuff up here */} + +int function_under_test(int a, int b) { return a + b; } + +void test_calculator_addition(void) { + TEST_ASSERT_EQUAL(32, function_under_test(25, 7)); +} + +void setup() { + // NOTE!!! Wait for >2 secs + // if board doesn't support software reset via Serial.DTR/RTS + delay(2000); + + UNITY_BEGIN(); + RUN_TEST(test_calculator_addition); + UNITY_END(); +} + +void loop() { digitalWrite(LED_BUILTIN, HIGH); delay(100); digitalWrite(LED_BUILTIN, LOW); delay(500); } \ No newline at end of file diff --git a/misc/openocd/gd32vw55x.cfg b/misc/openocd/gd32vw55x.cfg new file mode 100644 index 0000000..9319ca2 --- /dev/null +++ b/misc/openocd/gd32vw55x.cfg @@ -0,0 +1,52 @@ +# +# GigaDevice GD32VW55x target +# +# https://www.gigadevice.com/products/microcontrollers/gd32/risc-v/ +# +adapter speed 1000 +reset_config trst_only +adapter srst pulse_width 100 + +adapter driver cmsis-dap + +transport select jtag + +## bindto 0.0.0.0 can be used to cover all available interfaces. +## Uncomment bindto line to enable remote machine debug +# bindto 0.0.0.0 + +# Bind JTAG with specified serial number passed by JTAGSN +if { [ info exists JTAGSN ] } { + puts "Bind JTAG with serial number $JTAGSN" + adapter serial $JTAGSN +} + +# if NOFLASH variable exist or passed by openocd command +# will not probe flash device +set _noflash [ info exists NOFLASH ] + +set _CHIPNAME riscv +jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x10307a6d + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME riscv -chain-position $_TARGETNAME +$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size 20480 -work-area-backup 0 + +# flash size will be probed +if { $_noflash == 0 } { + set _FLASHNAME $_CHIPNAME.flash + # require gd32 distributed openocd, Nuclei OpenOCD <= 2023.10 don't support it + flash bank $_FLASHNAME gd32vw55x 0x08000000 0x400000 0 0 $_TARGETNAME +} + +# Expose Nuclei self-defined CSRS range +# See https://github.com/riscv/riscv-gnu-toolchain/issues/319#issuecomment-358397306 +# Then user can view the csr register value in gdb using: info reg csr775 for CSR MTVT(0x307) +# needed when using gd32 openocd +# riscv expose_csrs 770-800,835-850,1984-2032,2064-2070 + +riscv set_reset_timeout_sec 1 + +init + +halt \ No newline at end of file diff --git a/misc/svd/GD32VW55x.svd b/misc/svd/GD32VW55x.svd new file mode 100644 index 0000000..7bc8e73 --- /dev/null +++ b/misc/svd/GD32VW55x.svd @@ -0,0 +1,38093 @@ + + + + + GD32VF103 + 1.0 + GD32VF103 RISC-V Microcontroller based device + + + GD32VF103 + r1p0 + little + 1 + 0 + 0 + + + 8 + 32 + 32 + 0x0 + 0xFFFFFFFF + + + + ADC0 + Analog to digital converter + ADC + 0x40012400 + + 0x0 + 0x400 + registers + + + ADC0_1 + 37 + + + + STAT + STAT + status register + 0x0 + 0x20 + read-write + 0x00000000 + + + STRC + Start flag of regular channel group + 4 + 1 + + + STIC + Start flag of inserted channel group + 3 + 1 + + + EOIC + End of inserted group conversion flag + 2 + 1 + + + EOC + End of group conversion flag + 1 + 1 + + + WDE + Analog watchdog event flag + 0 + 1 + + + + + CTL0 + CTL0 + control register 0 + 0x04 + 0x20 + read-write + 0x00000000 + + + RWDEN + Regular channel analog watchdog enable + 23 + 1 + + + IWDEN + Inserted channel analog watchdog + enable + 22 + 1 + + + SYNCM + sync mode selection + 16 + 4 + + + DISNUM + Number of conversions in + discontinuous mode + 13 + 3 + + + DISIC + Discontinuous mode on + inserted channels + 12 + 1 + + + DISRC + Discontinuous mode on regular + channels + 11 + 1 + + + ICA + Inserted channel group convert + automatically + 10 + 1 + + + WDSC + When in scan mode, analog watchdog + is effective on a single channel + 9 + 1 + + + SM + Scan mode + 8 + 1 + + + EOICIE + Interrupt enable for EOIC + 7 + 1 + + + WDEIE + Interrupt enable for WDE + 6 + 1 + + + EOCIE + Interrupt enable for EOC + 5 + 1 + + + WDCHSEL + Analog watchdog channel select + 0 + 5 + + + + + CTL1 + CTL1 + control register 1 + 0x08 + 0x20 + read-write + 0x00000000 + + + TSVREN + Channel 16 and 17 enable of ADC0 + 23 + 1 + + + SWRCST + Start on regular channel + 22 + 1 + + + SWICST + Start on inserted channel + 21 + 1 + + + ETERC + External trigger enable for regular channel + 20 + 1 + + + ETSRC + External trigger select for regular channel + 17 + 3 + + + ETEIC + External trigger select for inserted channel + 15 + 1 + + + ETSIC + External trigger select for inserted channel + 12 + 3 + + + DAL + Data alignment + 11 + 1 + + + DMA + DMA request enable + 8 + 1 + + + RSTCLB + Reset calibration + 3 + 1 + + + CLB + ADC calibration + 2 + 1 + + + CTN + Continuous mode + 1 + 1 + + + ADCON + ADC on + 0 + 1 + + + + + SAMPT0 + SAMPT0 + Sample time register 0 + 0x0C + 0x20 + read-write + 0x00000000 + + + SPT10 + Channel 10 sample time + selection + 0 + 3 + + + SPT11 + Channel 11 sample time + selection + 3 + 3 + + + SPT12 + Channel 12 sample time + selection + 6 + 3 + + + SPT13 + Channel 13 sample time + selection + 9 + 3 + + + SPT14 + Channel 14 sample time + selection + 12 + 3 + + + SPT15 + Channel 15 sample time + selection + 15 + 3 + + + SPT16 + Channel 16 sample time + selection + 18 + 3 + + + SPT17 + Channel 17 sample time + selection + 21 + 3 + + + + + SAMPT1 + SAMPT1 + Sample time register 1 + 0x10 + 0x20 + read-write + 0x00000000 + + + SPT0 + Channel 0 sample time + selection + 0 + 3 + + + SPT1 + Channel 1 sample time + selection + 3 + 3 + + + SPT2 + Channel 2 sample time + selection + 6 + 3 + + + SPT3 + Channel 3 sample time + selection + 9 + 3 + + + SPT4 + Channel 4 sample time + selection + 12 + 3 + + + SPT5 + Channel 5 sample time + selection + 15 + 3 + + + SPT6 + Channel 6 sample time + selection + 18 + 3 + + + SPT7 + Channel 7 sample time + selection + 21 + 3 + + + SPT8 + Channel 8 sample time + selection + 24 + 3 + + + SPT9 + Channel 9 sample time + selection + 27 + 3 + + + + + IOFF0 + IOFF0 + Inserted channel data offset register + 0 + 0x14 + 0x20 + read-write + 0x00000000 + + + IOFF + Data offset for inserted channel + 0 + 0 + 12 + + + + + IOFF1 + IOFF1 + Inserted channel data offset register + 1 + 0x18 + 0x20 + read-write + 0x00000000 + + + IOFF + Data offset for inserted channel + 1 + 0 + 12 + + + + + IOFF2 + IOFF2 + Inserted channel data offset register + 2 + 0x1C + 0x20 + read-write + 0x00000000 + + + IOFF + Data offset for inserted channel + 2 + 0 + 12 + + + + + IOFF3 + IOFF3 + Inserted channel data offset register + 3 + 0x20 + 0x20 + read-write + 0x00000000 + + + IOFF + Data offset for inserted channel + 3 + 0 + 12 + + + + + WDHT + WDHT + watchdog higher threshold + register + 0x24 + 0x20 + read-write + 0x00000FFF + + + WDHT + Analog watchdog higher + threshold + 0 + 12 + + + + + WDLT + WDLT + watchdog lower threshold + register + 0x28 + 0x20 + read-write + 0x00000000 + + + WDLT + Analog watchdog lower + threshold + 0 + 12 + + + + + RSQ0 + RSQ0 + regular sequence register 0 + 0x2C + 0x20 + read-write + 0x00000000 + + + RL + Regular channel group + length + 20 + 4 + + + RSQ15 + 16th conversion in regular + sequence + 15 + 5 + + + RSQ14 + 15th conversion in regular + sequence + 10 + 5 + + + RSQ13 + 14th conversion in regular + sequence + 5 + 5 + + + RSQ12 + 13th conversion in regular + sequence + 0 + 5 + + + + + RSQ1 + RSQ1 + regular sequence register 1 + 0x30 + 0x20 + read-write + 0x00000000 + + + RSQ11 + 12th conversion in regular + sequence + 25 + 5 + + + RSQ10 + 11th conversion in regular + sequence + 20 + 5 + + + RSQ9 + 10th conversion in regular + sequence + 15 + 5 + + + RSQ8 + 9th conversion in regular + sequence + 10 + 5 + + + RSQ7 + 8th conversion in regular + sequence + 5 + 5 + + + RSQ6 + 7th conversion in regular + sequence + 0 + 5 + + + + + RSQ2 + RSQ2 + regular sequence register 2 + 0x34 + 0x20 + read-write + 0x00000000 + + + RSQ5 + 6th conversion in regular + sequence + 25 + 5 + + + RSQ4 + 5th conversion in regular + sequence + 20 + 5 + + + RSQ3 + 4th conversion in regular + sequence + 15 + 5 + + + RSQ2 + 3rd conversion in regular + sequence + 10 + 5 + + + RSQ1 + 2nd conversion in regular + sequence + 5 + 5 + + + RSQ0 + 1st conversion in regular + sequence + 0 + 5 + + + + + ISQ + ISQ + Inserted sequence register + 0x38 + 0x20 + read-write + 0x00000000 + + + IL + Inserted channel group length + 20 + 2 + + + ISQ3 + 4th conversion in inserted + sequence + 15 + 5 + + + ISQ2 + 3rd conversion in inserted + sequence + 10 + 5 + + + ISQ1 + 2nd conversion in inserted + sequence + 5 + 5 + + + ISQ0 + 1st conversion in inserted + sequence + 0 + 5 + + + + + IDATA0 + IDATA0 + Inserted data register 0 + 0x3C + 0x20 + read-only + 0x00000000 + + + IDATAn + Inserted number n conversion data + 0 + 16 + + + + + IDATA1 + IDATA1 + Inserted data register 1 + 0x40 + 0x20 + read-only + 0x00000000 + + + IDATAn + Inserted number n conversion data + 0 + 16 + + + + + IDATA2 + IDATA2 + Inserted data register 2 + 0x44 + 0x20 + read-only + 0x00000000 + + + IDATAn + Inserted number n conversion data + 0 + 16 + + + + + IDATA3 + IDATA3 + Inserted data register 3 + 0x48 + 0x20 + read-only + 0x00000000 + + + IDATAn + Inserted number n conversion data + 0 + 16 + + + + + RDATA + RDATA + regular data register + 0x4C + 0x20 + read-only + 0x00000000 + + + ADC1RDTR + ADC regular channel data + 16 + 16 + + + RDATA + Regular channel data + 0 + 16 + + + + + OVSAMPCTL + OVSAMPCTL + Oversample control register + 0x80 + 0x20 + read-write + 0x00000000 + + + DRES + ADC resolution + 12 + 2 + + + TOVS + Triggered Oversampling + 9 + 1 + + + OVSS + Oversampling shift + 5 + 4 + + + OVSR + Oversampling ratio + 2 + 3 + + + OVSEN + Oversampler Enable + 0 + 1 + + + + + + + ADC1 + Analog to digital converter + ADC + 0x40012800 + + 0x0 + 0x400 + registers + + + ADC0_1 + 37 + + + + STAT + STAT + status register + 0x0 + 0x20 + read-write + 0x00000000 + + + STRC + Start flag of regular channel group + 4 + 1 + + + STIC + Start flag of inserted channel group + 3 + 1 + + + EOIC + End of inserted group conversion flag + 2 + 1 + + + EOC + End of group conversion flag + 1 + 1 + + + WDE + Analog watchdog event flag + 0 + 1 + + + + + CTL0 + CTL0 + control register 0 + 0x4 + 0x20 + read-write + 0x00000000 + + + RWDEN + Regular channel analog watchdog + enable + 23 + 1 + + + IWDEN + Inserted channel analog watchdog + enable + 22 + 1 + + + DISNUM + Number of conversions in + discontinuous mode + 13 + 3 + + + DISIC + Discontinuous mode on + inserted channels + 12 + 1 + + + DISRC + Discontinuous mode on regular + channels + 11 + 1 + + + ICA + Inserted channel group convert + automatically + 10 + 1 + + + WDSC + When in scan mode, analog watchdog + is effective on a single channel + 9 + 1 + + + SM + Scan mode + 8 + 1 + + + EOICIE + Interrupt enable for EOIC + 7 + 1 + + + WDEIE + Interrupt enable for WDE + 6 + 1 + + + EOCIE + Interrupt enable for EOC + 5 + 1 + + + WDCHSEL + Analog watchdog channel select + 0 + 5 + + + + + CTL1 + CTL1 + control register 1 + 0x08 + 0x20 + read-write + 0x00000000 + + + SWRCST + Start on regular channel + 22 + 1 + + + SWICST + Start on inserted channel + 21 + 1 + + + ETERC + External trigger enable for regular channel + 20 + 1 + + + ETSRC + External trigger select for regular channel + 17 + 3 + + + ETEIC + External trigger enable for inserted channel + 15 + 1 + + + ETSIC + External trigger select for inserted channel + 12 + 3 + + + DAL + Data alignment + 11 + 1 + + + DMA + DMA request enable + 8 + 1 + + + RSTCLB + Reset calibration + 3 + 1 + + + CLB + ADC calibration + 2 + 1 + + + CTN + Continuous mode + 1 + 1 + + + ADCON + ADC on + 0 + 1 + + + + + SAMPT0 + SAMPT0 + Sample time register 0 + 0x0C + 0x20 + read-write + 0x00000000 + + + SPT10 + Channel 10 sample time + selection + 0 + 3 + + + SPT11 + Channel 11 sample time + selection + 3 + 3 + + + SPT12 + Channel 12 sample time + selection + 6 + 3 + + + SPT13 + Channel 13 sample time + selection + 9 + 3 + + + SPT14 + Channel 14 sample time + selection + 12 + 3 + + + SPT15 + Channel 15 sample time + selection + 15 + 3 + + + SPT16 + Channel 16 sample time + selection + 18 + 3 + + + SPT17 + Channel 17 sample time + selection + 21 + 3 + + + + + SAMPT1 + SAMPT1 + Sample time register 1 + 0x10 + 0x20 + read-write + 0x00000000 + + + SPT0 + Channel 0 sample time + selection + 0 + 3 + + + SPT1 + Channel 1 sample time + selection + 3 + 3 + + + SPT2 + Channel 2 sample time + selection + 6 + 3 + + + SPT3 + Channel 3 sample time + selection + 9 + 3 + + + SPT4 + Channel 4 sample time + selection + 12 + 3 + + + SPT5 + Channel 5 sample time + selection + 15 + 3 + + + SPT6 + Channel 6 sample time + selection + 18 + 3 + + + SPT7 + Channel 7 sample time + selection + 21 + 3 + + + SPT8 + Channel 8 sample time + selection + 24 + 3 + + + SPT9 + Channel 9 sample time + selection + 27 + 3 + + + + + IOFF0 + IOFF0 + Inserted channel data offset register + 0 + 0x14 + 0x20 + read-write + 0x00000000 + + + IOFF + Data offset for inserted channel + 0 + 0 + 12 + + + + + IOFF1 + IOFF1 + Inserted channel data offset register + 1 + 0x18 + 0x20 + read-write + 0x00000000 + + + IOFF + Data offset for inserted channel + 1 + 0 + 12 + + + + + IOFF2 + IOFF2 + Inserted channel data offset register + 2 + 0x1C + 0x20 + read-write + 0x00000000 + + + IOFF + Data offset for inserted channel + 2 + 0 + 12 + + + + + IOFF3 + IOFF3 + Inserted channel data offset register + 3 + 0x20 + 0x20 + read-write + 0x00000000 + + + IOFF + Data offset for inserted channel + 3 + 0 + 12 + + + + + WDHT + WDHT + watchdog higher threshold + register + 0x24 + 0x20 + read-write + 0x00000FFF + + + WDHT + Analog watchdog higher + threshold + 0 + 12 + + + + + WDLT + WDLT + watchdog lower threshold + register + 0x28 + 0x20 + read-write + 0x00000000 + + + WDLT + Analog watchdog lower + threshold + 0 + 12 + + + + + RSQ0 + RSQ0 + regular sequence register 0 + 0x2C + 0x20 + read-write + 0x00000000 + + + RL + Regular channel group + length + 20 + 4 + + + RSQ15 + 16th conversion in regular + sequence + 15 + 5 + + + RSQ14 + 15th conversion in regular + sequence + 10 + 5 + + + RSQ13 + 14th conversion in regular + sequence + 5 + 5 + + + RSQ12 + 13th conversion in regular + sequence + 0 + 5 + + + + + RSQ1 + RSQ1 + regular sequence register 1 + 0x30 + 0x20 + read-write + 0x00000000 + + + RSQ11 + 12th conversion in regular + sequence + 25 + 5 + + + RSQ10 + 11th conversion in regular + sequence + 20 + 5 + + + RSQ9 + 10th conversion in regular + sequence + 15 + 5 + + + RSQ8 + 9th conversion in regular + sequence + 10 + 5 + + + RSQ7 + 8th conversion in regular + sequence + 5 + 5 + + + RSQ6 + 7th conversion in regular + sequence + 0 + 5 + + + + + RSQ2 + RSQ2 + regular sequence register 2 + 0x34 + 0x20 + read-write + 0x00000000 + + + RSQ5 + 6th conversion in regular + sequence + 25 + 5 + + + RSQ4 + 5th conversion in regular + sequence + 20 + 5 + + + RSQ3 + 4th conversion in regular + sequence + 15 + 5 + + + RSQ2 + 3rd conversion in regular + sequence + 10 + 5 + + + RSQ1 + 2nd conversion in regular + sequence + 5 + 5 + + + RSQ0 + 1st conversion in regular + sequence + 0 + 5 + + + + + ISQ + ISQ + Inserted sequence register + 0x38 + 0x20 + read-write + 0x00000000 + + + IL + Inserted channel group length + 20 + 2 + + + ISQ3 + 4th conversion in inserted + sequence + 15 + 5 + + + ISQ2 + 3rd conversion in inserted + sequence + 10 + 5 + + + ISQ1 + 2nd conversion in inserted + sequence + 5 + 5 + + + ISQ0 + 1st conversion in inserted + sequence + 0 + 5 + + + + + IDATA0 + IDATA0 + Inserted data register 0 + 0x3C + 0x20 + read-only + 0x00000000 + + + IDATAn + Inserted number n conversion data + 0 + 16 + + + + + IDATA1 + IDATA1 + Inserted data register 1 + 0x40 + 0x20 + read-only + 0x00000000 + + + IDATAn + Inserted number n conversion data + 0 + 16 + + + + + IDATA2 + IDATA2 + Inserted data register 2 + 0x44 + 0x20 + read-only + 0x00000000 + + + IDATAn + Inserted number n conversion data + 0 + 16 + + + + + IDATA3 + IDATA3 + Inserted data register 3 + 0x48 + 0x20 + read-only + 0x00000000 + + + IDATAn + Inserted number n conversion data + 0 + 16 + + + + + RDATA + RDATA + regular data register + 0x4C + 0x20 + read-only + 0x00000000 + + + RDATA + Regular channel data + 0 + 16 + + + + + + + AFIO + Alternate-function I/Os + AFIO + 0x40010000 + + 0x0 + 0x400 + registers + + + + EC + EC + Event control register + 0x0 + 0x20 + read-write + 0x00000000 + + + EOE + Event output enable + 7 + 1 + + + PORT + Event output port selection + 4 + 3 + + + PIN + Event output pin selection + 0 + 4 + + + + + PCF0 + PCF0 + AFIO port configuration register 0 + 0x04 + 0x20 + read-write + 0x00000000 + + + TIMER1ITI1_REMAP + TIMER1 internal trigger 1 remapping + 29 + 1 + + + SPI2_REMAP + SPI2/I2S2 remapping + 28 + 1 + + + SWJ_CFG + Serial wire JTAG configuration + 24 + 3 + + + CAN1_REMAP + CAN1 I/O remapping + 22 + 1 + + + TIMER4CH3_IREMAP + TIMER4 channel3 internal remapping + 16 + 1 + + + PD01_REMAP + Port D0/Port D1 mapping on OSC_IN/OSC_OUT + 15 + 1 + + + CAN0_REMAP + CAN0 alternate interface remapping + 13 + 2 + + + TIMER3_REMAP + TIMER3 remapping + 12 + 1 + + + TIMER2_REMAP + TIMER2 remapping + 10 + 2 + + + TIMER1_REMAP + TIMER1 remapping + 8 + 2 + + + TIMER0_REMAP + TIMER0 remapping + 6 + 2 + + + USART2_REMAP + USART2 remapping + 4 + 2 + + + USART1_REMAP + USART1 remapping + 3 + 1 + + + USART0_REMAP + USART0 remapping + 2 + 1 + + + I2C0_REMAP + I2C0 remapping + 1 + 1 + + + SPI0_REMAP + SPI0 remapping + 0 + 1 + + + + + EXTISS0 + EXTISS0 + EXTI sources selection register 0 + 0x08 + 0x20 + read-write + 0x00000000 + + + EXTI3_SS + EXTI 3 sources selection + 12 + 4 + + + EXTI2_SS + EXTI 2 sources selection + 8 + 4 + + + EXTI1_SS + EXTI 1 sources selection + 4 + 4 + + + EXTI0_SS + EXTI 0 sources selection + 0 + 4 + + + + + EXTISS1 + EXTISS1 + EXTI sources selection register 1 + 0x0C + 0x20 + read-write + 0x00000000 + + + EXTI7_SS + EXTI 7 sources selection + 12 + 4 + + + EXTI6_SS + EXTI 6 sources selection + 8 + 4 + + + EXTI5_SS + EXTI 5 sources selection + 4 + 4 + + + EXTI4_SS + EXTI 4 sources selection + 0 + 4 + + + + + EXTISS2 + EXTISS2 + EXTI sources selection register 2 + 0x10 + 0x20 + read-write + 0x00000000 + + + EXTI11_SS + EXTI 11 sources selection + 12 + 4 + + + EXTI10_SS + EXTI 10 sources selection + 8 + 4 + + + EXTI9_SS + EXTI 9 sources selection + 4 + 4 + + + EXTI8_SS + EXTI 8 sources selection + 0 + 4 + + + + + EXTISS3 + EXTISS3 + EXTI sources selection register 3 + 0x14 + 0x20 + read-write + 0x00000000 + + + EXTI15_SS + EXTI 15 sources selection + 12 + 4 + + + EXTI14_SS + EXTI 14 sources selection + 8 + 4 + + + EXTI13_SS + EXTI 13 sources selection + 4 + 4 + + + EXTI12_SS + EXTI 12 sources selection + 0 + 4 + + + + + PCF1 + PCF1 + AFIO port configuration register 1 + 0x1C + 0x20 + read-write + 0x00000000 + + + EXMC_NADV + EXMC_NADV connect/disconnect + 10 + 1 + + + + + + + BKP + Backup registers + BKP + 0x40006C00 + + 0x0 + 0x400 + registers + + + Tamper + 21 + + + + DATA0 + DATA0 + Backup data register 0 + 0x4 + 0x10 + read-write + 0x0000 + + + DATA + Backup data + 0 + 16 + + + + + DATA1 + DATA1 + Backup data register 1 + 0x8 + 0x10 + read-write + 0x0000 + + + DATA + Backup data + 0 + 16 + + + + + DATA2 + DATA2 + Backup data register 2 + 0xC + 0x10 + read-write + 0x0000 + + + DATA + Backup data + 0 + 16 + + + + + DATA3 + DATA3 + Backup data register 3 + 0x10 + 0x10 + read-write + 0x0000 + + + DATA + Backup data + 0 + 16 + + + + + DATA4 + DATA4 + Backup data register 4 + 0x14 + 0x10 + read-write + 0x0000 + + + DATA + Backup data + 0 + 16 + + + + + DATA5 + DATA5 + Backup data register 5 + 0x18 + 0x10 + read-write + 0x0000 + + + DATA + Backup data + 0 + 16 + + + + + DATA6 + DATA6 + Backup data register 6 + 0x1C + 0x10 + read-write + 0x0000 + + + DATA + Backup data + 0 + 16 + + + + + DATA7 + DATA7 + Backup data register 7 + 0x20 + 0x10 + read-write + 0x0000 + + + DATA + Backup data + 0 + 16 + + + + + DATA8 + DATA8 + Backup data register 8 + 0x24 + 0x10 + read-write + 0x0000 + + + DATA + Backup data + 0 + 16 + + + + + DATA9 + DATA9 + Backup data register 9 + 0x28 + 0x10 + read-write + 0x0000 + + + DATA + Backup data + 0 + 16 + + + + + DATA10 + DATA10 + Backup data register 10 + 0x40 + 0x10 + read-write + 0x0000 + + + DATA + Backup data + 0 + 16 + + + + + DATA11 + DATA11 + Backup data register 11 + 0x44 + 0x10 + read-write + 0x0000 + + + DATA + Backup data + 0 + 16 + + + + + DATA12 + DATA12 + Backup data register 12 + 0x48 + 0x10 + read-write + 0x0000 + + + DATA + Backup data + 0 + 16 + + + + + DATA13 + DATA13 + Backup data register 13 + 0x4C + 0x10 + read-write + 0x0000 + + + DATA + Backup data + 0 + 16 + + + + + DATA14 + DATA14 + Backup data register 14 + 0x50 + 0x10 + read-write + 0x0000 + + + DATA + Backup data + 0 + 16 + + + + + DATA15 + DATA15 + Backup data register 15 + 0x54 + 0x10 + read-write + 0x0000 + + + DATA + Backup data + 0 + 16 + + + + + DATA16 + DATA16 + Backup data register 16 + 0x58 + 0x10 + read-write + 0x0000 + + + DATA + Backup data + 0 + 16 + + + + + DATA17 + DATA17 + Backup data register 17 + 0x5C + 0x10 + read-write + 0x0000 + + + DATA + Backup data + 0 + 16 + + + + + DATA18 + DATA18 + Backup data register 18 + 0x60 + 0x10 + read-write + 0x0000 + + + DATA + Backup data + 0 + 16 + + + + + DATA19 + DATA19 + Backup data register 19 + 0x64 + 0x10 + read-write + 0x0000 + + + DATA + Backup data + 0 + 16 + + + + + DATA20 + DATA20 + Backup data register 20 + 0x68 + 0x10 + read-write + 0x0000 + + + DATA + Backup data + 0 + 16 + + + + + DATA21 + DATA21 + Backup data register 21 + 0x6C + 0x10 + read-write + 0x0000 + + + DATA + Backup data + 0 + 16 + + + + + DATA22 + DATA22 + Backup data register 22 + 0x70 + 0x10 + read-write + 0x0000 + + + DATA + Backup data + 0 + 16 + + + + + DATA23 + DATA23 + Backup data register 23 + 0x74 + 0x10 + read-write + 0x0000 + + + DATA + Backup data + 0 + 16 + + + + + DATA24 + DATA24 + Backup data register 24 + 0x78 + 0x10 + read-write + 0x0000 + + + DATA + Backup data + 0 + 16 + + + + + DATA25 + DATA25 + Backup data register 25 + 0x7C + 0x10 + read-write + 0x0000 + + + DATA + Backup data + 0 + 16 + + + + + DATA26 + DATA26 + Backup data register 26 + 0x80 + 0x10 + read-write + 0x0000 + + + DATA + Backup data + 0 + 16 + + + + + DATA27 + DATA27 + Backup data register 27 + 0x84 + 0x10 + read-write + 0x0000 + + + DATA + Backup data + 0 + 16 + + + + + DATA28 + DATA28 + Backup data register 28 + 0x88 + 0x10 + read-write + 0x0000 + + + DATA + Backup data + 0 + 16 + + + + + DATA29 + DATA29 + Backup data register 29 + 0x8C + 0x10 + read-write + 0x0000 + + + DATA + Backup data + 0 + 16 + + + + + DATA30 + DATA30 + Backup data register 30 + 0x90 + 0x10 + read-write + 0x0000 + + + DATA + Backup data + 0 + 16 + + + + + DATA31 + DATA31 + Backup data register 31 + 0x94 + 0x10 + read-write + 0x0000 + + + DATA + Backup data + 0 + 16 + + + + + DATA32 + DATA32 + Backup data register 32 + 0x98 + 0x10 + read-write + 0x0000 + + + DATA + Backup data + 0 + 16 + + + + + DATA33 + DATA33 + Backup data register 33 + 0x9C + 0x10 + read-write + 0x0000 + + + DATA + Backup data + 0 + 16 + + + + + DATA34 + DATA34 + Backup data register 34 + 0xA0 + 0x10 + read-write + 0x0000 + + + DATA + Backup data + 0 + 16 + + + + + DATA35 + DATA35 + Backup data register 35 + 0xA4 + 0x10 + read-write + 0x0000 + + + DATA + Backup data + 0 + 16 + + + + + DATA36 + DATA36 + Backup data register 36 + 0xA8 + 0x10 + read-write + 0x0000 + + + DATA + Backup data + 0 + 16 + + + + + DATA37 + DATA37 + Backup data register 37 + 0xAC + 0x10 + read-write + 0x0000 + + + DATA + Backup data + 0 + 16 + + + + + DATA38 + DATA38 + Backup data register 38 + 0xB0 + 0x10 + read-write + 0x0000 + + + DATA + Backup data + 0 + 16 + + + + + DATA39 + DATA39 + Backup data register 39 + 0xB4 + 0x10 + read-write + 0x0000 + + + DATA + Backup data + 0 + 16 + + + + + DATA40 + DATA40 + Backup data register 40 + 0xB8 + 0x10 + read-write + 0x0000 + + + DATA + Backup data + 0 + 16 + + + + + DATA41 + DATA41 + Backup data register 41 + 0xBC + 0x10 + read-write + 0x0000 + + + DATA + Backup data + 0 + 16 + + + + + OCTL + OCTL + RTC signal output control register + 0x2C + 0x10 + read-write + 0x0000 + + + ROSEL + RTC output selection + 9 + 1 + + + ASOEN + RTC alarm or second signal output enable + 8 + 1 + + + COEN + RTC clock calibration output enable + 7 + 1 + + + RCCV + RTC clock calibration value + 0 + 7 + + + + + TPCTL + TPCTL + Tamper pin control register + 0x30 + 0x10 + read-write + 0x0000 + + + TPAL + TAMPER pin active level + 1 + 1 + + + TPEN + TAMPER detection enable + 0 + 1 + + + + + TPCS + TPCS + Tamper control and status register + 0x34 + 0x10 + read-write + 0x0000 + + + TIF + Tamper interrupt flag + 9 + 1 + + + TEF + Tamper event flag + 8 + 1 + + + TPIE + Tamper interrupt enable + 2 + 1 + + + TIR + Tamper interrupt reset + 1 + 1 + + + TER + Tamper event reset + 0 + 1 + + + + + + + CAN0 + Controller area network + CAN + 0x40006400 + + 0x0 + 0x400 + registers + + + CAN0_TX + 38 + + + CAN0_RX0 + 39 + + + CAN0_RX1 + 40 + + + CAN0_EWMC + 41 + + + + CTL + CTL + Control register + 0x0 + 0x20 + read-write + 0x00010002 + + + DFZ + Debug freeze + 16 + 1 + + + SWRST + Software reset + 15 + 1 + + + TTC + Time-triggered communication + 7 + 1 + + + ABOR + Automatic bus-off recovery + 6 + 1 + + + AWU + Automatic wakeup + 5 + 1 + + + ARD + Automatic retransmission disable + 4 + 1 + + + RFOD + Receive FIFO overwrite disable + 3 + 1 + + + TFO + Transmit FIFO order + 2 + 1 + + + SLPWMOD + Sleep working mode + 1 + 1 + + + IWMOD + Initial working mode + 0 + 1 + + + + + STAT + STAT + Status register + 0x04 + 0x20 + 0x00000C02 + + + RXL + RX level + 11 + 1 + read-only + + + LASTRX + Last sample value of RX pin + 10 + 1 + read-only + + + RS + Receiving state + 9 + 1 + read-only + + + TS + Transmitting state + 8 + 1 + read-only + + + SLPIF + Status change interrupt flag of sleep + working mode entering + 4 + 1 + read-write + + + WUIF + Status change interrupt flag of wakeup + from sleep working mode + 3 + 1 + read-write + + + ERRIF + Error interrupt flag + 2 + 1 + read-write + + + SLPWS + Sleep working state + 1 + 1 + read-only + + + IWS + Initial working state + 0 + 1 + read-only + + + + + TSTAT + TSTAT + Transmit status register + 0x8 + 0x20 + 0x1C000000 + + + TMLS2 + Transmit mailbox 2 last sending + in transmit FIFO + 31 + 1 + read-only + + + TMLS1 + Transmit mailbox 1 last sending + in transmit FIFO + 30 + 1 + read-only + + + TMLS0 + Transmit mailbox 0 last sending + in transmit FIFO + 29 + 1 + read-only + + + TME2 + Transmit mailbox 2 empty + 28 + 1 + read-only + + + TME1 + Transmit mailbox 1 empty + 27 + 1 + read-only + + + TME0 + Transmit mailbox 0 empty + 26 + 1 + read-only + + + NUM + number of the transmit FIFO mailbox in + which the frame will be transmitted if at least one mailbox is empty + 24 + 2 + read-only + + + MST2 + Mailbox 2 stop transmitting + 23 + 1 + read-write + + + MTE2 + Mailbox 2 transmit error + 19 + 1 + read-write + + + MAL2 + Mailbox 2 arbitration lost + 18 + 1 + read-write + + + MTFNERR2 + Mailbox 2 transmit finished and no error + 17 + 1 + read-write + + + MTF2 + Mailbox 2 transmit finished + 16 + 1 + read-write + + + MST1 + Mailbox 1 stop transmitting + 15 + 1 + read-write + + + MTE1 + Mailbox 1 transmit error + 11 + 1 + read-write + + + MAL1 + Mailbox 1 arbitration lost + 10 + 1 + read-write + + + MTFNERR1 + Mailbox 1 transmit finished and no error + 9 + 1 + read-write + + + MTF1 + Mailbox 1 transmit finished + 8 + 1 + read-write + + + MST0 + Mailbox 0 stop transmitting + 7 + 1 + read-write + + + MTE0 + Mailbox 0 transmit error + 3 + 1 + read-write + + + MAL0 + Mailbox 0 arbitration lost + 2 + 1 + read-write + + + MTFNERR0 + Mailbox 0 transmit finished and no error + 1 + 1 + read-write + + + MTF0 + Mailbox 0 transmit finished + 0 + 1 + read-write + + + + + RFIFO0 + RFIFO0 + Receive message FIFO0 register + 0x0C + 0x20 + 0x00000000 + + + RFD0 + Receive FIFO0 dequeue + 5 + 1 + read-write + + + RFO0 + Receive FIFO0 overfull + 4 + 1 + read-write + + + RFF0 + Receive FIFO0 full + 3 + 1 + read-write + + + RFL0 + Receive FIFO0 length + 0 + 2 + read-only + + + + + RFIFO1 + RFIFO1 + Receive message FIFO1 register + 0x10 + 0x20 + 0x00000000 + + + RFD1 + Receive FIFO1 dequeue + 5 + 1 + read-write + + + RFO1 + Receive FIFO1 overfull + 4 + 1 + read-write + + + RFF1 + Receive FIFO1 full + 3 + 1 + read-write + + + RFL1 + Receive FIFO1 length + 0 + 2 + read-only + + + + + INTEN + INTEN + Interrupt enable register + 0x14 + 0x20 + read-write + 0x00000000 + + + SLPWIE + Sleep working interrupt enable + 17 + 1 + + + WIE + Wakeup interrupt enable + 16 + 1 + + + ERRIE + Error interrupt enable + 15 + 1 + + + ERRNIE + Error number interrupt enable + 11 + 1 + + + BOIE + Bus-off interrupt enable + 10 + 1 + + + PERRIE + Passive error interrupt enable + 9 + 1 + + + WERRIE + Warning error interrupt enable + 8 + 1 + + + RFOIE1 + Receive FIFO1 overfull interrupt enable + 6 + 1 + + + RFFIE1 + Receive FIFO1 full interrupt enable + 5 + 1 + + + RFNEIE1 + Receive FIFO1 not empty interrupt enable + 4 + 1 + + + RFOIE0 + Receive FIFO0 overfull interrupt enable + 3 + 1 + + + RFFIE0 + Receive FIFO0 full interrupt enable + 2 + 1 + + + RFNEIE0 + Receive FIFO0 not empty interrupt enable + 1 + 1 + + + TMEIE + Transmit mailbox empty interrupt enable + 0 + 1 + + + + + ERR + ERR + Error register + 0x18 + 0x20 + 0x00000000 + + + RECNT + Receive Error Count defined + by the CAN standard + 24 + 8 + read-only + + + TECNT + Transmit Error Count defined + by the CAN standard + 16 + 8 + read-only + + + ERRN + Error number + 4 + 3 + read-write + + + BOERR + Bus-off error + 2 + 1 + read-only + + + PERR + Passive error + 1 + 1 + read-only + + + WERR + Warning error + 0 + 1 + read-only + + + + + BT + BT + Bit timing register + 0x1C + 0x20 + read-write + 0x01230000 + + + SCMOD + Silent communication mode + 31 + 1 + + + LCMOD + Loopback communication mode + 30 + 1 + + + SJW + Resynchronization jump width + 24 + 2 + + + BS2 + Bit segment 2 + 20 + 3 + + + BS1 + Bit segment 1 + 16 + 4 + + + BAUDPSC + Baud rate prescaler + 0 + 10 + + + + + TMI0 + TMI0 + Transmit mailbox identifier register 0 + 0x180 + 0x20 + read-write + 0x00000000 + + + SFID_EFID + The frame identifier + 21 + 11 + + + EFID + The frame identifier + 3 + 18 + + + FF + Frame format + 2 + 1 + + + FT + Frame type + 1 + 1 + + + TEN + Transmit enable + 0 + 1 + + + + + TMP0 + TMP0 + Transmit mailbox property register 0 + 0x184 + 0x20 + read-write + 0x00000000 + + + TS + Time stamp + 16 + 16 + + + TSEN + Time stamp enable + 8 + 1 + + + DLENC + Data length code + 0 + 4 + + + + + TMDATA00 + TMDATA00 + Transmit mailbox data0 register + 0x188 + 0x20 + read-write + 0x00000000 + + + DB3 + Data byte 3 + 24 + 8 + + + DB2 + Data byte 2 + 16 + 8 + + + DB1 + Data byte 1 + 8 + 8 + + + DB0 + Data byte 0 + 0 + 8 + + + + + TMDATA10 + TMDATA10 + Transmit mailbox data1 register + 0x18C + 0x20 + read-write + 0x00000000 + + + DB7 + Data byte 7 + 24 + 8 + + + DB6 + Data byte 6 + 16 + 8 + + + DB5 + Data byte 5 + 8 + 8 + + + DB4 + Data byte 4 + 0 + 8 + + + + + TMI1 + TMI1 + Transmit mailbox identifier register 1 + 0x190 + 0x20 + read-write + 0x00000000 + + + SFID_EFID + The frame identifier + 21 + 11 + + + EFID + The frame identifier + 3 + 18 + + + FF + Frame format + 2 + 1 + + + FT + Frame type + 1 + 1 + + + TEN + Transmit enable + 0 + 1 + + + + + TMP1 + TMP1 + Transmit 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DMA0 + DMA controller + DMA + 0x40020000 + + 0x0 + 0x400 + registers + + + DMA0_Channel0 + 30 + + + DMA0_Channel1 + 31 + + + DMA0_Channel2 + 32 + + + DMA0_Channel3 + 33 + + + DMA0_Channel4 + 34 + + + DMA0_Channel5 + 35 + + + DMA0_Channel6 + 36 + + + + INTF + INTF + Interrupt flag register + 0x0 + 0x20 + read-only + 0x00000000 + + + GIF0 + Global interrupt flag of channel 0 + 0 + 1 + + + FTFIF0 + Full Transfer finish flag of channe 0 + 1 + 1 + + + HTFIF0 + Half transfer finish flag of channel 0 + 2 + 1 + + + ERRIF0 + Error flag of channel 0 + 3 + 1 + + + GIF1 + Global interrupt flag of channel 1 + 4 + 1 + + + FTFIF1 + Full Transfer finish flag of channe 1 + 5 + 1 + + + HTFIF1 + Half transfer finish flag of channel 1 + 6 + 1 + + + ERRIF1 + Error flag of channel 1 + 7 + 1 + + + GIF2 + Global interrupt flag of channel 2 + 8 + 1 + + + FTFIF2 + Full Transfer finish flag of channe 2 + 9 + 1 + + + HTFIF2 + Half transfer finish flag of channel 2 + 10 + 1 + + + ERRIF2 + Error flag of channel 2 + 11 + 1 + + + GIF3 + Global interrupt flag of channel 3 + 12 + 1 + + + FTFIF3 + Full Transfer finish flag of channe 3 + 13 + 1 + + + HTFIF3 + Half transfer finish flag of channel 3 + 14 + 1 + + + ERRIF3 + Error flag of channel 3 + 15 + 1 + + + GIF4 + Global interrupt flag of channel 4 + 16 + 1 + + + FTFIF4 + Full Transfer finish flag of channe 4 + 17 + 1 + + + HTFIF4 + Half transfer finish flag of channel 4 + 18 + 1 + + + ERRIF4 + Error flag of channel 4 + 19 + 1 + + + GIF5 + Global interrupt flag of channel 5 + 20 + 1 + + + FTFIF5 + Full Transfer finish flag of channe 5 + 21 + 1 + + + HTFIF5 + Half transfer finish flag of channel 5 + 22 + 1 + + + ERRIF5 + Error flag of channel 5 + 23 + 1 + + + GIF6 + Global interrupt flag of channel 6 + 24 + 1 + + + FTFIF6 + Full Transfer finish flag of channe 6 + 25 + 1 + + + HTFIF6 + Half transfer finish flag of channel 6 + 26 + 1 + + + ERRIF6 + Error flag of channel 6 + 27 + 1 + + + + + INTC + INTC + Interrupt flag clear register + 0x04 + 0x20 + write-only + 0x00000000 + + + GIFC0 + Clear global interrupt flag of channel 0 + 0 + 1 + + + FTFIFC0 + Clear bit for full transfer finish flag of channel 0 + 1 + 1 + + + HTFIFC0 + Clear bit for half transfer finish flag of channel 0 + 2 + 1 + + + ERRIFC0 + Clear bit for error flag of channel 0 + 3 + 1 + + + GIFC1 + Clear global interrupt flag of channel 1 + 4 + 1 + + + FTFIFC1 + Clear bit for full transfer finish flag of channel 1 + 5 + 1 + + + HTFIFC1 + Clear bit for half transfer finish flag of channel 1 + 6 + 1 + + + ERRIFC1 + Clear bit for error flag of channel 1 + 7 + 1 + + GIFC2 + Clear global interrupt flag of channel 2 + 8 + 1 + + + FTFIFC2 + Clear bit for full transfer finish flag of channel 2 + 9 + 1 + + + HTFIFC2 + Clear bit for half transfer finish flag of channel 2 + 10 + 1 + + + ERRIFC2 + Clear bit for error flag of channel 2 + 11 + 1 + + GIFC3 + Clear global interrupt flag of channel 3 + 12 + 1 + + + FTFIFC3 + Clear bit for full transfer finish flag of channel 3 + 13 + 1 + + + HTFIFC3 + Clear bit for half transfer finish flag of channel 3 + 14 + 1 + + + ERRIFC3 + Clear bit for error flag of channel 3 + 15 + 1 + + GIFC4 + Clear global interrupt flag of channel 4 + 16 + 1 + + + FTFIFC4 + Clear bit for full transfer finish flag of channel 4 + 17 + 1 + + + HTFIFC4 + Clear bit for half transfer finish flag of channel 4 + 18 + 1 + + + ERRIFC4 + Clear bit for error flag of channel 4 + 19 + 1 + + GIFC5 + Clear global interrupt flag of channel 5 + 20 + 1 + + + FTFIFC5 + Clear bit for full transfer finish flag of channel 5 + 21 + 1 + + + HTFIFC5 + Clear bit for half transfer finish flag of channel 5 + 22 + 1 + + + ERRIFC5 + Clear bit for error flag of channel 5 + 23 + 1 + + GIFC6 + Clear global interrupt flag of channel 6 + 24 + 1 + + + FTFIFC6 + Clear bit for full transfer finish flag of channel 6 + 25 + 1 + + + HTFIFC6 + Clear bit for half transfer finish flag of channel 6 + 26 + 1 + + + ERRIFC6 + Clear bit for error flag of channel 6 + 27 + 1 + + + + + CH0CTL + CH0CTL + Channel 0 control register + 0x08 + 0x20 + read-write + 0x00000000 + + + CHEN + Channel enable + 0 + 1 + + + FTFIE + Enable bit for channel full transfer finish interrupt + 1 + 1 + + + HTFIE + Enable bit for channel half transfer finish interrupt + 2 + 1 + + + ERRIE + Enable bit for channel error interrupt + 3 + 1 + + + DIR + Transfer direction + 4 + 1 + + + CMEN + Circular mode enable + 5 + 1 + + + PNAGA + Next address generation algorithm of peripheral + 6 + 1 + + + MNAGA + Next address generation algorithm of memory + 7 + 1 + + + PWIDTH + Transfer data size of peripheral + 8 + 2 + + + MWIDTH + Transfer data size of memory + 10 + 2 + + + PRIO + Priority level + 12 + 2 + + + M2M + Memory to Memory Mode + 14 + 1 + + + + + CH0CNT + CH0CNT + Channel 0 counter register + 0x0C + 0x20 + read-write + 0x00000000 + + + CNT + Transfer counter + 0 + 16 + + + + + CH0PADDR + CH0PADDR + Channel 0 peripheral base address register + 0x10 + 0x20 + read-write + 0x00000000 + + + PADDR + Peripheral base address + 0 + 32 + + + + + CH0MADDR + CH0MADDR + Channel 0 memory base address register + 0x14 + 0x20 + read-write + 0x00000000 + + + MADDR + Memory base address + 0 + 32 + + + + + CH1CTL + CH1CTL + Channel 1 control register + 0x1C + 0x20 + read-write + 0x00000000 + + + CHEN + Channel enable + 0 + 1 + + + FTFIE + Enable bit for channel full transfer finish interrupt + 1 + 1 + + + HTFIE + Enable bit for channel half transfer finish interrupt + 2 + 1 + + + ERRIE + Enable bit for channel error interrupt + 3 + 1 + + + DIR + Transfer direction + 4 + 1 + + + CMEN + Circular mode enable + 5 + 1 + + + PNAGA + Next address generation algorithm of peripheral + 6 + 1 + + + MNAGA + Next address generation algorithm of memory + 7 + 1 + + + PWIDTH + Transfer data size of peripheral + 8 + 2 + + + MWIDTH + Transfer data size of memory + 10 + 2 + + + PRIO + Priority level + 12 + 2 + + + M2M + Memory to Memory Mode + 14 + 1 + + + + + CH1CNT + CH1CNT + Channel 1 counter register + 0x20 + 0x20 + read-write + 0x00000000 + + + CNT + Transfer counter + 0 + 16 + + + + + CH1PADDR + CH1PADDR + Channel 1 peripheral base address register + 0x24 + 0x20 + read-write + 0x00000000 + + + PADDR + Peripheral base address + 0 + 32 + + + + + CH1MADDR + CH1MADDR + Channel 1 memory base address register + 0x28 + 0x20 + read-write + 0x00000000 + + + MADDR + Memory base address + 0 + 32 + + + + + CH2CTL + CH2CTL + Channel 2 control register + 0x30 + 0x20 + read-write + 0x00000000 + + + CHEN + Channel enable + 0 + 1 + + + FTFIE + Enable bit for channel full transfer finish interrupt + 1 + 1 + + + HTFIE + Enable bit for channel half transfer finish interrupt + 2 + 1 + + + ERRIE + Enable bit for channel error interrupt + 3 + 1 + + + DIR + Transfer direction + 4 + 1 + + + CMEN + Circular mode enable + 5 + 1 + + + PNAGA + Next address generation algorithm of peripheral + 6 + 1 + + + MNAGA + Next address generation algorithm of memory + 7 + 1 + + + PWIDTH + Transfer data size of peripheral + 8 + 2 + + + MWIDTH + Transfer data size of memory + 10 + 2 + + + PRIO + Priority level + 12 + 2 + + + M2M + Memory to Memory Mode + 14 + 1 + + + + + CH2CNT + CH2CNT + Channel 2 counter register + 0x34 + 0x20 + read-write + 0x00000000 + + + CNT + Transfer counter + 0 + 16 + + + + + CH2PADDR + CH2PADDR + Channel 2 peripheral base address register + 0x38 + 0x20 + read-write + 0x00000000 + + + PADDR + Peripheral base address + 0 + 32 + + + + + CH2MADDR + CH2MADDR + Channel 2 memory base address register + 0x3C + 0x20 + read-write + 0x00000000 + + + MADDR + Memory base address + 0 + 32 + + + + + CH3CTL + CH3CTL + Channel 3 control register + 0x44 + 0x20 + read-write + 0x00000000 + + + CHEN + Channel enable + 0 + 1 + + + FTFIE + Enable bit for channel full transfer finish interrupt + 1 + 1 + + + HTFIE + Enable bit for channel half transfer finish interrupt + 2 + 1 + + + ERRIE + Enable bit for channel error interrupt + 3 + 1 + + + DIR + Transfer direction + 4 + 1 + + + CMEN + Circular mode enable + 5 + 1 + + + PNAGA + Next address generation algorithm of peripheral + 6 + 1 + + + MNAGA + Next address generation algorithm of memory + 7 + 1 + + + PWIDTH + Transfer data size of peripheral + 8 + 2 + + + MWIDTH + Transfer data size of memory + 10 + 2 + + + PRIO + Priority level + 12 + 2 + + + M2M + Memory to Memory Mode + 14 + 1 + + + + + CH3CNT + CH3CNT + Channel 3 counter register + 0x48 + 0x20 + read-write + 0x00000000 + + + CNT + Transfer counter + 0 + 16 + + + + + CH3PADDR + CH3PADDR + Channel 3 peripheral base address register + 0x4C + 0x20 + read-write + 0x00000000 + + + PADDR + Peripheral base address + 0 + 32 + + + + + CH3MADDR + CH3MADDR + Channel 3 memory base address register + 0x50 + 0x20 + read-write + 0x00000000 + + + MADDR + Memory base address + 0 + 32 + + + + + CH4CTL + CH4CTL + Channel 4 control register + 0x58 + 0x20 + read-write + 0x00000000 + + + CHEN + Channel enable + 0 + 1 + + + FTFIE + Enable bit for channel full transfer finish interrupt + 1 + 1 + + + HTFIE + Enable bit for channel half transfer finish interrupt + 2 + 1 + + + ERRIE + Enable bit for channel error interrupt + 3 + 1 + + + DIR + Transfer direction + 4 + 1 + + + CMEN + Circular mode enable + 5 + 1 + + + PNAGA + Next address generation algorithm of peripheral + 6 + 1 + + + MNAGA + Next address generation algorithm of memory + 7 + 1 + + + PWIDTH + Transfer data size of peripheral + 8 + 2 + + + MWIDTH + Transfer data size of memory + 10 + 2 + + + PRIO + Priority level + 12 + 2 + + + M2M + Memory to Memory Mode + 14 + 1 + + + + + CH4CNT + CH4CNT + Channel 4 counter register + 0x5C + 0x20 + read-write + 0x00000000 + + + CNT + Transfer counter + 0 + 16 + + + + + CH4PADDR + CH4PADDR + Channel 4 peripheral base address register + 0x60 + 0x20 + read-write + 0x00000000 + + + PADDR + Peripheral base address + 0 + 32 + + + + + CH4MADDR + CH4MADDR + Channel 4 memory base address register + 0x64 + 0x20 + read-write + 0x00000000 + + + MADDR + Memory base address + 0 + 32 + + + + + CH5CTL + CH5CTL + Channel 5 control register + 0x6C + 0x20 + read-write + 0x00000000 + + + CHEN + Channel enable + 0 + 1 + + + FTFIE + Enable bit for channel full transfer finish interrupt + 1 + 1 + + + HTFIE + Enable bit for channel half transfer finish interrupt + 2 + 1 + + + ERRIE + Enable bit for channel error interrupt + 3 + 1 + + + DIR + Transfer direction + 4 + 1 + + + CMEN + Circular mode enable + 5 + 1 + + + PNAGA + Next address generation algorithm of peripheral + 6 + 1 + + + MNAGA + Next address generation algorithm of memory + 7 + 1 + + + PWIDTH + Transfer data size of peripheral + 8 + 2 + + + MWIDTH + Transfer data size of memory + 10 + 2 + + + PRIO + Priority level + 12 + 2 + + + M2M + Memory to Memory Mode + 14 + 1 + + + + + CH5CNT + CH5CNT + Channel 5 counter register + 0x70 + 0x20 + read-write + 0x00000000 + + + CNT + Transfer counter + 0 + 16 + + + + + CH5PADDR + CH5PADDR + Channel 5 peripheral base address register + 0x74 + 0x20 + read-write + 0x00000000 + + + PADDR + Peripheral base address + 0 + 32 + + + + + CH5MADDR + CH5MADDR + Channel 5 memory base address register + 0x78 + 0x20 + read-write + 0x00000000 + + + MADDR + Memory base address + 0 + 32 + + + + + CH6CTL + CH6CTL + Channel 6 control register + 0x80 + 0x20 + read-write + 0x00000000 + + + CHEN + Channel enable + 0 + 1 + + + FTFIE + Enable bit for channel full transfer finish interrupt + 1 + 1 + + + HTFIE + Enable bit for channel half transfer finish interrupt + 2 + 1 + + + ERRIE + Enable bit for channel error interrupt + 3 + 1 + + + DIR + Transfer direction + 4 + 1 + + + CMEN + Circular mode enable + 5 + 1 + + + PNAGA + Next address generation algorithm of peripheral + 6 + 1 + + + MNAGA + Next address generation algorithm of memory + 7 + 1 + + + PWIDTH + Transfer data size of peripheral + 8 + 2 + + + MWIDTH + Transfer data size of memory + 10 + 2 + + + PRIO + Priority level + 12 + 2 + + + M2M + Memory to Memory Mode + 14 + 1 + + + + + CH6CNT + CH6CNT + Channel 6 counter register + 0x84 + 0x20 + read-write + 0x00000000 + + + CNT + Transfer counter + 0 + 16 + + + + + CH6PADDR + CH6PADDR + Channel 6 peripheral base address register + 0x88 + 0x20 + read-write + 0x00000000 + + + PADDR + Peripheral base address + 0 + 32 + + + + + CH6MADDR + CH6MADDR + Channel 6 memory base address register + 0x8C + 0x20 + read-write + 0x00000000 + + + MADDR + Memory base address + 0 + 32 + + + + + + + DMA1 + Direct memory access controller + DMA + 0x40020000 + + 0x0 + 0x400 + registers + + 0x40020400 + + DMA1_Channel0 + 75 + + + DMA1_Channel1 + 76 + + + DMA1_Channel2 + 77 + + + DMA1_Channel3 + 78 + + + DMA1_Channel4 + 79 + + + + INTF + INTF + Interrupt flag register + 0x0 + 0x20 + read-only + 0x00000000 + + + GIF0 + Global interrupt flag of channel 0 + 0 + 1 + + + FTFIF0 + Full Transfer finish flag of channe 0 + 1 + 1 + + + HTFIF0 + Half transfer finish flag of channel 0 + 2 + 1 + + + ERRIF0 + Error flag of channel 0 + 3 + 1 + + + GIF1 + Global interrupt flag of channel 1 + 4 + 1 + + + FTFIF1 + Full Transfer finish flag of channe 1 + 5 + 1 + + + HTFIF1 + Half transfer finish flag of channel 1 + 6 + 1 + + + ERRIF1 + Error flag of channel 1 + 7 + 1 + + + GIF2 + Global interrupt flag of channel 2 + 8 + 1 + + + FTFIF2 + Full Transfer finish flag of channe 2 + 9 + 1 + + + HTFIF2 + Half transfer finish flag of channel 2 + 10 + 1 + + + ERRIF2 + Error flag of channel 2 + 11 + 1 + + + GIF3 + Global interrupt flag of channel 3 + 12 + 1 + + + FTFIF3 + Full Transfer finish flag of channe 3 + 13 + 1 + + + HTFIF3 + Half transfer finish flag of channel 3 + 14 + 1 + + + ERRIF3 + Error flag of channel 3 + 15 + 1 + + + GIF4 + Global interrupt flag of channel 4 + 16 + 1 + + + FTFIF4 + Full Transfer finish flag of channe 4 + 17 + 1 + + + HTFIF4 + Half transfer finish flag of channel 4 + 18 + 1 + + + ERRIF4 + Error flag of channel 4 + 19 + 1 + + + + + INTC + INTC + Interrupt flag clear register + 0x04 + 0x20 + write-only + 0x00000000 + + + GIFC0 + Clear global interrupt flag of channel 0 + 0 + 1 + + + FTFIFC0 + Clear bit for full transfer finish flag of channel 0 + 1 + 1 + + + HTFIFC0 + Clear bit for half transfer finish flag of channel 0 + 2 + 1 + + + ERRIFC0 + Clear bit for error flag of channel 0 + 3 + 1 + + + GIFC1 + Clear global interrupt flag of channel 1 + 4 + 1 + + + FTFIFC1 + Clear bit for full transfer finish flag of channel 1 + 5 + 1 + + + HTFIFC1 + Clear bit for half transfer finish flag of channel 1 + 6 + 1 + + + ERRIFC1 + Clear bit for error flag of channel 1 + 7 + 1 + + GIFC2 + Clear global interrupt flag of channel 2 + 8 + 1 + + + FTFIFC2 + Clear bit for full transfer finish flag of channel 2 + 9 + 1 + + + HTFIFC2 + Clear bit for half transfer finish flag of channel 2 + 10 + 1 + + + ERRIFC2 + Clear bit for error flag of channel 2 + 11 + 1 + + GIFC3 + Clear global interrupt flag of channel 3 + 12 + 1 + + + FTFIFC3 + Clear bit for full transfer finish flag of channel 3 + 13 + 1 + + + HTFIFC3 + Clear bit for half transfer finish flag of channel 3 + 14 + 1 + + + ERRIFC3 + Clear bit for error flag of channel 3 + 15 + 1 + + GIFC4 + Clear global interrupt flag of channel 4 + 16 + 1 + + + FTFIFC4 + Clear bit for full transfer finish flag of channel 4 + 17 + 1 + + + HTFIFC4 + Clear bit for half transfer finish flag of channel 4 + 18 + 1 + + + ERRIFC4 + Clear bit for error flag of channel 4 + 19 + 1 + + + + + CH0CTL + CH0CTL + Channel 0 control register + 0x08 + 0x20 + read-write + 0x00000000 + + + CHEN + Channel enable + 0 + 1 + + + FTFIE + Enable bit for channel full transfer finish interrupt + 1 + 1 + + + HTFIE + Enable bit for channel half transfer finish interrupt + 2 + 1 + + + ERRIE + Enable bit for channel error interrupt + 3 + 1 + + + DIR + Transfer direction + 4 + 1 + + + CMEN + Circular mode enable + 5 + 1 + + + PNAGA + Next address generation algorithm of peripheral + 6 + 1 + + + MNAGA + Next address generation algorithm of memory + 7 + 1 + + + PWIDTH + Transfer data size of peripheral + 8 + 2 + + + MWIDTH + Transfer data size of memory + 10 + 2 + + + PRIO + Priority level + 12 + 2 + + + M2M + Memory to Memory Mode + 14 + 1 + + + + + CH0CNT + CH0CNT + Channel 0 counter register + 0x0C + 0x20 + read-write + 0x00000000 + + + CNT + Transfer counter + 0 + 16 + + + + + CH0PADDR + CH0PADDR + Channel 0 peripheral base address register + 0x10 + 0x20 + read-write + 0x00000000 + + + PADDR + Peripheral base address + 0 + 32 + + + + + CH0MADDR + CH0MADDR + Channel 0 memory base address register + 0x14 + 0x20 + read-write + 0x00000000 + + + MADDR + Memory base address + 0 + 32 + + + + + CH1CTL + CH1CTL + Channel 1 control register + 0x1C + 0x20 + read-write + 0x00000000 + + + CHEN + Channel enable + 0 + 1 + + + FTFIE + Enable bit for channel full transfer finish interrupt + 1 + 1 + + + HTFIE + Enable bit for channel half transfer finish interrupt + 2 + 1 + + + ERRIE + Enable bit for channel error interrupt + 3 + 1 + + + DIR + Transfer direction + 4 + 1 + + + CMEN + Circular mode enable + 5 + 1 + + + PNAGA + Next address generation algorithm of peripheral + 6 + 1 + + + MNAGA + Next address generation algorithm of memory + 7 + 1 + + + PWIDTH + Transfer data size of peripheral + 8 + 2 + + + MWIDTH + Transfer data size of memory + 10 + 2 + + + PRIO + Priority level + 12 + 2 + + + M2M + Memory to Memory Mode + 14 + 1 + + + + + CH1CNT + CH1CNT + Channel 1 counter register + 0x20 + 0x20 + read-write + 0x00000000 + + + CNT + Transfer counter + 0 + 16 + + + + + CH1PADDR + CH1PADDR + Channel 1 peripheral base address register + 0x24 + 0x20 + read-write + 0x00000000 + + + PADDR + Peripheral base address + 0 + 32 + + + + + CH1MADDR + CH1MADDR + Channel 1 memory base address register + 0x28 + 0x20 + read-write + 0x00000000 + + + MADDR + Memory base address + 0 + 32 + + + + + CH2CTL + CH2CTL + Channel 2 control register + 0x30 + 0x20 + read-write + 0x00000000 + + + CHEN + Channel enable + 0 + 1 + + + FTFIE + Enable bit for channel full transfer finish interrupt + 1 + 1 + + + HTFIE + Enable bit for channel half transfer finish interrupt + 2 + 1 + + + ERRIE + Enable bit for channel error interrupt + 3 + 1 + + + DIR + Transfer direction + 4 + 1 + + + CMEN + Circular mode enable + 5 + 1 + + + PNAGA + Next address generation algorithm of peripheral + 6 + 1 + + + MNAGA + Next address generation algorithm of memory + 7 + 1 + + + PWIDTH + Transfer data size of peripheral + 8 + 2 + + + MWIDTH + Transfer data size of memory + 10 + 2 + + + PRIO + Priority level + 12 + 2 + + + M2M + Memory to Memory Mode + 14 + 1 + + + + + CH2CNT + CH2CNT + Channel 2 counter register + 0x34 + 0x20 + read-write + 0x00000000 + + + CNT + Transfer counter + 0 + 16 + + + + + CH2PADDR + CH2PADDR + Channel 2 peripheral base address register + 0x38 + 0x20 + read-write + 0x00000000 + + + PADDR + Peripheral base address + 0 + 32 + + + + + CH2MADDR + CH2MADDR + Channel 2 memory base address register + 0x3C + 0x20 + read-write + 0x00000000 + + + MADDR + Memory base address + 0 + 32 + + + + + CH3CTL + CH3CTL + Channel 3 control register + 0x44 + 0x20 + read-write + 0x00000000 + + + CHEN + Channel enable + 0 + 1 + + + FTFIE + Enable bit for channel full transfer finish interrupt + 1 + 1 + + + HTFIE + Enable bit for channel half transfer finish interrupt + 2 + 1 + + + ERRIE + Enable bit for channel error interrupt + 3 + 1 + + + DIR + Transfer direction + 4 + 1 + + + CMEN + Circular mode enable + 5 + 1 + + + PNAGA + Next address generation algorithm of peripheral + 6 + 1 + + + MNAGA + Next address generation algorithm of memory + 7 + 1 + + + PWIDTH + Transfer data size of peripheral + 8 + 2 + + + MWIDTH + Transfer data size of memory + 10 + 2 + + + PRIO + Priority level + 12 + 2 + + + M2M + Memory to Memory Mode + 14 + 1 + + + + + CH3CNT + CH3CNT + Channel 3 counter register + 0x48 + 0x20 + read-write + 0x00000000 + + + CNT + Transfer counter + 0 + 16 + + + + + CH3PADDR + CH3PADDR + Channel 3 peripheral base address register + 0x4C + 0x20 + read-write + 0x00000000 + + + PADDR + Peripheral base address + 0 + 32 + + + + + CH3MADDR + CH3MADDR + Channel 3 memory base address register + 0x50 + 0x20 + read-write + 0x00000000 + + + MADDR + Memory base address + 0 + 32 + + + + + CH4CTL + CH4CTL + Channel 4 control register + 0x58 + 0x20 + read-write + 0x00000000 + + + CHEN + Channel enable + 0 + 1 + + + FTFIE + Enable bit for channel full transfer finish interrupt + 1 + 1 + + + HTFIE + Enable bit for channel half transfer finish interrupt + 2 + 1 + + + ERRIE + Enable bit for channel error interrupt + 3 + 1 + + + DIR + Transfer direction + 4 + 1 + + + CMEN + Circular mode enable + 5 + 1 + + + PNAGA + Next address generation algorithm of peripheral + 6 + 1 + + + MNAGA + Next address generation algorithm of memory + 7 + 1 + + + PWIDTH + Transfer data size of peripheral + 8 + 2 + + + MWIDTH + Transfer data size of memory + 10 + 2 + + + PRIO + Priority level + 12 + 2 + + + M2M + Memory to Memory Mode + 14 + 1 + + + + + CH4CNT + CH4CNT + Channel 4 counter register + 0x5C + 0x20 + read-write + 0x00000000 + + + CNT + Transfer counter + 0 + 16 + + + + + CH4PADDR + CH4PADDR + Channel 4 peripheral base address register + 0x60 + 0x20 + read-write + 0x00000000 + + + PADDR + Peripheral base address + 0 + 32 + + + + + CH4MADDR + CH4MADDR + Channel 4 memory base address register + 0x64 + 0x20 + read-write + 0x00000000 + + + MADDR + Memory base address + 0 + 32 + + + + + + + EXMC + External memory controller + EXMC + 0xA0000000 + + 0x0 + 0x1000 + registers + + + + SNCTL0 + SNCTL0 + SRAM/NOR flash control register 0 + 0x0 + 0x20 + read-write + 0x000030DA + + + ASYNCWAIT + Asynchronous wait + 15 + 1 + + + NRWTEN + NWAIT signal enable + 13 + 1 + + + WREN + Write enable + 12 + 1 + + + NRWTPOL + NWAIT signal polarity + 9 + 1 + + + NREN + NOR Flash access enable + 6 + 1 + + + NRW + NOR bank memory data bus width + 4 + 2 + + + NRTP + NOR bank memory type + 2 + 2 + + + NRMUX + NOR bank memory address/data multiplexing + 1 + 1 + + + NRBKEN + NOR bank enable + 0 + 1 + + + + + SNTCFG0 + SNTCFG0 + SRAM/NOR flash timing configuration register 0 + 0x4 + 0x20 + read-write + 0x0FFFFFFF + + + BUSLAT + Bus latency + 16 + 4 + + + DSET + Data setup time + 8 + 8 + + + AHLD + Address hold time + 4 + 4 + + + ASET + Address setup time + 0 + 4 + + + + + SNCTL1 + SNCTL1 + SRAM/NOR flash control register 1 + 0x8 + 0x20 + read-write + 0x000030DA + + + ASYNCWAIT + Asynchronous wait + 15 + 1 + + + NRWTEN + NWAIT signal enable + 13 + 1 + + + WREN + Write enable + 12 + 1 + + + NRWTPOL + NWAIT signal polarity + 9 + 1 + + + NREN + NOR Flash access enable + 6 + 1 + + + NRW + NOR bank memory data bus width + 4 + 2 + + + NRTP + NOR bank memory type + 2 + 2 + + + NRMUX + NOR bank memory address/data multiplexing + 1 + 1 + + + NRBKEN + NOR bank enable + 0 + 1 + + + + + + + EXTI + External interrupt/event + controller + EXTI + 0x40010400 + + 0x0 + 0x400 + registers + + + EXTI_Line0 + 25 + + + EXTI_Line1 + 26 + + + EXTI_Line2 + 27 + + + EXTI_Line3 + 28 + + + EXTI_Line4 + 29 + + + EXTI_line9_5 + 42 + + + EXTI_line15_10 + 59 + + + + INTEN + INTEN + Interrupt enable register + (EXTI_INTEN) + 0x0 + 0x20 + read-write + 0x00000000 + + + INTEN0 + Enable Interrupt on line 0 + 0 + 1 + + + INTEN1 + Enable Interrupt on line 1 + 1 + 1 + + + INTEN2 + Enable Interrupt on line 2 + 2 + 1 + + + INTEN3 + Enable Interrupt on line 3 + 3 + 1 + + + INTEN4 + Enable Interrupt on line 4 + 4 + 1 + + + INTEN5 + Enable Interrupt on line 5 + 5 + 1 + + + INTEN6 + Enable Interrupt on line 6 + 6 + 1 + + + INTEN7 + Enable Interrupt on line 7 + 7 + 1 + + + INTEN8 + Enable Interrupt on line 8 + 8 + 1 + + + INTEN9 + Enable Interrupt on line 9 + 9 + 1 + + + INTEN10 + Enable Interrupt on line 10 + 10 + 1 + + + INTEN11 + Enable Interrupt on line 11 + 11 + 1 + + + INTEN12 + Enable Interrupt on line 12 + 12 + 1 + + + INTEN13 + Enable Interrupt on line 13 + 13 + 1 + + + INTEN14 + Enable Interrupt on line 14 + 14 + 1 + + + INTEN15 + Enable Interrupt on line 15 + 15 + 1 + + + INTEN16 + Enable Interrupt on line 16 + 16 + 1 + + + INTEN17 + Enable Interrupt on line 17 + 17 + 1 + + + INTEN18 + Enable Interrupt on line 18 + 18 + 1 + + + + + EVEN + EVEN + Event enable register (EXTI_EVEN) + 0x04 + 0x20 + read-write + 0x00000000 + + + EVEN0 + Enable Event on line 0 + 0 + 1 + + + EVEN1 + Enable Event on line 1 + 1 + 1 + + + EVEN2 + Enable Event on line 2 + 2 + 1 + + + EVEN3 + Enable Event on line 3 + 3 + 1 + + + EVEN4 + Enable Event on line 4 + 4 + 1 + + + EVEN5 + Enable Event on line 5 + 5 + 1 + + + EVEN6 + Enable Event on line 6 + 6 + 1 + + + EVEN7 + Enable Event on line 7 + 7 + 1 + + + EVEN8 + Enable Event on line 8 + 8 + 1 + + + EVEN9 + Enable Event on line 9 + 9 + 1 + + + EVEN10 + Enable Event on line 10 + 10 + 1 + + + EVEN11 + Enable Event on line 11 + 11 + 1 + + + EVEN12 + Enable Event on line 12 + 12 + 1 + + + EVEN13 + Enable Event on line 13 + 13 + 1 + + + EVEN14 + Enable Event on line 14 + 14 + 1 + + + EVEN15 + Enable Event on line 15 + 15 + 1 + + + EVEN16 + Enable Event on line 16 + 16 + 1 + + + EVEN17 + Enable Event on line 17 + 17 + 1 + + + EVEN18 + Enable Event on line 18 + 18 + 1 + + + + + RTEN + RTEN + Rising Edge Trigger Enable register + (EXTI_RTEN) + 0x08 + 0x20 + read-write + 0x00000000 + + + RTEN0 + Rising edge trigger enable of + line 0 + 0 + 1 + + + RTEN1 + Rising edge trigger enable of + line 1 + 1 + 1 + + + RTEN2 + Rising edge trigger enable of + line 2 + 2 + 1 + + + RTEN3 + Rising edge trigger enable of + line 3 + 3 + 1 + + + RTEN4 + Rising edge trigger enable of + line 4 + 4 + 1 + + + RTEN5 + Rising edge trigger enable of + line 5 + 5 + 1 + + + RTEN6 + Rising edge trigger enable of + line 6 + 6 + 1 + + + RTEN7 + Rising edge trigger enable of + line 7 + 7 + 1 + + + RTEN8 + Rising edge trigger enable of + line 8 + 8 + 1 + + + RTEN9 + Rising edge trigger enable of + line 9 + 9 + 1 + + + RTEN10 + Rising edge trigger enable of + line 10 + 10 + 1 + + + RTEN11 + Rising edge trigger enable of + line 11 + 11 + 1 + + + RTEN12 + Rising edge trigger enable of + line 12 + 12 + 1 + + + RTEN13 + Rising edge trigger enable of + line 13 + 13 + 1 + + + RTEN14 + Rising edge trigger enable of + line 14 + 14 + 1 + + + RTEN15 + Rising edge trigger enable of + line 15 + 15 + 1 + + + RTEN16 + Rising edge trigger enable of + line 16 + 16 + 1 + + + RTEN17 + Rising edge trigger enable of + line 17 + 17 + 1 + + + RTEN18 + Rising edge trigger enable of + line 18 + 18 + 1 + + + + + FTEN + FTEN + Falling Egde Trigger Enable register + (EXTI_FTEN) + 0x0C + 0x20 + read-write + 0x00000000 + + + FTEN0 + Falling edge trigger enable of + line 0 + 0 + 1 + + + FTEN1 + Falling edge trigger enable of + line 1 + 1 + 1 + + + FTEN2 + Falling edge trigger enable of + line 2 + 2 + 1 + + + FTEN3 + Falling edge trigger enable of + line 3 + 3 + 1 + + + FTEN4 + Falling edge trigger enable of + line 4 + 4 + 1 + + + FTEN5 + Falling edge trigger enable of + line 5 + 5 + 1 + + + FTEN6 + Falling edge trigger enable of + line 6 + 6 + 1 + + + FTEN7 + Falling edge trigger enable of + line 7 + 7 + 1 + + + FTEN8 + Falling edge trigger enable of + line 8 + 8 + 1 + + + FTEN9 + Falling edge trigger enable of + line 9 + 9 + 1 + + + FTEN10 + Falling edge trigger enable of + line 10 + 10 + 1 + + + FTEN11 + Falling edge trigger enable of + line 11 + 11 + 1 + + + FTEN12 + Falling edge trigger enable of + line 12 + 12 + 1 + + + FTEN13 + Falling edge trigger enable of + line 13 + 13 + 1 + + + FTEN14 + Falling edge trigger enable of + line 14 + 14 + 1 + + + FTEN15 + Falling edge trigger enable of + line 15 + 15 + 1 + + + FTEN16 + Falling edge trigger enable of + line 16 + 16 + 1 + + + FTEN17 + Falling edge trigger enable of + line 17 + 17 + 1 + + + FTEN18 + Falling edge trigger enable of + line 18 + 18 + 1 + + + + + SWIEV + SWIEV + Software interrupt event register + (EXTI_SWIEV) + 0x10 + 0x20 + read-write + 0x00000000 + + + SWIEV0 + Interrupt/Event software trigger on line + 0 + 0 + 1 + + + SWIEV1 + Interrupt/Event software trigger on line + 1 + 1 + 1 + + + SWIEV2 + Interrupt/Event software trigger on line + 2 + 2 + 1 + + + SWIEV3 + Interrupt/Event software trigger on line + 3 + 3 + 1 + + + SWIEV4 + Interrupt/Event software trigger on line + 4 + 4 + 1 + + + SWIEV5 + Interrupt/Event software trigger on line + 5 + 5 + 1 + + + SWIEV6 + Interrupt/Event software trigger on line + 6 + 6 + 1 + + + SWIEV7 + Interrupt/Event software trigger on line + 7 + 7 + 1 + + + SWIEV8 + Interrupt/Event software trigger on line + 8 + 8 + 1 + + + SWIEV9 + Interrupt/Event software trigger on line + 9 + 9 + 1 + + + SWIEV10 + Interrupt/Event software trigger on line + 10 + 10 + 1 + + + SWIEV11 + Interrupt/Event software trigger on line + 11 + 11 + 1 + + + SWIEV12 + Interrupt/Event software trigger on line + 12 + 12 + 1 + + + SWIEV13 + Interrupt/Event software trigger on line + 13 + 13 + 1 + + + SWIEV14 + Interrupt/Event software trigger on line + 14 + 14 + 1 + + + SWIEV15 + Interrupt/Event software trigger on line + 15 + 15 + 1 + + + SWIEV16 + Interrupt/Event software trigger on line + 16 + 16 + 1 + + + SWIEV17 + Interrupt/Event software trigger on line + 17 + 17 + 1 + + + SWIEV18 + Interrupt/Event software trigger on line + 18 + 18 + 1 + + + + + PD + PD + Pending register (EXTI_PD) + 0x14 + 0x20 + read-write + 0x00000000 + + + PD0 + Interrupt pending status of line 0 + 0 + 1 + + + PD1 + Interrupt pending status of line 1 + 1 + 1 + + + PD2 + Interrupt pending status of line 2 + 2 + 1 + + + PD3 + Interrupt pending status of line 3 + 3 + 1 + + + PD4 + Interrupt pending status of line 4 + 4 + 1 + + + PD5 + Interrupt pending status of line 5 + 5 + 1 + + + PD6 + Interrupt pending status of line 6 + 6 + 1 + + + PD7 + Interrupt pending status of line 7 + 7 + 1 + + + PD8 + Interrupt pending status of line 8 + 8 + 1 + + + PD9 + Interrupt pending status of line 9 + 9 + 1 + + + PD10 + Interrupt pending status of line 10 + 10 + 1 + + + PD11 + Interrupt pending status of line 11 + 11 + 1 + + + PD12 + Interrupt pending status of line 12 + 12 + 1 + + + PD13 + Interrupt pending status of line 13 + 13 + 1 + + + PD14 + Interrupt pending status of line 14 + 14 + 1 + + + PD15 + Interrupt pending status of line 15 + 15 + 1 + + + PD16 + Interrupt pending status of line 16 + 16 + 1 + + + PD17 + Interrupt pending status of line 17 + 17 + 1 + + + PD18 + Interrupt pending status of line 18 + 18 + 1 + + + + + + + FMC + FMC + FMC + 0x40022000 + + 0x0 + 0x400 + registers + + + FMC + 23 + + + + WS + WS + wait state counter register + 0x0 + 0x20 + read-write + 0x00000000 + + + WSCNT + wait state counter register + 0 + 3 + + + + + KEY0 + KEY0 + Unlock key register 0 + 0x04 + 0x20 + write-only + 0x00000000 + + + KEY + FMC_CTL0 unlock key + 0 + 32 + + + + + OBKEY + OBKEY + Option byte unlock key register + 0x08 + 0x20 + write-only + 0x00000000 + + + OBKEY + FMC_ CTL0 option byte operation unlock register + 0 + 32 + + + + + STAT0 + STAT0 + Status register 0 + 0x0C + 0x20 + 0x00000000 + + + ENDF + End of operation flag bit + 5 + 1 + read-write + + + WPERR + Erase/Program protection error flag bit + 4 + 1 + read-write + + + PGERR + Program error flag bit + 2 + 1 + read-write + + + BUSY + The flash is busy bit + 0 + 1 + read-only + + + + + CTL0 + CTL0 + Control register 0 + 0x10 + 0x20 + read-write + 0x00000080 + + + ENDIE + End of operation interrupt enable bit + 12 + 1 + + + ERRIE + Error interrupt enable bit + 10 + 1 + + + OBWEN + Option byte erase/program enable bit + 9 + 1 + + + LK + FMC_CTL0 lock bit + 7 + 1 + + + START + Send erase command to FMC bit + 6 + 1 + + + OBER + Option bytes erase command bit + 5 + 1 + + + OBPG + Option bytes program command bit + 4 + 1 + + + MER + Main flash mass erase for bank0 command bit + 2 + 1 + + + PER + Main flash page erase for bank0 command bit + 1 + 1 + + + PG + Main flash program for bank0 command bit + 0 + 1 + + + + + ADDR0 + ADDR0 + Address register 0 + 0x14 + 0x20 + write-only + 0x00000000 + + + ADDR + Flash erase/program command address bits + 0 + 32 + + + + + OBSTAT + OBSTAT + Option byte status register + 0x1C + 0x20 + read-only + 0x00000000 + + + OBERR + Option bytes read error bit + 0 + 1 + + + SPC + Option bytes security protection code + 1 + 1 + + + USER + Store USER of option bytes block after system reset + 2 + 8 + + + DATA + Store DATA[15:0] of option bytes block after system reset + 10 + 16 + + + + + WP + WP + Erase/Program Protection register + 0x20 + 0x20 + read-only + 0x00000000 + + + WP + Store WP[31:0] of option bytes block after system reset + 0 + 32 + + + + + PID + PID + Product ID register + 0x100 + 0x20 + read-only + 0x00000000 + + + PID + Product reserved ID code register + 0 + 32 + + + + + + + FWDGT + free watchdog timer + FWDGT + 0x40003000 + + 0x0 + 0x400 + registers + + + + CTL + CTL + Control register + 0x00 + 0x20 + write-only + 0x00000000 + + + CMD + Key value + 0 + 16 + + + + + PSC + PSC + Prescaler register + 0x04 + 0x20 + read-write + 0x00000000 + + + PSC + Free watchdog timer prescaler selection + 0 + 3 + + + + + RLD + RLD + Reload register + 0x08 + 0x20 + read-write + 0x00000FFF + + + RLD + Free watchdog timer counter reload value + 0 + 12 + + + + + STAT + STAT + Status register + 0x0C + 0x20 + read-only + 0x00000000 + + + PUD + Free watchdog timer prescaler value update + 0 + 1 + + + RUD + Free watchdog timer counter reload value update + 1 + 1 + + + + + + + GPIOA + General-purpose I/Os + GPIO + 0x40010800 + + 0x0 + 0x400 + registers + + + + CTL0 + CTL0 + port control register 0 + 0x0 + 0x20 + read-write + 0x44444444 + + + CTL7 + Port x configuration bits (x = + 7) + 30 + 2 + + + MD7 + Port x mode bits (x = + 7) + 28 + 2 + + + CTL6 + Port x configuration bits (x = + 6) + 26 + 2 + + + MD6 + Port x mode bits (x = + 6) + 24 + 2 + + + CTL5 + Port x configuration bits (x = + 5) + 22 + 2 + + + MD5 + Port x mode bits (x = + 5) + 20 + 2 + + + CTL4 + Port x configuration bits (x = + 4) + 18 + 2 + + + MD4 + Port x mode bits (x = + 4) + 16 + 2 + + + CTL3 + Port x configuration bits (x = + 3) + 14 + 2 + + + MD3 + Port x mode bits (x = + 3 ) + 12 + 2 + + + CTL2 + Port x configuration bits (x = + 2) + 10 + 2 + + + MD2 + Port x mode bits (x = + 2 ) + 8 + 2 + + + CTL1 + Port x configuration bits (x = + 1) + 6 + 2 + + + MD1 + Port x mode bits (x = + 1) + 4 + 2 + + + CTL0 + Port x configuration bits (x = + 0) + 2 + 2 + + + MD0 + Port x mode bits (x = + 0) + 0 + 2 + + + + + CTL1 + CTL1 + port control register 1 + 0x04 + 0x20 + read-write + 0x44444444 + + + CTL15 + Port x configuration bits (x = + 15) + 30 + 2 + + + MD15 + Port x mode bits (x = + 15) + 28 + 2 + + + CTL14 + Port x configuration bits (x = + 14) + 26 + 2 + + + MD14 + Port x mode bits (x = + 14) + 24 + 2 + + + CTL13 + Port x configuration bits (x = + 13) + 22 + 2 + + + MD13 + Port x mode bits (x = + 13) + 20 + 2 + + + CTL12 + Port x configuration bits (x = + 12) + 18 + 2 + + + MD12 + Port x mode bits (x = + 12) + 16 + 2 + + + CTL11 + Port x configuration bits (x = + 11) + 14 + 2 + + + MD11 + Port x mode bits (x = + 11 ) + 12 + 2 + + + CTL10 + Port x configuration bits (x = + 10) + 10 + 2 + + + MD10 + Port x mode bits (x = + 10 ) + 8 + 2 + + + CTL9 + Port x configuration bits (x = + 9) + 6 + 2 + + + MD9 + Port x mode bits (x = + 9) + 4 + 2 + + + CTL8 + Port x configuration bits (x = + 8) + 2 + 2 + + + MD8 + Port x mode bits (x = + 8) + 0 + 2 + + + + + ISTAT + ISTAT + Port input status register + 0x08 + 0x20 + read-only + 0x00000000 + + + ISTAT15 + Port input status + 15 + 1 + + + ISTAT14 + Port input status + 14 + 1 + + + ISTAT13 + Port input status + 13 + 1 + + + ISTAT12 + Port input status + 12 + 1 + + + ISTAT11 + Port input status + 11 + 1 + + + ISTAT10 + Port input status + 10 + 1 + + + ISTAT9 + Port input status + 9 + 1 + + + ISTAT8 + Port input status + 8 + 1 + + + ISTAT7 + Port input status + 7 + 1 + + + ISTAT6 + Port input status + 6 + 1 + + + ISTAT5 + Port input status + 5 + 1 + + + ISTAT4 + Port input status + 4 + 1 + + + ISTAT3 + Port input status + 3 + 1 + + + ISTAT2 + Port input status + 2 + 1 + + + ISTAT1 + Port input status + 1 + 1 + + + ISTAT0 + Port input status + 0 + 1 + + + + + OCTL + OCTL + Port output control register + 0x0C + 0x20 + read-write + 0x00000000 + + + OCTL15 + Port output control + 15 + 1 + + + OCTL14 + Port output control + 14 + 1 + + + OCTL13 + Port output control + 13 + 1 + + + OCTL12 + Port output control + 12 + 1 + + + OCTL11 + Port output control + 11 + 1 + + + OCTL10 + Port output control + 10 + 1 + + + OCTL9 + Port output control + 9 + 1 + + + OCTL8 + Port output control + 8 + 1 + + + OCTL7 + Port output control + 7 + 1 + + + OCTL6 + Port output control + 6 + 1 + + + OCTL5 + Port output control + 5 + 1 + + + OCTL4 + Port output control + 4 + 1 + + + OCTL3 + Port output control + 3 + 1 + + + OCTL2 + Port output control + 2 + 1 + + + OCTL1 + Port output control + 1 + 1 + + + OCTL0 + Port output control + 0 + 1 + + + + + BOP + BOP + Port bit operate register + 0x10 + 0x20 + write-only + 0x00000000 + + + CR15 + Port 15 Clear bit + 31 + 1 + + + CR14 + Port 14 Clear bit + 30 + 1 + + + CR13 + Port 13 Clear bit + 29 + 1 + + + CR12 + Port 12 Clear bit + 28 + 1 + + + CR11 + Port 11 Clear bit + 27 + 1 + + + CR10 + Port 10 Clear bit + 26 + 1 + + + CR9 + Port 9 Clear bit + 25 + 1 + + + CR8 + Port 8 Clear bit + 24 + 1 + + + CR7 + Port 7 Clear bit + 23 + 1 + + + CR6 + Port 6 Clear bit + 22 + 1 + + + CR5 + Port 5 Clear bit + 21 + 1 + + + CR4 + Port 4 Clear bit + 20 + 1 + + + CR3 + Port 3 Clear bit + 19 + 1 + + + CR2 + Port 2 Clear bit + 18 + 1 + + + CR1 + Port 1 Clear bit + 17 + 1 + + + CR0 + Port 0 Clear bit + 16 + 1 + + + BOP15 + Port 15 Set bit + 15 + 1 + + + BOP14 + Port 14 Set bit + 14 + 1 + + + BOP13 + Port 13 Set bit + 13 + 1 + + + BOP12 + Port 12 Set bit + 12 + 1 + + + BOP11 + Port 11 Set bit + 11 + 1 + + + BOP10 + Port 10 Set bit + 10 + 1 + + + BOP9 + Port 9 Set bit + 9 + 1 + + + BOP8 + Port 8 Set bit + 8 + 1 + + + BOP7 + Port 7 Set bit + 7 + 1 + + + BOP6 + Port 6 Set bit + 6 + 1 + + + BOP5 + Port 5 Set bit + 5 + 1 + + + BOP4 + Port 4 Set bit + 4 + 1 + + + BOP3 + Port 3 Set bit + 3 + 1 + + + BOP2 + Port 2 Set bit + 2 + 1 + + + BOP1 + Port 1 Set bit + 1 + 1 + + + BOP0 + Port 0 Set bit + 0 + 1 + + + + + BC + BC + Port bit clear register + 0x14 + 0x20 + write-only + 0x00000000 + + + CR15 + Port 15 Clear bit + 15 + 1 + + + CR14 + Port 14 Clear bit + 14 + 1 + + + CR13 + Port 13 Clear bit + 13 + 1 + + + CR12 + Port 12 Clear bit + 12 + 1 + + + CR11 + Port 11 Clear bit + 11 + 1 + + + CR10 + Port 10 Clear bit + 10 + 1 + + + CR9 + Port 9 Clear bit + 9 + 1 + + + CR8 + Port 8 Clear bit + 8 + 1 + + + CR7 + Port 7 Clear bit + 7 + 1 + + + CR6 + Port 6 Clear bit + 6 + 1 + + + CR5 + Port 5 Clear bit + 5 + 1 + + + CR4 + Port 4 Clear bit + 4 + 1 + + + CR3 + Port 3 Clear bit + 3 + 1 + + + CR2 + Port 2 Clear bit + 2 + 1 + + + CR1 + Port 1 Clear bit + 1 + 1 + + + CR0 + Port 0 Clear bit + 0 + 1 + + + + + LOCK + LOCK + GPIO port configuration lock + register + 0x18 + 0x20 + read-write + 0x00000000 + + + LKK + Lock sequence key + + 16 + 1 + + + LK15 + Port Lock bit 15 + 15 + 1 + + + LK14 + Port Lock bit 14 + 14 + 1 + + + LK13 + Port Lock bit 13 + 13 + 1 + + + LK12 + Port Lock bit 12 + 12 + 1 + + + LK11 + Port Lock bit 11 + 11 + 1 + + + LK10 + Port Lock bit 10 + 10 + 1 + + + LK9 + Port Lock bit 9 + 9 + 1 + + + LK8 + Port Lock bit 8 + 8 + 1 + + + LK7 + Port Lock bit 7 + 7 + 1 + + + LK6 + Port Lock bit 6 + 6 + 1 + + + LK5 + Port Lock bit 5 + 5 + 1 + + + LK4 + Port Lock bit 4 + 4 + 1 + + + LK3 + Port Lock bit 3 + 3 + 1 + + + LK2 + Port Lock bit 2 + 2 + 1 + + + LK1 + Port Lock bit 1 + 1 + 1 + + + LK0 + Port Lock bit 0 + 0 + 1 + + + + + + + GPIOB + 0x40010C00 + + + GPIOC + 0x40011000 + + + GPIOD + 0x40011400 + + + GPIOE + 0x40011800 + + + I2C0 + Inter integrated circuit + I2C + 0x40005400 + + 0x0 + 0x400 + registers + + + I2C0_EV + 50 + + + I2C0_ER + 51 + + + + CTL0 + CTL0 + Control register 0 + 0x0 + 0x10 + read-write + 0x0000 + + + SRESET + Software reset + 15 + 1 + + + SALT + SMBus alert + 13 + 1 + + + PECTRANS + PEC Transfer + 12 + 1 + + + POAP + Position of ACK and PEC when receiving + 11 + 1 + + + ACKEN + Whether or not to send an ACK + 10 + 1 + + + STOP + Generate a STOP condition on I2C bus + 9 + 1 + + + START + Generate a START condition on I2C bus + 8 + 1 + + + SS + Whether to stretch SCL low when data is not ready in slave mode + 7 + 1 + + + GCEN + Whether or not to response to a General Call (0x00) + 6 + 1 + + + PECEN + PEC Calculation Switch + 5 + 1 + + + ARPEN + ARP protocol in SMBus switch + 4 + 1 + + + SMBSEL + SMBusType Selection + 3 + 1 + + + SMBEN + SMBus/I2C mode switch + 1 + 1 + + + I2CEN + I2C peripheral enable + 0 + 1 + + + + + CTL1 + CTL1 + Control register 1 + 0x04 + 0x10 + read-write + 0x0000 + + + DMALST + Flag indicating DMA last transfer + 12 + 1 + + + DMAON + DMA mode switch + 11 + 1 + + + BUFIE + Buffer interrupt enable + 10 + 1 + + + EVIE + Event interrupt enable + 9 + 1 + + + ERRIE + Error interrupt enable + 8 + 1 + + + I2CCLK + I2C Peripheral clock frequency + 0 + 6 + + + + + SADDR0 + SADDR0 + Slave address register 0 + 0x08 + 0x10 + read-write + 0x0000 + + + ADDFORMAT + Address mode for the I2C slave + 15 + 1 + + + ADDRESS9_8 + Highest two bits of a 10-bit address + 8 + 2 + + + ADDRESS7_1 + 7-bit address or bits 7:1 of a 10-bit address + 1 + 7 + + + ADDRESS0 + Bit 0 of a 10-bit address + 0 + 1 + + + + + SADDR1 + SADDR1 + Slave address register 1 + 0x0C + 0x10 + read-write + 0x0000 + + + ADDRESS2 + Second I2C address for the slave in Dual-Address mode + 1 + 7 + + + DUADEN + Dual-Address mode switch + 0 + 1 + + + + + DATA + DATA + Transfer buffer register + 0x10 + 0x10 + read-write + 0x0000 + + + TRB + Transmission or reception data buffer register + 0 + 8 + + + + + STAT0 + STAT0 + Transfer status register 0 + 0x14 + 0x10 + 0x0000 + + + SMBALT + SMBus Alert status + 15 + 1 + read-write + + + SMBTO + Timeout signal in SMBus mode + 14 + 1 + read-write + + + PECERR + PEC error when receiving data + 12 + 1 + read-write + + + OUERR + Over-run or under-run situation occurs in slave mode + 11 + 1 + read-write + + + AERR + Acknowledge error + 10 + 1 + read-write + + + LOSTARB + Arbitration Lost in master mode + 9 + 1 + read-write + + + BERR + A bus error occurs indication a unexpected START or STOP condition on I2C bus + 8 + 1 + read-write + + + TBE + I2C_DATA is Empty during transmitting + 7 + 1 + read-only + + + RBNE + I2C_DATA is not Empty during receiving + 6 + 1 + read-only + + + STPDET + STOP condition detected in slave mode + 4 + 1 + read-only + + + ADD10SEND + Header of 10-bit address is sent in master mode + 3 + 1 + read-only + + + BTC + Byte transmission completed + 2 + 1 + read-only + + + ADDSEND + Address is sent in master mode or received and matches in slave mode + 1 + 1 + read-only + + + SBSEND + START condition sent out in master mode + 0 + 1 + read-only + + + + + STAT1 + STAT1 + Transfer status register 1 + 0x18 + 0x10 + read-only + 0x0000 + + + PECV + Packet Error Checking Value that calculated by hardware when PEC is enabled + 8 + 8 + + + DUMODF + Dual Flag in slave mode + 7 + 1 + + + HSTSMB + SMBus Host Header detected in slave mode + 6 + 1 + + + DEFSMB + Default address of SMBusDevice + 5 + 1 + + + RXGC + General call address (00h) received + 4 + 1 + + + TR + Whether the I2C is a transmitter or a receiver + 2 + 1 + + + I2CBSY + Busy flag + 1 + 1 + + + MASTER + A flag indicating whether I2C block is in master or slave mode + 0 + 1 + + + + + CKCFG + CKCFG + Clock configure register + 0x1C + 0x10 + read-write + 0x0000 + + + FAST + I2C speed selection in master mode + 15 + 1 + + + DTCY + Duty cycle in fast mode + 14 + 1 + + + CLKC + I2C Clock control in master mode + 0 + 12 + + + + + RT + RT + Rise time register + 0x20 + 0x10 + read-write + 0x0002 + + + RISETIME + Maximum rise time in master mode + 0 + 6 + + + + + + + I2C1 + 0x40005800 + + I2C1_EV + 52 + + + I2C1_ER + 53 + + + + + ECLIC + Enhanced Core Local Interrupt Controller + ECLIC + 0xD2000000 + + 0x0 + 0xFFFF + registers + + + + CLICCFG + CLICCFG + cliccfg Register + 0x0 + 0x08 + read-write + 0x00 + + + NLBITS + NLBITS + 1 + 4 + + + + + CLICINFO + CLICINFO + clicinfo Register + 0x04 + 0x20 + read-only + 0x00000000 + + + NUM_INTERRUPT + NUM_INTERRUPT + 0 + 13 + + + VERSION + VERSION + 13 + 8 + + + CLICINTCTLBITS + CLICINTCTLBITS + 21 + 4 + + + + + MTH + MTH + MTH Register + 0x0b + 0x08 + read-write + 0x00 + + + MTH + MTH + 0 + 8 + + + + + CLICINTIP_0 + CLICINTIP_0 + clicintip Register + 0x1000 + 0x08 + read-write + 0x00 + + + IP + IP + 0 + 1 + + + + + CLICINTIP_1 + CLICINTIP_1 + clicintip Register + 0x1004 + 0x08 + read-write + 0x00 + + + IP + IP + 0 + 1 + + + + + CLICINTIP_2 + CLICINTIP_2 + clicintip Register + 0x1008 + 0x08 + read-write + 0x00 + + + IP + IP + 0 + 1 + + + + + CLICINTIP_3 + CLICINTIP_3 + clicintip Register + 0x100C + 0x08 + read-write + 0x00 + + + IP + IP + 0 + 1 + + + + + CLICINTIP_4 + CLICINTIP_4 + clicintip Register + 0x1010 + 0x08 + read-write + 0x00 + + + IP + IP + 0 + 1 + + + + + CLICINTIP_5 + CLICINTIP_5 + clicintip Register + 0x1014 + 0x08 + read-write + 0x00 + + + IP + IP + 0 + 1 + + + + + CLICINTIP_6 + CLICINTIP_6 + clicintip Register + 0x1018 + 0x08 + read-write + 0x00 + + + IP + IP + 0 + 1 + + + + + CLICINTIP_7 + CLICINTIP_7 + clicintip Register + 0x101C + 0x08 + read-write + 0x00 + + + IP + IP + 0 + 1 + + + + + CLICINTIP_8 + CLICINTIP_8 + clicintip Register + 0x1020 + 0x08 + read-write + 0x00 + + + IP + IP + 0 + 1 + + + + + CLICINTIP_9 + CLICINTIP_9 + clicintip Register + 0x1024 + 0x08 + read-write + 0x00 + + + IP + IP + 0 + 1 + + + + + CLICINTIP_10 + CLICINTIP_10 + clicintip Register + 0x1028 + 0x08 + read-write + 0x00 + + + IP + IP + 0 + 1 + + + + + CLICINTIP_11 + CLICINTIP_11 + clicintip Register + 0x102C + 0x08 + read-write + 0x00 + + + IP + IP + 0 + 1 + + + + + CLICINTIP_12 + CLICINTIP_12 + clicintip Register + 0x1030 + 0x08 + read-write + 0x00 + + + IP + IP + 0 + 1 + + + + + CLICINTIP_13 + CLICINTIP_13 + clicintip Register + 0x1034 + 0x08 + read-write + 0x00 + + + IP + IP + 0 + 1 + + + + + CLICINTIP_14 + CLICINTIP_14 + clicintip Register + 0x1038 + 0x08 + read-write + 0x00 + + + IP + IP + 0 + 1 + + + + + CLICINTIP_15 + CLICINTIP_15 + clicintip Register + 0x103C + 0x08 + read-write + 0x00 + + + IP + IP + 0 + 1 + + + + + CLICINTIP_16 + CLICINTIP_16 + clicintip Register + 0x1040 + 0x08 + read-write + 0x00 + + + IP + IP + 0 + 1 + + + + + CLICINTIP_17 + CLICINTIP_17 + clicintip Register + 0x1044 + 0x08 + read-write + 0x00 + + + IP + IP + 0 + 1 + + + + + CLICINTIP_18 + CLICINTIP_18 + clicintip Register + 0x1048 + 0x08 + read-write + 0x00 + + + IP + IP + 0 + 1 + + + + + CLICINTIP_19 + CLICINTIP_19 + clicintip Register + 0x104C + 0x08 + read-write + 0x00 + + + IP + IP + 0 + 1 + + + + + CLICINTIP_20 + CLICINTIP_20 + clicintip Register + 0x1050 + 0x08 + read-write + 0x00 + + + IP + IP + 0 + 1 + + + + + CLICINTIP_21 + CLICINTIP_21 + clicintip Register + 0x1054 + 0x08 + read-write + 0x00 + + + IP + IP + 0 + 1 + + + + + CLICINTIP_22 + CLICINTIP_22 + clicintip Register + 0x1058 + 0x08 + read-write + 0x00 + + + IP + IP + 0 + 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SHV + SHV + 0 + 1 + + + TRIG + TRIG + 1 + 2 + + + + + CLICINTATTR_83 + CLICINTIE_83 + clicintattr Register + 0x114E + 0x08 + read-write + 0x00 + + + SHV + SHV + 0 + 1 + + + TRIG + TRIG + 1 + 2 + + + + + CLICINTATTR_84 + CLICINTIE_84 + clicintattr Register + 0x1152 + 0x08 + read-write + 0x00 + + + SHV + SHV + 0 + 1 + + + TRIG + TRIG + 1 + 2 + + + + + CLICINTATTR_85 + CLICINTIE_85 + clicintattr Register + 0x1156 + 0x08 + read-write + 0x00 + + + SHV + SHV + 0 + 1 + + + TRIG + TRIG + 1 + 2 + + + + + CLICINTATTR_86 + CLICINTIE_86 + clicintattr Register + 0x115A + 0x08 + read-write + 0x00 + + + SHV + SHV + 0 + 1 + + + TRIG + TRIG + 1 + 2 + + + + + + CLICINTCTL_0 + CLICINTCTL_0 + clicintctl Register + 0x1003 + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_1 + CLICINTCTL_1 + clicintctl Register + 0x1007 + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_2 + CLICINTCTL_2 + clicintctl Register + 0x100B + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_3 + CLICINTCTL_3 + clicintctl Register + 0x100F + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_4 + CLICINTCTL_4 + clicintctl Register + 0x1013 + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_5 + CLICINTCTL_5 + clicintctl Register + 0x1017 + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_6 + CLICINTCTL_6 + clicintctl Register + 0x101B + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_7 + CLICINTCTL_7 + clicintctl Register + 0x101F + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_8 + CLICINTCTL_8 + clicintctl Register + 0x1023 + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_9 + CLICINTCTL_9 + clicintctl Register + 0x1027 + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_10 + CLICINTCTL_10 + clicintctl Register + 0x102B + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_11 + CLICINTCTL_11 + clicintctl Register + 0x102F + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_12 + CLICINTCTL_12 + clicintctl Register + 0x1033 + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_13 + CLICINTCTL_13 + clicintctl Register + 0x1037 + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_14 + CLICINTCTL_14 + clicintctl Register + 0x103B + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_15 + CLICINTCTL_15 + clicintctl Register + 0x103F + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_16 + CLICINTCTL_16 + clicintctl Register + 0x1043 + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_17 + CLICINTCTL_17 + clicintctl Register + 0x1047 + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_18 + CLICINTCTL_18 + clicintctl Register + 0x104B + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_19 + CLICINTCTL_19 + clicintctl Register + 0x104F + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_20 + CLICINTCTL_20 + clicintctl Register + 0x1053 + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_21 + CLICINTCTL_21 + clicintctl Register + 0x1057 + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_22 + CLICINTCTL_22 + clicintctl Register + 0x105B + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_23 + CLICINTCTL_23 + clicintctl Register + 0x105F + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_24 + CLICINTCTL_24 + clicintctl Register + 0x1063 + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_25 + CLICINTCTL_25 + clicintctl Register + 0x1067 + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_26 + CLICINTCTL_26 + clicintctl Register + 0x106B + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_27 + CLICINTCTL_27 + clicintctl Register + 0x106F + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_28 + CLICINTCTL_28 + clicintctl Register + 0x1073 + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_29 + CLICINTCTL_29 + clicintctl Register + 0x1077 + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_30 + CLICINTCTL_30 + clicintctl Register + 0x107B + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_31 + CLICINTCTL_31 + clicintctl Register + 0x107F + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_32 + CLICINTCTL_32 + clicintctl Register + 0x1083 + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_33 + CLICINTCTL_33 + clicintctl Register + 0x1087 + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_34 + CLICINTCTL_34 + clicintctl Register + 0x108B + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_35 + CLICINTCTL_35 + clicintctl Register + 0x108F + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_36 + CLICINTCTL_36 + clicintctl Register + 0x1093 + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_37 + CLICINTCTL_37 + clicintctl Register + 0x1097 + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_38 + CLICINTCTL_38 + clicintctl Register + 0x109B + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_39 + CLICINTCTL_39 + clicintctl Register + 0x109F + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_40 + CLICINTCTL_40 + clicintctl Register + 0x10A3 + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_41 + CLICINTCTL_41 + clicintctl Register + 0x10A7 + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_42 + CLICINTCTL_42 + clicintctl Register + 0x10AB + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_43 + CLICINTCTL_43 + clicintctl Register + 0x10AF + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_44 + CLICINTCTL_44 + clicintctl Register + 0x10B3 + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_45 + CLICINTCTL_45 + clicintctl Register + 0x10B7 + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_46 + CLICINTCTL_46 + clicintctl Register + 0x10BB + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_47 + CLICINTCTL_47 + clicintctl Register + 0x10BF + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_48 + CLICINTCTL_48 + clicintctl Register + 0x10C3 + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_49 + CLICINTCTL_49 + clicintctl Register + 0x10C7 + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_50 + CLICINTCTL_50 + clicintctl Register + 0x10CB + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_51 + CLICINTCTL_51 + clicintctl Register + 0x10CF + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_52 + CLICINTCTL_52 + clicintctl Register + 0x10D3 + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_53 + CLICINTCTL_53 + clicintctl Register + 0x10D7 + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_54 + CLICINTCTL_54 + clicintctl Register + 0x10DB + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_55 + CLICINTCTL_55 + clicintctl Register + 0x10DF + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_56 + CLICINTCTL_56 + clicintctl Register + 0x10E3 + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_57 + CLICINTCTL_57 + clicintctl Register + 0x10E7 + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_58 + CLICINTCTL_58 + clicintctl Register + 0x10EB + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_59 + CLICINTCTL_59 + clicintctl Register + 0x10EF + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_60 + CLICINTCTL_60 + clicintctl Register + 0x10F3 + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_61 + CLICINTCTL_61 + clicintctl Register + 0x10F7 + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_62 + CLICINTCTL_62 + clicintctl Register + 0x10FB + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_63 + CLICINTCTL_63 + clicintctl Register + 0x10FF + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_64 + CLICINTCTL_64 + clicintctl Register + 0x1103 + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_65 + CLICINTCTL_65 + clicintctl Register + 0x1107 + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_66 + CLICINTCTL_66 + clicintctl Register + 0x110B + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_67 + CLICINTCTL_67 + clicintctl Register + 0x110F + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_68 + CLICINTCTL_68 + clicintctl Register + 0x1113 + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_69 + CLICINTCTL_69 + clicintctl Register + 0x1117 + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_70 + CLICINTCTL_70 + clicintctl Register + 0x111B + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_71 + CLICINTCTL_71 + clicintctl Register + 0x111F + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_72 + CLICINTCTL_72 + clicintctl Register + 0x1123 + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_73 + CLICINTCTL_73 + clicintctl Register + 0x1127 + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_74 + CLICINTCTL_74 + clicintctl Register + 0x112B + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_75 + CLICINTCTL_75 + clicintctl Register + 0x112F + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_76 + CLICINTCTL_76 + clicintctl Register + 0x1133 + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_77 + CLICINTCTL_77 + clicintctl Register + 0x1137 + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_78 + CLICINTCTL_78 + clicintctl Register + 0x113B + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_79 + CLICINTCTL_79 + clicintctl Register + 0x113F + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_80 + CLICINTCTL_80 + clicintctl Register + 0x1143 + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_81 + CLICINTCTL_81 + clicintctl Register + 0x1147 + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_82 + CLICINTCTL_82 + clicintctl Register + 0x114B + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_83 + CLICINTCTL_83 + clicintctl Register + 0x114F + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_84 + CLICINTCTL_84 + clicintctl Register + 0x1153 + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_85 + CLICINTCTL_85 + clicintctl Register + 0x1157 + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_86 + CLICINTCTL_86 + clicintctl Register + 0x115B + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + + + + PMU + Power management unit + PMU + 0x40007000 + + 0x0 + 0x400 + registers + + + + CTL + CTL + power control register + 0x00 + 0x20 + read-write + 0x00000000 + + + BKPWEN + Backup Domain Write Enable + 8 + 1 + + + LVDT + Low Voltage Detector Threshold + 5 + 3 + + + LVDEN + Low Voltage Detector Enable + 4 + 1 + + + STBRST + Standby Flag Reset + 3 + 1 + + + WURST + Wakeup Flag Reset + 2 + 1 + + + STBMOD + Standby Mode + 1 + 1 + + + LDOLP + LDO Low Power Mode + 0 + 1 + + + + + CS + CS + power control/status register + 0x04 + 0x20 + 0x00000000 + + + WUPEN + Enable WKUP pin + 8 + 1 + read-write + + + LVDF + Low Voltage Detector Status Flag + 2 + 1 + read-only + + + STBF + Standby flag + 1 + 1 + read-only + + + WUF + Wakeup flag + 0 + 1 + read-only + + + + + + + RCU + Reset and clock unit + RCU + 0x40021000 + + 0x0 + 0x400 + registers + + + RCU + 24 + + + + CTL + CTL + Control register + 0x0 + 0x20 + 0x00000083 + + + IRC8MEN + Internal 8MHz RC oscillator Enable + 0 + 1 + read-write + + + IRC8MSTB + IRC8M Internal 8MHz RC Oscillator stabilization Flag + 1 + 1 + read-only + + + IRC8MADJ + Internal 8MHz RC Oscillator clock trim adjust value + 3 + 5 + read-write + + + IRC8MCALIB + Internal 8MHz RC Oscillator calibration value register + 8 + 8 + read-only + + + HXTALEN + External High Speed oscillator Enable + 16 + 1 + read-write + + + HXTALSTB + External crystal oscillator (HXTAL) clock stabilization flag + 17 + 1 + read-only + + + HXTALBPS + External crystal oscillator (HXTAL) clock bypass mode enable + 18 + 1 + read-write + + + CKMEN + HXTAL Clock Monitor Enable + 19 + 1 + read-write + + + PLLEN + PLL enable + 24 + 1 + read-write + + + PLLSTB + PLL Clock Stabilization Flag + 25 + 1 + read-only + + + PLL1EN + PLL1 enable + 26 + 1 + read-write + + + PLL1STB + PLL1 Clock Stabilization Flag + 27 + 1 + read-only + + + PLL2EN + PLL2 enable + 28 + 1 + read-write + + + PLL2STB + PLL2 Clock Stabilization Flag + 29 + 1 + read-only + + + + + CFG0 + CFG0 + Clock configuration register 0 + (RCU_CFG0) + 0x04 + 0x20 + 0x00000000 + + + SCS + System clock switch + 0 + 2 + read-write + + + SCSS + System clock switch status + 2 + 2 + read-only + + + AHBPSC + AHB prescaler selection + 4 + 4 + read-write + + + APB1PSC + APB1 prescaler selection + 8 + 3 + read-write + + + APB2PSC + APB2 prescaler selection + 11 + 3 + read-write + + + ADCPSC_1_0 + ADC clock prescaler selection + 14 + 2 + read-write + + + PLLSEL + PLL Clock Source Selection + 16 + 1 + read-write + + + PREDV0_LSB + The LSB of PREDV0 division factor + 17 + 1 + read-write + + + PLLMF_3_0 + The PLL clock multiplication factor + 18 + 4 + read-write + + + USBFSPSC + USBFS clock prescaler selection + 22 + 2 + read-write + + + CKOUT0SEL + CKOUT0 Clock Source Selection + 24 + 4 + read-write + + + ADCPSC_2 + Bit 2 of ADCPSC + 28 + 1 + read-write + + + PLLMF_4 + Bit 4 of PLLMF + 29 + 1 + read-write + + + + + INT + INT + Clock interrupt register + (RCU_INT) + 0x08 + 0x20 + 0x00000000 + + + IRC40KSTBIF + IRC40K stabilization interrupt flag + 0 + 1 + read-only + + + LXTALSTBIF + LXTAL stabilization interrupt flag + 1 + 1 + read-only + + + IRC8MSTBIF + IRC8M stabilization interrupt flag + 2 + 1 + read-only + + + HXTALSTBIF + HXTAL stabilization interrupt flag + 3 + 1 + read-only + + + PLLSTBIF + PLL stabilization interrupt flag + 4 + 1 + read-only + + + PLL1STBIF + PLL1 stabilization interrupt flag + 5 + 1 + read-only + + + PLL2STBIF + PLL2 stabilization interrupt flag + 6 + 1 + read-only + + + CKMIF + HXTAL Clock Stuck Interrupt Flag + 7 + 1 + read-only + + + IRC40KSTBIE + IRC40K Stabilization interrupt enable + 8 + 1 + read-write + + + LXTALSTBIE + LXTAL Stabilization Interrupt Enable + 9 + 1 + read-write + + + IRC8MSTBIE + IRC8M Stabilization Interrupt Enable + 10 + 1 + read-write + + + HXTALSTBIE + HXTAL Stabilization Interrupt Enable + 11 + 1 + read-write + + + PLLSTBIE + PLL Stabilization Interrupt Enable + 12 + 1 + read-write + + + PLL1STBIE + PLL1 Stabilization Interrupt Enable + 13 + 1 + read-write + + + PLL2STBIE + PLL2 Stabilization Interrupt Enable + 14 + 1 + read-write + + + IRC40KSTBIC + IRC40K Stabilization Interrupt Clear + 16 + 1 + write-only + + + LXTALSTBIC + LXTAL Stabilization Interrupt Clear + 17 + 1 + write-only + + + IRC8MSTBIC + IRC8M Stabilization Interrupt Clear + 18 + 1 + write-only + + + HXTALSTBIC + HXTAL Stabilization Interrupt Clear + 19 + 1 + write-only + + + PLLSTBIC + PLL stabilization Interrupt Clear + 20 + 1 + write-only + + + PLL1STBIC + PLL1 stabilization Interrupt Clear + 21 + 1 + write-only + + + PLL2STBIC + PLL2 stabilization Interrupt Clear + 22 + 1 + write-only + + + CKMIC + HXTAL Clock Stuck Interrupt Clear + 23 + 1 + write-only + + + + + + APB2RST + APB2RST + APB2 reset register + (RCU_APB2RST) + 0x0C + 0x20 + read-write + 0x00000000 + + + AFRST + Alternate function I/O reset + 0 + 1 + + + PARST + GPIO port A reset + 2 + 1 + + + PBRST + GPIO port B reset + 3 + 1 + + + PCRST + GPIO port C reset + 4 + 1 + + + PDRST + GPIO port D reset + 5 + 1 + + + PERST + GPIO port E reset + 6 + 1 + + + ADC0RST + ADC0 reset + 9 + 1 + + + ADC1RST + ADC1 reset + 10 + 1 + + + TIMER0RST + Timer 0 reset + 11 + 1 + + + SPI0RST + SPI0 reset + 12 + 1 + + + USART0RST + USART0 Reset + 14 + 1 + + + + + APB1RST + APB1RST + APB1 reset register + (RCU_APB1RST) + 0x10 + 0x20 + read-write + 0x00000000 + + + TIMER1RST + TIMER1 timer reset + 0 + 1 + + + TIMER2RST + TIMER2 timer reset + 1 + 1 + + + TIMER3RST + TIMER3 timer reset + 2 + 1 + + + TIMER4RST + TIMER4 timer reset + 3 + 1 + + + TIMER5RST + TIMER5 timer reset + 4 + 1 + + + TIMER6RST + TIMER6 timer reset + 5 + 1 + + + WWDGTRST + Window watchdog timer reset + 11 + 1 + + + SPI1RST + SPI1 reset + 14 + 1 + + + SPI2RST + SPI2 reset + 15 + 1 + + + USART1RST + USART1 reset + 17 + 1 + + + USART2RST + USART2 reset + 18 + 1 + + + UART3RST + UART3 reset + 19 + 1 + + + UART4RST + UART4 reset + 20 + 1 + + + I2C0RST + I2C0 reset + 21 + 1 + + + I2C1RST + I2C1 reset + 22 + 1 + + + CAN0RST + CAN0 reset + 25 + 1 + + + CAN1RST + CAN1 reset + 26 + 1 + + + BKPIRST + Backup interface reset + 27 + 1 + + + PMURST + Power control reset + 28 + 1 + + + DACRST + DAC reset + 29 + 1 + + + + + + AHBEN + AHBEN + AHB enable register + 0x14 + 0x20 + read-write + 0x00000014 + + + DMA0EN + DMA0 clock enable + 0 + 1 + + + DMA1EN + DMA1 clock enable + 1 + 1 + + + SRAMSPEN + SRAM interface clock enable when sleep mode + 2 + 1 + + + FMCSPEN + FMC clock enable when sleep mode + 4 + 1 + + + CRCEN + CRC clock enable + 6 + 1 + + + EXMCEN + EXMC clock enable + 8 + 1 + + + USBFSEN + USBFS clock enable + 12 + 1 + + + + + APB2EN + APB2EN + APB2 clock enable register + (RCU_APB2EN) + 0x18 + 0x20 + read-write + 0x00000000 + + + AFEN + Alternate function IO clock enable + 0 + 1 + + + PAEN + GPIO port A clock enable + 2 + 1 + + + PBEN + GPIO port B clock enable + 3 + 1 + + + PCEN + GPIO port C clock enable + 4 + 1 + + + PDEN + GPIO port D clock enable + 5 + 1 + + + PEEN + GPIO port E clock enable + 6 + 1 + + + ADC0EN + ADC0 clock enable + 9 + 1 + + + ADC1EN + ADC1 clock enable + 10 + 1 + + + TIMER0EN + TIMER0 clock enable + 11 + 1 + + + SPI0EN + SPI0 clock enable + 12 + 1 + + + USART0EN + USART0 clock enable + 14 + 1 + + + + + + APB1EN + APB1EN + APB1 clock enable register + (RCU_APB1EN) + 0x1C + 0x20 + read-write + 0x00000000 + + + TIMER1EN + TIMER1 timer clock enable + 0 + 1 + + + TIMER2EN + TIMER2 timer clock enable + 1 + 1 + + + TIMER3EN + TIMER3 timer clock enable + 2 + 1 + + + TIMER4EN + TIMER4 timer clock enable + 3 + 1 + + + TIMER5EN + TIMER5 timer clock enable + 4 + 1 + + + TIMER6EN + TIMER6 timer clock enable + 5 + 1 + + + WWDGTEN + Window watchdog timer clock enable + 11 + 1 + + + SPI1EN + SPI1 clock enable + 14 + 1 + + + SPI2EN + SPI2 clock enable + 15 + 1 + + + USART1EN + USART1 clock enable + 17 + 1 + + + USART2EN + USART2 clock enable + 18 + 1 + + + UART3EN + UART3 clock enable + 19 + 1 + + + UART4EN + UART4 clock enable + 20 + 1 + + + I2C0EN + I2C0 clock enable + 21 + 1 + + + I2C1EN + I2C1 clock enable + 22 + 1 + + + CAN0EN + CAN0 clock enable + 25 + 1 + + + CAN1EN + CAN1 clock enable + 26 + 1 + + + BKPIEN + Backup interface clock enable + 27 + 1 + + + PMUEN + Power control clock enable + 28 + 1 + + + DACEN + DAC clock enable + 29 + 1 + + + + + + BDCTL + BDCTL + Backup domain control register + (RCU_BDCTL) + 0x20 + 0x20 + 0x00000018 + + + LXTALEN + LXTAL enable + 0 + 1 + read-write + + + LXTALSTB + External low-speed oscillator stabilization + 1 + 1 + read-only + + + LXTALBPS + LXTAL bypass mode enable + 2 + 1 + read-write + + + RTCSRC + RTC clock entry selection + 8 + 2 + read-write + + + RTCEN + RTC clock enable + 15 + 1 + read-write + + + BKPRST + Backup domain reset + 16 + 1 + read-write + + + + + RSTSCK + RSTSCK + Reset source /clock register + (RCU_RSTSCK) + 0x24 + 0x20 + 0x0C000000 + + + IRC40KEN + IRC40K enable + 0 + 1 + read-write + + + IRC40KSTB + IRC40K stabilization + 1 + 1 + read-only + + + RSTFC + Reset flag clear + 24 + 1 + read-write + + + EPRSTF + External PIN reset flag + 26 + 1 + read-only + + + PORRSTF + Power reset flag + 27 + 1 + read-only + + + SWRSTF + Software reset flag + 28 + 1 + read-only + + + FWDGTRSTF + Free Watchdog timer reset flag + 29 + 1 + read-only + + + WWDGTRSTF + Window watchdog timer reset flag + 30 + 1 + read-only + + + LPRSTF + Low-power reset flag + 31 + 1 + read-only + + + + + + AHBRST + AHBRST + AHB reset register + 0x28 + 0x20 + read-write + 0x00000000 + + + USBFSRST + USBFS reset + 12 + 1 + + + + + + CFG1 + CFG1 + Clock Configuration register 1 + 0x2C + 0x20 + read-write + 0x00000000 + + + PREDV0 + PREDV0 division factor + 0 + 4 + + + PREDV1 + PREDV1 division factor + 4 + 4 + + + PLL1MF + The PLL1 clock multiplication factor + 8 + 4 + + + PLL2MF + The PLL2 clock multiplication factor + 12 + 4 + + + PREDV0SEL + PREDV0 input Clock Source Selection + 16 + 1 + + + I2S1SEL + I2S1 Clock Source Selection + 17 + 1 + + + I2S2SEL + I2S2 Clock Source Selection + 18 + 1 + + + + + DSV + DSV + Deep sleep mode Voltage register + 0x34 + 0x20 + 0x00000000 + + + DSLPVS + Deep-sleep mode voltage select + 0 + 2 + read-write + + + + + + + + RTC + Real-time clock + RTC + 0x40002800 + + 0x0 + 0x400 + registers + + + RTC + 22 + + + RTC_Alarm + 60 + + + + INTEN + INTEN + RTC interrupt enable register + 0x0 + 0x20 + read-write + 0x00000000 + + + OVIE + Overflow interrupt enable + 2 + 1 + + + ALRMIE + Alarm interrupt enable + 1 + 1 + + + SCIE + Second interrupt + 0 + 1 + + + + + CTL + CTL + control register + 0x04 + 0x20 + read-write + 0x00000020 + + + LWOFF + Last write operation finished flag + 5 + 1 + + + CMF + Configuration mode flag + 4 + 1 + + + RSYNF + Registers synchronized flag + 3 + 1 + + + OVIF + Overflow interrupt flag + 2 + 1 + + + ALRMIF + Alarm interrupt flag + 1 + 1 + + + SCIF + Sencond interrupt flag + 0 + 1 + + + + + PSCH + PSCH + RTC prescaler high register + 0x08 + 0x20 + 0x00000000 + + + PSC + RTC prescaler value high + 0 + 4 + write + + + + + PSCL + PSCL + RTC prescaler low + register + 0x0C + 0x20 + 0x00008000 + + + PSC + RTC prescaler value low + 0 + 16 + write + + + + + DIVH + DIVH + RTC divider high register + 0x10 + 0x20 + read-only + 0x00000000 + + + DIV + RTC divider value high + 0 + 4 + + + + + DIVL + DIVL + RTC divider low register + 0x14 + 0x20 + read-only + 0x00008000 + + + DIV + RTC divider value low + 0 + 16 + + + + + CNTH + CNTH + RTC counter high register + 0x18 + 0x20 + read-write + 0x00000000 + + + CNT + RTC counter value high + 0 + 16 + + + + + CNTL + CNTL + RTC counter low register + 0x1C + 0x20 + read-write + 0x00000000 + + + CNT + RTC counter value low + 0 + 16 + + + + + ALRMH + ALRMH + Alarm high register + 0x20 + 0x20 + write + 0x0000FFFF + + + ALRM + Alarm value high + 0 + 16 + + + + + ALRML + ALRML + RTC alarm low register + 0x24 + 0x20 + write + 0x0000FFFF + + + ALRM + alarm value low + 0 + 16 + + + + + + + + SPI0 + Serial peripheral interface + SPI + 0x40013000 + + 0x0 + 0x400 + registers + + + SPI0 + 54 + + + + CTL0 + CTL0 + control register 0 + 0x0 + 0x10 + read-write + 0x0000 + + + BDEN + Bidirectional + enable + 15 + 1 + + + BDOEN + Bidirectional Transmit output enable + + 14 + 1 + + + CRCEN + CRC Calculation Enable + 13 + 1 + + + CRCNT + CRC Next Transfer + 12 + 1 + + + FF16 + Data frame format + 11 + 1 + + + RO + Receive only + 10 + 1 + + + SWNSSEN + NSS Software Mode Selection + 9 + 1 + + + SWNSS + NSS Pin Selection In NSS Software Mode + 8 + 1 + + + LF + LSB First Mode + 7 + 1 + + + SPIEN + SPI enable + 6 + 1 + + + PSC + Master Clock Prescaler Selection + 3 + 3 + + + MSTMOD + Master Mode Enable + 2 + 1 + + + CKPL + Clock polarity Selection + 1 + 1 + + + CKPH + Clock Phase Selection + 0 + 1 + + + + + CTL1 + CTL1 + control register 1 + 0x04 + 0x10 + read-write + 0x0000 + + + TBEIE + Tx buffer empty interrupt + enable + 7 + 1 + + + RBNEIE + RX buffer not empty interrupt + enable + 6 + 1 + + + ERRIE + Error interrupt enable + 5 + 1 + + + TMOD + SPI TI mode enable + 4 + 1 + + + NSSP + SPI NSS pulse mode enable + 3 + 1 + + + NSSDRV + Drive NSS Output + 2 + 1 + + + DMATEN + Transmit Buffer DMA Enable + 1 + 1 + + + DMAREN + Rx buffer DMA enable + 0 + 1 + + + + + STAT + STAT + status register + 0x08 + 0x10 + 0x0002 + + + FERR + Format error + 8 + 1 + read-only + + + TRANS + Transmitting On-going Bit + 7 + 1 + read-only + + + RXORERR + Reception Overrun Error Bit + 6 + 1 + read-only + + + CONFERR + SPI Configuration error + 5 + 1 + read-only + + + CRCERR + SPI CRC Error Bit + 4 + 1 + read-write + + + TXURERR + Transmission underrun error bit + 3 + 1 + read-only + + + I2SCH + I2S channel side + 2 + 1 + read-only + + + TBE + Transmit Buffer Empty + 1 + 1 + read-only + + + RBNE + Receive Buffer Not Empty + 0 + 1 + read-only + + + + + DATA + DATA + data register + 0x0C + 0x10 + read-write + 0x0000 + + + SPI_DATA + Data transfer register + 0 + 16 + + + + + CRCPOLY + CRCPOLY + CRC polynomial register + 0x10 + 0x10 + read-write + 0x0007 + + + CRCPOLY + CRC polynomial value + 0 + 16 + + + + + RCRC + RCRC + RX CRC register + 0x14 + 0x10 + read-only + 0x0000 + + + RCRC + RX CRC value + 0 + 16 + + + + + TCRC + TCRC + TX CRC register + 0x18 + 0x10 + read-only + 0x0000 + + + TCRC + Tx CRC value + 0 + 16 + + + + + I2SCTL + I2SCTL + I2S control register + 0x1C + 0x10 + read-write + 0x0000 + + + I2SSEL + I2S mode selection + 11 + 1 + + + I2SEN + I2S Enable + 10 + 1 + + + I2SOPMOD + I2S operation mode + 8 + 2 + + + PCMSMOD + PCM frame synchronization mode + 7 + 1 + + + I2SSTD + I2S standard selection + 4 + 2 + + + CKPL + Idle state clock polarity + 3 + 1 + + + DTLEN + Data length + 1 + 2 + + + CHLEN + Channel length (number of bits per audio + channel) + 0 + 1 + + + + + I2SPSC + I2SPSC + I2S prescaler register + 0x20 + 0x10 + read-write + 0x0002 + + + MCKOEN + I2S_MCK output enable + 9 + 1 + + + OF + Odd factor for the + prescaler + 8 + 1 + + + DIV + Dividing factor for the prescaler + 0 + 8 + + + + + + + SPI1 + 0x40003800 + + SPI1 + 55 + + + + SPI2 + 0x40003C00 + + SPI2 + 70 + + + + TIMER0 + Advanced-timers + TIMER + 0x40012c00 + + 0x0 + 0x400 + registers + + + TIMER0_BRK + 43 + + + TIMER0_UP + 44 + + + TIMER0_TRG_CMT + 45 + + + TIMER0_Channel + 46 + + + + CTL0 + CTL0 + control register 0 + 0x0 + 0x10 + read-write + 0x0000 + + + CKDIV + Clock division + 8 + 2 + + + ARSE + Auto-reload shadow enable + 7 + 1 + + + CAM + Counter aligns mode + selection + 5 + 2 + + + DIR + Direction + 4 + 1 + + + SPM + Single pulse mode + 3 + 1 + + + UPS + Update source + 2 + 1 + + + UPDIS + Update disable + 1 + 1 + + + CEN + Counter enable + 0 + 1 + + + + + CTL1 + CTL1 + control register 1 + 0x04 + 0x10 + read-write + 0x0000 + + + ISO3 + Idle state of channel 3 output + 14 + 1 + + + ISO2N + Idle state of channel 2 complementary output + 13 + 1 + + + ISO2 + Idle state of channel 2 output + 12 + 1 + + + ISO1N + Idle state of channel 1 complementary output + 11 + 1 + + + ISO1 + Idle state of channel 1 output + 10 + 1 + + + ISO0N + Idle state of channel 0 complementary output + 9 + 1 + + + ISO0 + Idle state of channel 0 output + 8 + 1 + + + TI0S + Channel 0 trigger input selection + 7 + 1 + + + MMC + Master mode control + 4 + 3 + + + DMAS + DMA request source selection + 3 + 1 + + + CCUC + Commutation control shadow register update control + 2 + 1 + + + CCSE + Commutation control shadow enable + 0 + 1 + + + + + SMCFG + SMCFG + slave mode configuration register + 0x08 + 0x10 + read-write + 0x0000 + + + ETP + External trigger polarity + 15 + 1 + + + SMC1 + Part of SMC for enable External clock mode1 + 14 + 1 + + + ETPSC + External trigger prescaler + 12 + 2 + + + ETFC + External trigger filter control + 8 + 4 + + + MSM + Master/Slave mode + 7 + 1 + + + TRGS + Trigger selection + 4 + 3 + + + SMC + Slave mode selection + 0 + 3 + + + + + DMAINTEN + DMAINTEN + DMA/Interrupt enable register + 0x0C + 0x10 + read-write + 0x0000 + + + TRGDEN + Trigger DMA request enable + 14 + 1 + + + CMTDEN + Commutation DMA request enable + 13 + 1 + + + CH3DEN + Channel 3 capture/compare DMA request enable + 12 + 1 + + + CH2DEN + Channel 2 capture/compare DMA request enable + 11 + 1 + + + CH1DEN + Channel 1 capture/compare DMA request enable + 10 + 1 + + + CH0DEN + Channel 0 capture/compare DMA request enable + 9 + 1 + + + UPDEN + Update DMA request enable + 8 + 1 + + + BRKIE + Break interrupt enable + 7 + 1 + + + TRGIE + Trigger interrupt enable + 6 + 1 + + + CMTIE + commutation interrupt enable + 5 + 1 + + + CH3IE + Channel 3 capture/compare interrupt enable + 4 + 1 + + + CH2IE + Channel 2 capture/compare interrupt enable + 3 + 1 + + + CH1IE + Channel 1 capture/compare interrupt enable + 2 + 1 + + + CH0IE + Channel 0 capture/compare interrupt enable + 1 + 1 + + + UPIE + Update interrupt enable + 0 + 1 + + + + + INTF + INTF + Interrupt flag register + 0x10 + 0x10 + read-write + 0x0000 + + + CH3OF + Channel 3 over capture flag + 12 + 1 + + + CH2OF + Channel 2 over capture flag + 11 + 1 + + + CH1OF + Channel 1 over capture flag + 10 + 1 + + + CH0OF + Channel 0 over capture flag + 9 + 1 + + + BRKIF + Break interrupt flag + 7 + 1 + + + TRGIF + Trigger interrupt flag + 6 + 1 + + + CMTIF + Channel commutation interrupt flag + 5 + 1 + + + CH3IF + Channel 3 capture/compare interrupt flag + 4 + 1 + + + CH2IF + Channel 2 capture/compare interrupt flag + 3 + 1 + + + CH1IF + Channel 1 capture/compare interrupt flag + 2 + 1 + + + CH0IF + Channel 0 capture/compare interrupt flag + 1 + 1 + + + UPIF + Update interrupt flag + 0 + 1 + + + + + SWEVG + SWEVG + Software event generation register + 0x14 + 0x10 + write-only + 0x0000 + + + BRKG + Break event generation + 7 + 1 + + + TRGG + Trigger event generation + 6 + 1 + + + CMTG + Channel commutation event generation + 5 + 1 + + + CH3G + Channel 3 capture or compare event generation + 4 + 1 + + + CH2G + Channel 2 capture or compare event generation + 3 + 1 + + + CH1G + Channel 1 capture or compare event generation + 2 + 1 + + + CH0G + Channel 0 capture or compare event generation + 1 + 1 + + + UPG + Update event generation + 0 + 1 + + + + + CHCTL0_Output + CHCTL0_Output + Channel control register 0 (output + mode) + 0x18 + 0x10 + read-write + 0x0000 + + + CH1COMCEN + Channel 1 output compare clear enable + 15 + 1 + + + CH1COMCTL + Channel 1 compare output control + 12 + 3 + + + CH1COMSEN + Channel 1 output compare shadow enable + 11 + 1 + + + CH1COMFEN + Channel 1 output compare fast enable + 10 + 1 + + + CH1MS + Channel 1 mode selection + 8 + 2 + + + CH0COMCEN + Channel 0 output compare clear enable + 7 + 1 + + + CH0COMCTL + Channel 0 compare output control + 4 + 3 + + + CH0COMSEN + Channel 0 compare output shadow enable + 3 + 1 + + + CH0COMFEN + Channel 0 output compare fast enable + 2 + 1 + + + CH0MS + Channel 0 I/O mode selection + 0 + 2 + + + + + CHCTL0_Input + CHCTL0_Input + Channel control register 0 (input + mode) + CHCTL0_Output + 0x18 + 0x10 + read-write + 0x0000 + + + CH1CAPFLT + Channel 1 input capture filter control + 12 + 4 + + + CH1CAPPSC + Channel 1 input capture prescaler + 10 + 2 + + + CH1MS + Channel 1 mode selection + 8 + 2 + + + CH0CAPFLT + Channel 0 input capture filter control + 4 + 4 + + + CH0CAPPSC + Channel 0 input capture prescaler + 2 + 2 + + + CH0MS + Channel 0 mode selection + 0 + 2 + + + + + CHCTL1_Output + CHCTL1_Output + Channel control register 1 (output + mode) + 0x1C + 0x10 + read-write + 0x0000 + + + CH3COMCEN + Channel 3 output compare clear enable + 15 + 1 + + + CH3COMCTL + Channel 3 compare output control + 12 + 3 + + + CH3COMSEN + Channel 3 output compare shadow enable + 11 + 1 + + + CH3COMFEN + Channel 3 output compare fast enable + 10 + 1 + + + CH3MS + Channel 3 mode selection + 8 + 2 + + + CH2COMCEN + Channel 2 output compare clear enable + 7 + 1 + + + CH2COMCTL + Channel 2 compare output control + 4 + 3 + + + CH2COMSEN + Channel 2 compare output shadow enable + 3 + 1 + + + CH2COMFEN + Channel 2 output compare fast enable + 2 + 1 + + + CH2MS + Channel 2 I/O mode selection + 0 + 2 + + + + + CHCTL1_Input + CHCTL1_Input + Channel control register 1 (input + mode) + CHCTL1_Output + 0x1C + 0x10 + read-write + 0x0000 + + + CH3CAPFLT + Channel 3 input capture filter control + 12 + 4 + + + CH3CAPPSC + Channel 3 input capture prescaler + 10 + 2 + + + CH3MS + Channel 3 mode selection + 8 + 2 + + + CH2CAPFLT + Channel 2 input capture filter control + 4 + 4 + + + CH2CAPPSC + Channel 2 input capture prescaler + 2 + 2 + + + CH2MS + Channel 2 mode selection + 0 + 2 + + + + + CHCTL2 + CHCTL2 + Channel control register 2 + 0x20 + 0x10 + read-write + 0x0000 + + + CH3P + Channel 3 capture/compare function polarity + 13 + 1 + + + CH3EN + Channel 3 capture/compare function enable + 12 + 1 + + + CH2NP + Channel 2 complementary output polarity + 11 + 1 + + + CH2NEN + Channel 2 complementary output enable + 10 + 1 + + + CH2P + Channel 2 capture/compare function polarity + 9 + 1 + + + CH2EN + Channel 2 capture/compare function enable + 8 + 1 + + + CH1NP + Channel 1 complementary output polarity + 7 + 1 + + + CH1NEN + Channel 1 complementary output enable + 6 + 1 + + + CH1P + Channel 1 capture/compare function polarity + 5 + 1 + + + CH1EN + Channel 1 capture/compare function enable + 4 + 1 + + + CH0NP + Channel 0 complementary output polarity + 3 + 1 + + + CH0NEN + Channel 0 complementary output enable + 2 + 1 + + + CH0P + Channel 0 capture/compare function polarity + 1 + 1 + + + CH0EN + Channel 0 capture/compare function enable + 0 + 1 + + + + + CNT + CNT + counter + 0x24 + 0x10 + read-write + 0x0000 + + + CNT + current counter value + 0 + 16 + + + + + PSC + PSC + prescaler + 0x28 + 0x10 + read-write + 0x0000 + + + PSC + Prescaler value of the counter clock + 0 + 16 + + + + + CAR + CAR + Counter auto reload register + 0x2C + 0x10 + read-write + 0x0000 + + + CARL + Counter auto reload value + 0 + 16 + + + + + CREP + CREP + Counter repetition register + 0x30 + 0x10 + read-write + 0x0000 + + + CREP + Counter repetition value + 0 + 8 + + + + + CH0CV + CH0CV + Channel 0 capture/compare value register + 0x34 + 0x10 + read-write + 0x0000 + + + CH0VAL + Capture or compare value of channel0 + 0 + 16 + + + + + CH1CV + CH1CV + Channel 1 capture/compare value register + 0x38 + 0x10 + read-write + 0x0000 + + + CH1VAL + Capture or compare value of channel1 + 0 + 16 + + + + + CH2CV + CH2CV + Channel 2 capture/compare value register + 0x3C + 0x10 + read-write + 0x0000 + + + CH2VAL + Capture or compare value of channel 2 + 0 + 16 + + + + + CH3CV + CH3CV + Channel 3 capture/compare value register + 0x40 + 0x10 + read-write + 0x0000 + + + CH3VAL + Capture or compare value of channel 3 + 0 + 16 + + + + + CCHP + CCHP + channel complementary protection register + 0x44 + 0x10 + read-write + 0x0000 + + + POEN + Primary output enable + 15 + 1 + + + OAEN + Output automatic enable + 14 + 1 + + + BRKP + Break polarity + 13 + 1 + + + BRKEN + Break enable + 12 + 1 + + + ROS + Run mode off-state configure + 11 + 1 + + + IOS + Idle mode off-state configure + 10 + 1 + + + PROT + Complementary register protect control + 8 + 2 + + + DTCFG + Dead time configure + 0 + 8 + + + + + DMACFG + DMACFG + DMA configuration register + 0x48 + 0x10 + read-write + 0x0000 + + + DMATC + DMA transfer count + 8 + 5 + + + DMATA + DMA transfer access start address + 0 + 5 + + + + + DMATB + DMATB + DMA transfer buffer register + 0x4C + 0x10 + read-write + 0x0000 + + + DMATB + DMA transfer buffer + 0 + 16 + + + + + + + TIMER1 + General-purpose-timers + TIMER + 0x40000000 + + 0x0 + 0x400 + registers + + + TIMER1 + 47 + + + + CTL0 + CTL0 + control register 0 + 0x0 + 0x10 + read-write + 0x0000 + + + CKDIV + Clock division + 8 + 2 + + + ARSE + Auto-reload shadow enable + 7 + 1 + + + CAM + Counter aligns mode selection + 5 + 2 + + + DIR + Direction + 4 + 1 + + + SPM + Single pulse mode + 3 + 1 + + + UPS + Update source + 2 + 1 + + + UPDIS + Update disable + 1 + 1 + + + CEN + Counter enable + 0 + 1 + + + + + CTL1 + CTL1 + control register 1 + 0x04 + 0x10 + read-write + 0x0000 + + + TI0S + Channel 0 trigger input selection + 7 + 1 + + + MMC + Master mode control + 4 + 3 + + + DMAS + DMA request source selection + 3 + 1 + + + + + SMCFG + SMCFG + slave mode control register + 0x08 + 0x10 + read-write + 0x0000 + + + ETP + External trigger polarity + 15 + 1 + + + SMC1 + Part of SMC for enable External clock mode1 + 14 + 1 + + + ETPSC + External trigger prescaler + 12 + 2 + + + ETFC + External trigger filter control + 8 + 4 + + + MSM + Master-slave mode + 7 + 1 + + + TRGS + Trigger selection + 4 + 3 + + + SMC + Slave mode control + 0 + 3 + + + + + DMAINTEN + DMAINTEN + DMA/Interrupt enable register + 0x0C + 0x10 + read-write + 0x0000 + + + TRGDEN + Trigger DMA request enable + 14 + 1 + + + CH3DEN + Channel 3 capture/compare DMA request enable + 12 + 1 + + + CH2DEN + Channel 2 capture/compare DMA request enable + 11 + 1 + + + CH1DEN + Channel 1 capture/compare DMA request enable + 10 + 1 + + + CH0DEN + Channel 0 capture/compare DMA request enable + 9 + 1 + + + UPDEN + Update DMA request enable + 8 + 1 + + + TRGIE + Trigger interrupt enable + 6 + 1 + + + CH3IE + Channel 3 capture/compare interrupt enable + 4 + 1 + + + CH2IE + Channel 2 capture/compare interrupt enable + 3 + 1 + + + CH1IE + Channel 1 capture/compare interrupt enable + 2 + 1 + + + CH0IE + Channel 0 capture/compare interrupt enable + 1 + 1 + + + UPIE + Update interrupt enable + 0 + 1 + + + + + INTF + INTF + interrupt flag register + 0x10 + 0x10 + read-write + 0x0000 + + + CH3OF + Channel 3 over capture flag + 12 + 1 + + + CH2OF + Channel 2 over capture flag + 11 + 1 + + + CH1OF + Channel 1 over capture flag + 10 + 1 + + + CH0OF + Channel 0 over capture flag + 9 + 1 + + + TRGIF + Trigger interrupt flag + 6 + 1 + + + CH3IF + Channel 3 capture/compare interrupt enable + 4 + 1 + + + CH2IF + Channel 2 capture/compare interrupt enable + 3 + 1 + + + CH1IF + Channel 1 capture/compare interrupt flag + 2 + 1 + + + CH0IF + Channel 0 capture/compare interrupt flag + 1 + 1 + + + UPIF + Update interrupt flag + 0 + 1 + + + + + SWEVG + SWEVG + event generation register + 0x14 + 0x10 + write-only + 0x0000 + + + TRGG + Trigger event generation + 6 + 1 + + + CH3G + Channel 3 capture or compare event generation + 4 + 1 + + + CH2G + Channel 2 capture or compare event generation + 3 + 1 + + + CH1G + Channel 1 capture or compare event generation + 2 + 1 + + + CH0G + Channel 0 capture or compare event generation + 1 + 1 + + + UPG + Update generation + 0 + 1 + + + + + CHCTL0_Output + CHCTL0_Output + Channel control register 0 (output + mode) + 0x18 + 0x10 + read-write + 0x0000 + + + CH1COMCEN + Channel 1 output compare clear enable + 15 + 1 + + + CH1COMCTL + Channel 1 compare output control + 12 + 3 + + + CH1COMSEN + Channel 1 output compare shadow enable + 11 + 1 + + + CH1COMFEN + Channel 1 output compare fast enable + 10 + 1 + + + CH1MS + Channel 1 mode selection + 8 + 2 + + + CH0COMCEN + Channel 0 output compare clear enable + 7 + 1 + + + CH0COMCTL + Channel 0 compare output control + 4 + 3 + + + CH0COMSEN + Channel 0 compare output shadow enable + 3 + 1 + + + CH0COMFEN + Channel 0 output compare fast enable + 2 + 1 + + + CH0MS + Channel 0 I/O mode selection + 0 + 2 + + + + + CHCTL0_Input + CHCTL0_Input + Channel control register 0 (input + mode) + CHCTL0_Output + 0x18 + 0x10 + read-write + 0x00000000 + + + CH1CAPFLT + Channel 1 input capture filter control + 12 + 4 + + + CH1CAPPSC + Channel 1 input capture prescaler + 10 + 2 + + + CH1MS + Channel 1 mode selection + 8 + 2 + + + CH0CAPFLT + Channel 0 input capture filter control + 4 + 4 + + + CH0CAPPSC + Channel 0 input capture prescaler + 2 + 2 + + + CH0MS + Channel 0 mode selection + 0 + 2 + + + + + CHCTL1_Output + CHCTL1_Output + Channel control register 1 (output mode) + 0x1C + 0x10 + read-write + 0x0000 + + + CH3COMCEN + Channel 3 output compare clear enable + 15 + 1 + + + CH3COMCTL + Channel 3 compare output control + 12 + 3 + + + CH3COMSEN + Channel 3 output compare shadow enable + 11 + 1 + + + CH3COMFEN + Channel 3 output compare fast enable + 10 + 1 + + + CH3MS + Channel 3 mode selection + 8 + 2 + + + CH2COMCEN + Channel 2 output compare clear enable + 7 + 1 + + + CH2COMCTL + Channel 2 compare output control + 4 + 3 + + + CH2COMSEN + Channel 2 compare output shadow enable + 3 + 1 + + + CH2COMFEN + Channel 2 output compare fast enable + 2 + 1 + + + CH2MS + Channel 2 I/O mode selection + 0 + 2 + + + + + CHCTL1_Input + CHCTL1_Input + Channel control register 1 (input + mode) + CHCTL1_Output + 0x1C + 0x10 + read-write + 0x0000 + + + CH3CAPFLT + Channel 3 input capture filter control + 12 + 4 + + + CH3CAPPSC + Channel 3 input capture prescaler + 10 + 2 + + + CH3MS + Channel 3 mode selection + 8 + 2 + + + CH2CAPFLT + Channel 2 input capture filter control + 4 + 4 + + + CH2CAPPSC + Channel 2 input capture prescaler + 2 + 2 + + + CH2MS + Channel 2 mode selection + 0 + 2 + + + + + CHCTL2 + CHCTL2 + Channel control register 2 + 0x20 + 0x10 + read-write + 0x0000 + + + CH3P + Channel 3 capture/compare function polarity + 13 + 1 + + + CH3EN + Channel 3 capture/compare function enable + 12 + 1 + + + CH2P + Channel 2 capture/compare function polarity + 9 + 1 + + + CH2EN + Channel 2 capture/compare function enable + 8 + 1 + + + CH1P + Channel 1 capture/compare function polarity + 5 + 1 + + + CH1EN + Channel 1 capture/compare function enable + 4 + 1 + + + CH0P + Channel 0 capture/compare function polarity + 1 + 1 + + + CH0EN + Channel 0 capture/compare function enable + 0 + 1 + + + + + CNT + CNT + Counter register + 0x24 + 0x10 + read-write + 0x0000 + + + CNT + counter value + 0 + 16 + + + + + PSC + PSC + Prescaler register + 0x28 + 0x10 + read-write + 0x0000 + + + PSC + Prescaler value of the counter clock + 0 + 16 + + + + + CAR + CAR + Counter auto reload register + 0x2C + 0x10 + read-write + 0x0000 + + + CARL + Counter auto reload value + 0 + 16 + + + + + CH0CV + CH0CV + Channel 0 capture/compare value register + 0x34 + 0x20 + read-write + 0x00000000 + + + CH0VAL + Capture or compare value of channel 0 + 0 + 16 + + + + + CH1CV + CH1CV + Channel 1 capture/compare value register + 0x38 + 0x20 + read-write + 0x00000000 + + + CH1VAL + Capture or compare value of channel1 + 0 + 16 + + + + + CH2CV + CH2CV + Channel 2 capture/compare value register + 0x3C + 0x20 + read-write + 0x00000000 + + + CH2VAL + Capture or compare value of channel 2 + 0 + 16 + + + + + CH3CV + CH3CV + Channel 3 capture/compare value register + 0x40 + 0x20 + read-write + 0x00000000 + + + CH3VAL + Capture or compare value of channel 3 + 0 + 16 + + + + + DMACFG + DMACFG + DMA configuration register + 0x48 + 0x10 + read-write + 0x0000 + + + DMATC + DMA transfer count + 8 + 5 + + + DMATA + DMA transfer access start address + 0 + 5 + + + + + DMATB + DMATB + DMA transfer buffer register + 0x4C + 0x20 + read-write + 0x0000 + + + DMATB + DMA transfer buffer + 0 + 16 + + + + + + + TIMER2 + TIMER + 0x40000400 + + TIMER2 + 48 + + + + TIMER3 + TIMER + 0x40000800 + + TIMER3 + 49 + + + + TIMER4 + TIMER + 0x40000C00 + + TIMER4 + 69 + + + + TIMER5 + Basic-timers + TIMER + 0x40001000 + + 0x0 + 0x400 + registers + + + TIMER5 + 73 + + + + CTL0 + CTL0 + control register 0 + 0x0 + 0x10 + read-write + 0x0000 + + + ARSE + Auto-reload shadow enable + 7 + 1 + + + SPM + Single pulse mode + 3 + 1 + + + UPS + Update source + 2 + 1 + + + UPDIS + Update disable + 1 + 1 + + + CEN + Counter enable + 0 + 1 + + + + + CTL1 + CTL1 + control register 1 + 0x04 + 0x10 + read-write + 0x0000 + + + MMC + Master mode control + 4 + 3 + + + + + DMAINTEN + DMAINTEN + DMA/Interrupt enable register + 0x0C + 0x10 + read-write + 0x0000 + + + UPDEN + Update DMA request enable + 8 + 1 + + + UPIE + Update interrupt enable + 0 + 1 + + + + + INTF + INTF + Interrupt flag register + 0x10 + 0x10 + read-write + 0x0000 + + + UPIF + Update interrupt flag + 0 + 1 + + + + + SWEVG + SWEVG + event generation register + 0x14 + 0x10 + write-only + 0x0000 + + + UPG + Update generation + 0 + 1 + + + + + CNT + CNT + Counter register + 0x24 + 0x10 + read-write + 0x0000 + + + CNT + Low counter value + 0 + 16 + + + + + PSC + PSC + Prescaler register + 0x28 + 0x10 + read-write + 0x0000 + + + PSC + Prescaler value of the counter clock + 0 + 16 + + + + + CAR + CAR + Counter auto reload register + 0x2C + 0x10 + read-write + 0x0000 + + + CARL + Counter auto reload value + 0 + 16 + + + + + + + TIMER6 + TIMER + 0x40001400 + + TIMER6 + 74 + + + + + USART0 + Universal synchronous asynchronous receiver + transmitter + USART + 0x40013800 + + 0x0 + 0x400 + registers + + + USART0 + 56 + + + + STAT + STAT + Status register + 0x00 + 0x20 + 0x000000C0 + + + CTSF + CTS change flag + 9 + 1 + read-write + + + LBDF + LIN break detection flag + 8 + 1 + read-write + + + TBE + Transmit data buffer empty + 7 + 1 + read-only + + + TC + Transmission complete + 6 + 1 + read-write + + + RBNE + Read data buffer not empty + 5 + 1 + read-write + + + IDLEF + IDLE frame detected flag + 4 + 1 + read-only + + + ORERR + Overrun error + 3 + 1 + read-only + + + NERR + Noise error flag + 2 + 1 + read-only + + + FERR + Frame error flag + 1 + 1 + read-only + + + PERR + Parity error flag + 0 + 1 + read-only + + + + + DATA + DATA + Data register + 0x04 + 0x20 + read-write + 0x00000000 + + + DATA + Transmit or read data value + 0 + 9 + + + + + BAUD + BAUD + Baud rate register + 0x08 + 0x20 + read-write + 0x00000000 + + + INTDIV + Integer part of baud-rate divider + 4 + 12 + + + FRADIV + Fraction part of baud-rate divider + 0 + 4 + + + + + CTL0 + CTL0 + Control register 0 + 0x0C + 0x20 + read-write + 0x00000000 + + + UEN + USART enable + 13 + 1 + + + WL + Word length + 12 + 1 + + + WM + Wakeup method in mute mode + 11 + 1 + + + PCEN + Parity check function enable + 10 + 1 + + + PM + Parity mode + 9 + 1 + + + PERRIE + Parity error interrupt enable + 8 + 1 + + + TBEIE + Transmitter buffer empty interrupt enable + 7 + 1 + + + TCIE + Transmission complete interrupt enable + 6 + 1 + + + RBNEIE + Read data buffer not empty interrupt and overrun error interrupt enable + 5 + 1 + + + IDLEIE + IDLE line detected interrupt enable + 4 + 1 + + + TEN + Transmitter enable + 3 + 1 + + + REN + Receiver enable + 2 + 1 + + + RWU + Receiver wakeup from mute mode + 1 + 1 + + + SBKCMD + Send break command + 0 + 1 + + + + + CTL1 + CTL1 + Control register 1 + 0x10 + 0x20 + read-write + 0x00000000 + + + LMEN + LIN mode enable + 14 + 1 + + + STB + STOP bits length + 12 + 2 + + + CKEN + CK pin enable + 11 + 1 + + + CPL + Clock polarity + 10 + 1 + + + CPH + Clock phase + 9 + 1 + + + CLEN + CK Length + 8 + 1 + + + LBDIE + LIN break detection interrupt + enable + 6 + 1 + + + LBLEN + LIN break frame length + 5 + 1 + + + ADDR + Address of the USART + 0 + 4 + + + + + CTL2 + CTL2 + Control register 2 + 0x14 + 0x20 + read-write + 0x00000000 + + + CTSIE + CTS interrupt enable + 10 + 1 + + + CTSEN + CTS enable + 9 + 1 + + + RTSEN + RTS enable + 8 + 1 + + + DENT + DMA request enable for transmission + 7 + 1 + + + DENR + DMA request enable for reception + 6 + 1 + + + SCEN + Smartcard mode enable + 5 + 1 + + + NKEN + Smartcard NACK enable + 4 + 1 + + + HDEN + Half-duplex selection + 3 + 1 + + + IRLP + IrDA low-power + 2 + 1 + + + IREN + IrDA mode enable + 1 + 1 + + + ERRIE + Error interrupt enable + 0 + 1 + + + + + GP + GP + Guard time and prescaler + register + 0x18 + 0x20 + read-write + 0x00000000 + + + GUAT + Guard time value in Smartcard mode + 8 + 8 + + + PSC + Prescaler value + 0 + 8 + + + + + + + USART1 + 0x40004400 + + USART1 + 57 + + + + USART2 + 0x40004800 + + USART2 + 58 + + + + UART3 + Universal asynchronous receiver + transmitter + UART + 0x40004C00 + + 0x0 + 0x400 + registers + + + UART3 + 71 + + + + STAT + STAT + Status register + 0x00 + 0x20 + 0x000000C0 + + + LBDF + LIN break detection flag + 8 + 1 + read-write + + + TBE + Transmit data buffer empty + 7 + 1 + read-only + + + TC + Transmission complete + 6 + 1 + read-write + + + RBNE + Read data buffer not empty + 5 + 1 + read-write + + + IDLEF + IDLE frame detected flag + 4 + 1 + read-only + + + ORERR + Overrun error + 3 + 1 + read-only + + + NERR + Noise error flag + 2 + 1 + read-only + + + FERR + Frame error flag + 1 + 1 + read-only + + + PERR + Parity error flag + 0 + 1 + read-only + + + + + DATA + DATA + Data register + 0x04 + 0x20 + read-write + 0x00000000 + + + DATA + Transmit or read data value + 0 + 9 + + + + + BAUD + BAUD + Baud rate register + 0x08 + 0x20 + read-write + 0x00000000 + + + INTDIV + Integer part of baud-rate divider + 4 + 12 + + + FRADIV + Fraction part of baud-rate divider + 0 + 4 + + + + + CTL0 + CTL0 + Control register 0 + 0x0C + 0x20 + read-write + 0x00000000 + + + UEN + USART enable + 13 + 1 + + + WL + Word length + 12 + 1 + + + WM + Wakeup method in mute mode + 11 + 1 + + + PCEN + Parity check function enable + 10 + 1 + + + PM + Parity mode + 9 + 1 + + + PERRIE + Parity error interrupt enable + 8 + 1 + + + TBEIE + Transmitter buffer empty interrupt enable + 7 + 1 + + + TCIE + Transmission complete interrupt enable + 6 + 1 + + + RBNEIE + Read data buffer not empty interrupt and overrun error interrupt enable + 5 + 1 + + + IDLEIE + IDLE line detected interrupt enable + 4 + 1 + + + TEN + Transmitter enable + 3 + 1 + + + REN + Receiver enable + 2 + 1 + + + RWU + Receiver wakeup from mute mode + 1 + 1 + + + SBKCMD + Send break command + 0 + 1 + + + + + CTL1 + CTL1 + Control register 1 + 0x10 + 0x20 + read-write + 0x00000000 + + + LMEN + LIN mode enable + 14 + 1 + + + STB + STOP bits length + 12 + 2 + + + LBDIE + LIN break detection interrupt + enable + 6 + 1 + + + LBLEN + LIN break frame length + 5 + 1 + + + ADDR + Address of the USART + 0 + 4 + + + + + CTL2 + CTL2 + Control register 2 + 0x14 + 0x20 + read-write + 0x00000000 + + + DENT + DMA request enable for transmission + 7 + 1 + + + DENR + DMA request enable for reception + 6 + 1 + + + HDEN + Half-duplex selection + 3 + 1 + + + IRLP + IrDA low-power + 2 + 1 + + + IREN + IrDA mode enable + 1 + 1 + + + ERRIE + Error interrupt enable + 0 + 1 + + + + + GP + GP + Guard time and prescaler + register + 0x18 + 0x20 + read-write + 0x00000000 + + + PSC + Prescaler value + 0 + 8 + + + + + + + UART4 + 0x40005000 + + UART4 + 72 + + + + + USBFS_GLOBAL + USB full speed global registers + USBFS + 0x50000000 + + 0x0 + 0x400 + registers + + + USBFS_WKUP + 61 + + + USBFS + 86 + + + + GOTGCS + GOTGCS + Global OTG control and status register + (USBFS_GOTGCS) + 0x0 + 0x20 + 0x00000800 + + + SRPS + SRP success + 0 + 1 + read-only + + + SRPREQ + SRP request + 1 + 1 + read-write + + + HNPS + Host success + 8 + 1 + read-only + + + HNPREQ + HNP request + 9 + 1 + read-write + + + HHNPEN + Host HNP enable + 10 + 1 + read-write + + + DHNPEN + Device HNP enabled + 11 + 1 + read-write + + + IDPS + ID pin status + 16 + 1 + read-only + + + DI + Debounce interval + 17 + 1 + read-only + + + ASV + A-session valid + 18 + 1 + read-only + + + BSV + B-session valid + 19 + 1 + read-only + + + + + GOTGINTF + GOTGINTF + Global OTG interrupt flag register + (USBFS_GOTGINTF) + 0x04 + 0x20 + read-write + 0x00000000 + + + SESEND + Session end + 2 + 1 + + + SRPEND + Session request success status + change + 8 + 1 + + + HNPEND + HNP end + 9 + 1 + + + HNPDET + Host negotiation request detected + 17 + 1 + + + ADTO + A-device timeout + 18 + 1 + + + DF + Debounce finish + 19 + 1 + + + + + GAHBCS + GAHBCS + Global AHB control and status register + (USBFS_GAHBCS) + 0x08 + 0x20 + read-write + 0x00000000 + + + GINTEN + Global interrupt enable + 0 + 1 + + + TXFTH + Tx FIFO threshold + 7 + 1 + + + PTXFTH + Periodic Tx FIFO threshold + 8 + 1 + + + + + GUSBCS + GUSBCS + Global USB control and status register + (USBFS_GUSBCSR) + 0x0C + 0x20 + 0x00000A80 + + + TOC + Timeout calibration + 0 + 3 + read-write + + + SRPCEN + SRP capability enable + 8 + 1 + read-write + + + HNPCEN + HNP capability enable + 9 + 1 + read-write + + + UTT + USB turnaround time + 10 + 4 + read-write + + + FHM + Force host mode + 29 + 1 + read-write + + + FDM + Force device mode + 30 + 1 + read-write + + + + + GRSTCTL + GRSTCTL + Global reset control register (USBFS_GRSTCTL) + 0x10 + 0x20 + 0x80000000 + + + CSRST + Core soft reset + 0 + 1 + read-write + + + HCSRST + HCLK soft reset + 1 + 1 + read-write + + + HFCRST + Host frame counter reset + 2 + 1 + read-write + + + RXFF + RxFIFO flush + 4 + 1 + read-write + + + TXFF + TxFIFO flush + 5 + 1 + read-write + + + TXFNUM + TxFIFO number + 6 + 5 + read-write + + + + + GINTF + GINTF + Global interrupt flag register (USBFS_GINTF) + 0x14 + 0x20 + 0x04000021 + + + COPM + Current operation mode + 0 + 1 + read-only + + + MFIF + Mode fault interrupt flag + 1 + 1 + read-write + + + OTGIF + OTG interrupt flag + 2 + 1 + read-only + + + SOF + Start of frame + 3 + 1 + read-write + + + RXFNEIF + RxFIFO non-empty interrupt flag + 4 + 1 + read-only + + + NPTXFEIF + Non-periodic TxFIFO empty interrupt flag + 5 + 1 + read-only + + + GNPINAK + Global Non-Periodic IN NAK effective + 6 + 1 + read-only + + + GONAK + Global OUT NAK effective + 7 + 1 + read-only + + + ESP + Early suspend + 10 + 1 + read-write + + + SP + USB suspend + 11 + 1 + read-write + + + RST + USB reset + 12 + 1 + read-write + + + ENUMF + Enumeration finished + 13 + 1 + read-write + + + ISOOPDIF + Isochronous OUT packet dropped + interrupt + 14 + 1 + read-write + + + EOPFIF + End of periodic frame + interrupt flag + 15 + 1 + read-write + + + IEPIF + IN endpoint interrupt flag + 18 + 1 + read-only + + + OEPIF + OUT endpoint interrupt flag + 19 + 1 + read-only + + + ISOINCIF + Isochronous IN transfer Not Complete Interrupt Flag + 20 + 1 + read-write + + + PXNCIF_ISOONCIF + periodic transfer not complete interrupt flag(Host + mode)/isochronous OUT transfer not complete interrupt flag(Device + mode) + 21 + 1 + read-write + + + HPIF + Host port interrupt flag + 24 + 1 + read-only + + + HCIF + Host channels interrupt flag + 25 + 1 + read-only + + + PTXFEIF + Periodic TxFIFO empty interrupt flag + 26 + 1 + read-only + + + IDPSC + ID pin status change + 28 + 1 + read-write + + + DISCIF + Disconnect interrupt flag + 29 + 1 + read-write + + + SESIF + Session interrupt flag + 30 + 1 + read-write + + + WKUPIF + Wakeup interrupt flag + 31 + 1 + read-write + + + + + GINTEN + GINTEN + Global interrupt enable register + (USBFS_GINTEN) + 0x18 + 0x20 + 0x00000000 + + + MFIE + Mode fault interrupt + enable + 1 + 1 + read-write + + + OTGIE + OTG interrupt enable + 2 + 1 + read-write + + + SOFIE + Start of frame interrupt enable + 3 + 1 + read-write + + + RXFNEIE + Receive FIFO non-empty + interrupt enable + 4 + 1 + read-write + + + NPTXFEIE + Non-periodic TxFIFO empty + interrupt enable + 5 + 1 + read-write + + + GNPINAKIE + Global non-periodic IN NAK effective interrupt enable + 6 + 1 + read-write + + + GONAKIE + Global OUT NAK effective + interrupt enable + 7 + 1 + read-write + + + ESPIE + Early suspend interrupt enable + 10 + 1 + read-write + + + SPIE + USB suspend interrupt enable + 11 + 1 + read-write + + + RSTIE + USB reset interrupt enable + 12 + 1 + read-write + + + ENUMFIE + Enumeration finish interrupt enable + 13 + 1 + read-write + + + ISOOPDIE + Isochronous OUT packet dropped interrupt enable + 14 + 1 + read-write + + + EOPFIE + End of periodic frame interrupt enable + 15 + 1 + read-write + + + IEPIE + IN endpoints interrupt enable + 18 + 1 + read-write + + + OEPIE + OUT endpoints interrupt enable + 19 + 1 + read-write + + + ISOINCIE + isochronous IN transfer not complete + interrupt enable + 20 + 1 + read-write + + + PXNCIE_ISOONCIE + periodic transfer not compelete Interrupt enable(Host + mode)/isochronous OUT transfer not complete interrupt enable(Device + mode) + 21 + 1 + read-write + + + HPIE + Host port interrupt enable + 24 + 1 + read-only + + + HCIE + Host channels interrupt enable + 25 + 1 + read-write + + + PTXFEIE + Periodic TxFIFO empty interrupt enable + 26 + 1 + read-write + + + IDPSCIE + ID pin status change interrupt enable + 28 + 1 + read-write + + + DISCIE + Disconnect interrupt enable + 29 + 1 + read-write + + + SESIE + Session interrupt enable + 30 + 1 + read-write + + + WKUPIE + Wakeup interrupt enable + 31 + 1 + read-write + + + + + GRSTATR_Device + GRSTATR_Device + Global Receive status read(Device + mode) + 0x1C + 0x20 + read-only + 0x00000000 + + + EPNUM + Endpoint number + 0 + 4 + + + BCOUNT + Byte count + 4 + 11 + + + DPID + Data PID + 15 + 2 + + + RPCKST + Recieve packet status + 17 + 4 + + + + + GRSTATR_Host + GRSTATR_Host + Global Receive status read(Host + mode) + GRSTATR_Device + 0x1C + 0x20 + read-only + 0x00000000 + + + CNUM + Channel number + 0 + 4 + + + BCOUNT + Byte count + 4 + 11 + + + DPID + Data PID + 15 + 2 + + + RPCKST + Reivece packet status + 17 + 4 + + + + + + GRSTATP_Device + GRSTATP_Device + Global Receive status pop(Device + mode) + 0x20 + 0x20 + read-only + 0x00000000 + + + EPNUM + Endpoint number + 0 + 4 + + + BCOUNT + Byte count + 4 + 11 + + + DPID + Data PID + 15 + 2 + + + RPCKST + Recieve packet status + 17 + 4 + + + + + GRSTATP_Host + GRSTATP_Host + Global Receive status pop(Host + mode) + GRSTATP_Device + 0x20 + 0x20 + read-only + 0x00000000 + + + CNUM + Channel number + 0 + 4 + + + BCOUNT + Byte count + 4 + 11 + + + DPID + Data PID + 15 + 2 + + + RPCKST + Reivece packet status + 17 + 4 + + + + + GRFLEN + GRFLEN + Global Receive FIFO size register + (USBFS_GRFLEN) + 0x24 + 0x20 + read-write + 0x00000200 + + + RXFD + Rx FIFO depth + 0 + 16 + + + + + HNPTFLEN + HNPTFLEN + Host non-periodic transmit FIFO length register + (Host mode) + 0x28 + 0x20 + read-write + 0x02000200 + + + HNPTXRSAR + host non-periodic transmit Tx RAM start + address + 0 + 16 + + + HNPTXFD + host non-periodic TxFIFO depth + 16 + 16 + + + + + DIEP0TFLEN + DIEP0TFLEN + Device IN endpoint 0 transmit FIFO length + (Device mode) + HNPTFLEN + 0x28 + 0x20 + read-write + 0x02000200 + + + IEP0TXFD + in endpoint 0 Tx FIFO depth + 16 + 16 + + + IEP0TXRSAR + in endpoint 0 Tx RAM start address + 0 + 16 + + + + + HNPTFQSTAT + HNPTFQSTAT + Host non-periodic transmit FIFO/queue + status register (HNPTFQSTAT) + 0x2C + 0x20 + read-only + 0x00080200 + + + NPTXFS + Non-periodic TxFIFO space + 0 + 16 + + + NPTXRQS + Non-periodic transmit request queue + space + 16 + 8 + + + NPTXRQTOP + Top of the non-periodic transmit request + queue + 24 + 7 + + + + + GCCFG + GCCFG + Global core configuration register (USBFS_GCCFG) + 0x38 + 0x20 + read-write + 0x00000000 + + + PWRON + Power on + 16 + 1 + + + VBUSACEN + The VBUS A-device Comparer enable + 18 + 1 + + + VBUSBCEN + The VBUS B-device Comparer enable + 19 + 1 + + + SOFOEN + SOF output enable + 20 + 1 + + + VBUSIG + VBUS ignored + 21 + 1 + + + + + CID + CID + core ID register + 0x3C + 0x20 + read-write + 0x00001000 + + + CID + Core ID + 0 + 32 + + + + + HPTFLEN + HPTFLEN + Host periodic transmit FIFO length register (HPTFLEN) + 0x100 + 0x20 + read-write + 0x02000600 + + + HPTXFSAR + Host periodic TxFIFO start + address + 0 + 16 + + + HPTXFD + Host periodic TxFIFO depth + 16 + 16 + + + + + DIEP1TFLEN + DIEP1TFLEN + device IN endpoint transmit FIFO size + register (DIEP1TFLEN) + 0x104 + 0x20 + read-write + 0x02000400 + + + IEPTXRSAR + IN endpoint FIFO transmit RAM start + address + 0 + 16 + + + IEPTXFD + IN endpoint TxFIFO depth + 16 + 16 + + + + + DIEP2TFLEN + DIEP2TFLEN + device IN endpoint transmit FIFO size + register (DIEP2TFLEN) + 0x108 + 0x20 + read-write + 0x02000400 + + + IEPTXRSAR + IN endpoint FIFO transmit RAM start + address + 0 + 16 + + + IEPTXFD + IN endpoint TxFIFO depth + 16 + 16 + + + + + DIEP3TFLEN + DIEP3TFLEN + device IN endpoint transmit FIFO size + register (FS_DIEP3TXFLEN) + 0x10C + 0x20 + read-write + 0x02000400 + + + IEPTXRSAR + IN endpoint FIFO4 transmit RAM start + address + 0 + 16 + + + IEPTXFD + IN endpoint TxFIFO depth + 16 + 16 + + + + + + + + USBFS_HOST + USB on the go full speed host + USBFS + 0x50000400 + + 0x0 + 0x400 + registers + + + + HCTL + HCTL + host configuration register + (HCTL) + 0x00 + 0x20 + 0x00000000 + + + CLKSEL + clock select for USB clock + 0 + 2 + read-write + + + + + HFT + HFT + Host frame interval + register + 0x04 + 0x20 + read-write + 0x0000BB80 + + + FRI + Frame interval + 0 + 16 + + + + + HFINFR + HFINFR + FS host frame number/frame time + remaining register (HFINFR) + 0x08 + 0x20 + read-only + 0xBB800000 + + + FRNUM + Frame number + 0 + 16 + + + FRT + Frame remaining time + 16 + 16 + + + + + HPTFQSTAT + HPTFQSTAT + Host periodic transmit FIFO/queue + status register (HPTFQSTAT) + 0x10 + 0x20 + 0x00080200 + + + PTXFS + Periodic transmit data FIFO space + available + 0 + 16 + read-only + + + PTXREQS + Periodic transmit request queue space + available + 16 + 8 + read-only + + + PTXREQT + Top of the periodic transmit request + queue + 24 + 8 + read-only + + + + + HACHINT + HACHINT + Host all channels interrupt + register + 0x14 + 0x20 + read-only + 0x00000000 + + + HACHINT + Host all channel interrupts + 0 + 8 + + + + + HACHINTEN + HACHINTEN + host all channels interrupt mask + register + 0x18 + 0x20 + read-write + 0x00000000 + + + CINTEN + Channel interrupt enable + 0 + 8 + + + + + HPCS + HPCS + Host port control and status register (USBFS_HPCS) + 0x40 + 0x20 + 0x00000000 + + + PCST + Port connect status + 0 + 1 + read-only + + + PCD + Port connect detected + 1 + 1 + read-write + + + PE + Port enable + 2 + 1 + read-write + + + PEDC + Port enable/disable change + 3 + 1 + read-write + + + PREM + Port resume + 6 + 1 + read-write + + + PSP + Port suspend + 7 + 1 + read-write + + + PRST + Port reset + 8 + 1 + read-write + + + PLST + Port line status + 10 + 2 + read-only + + + PP + Port power + 12 + 1 + read-write + + + PS + Port speed + 17 + 2 + read-only + + + + + HCH0CTL + HCH0CTL + host channel-0 characteristics + register (HCH0CTL) + 0x100 + 0x20 + read-write + 0x00000000 + + + MPL + Maximum packet size + 0 + 11 + + + EPNUM + Endpoint number + 11 + 4 + + + EPDIR + Endpoint direction + 15 + 1 + + + LSD + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + DAR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CDIS + Channel disable + 30 + 1 + + + CEN + Channel enable + 31 + 1 + + + + + HCH1CTL + HCH1CTL + host channel-1 characteristics + register (HCH1CTL) + 0x120 + 0x20 + read-write + 0x00000000 + + + MPL + Maximum packet size + 0 + 11 + + + EPNUM + Endpoint number + 11 + 4 + + + EPDIR + Endpoint direction + 15 + 1 + + + LSD + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + DAR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CDIS + Channel disable + 30 + 1 + + + CEN + Channel enable + 31 + 1 + + + + + HCH2CTL + HCH2CTL + host channel-2 characteristics + register (HCH2CTL) + 0x140 + 0x20 + read-write + 0x00000000 + + + MPL + Maximum packet size + 0 + 11 + + + EPNUM + Endpoint number + 11 + 4 + + + EPDIR + Endpoint direction + 15 + 1 + + + LSD + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + DAR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CDIS + Channel disable + 30 + 1 + + + CEN + Channel enable + 31 + 1 + + + + + HCH3CTL + HCH3CTL + host channel-3 characteristics + register (HCH3CTL) + 0x160 + 0x20 + read-write + 0x00000000 + + + MPL + Maximum packet size + 0 + 11 + + + EPNUM + Endpoint number + 11 + 4 + + + EPDIR + Endpoint direction + 15 + 1 + + + LSD + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + DAR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CDIS + Channel disable + 30 + 1 + + + CEN + Channel enable + 31 + 1 + + + + + HCH4CTL + HCH4CTL + host channel-4 characteristics + register (HCH4CTL) + 0x180 + 0x20 + read-write + 0x00000000 + + + MPL + Maximum packet size + 0 + 11 + + + EPNUM + Endpoint number + 11 + 4 + + + EPDIR + Endpoint direction + 15 + 1 + + + LSD + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + DAR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CDIS + Channel disable + 30 + 1 + + + CEN + Channel enable + 31 + 1 + + + + + HCH5CTL + HCH5CTL + host channel-5 characteristics + register (HCH5CTL) + 0x1A0 + 0x20 + read-write + 0x00000000 + + + MPL + Maximum packet size + 0 + 11 + + + EPNUM + Endpoint number + 11 + 4 + + + EPDIR + Endpoint direction + 15 + 1 + + + LSD + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + DAR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CDIS + Channel disable + 30 + 1 + + + CEN + Channel enable + 31 + 1 + + + + + HCH6CTL + HCH6CTL + host channel-6 characteristics + register (HCH6CTL) + 0x1C0 + 0x20 + read-write + 0x00000000 + + + MPL + Maximum packet size + 0 + 11 + + + EPNUM + Endpoint number + 11 + 4 + + + EPDIR + Endpoint direction + 15 + 1 + + + LSD + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + DAR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CDIS + Channel disable + 30 + 1 + + + CEN + Channel enable + 31 + 1 + + + + + HCH7CTL + HCH7CTL + host channel-7 characteristics + register (HCH7CTL) + 0x1E0 + 0x20 + read-write + 0x00000000 + + + MPL + Maximum packet size + 0 + 11 + + + EPNUM + Endpoint number + 11 + 4 + + + EPDIR + Endpoint direction + 15 + 1 + + + LSD + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + DAR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CDIS + Channel disable + 30 + 1 + + + CEN + Channel enable + 31 + 1 + + + + + HCH0INTF + HCH0INTF + host channel-0 interrupt register + (USBFS_HCHxINTF) + 0x108 + 0x20 + read-write + 0x00000000 + + + TF + Transfer finished + 0 + 1 + + + CH + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + USBER + USB bus error + 7 + 1 + + + BBER + Babble error + 8 + 1 + + + REQOVR + Request queue overrun + 9 + 1 + + + DTER + Data toggle error + 10 + 1 + + + + + HCH1INTF + HCH1INTF + host channel-1 interrupt register + (HCH1INTF) + 0x128 + 0x20 + read-write + 0x00000000 + + + TF + Transfer finished + 0 + 1 + + + CH + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + USBER + USB bus error + 7 + 1 + + + BBER + Babble error + 8 + 1 + + + REQOVR + Request queue overrun + 9 + 1 + + + DTER + Data toggle error + 10 + 1 + + + + + HCH2INTF + HCH2INTF + host channel-2 interrupt register + (HCH2INTF) + 0x148 + 0x20 + read-write + 0x00000000 + + + TF + Transfer finished + 0 + 1 + + + CH + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + USBER + USB bus error + 7 + 1 + + + BBER + Babble error + 8 + 1 + + + REQOVR + Request queue overrun + 9 + 1 + + + DTER + Data toggle error + 10 + 1 + + + + + HCH3INTF + HCH3INTF + host channel-3 interrupt register + (HCH3INTF) + 0x168 + 0x20 + read-write + 0x00000000 + + + TF + Transfer finished + 0 + 1 + + + CH + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + USBER + USB bus error + 7 + 1 + + + BBER + Babble error + 8 + 1 + + + REQOVR + Request queue overrun + 9 + 1 + + + DTER + Data toggle error + 10 + 1 + + + + + HCH4INTF + HCH4INTF + host channel-4 interrupt register + (HCH4INTF) + 0x188 + 0x20 + read-write + 0x00000000 + + + TF + Transfer finished + 0 + 1 + + + CH + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + USBER + USB bus error + 7 + 1 + + + BBER + Babble error + 8 + 1 + + + REQOVR + Request queue overrun + 9 + 1 + + + DTER + Data toggle error + 10 + 1 + + + + + HCH5INTF + HCH5INTF + host channel-5 interrupt register + (HCH5INTF) + 0x1A8 + 0x20 + read-write + 0x00000000 + + + TF + Transfer finished + 0 + 1 + + + CH + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + USBER + USB bus error + 7 + 1 + + + BBER + Babble error + 8 + 1 + + + REQOVR + Request queue overrun + 9 + 1 + + + DTER + Data toggle error + 10 + 1 + + + + + HCH6INTF + HCH6INTF + host channel-6 interrupt register + (HCH6INTF) + 0x1C8 + 0x20 + read-write + 0x00000000 + + + TF + Transfer finished + 0 + 1 + + + CH + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + USBER + USB bus error + 7 + 1 + + + BBER + Babble error + 8 + 1 + + + REQOVR + Request queue overrun + 9 + 1 + + + DTER + Data toggle error + 10 + 1 + + + + + HCH7INTF + HCH7INTF + host channel-7 interrupt register + (HCH7INTF) + 0x1E8 + 0x20 + read-write + 0x00000000 + + + TF + Transfer finished + 0 + 1 + + + CH + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + USBER + USB bus error + 7 + 1 + + + BBER + Babble error + 8 + 1 + + + REQOVR + Request queue overrun + 9 + 1 + + + DTER + Data toggle error + 10 + 1 + + + + + HCH0INTEN + HCH0INTEN + host channel-0 interrupt enable register + (HCH0INTEN) + 0x10C + 0x20 + read-write + 0x00000000 + + + TFIE + Transfer completed interrupt enable + 0 + 1 + + + CHIE + Channel halted interrupt enable + 1 + 1 + + + STALLIE + STALL interrupt enable + 3 + 1 + + + NAKIE + NAK interrupt enable + 4 + 1 + + + ACKIE + ACK interrupt enable + 5 + 1 + + + USBERIE + USB bus error interrupt enable + 7 + 1 + + + BBERIE + Babble error interrupt enable + 8 + 1 + + + REQOVRIE + request queue overrun interrupt enable + 9 + 1 + + + DTERIE + Data toggle error interrupt enable + 10 + 1 + + + + + HCH1INTEN + HCH1INTEN + host channel-1 interrupt enable register + (HCH1INTEN) + 0x12C + 0x20 + read-write + 0x00000000 + + + TFIE + Transfer completed interrupt enable + 0 + 1 + + + CHIE + Channel halted interrupt enable + 1 + 1 + + + STALLIE + STALL interrupt enable + 3 + 1 + + + NAKIE + NAK interrupt enable + 4 + 1 + + + ACKIE + ACK interrupt enable + 5 + 1 + + + USBERIE + USB bus error interrupt enable + 7 + 1 + + + BBERIE + Babble error interrupt enable + 8 + 1 + + + REQOVRIE + request queue overrun interrupt enable + 9 + 1 + + + DTERIE + Data toggle error interrupt enable + 10 + 1 + + + + + HCH2INTEN + HCH2INTEN + host channel-2 interrupt enable register + (HCH2INTEN) + 0x14C + 0x20 + read-write + 0x00000000 + + + TFIE + Transfer completed interrupt enable + 0 + 1 + + + CHIE + Channel halted interrupt enable + 1 + 1 + + + STALLIE + STALL interrupt enable + 3 + 1 + + + NAKIE + NAK interrupt enable + 4 + 1 + + + ACKIE + ACK interrupt enable + 5 + 1 + + + USBERIE + USB bus error interrupt enable + 7 + 1 + + + BBERIE + Babble error interrupt enable + 8 + 1 + + + REQOVRIE + request queue overrun interrupt enable + 9 + 1 + + + DTERIE + Data toggle error interrupt enable + 10 + 1 + + + + + HCH3INTEN + HCH3INTEN + host channel-3 interrupt enable register + (HCH3INTEN) + 0x16C + 0x20 + read-write + 0x00000000 + + + TFIE + Transfer completed interrupt enable + 0 + 1 + + + CHIE + Channel halted interrupt enable + 1 + 1 + + + STALLIE + STALL interrupt enable + 3 + 1 + + + NAKIE + NAK interrupt enable + 4 + 1 + + + ACKIE + ACK interrupt enable + 5 + 1 + + + USBERIE + USB bus error interrupt enable + 7 + 1 + + + BBERIE + Babble error interrupt enable + 8 + 1 + + + REQOVRIE + request queue overrun interrupt enable + 9 + 1 + + + DTERIE + Data toggle error interrupt enable + 10 + 1 + + + + + HCH4INTEN + HCH4INTEN + host channel-4 interrupt enable register + (HCH4INTEN) + 0x18C + 0x20 + read-write + 0x00000000 + + + TFIE + Transfer completed interrupt enable + 0 + 1 + + + CHIE + Channel halted interrupt enable + 1 + 1 + + + STALLIE + STALL interrupt enable + 3 + 1 + + + NAKIE + NAK interrupt enable + 4 + 1 + + + ACKIE + ACK interrupt enable + 5 + 1 + + + USBERIE + USB bus error interrupt enable + 7 + 1 + + + BBERIE + Babble error interrupt enable + 8 + 1 + + + REQOVRIE + request queue overrun interrupt enable + 9 + 1 + + + DTERIE + Data toggle error interrupt enable + 10 + 1 + + + + + HCH5INTEN + HCH5INTEN + host channel-5 interrupt enable register + (HCH5INTEN) + 0x1AC + 0x20 + read-write + 0x00000000 + + + TFIE + Transfer completed interrupt enable + 0 + 1 + + + CHIE + Channel halted interrupt enable + 1 + 1 + + + STALLIE + STALL interrupt enable + 3 + 1 + + + NAKIE + NAK interrupt enable + 4 + 1 + + + ACKIE + ACK interrupt enable + 5 + 1 + + + USBERIE + USB bus error interrupt enable + 7 + 1 + + + BBERIE + Babble error interrupt enable + 8 + 1 + + + REQOVRIE + request queue overrun interrupt enable + 9 + 1 + + + DTERIE + Data toggle error interrupt enable + 10 + 1 + + + + + HCH6INTEN + HCH6INTEN + host channel-6 interrupt enable register + (HCH6INTEN) + 0x1CC + 0x20 + read-write + 0x00000000 + + + TFIE + Transfer completed interrupt enable + 0 + 1 + + + CHIE + Channel halted interrupt enable + 1 + 1 + + + STALLIE + STALL interrupt enable + 3 + 1 + + + NAKIE + NAK interrupt enable + 4 + 1 + + + ACKIE + ACK interrupt enable + 5 + 1 + + + USBERIE + USB bus error interrupt enable + 7 + 1 + + + BBERIE + Babble error interrupt enable + 8 + 1 + + + REQOVRIE + request queue overrun interrupt enable + 9 + 1 + + + DTERIE + Data toggle error interrupt enable + 10 + 1 + + + + + HCH7INTEN + HCH7INTEN + host channel-7 interrupt enable register + (HCH7INTEN) + 0x1EC + 0x20 + read-write + 0x00000000 + + + TFIE + Transfer completed interrupt enable + 0 + 1 + + + CHIE + Channel halted interrupt enable + 1 + 1 + + + STALLIE + STALL interrupt enable + 3 + 1 + + + NAKIE + NAK interrupt enable + 4 + 1 + + + ACKIE + ACK interrupt enable + 5 + 1 + + + USBERIE + USB bus error interrupt enable + 7 + 1 + + + BBERIE + Babble error interrupt enable + 8 + 1 + + + REQOVRIE + request queue overrun interrupt enable + 9 + 1 + + + DTERIE + Data toggle error interrupt enable + 10 + 1 + + + + + HCH0LEN + HCH0LEN + host channel-0 transfer length + register + 0x110 + 0x20 + read-write + 0x00000000 + + + TLEN + Transfer length + 0 + 19 + + + PCNT + Packet count + 19 + 10 + + + DPID + Data PID + 29 + 2 + + + + + HCH1LEN + HCH1LEN + host channel-1 transfer length + register + 0x130 + 0x20 + read-write + 0x00000000 + + + TLEN + Transfer length + 0 + 19 + + + PCNT + Packet count + 19 + 10 + + + DPID + Data PID + 29 + 2 + + + + + HCH2LEN + HCH2LEN + host channel-2 transfer length + register + 0x150 + 0x20 + read-write + 0x00000000 + + + TLEN + Transfer length + 0 + 19 + + + PCNT + Packet count + 19 + 10 + + + DPID + Data PID + 29 + 2 + + + + + HCH3LEN + HCH3LEN + host channel-3 transfer length + register + 0x170 + 0x20 + read-write + 0x00000000 + + + TLEN + Transfer length + 0 + 19 + + + PCNT + Packet count + 19 + 10 + + + DPID + Data PID + 29 + 2 + + + + + HCH4LEN + HCH4LEN + host channel-4 transfer length + register + 0x190 + 0x20 + read-write + 0x00000000 + + + TLEN + Transfer length + 0 + 19 + + + PCNT + Packet count + 19 + 10 + + + DPID + Data PID + 29 + 2 + + + + + HCH5LEN + HCH5LEN + host channel-5 transfer length + register + 0x1B0 + 0x20 + read-write + 0x00000000 + + + TLEN + Transfer length + 0 + 19 + + + PCNT + Packet count + 19 + 10 + + + DPID + Data PID + 29 + 2 + + + + + HCH6LEN + HCH6LEN + host channel-6 transfer length + register + 0x1D0 + 0x20 + read-write + 0x00000000 + + + TLEN + Transfer length + 0 + 19 + + + PCNT + Packet count + 19 + 10 + + + DPID + Data PID + 29 + 2 + + + + + HCH7LEN + HCH7LEN + host channel-7 transfer length + register + 0x1F0 + 0x20 + read-write + 0x00000000 + + + TLEN + Transfer length + 0 + 19 + + + PCNT + Packet count + 19 + 10 + + + DPID + Data PID + 29 + 2 + + + + + + + USBFS_DEVICE + USB on the go full speed device + USBFS + 0x50000800 + + 0x00 + 0x400 + registers + + + + DCFG + DCFG + device configuration register + (DCFG) + 0x0 + 0x20 + read-write + 0x00000000 + + + DS + Device speed + 0 + 2 + + + NZLSOH + Non-zero-length status OUT + handshake + 2 + 1 + + + DAR + Device address + 4 + 7 + + + EOPFT + end of periodic frame time + 11 + 2 + + + + + DCTL + DCTL + device control register + (DCTL) + 0x04 + 0x20 + 0x00000000 + + + RWKUP + Remote wakeup + 0 + 1 + read-write + + + SD + Soft disconnect + 1 + 1 + read-write + + + GINS + Global IN NAK status + 2 + 1 + read-only + + + GONS + Global OUT NAK status + 3 + 1 + read-only + + + SGINAK + Set global IN NAK + 7 + 1 + write-only + + + CGINAK + Clear global IN NAK + 8 + 1 + write-only + + + SGONAK + Set global OUT NAK + 9 + 1 + write-only + + + CGONAK + Clear global OUT NAK + 10 + 1 + write-only + + + POIF + Power-on initialization flag + 11 + 1 + read-write + + + + + DSTAT + DSTAT + device status register + (DSTAT) + 0x08 + 0x20 + read-only + 0x00000000 + + + SPST + Suspend status + 0 + 1 + + + ES + Enumerated speed + 1 + 2 + + + FNRSOF + Frame number of the received + SOF + 8 + 14 + + + + + DIEPINTEN + DIEPINTEN + device IN endpoint common interrupt + mask register (DIEPINTEN) + 0x10 + 0x20 + read-write + 0x00000000 + + + TFEN + Transfer finished interrupt + enable + 0 + 1 + + + EPDISEN + Endpoint disabled interrupt + enable + 1 + 1 + + + CITOEN + Control IN timeout condition interrupt enable (Non-isochronous + endpoints) + 3 + 1 + + + EPTXFUDEN + Endpoint Tx FIFO underrun interrupt enable bit + 4 + 1 + + + IEPNEEN + IN endpoint NAK effective + interrupt enable + 6 + 1 + + + + + DOEPINTEN + DOEPINTEN + device OUT endpoint common interrupt + enable register (DOEPINTEN) + 0x14 + 0x20 + read-write + 0x00000000 + + + TFEN + Transfer finished interrupt + enable + 0 + 1 + + + EPDISEN + Endpoint disabled interrupt + enable + 1 + 1 + + + STPFEN + SETUP phase finished interrupt enable + 3 + 1 + + + EPRXFOVREN + Endpoint Rx FIFO overrun interrupt enable + 4 + 1 + + + BTBSTPEN + Back-to-back SETUP packets + interrupt enable + 6 + 1 + + + + + DAEPINT + DAEPINT + device all endpoints interrupt + register (DAEPINT) + 0x18 + 0x20 + read-only + 0x00000000 + + + IEPITB + Device all IN endpoint interrupt bits + 0 + 4 + + + OEPITB + Device all OUT endpoint interrupt bits + 16 + 4 + + + + + DAEPINTEN + DAEPINTEN + Device all endpoints interrupt enable register + (DAEPINTEN) + 0x1C + 0x20 + read-write + 0x00000000 + + + IEPIE + IN EP interrupt interrupt enable bits + 0 + 4 + + + OEPIE + OUT endpoint interrupt enable bits + 16 + 4 + + + + + DVBUSDT + DVBUSDT + device VBUS discharge time + register + 0x28 + 0x20 + read-write + 0x000017D7 + + + DVBUSDT + Device VBUS discharge time + 0 + 16 + + + + + DVBUSPT + DVBUSPT + device VBUS pulsing time + register + 0x2C + 0x20 + read-write + 0x000005B8 + + + DVBUSPT + Device VBUS pulsing time + 0 + 12 + + + + + DIEPFEINTEN + DIEPFEINTEN + device IN endpoint FIFO empty + interrupt enable register + 0x34 + 0x20 + read-write + 0x00000000 + + + IEPTXFEIE + IN EP Tx FIFO empty interrupt enable + bits + 0 + 4 + + + + + DIEP0CTL + DIEP0CTL + device IN endpoint 0 control + register (DIEP0CTL) + 0x100 + 0x20 + 0x00008000 + + + MPL + Maximum packet length + 0 + 2 + read-write + + + EPACT + endpoint active + 15 + 1 + read-only + + + NAKS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-only + + + STALL + STALL handshake + 21 + 1 + read-write + + + TXFNUM + TxFIFO number + 22 + 4 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + EPD + Endpoint disable + 30 + 1 + read-write + + + EPEN + Endpoint enable + 31 + 1 + read-write + + + + + DIEP1CTL + DIEP1CTL + device in endpoint-1 control + register + 0x120 + 0x20 + 0x00000000 + + + EPEN + Endpoint enable + 31 + 1 + read-write + + + EPD + Endpoint disable + 30 + 1 + read-write + + + SD1PID_SODDFRM + Set DATA1 PID/Set odd frame + 29 + 1 + write-only + + + SD0PID_SEVENFRM + SD0PID/SEVNFRM + 28 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + CNAK + Clear NAK + 26 + 1 + write-only + + + TXFNUM + Tx FIFO number + 22 + 4 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + NAKS + NAK status + 17 + 1 + read-only + + + EOFRM_DPID + EOFRM/DPID + 16 + 1 + read-only + + + EPACT + Endpoint active + 15 + 1 + read-write + + + MPL + maximum packet length + 0 + 11 + read-write + + + + + DIEP2CTL + DIEP2CTL + device endpoint-2 control + register + 0x140 + 0x20 + 0x00000000 + + + EPEN + Endpoint enable + 31 + 1 + read-write + + + EPD + Endpoint disable + 30 + 1 + read-write + + + SD1PID_SODDFRM + Set DATA1 PID/Set odd frame + 29 + 1 + write-only + + + SD0PID_SEVENFRM + SD0PID/SEVNFRM + 28 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + CNAK + Clear NAK + 26 + 1 + write-only + + + TXFNUM + Tx FIFO number + 22 + 4 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + NAKS + NAK status + 17 + 1 + read-only + + + EOFRM_DPID + EOFRM/DPID + 16 + 1 + read-only + + + EPACT + Endpoint active + 15 + 1 + read-write + + + MPL + maximum packet length + 0 + 11 + read-write + + + + + DIEP3CTL + DIEP3CTL + device endpoint-3 control + register + 0x160 + 0x20 + 0x00000000 + + + EPEN + Endpoint enable + 31 + 1 + read-write + + + EPD + Endpoint disable + 30 + 1 + read-write + + + SD1PID_SODDFRM + Set DATA1 PID/Set odd frame + 29 + 1 + write-only + + + SD0PID_SEVENFRM + SD0PID/SEVNFRM + 28 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + CNAK + Clear NAK + 26 + 1 + write-only + + + TXFNUM + Tx FIFO number + 22 + 4 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + NAKS + NAK status + 17 + 1 + read-only + + + EOFRM_DPID + EOFRM/DPID + 16 + 1 + read-only + + + EPACT + Endpoint active + 15 + 1 + read-write + + + MPL + maximum packet length + 0 + 11 + read-write + + + + + DOEP0CTL + DOEP0CTL + device endpoint-0 control + register + 0x300 + 0x20 + 0x00008000 + + + EPEN + Endpoint enable + 31 + 1 + read-write + + + EPD + Endpoint disable + 30 + 1 + read-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + CNAK + Clear NAK + 26 + 1 + write-only + + + STALL + STALL handshake + 21 + 1 + read-write + + + SNOOP + Snoop mode + 20 + 1 + read-write + + + EPTYPE + Endpoint type + 18 + 2 + read-only + + + NAKS + NAK status + 17 + 1 + read-only + + + EPACT + Endpoint active + 15 + 1 + read-only + + + MPL + Maximum packet length + 0 + 2 + read-only + + + + + DOEP1CTL + DOEP1CTL + device endpoint-1 control + register + 0x320 + 0x20 + 0x00000000 + + + EPEN + Endpoint enable + 31 + 1 + read-write + + + EPD + Endpoint disable + 30 + 1 + read-write + + + SD1PID_SODDFRM + SD1PID/SODDFRM + 29 + 1 + write-only + + + SD0PID_SEVENFRM + SD0PID/SEVENFRM + 28 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + CNAK + Clear NAK + 26 + 1 + write-only + + + STALL + STALL handshake + 21 + 1 + read-write + + + SNOOP + Snoop mode + 20 + 1 + read-write + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + NAKS + NAK status + 17 + 1 + read-only + + + EOFRM_DPID + EOFRM/DPID + 16 + 1 + read-only + + + EPACT + Endpoint active + 15 + 1 + read-write + + + MPL + maximum packet length + 0 + 11 + read-write + + + + + DOEP2CTL + DOEP2CTL + device endpoint-2 control + register + 0x340 + 0x20 + 0x00000000 + + + EPEN + Endpoint enable + 31 + 1 + read-write + + + EPD + Endpoint disable + 30 + 1 + read-write + + + SD1PID_SODDFRM + SD1PID/SODDFRM + 29 + 1 + write-only + + + SD0PID_SEVENFRM + SD0PID/SEVENFRM + 28 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + CNAK + Clear NAK + 26 + 1 + write-only + + + STALL + STALL handshake + 21 + 1 + read-write + + + SNOOP + Snoop mode + 20 + 1 + read-write + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + NAKS + NAK status + 17 + 1 + read-only + + + EOFRM_DPID + EOFRM/DPID + 16 + 1 + read-only + + + EPACT + Endpoint active + 15 + 1 + read-write + + + MPL + maximum packet length + 0 + 11 + read-write + + + + + DOEP3CTL + DOEP3CTL + device endpoint-3 control + register + 0x360 + 0x20 + 0x00000000 + + + EPEN + Endpoint enable + 31 + 1 + read-write + + + EPD + Endpoint disable + 30 + 1 + read-write + + + SD1PID_SODDFRM + SD1PID/SODDFRM + 29 + 1 + write-only + + + SD0PID_SEVENFRM + SD0PID/SEVENFRM + 28 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + CNAK + Clear NAK + 26 + 1 + write-only + + + STALL + STALL handshake + 21 + 1 + read-write + + + SNOOP + Snoop mode + 20 + 1 + read-write + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + NAKS + NAK status + 17 + 1 + read-only + + + EOFRM_DPID + EOFRM/DPID + 16 + 1 + read-only + + + EPACT + Endpoint active + 15 + 1 + read-write + + + MPL + maximum packet length + 0 + 11 + read-write + + + + + DIEP0INTF + DIEP0INTF + device endpoint-0 interrupt + register + 0x108 + 0x20 + 0x00000080 + + + TXFE + Transmit FIFO empty + 7 + 1 + read-only + + + IEPNE + IN endpoint NAK effective + 6 + 1 + read-write + + + EPTXFUD + Endpoint Tx FIFO underrun + 4 + 1 + read-write + + + CITO + Control in timeout interrupt + 3 + 1 + read-write + + + EPDIS + Endpoint finished + 1 + 1 + read-write + + + TF + Transfer finished + 0 + 1 + read-write + + + + + DIEP1INTF + DIEP1INTF + device endpoint-1 interrupt + register + 0x128 + 0x20 + 0x00000080 + + + TXFE + Transmit FIFO empty + 7 + 1 + read-only + + + IEPNE + IN endpoint NAK effective + 6 + 1 + read-write + + + EPTXFUD + Endpoint Tx FIFO underrun + 4 + 1 + read-write + + + CITO + Control in timeout interrupt + 3 + 1 + read-write + + + EPDIS + Endpoint finished + 1 + 1 + read-write + + + TF + Transfer finished + 0 + 1 + read-write + + + + + DIEP2INTF + DIEP2INTF + device endpoint-2 interrupt + register + 0x148 + 0x20 + 0x00000080 + + + TXFE + Transmit FIFO empty + 7 + 1 + read-only + + + IEPNE + IN endpoint NAK effective + 6 + 1 + read-write + + + EPTXFUD + Endpoint Tx FIFO underrun + 4 + 1 + read-write + + + CITO + Control in timeout interrupt + 3 + 1 + read-write + + + EPDIS + Endpoint finished + 1 + 1 + read-write + + + TF + Transfer finished + 0 + 1 + read-write + + + + + DIEP3INTF + DIEP3INTF + device endpoint-3 interrupt + register + 0x168 + 0x20 + 0x00000080 + + + TXFE + Transmit FIFO empty + 7 + 1 + read-only + + + IEPNE + IN endpoint NAK effective + 6 + 1 + read-write + + + EPTXFUD + Endpoint Tx FIFO underrun + 4 + 1 + read-write + + + CITO + Control in timeout interrupt + 3 + 1 + read-write + + + EPDIS + Endpoint finished + 1 + 1 + read-write + + + TF + Transfer finished + 0 + 1 + read-write + + + + + DOEP0INTF + DOEP0INTF + device out endpoint-0 interrupt flag + register + 0x308 + 0x20 + read-write + 0x00000000 + + + BTBSTP + Back-to-back SETUP packets + 6 + 1 + + + EPRXFOVR + Endpoint Rx FIFO overrun + 4 + 1 + + + STPF + Setup phase finished + 3 + 1 + + + EPDIS + Endpoint disabled + 1 + 1 + + + TF + Transfer finished + 0 + 1 + + + + + DOEP1INTF + DOEP1INTF + device out endpoint-1 interrupt flag + register + 0x328 + 0x20 + read-write + 0x00000000 + + + BTBSTP + Back-to-back SETUP packets + 6 + 1 + + + EPRXFOVR + Endpoint Rx FIFO overrun + 4 + 1 + + + STPF + Setup phase finished + 3 + 1 + + + EPDIS + Endpoint disabled + 1 + 1 + + + TF + Transfer finished + 0 + 1 + + + + + DOEP2INTF + DOEP2INTF + device out endpoint-2 interrupt flag + register + 0x348 + 0x20 + read-write + 0x00000000 + + + BTBSTP + Back-to-back SETUP packets + 6 + 1 + + + EPRXFOVR + Endpoint Rx FIFO overrun + 4 + 1 + + + STPF + Setup phase finished + 3 + 1 + + + EPDIS + Endpoint disabled + 1 + 1 + + + TF + Transfer finished + 0 + 1 + + + + + DOEP3INTF + DOEP3INTF + device out endpoint-3 interrupt flag + register + 0x368 + 0x20 + read-write + 0x00000000 + + + BTBSTP + Back-to-back SETUP packets + 6 + 1 + + + EPRXFOVR + Endpoint Rx FIFO overrun + 4 + 1 + + + STPF + Setup phase finished + 3 + 1 + + + EPDIS + Endpoint disabled + 1 + 1 + + + TF + Transfer finished + 0 + 1 + + + + + DIEP0LEN + DIEP0LEN + device IN endpoint-0 transfer length + register + 0x110 + 0x20 + read-write + 0x00000000 + + + PCNT + Packet count + 19 + 2 + + + TLEN + Transfer length + 0 + 7 + + + + + DOEP0LEN + DOEP0LEN + device OUT endpoint-0 transfer length + register + 0x310 + 0x20 + read-write + 0x00000000 + + + STPCNT + SETUP packet count + 29 + 2 + + + PCNT + Packet count + 19 + 1 + + + TLEN + Transfer length + 0 + 7 + + + + + DIEP1LEN + DIEP1LEN + device IN endpoint-1 transfer length + register + 0x130 + 0x20 + read-write + 0x00000000 + + + MCPF + Multi packet count per frame + 29 + 2 + + + PCNT + Packet count + 19 + 10 + + + TLEN + Transfer length + 0 + 19 + + + + + DIEP2LEN + DIEP2LEN + device IN endpoint-2 transfer length + register + 0x150 + 0x20 + read-write + 0x00000000 + + + MCPF + Multi packet count per frame + 29 + 2 + + + PCNT + Packet count + 19 + 10 + + + TLEN + Transfer length + 0 + 19 + + + + + DIEP3LEN + DIEP3LEN + device IN endpoint-3 transfer length + register + 0x170 + 0x20 + read-write + 0x00000000 + + + MCPF + Multi packet count per frame + 29 + 2 + + + PCNT + Packet count + 19 + 10 + + + TLEN + Transfer length + 0 + 19 + + + + + DOEP1LEN + DOEP1LEN + device OUT endpoint-1 transfer length + register + 0x330 + 0x20 + read-write + 0x00000000 + + + STPCNT_RXDPID + SETUP packet count/Received data PID + 29 + 2 + + + PCNT + Packet count + 19 + 10 + + + TLEN + Transfer length + 0 + 19 + + + + + DOEP2LEN + DOEP2LEN + device OUT endpoint-2 transfer length + register + 0x350 + 0x20 + read-write + 0x00000000 + + + STPCNT_RXDPID + SETUP packet count/Received data PID + 29 + 2 + + + PCNT + Packet count + 19 + 10 + + + TLEN + Transfer length + 0 + 19 + + + + + DOEP3LEN + DOEP3LEN + device OUT endpoint-3 transfer length + register + 0x370 + 0x20 + read-write + 0x00000000 + + + STPCNT_RXDPID + SETUP packet count/Received data PID + 29 + 2 + + + PCNT + Packet count + 19 + 10 + + + TLEN + Transfer length + 0 + 19 + + + + + DIEP0TFSTAT + DIEP0TFSTAT + device IN endpoint 0 transmit FIFO + status register + 0x118 + 0x20 + read-only + 0x00000200 + + + IEPTFS + IN endpoint TxFIFO space + remaining + 0 + 16 + + + + + DIEP1TFSTAT + DIEP1TFSTAT + device IN endpoint 1 transmit FIFO + status register + 0x138 + 0x20 + read-only + 0x00000200 + + + IEPTFS + IN endpoint TxFIFO space + remaining + 0 + 16 + + + + + DIEP2TFSTAT + DIEP2TFSTAT + device IN endpoint 2 transmit FIFO + status register + 0x158 + 0x20 + read-only + 0x00000200 + + + IEPTFS + IN endpoint TxFIFO space + remaining + 0 + 16 + + + + + DIEP3TFSTAT + DIEP3TFSTAT + device IN endpoint 3 transmit FIFO + status register + 0x178 + 0x20 + read-only + 0x00000200 + + + IEPTFS + IN endpoint TxFIFO space + remaining + 0 + 16 + + + + + + + USBFS_PWRCLK + USB on the go full speed + USBFS + 0x50000E00 + + 0x0 + 0x100 + registers + + + + PWRCLKCTL + PWRCLKCTL + power and clock gating control + register (PWRCLKCTL) + 0x00 + 0x20 + read-write + 0x00000000 + + + SUCLK + Stop the USB clock + 0 + 1 + + + SHCLK + Stop HCLK + 1 + 1 + + + + + + + + WWDGT + Window watchdog timer + WWDGT + 0x40002C00 + + 0x0 + 0x400 + registers + + + WWDGT + 0 + + + + CTL + CTL + Control register + 0x0 + 0x20 + read-write + 0x0000007F + + + WDGTEN + Activation bit + 7 + 1 + + + CNT + 7-bit counter + 0 + 7 + + + + + CFG + CFG + Configuration register + 0x04 + 0x20 + read-write + 0x0000007F + + + EWIE + Early wakeup interrupt + 9 + 1 + + + PSC + Prescaler + 7 + 2 + + + WIN + 7-bit window value + 0 + 7 + + + + + STAT + STAT + Status register + 0x08 + 0x20 + read-write + 0x00000000 + + + EWIF + Early wakeup interrupt + flag + 0 + 1 + + + + + + + diff --git a/platform.json b/platform.json index 9c55a6d..a03f25a 100644 --- a/platform.json +++ b/platform.json @@ -67,6 +67,11 @@ "~1.90201.0" ] }, + "toolchain-riscv-nuclei": { + "type": "toolchain", + "optional": true, + "version": "https://github.com/CommunityGD32Cores/toolchain-riscv-nuclei.git#windows_x64" + }, "framework-mbed": { "type": "framework", "optional": true, diff --git a/platform.py b/platform.py index 2e150bf..0f3f179 100644 --- a/platform.py +++ b/platform.py @@ -28,15 +28,26 @@ class Gd32Platform(PlatformBase): "windows_amd64": "https://github.com/CommunityGD32Cores/tool-openocd-gd32.git#windows_x64_gigadevice", "linux_x86_64": "https://github.com/CommunityGD32Cores/tool-openocd-gd32.git#linux_x64", } + toolchain_riscv = { + "windows_amd64": "https://github.com/CommunityGD32Cores/toolchain-riscv-nuclei.git#windows_x64", + "linux_x86_64": "https://github.com/CommunityGD32Cores/toolchain-riscv-nuclei.git#linux_x64" + } def configure_default_packages(self, variables, targets): board = variables.get("board") board_config = self.board_config(board) build_core = variables.get( "board_build.core", board_config.get("build.core", "arduino")) - build_mcu = variables.get("board_build.mcu", board_config.get("build.mcu", "")) + build_mcu:str = variables.get("board_build.mcu", board_config.get("build.mcu", "")) sys_type = get_systype() + is_riscv = build_mcu.startswith("gd32vw") + if is_riscv: + del self.packages["toolchain-gccarmnoneeabi"] + self.packages["toolchain-riscv-nuclei"]["optional"] = False + if sys_type in Gd32Platform.toolchain_riscv: + self.packages["toolchain-riscv-nuclei"]["version"] = Gd32Platform.toolchain_riscv[sys_type] + openocd_pkg = "tool-openocd-gd32" # upgrade OpenOCD version if we have a package for it if openocd_pkg in self.packages and sys_type in Gd32Platform.openocd_gd32: