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sim.out
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| Core 0
Instructions | 666800
Cycles | 975954
IPC | 0.68
Time (ns) | 366900
Idle time (ns) | 290
Idle time (%) | 0.1%
Branch predictor stats |
num correct | 108867
num incorrect | 4809
misprediction rate | 4.23%
mpki | 7.21
TLB Summary |
I-TLB |
num accesses | 88626
num misses | 135
miss rate | 0.15%
mpki | 0.20
D-TLB |
num accesses | 224955
num misses | 489
miss rate | 0.22%
mpki | 0.73
L2 TLB |
num accesses | 624
num misses | 267
miss rate | 42.79%
mpki | 0.40
Cache Summary |
Cache L1-I |
num cache accesses | 88626
num cache misses | 1956
miss rate | 2.21%
mpki | 2.93
Cache L1-D |
num cache accesses | 224955
num cache misses | 5965
miss rate | 2.65%
mpki | 8.95
Cache L2 |
num cache accesses | 8057
num cache misses | 6255
miss rate | 77.63%
mpki | 9.38
Cache L3 |
num cache accesses | 6400
num cache misses | 6084
miss rate | 95.06%
mpki | 9.12
DRAM summary |
num dram accesses | 6084
average dram access latency (ns) | 73.10
average dram queueing delay | 19.67
average dram bandwidth utilization | 13.00%
Coherency Traffic |
num loads from dram | 3025
num loads from dram cache | 0
num loads from remote cache | 0