Testbench contains syntax errors..?

[cpt-n3mo]

hello, im new to icestudio, and to verilog in general,
and im sort of smashing my head against the wall here, as it seems the program exports the testbench file with allot of syntax errors,,

steps to reproduce:
create a new project in a new folder.
select board type
add a and gate, connect 2 inputs to A and B of and gate.
add output pin,
give input and output pins from the list
save the project
export as verilog,pcf,testbench,gtkwave,
run apio init --board {boardname}
run apio sim.
outputs >>
Untitled_tb.v:18: syntax error Untitled_tb.v:18: error: invalid module item. Untitled_tb.v:19: syntax error Untitled_tb.v:19: error: invalid module item. Untitled_tb.v:20: syntax error Untitled_tb.v:20: error: invalid module item. Untitled_tb.v:37: syntax error Untitled_tb.v:37: Syntax in assignment statement l-value. Untitled_tb.v:38: syntax error Untitled_tb.v:38: Syntax in assignment statement l-value. scons: *** [Untitled_tb.out] Error 10

content of tb file
`// Code generated by Icestudio 0.6.0
// Thu, 12 Aug 2021 02:44:48 GMT

// Testbench template

default_nettype none define DUMPSTR(x) "x.vcd"
`timescale 10 ns / 1 ns

module main_tb
;

// Simulation time: 100ns (10 * 10ns)
parameter DURATION = 10;

// Input/Output
reg 1;
reg 2;
wire 3;

// Module instance
main MAIN (
.v62539e(1),
.ve29200(2),
.v0c739c(3)
);

initial begin
// File were to store the simulation results
$dumpfile(DUMPSTR(VCD_OUTPUT));
$dumpvars(0, main_tb);

// TODO: initialize the registers here
// e.g. value = 1;
// e.g. #2 value = 0;
1 = 0;
2 = 0;

#(DURATION) $display("End of simulation");
$finish;
end

endmodule`

can someone please help me..?
im using iceStudio version 0.6.0
is there some proper documentation around somewhere..? so i can figure out how to actually use this, as this software seems very nice but the documention seems very scares on this subject..

[TimRudy]

I think you're on your own to use that skeleton and get the test bench doing what you want (from your learning).

You'll find examples. Mine use a macro ("TBASSERT") that makes tests "self-checking" - it prints output to the console if that test's result is not as predicted: https://github.com/TimRudy/ice-chips-verilog/source-7400

As for the wires with names like "v62539e": These are auto-generated, see "main.v" file in "ice-build". Just interpret (or re-name) to relate these to the inputs of your own modules.

Related issue, for documenting Export -> Testbench: #634