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common.bib
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@misc{taulbee2019,
title={2019 Taulbee Survey},
author ={Zweben, Stuart and Bizot, Betsy},
year={2019}}
@inproceedings{Gunawi:2008:SDF:1855741.1855751,
author = {Gunawi, Haryadi S. and Rajimwale, Abhishek and Arpaci-Dusseau, Andrea C. and Arpaci-Dusseau, Remzi H.},
title = {SQCK: A Declarative File System Checker},
booktitle = {Proceedings of the 8th USENIX Conference on Operating Systems Design and Implementation},
series = {OSDI'08},
year = {2008},
location = {San Diego, California},
pages = {131--146},
numpages = {16},
url = {http://dl.acm.org/citation.cfm?id=1855741.1855751},
acmid = {1855751},
publisher = {USENIX Association},
address = {Berkeley, CA, USA},
}
@inproceedings{ceph,
title={Ceph: A scalable, high-performance distributed file system},
author={Weil, Sage A and Brandt, Scott A and Miller, Ethan L and Long, Darrell DE and Maltzahn, Carlos},
booktitle={Proceedings of the 7th symposium on Operating systems design and implementation},
pages={307--320},
year={2006},
organization={USENIX Association}
}
@article{gluster,
title={Scale out with GlusterFS},
author={Davies, Alex and Orsaria, Alessandro},
journal={Linux Journal},
volume={2013},
number={235},
pages={1},
year={2013},
publisher={Belltown Media}
}
@article{Yang:2006:UMC:1189256.1189259,
author = {Yang, Junfeng and Twohey, Paul and Engler, Dawson and Musuvathi, Madanlal},
title = {Using Model Checking to Find Serious File System Errors},
journal = {ACM Trans. Comput. Syst.},
issue_date = {November 2006},
volume = {24},
number = {4},
month = nov,
year = {2006},
issn = {0734-2071},
pages = {393--423},
numpages = {31},
url = {http://doi.acm.org/10.1145/1189256.1189259},
doi = {10.1145/1189256.1189259},
acmid = {1189259},
publisher = {ACM},
address = {New York, NY, USA},
keywords = {Model checking, crash, file system, journaling, recovery},
}
@inproceedings{Sigurbjarnarson:2016:PVF:3026877.3026879,
author = {Sigurbjarnarson, Helgi and Bornholt, James and Torlak, Emina and Wang, Xi},
title = {Push-button Verification of File Systems via Crash Refinement},
booktitle = {Proceedings of the 12th USENIX Conference on Operating Systems Design and Implementation},
series = {OSDI'16},
year = {2016},
isbn = {978-1-931971-33-1},
location = {Savannah, GA, USA},
pages = {1--16},
numpages = {16},
url = {http://dl.acm.org/citation.cfm?id=3026877.3026879},
acmid = {3026879},
publisher = {USENIX Association},
address = {Berkeley, CA, USA},
}
@inproceedings{Bairavasundaram:2006:LTS:1179559.1179569,
author = {Bairavasundaram, Lakshmi N. and Rungta, Meenali and Arpaci-Dusseau, Andrea C. and Arpaci-Dusseau, Remzi H.},
title = {Limiting Trust in the Storage Stack},
booktitle = {Proceedings of the Second ACM Workshop on Storage Security and Survivability},
series = {StorageSS '06},
year = {2006},
isbn = {1-59593-552-5},
location = {Alexandria, Virginia, USA},
pages = {53--60},
numpages = {8},
url = {http://doi.acm.org/10.1145/1179559.1179569},
doi = {10.1145/1179559.1179569},
acmid = {1179569},
publisher = {ACM},
address = {New York, NY, USA},
keywords = {pointer corruption, type-aware corruption, verifiable invariants},
}
@inproceedings{Gunawi:2008:EEH:1364813.1364827,
author = {Gunawi, Haryadi S. and Rubio-Gonz\'{a}lez, Cindy and Arpaci-Dusseau, Andrea C. and Arpaci-Dussea, Remzi H. and Liblit, Ben},
title = {EIO: Error Handling is Occasionally Correct},
booktitle = {Proceedings of the 6th USENIX Conference on File and Storage Technologies},
series = {FAST'08},
year = {2008},
location = {San Jose, California},
pages = {14:1--14:16},
articleno = {14},
numpages = {16},
url = {http://dl.acm.org/citation.cfm?id=1364813.1364827},
acmid = {1364827},
publisher = {USENIX Association},
address = {Berkeley, CA, USA},
}
@inproceedings{Yang:2006:ELG:1298455.1298469,
author = {Yang, Junfeng and Sar, Can and Engler, Dawson},
title = {EXPLODE: A Lightweight, General System for Finding Serious Storage System Errors},
booktitle = {Proceedings of the 7th Symposium on Operating Systems Design and Implementation},
series = {OSDI '06},
year = {2006},
isbn = {1-931971-47-1},
location = {Seattle, Washington},
pages = {131--146},
numpages = {16},
url = {http://dl.acm.org/citation.cfm?id=1298455.1298469},
acmid = {1298469},
publisher = {USENIX Association},
address = {Berkeley, CA, USA},
}
@article{Sundararaman:2010:WPI:1740390.1740397,
author = {Sundararaman, Swaminathan and Subramanian, Sriram and Rajimwale, Abhishek and Arpaci-Dusseau, Andrea C. and Arpaci-Dusseau, Remzi H. and Swift, Michael M.},
title = {Why Panic()?: Improving Reliability with Restartable File Systems},
journal = {SIGOPS Oper. Syst. Rev.},
issue_date = {January 2010},
volume = {44},
number = {1},
month = mar,
year = {2010},
issn = {0163-5980},
pages = {25--29},
numpages = {5},
url = {http://doi.acm.org/10.1145/1740390.1740397},
doi = {10.1145/1740390.1740397},
acmid = {1740397},
publisher = {ACM},
address = {New York, NY, USA},
}
@misc{ext4dax,
title={Add Support for {NV-DIMMs} to Ext4},
author={Matthew Wilcox},
note={\url{https://lwn.net/Articles/613384/}},
key={linux},
year={2014}
}
@misc{oracle-nvm-direct,
title={{NVM Support for C Applications}},
author={Bridge, Bill},
year={2015},
publisher={Storage Industry Summit},
location={San Jose, California, USA},
note={Available at \url{http://www.snia.org/sites/default/files/BillBridgeNVMSummit2015Slides.pdf}
}}
@misc{intel-nvml,
title={{NVML: Implementing Persistent Memory Applications}},
author={Paul von Behren},
publisher={SNIA Global Education},
year={2015},
note={Available at \url{http://www.snia.org/sites/default/files/Paul_von_behren_NVML_Implementing_Persistent_Memory.pdf}}
}
@misc{acpi62,
title = {Advanced Configuration and Power Interface Specification},
author={{UEFI Forum}},
note = {http://www.uefi.org/sites/default/files/resources/ACPI\_6\_2.pdf},
year = {2017},
key={acpi}
}
@article{btrfs,
author = {Rodeh, Ohad and Bacik, Josef and Mason, Chris},
title = {{BTRFS: The Linux B-Tree Filesystem}},
journal = {Trans. Storage},
issue_date = {August 2013},
volume = {9},
number = {3},
month = aug,
year = {2013},
issn = {1553-3077},
pages = {9:1--9:32},
articleno = {9},
numpages = {32},
url = {http://doi.acm.org/10.1145/2501620.2501623},
doi = {10.1145/2501620.2501623},
acmid = {2501623},
publisher = {ACM},
address = {New York, NY, USA},
keywords = {B-trees, RAID, concurrency, copy-on-write, filesystem, shadowing, snapshots},
}
@misc{BEE3,
key={Bee3},
note={http://beecube.com/products/}
}
@misc{Exim,
title={{Exim Internet Mailer}},
key={Exim},
year={2017},
note={\url{http://www.exim.org}}
}
@misc{rocksdb,
title={{RocksDB}},
year={2017},
key={RocksDB},
author={{Facebook}},
note={\url{http://rocksdb.org}}
}
@misc{MongoDB,
year={2017},
title={{MongoDB}},
key={MongoDB},
author={{MongoDB, Inc.}},
note={\url{https://www.mongodb.com}}
}
@misc{sqlite,
title={{SQLite}},
author={{SQLite}},
year={2017},
key={SQLite},
note={\url{https://www.sqlite.org}}
}
@inproceedings{YCSB,
author = {Cooper, Brian F. and Silberstein, Adam and Tam, Erwin and Ramakrishnan, Raghu and Sears, Russell},
title = {{Benchmarking Cloud Serving Systems with YCSB}},
booktitle = {Proceedings of the 1st ACM Symposium on Cloud Computing},
series = {SoCC '10},
year = {2010},
isbn = {978-1-4503-0036-0},
location = {Indianapolis, Indiana, USA},
pages = {143--154},
numpages = {12},
url = {http://doi.acm.org/10.1145/1807128.1807152},
doi = {10.1145/1807128.1807152},
acmid = {1807152},
publisher = {ACM},
keywords = {benchmarking, cloud serving database},
}
@misc{pmfs-code,
key={PMFS1},
title={{Persistent Memory File System}},
note={\url{https://github.com/linux-pmfs/pmfs}}
}
@misc{NOVA-code,
key={NOVA},
title={{NOVA: NOn-Volatile memory Accelerated log-structured file system}},
note={\url{https://github.com/NVSL/NOVA}}
}
@misc{intel-instructions,
author={Intel},
year={2017},
title={{Intel Architecture Instruction Set Extensions Programming Reference}},
note={\url{https://software.intel.com/sites/default/files/managed/0d/53/319433-022.pdf}}
}
@misc{optane,
author={Intel},
year={2017},
key={optane},
title={{Intel Optane Memory}},
note={\url{http://www.intel.com/content/www/us/en/architecture-and-technology/optane-memory.html}}
}
@misc{intel-instructions-patch,
title={Add Support for New Persistent Memory Instructions},
author={Ross Zwisler},
key={Intel instructions patch},
note={\url{https://lwn.net/Articles/619851/}},
}
@inproceedings{tmpfs,
title={tmpfs: A Virtual Memory File System},
author={Snyder, Peter}
}
@misc{xfs,
author={Silicon Graphics International},
title="{{XFS}: A High-performance Journaling Filesystem}",
note={\url{http://oss.sgi.com/projects/xfs}}
}
@misc{xfsdax,
author={Dave Chinner},
year={2015},
title={xfs: updates for 4.2-rc1},
note={\url{http://oss.sgi.com/archives/xfs/2015-06/msg00478.html}}
}
@misc{windowsdax,
author={Robin Harris},
year={2016},
title={{Windows leaps into the NVM revolution}},
note={\url{http://www.zdnet.com/article/windows-leaps-into-the-nvm-revolution/}}
}
@article{startgap2,
author = {Moinuddin K. Qureshi and Andre Seznec and Luis A. Lastras and Michele M. Franceschini},
title = {Practical and Secure {PCM} Systems by Online Detection of Malicious Write Streams},
journal ={High-Performance Computer Architecture, International Symposium on},
volume = {0},
isbn = {978-1-4244-9432-3},
year = {2011},
pages = {478-489},
doi = {http://doi.ieeecomputersociety.org/10.1109/HPCA.2011.5749753},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
%%%%%%%% Start of template bibtex entries
@ARTICLE{1696083,
title={A 56nm CMOS 99mm2 8Gb Multi-level NAND Flash Memory with 10MB/s Program Throughput},
author={ Takeuchi, K. and Kameda, Y. and Fujimura, S. and Otake, H. and Hosono, K. and Shiga, H. and Watanabe, Y. and Futatsuyama, T. and Shindo, Y. and Kojima, M. and Iwai, M. and Shirakawa, M. and Ichige, M. and Hatakeyama, K. and Tanaka, S. and Kamei, T. and Jia-Yi Fu and Cernea, A. and Yan Li and Higashitani, M. and Hemink, G. and Sato, S. and Oowada, K. and Shih-Chung Lee and Hayashida, N. and Jun Wan and Lutze, J. and Shouchang Tsao and Mofidi, M. and Sakurai, K. and Tokiwa, N. and Waki, H. and Nozawa, Y. and Kanazawa, K. and Ohshima, S.},
journal={Solid-State Circuits Conference, 2006. ISSCC 2006. Digest of Technical Papers. IEEE International},
year={Feb. 6-9, 2006},
volume={},
number={},
pages={ 507-516},
abstract={},
doi={10.1109/ISSCC.2006.1696083},
ISSN={0193-6530}, }
@misc{mongo,
title={Mongo: A Scalable Flash Memory Simulator},
author={Withheld for publication}
}
@ARTICLE{1493861,
title={An 8 Gb multi-level NAND flash memory with 63 nm STI CMOS process technology},
author={Dae-Seok Byeon and Sung-Soo Lee and Young-Ho Lim and Jin-Sung Park and Wook-Kee Han and Pan-Suk Kwak and Dong-Hwan Kim and Dong-Hyuk Chae and Seung-Hyun Moon and Seung-Jae Lee and Hyun-Chul Cho and Jung-Woo Lee and Moo-Sung Kim and Joon-Sung Yang and Young-Woo Park and Duk-Won Bae and Jung-Dal Choi and Sung-Hoi Hur and Kang-Deog Suh},
journal={Solid-State Circuits Conference, 2005. Digest of Technical Papers. ISSCC. 2005 IEEE International},
year={10-10 Feb. 2005},
volume={},
number={},
pages={46-47 Vol. 1},
keywords={CMOS memory circuits, flash memories, integrated circuit design, logic design23 MB/s, 30 ns, 4.4 MB/s, 50 ns, 63 nm, 8 Gbit, CMOS process technology, cell size, chip size, cycle time, multi-level NAND flash memory, program mode, read throughput, shallow trench isolation},
doi={10.1109/ISSCC.2005.1493861},
ISSN={0193-6530}, }
@ARTICLE{1493860,
title={A 146 mm/sup 2/ 8 Gb NAND flash memory with 70 nm CMOS technology},
author={Hara, T. and Fukuda, K. and Kanazawa, K. and Shibata, N. and Hosono, K. and Maejima, H. and Nakagawa, M. and Abe, T. and Kojima, M. and Fujiu, M. and Takeuchi, Y. and Amemiya, K. and Morooka, M. and Kamei, T. and Nasu, H. and Kawano, K. and Chi-Ming Wan and Sakurai, K. and Tokiwa, N. and Waki, H. and Maruyama, T. and Yoshikawa, S. and Higashitani, M. and Pham, T.D. and Watanabe, T.},
journal={Solid-State Circuits Conference, 2005. Digest of Technical Papers. ISSCC. 2005 IEEE International},
year={10-10 Feb. 2005},
volume={},
number={},
pages={44-584 Vol. 1},
keywords={CMOS memory circuits, flash memories, integrated circuit layout, logic design4-level programmed cells, 6 MB/s, 70 nm, 8 Gbit, CMOS technology, NAND flash memory, binary flash memories, die size reduction, extended block-addressing scheme, memory core layout, single-sided pad architecture},
doi={10.1109/ISSCC.2005.1493860},
ISSN={0193-6530}, }
@article{HideakiKURATA11012007,
author = {KURATA, Hideaki and NODA, Satoshi and SASAGO, Yoshitaka and OTSUGA, Kazuo and ARIGANE, Tsuyoshi and KAWAMURA, Tetsufumi and KOBAYASHI, Takashi and KUME, Hitoshi and HOMMA, Kazuki and ITO, Teruhiko and SAKAMOTO, Yoshinori and SHIMIZU, Masahiro and IKEDA, Yoshinori and TSUCHIYA, Osamu and FURUSAWA, Kazunori},
title = {{A 126 mm2 4-Gb Multilevel AG-AND Flash Memory with Inversion-Layer-Bit-Line Technology}},
journal = {IEICE Trans Electron},
volume = {E90-C},
number = {11},
pages = {2146-2156},
doi = {10.1093/ietele/e90-c.11.2146},
year = {2007},
abstract = {A 4-Gb AG-AND flash memory was fabricated by using a 90-nm CMOS technology. To reduce cell size, an inversion-layer-bit-line technology was developed, enabling the elimination of both shallow trench isolations and diffusion layers from the memory cells. The inversion-layer-bit-line technology combined with a multilevel cell technique achieved a bit area 2F2 of 0.0162 {micro}m2, resulting in a chip size of 126 mm2. Both an address and temperature compensation techniques control the resistance of the inversion-layer local bit line. Source-side hot-electron injection programming with self-boosted charge, accumulated in inversion-layer bit lines under assist gates, reduces the dispersal of programming characteristics and also reduces the time overhead of pre-charging the bit lines. This self-boosted charge-injection scheme achieves a programming throughput of 10 MB/s.
},
URL = {http://ietele.oxfordjournals.org/cgi/content/abstract/E90-C/11/2146},
eprint = {http://ietele.oxfordjournals.org/cgi/reprint/E90-C/11/2146.pdf}
}
@ARTICLE{ProgramDisturb,
title={A 3.3 V 128 Mb multi-level NAND flash memory for mass storage applications},
author={Tae-Sung Jung and Young-Joon Choi and Kang-Deog Suh and Byung-Hoon Suh and Jin-Ki Kim and Young-Ho Lim and Yong-Nam Koh and Jong-Wook Park and Ki-Jong Lee and Jung-Hoon Park and Kee-Tae Park and Jang-Rae Kim and Jeong-Hyong Lee and Hyung-Kyu Lim},
journal={Solid-State Circuits Conference, 1996. Digest of Technical Papers. 42nd ISSCC., 1996 IEEE International},
year={Feb 1996},
volume={},
number={},
pages={32-33, 412},
keywords={CMOS memory circuits, EPROM, NAND circuits128 Mbit, 3.3 V, NAND flash memory, cost, multi-level cell, program disturbs, programmed threshold voltage control, serial access throughput, solid-state mass storage},
doi={10.1109/ISSCC.1996.488501},
ISSN={0193-6530}, }
@misc{NAND_RELIABILITY_PPT1,
author="Wes Prouty",
note="http://download.micron.com/pdf/presentations/events/flash\_mem\_summit\_waprouty\_nand\_reliability.pdf"
}
@misc{NAND_RELIABILITY_PPT2,
author="Jon G Elerath",
note="http://www.idemaap.org/Presentations/F14.Jon\_Elerath\_Demystifing\_Reliability\_of\_HD\_and\_SS\_Drives-r7.pdf"
}
@misc{NAND_RELIABILITY_PPT3,
author="Jim Cooke",
note="http://download.micron.com/pdf/presentations/events/flash\_mem\_summit\_jcooke\_inconvenient\_truths\_nand.pdf"
}
@article{MSP430,
author="Peter Forstner",
Title="MSP430 Flash Memory Characteristics -- SLAA334",
year=2006,
month="September"}
@ARTICLE{MLC16Levels,
title={A 70 nm 16 Gb 16-Level-Cell NAND flash Memory},
author={Shibata, N. and Maejima, H. and Isobe, K. and Iwasa, K. and Nakagawa, M. and Fujiu, M. and Shimizu, T. and Honma, M. and Hoshi, S. and Kawaai, T. and Kanebako, K. and Yoshikawa, S. and Tabata, H. and Inoue, A. and Takahashi, T. and Shano, T. and Komatsu, Y. and Nagaba, K. and Kosakai, M. and Motohashi, N. and Kanazawa, K. and Imamiya, K. and Nakai, H. and Lasser, M. and Murin, M. and Meir (Poza), A. and Eyal, A. and Shlick, M.},
journal={Solid-State Circuits, IEEE Journal of},
year={April 2008},
volume={43},
number={4},
pages={929-937},
doi={10.1109/JSSC.2008.917559},
ISSN={0018-9200}, }
@ARTICLE{IntelFlashCache,
title={A NAND Flash PC Platform Read Write Cache},
author={Pon, H. and Rao, K.},
journal={Non-Volatile Semiconductor Memory Workshop, 2007 22nd IEEE},
year={26-30 Aug. 2007},
volume={},
number={},
pages={21-22},
keywords={NAND circuits, cache storage, flash memories, integrated circuit reliability, random-access storageNAND flash, PC platform, PCI express bus, cache usage model, nonvolatile memory layer hierarchy, read write cache, reliability requirements, work load analysis},
doi={10.1109/NVSMW.2007.4290564},
ISSN={}, }
@ARTICLE{AlternateNANDInterface,
title={HyperLink NAND Flash Architecture for Mass Storage Applications},
author={Schuetz, R. and HakJune Oh and Jin-Ki Kim and Hong-Beom Pyeon and Przybylski, S.A. and Gillingham, P.},
journal={Non-Volatile Semiconductor Memory Workshop, 2007 22nd IEEE},
year={26-30 Aug. 2007},
volume={},
number={},
pages={3-4},
keywords={NAND circuits, flash memories, integrated memory circuitsdramatic price reduction, hyperlink NAND flash architecture, low pin count interface, mass storage, memory vendors},
doi={10.1109/NVSMW.2007.4290560},
ISSN={}, }
@ARTICLE{Flash3D1,
title={Three Dimensionally Stacked NAND Flash Memory Technology Using Stacking Single Crystal Si Layers on ILD and TANOS Structure for Beyond 30nm Node},
author={Jung, Soon-Moon and Jang, Jaehoon and Cho, Wonseok and Cho, Hoosung and Jeong, Jaehun and Chang, Youngchul and Kim, Jonghyuk and Rah, Youngseop and Son, Yangsoo and Park, Junbeom and Song, Min-Sung and Kim, Kyoung-Hon and Lim, Jin-Soo and Kim, Kinam},
journal={Electron Devices Meeting, 2006. IEDM '06. International},
year={11-13 Dec. 2006},
volume={},
number={},
pages={1-4},
abstract={For the first time, the 3 dimensionally stacked NAND Flash memory, is developed by implementing S3 (single-crystal Si layer stacking) technology, which was used to develop S3 SRAM previously. The NAND cell arrays are formed on the ILD as well as on the bulk to double the memory density without increasing the chip size. The feasibility of the technology was proven by the successful operation of 32 bit NAND flash memory cell strings with 63nm dimension and TANOS structures. The novel NAND cell operational scheme, so called SBT (source-body tied) scheme, is presented to maximize the advantages of 3 dimensionally stacked NAND cell structures},
keywords={NAND circuits, SRAM chips, flash memories, silicon, stacking32 bit, 3D stacked NAND flash memory, ILD, SRAM, TANOS structure, single crystal silicon layers, single-crystal Si layer stacking, source-body tied scheme},
doi={10.1109/IEDM.2006.346902},
ISSN={}, }
@ARTICLE{Flash3D2,
title={Optimal Integration and Characteristics of Vertical Array Devices for Ultra-High Density, Bit-Cost Scalable Flash Memory},
author={Fukuzumi, Y. and Matsuoka, Y. and Kito, M. and Kido, M. and Sato, M. and Tanaka, H. and Nagata, Y. and Iwata, Y. and Aochi, H. and Nitayama, A.},
journal={Electron Devices Meeting, 2007. IEDM 2007. IEEE International},
year={10-12 Dec. 2007},
volume={},
number={},
pages={449-452},
keywords={field effect transistors, flash memories, integrated memory circuitsSiN, bit-cost scalable flash memory, cell array, depletion-mode polysilicon transistors, gate dielectrics, macaroni body FET, ultra-high density memory, vertical array device characteristics},
doi={10.1109/IEDM.2007.4418970},
ISSN={}, }
@ARTICLE{longstring,
title={A 64-Cell NAND Flash Memory with Asymmetric S/D Structure for Sub-40nm Technology and Beyond},
author={K.-T. Park and J. Choi and J. Sel and V. Kim and C. Kang and Y. Shin and U. Roh and J. Park and J.-S. Lee and J. Sim and S. Jeon and C. Lee and K. Kim},
journal={VLSI Technology, 2006. Digest of Technical Papers. 2006 Symposium on},
year={ 2006},
volume={},
number={},
pages={19-20},
keywords={NAND circuits, flash memories, integrated memory circuits40 nm, NAND flash memory, NAND memory cell, asymmetric source-drain structure, inversion layer, short channel effect},
doi={10.1109/VLSIT.2006.1705196},
ISSN={}, }
@misc{ONFIOverview,
title="ONFi: Leading the Way to Higher Performance",
author="Amber Huffman",
note="http://www.onfi.org/docs/ComputexDRAMeXchange.pdf"
}
@ARTICLE{1705196,
title={A 64-Cell NAND Flash Memory with Asymmetric S/D Structure for Sub-40nm Technology and Beyond},
author={K.-T. Park and J. Choi and J. Sel and V. Kim and C. Kang and Y. Shin and U. Roh and J. Park and J.-S. Lee and J. Sim and S. Jeon and C. Lee and K. Kim},
journal={VLSI Technology, 2006. Digest of Technical Papers. 2006 Symposium on},
year={ 2006},
volume={},
number={},
pages={19-20},
abstract={A new 64-cell NAND flash memory with asymmetric S/D (Source/Drain) structure for sub-40nm node technology and beyond has been successfully developed. To suppress short channel effect in NAND memory cell, asymmetric S/D consisting of optimized junction and inversion layer induced by fringe field of WL bias which is applied at NAND operation conditions is successfully utilized. 64-cell NAND string which is double number of cells used in current NAND string is also used to further reduce bit cost by achieving over 10% chip size reduction while almost maintaining MLC (multi-level-cell) NAND performance requirements},
keywords={NAND circuits, flash memories, integrated memory circuits40 nm, NAND flash memory, NAND memory cell, asymmetric source-drain structure, inversion layer, short channel effect},
doi={10.1109/VLSIT.2006.1705196},
ISSN={}, }
@ARTICLE{904432,
title={High-density (4.4F2) NAND flash technology using Super-Shallow Channel Profile (SSCP) engineering},
author={Arai, F. and Arai, N. and Satoh, S. and Yaegashi, T. and Kamiya, E. and Matsunaga, Y. and Takeuchi, Y. and Kamata, H. and Shimizu, A. and Ohtami, N. and Kai, N. and Takahashi, S. and Moriyama, W. and Kugimiya, K. and Miyazaki, S. and Hirose, T. and Meguro, H. and Hatakeyama, K. and Shimizu, K. and Shirota, R.},
journal={Electron Devices Meeting, 2000. IEDM Technical Digest. International},
year={2000},
volume={},
number={},
pages={775-778},
abstract={This paper describes a novel high-density 4.4F2 (F: feature size) NAND flash memory with the cell size of 0.074 um2 for 0.13 um design rule. To minimize the cell size, two key technologies are introduced as follows. (1) The Super-Shallow Channel Profile (SSCP) engineering and (2) a novel layout of the NAND string that consists of 32 cells. The NAND cells fabricated by the above technologies have demonstrated good cell characteristics. This 4.4F2 NAND flash technology is highly advantageous for low cost flash memories of 4 Gbit and beyond for mass storage applications },
keywords={NAND circuits, cellular arrays, doping profiles, flash memories, integrated circuit design0.13 micron, 4 Gbit, NAND string, SSCP, Super-Shallow Channel Profile, cell characteristics, cell size, design rule, high-density NAND flash technology, low cost flash memories, mass storage applications},
doi={10.1109/IEDM.2000.904432},
ISSN={}, }
@inproceedings{mapreduce,
author = {Jeffrey Dean and Sanjay Ghemawat},
title = {MapReduce: simplified data processing on large clusters},
booktitle = {OSDI'04: Proceedings of the 6th conference on Symposium on Opearting Systems Design \& Implementation},
year = {2004},
pages = {10--10},
location = {San Francisco, CA},
publisher = {USENIX Association},
address = {Berkeley, CA, USA},
}
@inproceedings{mapreduceswarm,
author = {Andrew W. McNabb and Christopher K. Monson and Kevin D. Seppi},
title = {MRPSO: MapReduce particle swarm optimization},
booktitle = {GECCO '07: Proceedings of the 9th annual conference on Genetic and evolutionary computation},
year = {2007},
isbn = {978-1-59593-697-4},
pages = {177--177},
location = {London, England},
doi = {http://doi.acm.org/10.1145/1276958.1276991},
publisher = {ACM},
address = {New York, NY, USA},
}
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author = {Rob Pike and Sean Dorward and Robert Griesemer and Sean Quinlan},
title = {Interpreting the data: Parallel analysis with Sawzall},
journal = {Sci. Program.},
volume = {13},
number = {4},
year = {2005},
issn = {1058-9244},
pages = {277--298},
publisher = {IOS Press},
address = {Amsterdam, The Netherlands, The Netherlands},
}
@inproceedings{mapreducelearn,
author = {Chu, Cheng T. and Kim, Sang K. and Lin, Yi A. and Yu, Yuanyuan and Bradski, Gary R. and Ng, Andrew Y. and Olukotun, Kunle },
booktitle = {NIPS},
citeulike-article-id = {2308503},
editor = {Sch\"{o}lkopf, Bernhard and Platt, John C. and Hoffman, Thomas },
keywords = {google, map-reduce},
pages = {281--288},
posted-at = {2008-03-07 03:16:12},
priority = {0},
publisher = {MIT Press},
title = {Map-Reduce for Machine Learning on Multicore},
url = {http://dblp.uni-trier.de/rec/bibtex/conf/nips/ChuKLYBNO06},
year = {2006}
}
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author = {Hung-chih Yang and Ali Dasdan and Ruey-Lung Hsiao and D. Stott Parker},
title = {Map-reduce-merge: simplified relational data processing on large clusters},
booktitle = {SIGMOD '07: Proceedings of the 2007 ACM SIGMOD international conference on Management of data},
year = {2007},
isbn = {978-1-59593-686-8},
pages = {1029--1040},
location = {Beijing, China},
doi = {http://doi.acm.org/10.1145/1247480.1247602},
publisher = {ACM},
address = {New York, NY, USA},
}
@misc{intelserverpower,
Title="Increasing Data Center Density While Driving Down Power and Cooling Costs",
month="June",
Year=2006}
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Title="New Intel Centrino Atom Processor Technology Ushers in 'Best Internet Experience in Your Pocket'",
year=2008,
month=April,
note="Press release"}
@misc{atombenchmark1,
note="http://xtreview.com/addcomment-id-4801-view-Intel-atom-1.6-Ghz-benchmark.html",
}
@misc{atombenchmark2,
note="http://laptoping.com/intel-atom-benchmark.html"
}
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title="Samsung debuts 64Gbit MLC NAND flash memory",
month="October",
year=2007,
journal="EE Times Asia",
note="http://www.eetasia.com/ART\_8800485916\_499486\_NP\_11c4687c.HTM"
}
@ARTICLE{bigsamsungchip,
title={Integration Technology of 30nm Generation Multi-Level NAND Flash for 64Gb NAND Flash Memory},
author={Donghwa Kwak and Jaekwan Park and Keonsoo Kim and Yongsik Yim and Soojin Ahn and Yoonmoon Park and Jinho Kim and Woncheol Jeong and Jooyoung Kim and Mincheol Park and Byungkwan Yoo and Sangbin Song and Hyunsuk Kim and Jaehwang Sim and Sunghyun Kwon and Byungjoon Hwang and Hyung-kyu Park and Sunghoon Kim and Yunkyoung Lee and Hwagyung Shin and Namsoo Yim and Kwangseok Lee and Minjung Kim and Youngho Lee and Jangho Park and Sangyong Park and Jaesuk Jung and Kinam Kim},
journal={VLSI Technology, 2007 IEEE Symposium on},
year={12-14 June 2007},
volume={},
number={},
pages={12-13},
abstract={Multi-level NAND flash memories with a 38 nm design rule have been successfully developed for the first time. A breakthrough patterning technology of Self Aligned Double Patterning (SADP) together with ArF lithography is applied to three critical lithographic steps. Other key integration technologies include low thermal budget ILD process and twisted bit-line contact for excellent isolation between adjacent bit lines. Hemi-Cylindrical FET (HCFET) together with charge trapping memory cell of Si/SiO2 /SiN/Al2O3/TaN (TANOS) was found to be effective in sufficing various electrical requirements of 30 nm generation flash cells. Finally, MLC operation is successfully demonstrated with flash cells of 8 Gb density in which all the technologies aforementioned are combined.},
keywords={NAND circuits, field effect transistor circuits, lithography, semiconductor storageHCFET, NAND flash memory, breakthrough patterning technology, generation multi-level NAND flash, hemi-cylindrical FET, lithography, self aligned double patterning, size 38 nm},
doi={10.1109/VLSIT.2007.4339707},
ISSN={}, }
@article{gamma,
author = {D. J. Dewitt and S. Ghandeharizadeh and D. A. Schneider and A. Bricker and H. -I. Hsiao and R. Rasmussen},
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publisher = {IEEE Educational Activities Department},
address = {Piscataway, NJ, USA},
}
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address = {New York, NY, USA},
}
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author = {Michael Isard and Mihai Budiu and Yuan Yu and Andrew Birrell and Dennis Fetterly},
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publisher = {ACM},
address = {New York, NY, USA},
}
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author = {Goetz Graefe},
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}
@inproceedings{warehousepower,
author = {Xiaobo Fan and Wolf-Dietrich Weber and Luiz Andre Barroso},
title = {Power provisioning for a warehouse-sized computer},
booktitle = {ISCA '07: Proceedings of the 34th annual international symposium on Computer architecture},
year = {2007},
isbn = {978-1-59593-706-3},
pages = {13--23},
location = {San Diego, California, USA},
doi = {http://doi.acm.org/10.1145/1250662.1250665},
publisher = {ACM},
address = {New York, NY, USA},
}
@misc{disksim,
author={Greg Ganger and Bruce Worthington and Yale Patt},
title="DiskSim",
note="http://www.pdl.cmu.edu/DiskSim/"
}
@inproceedings{cmpmapreduce,
author = {Colby Ranger and Ramanan Raghuraman and Arun Penmetsa and Gary Bradski and Christos Kozyrakis},
title = {Evaluating MapReduce for Multi-core and Multiprocessor Systems},
booktitle = {HPCA '07: Proceedings of the 2007 IEEE 13th International Symposium on High Performance Computer Architecture},
year = {2007},
isbn = {1-4244-0804-0},
pages = {13--24},
doi = {http://dx.doi.org/10.1109/HPCA.2007.346181},
publisher = {IEEE Computer Society},
address = {Washington, DC, USA},
}
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author = {Sanjay Ghemawat and Howard Gobioff and Shun-Tak Leung},
title = {The Google file system},
journal = {SIGOPS Oper. Syst. Rev.},
volume = {37},
number = {5},
year = {2003},
issn = {0163-5980},
pages = {29--43},
doi = {http://doi.acm.org/10.1145/1165389.945450},
publisher = {ACM},
address = {New York, NY, USA},
}
@misc{samsungslc,
title="K9F8G08UXM Flash Memory datasheet"}
@ARTICLE{4154319,
title={Highly Manufacturable 32Gb Multi-Level NAND Flash Memory with 0.0098 $\mu$m2 Cell Size using TANOS(Si - Oxide - Al2O3 - TaN) Cell Technology},
author={Youngwoo Park and Jungdal Choi and Changseok Kang and Changhyun Lee and Yuchoel Shin and Bonghyn Choi and Juhung Kim and Sanghun Jeon and Jongsun Sel and Jintaek Park and Kihwan Choi and Taehwa Yoo and Jaesung Sim and Kinam Kim},
journal={Electron Devices Meeting, 2006. IEDM '06. International},
year={11-13 Dec. 2006},
volume={},
number={},
pages={1-4},
abstract={A highly manufacturable 32Gb multi-level NAND flash memory with 0.0098 mum cell size using 40nm TANOS cell technologies has been successfully developed for the first time. The main key technologies of 40nm 32Gb NAND flash are advanced high N.A immersion photolithography with off-axis illumination system, advanced blocking oxide of the TANOS cell, and PVD tungsten and flowable oxide for bit line},
keywords={NAND circuits, alumina, flash memories, immersion lithography, silicon compounds, tantalum compounds, tungsten32 Gbit, 40 nm, PVD tungsten, Si-Al2O3-TaN, TANOS cell technology, high N.A immersion photolithography, highly manufacturable multilevel NAND flash memory, off-axis illumination system},
doi={10.1109/IEDM.2006.346900},
ISSN={}, }
@misc{hadoop,
title="Hadoop",
note="http://hadoop.apache.org/core/"
}
@misc{ONFi1,
title={Open NAND Flash Interface Specification 1.0},
note={http://www.onfi.org/documentation.html}
}
@misc{ONFi2,
title={Open NAND Flash Interface Specification 2.0},
note={http://www.onfi.org/documentation.html}
}
@ARTICLE{flashring,
title={HyperLink NAND Flash Architecture for Mass Storage Applications},
author={Schuetz, R. and HakJune Oh and Jin-Ki Kim and Hong-Beom Pyeon and Przybylski, S.A. and Gillingham, P.},
journal={Non-Volatile Semiconductor Memory Workshop, 2007 22nd IEEE},
year={26-30 Aug. 2007},
volume={},
number={},
pages={3-4},
keywords={NAND circuits, flash memories, integrated memory circuitsdramatic price reduction, hyperlink NAND flash architecture, low pin count interface, mass storage, memory vendors},
doi={10.1109/NVSMW.2007.4290560},
ISSN={}, }
@article{usenixflash,
title={Design Tradeoffs for SSD Performance},
author={Nitin Agrawal and Vijayan Prabhakaran and Ted Wobber and John D. Davis and Mark Manasse and Rina Panigrahy},
year=2008,
month={June},
booktitle={Proceedings of the 2008 USENIX Annual Technical Conference}
}
@misc{fusionio,
note={http://www.fusionio.com/}
}
@misc{violin6000,
title={Violin Memory 6000 Series Flash Memory Arrays},
key={violin},
note={http://www.violin-memory.com/products/6000-flash-memory-array/}}
@misc{IntelSSD910Series,
key={intel},
note={http://www.intel.com/content/www/us/en/solid-state-drives/ssd-910-series-specification.html}
}
@misc{vmware,
note={http://www.vmware.com/}
}
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title={Full-system Power Analysis and Modeling for Server Environments},
author={Dimitris Economou and Suzanne Rivoire and Christos Kozyrakis and Partha Ranganathan},
booktitle={Workshop on Modeling Benchmarking and Simulation (MOBS) at ISCA},
year=2006,
month="June"}
@TechReport{msrftl,
author = {Andrew Birrell and Michael Isard and Chuck Thacker and Ted Wobber},
title = {A Design for High-Performance Flash Disks},
institution = {Microsoft Research},
year = {2005},
number = {MSR-TR-2005-176},
month = {December}
}
@misc{jffs2,
author={David Woodhouse},
title="JFFS2: The Journalling Flash File System, version 2",
note="http://sources.redhat.com/jffs2/"}
@inproceedings{wearleveling2,
author = {Dawoon Jung and Yoon-Hee Chae and Heeseung Jo and Jin-Soo Kim and Joonwon Lee},
title = {A group-based wear-leveling algorithm for large-capacity flash memory storage systems},
booktitle = {CASES '07: Proceedings of the 2007 international conference on Compilers, architecture, and synthesis for embedded systems},
year = {2007},
isbn = {978-1-59593-826-8},
pages = {160--164},
location = {Salzburg, Austria},
doi = {http://doi.acm.org/10.1145/1289881.1289911},
publisher = {ACM},
address = {New York, NY, USA},
}
@inproceedings{wearleveling1,
author = {Li-Pin Chang},
title = {On efficient wear leveling for large-scale flash-memory storage systems},
booktitle = {SAC '07: Proceedings of the 2007 ACM symposium on Applied computing},
year = {2007},
isbn = {1-59593-480-4},
pages = {1126--1130},
location = {Seoul, Korea},
doi = {http://doi.acm.org/10.1145/1244002.1244248},
publisher = {ACM},
address = {New York, NY, USA},
}
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journal={PC World},
year=2008,
month={February},
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@misc{atomdatasheet,
title={Intel Atom Processor Z5xx Series Datasheet},
month={April},
year=2008}
@misc{dramexchange,
title={{DRAMeXchange}},
note={http://www.dramexchange.com/}}
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title={Intel's Tiny Atom},
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year=2008,
month="April"
}
@misc{core2duodatasheet,
title={Quad-Core Intel Xeon Processor 3200 Series Datasheet},
author={Intel},
year=2007,
month=January
}
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title={Micron DDR3 SDRAM MT41J256M8 Datasheet Rev D},
author={Micron},
year=2008,
month=January,
note="http://download.micron.com/pdf/datasheets/dram/ddr3/2Gb DDR3 SDRAM.pdf"
}
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title={Intel System Controller Hub Datasheet},
author={Intel},
year=2008,
month=April,
note="http://download.intel.com/design/chipsets/embedded/datashts/319537.pdf"
}
@misc{umassiotraces,
title={UMass Trace Repository},
note="http://traces.cs.umass.edu/index.php/Storage/Storage"
}
@misc{webindexer,
title={Nutch},
note="http://lucene.apache.org/nutch/"
}
@misc{memoright,
title={MemoRight},
note="http://www.memoright.com/en/"
}
@misc{seagatecheetah,
title={Cheetah 10K.7 Datasheet},
author={Seagate},
year=2004,
note="https://spp.seagate.com/docs/pdf/datasheet/disc/ds\_cheetah10k.7.pdf"
}
@misc{seagatebarracuda,
title={Barracuda 7200.10 Datasheet},
author={Seagate},
year=2007,
note="http://www.seagate.com/docs/pdf/datasheet/disc/ds\_barracuda\_7200\_10.pdf"
}
%%%%%%%% Start of Atomic Write bibtex entries
@book{oodbbook,
author = {Cattell, R. G.},
title = {Object Data Management: Object-Oriented and Extended},
year = {1994},
isbn = {0201547481},
publisher = {Addison-Wesley Longman Publishing Co., Inc.},
address = {Boston, MA, USA},
}
@inproceedings{1251251,
author = {Gribble, Steven D. and Brewer, Eric A. and Hellerstein, Joseph M. and Culler, David},
title = {Scalable, distributed data structures for internet service construction},
booktitle = {OSDI'00: Proceedings of the 4th conference on Symposium on Operating System Design \& Implementation},
year = {2000},
pages = {22--22},
location = {San Diego, California},
publisher = {USENIX Association},
address = {Berkeley, CA, USA},
}
@misc{bdb,
key={oracle},
title={{Berkeley DB}},
note={\url{http://www.oracle.com/technology/products/berkeley-db/index.html}}
}
@misc{memcached,
key={memcached},
title={Memcached},
note={http://memcached.org/}
}
@misc{memcachedb,
key={memcachedb},
author={Steve Chu},
title={Memcachedb},
note={http://memcachedb.org/}
}
@misc{libmemcached,
key={libmemcached},
author={Brian Aker},
title={Libmemcached},
note={http://libmemcached.org/}
}
@inproceedings{ecp,
author = {Schechter, Stuart and Loh, Gabriel H. and Straus, Karin and Burger, Doug},
title = {Use ECP, not ECC, for hard failures in resistive memories},
booktitle = {Proceedings of the 37th annual international symposium on Computer architecture},
series = {ISCA '10},
year = {2010},
isbn = {978-1-4503-0053-7},
location = {Saint-Malo, France},
pages = {141--152},
numpages = {12},