diff --git a/sdk/app_cpu1/common/drv/pwm.h b/sdk/app_cpu1/common/drv/pwm.h
index aea2b560..8311516b 100644
--- a/sdk/app_cpu1/common/drv/pwm.h
+++ b/sdk/app_cpu1/common/drv/pwm.h
@@ -62,8 +62,8 @@ typedef enum {
 
 typedef enum {
     PWM_LATCH_MODE_TIMING_MANAGER = 0, // Update duty ratios at next timing manager trigger (default)
-    PWM_LATCH_MODE_PWM, // Update duty ratios at next PWM carrier peak/valley
-    PWM_LATCH_MODE_IMMEDIATE // Update duty ratios immediately (next FPGA clock rise)
+    PWM_LATCH_MODE_PWM,                // Update duty ratios at next PWM carrier peak/valley
+    PWM_LATCH_MODE_IMMEDIATE           // Update duty ratios immediately (next FPGA clock rise)
 } pwm_latch_mode;
 
 static inline bool pwm_is_valid_channel(pwm_channel_e channel)
diff --git a/sdk/app_cpu1/common/drv/timing_manager.c b/sdk/app_cpu1/common/drv/timing_manager.c
index 66290d39..472dd333 100644
--- a/sdk/app_cpu1/common/drv/timing_manager.c
+++ b/sdk/app_cpu1/common/drv/timing_manager.c
@@ -444,7 +444,8 @@ double timing_manager_get_time_per_sensor(sensor_e sensor)
 /*
  * Get the time since the sensor value was gathered for the requested sensor, in nanoseconds
  */
-double timing_manager_get_time_since_sensor_poll(sensor_e sensor) {
+double timing_manager_get_time_since_sensor_poll(sensor_e sensor)
+{
     uint32_t clock_cycles = Xil_In32(TM_BASE_ADDR + TM_INT_TIME_REG_OFFSET);
     double time = 0;