diff --git a/.github/workflows/gds.yaml b/.github/workflows/gds.yaml index fdad2bf..339b7e6 100644 --- a/.github/workflows/gds.yaml +++ b/.github/workflows/gds.yaml @@ -23,18 +23,6 @@ jobs: - name: Run Tiny Tapeout Precheck uses: TinyTapeout/tt-gds-action/precheck@tt06-staging - gl_test: - needs: gds - runs-on: ubuntu-latest - steps: - - name: checkout repo - uses: actions/checkout@v3 - with: - submodules: recursive - - - name: GL test - uses: TinyTapeout/tt-gds-action/gl_test@tt06-staging - viewer: needs: gds runs-on: ubuntu-latest diff --git a/.github/workflows/test.yaml b/.github/workflows/test.yaml deleted file mode 100644 index f85f37d..0000000 --- a/.github/workflows/test.yaml +++ /dev/null @@ -1,43 +0,0 @@ -name: test -on: [push, workflow_dispatch] -jobs: - test: - runs-on: ubuntu-latest - steps: - - name: Checkout repo - uses: actions/checkout@v4 - - # This installs cocotb and iverilog - - name: Install oss-cad-suite - uses: YosysHQ/setup-oss-cad-suite@v2 - with: - python-override: true - github-token: ${{ secrets.GITHUB_TOKEN }} - - run: | - yosys --version - iverilog -V - cocotb-config --libpython - cocotb-config --python-bin - - - name: Run tests - run: | - cd test - make clean - make - # make will return success even if the test fails, so check for failure in the results.xml - ! grep failure results.xml - - - name: Test Summary - uses: test-summary/action@v2 - with: - paths: "test/results.xml" - if: always() - - - name: upload vcd - if: success() || failure() - uses: actions/upload-artifact@v3 - with: - name: test-vcd - path: | - test/tb.vcd - test/result.xml diff --git a/.github/workflows/wokwi_test.yaml b/.github/workflows/wokwi_test.yaml new file mode 100644 index 0000000..fdc7b8e --- /dev/null +++ b/.github/workflows/wokwi_test.yaml @@ -0,0 +1,66 @@ +name: wokwi_test +# either manually started, or on a schedule +on: [ push, workflow_dispatch ] +jobs: + wokwi_test: + # ubuntu + runs-on: ubuntu-latest + steps: + # need the repo checked out + - name: checkout repo + uses: actions/checkout@v3 + with: + submodules: recursive + + # install oss fpga tools + - name: install oss-cad-suite + uses: YosysHQ/setup-oss-cad-suite@v2 + with: + python-override: true + github-token: ${{ secrets.GITHUB_TOKEN }} + - run: | + yosys --version + iverilog -V + cocotb-config --libpython + cocotb-config --python-bin + + - name: checkout tt tools repo + uses: actions/checkout@v3 + with: + repository: tinytapeout/tt-support-tools + path: tt + ref: tt06 + + # need python and requirements + - name: setup python + uses: actions/setup-python@v4 + with: + python-version: '3.10' + - run: pip install -r tt/requirements.txt + + # fetch the truth table + - name: fetch Verilog and build config + run: ./tt/tt_tool.py --create-user-config + + # does the wokwi project have a truthtable? + - name: Check the truthtable exists + id: check_files + uses: andstor/file-existence-action@v2 + with: + files: "src/truthtable.md" + + - name: test + if: steps.check_files.outputs.files_exists == 'true' + run: | + cd src + make clean + make + # make will return success even if the test fails, so check for failure in the results.xml + ! grep failure results.xml + + - name: upload vcd + if: success() || failure() + uses: actions/upload-artifact@v3 + with: + name: test-vcd + path: src/*.vcd diff --git a/README.md b/README.md index e67811b..b8fd2ec 100644 --- a/README.md +++ b/README.md @@ -1,6 +1,6 @@ -![](../../workflows/gds/badge.svg) ![](../../workflows/docs/badge.svg) ![](../../workflows/test/badge.svg) +![](../../workflows/gds/badge.svg) ![](../../workflows/docs/badge.svg) ![](../../workflows/wokwi_test/badge.svg) -# Tiny Tapeout Verilog Project Template +# Tiny Tapeout Wokwi Project Template - [Read the documentation for project](docs/info.md) @@ -10,15 +10,6 @@ TinyTapeout is an educational project that aims to make it easier and cheaper th To learn more and get started, visit https://tinytapeout.com. -## Verilog Projects - -1. Add your Verilog files to the `src` folder. -2. Edit the [info.yaml](info.yaml) and update information about your project, paying special attention to the `source_files` and `top_module` properties. -3. Edit [docs/info.md](docs/info.md) and add a description of your project. -4. Optionally, add a testbench to the `test` folder. See [test/README.md](test/README.md) for more information. - -The GitHub action will automatically build the ASIC files using [OpenLane](https://www.zerotoasiccourse.com/terminology/openlane/). - ## Enable GitHub actions to build the results page - [Enabling GitHub Pages](https://tinytapeout.com/faq/#my-github-action-is-failing-on-the-pages-part) diff --git a/info.yaml b/info.yaml index f04da75..75dc73e 100644 --- a/info.yaml +++ b/info.yaml @@ -1,5 +1,6 @@ -# Tiny Tapeout project information +# Tiny Tapeout project information (Wokwi project) project: + wokwi_id: 0 # Set this to the ID of your Wokwi project (the number from the project's URL) title: "" # Project title author: "" # Your name discord: "" # Your discord username, for communication and automatically assigning you a Tapeout role (optional) @@ -10,13 +11,6 @@ project: # How many tiles your design occupies? A single tile is about 167x108 uM. tiles: "1x1" # Valid values: 1x1, 1x2, 2x2, 3x2, 4x2, 6x2 or 8x2 - # Your top module name must start with "tt_um_". Make it unique by including your github username: - top_module: "tt_um_example" - - # List your project's source files here. Source files must be in ./src and you must list each source file separately, one per line: - source_files: - - "project.v" - # The pinout of your project. Leave unused pins blank. DO NOT delete or add any pins. pinout: # Inputs diff --git a/src/cells.v b/src/cells.v new file mode 100644 index 0000000..8bad93c --- /dev/null +++ b/src/cells.v @@ -0,0 +1,102 @@ +/* +This file provides the mapping from the Wokwi modules to Verilog HDL. + +It's only needed for Wokwi designs. +*/ + +`define default_netname none + +module buffer_cell ( + input wire in, + output wire out + ); + assign out = in; +endmodule + +module and_cell ( + input wire a, + input wire b, + output wire out + ); + + assign out = a & b; +endmodule + +module or_cell ( + input wire a, + input wire b, + output wire out + ); + + assign out = a | b; +endmodule + +module xor_cell ( + input wire a, + input wire b, + output wire out + ); + + assign out = a ^ b; +endmodule + +module nand_cell ( + input wire a, + input wire b, + output wire out + ); + + assign out = !(a&b); +endmodule + +module not_cell ( + input wire in, + output wire out + ); + + assign out = !in; +endmodule + +module mux_cell ( + input wire a, + input wire b, + input wire sel, + output wire out + ); + + assign out = sel ? b : a; +endmodule + +module dff_cell ( + input wire clk, + input wire d, + output reg q, + output wire notq + ); + + assign notq = !q; + always @(posedge clk) + q <= d; + +endmodule + +module dffsr_cell ( + input wire clk, + input wire d, + input wire s, + input wire r, + output reg q, + output wire notq + ); + + assign notq = !q; + + always @(posedge clk or posedge s or posedge r) begin + if (r) + q <= 0; + else if (s) + q <= 1; + else + q <= d; + end +endmodule diff --git a/src/project.v b/src/project.v deleted file mode 100644 index ca2cf39..0000000 --- a/src/project.v +++ /dev/null @@ -1,22 +0,0 @@ -/* - * Copyright (c) 2023 Your Name - * SPDX-License-Identifier: Apache-2.0 - */ - -module tt_um_example ( - input wire [7:0] ui_in, // Dedicated inputs - output wire [7:0] uo_out, // Dedicated outputs - input wire [7:0] uio_in, // IOs: Input path - output wire [7:0] uio_out, // IOs: Output path - output wire [7:0] uio_oe, // IOs: Enable path (active high: 0=input, 1=output) - input wire ena, - input wire clk, - input wire rst_n -); - - // All output pins must be assigned. If not used, assign to 0. - assign uo_out = ui_in + uio_in; // Example: ou_out is the sum of ui_in and uio_in - assign uio_out = 0; - assign uio_oe = 0; - -endmodule