board.h

////////////////////////////////////////////////////////////////////////////////
//
// Filename:	../demo-out/board.h
//
// Project:	AutoFPGA, a utility for composing FPGA designs from peripherals
// {{{
// Computer Generated: This file is computer generated by AUTOFPGA. DO NOT EDIT.
// DO NOT EDIT THIS FILE!
//
// CmdLine:	./autofpga -d -o ../demo-out -I ../auto-data allclocks.txt bkram.txt buserr.txt clkcheck.txt crossbus.txt ddr3.txt edidslvscope.txt edid.txt exconsole.txt flashcfg.txt flash.txt global.txt gpio.txt gps.txt hdmi.txt i2ccpu.txt i2cdma.txt i2saudio.txt icape.txt meganet.txt mdio.txt pic.txt pwrcount.txt rtcdate.txt rtcgps.txt spio.txt sdio.txt vadj33.txt version.txt wboledbw.txt wbpmic.txt wbuarbiter.txt wbubus.txt zipcpu.txt zipmaster.txt
//
// Creator:	Dan Gisselquist, Ph.D.
//		Gisselquist Technology, LLC
//
////////////////////////////////////////////////////////////////////////////////
// }}}
// Copyright (C) 2017-2024, Gisselquist Technology, LLC
// {{{
// This program is free software (firmware): you can redistribute it and/or
// modify it under the terms of the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or (at
// your option) any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with this program.  (It's in the $(ROOT)/doc directory.  Run make with no
// target there if the PDF file isn't present.)  If not, see
// <http://www.gnu.org/licenses/> for a copy.
// }}}
// License:	GPL, v3, as defined and found on www.gnu.org,
// {{{
//		http://www.gnu.org/licenses/gpl.html
//
//
////////////////////////////////////////////////////////////////////////////////
//
// }}}
#ifndef	BOARD_H
#define	BOARD_H

// And, so that we can know what is and isn't defined
// from within our main.v file, let's include:
#include <design.h>

#include <stdint.h>


#ifndef	UDP_DBGPORT
#define	UDP_DBGPORT	6784
#define	UDP_DATAPORT	6785
#endif


////////////////////////////////////////////////////////////////////////////////
//
// ZipCPU defines and macros
// {{{
#include <design.h>

#define	_HAVE_ZIPSYS
#define	PIC	_zip->z_pic

#ifdef	INCLUDE_ZIPCPU
#ifdef INCLUDE_DMA_CONTROLLER
#define	_HAVE_ZIPSYS_DMA
#endif	// INCLUDE_DMA_CONTROLLER
#ifdef INCLUDE_ACCOUNTING_COUNTERS
#define	_HAVE_ZIPSYS_PERFORMANCE_COUNTERS
#endif	// INCLUDE_ACCOUNTING_COUNTERS
#endif // INCLUDE_ZIPCPU
// }}}


#define	SYSPIC(A)	(1<<(A))


#define	ALTPIC(A)	(1<<(A))


	////////////////////////////////////////////////////////////////////////
	//
	// I2C CPU data structures
	// {{{
	////////////////////////////////////////////////////////////////////////
	//
	//
#ifndef	I2CCPU_H
#define	I2CCPU_H

#define	I2CC_WAITING	0x00800000	// True if waiting for synch signal
#define	I2CC_HALT	0x00400000	// Halt request
#define	I2CC_ABORT	0x00200000	// Abort
#define	I2CC_ERROR	0x00100000
#define	I2CC_HARDHALT	0x00080000
#define	I2CC_SCL	0x00000200
#define	I2CC_SDA	0x00000100
#define I2CC_STOPPED	I2CC_HARDHALT
#define I2CC_FAULT	(I2CC_ERROR | I2CC_ABORT)
#define I2CC_CLEAR	(I2CC_FAULT | I2CC_HALT)

// For the manual port
#define	I2CC_MANSCL	0x00008000
#define	I2CC_MANSDA	0x00004000
#define	I2CC_MANUAL	0x00000800
#define	I2CC_TVALID	0x00000200
#define	I2CC_TLAST	0x00000100

typedef	struct	I2CCPU_S {
	volatile unsigned	ic_control,
				ic_override,
				ic_address,
				ic_clkcount;
} I2CCPU;

#endif	// I2CCPU_H
	// }}}




#ifndef	WBUART_H
#define	WBUART_H

#define UART_PARITY_NONE        0
#define UART_HWFLOW_OFF         0x40000000
#define UART_PARITY_ODD         0x04000000
#define UART_PARITY_EVEN        0x05000000
#define UART_PARITY_SPACE       0x06000000
#define UART_PARITY_MARK        0x07000000
#define UART_STOP_ONEBIT        0
#define UART_STOP_TWOBITS       0x08000000
#define UART_DATA_8BITS         0
#define UART_DATA_7BITS         0x10000000
#define UART_DATA_6BITS         0x20000000
#define UART_DATA_5BITS         0x30000000
#define UART_RX_BREAK           0x0800
#define UART_RX_FRAMEERR        0x0400
#define UART_RX_PARITYERR       0x0200
#define UART_RX_NOTREADY        0x0100
#define UART_RX_ERR             (-256)
#define UART_TX_BUSY            0x0100
#define UART_TX_BREAK           0x0200

typedef struct  WBUART_S {
	unsigned	u_setup;
	unsigned	u_fifo;
	unsigned	u_rx, u_tx;
} WBUART;

#endif	// WBUART_H



#ifndef VIDPIPE_H
#define VIDPIPE_H

#define	VIDPIPE_RESET	0x000001
#define	VIDPIPE_RXPLLCK	0x000002
#define	VIDPIPE_LOCALCK	0x000000
#define	VIDPIPE_RXCLOCK	0x000020
#define	VIDPIPE_LCLSRC	0x000000
#define	VIDPIPE_RXSRC	0x000040
#define	VIDPIPE_RXSYNCD	0x010000
#define	VIDPIPE_OVLYERR	0x020000

#define	VIDCMAP_BW	0x000000
#define	VIDCMAP_2GRAY	0x000100
#define	VIDCMAP_4CMAP	0x000200
#define	VIDCMAP_8CMAP	0x000300
#define	VIDCMAP_8CLR	0x000400
#define	VIDCMAP_16CLR	0x000500
#define	VIDCMAP_24CLR	0x000600
#define	VIDCMAP_32CLR	0x000700

typedef struct __attribute__((packed)) VIDMODE_S {
	uint16_t	m_height,     m_width;
	uint16_t	m_vporch,     m_hporch;
	uint16_t	m_vsync,      m_hsync;
	uint16_t	m_raw_height, m_raw_width;
} VIDMODE;

typedef struct __attribute__((packed)) VIDPIPE_S {
	uint32_t	v_control, v_hdmifreq, v_sifreq, v_pxfreq;
	VIDMODE		v_in, v_src;
	const char	*v_overlay;
	uint16_t	v_ovheight, v_ovwidth;
	uint16_t	v_ovypos,  v_ovhpos;
	unsigned	v_fps;
	uint32_t	v_capture;
	const char	*v_capbase;
	uint32_t	v_capwords, v_capposn, v_capsize;
	unsigned	v_ovwords;
	unsigned	v_unused2[2];
	unsigned	v_syncword;
	uint32_t	v_unused[512-25];
	uint32_t	v_clrmap[256];
} VIDPIPE;

#endif // VIDPIPE_H


#ifndef	WBSCOPE_H
#define	WBSCOPE_H

#define	WBSCOPE_NO_RESET	0x80000000u
#define	WBSCOPE_STOPPED		0x40000000u
#define	WBSCOPE_TRIGGERED	0x20000000u
#define	WBSCOPE_PRIMED		0x10000000u
#define	WBSCOPE_TRIGGER		(WBSCOPE_NO_RESET|0x08000000u)
#define	WBSCOPE_MANUAL		(WBSCOPE_TRIGGER)
#define	WBSCOPE_DISABLE		0x04000000u

typedef	struct	WBSCOPE_S {
	volatile unsigned s_ctrl, s_data;
} WBSCOPE;
#endif


// Offsets for the ICAPE2 interface
#define	CFG_CRC		0
#define	CFG_FAR		1
#define	CFG_FDRI	2
#define	CFG_FDRO	3
#define	CFG_CMD		4
#define	CFG_CTL0	5
#define	CFG_MASK	6
#define	CFG_STAT	7
#define	CFG_LOUT	8
#define	CFG_COR0	9
#define	CFG_MFWR	10
#define	CFG_CBC		11
#define	CFG_IDCODE	12
#define	CFG_AXSS	13
#define	CFG_COR1	14
#define	CFG_WBSTAR	16
#define	CFG_TIMER	17
#define	CFG_BOOTSTS	22
#define	CFG_CTL1	24
#define	CFG_BSPI	31




typedef	struct	DDR3_PHY_S {
	unsigned	ph_something;
} DDR3_PHY;



#ifndef	I2CDMA_H
#define	I2CDMA_H
	////////////////////////////////////////////////////////////////////////
	//
	// I2C DMA data structures
	// {{{
	////////////////////////////////////////////////////////////////////////
	//
	//

typedef struct  I2CDMA_S        {
	unsigned	id_control, id_current, id_base, id_memlen;
} I2CDMA;

#endif	// I2CDMA_H
	// }}}


typedef	struct	GPSTB_S	{
	unsigned	tb_maxcount, tb_jump;
	unsigned long	tb_err, tb_count, tb_step;
} GPSTB;


// Network stream/packet interface
// {{{
#ifndef	ENETSTREAM_H
#define	ENETSTREAM_H
typedef struct ENETSTREAM_S {
        unsigned        n_rxcmd, n_txcmd;
        unsigned long   n_mac;
	unsigned	n_ipaddr;
        unsigned        n_rxmiss, n_rxerr, n_rxcrc;
	//
	unsigned	n_rxpkt, n_rxarp, n_rxicmp;
	unsigned	n_txpkt, n_txarp, n_txicmp;
	unsigned	n_data, n_aborts;
	unsigned	n_rxdbg, n_txdbg;
} ENETSTREAM;
#endif
// }}}


typedef	struct	RTCLIGHT_S	{
	unsigned	r_clock, r_stopwatch, r_timer, r_alarm;
} RTCLIGHT;


#define	SPIO_BTNC	0x01000
#define	SPIO_BTND	0x00800
#define	SPIO_BTNL	0x00400
#define	SPIO_BTNR	0x00200
#define	SPIO_BTNU	0x00100


//
// GPIO input wires
//
#define	GPIO_HDMIRX_CEC		0x000010000
#define	GPIO_HDMITX_CEC		0x000020000
#define	GPIO_SD_DETECTED	0x000080000
#define	GPIO_HDMITX_DETECT	0x000100000
#define	GPIO_GPS_3DF		0x000200000
#define	GPIO_SYSCLK_LOCKED	0x000400000
#define	GPIO_VIDCLK_LOCKED	0x000800000
//
// GPIO output wires
//
#define	GPIO_SET(WIRE)	(((WIRE)<<16)|(WIRE))
#define	GPIO_CLR(WIRE)	 ((WIRE)<<16)
//
#define	GPIO_HDMIRX_CEC_SET	0x000010001
#define	GPIO_HDMIRX_CEC_CLR	0x000010000
#define	GPIO_HDMITX_CEC_SET	0x000020002
#define	GPIO_HDMITX_CEC_CLR	0x000020000
//
#define	GPIO_HDMIRX_TXEN	0x000000004
#define	GPIO_HDMIRX_HPA		0x000000008
#define	GPIO_SD_RESET		0x000000010
#define	GPIO_OLED_RESET		0x000000020
#define	GPIO_OLED_PANELEN	0x000000040
#define	GPIO_OLED_LOGICEN	0x000000080
#define	GPIO_TRACE		0x000000100
#define	GPIO_TESTHALT		0x000000200
//
#define	GPIO_EDID_SCL_SET	GPIO_SET(GPIO_EDID_SCL)
#define	GPIO_EDID_SCL_CLR	GPIO_CLR(GPIO_EDID_SCL)
#define	GPIO_EDID_SDA_SET	GPIO_SET(GPIO_EDID_SDA)
#define	GPIO_EDID_SDA_CLR	GPIO_CLR(GPIO_EDID_SDA)
#define	GPIO_HDMIRX_HPA_SET	GPIO_SET(GPIO_HDMIRX_HPA)
#define	GPIO_HDMIRX_HPA_CLR	GPIO_CLR(GPIO_HDMIRX_HPA)
#define	GPIO_SD_RESET_SET	GPIO_SET(GPIO_SD_RESET)
#define	GPIO_SD_RESET_CLR	GPIO_CLR(GPIO_SD_RESET)
#define	GPIO_HDMIRX_TXEN_SET	GPIO_SET(GPIO_HDMIRX_TXEN)
#define	GPIO_HDMIRX_TXEN_CLR	GPIO_CLR(GPIO_HDMIRX_TXEN)
#define	OLED_RESET		GPIO_SET(GPIO_OLED_RESET)
#define	OLED_RUN		GPIO_CLR(GPIO_OLED_RESET)
#define	OLED_PANELEN		GPIO_SET(GPIO_OLED_PANELEN)
#define	OLED_PANELDIS		GPIO_CLR(GPIO_OLED_PANELEN)
#define	OLED_LOGICEN		GPIO_SET(GPIO_OLED_LOGICEN)
#define	OLED_LOGICDIS		GPIO_CLR(GPIO_OLED_LOGICEN)
#define	GPIO_TRACE_SET		GPIO_SET(GPIO_TRACE)
#define	GPIO_TRACE_CLR		GPIO_CLR(GPIO_TRACE)
#define	GPIO_HALT_SET		GPIO_SET(GPIO_TESTHALT)
#define	GPIO_HALT_CLR		GPIO_CLR(GPIO_TESTHALT)


////////////////////////////////////////////////////////////////////////////////
//
// SDIO SD Card constants
// {{{
////////////////////////////////////////////////////////////////////////////////
//
//

// These will be defined in sdiodrv.h for the SDIO controller
struct SDIO_S;
// }}}


#define BUSPIC(X) (1<<X)


typedef	struct	GPSTRACKER_S	{
	unsigned	g_alpha, g_beta, g_gamma, g_step;
} GPSTRACKER;


//
// The Ethernet MDIO interface
//
#define MDIO_BMCR	0x00
#define MDIO_BMSR	0x01
#define MDIO_PHYIDR1	0x02	// PHY ID Register #1
#define MDIO_PHYIDR2	0x03	// PHY ID Register #2
#define MDIO_ANAR	0x04	// Autonegotiation advertisement
#define MDIO_ANLPAR	0x05	// Autonegotiation link partner ability
#define MDIO_ANER	0x06	// Autonegotiation expansion
#define MDIO_ANNPTR	0x07	// Autonegotiation next page
#define MDIO_ANNPRR	0x08	// Autonegotiation link partner next page
#define MDIO_GBCR	0x09	// 1GBase-T Control
#define MDIO_GBSR	0x0a	// 1GBase-T Status
#define MDIO_MACR	0x0d	// MMD Access control
#define MDIO_MAADR	0x0e	// MMD Access register/data
#define MDIO_GBESR	0x0f
#define MDIO_PHYCR	0x10
#define MDIO_PHYSR	0x11
#define MDIO_INER	0x12
#define MDIO_INSR	0x13
#define MDIO_LDPSR	0x1b
#define MDIO_EPAGSR	0x1e
#define MDIO_PAGSEL	0x1f

#define XMDIO_PC1R	0x00
#define XMDIO_PS1R	0x01
#define XMDIO_EEECR	0x14
#define XMDIO_EEEWER	0x10
// #define XMDIO_EEEAR	0x
// #define XMDIO_EEELPAR	0x18
#define XMDIO_LACR	0x1a
#define XMDIO_LCR	0x1c
// #define XMDIO_ACCR	0x1b

typedef struct ENETMDIO_S {
	unsigned	e_v[32][32];
} ENETMDIO;



typedef	struct OLEDBW_S {
	unsigned	o_cmd, o_override, o_addr, o_clk;
} OLEDBW;



#define WBMIC_ENABLE	0
#define WBMIC_DISABLE	(1<<20)
#define WBMIC_NONEMPTY	0
#define WBMIC_HALFINT	(1<<22)
#define WBMIC_RESET	(1<<24)

typedef struct  WBMIC_S {
	unsigned	m_data;
	unsigned	m_setup;
} WBMIC;


#ifdef	FLASH_ACCESS
#define	_BOARD_HAS_FLASH
extern int _flash[1];
#endif	// FLASH_ACCESS
#ifdef	I2CCPU_ACCESS
#define	_BOARD_HAS_I2CCPU
static volatile I2CCPU *const _i2c=((I2CCPU *)0x08001420);
#endif	// I2CCPU_ACCESS
#define	_BOARD_HAS_BUSERR
static volatile unsigned *const _buserr = ((unsigned *)0x08001488);
#define	_BOARD_HAS_SUBSECONDS
static volatile unsigned *const _subseconds = ((unsigned *)0x080014a4);
#ifdef	ADCCLK
static volatile unsigned *const _adcclk = ((unsigned *)0x08001480);
#endif	// ADCCLK
#ifdef	FLASHCFG_ACCESS
#define	_BOARD_HAS_FLASHCFG
static volatile unsigned * const _flashcfg = ((unsigned *)(0x08000400));
#endif	// FLASHCFG_ACCESS
#ifdef	EDID_ACCESS
#define	_BOARD_HAS_EDID
static volatile I2CCPU *const _edid = ((I2CCPU *)0x08001400);
#endif	// EDID_ACCESS
#ifdef	GPSUART_ACCESS
#define	_BOARD_HAS_GPS_UART
static volatile WBUART *const _gpsu = ((WBUART *)(0x08000a00));
#endif	// GPSUART_ACCESS
#ifdef	VIDPIPE_ACCESS
#define	_BOARD_HAS_VIDPIPE
static volatile VIDPIPE *const _hdmi = ((VIDPIPE *)0x08002000);
#endif	// VIDPIPE_ACCESS
static volatile char *const _edidslv = ((char *)0x08001500);
#ifdef	EDIDSLVSCOPE_SCOPC
#define	_BOARD_HAS_EDIDSLVSCOPE
static volatile WBSCOPE *const _edidslvscope = ((WBSCOPE *)0x08000600);
#endif	// EDIDSLVSCOPE_SCOPC
#ifdef	CFG_ACCESS
#define	_BOARD_HAS_ICAPETWO
static volatile unsigned *const _icape = ((unsigned *)0x08000c00);
#endif	// CFG_ACCESS
#ifdef	TXCLK
static volatile unsigned *const _txclk = ((unsigned *)0x080014a8);
#endif	// TXCLK
#ifdef	RXETH0CK
static volatile unsigned *const _rxeth0ck = ((unsigned *)0x0800149c);
#endif	// RXETH0CK
#ifdef	BKRAM_ACCESS
#define	_BOARD_HAS_BKRAM
extern char	_bkram[0x00100000];
#endif	// BKRAM_ACCESS
#ifdef	SDRAM_ACCESS
#define	_BOARD_HAS_SDRAM
extern char	_ddr3[0x40000000];
#endif	// SDRAM_ACCESS
#ifdef	DDR3_PHY_ACCESS
#define	_BOARD_HAS_DDR3_PHY
static volatile DDR3_PHY *const _ddr3_phy = ((DDR3_PHY *)0x08001000);
#endif	// DDR3_PHY_ACCESS
#ifdef	I2CDMA_ACCESS
#define	_BOARD_HAS_I2CDMA
static volatile I2CDMA *const _i2cdma=((I2CDMA *)0x08001430);
#endif	// I2CDMA_ACCESS
#ifdef	PWRCOUNT_ACCESS
static volatile unsigned *const _pwrcount = ((unsigned *)0x08001494);
#endif	// PWRCOUNT_ACCESS
static volatile GPSTB *const _gpstb = ((GPSTB *)0x08001460);
#define	_BOARD_HAS_PXPLL
static volatile unsigned *const _pxclk=((unsigned *)0x08001200);
#ifdef	MEGANET_ACCESS
#define	_BOARD_HAS_MEGANET
static volatile ENETSTREAM *const _net = ((ENETSTREAM *)0x08000e00);
#endif	// MEGANET_ACCESS
#ifdef	RTCDATE_ACCESS
#define	_BOARD_HAS_RTCDATE
static volatile unsigned *const _rtcdate = ((unsigned *)134223000);
#endif	// RTCDATE_ACCESS
#ifdef	RTC_ACCESS
#define	_BOARD_HAS_RTC
static volatile RTCLIGHT *const _rtc = ((RTCLIGHT *)0x08001450);
#endif	// RTC_ACCESS
#ifdef	SPIO_ACCESS
#define	_BOARD_HAS_SPIO
static volatile unsigned *const _spio = ((unsigned *)0x080014a0);
#endif	// SPIO_ACCESS
#ifdef	GPIO_ACCESS
#define	_BOARD_HAS_GPIO
static volatile unsigned *const _gpio = ((unsigned *)0x08001490);
#endif	// GPIO_ACCESS
#ifdef	SDIO_ACCESS
#define	_BOARD_HAS_SDIO
static volatile struct SDIO_S *const _sdio = ((struct SDIO_S *)0x00800000);
#endif	// SDIO_ACCESS
#ifdef	BUSPIC_ACCESS
#define	_BOARD_HAS_BUSPIC
static volatile unsigned *const _buspic = ((unsigned *)0x0800148c);
#endif	// BUSPIC_ACCESS
#ifdef	GPSTRK_ACCESS
static volatile GPSTRACKER *const _gps = ((GPSTRACKER *)0x08001410);
#endif	// GPSTRK_ACCESS
#ifdef	NETCTRL_ACCESS
#define	_BOARD_HAS_NETMDIO
static volatile ENETMDIO *const _mdio = ((ENETMDIO *)0x08003000);
#endif	// NETCTRL_ACCESS
#define	_BOARD_HAS_BUILDTIME
static volatile unsigned *const _buildtime = ((unsigned *)0x08001484);
#ifdef	VERSION_ACCESS
#define	_BOARD_HAS_VERSION
static volatile unsigned *const _version = ((unsigned *)0x080014ac);
#endif	// VERSION_ACCESS
#ifdef	OLEDBW_ACCESS
#define	_BOARD_HAS_OLEDBW
static volatile OLEDBW *const _oled = ((OLEDBW *)134222912);
#endif	// OLEDBW_ACCESS
#ifdef	MICROPHONE_ACCESS
#define	_BOARD_HAS_WBMIC
static volatile WBMIC *const _wbmic = ((WBMIC *)134219776);
#endif	// MICROPHONE_ACCESS
//
// Interrupt assignments (3 PICs)
//
// PIC: syspic
#define	SYSPIC_DMAC	SYSPIC(0)
#define	SYSPIC_JIFFIES	SYSPIC(1)
#define	SYSPIC_TMC	SYSPIC(2)
#define	SYSPIC_TMB	SYSPIC(3)
#define	SYSPIC_TMA	SYSPIC(4)
#define	SYSPIC_ALT	SYSPIC(5)
#define	SYSPIC_BUS	SYSPIC(6)
#define	SYSPIC_I2C	SYSPIC(7)
#define	SYSPIC_EDID	SYSPIC(8)
#define	SYSPIC_VIDFRAME	SYSPIC(9)
#define	SYSPIC_GPIO	SYSPIC(10)
#define	SYSPIC_SDCARD	SYSPIC(11)
#define	SYSPIC_PPS	SYSPIC(12)
#define	SYSPIC_OLED	SYSPIC(13)
#define	SYSPIC_MIC	SYSPIC(14)
// PIC: altpic
#define	ALTPIC_UIC	ALTPIC(0)
#define	ALTPIC_UOC	ALTPIC(1)
#define	ALTPIC_UPC	ALTPIC(2)
#define	ALTPIC_UTC	ALTPIC(3)
#define	ALTPIC_MIC	ALTPIC(4)
#define	ALTPIC_MOC	ALTPIC(5)
#define	ALTPIC_MPC	ALTPIC(6)
#define	ALTPIC_MTC	ALTPIC(7)
#define	ALTPIC_GPSRX	ALTPIC(8)
#define	ALTPIC_GPSTX	ALTPIC(9)
#define	ALTPIC_GPSRXF	ALTPIC(10)
#define	ALTPIC_GPSTXF	ALTPIC(11)
#define	ALTPIC_EDIDSLVSCOPE	ALTPIC(12)
#define	ALTPIC_RTC	ALTPIC(13)
// PIC: buspic
#define	BUSPIC_SPIO	BUSPIC(0)
#define	SYSINT_GPSRXF	ALTINT(@$(INT.GPSRXF.syspic.ID))
#define	SYSINT_GPSTXF	ALTINT(11)
#define	SYSINT_GPSRX	ALTINT(8)
#define	SYSINT_GPSTX	ALTINT(9)


#define	SYSINT_PPS	SYSINT(12)


#endif	// BOARD_H