-
Notifications
You must be signed in to change notification settings - Fork 19
/
Copy pathregdefs.h
392 lines (379 loc) · 21 KB
/
regdefs.h
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
////////////////////////////////////////////////////////////////////////////////
//
// Filename: ../demo-out/regdefs.h
//
// Project: AutoFPGA, a utility for composing FPGA designs from peripherals
// {{{
// Computer Generated: This file is computer generated by AUTOFPGA. DO NOT EDIT.
// DO NOT EDIT THIS FILE!
//
// CmdLine: ./autofpga -d -o ../demo-out -I ../auto-data allclocks.txt bkram.txt buserr.txt clkcheck.txt crossbus.txt ddr3.txt edidslvscope.txt edid.txt exconsole.txt flashcfg.txt flash.txt global.txt gpio.txt gps.txt hdmi.txt i2ccpu.txt i2cdma.txt i2saudio.txt icape.txt meganet.txt mdio.txt pic.txt pwrcount.txt rtcdate.txt rtcgps.txt spio.txt sdio.txt vadj33.txt version.txt wboledbw.txt wbpmic.txt wbuarbiter.txt wbubus.txt zipcpu.txt zipmaster.txt
//
// Creator: Dan Gisselquist, Ph.D.
// Gisselquist Technology, LLC
//
////////////////////////////////////////////////////////////////////////////////
// }}}
// Copyright (C) 2017-2024, Gisselquist Technology, LLC
// {{{
// This program is free software (firmware): you can redistribute it and/or
// modify it under the terms of the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or (at
// your option) any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with this program. (It's in the $(ROOT)/doc directory. Run make with no
// target there if the PDF file isn't present.) If not, see
// <http://www.gnu.org/licenses/> for a copy.
// }}}
// License: GPL, v3, as defined and found on www.gnu.org,
// {{{
// http://www.gnu.org/licenses/gpl.html
//
//
////////////////////////////////////////////////////////////////////////////////
//
// }}}
#ifndef REGDEFS_H
#define REGDEFS_H
//
// The @REGDEFS.H.INCLUDE tag
//
// @REGDEFS.H.INCLUDE for masters
// @REGDEFS.H.INCLUDE for peripherals
#ifndef FPGAPORT
#define FPGAPORT 6782
#define UARTDBGPORT 6782
#define UARTPORT 6783
#define UDP_DBGPORT 6784
#define UDP_DATAPORT 6785
#endif
// And finally any master REGDEFS.H.INCLUDE tags
// End of definitions from REGDEFS.H.INCLUDE
//
// Register address definitions, from @REGS.#d
//
// SDIO SD Card addresses
#define R_SDIO_CTRL 0x00800000 // 00800000, wbregs names: SDCARD
#define R_SDIO_DATA 0x00800004 // 00800000, wbregs names: SDDATA
#define R_SDIO_FIFOA 0x00800008 // 00800000, wbregs names: SDFIFOA, SDFIF0, SDFIFA
#define R_SDIO_FIFOB 0x0080000c // 00800000, wbregs names: SDFIFOB, SDFIF1, SDFIFB
#define R_SDIO_PHY 0x00800010 // 00800000, wbregs names: SDPHY
#define R_FLASH 0x01000000 // 01000000, wbregs names: FLASH
// FLASH erase/program configuration registers
#define R_FLASHCFG 0x08000400 // 08000400, wbregs names: FLASHCFG, QSPIC
// edidslvscope compressed scope
#define R_EDIDSLVSCOPE 0x08000600 // 08000600, wbregs names: EDIDSLVSCOPE
#define R_EDIDSLVSCOPED 0x08000604 // 08000600, wbregs names: EDIDSLVSCOPED
// WB-Microphone registers
#define R_MIC_DATA 0x08000800 // 08000800, wbregs names: MICD
#define R_MIC_CTRL 0x08000804 // 08000800, wbregs names: MICC
// GPS UART registers, similar to WBUART
#define R_GPSU_SETUP 0x08000a00 // 08000a00, wbregs names: GPSSETUP
#define R_GPSU_FIFO 0x08000a04 // 08000a00, wbregs names: GPSFIFO
#define R_GPSU_UARTRX 0x08000a08 // 08000a00, wbregs names: GPSRX
#define R_GPSU_UARTTX 0x08000a0c // 08000a00, wbregs names: GPSTX
// FPGA CONFIG REGISTERS: 0x4e0-0x4ff
#define R_CFG_CRC 0x08000c00 // 08000c00, wbregs names: FPGACRC
#define R_CFG_FAR 0x08000c04 // 08000c00, wbregs names: FPGAFAR
#define R_CFG_FDRI 0x08000c08 // 08000c00, wbregs names: FPGAFDRI
#define R_CFG_FDRO 0x08000c0c // 08000c00, wbregs names: FPGAFDRO
#define R_CFG_CMD 0x08000c10 // 08000c00, wbregs names: FPGACMD
#define R_CFG_CTL0 0x08000c14 // 08000c00, wbregs names: FPGACTL0
#define R_CFG_MASK 0x08000c18 // 08000c00, wbregs names: FPGAMASK
#define R_CFG_STAT 0x08000c1c // 08000c00, wbregs names: FPGASTAT
#define R_CFG_LOUT 0x08000c20 // 08000c00, wbregs names: FPGALOUT
#define R_CFG_COR0 0x08000c24 // 08000c00, wbregs names: FPGACOR0
#define R_CFG_MFWR 0x08000c28 // 08000c00, wbregs names: FPGAMFWR
#define R_CFG_CBC 0x08000c2c // 08000c00, wbregs names: FPGACBC
#define R_CFG_IDCODE 0x08000c30 // 08000c00, wbregs names: FPGAIDCODE
#define R_CFG_AXSS 0x08000c34 // 08000c00, wbregs names: FPGAAXSS
#define R_CFG_COR1 0x08000c38 // 08000c00, wbregs names: FPGACOR1
#define R_CFG_WBSTAR 0x08000c40 // 08000c00, wbregs names: WBSTAR
#define R_CFG_TIMER 0x08000c44 // 08000c00, wbregs names: CFGTIMER
#define R_CFG_BOOTSTS 0x08000c58 // 08000c00, wbregs names: BOOTSTS
#define R_CFG_CTL1 0x08000c60 // 08000c00, wbregs names: FPGACTL1
#define R_CFG_BSPI 0x08000c7c // 08000c00, wbregs names: FPGABSPI
// Meganet register definitions
#define R_MEGANET_RXCMD 0x08000e00 // 08000e00, wbregs names: MEGANETRX
#define R_MEGANET_TXCMD 0x08000e04 // 08000e00, wbregs names: MEGANETTX
#define R_MEGANET_MACHI 0x08000e08 // 08000e00, wbregs names: MEGANETMACHI
#define R_MEGANET_MACLO 0x08000e0c // 08000e00, wbregs names: MEGANETMACLO
#define R_MEGANET_IPADDR 0x08000e10 // 08000e00, wbregs names: MEGANETIPADDR, MEGANETIP
#define R_MEGANET_RXMISS 0x08000e14 // 08000e00, wbregs names: MEGANETMISS
#define R_MEGANET_RXERR 0x08000e18 // 08000e00, wbregs names: MEGANETERR
#define R_MEGANET_RXCRC 0x08000e1c // 08000e00, wbregs names: MEGANETCRCER
#define R_MEGANET_DBGSEL 0x08000e20 // 08000e00, wbregs names: MEGANETDBGSL
#define R_MEGANET_RXPKTS 0x08000e20 // 08000e00, wbregs names: MEGANETRXPKT
#define R_MEGANET_ARPRX 0x08000e24 // 08000e00, wbregs names: MEGANETARPRX
#define R_MEGANET_ICMPRX 0x08000e28 // 08000e00, wbregs names: MEGANETICMRX
#define R_MEGANET_TXPKTS 0x08000e2c // 08000e00, wbregs names: MEGANETTXPKT
#define R_MEGANET_ARPTX 0x08000e30 // 08000e00, wbregs names: MEGANETARPTX
#define R_MEGANET_ICMPTX 0x08000e34 // 08000e00, wbregs names: MEGANETICMTX
#define R_MEGANET_DATATX 0x08000e38 // 08000e00, wbregs names: MEGANETDATTX
#define R_MEGANET_TXABORTS 0x08000e3c // 08000e00, wbregs names: MEGANETABRTS
#define R_MEGANET_DBGRX 0x08000e40 // 08000e00, wbregs names: MEGANETDBGRX
#define R_MEGANET_DBGTX 0x08000e44 // 08000e00, wbregs names: MEGANETDBGTX
#define R_DDR3_PHY 0x08001000 // 08001000, wbregs names: DDR3_PHY, DPHYSTAT0
#define R_DDR3_PHYSTAT1 0x08001004 // 08001000, wbregs names: DDR3_PHYSTAT1, DPHYSTAT1
#define R_DDR3_PHYSTAT2 0x08001008 // 08001000, wbregs names: DDR3_PHYSTAT2, DPHYSTAT2
#define R_DDR3_PHYSTAT3 0x0800100c // 08001000, wbregs names: DDR3_PHYSTAT3, DPHYSTAT3
#define R_DDR3_PHYCTRLSTAT 0x08001010 // 08001000, wbregs names: DDR3_PHYCTRLSTAT, DCTRLSTAT
#define R_DDR3_PHYRESET 0x08001044 // 08001000, wbregs names: DDR3_PHYRESET, DCTRLRESET
#define R_DDR3_PHYDBGSEL 0x0800104c // 08001000, wbregs names: DDR3_PHYDBGSEL, DCTRLDBG
// HDMI pixel clock PLL reconfiguration port
#define R_PXPLL 0x08001200 // 08001200, wbregs names: PXPLL
// I2C Controller registers
#define R_EDID 0x08001400 // 08001400, wbregs names: EDID, EDID_CTRL, EDIDCTRL
#define R_EDID_OVW 0x08001404 // 08001400, wbregs names: EDID_OVW, EDID_OVERRIDE
#define R_EDID_ADDR 0x08001408 // 08001400, wbregs names: EDID_ADDR, EDID_ADDRESS
#define R_EDID_CKCOUNT 0x0800140c // 08001400, wbregs names: EDIDCLK, EDID_CKCOUNT
// GPS clock tracker, control loop settings registers
#define R_GPS_ALPHA 0x08001410 // 08001410, wbregs names: ALPHA
#define R_GPS_BETA 0x08001414 // 08001410, wbregs names: BETA
#define R_GPS_GAMMA 0x08001418 // 08001410, wbregs names: GAMMA
#define R_GPS_STEP 0x0800141c // 08001410, wbregs names: STEP
// I2C Controller registers
#define R_I2CCPU 0x08001420 // 08001420, wbregs names: I2CCPU, I2CCPU_CTRL, I2CCPUCTRL
#define R_I2CCPU_OVW 0x08001424 // 08001420, wbregs names: I2CCPU_OVW, I2CCPU_OVERRIDE
#define R_I2CCPU_ADDR 0x08001428 // 08001420, wbregs names: I2CCPU_ADDR, I2CCPU_ADDRESS
#define R_I2CCPU_CKCOUNT 0x0800142c // 08001420, wbregs names: I2CCPUCLK, I2CCPU_CKCOUNT
#define R_I2CDMA 0x08001430 // 08001430, wbregs names: I2CDMA
#define R_I2CDMA_ADDR 0x08001434 // 08001430, wbregs names: I2CDMAADDR
#define R_I2CDMA_BASE 0x08001438 // 08001430, wbregs names: I2CDMABASE
#define R_I2CDMA_LEN 0x0800143c // 08001430, wbregs names: I2CDMALEN
#define R_OLED 0x08001440 // 08001440, wbregs names: OLED
#define R_OLED_OV 0x08001444 // 08001440, wbregs names: OLEDOV
#define R_OLED_ADDR 0x08001448 // 08001440, wbregs names: OLEDADDR
#define R_OLED_CLK 0x0800144c // 08001440, wbregs names: OLEDCLK
// RTC clock registers
#define R_CLOCK 0x08001450 // 08001450, wbregs names: CLOCK
#define R_TIMER 0x08001454 // 08001450, wbregs names: TIMER
#define R_STOPWATCH 0x08001458 // 08001450, wbregs names: STOPWATCH
#define R_CKALARM 0x0800145c // 08001450, wbregs names: ALARM, CKALARM
// GPS clock test bench registers, for measuring the clock trackers performance
#define R_GPSTB_FREQ 0x08001460 // 08001460, wbregs names: GPSFREQ
#define R_GPSTB_JUMP 0x08001464 // 08001460, wbregs names: GPSJUMP
#define R_GPSTB_ERRHI 0x08001468 // 08001460, wbregs names: ERRHI
#define R_GPSTB_ERRLO 0x0800146c // 08001460, wbregs names: ERRLO
#define R_GPSTB_COUNTHI 0x08001470 // 08001460, wbregs names: CNTHI
#define R_GPSTB_COUNTLO 0x08001474 // 08001460, wbregs names: CNTLO
#define R_GPSTB_STEPHI 0x08001478 // 08001460, wbregs names: STEPHI
#define R_GPSTB_STEPLO 0x0800147c // 08001460, wbregs names: STEPLO
// SYSCLK Clock Counter (measures clock speed)
#define R_ADCCLK 0x08001480 // 08001480, wbregs names: ADCCLK
#define R_BUILDTIME 0x08001484 // 08001484, wbregs names: BUILDTIME, BUILDTIME
#define R_BUSERR 0x08001488 // 08001488, wbregs names: BUSERR
#define R_PIC 0x0800148c // 0800148c, wbregs names: PIC
#define R_GPIO 0x08001490 // 08001490, wbregs names: GPIO, GPI, GPO
#define R_PWRCOUNT 0x08001494 // 08001494, wbregs names: PWRCOUNT
#define R_RTCDATE 0x08001498 // 08001498, wbregs names: RTCDATE, DATE
// SYSCLK Clock Counter (measures clock speed)
#define R_RXETH0CK 0x0800149c // 0800149c, wbregs names: RXETH0CK
#define R_SPIO 0x080014a0 // 080014a0, wbregs names: SPIO
// A register capturing subseconds, locked to GPS if present
#define R_SUBSECONDS 0x080014a4 // 080014a4, wbregs names: SUBSECONDS
// SYSCLK Clock Counter (measures clock speed)
#define R_TXCLK 0x080014a8 // 080014a8, wbregs names: TXCLK
#define R_VERSION 0x080014ac // 080014ac, wbregs names: VERSION
#define R_EDIDRX 0x08001500 // 08001500, wbregs names: EDIDRX
// HDMI video processing pipe registers
#define R_VIDPIPE 0x08002000 // 08002000, wbregs names: VIDPIPE, VIDCTRL
#define R_HDMIFREQ 0x08002004 // 08002000, wbregs names: HDMIFREQ
#define R_SIFREQ 0x08002008 // 08002000, wbregs names: SIFREQ
#define R_PXFREQ 0x0800200c // 08002000, wbregs names: PXFREQ
#define R_INSIZE 0x08002010 // 08002000, wbregs names: INSIZE
#define R_INPORCH 0x08002014 // 08002000, wbregs names: INPORCH
#define R_INSYNC 0x08002018 // 08002000, wbregs names: INSYNC
#define R_INRAW 0x0800201c // 08002000, wbregs names: INRAW
#define R_HDMISIZE 0x08002020 // 08002000, wbregs names: HDMISIZE
#define R_HDMIPORCH 0x08002024 // 08002000, wbregs names: HDMIPORCH
#define R_HDMISYNC 0x08002028 // 08002000, wbregs names: HDMISYNC
#define R_HDMIRAW 0x0800202c // 08002000, wbregs names: HDMIRAW
#define R_OVADDR 0x08002030 // 08002000, wbregs names: OVADDR
#define R_OVSIZE 0x08002034 // 08002000, wbregs names: OVSIZE
#define R_OVOFFSET 0x08002038 // 08002000, wbregs names: OVOFFSET
#define R_FPS 0x0800203c // 08002000, wbregs names: FPS
#define R_CAPTURE 0x08002040 // 08002000, wbregs names: VCAPTURE
#define R_CAPBASE 0x08002044 // 08002000, wbregs names: VCAPBASE
#define R_CAPWORDS 0x08002048 // 08002000, wbregs names: VCAPWORDS
#define R_CAPPOSN 0x0800204c // 08002000, wbregs names: VCAPPOSN
#define R_CAPSIZE 0x08002050 // 08002000, wbregs names: VCAPSIZE
#define R_SYNCWORD 0x08002060 // 08002000, wbregs names: VSYNCWORD
#define R_CMAP 0x08002800 // 08002000, wbregs names: CMAP
// Ethernet configuration (MDIO) port
#define R_MDIO_BMCR 0x08003000 // 08003000, wbregs names: BMCR
#define R_MDIO_BMSR 0x08003004 // 08003000, wbregs names: BMSR
#define R_MDIO_PHYIDR1 0x08003008 // 08003000, wbregs names: PHYIDR1
#define R_MDIO_PHYIDR2 0x0800300c // 08003000, wbregs names: PHYIDR2
#define R_MDIO_ANAR 0x08003010 // 08003000, wbregs names: ANAR
#define R_MDIO_ANLPAR 0x08003014 // 08003000, wbregs names: ANLPAR
#define R_MDIO_ANER 0x08003018 // 08003000, wbregs names: ANER
#define R_MDIO_ANNPTR 0x0800301c // 08003000, wbregs names: ANNPTR
#define R_MDIO_ANNPRR 0x08003020 // 08003000, wbregs names: ANNPRR
#define R_MDIO_GBCR 0x08003024 // 08003000, wbregs names: GBCR
#define R_MDIO_GBSR 0x08003028 // 08003000, wbregs names: GBSR
#define R_MDIO_MACR 0x08003034 // 08003000, wbregs names: MACR
#define R_MDIO_MAADR 0x08003038 // 08003000, wbregs names: MAADR
#define R_MDIO_GBESR 0x0800303c // 08003000, wbregs names: GBESR
#define R_MDIO_PHYCR 0x08003040 // 08003000, wbregs names: PHYCR
#define R_MDIO_PHYSR 0x08003044 // 08003000, wbregs names: PHYSR
#define R_MDIO_INER 0x08003048 // 08003000, wbregs names: INER
#define R_MDIO_INSR 0x0800304c // 08003000, wbregs names: INSR
#define R_MDIO_RXERC 0x08003060 // 08003000, wbregs names: RXERC
#define R_MDIO_LDPSR 0x0800306c // 08003000, wbregs names: LDPSR
#define R_MDIO_EPAGSR 0x08003078 // 08003000, wbregs names: EPAGSR
#define R_MDIO_PAGSEL 0x0800307c // 08003000, wbregs names: PAGSEL
#define R_XMDIO_PC1R 0x08003000 // 08003000, wbregs names: XPC1R
#define R_XMDIO_PS1R 0x08003004 // 08003000, wbregs names: XPS1R
#define R_XMDIO_EEECR 0x08003050 // 08003000, wbregs names: XEEECR
#define R_XMDIO_EEEWER 0x08003040 // 08003000, wbregs names: XEEEWER
#define R_XMDIO_EEEAR 0x080030f0 // 08003000, wbregs names: XEEEAR
#define R_XMDIO_EEELPAR 0x080030f4 // 08003000, wbregs names: XEEELPAR
#define R_XMDIO_LACR 0x08003068 // 08003000, wbregs names: XLACR
#define R_XMDIO_LCR 0x08003070 // 08003000, wbregs names: XLCR
#define R_BKRAM 0x10000000 // 10000000, wbregs names: RAM
#define R_SDRAM 0x40000000 // 40000000, wbregs names: SDRAM
// ZipCPU control/debug registers
#define R_ZIPCTRL 0x80000000 // 80000000, wbregs names: CPU, ZIPCTRL
#define R_ZIPREGS 0x80000080 // 80000000, wbregs names: ZIPREGS
#define R_ZIPS0 0x80000080 // 80000000, wbregs names: SR0
#define R_ZIPS1 0x80000084 // 80000000, wbregs names: SR1
#define R_ZIPS2 0x80000088 // 80000000, wbregs names: SR2
#define R_ZIPS3 0x8000008c // 80000000, wbregs names: SR3
#define R_ZIPS4 0x80000090 // 80000000, wbregs names: SR4
#define R_ZIPS5 0x80000094 // 80000000, wbregs names: SR5
#define R_ZIPS6 0x80000098 // 80000000, wbregs names: SR6
#define R_ZIPS7 0x8000009c // 80000000, wbregs names: SR7
#define R_ZIPS8 0x800000a0 // 80000000, wbregs names: SR8
#define R_ZIPS9 0x800000a4 // 80000000, wbregs names: SR9
#define R_ZIPS10 0x800000a8 // 80000000, wbregs names: SR10
#define R_ZIPS11 0x800000ac // 80000000, wbregs names: SR11
#define R_ZIPS12 0x800000b0 // 80000000, wbregs names: SR12
#define R_ZIPSSP 0x800000b4 // 80000000, wbregs names: SSP, SR13
#define R_ZIPCC 0x800000b8 // 80000000, wbregs names: ZIPCC, CC, SCC, SR14
#define R_ZIPPC 0x800000bc // 80000000, wbregs names: ZIPPC, PC, SPC, SR15
#define R_ZIPUSER 0x800000c0 // 80000000, wbregs names: ZIPUSER
#define R_ZIPU0 0x800000c0 // 80000000, wbregs names: UR0
#define R_ZIPU1 0x800000c4 // 80000000, wbregs names: UR1
#define R_ZIPU2 0x800000c8 // 80000000, wbregs names: UR2
#define R_ZIPU3 0x800000cc // 80000000, wbregs names: UR3
#define R_ZIPU4 0x800000d0 // 80000000, wbregs names: UR4
#define R_ZIPU5 0x800000d4 // 80000000, wbregs names: UR5
#define R_ZIPU6 0x800000d8 // 80000000, wbregs names: UR6
#define R_ZIPU7 0x800000dc // 80000000, wbregs names: UR7
#define R_ZIPU8 0x800000e0 // 80000000, wbregs names: UR8
#define R_ZIPU9 0x800000e4 // 80000000, wbregs names: UR9
#define R_ZIPU10 0x800000e8 // 80000000, wbregs names: SR10
#define R_ZIPU11 0x800000ec // 80000000, wbregs names: SR11
#define R_ZIPU12 0x800000f0 // 80000000, wbregs names: SR12
#define R_ZIPUSP 0x800000f4 // 80000000, wbregs names: USP, UR13
#define R_ZIPUCC 0x800000f8 // 80000000, wbregs names: ZIPUCC, UCC
#define R_ZIPUPC 0x800000fc // 80000000, wbregs names: ZIPUPC, UPC
#define R_ZIPSYSTEM 0x80000100 // 80000000, wbregs names: ZIPSYSTEM, ZIPSYS
#define R_ZIPWATCHDOG 0x80000104 // 80000000, wbregs names: ZIPWATCHDOG
#define R_ZIPBUSDOG 0x80000108 // 80000000, wbregs names: BUSDOG
#define R_ZIPAPIC 0x8000010c // 80000000, wbregs names: ZIPAPIC, ALTPIC
#define R_ZIPTIMERA 0x80000110 // 80000000, wbregs names: ZIPTMA, ZIPTIMERA
#define R_ZIPTIMERB 0x80000114 // 80000000, wbregs names: ZIPTMB, ZIPTIMERB
#define R_ZIPTIMERC 0x80000118 // 80000000, wbregs names: ZIPTMC, ZIPTIMERC
#define R_ZIPJIFFIES 0x8000011c // 80000000, wbregs names: ZIPJIFF
#define R_ZIPMTASK 0x80000120 // 80000000, wbregs names: ZIPMTASK
#define R_ZIPMSTALL 0x80000124 // 80000000, wbregs names: ZIPMSTALL
#define R_ZIPMPSTAL 0x80000128 // 80000000, wbregs names: ZIPMPSTAL
#define R_ZIPMINSN 0x8000012c // 80000000, wbregs names: ZIPMINSN
#define R_ZIPUTASK 0x80000130 // 80000000, wbregs names: ZIPUTASK
#define R_ZIPUSTALL 0x80000134 // 80000000, wbregs names: ZIPUSTALL
#define R_ZIPUPSTAL 0x80000138 // 80000000, wbregs names: ZIPUPSTAL
#define R_ZIPUINSN 0x8000013c // 80000000, wbregs names: ZIPUINSN
#define R_ZIPUDMAC 0x80000140 // 80000000, wbregs names: ZIPDMAC
//
// The @REGDEFS.H.DEFNS tag
//
// @REGDEFS.H.DEFNS for masters
#define BAUDRATE 1000000
#define CLKFREQHZ 100000000
// @REGDEFS.H.DEFNS for peripherals
#define FLASHBASE 0x01000000
#define FLASHLEN 0x01000000
#define FLASHLGLEN 24
//
#define FLASH_RDDELAY 2
#define FLASH_NDUMMY 6
//
#define BKRAMBASE 0x10000000
#define BKRAMLEN 0x00100000
#define SDRAMBASE 0x40000000
#define SDRAMLEN 0x40000000
// @REGDEFS.H.DEFNS at the top level
// End of definitions from REGDEFS.H.DEFNS
//
// The @REGDEFS.H.INSERT tag
//
// @REGDEFS.H.INSERT for masters
// @REGDEFS.H.INSERT for peripherals
// Flash control constants
#define QSPI_FLASH // This core and hardware support a Quad SPI flash
#define SZPAGEB 256
#define PGLENB 256
#define SZPAGEW 64
#define PGLENW 64
#define NPAGES 256
#define SECTORSZB (NPAGES * SZPAGEB) // In bytes, not words!!
#define SECTORSZW (NPAGES * SZPAGEW) // In words
#define NSECTORS 64
#define SECTOROF(A) ((A) & (-1<<16))
#define SUBSECTOROF(A) ((A) & (-1<<12))
#define PAGEOF(A) ((A) & (-1<<8))
////////////////////////////////////////////////////////////////////////////////
//
// ZipCPU register definitions
// {{{
#define CPU_GO 0x0000
#define CPU_HALT 0x0001
#define CPU_STALL 0x0002
#define CPU_STEP 0x0004
#define CPU_RESET 0x0008
#define CPU_CLRCACHE 0x0010
// (Reserved) 0x00e0
#define CPU_SLEEPING 0x0100
#define CPU_GIE 0x0200
#define CPU_INT 0x0400
#define CPU_BREAK 0x0800
#define CPU_EXINT 0xfffff000
//
#define CPU_sR0 0x0020
#define CPU_sSP 0x002d
#define CPU_sCC 0x002e
#define CPU_sPC 0x002f
#define CPU_uR0 0x0030
#define CPU_uSP 0x003d
#define CPU_uCC 0x003e
#define CPU_uPC 0x003f
#ifdef BKROM_ACCESS
#define RESET_ADDRESS @$[0x%08x](bkrom.REGBASE)
#else
#ifdef FLASH_ACCESS
#define RESET_ADDRESS 0x01600000
#else
#define RESET_ADDRESS 0x10000000
#endif // FLASH_ACCESS
#endif // BKROM_ACCESS
// }}}
// @REGDEFS.H.INSERT from the top level
typedef struct {
unsigned m_addr;
const char *m_name;
} REGNAME;
extern const REGNAME *bregs;
extern const int NREGS;
// #define NREGS (sizeof(bregs)/sizeof(bregs[0]))
extern unsigned addrdecode(const char *v);
extern const char *addrname(const unsigned v);
// End of definitions from REGDEFS.H.INSERT
#endif // REGDEFS_H