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zipcpu_tb.cpp
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////////////////////////////////////////////////////////////////////////////////
//
// Filename: zipcpu_tb.cpp
// {{{
// Project: Zip CPU -- a small, lightweight, RISC CPU soft core
//
// Purpose: A bench simulator for the CPU. Eventually, you should be
// able to give this program the name of a piece of compiled
// code to load into memory. For now, we hand assemble with the computers
// help.
//
//
// Creator: Dan Gisselquist, Ph.D.
// Gisselquist Technology, LLC
//
////////////////////////////////////////////////////////////////////////////////
// }}}
// Copyright (C) 2015--2024, Gisselquist Technology, LLC
// {{{
// This program is free software (firmware): you can redistribute it and/or
// modify it under the terms of the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or (at
// your option) any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with this program. (It's in the $(ROOT)/doc directory. Run make with no
// target there if the PDF file isn't present.) If not, see
// <http://www.gnu.org/licenses/> for a copy.
// }}}
// License: GPL, v3, as defined and found on www.gnu.org,
// {{{
// http://www.gnu.org/licenses/gpl.html
//
//
////////////////////////////////////////////////////////////////////////////////
//
// }}}
#include <signal.h>
#include <time.h>
#include <unistd.h>
#include <poll.h>
#include <sys/types.h>
#include <sys/stat.h>
#include <fcntl.h>
#include <string.h>
#include <ctype.h>
#include <ncurses.h>
#include "verilated.h"
#include "verilated_vcd_c.h"
#ifdef VM_COVERAGE
#include "verilated_cov.h"
#endif
// ZipBones includes
#ifdef ZIPBONES
#include "Vzipbones.h"
#ifdef ROOT_VERILATOR
#include "Vzipbones___024root.h"
#endif
#define SIMCLASS Vzipbones
#else
// ZipSystem includes
#define ZIPSYSTEM
#include "Vzipsystem.h"
#ifdef ROOT_VERILATOR
#include "Vzipsystem___024root.h"
#endif
#define SIMCLASS Vzipsystem
#endif
#include "testb.h"
#include "zipelf.h"
// #include "twoc.h"
// #include "qspiflashsim.h"
#include "byteswap.h"
#include "memsim.h"
#include "zopcodes.h"
#define CMD_REG 0x00
#define CMD_SREG(A) (0x80 + (A<<2))
#define CMD_GO 0
#define CMD_HALT (1<<0)
#define CMD_HALTED (1<<1)
#define CMD_STEP (1<<2)
#define CMD_RESET (1<<3)
#define CMD_CLEAR_CACHE (1<<4)
#define CMD_CATCH (1<<5)
#define CMD_SLEEP (1<<8)
#define CMD_GIE (1<<9)
#define CMD_INT (1<<10)
#define CPU_HALT CMD_HALT
#define CPU_sPC (0x80+(15<<2))
#define KEY_ESCAPE 27
#define KEY_RETURN 10
#define CTRL(X) ((X)&0x01f)
#define MAXERR 10000
// Some versions of Verilator require a prefix starting with the top level
// module name, rather than v__DOT__.... For these versions of Verilator,
// you will need to replace these variable prefixes with either
// zipsystem__DOT__...
// or
// zipbones__DOT__...
#ifdef ROOT_VERILATOR
// {{{
#ifdef ZIPBONES
#ifdef VM_COVERAGE
#define VVAR(A) rootp->zipbones__DOT____Vtogcov_ ## A
#else
#define VVAR(A) rootp->zipbones__DOT_ ## A
#endif // VM_COVERAGE
#else // Not ZIPBONES, but still under ROOT_VERILATOR
#ifdef VM_COVERAGE
#define VVAR(A) rootp->zipsystem__DOT____Vtogcov_ ## A
#else
#define VVAR(A) rootp->zipsystem__DOT_ ## A
#endif // VM_COVERAGE
#endif // ZIPBONES
// }}}
#elif defined(NEW_VERILATOR)
// NEW_VERILATOR
// {{{
#ifdef ZIPBONES
#ifdef VM_COVERAGE
#define VVAR(A) zipbones__DOT____Vtogcov_ ## A
#else
#define VVAR(A) zipbones__DOT_ ## A
#endif
#else // Not ZIPBONES, but still under NEW_VERILATOR
#ifdef VM_COVERAGE
#define VVAR(A) zipsystem__DOT____Vtogcov_ ## A
#else
#define VVAR(A) zipsystem__DOT_ ## A
#endif // VM_COVERAGE
#endif
// }}}
#else // OLD_VERILATOR used the v__DOT_ prefix
#define VVAR(A) v__DOT_ ## A
#endif
#define CPUVAR(A) VVAR(_thecpu__DOT__core__DOT_ ##A)
#ifdef OPT_DCACHE
///
// dcache
#define MEMVAR(A) VVAR(_thecpu__DOT__DATA_CACHE__DOT__mem__DOT_ ## A)
///
#elif defined(OPT_PIPELINED_BUS_ACCESS)
///
// pipemem
#define MEMVAR(A) VVAR(_thecpu__DOT__PIPELINED_MEM__DOT__domem__DOT_ ## A)
#define mem_wraddr MEMVAR(_wraddr)
#define mem_rdaddr MEMVAR(_rdaddr)
///
#else
///
// memops
#define MEMVAR(A) VVAR(_thecpu__DOT__BARE_MEM__DOT__domem__DOT_ ## A)
#endif
#define cpu_halt VVAR(_cmd_halt)
#define cmd_reset VVAR(_cmd_reset)
#define cmd_step VVAR(_cmd_step)
#ifdef ROOT_VERILATOR
#define cpu_regs VVAR(_thecpu__DOT__core__DOT__regset.m_storage)
#else
#define cpu_regs VVAR(_thecpu__DOT__core__DOT__regset)
#endif
#ifdef ZIPSYSTEM
#else
#define dbg_cyc i_dbg_cyc
#define dbg_stb i_dbg_stb
#define dbg_we i_dbg_we
#define dbg_idata i_dbg_data
#define cpu_stall i_wb_stall
#define cpu_interrupt i_ext_int
#define cpu_idata i_wb_data
#define tick_counter tickcount()
#define dbg_addr i_dbg_addr
#endif
/*
// We are just a raw CPU with memory. There is no flash.
#define LGFLASHLEN 24
#define FLASHBASE 0x01000000
#define FLASHWORDS (1<<LGFLASHLEN)
*/
#define LGRAMLEN 28
#define RAMBASE (1<<(LGRAMLEN))
#define RAMLEN (1<<(LGRAMLEN))
#define RAMWORDS ((RAMLEN)>>2)
class SPARSEMEM {
public:
bool m_valid;
unsigned int m_a, m_d;
};
// ZIPSTATE
// {{{
class ZIPSTATE {
public:
bool m_valid, m_gie, m_last_pc_valid;
unsigned int m_sR[16], m_uR[16];
#ifdef ZIPSYSTEM
unsigned int m_p[20];
#endif
unsigned int m_last_pc, m_pc, m_sp;
SPARSEMEM m_smem[5]; // Nearby stack memory
SPARSEMEM m_imem[5]; // Nearby instruction memory
ZIPSTATE(void) : m_valid(false), m_last_pc_valid(false) {}
void step(void) {
m_last_pc_valid = true;
m_last_pc = m_pc;
}
};
// }}}
extern FILE *gbl_dbgfp;
FILE *gbl_dbgfp = NULL;
// ZIPCPU_TB
// {{{
// No particular "parameters" need definition or redefinition here.
class ZIPCPU_TB : public TESTB<SIMCLASS> {
public:
// Declarations
// {{{
unsigned long m_mem_size;
MEMSIM m_mem;
// QSPIFLASHSIM m_flash;
FILE *m_dbgfp, *m_profile_fp;
bool dbg_flag, m_bomb, m_show_user_timers, m_console, m_exit;
int m_cursor, m_rcode;
unsigned long m_last_instruction_tickcount;
ZIPSTATE m_state;
// }}}
ZIPCPU_TB(void) : m_mem_size(RAMWORDS), m_mem(m_mem_size) {
// {{{
m_rcode = 0;
m_exit = false;
if (true) {
m_dbgfp = fopen("debug.txt", "w");
dbg_flag = true;
gbl_dbgfp = m_dbgfp;
} else {
m_dbgfp = NULL;
dbg_flag = false;
gbl_dbgfp = NULL;
}
if(true) {
opentrace("trace.vcd");
} else {
m_trace = NULL;
}
m_bomb = false;
m_cursor = 0;
m_show_user_timers = false;
m_last_instruction_tickcount = 0l;
if (true) {
m_profile_fp = fopen("pfile.bin","wb");
} else {
m_profile_fp = NULL;
}
// }}}
}
~ZIPCPU_TB(void) {
// {{{
if (m_dbgfp)
fclose(m_dbgfp);
if (m_profile_fp)
fclose(m_profile_fp);
if (m_trace)
m_trace->close();
// }}}
}
void reset(void) {
// m_flash.debug(false);
TESTB<SIMCLASS>::reset();
}
void step(void) {
wb_write(CMD_REG, CMD_STEP | CMD_CATCH);
m_state.step();
}
void read_raw_state(void) {
// {{{
m_state.m_valid = false;
for(int i=0; i<16; i++)
m_state.m_sR[i] = cmd_read(i);
for(int i=0; i<16; i++)
m_state.m_uR[i] = cmd_read(i+16);
#ifdef ZIPSYSTEM
for(int i=0; i<20; i++)
m_state.m_p[i] = cmd_read(i+32);
#endif
m_state.m_gie = wb_read(CMD_REG) & CMD_GIE;
m_state.m_pc = (m_state.m_gie) ? (m_state.m_uR[15]):(m_state.m_sR[15]);
m_state.m_sp = (m_state.m_gie) ? (m_state.m_uR[13]):(m_state.m_sR[13]);
if (m_state.m_last_pc_valid)
m_state.m_imem[0].m_a = m_state.m_last_pc;
else
m_state.m_imem[0].m_a = m_state.m_pc - 1;
m_state.m_imem[0].m_d = m_mem[m_state.m_imem[0].m_a & 0x0fffff];
m_state.m_imem[0].m_valid = ((m_state.m_imem[0].m_a & 0xfff00000)==0x00100000);
m_state.m_imem[1].m_a = m_state.m_pc;
m_state.m_imem[1].m_valid = ((m_state.m_imem[1].m_a & 0xfff00000)==0x00100000);
m_state.m_imem[1].m_d = m_mem[m_state.m_imem[1].m_a & 0x0fffff];
for(int i=1; i<4; i++) {
// {{{
if (!m_state.m_imem[i].m_valid) {
m_state.m_imem[i+1].m_valid = false;
m_state.m_imem[i+1].m_a = m_state.m_imem[i].m_a+1;
continue;
}
m_state.m_imem[i+1].m_a = zop_early_branch(
m_state.m_imem[i].m_a,
m_state.m_imem[i].m_d);
m_state.m_imem[i+1].m_d = m_mem[m_state.m_imem[i].m_a & 0x0fffff];
m_state.m_imem[i+1].m_valid = ((m_state.m_imem[i].m_a&0xfff00000)==0x00100000);
// }}}
}
m_state.m_smem[0].m_a = m_state.m_sp;
for(int i=1; i<5; i++)
m_state.m_smem[i].m_a = m_state.m_smem[i-1].m_a+1;
for(int i=0; i<5; i++) {
m_state.m_smem[i].m_valid =
(m_state.m_imem[i].m_a > 0x10000);
m_state.m_smem[i].m_d = m_mem[m_state.m_imem[i].m_a & 0x0fffff];
}
m_state.m_valid = true;
// }}}
}
void read_raw_state_cheating(void) {
// {{{
m_state.m_valid = false;
for(int i=0; i<16; i++)
m_state.m_sR[i] = m_core->cpu_regs[i];
m_state.m_sR[14] = (m_state.m_sR[14]&0xffffe000)|m_core->w_iflags;
m_state.m_sR[15] = m_core->cpu_ipc;
for(int i=0; i<16; i++)
m_state.m_uR[i] = m_core->cpu_regs[i+16];
m_state.m_uR[14] = (m_state.m_uR[14]&0xffffe000)|m_core->w_uflags;
m_state.m_uR[15] = m_core->cpu_upc;
m_state.m_gie = m_core->r_gie;
m_state.m_pc = (m_state.m_gie) ? (m_state.m_uR[15]):(m_state.m_sR[15]);
m_state.m_sp = (m_state.m_gie) ? (m_state.m_uR[13]):(m_state.m_sR[13]);
#ifdef ZIPSYSTEM
// {{{
m_state.m_p[0] = m_core->pic_data;
m_state.m_p[1] = m_core->watchdog;
if (!m_show_user_timers) {
m_state.m_p[2] = m_core->watchbus;
} else {
// The last bus error address
m_state.m_p[2] = m_core->wdbus_data;
}
m_state.m_p[3] = m_core->alt_int_state;
m_state.m_p[4] = m_core->timer_a;
m_state.m_p[5] = m_core->timer_b;
m_state.m_p[6] = m_core->timer_c;
m_state.m_p[7] = m_core->jiffies;
m_state.m_p[ 8] = m_core->utc_data;
m_state.m_p[ 9] = m_core->uoc_data;
m_state.m_p[10] = m_core->upc_data;
m_state.m_p[11] = m_core->uic_data;
m_state.m_p[12] = m_core->mtc_data;
m_state.m_p[13] = m_core->moc_data;
m_state.m_p[14] = m_core->mpc_data;
m_state.m_p[15] = m_core->mic_data;
// }}}
#endif
// }}}
}
void showval(int y, int x, const char *lbl, unsigned int v, bool c) {
// {{{
if (c)
mvprintw(y,x, ">%s> 0x%08x<", lbl, v);
else
mvprintw(y,x, " %s: 0x%08x ", lbl, v);
// }}}
}
void dispreg(int y, int x, const char *n, unsigned int v, bool c) {
// {{{
// 4,4,8,1 = 17 of 20, +3 = 19
if (c)
mvprintw(y, x, ">%s> 0x%08x<", n, v);
else
mvprintw(y, x, " %s: 0x%08x ", n, v);
// }}}
}
void dbgreg(FILE *fp, int id, const char *n, unsigned int v) {
// {{{
/*
if ((id == 14)||(id == 14+16)) {
//char buf[64];
//fprintf(fp, " %s:",
fprintf(fp, " %s: 0x%08x ", n, v);
} else
*/
fprintf(fp, " %s: 0x%08x ", n, v);
// }}}
}
void showreg(int y, int x, const char *n, int r, bool c) {
// {{{
if (r < 16)
dispreg(y, x, n, m_state.m_sR[r], c);
else
dispreg(y, x, n, m_state.m_uR[r-16], c);
move(y,x+17);
#ifdef OPT_PIPELINED
addch( ((r == (int)(dcd_Aid()&0x01f))&&(m_core->dcd_valid)
&&(m_core->dcd_rA))
?'a':((c)?'<':' '));
addch( ((r == (int)(dcd_Bid()&0x01f))&&(m_core->dcd_valid)
&&(m_core->dcd_rB))
?'b':' ');
addch( ((r == m_core->wr_reg_id)
&&(m_core->wr_reg_ce))
?'W':' ');
#else
addch( ((r == m_core->wr_reg_id)
&&(m_core->wr_reg_ce))
?'W':((c)?'<':' '));
#endif
// }}}
}
void showins(int y, const char *lbl, const int ce, const int valid,
const int gie, const int stall, const unsigned int pc,
const bool phase) {
// {{{
char la[80], lb[80];
unsigned iv = m_mem[pc >> 2];
bool cisw = (iv & 0x80000000)?true:false;
if (ce)
mvprintw(y, 0, "Ck ");
else
mvprintw(y, 0, " ");
if (stall)
printw("Stl ");
else
printw(" ");
printw("%s%c 0x%08x", lbl, ((cisw)&&(phase))?'/':':', pc);
if (valid) {
if (gie) attroff(A_BOLD);
else attron(A_BOLD);
zipi_to_double_string(pc, iv, la, lb);
if ((!cisw)||(phase))
printw(" %-24s", la);
else
printw(" %-24s", lb);
} else {
attroff(A_BOLD);
printw(" (0x%08x)%28s", iv,"");
}
attroff(A_BOLD);
// }}}
}
void dbgins(const char *lbl, const int ce, const int valid,
const int gie, const int stall, const unsigned int pc,
const bool phase, const bool illegal) {
// {{{
char la[80], lb[80];
if (!m_dbgfp)
return;
if (ce)
fprintf(m_dbgfp, "%s Ck ", lbl);
else
fprintf(m_dbgfp, "%s ", lbl);
if (stall)
fprintf(m_dbgfp, "Stl ");
else
fprintf(m_dbgfp, " ");
fprintf(m_dbgfp, "0x%08x%s: ", pc, (phase)?"/P":" ");
if (valid) {
zipi_to_double_string(pc, m_mem[pc>>2], la, lb);
if ((phase)||((m_mem[pc>>2]&0x80000000)==0))
fprintf(m_dbgfp, " %-24s", la);
else
fprintf(m_dbgfp, " %-24s", lb);
} else {
fprintf(m_dbgfp, " (0x%08x)", m_mem[pc]);
} if (illegal)
fprintf(m_dbgfp, " (Illegal)");
fprintf(m_dbgfp, "\n");
// }}}
}
void show_state(void) {
// {{{
int ln= 0;
read_raw_state_cheating();
mvprintw(ln,0, "Peripherals-SS"); ln++;
printw(" %s",
// (m_core->pf_illegal)?"PI":" ",
(m_core->dcd_illegal)?"DI":" "
);
#ifdef OPT_EARLY_BRANCHING
printw(" %s",
(m_core->early_branch)?"EB":" ");
if (m_core->early_branch)
printw(" 0x%08x", m_core->early_branch_pc);
else printw(" %10s", "");
// printw(" %s", (m_core->v__DOT__thecpu__DOT____Vcellinp__pf____pinNumber3)?"-> P3":" ");
#endif
#ifdef ZIPSYSTEM
showval(ln, 0, "PIC ", m_state.m_p[0], (m_cursor==0));
showval(ln,20, "WDT ", m_state.m_p[1], (m_cursor==1));
// showval(ln,40, "CACH", m_core->v__DOT__manualcache__DOT__cache_base, (m_cursor==2));
if (!m_show_user_timers) {
showval(ln,40, "WBUS", m_core->watchbus, false);
} else {
// showval(ln,40, "UBUS", m_core->v__DOT__r_wdbus_data, false);
showval(ln,40, "UBUS", m_core->watchbus, false);
}
showval(ln,60, "PIC2", m_state.m_p[3], (m_cursor==3));
ln++;
showval(ln, 0, "TMRA", m_state.m_p[4], (m_cursor==4));
showval(ln,20, "TMRB", m_state.m_p[5], (m_cursor==5));
showval(ln,40, "TMRC", m_state.m_p[6], (m_cursor==6));
showval(ln,60, "JIF ", m_state.m_p[7], (m_cursor==7));
if (!m_show_user_timers) {
// {{{
ln++;
showval(ln, 0, "MTSK", m_state.m_p[12], (m_cursor==8));
showval(ln,20, "MOST", m_state.m_p[13], (m_cursor==9));
showval(ln,40, "MPST", m_state.m_p[14], (m_cursor==10));
showval(ln,60, "MICT", m_state.m_p[15], (m_cursor==11));
// }}}
} else {
// {{{
ln++;
showval(ln, 0, "UTSK", m_state.m_p[ 8], (m_cursor==8));
showval(ln,20, "UOST", m_state.m_p[ 9], (m_cursor==9));
showval(ln,40, "UPST", m_state.m_p[10], (m_cursor==10));
showval(ln,60, "UICT", m_state.m_p[11], (m_cursor==11));
// }}}
}
#else
ln += 2;
#endif
ln++;
mvprintw(ln, 40, "%s %s",
(m_core->cpu_halt)? "CPU-HALT": " ",
(m_core->cmd_reset)?"CPU-RESET":" "); ln++;
mvprintw(ln, 40, "%s %s %s %s %s",
(m_core->cpu_halt)? "HALT": " ",
(m_core->cmd_reset)?"RESET":" ",
(m_core->cmd_step)? "STEP" :" ",
// (m_core->cmd_addr)&0x3f,
(m_core->master_ce)? "*CE*" :"(ce)",
(m_core->cmd_reset)? "*RST*" :"(rst)");
if (m_core->r_gie)
attroff(A_BOLD);
else
attron(A_BOLD);
mvprintw(ln, 0, "Supervisor Registers");
ln++;
// Supervisor registers
// {{{
showreg(ln, 0, "sR0 ", 0, (m_cursor==12));
showreg(ln,20, "sR1 ", 1, (m_cursor==13));
showreg(ln,40, "sR2 ", 2, (m_cursor==14));
showreg(ln,60, "sR3 ", 3, (m_cursor==15)); ln++;
showreg(ln, 0, "sR4 ", 4, (m_cursor==16));
showreg(ln,20, "sR5 ", 5, (m_cursor==17));
showreg(ln,40, "sR6 ", 6, (m_cursor==18));
showreg(ln,60, "sR7 ", 7, (m_cursor==19)); ln++;
showreg(ln, 0, "sR8 ", 8, (m_cursor==20));
showreg(ln,20, "sR9 ", 9, (m_cursor==21));
showreg(ln,40, "sR10", 10, (m_cursor==22));
showreg(ln,60, "sR11", 11, (m_cursor==23)); ln++;
showreg(ln, 0, "sR12", 12, (m_cursor==24));
showreg(ln,20, "sSP ", 13, (m_cursor==25));
unsigned int cc = m_state.m_sR[14];
if (false) {
mvprintw(ln,40, "%ssCC : 0x%08x",
(m_cursor==26)?">":" ", cc);
} else {
char cbuf[32];
sprintf(cbuf, "%ssCC :%s%s%s%s%s%s%s",
(m_cursor==26)?">":" ",
(cc&0x01000)?"FE":"",
(cc&0x00800)?"DE":"",
(cc&0x00400)?"BE":"",
(cc&0x00200)?"TP":"",
(cc&0x00100)?"IL":"",
(cc&0x00080)?"BK":"",
((m_state.m_gie==0)&&(cc&0x010))?"HLT":"");
mvprintw(ln,40, "%-14s",cbuf);
mvprintw(ln, 54, "%s%s%s%s",
(cc&8)?"V":" ",
(cc&4)?"N":" ",
(cc&2)?"C":" ",
(cc&1)?"Z":" ");
}
showval(ln,60, "sPC ", m_state.m_sR[15], (m_cursor==27));
mvprintw(ln,60,"%s",
(m_core->wr_reg_id == 0x0e)
&&(m_core->wr_reg_ce)
?"V"
:(((m_core->wr_flags_ce)
&&(!m_core->alu_gie))?"+"
:" "));
ln++;
// }}}
// User registers
// {{{
if (m_core->r_gie)
attron(A_BOLD);
else
attroff(A_BOLD);
mvprintw(ln, 0, "User Registers");
mvprintw(ln, 42, "DCDR=%02x %s%s",
m_core->dcdR,
(m_core->dcd_wR)?"W":" ",
(m_core->dcd_wF)?"F":" ");
mvprintw(ln, 62, "OPR =%02x %s%s",
m_core->op_R,
(m_core->op_wR)?"W":" ",
(m_core->op_wF)?"F":" ");
ln++;
showreg(ln, 0, "uR0 ", 16, (m_cursor==28));
showreg(ln,20, "uR1 ", 17, (m_cursor==29));
showreg(ln,40, "uR2 ", 18, (m_cursor==30));
showreg(ln,60, "uR3 ", 19, (m_cursor==31)); ln++;
showreg(ln, 0, "uR4 ", 20, (m_cursor==32));
showreg(ln,20, "uR5 ", 21, (m_cursor==33));
showreg(ln,40, "uR6 ", 22, (m_cursor==34));
showreg(ln,60, "uR7 ", 23, (m_cursor==35)); ln++;
showreg(ln, 0, "uR8 ", 24, (m_cursor==36));
showreg(ln,20, "uR9 ", 25, (m_cursor==37));
showreg(ln,40, "uR10", 26, (m_cursor==38));
showreg(ln,60, "uR11", 27, (m_cursor==39)); ln++;
showreg(ln, 0, "uR12", 28, (m_cursor==40));
showreg(ln,20, "uSP ", 29, (m_cursor==41));
cc = m_state.m_uR[14];
if (false) {
mvprintw(ln,40, "%cuCC : 0x%08x",
(m_cursor == 42)?'>':' ', cc);
} else {
char cbuf[32];
sprintf(cbuf, "%cuCC :%s%s%s%s%s%s%s",
(m_cursor == 42)?'>':' ',
(cc & 0x1000)?"FE":"",
(cc & 0x0800)?"DE":"",
(cc & 0x0400)?"BE":"",
(cc & 0x0200)?"TP":"",
(cc & 0x0100)?"IL":"",
(cc & 0x0040)?"ST":"",
((m_state.m_gie)&&(cc & 0x010))?"SL":"");
mvprintw(ln,40, "%-14s",cbuf);
mvprintw(ln, 54, "%s%s%s%s",
(cc&8)?"V":" ",
(cc&4)?"N":" ",
(cc&2)?"C":" ",
(cc&1)?"Z":" ");
}
showval(ln,60, "uPC ", m_state.m_uR[15], (m_cursor==43));
mvprintw(ln,60,"%s",
(m_core->wr_reg_id == 0x1e)
&&(m_core->wr_reg_ce)
?"V"
:(((m_core->wr_flags_ce)
&&(m_core->alu_gie))?"+"
:" "));
attroff(A_BOLD);
ln+=1;
// }}}
// Prefetch data line
// {{{
ln++;
mvprintw(ln, 0, "PF BUS: %3s %3s %s @0x%08x[0x%08x] -> %s %s %08x",
(m_core->pf_cyc)?"CYC":" ",
(m_core->pf_stb)?"STB":" ",
" ", // (m_core->pf_we )?"WE":" ",
(m_core->pf_addr),
0, // (m_core->v__DOT__thecpu__DOT__pf_data),
(m_core->pf_ack)?"ACK":" ",
" ",//(m_core->v__DOT__thecpu__DOT__pf_stall)?"STL":" ",
(m_core->cpu_idata)); ln++;
// }}}
// Data bus info
// {{{
mvprintw(ln, 0, "MEMBUS: %3s %3s %s @0x%08x[0x%08x] -> %s %s %08x",
(m_core->wb_cyc_gbl)?"GCY"
:((m_core->wb_cyc_lcl)?"LCY":" "),
(m_core->mem_stb_gbl)?"GSB"
:((m_core->mem_stb_lcl)?"LSB":" "),
(m_core->mem_we )?"WE":" ",
(m_core->mem_addr<<2),
(m_core->mem_data),
(m_core->mem_ack)?"ACK":" ",
(m_core->mem_stall)?"STL":" ",
(m_core->mem_result));
// #define OPT_PIPELINED_BUS_ACCESS
#ifdef OPT_PIPELINED_BUS_ACCESS
#ifndef OPT_DCACHE
printw(" %x%x%c%c",
(m_core->mem_wraddr),
(m_core->mem_rdaddr),
(m_core->op_pipe)?'P':'-',
(mem_pipe_stalled())?'S':'-'); ln++;
#else
ln++;
#endif
#else
ln++;
#endif
// }}}
// The outgoing bus info
// {{{
mvprintw(ln, 0, "SYSBS%c: %3s %3s %s @0x%08x[0x%08x] -> %s %s %08x %s",
(m_core->pformem_owner)?'M':'P',
(m_core->o_wb_cyc)?"CYC":" ",
(m_core->o_wb_stb)?"STB":" ",
(m_core->o_wb_we )?"WE":" ",
(m_core->o_wb_addr<<2),
(m_core->o_wb_data),
(m_core->i_wb_ack)?"ACK":" ",
(m_core->i_wb_stall)?"STL":" ",
(m_core->i_wb_data),
(m_core->i_wb_err)?"(ER!)":" "); ln+=2;
#ifdef OPT_PIPELINED_BUS_ACCESS
mvprintw(ln-1, 0, "Mem CE: %d = %d%d%d%d%d, stall: %d = %d%d(%d|%d%d|..)",
(m_core->mem_ce),
(m_core->master_ce), //1
(m_core->op_valid_mem), //0
(!m_core->new_pc), //1
// (!m_core->clear_pipeline), //1
(m_core->set_cond), //1
(!mem_stalled()), //1
(mem_stalled()),
(m_core->op_valid_mem),
(m_core->master_ce),
(mem_pipe_stalled()),
(!m_core->op_pipe),
(m_core->mem_busy)
);
printw(" op_pipe = %d", m_core->dcd_pipe);
// mvprintw(4,4,"r_dcdI = 0x%06x",
// (m_core->v__DOT__thecpu__DOT__dcdI)&0x0ffffff);
#endif
// }}}
mvprintw(4,42,"0x%08x", m_core->pf_instruction);
/*
#ifdef OPT_SINGLE_CYCLE
printw(" A:%c%c B:%c%c",
(m_core->op_A_alu)?'A':'-',
(m_core->op_A_mem)?'M':'-',
(m_core->op_B_alu)?'A':'-',
(m_core->op_B_mem)?'M':'-');
#else
printw(" A:xx B:xx");
#endif
*/
printw(" PFPC=%08x", m_core->pf_pc);
showins(ln, "I ",
// {{{
#ifdef OPT_PIPELINED
!m_core->dcd_stalled,
#else
1,
#endif
m_core->pf_valid,
//m_core->v__DOT__thecpu__DOT__instruction_gie,
m_core->r_gie,
0,
(m_core->pf_instruction_pc),
true); ln++;
// m_core->pf_pc); ln++;
// }}}
showins(ln, "Dc",
// {{{
m_core->dcd_ce, m_core->dcd_valid,
m_core->dcd_gie,
#ifdef OPT_PIPELINED
m_core->dcd_stalled,
#else
0,
#endif
#ifdef OPT_CIS
((m_core->dcd_phase) ?
(m_core->dcd_pc+2):m_core->dcd_pc) -4,
m_core->dcd_phase
#else
m_core->dcd_pc - 4,
false
#endif
); ln++;
if (m_core->dcd_illegal)
mvprintw(ln-1,10,"I");
else if (m_core->dcd_M)
mvprintw(ln-1,10,"M");
// }}}
showins(ln, "Op",
// {{{
m_core->op_ce,
m_core->op_valid,
m_core->op_gie,
#ifdef op_stall
m_core->op_stall,
#else
0,
#endif
#ifdef OPT_CIS
m_core->op_pc-4+((m_core->op_phase)?2:0),
m_core->op_phase
#else
m_core->op_pc-4, false
#endif
); ln++;
if (m_core->op_illegal)
mvprintw(ln-1,10,"I");
else if (m_core->op_valid_mem)
mvprintw(ln-1,10,"M");
else if (m_core->op_valid_alu)
mvprintw(ln-1,10,"A");
// }}}
if (m_core->op_valid_mem) {
showins(ln, "Mm",
// {{{
m_core->mem_ce,
m_core->mem_pc_valid,
m_core->alu_gie,
#ifdef OPT_PIPELINED
m_core->mem_stall,
#else
0,
#endif
alu_pc_fn(),
#ifdef OPT_CIS
m_core->alu_phase
#else
false
#endif
);
// }}}
} else {
showins(ln, "Al",
// {{{
m_core->alu_ce,
m_core->alu_pc_valid,
m_core->alu_gie,
#ifdef OPT_PIPELINED
alu_stall(),
#else
0,
#endif
alu_pc_fn(),
#ifdef OPT_CIS
m_core->alu_phase
#else
false
#endif
);
// }}}
} ln++;
// Write-back
// {{{
if (m_core->wr_reg_ce)
mvprintw(ln-1,10,"W");
else if (m_core->alu_valid)
mvprintw(ln-1,10,(m_core->alu_wR)?"w":"V");
else if (m_core->mem_valid)
mvprintw(ln-1,10,"v");
else if (m_core->alu_illegal)
mvprintw(ln-1,10,"I");
// }}}
// else if (m_core->v__DOT__thecpu__DOT__alu_illegal_op)
// mvprintw(ln-1,10,"i");
mvprintw(ln-5, 65,"%s %s",
(m_core->op_break)?"OB":" ",
(m_core->new_pc)?"CLRP":" ");
mvprintw(ln-4, 48,
(m_core->new_pc)?"new-pc":" ");
printw("(%s:%02x,%x)",
(m_core->set_cond)?"SET":" ",
(m_core->op_F&0x0ff),
(m_core->op_gie)
? (m_core->w_uflags)
: (m_core->w_iflags));
printw("(%s%s%s:%02x)",
(m_core->op_wF)?"OF":" ",
(m_core->alu_wF)?"FL":" ",
(m_core->wr_flags_ce)?"W":" ",
(m_core->alu_flags));
#ifdef OPT_PIPELINED
mvprintw(ln-3, 48, "Op(%x)%8x,%8x->",
m_core->op_opn,
m_core->op_Aid, m_core->op_Bid);
#else
mvprintw(ln-3, 48, "");
#endif
if (m_core->alu_valid)
printw("%08x", m_core->alu_result);
else
printw("%8s","");
mvprintw(ln-1, 48, "%s%s%s ",
(m_core->alu_valid)?"A"
:((m_core->alu_busy)?"a":" "),
#ifdef OPT_DIVIDE
(m_core->div_valid)?"D"
:((m_core->div_busy)?"d":" "),
(m_core->div_valid)?"F"
:((m_core->div_busy)?"f":" ")
#else
" ", " "
#endif
);
if ((m_core->mem_ce)||(m_core->mem_valid)) {
printw("MEM: %s%s %s%s %s %-5s",
(m_core->op_valid_mem)?"M":" ",
(m_core->mem_ce)?"CE":" ",
(m_core->mem_we)?"Wr ":"Rd ",
(mem_stalled())?"PIPE":" ",
(m_core->mem_valid)?"V":" ",
zip_regstr[(m_core->mem_wreg&0x1f)^0x10]);
} else {
printw("%18s", "");
}
// }}}