Find solution to translate values to strings for Symbiyosys vcd files #254
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Even if reading and altering VCD files was in scope for nMigen (which I don't think it is), the pyvcd library we are using does not support reading VCD files. I believe that the appropriate solution for this is altering SymbiYosys such that it would support symbolic mappings, one way or another. |
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Do the symbolic names carry over from Python to the IL that Symbiyosys uses? |
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Right now that only happens for the A proper solution for this issue is quite challenging. Your suggestion of post-processing VCD files is actually not that bad, but there is the very real problem that we can't easily implement it. |
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I've looked closer at what SymbiYosys is doing. I believe there is a solution that is fairly elegant, would benefit everyone in FOSS FPGA community, and would solve 90% of the problem here. That is:
Would you be interested in tackling this? I could provide guidance and/or review of Yosys patches. |
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I could try. But I wouldn't even start unless I knew such a feature would be accepted into yosys. |
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I'm confident it would. SystemVerilog features in general are something Yosys is sorely lacking. |
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It seems like this has been tried several times already: YosysHQ/yosys#248 so I'm hesitant to spend a lot of time on it. |
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@RobertBaruch You could try a Yosys plugin? FYI -- Google also recently released https://github.com/google/verible which is a SystemVerilog parser, linter and code formatter. It does a pretty good job at https://github.com/SymbiFlow/sv-tests but would still need quite a bit of work to hook into Yosys for synthesis. @hzeller is currently looking at what is needed to make that happen. |
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@RobertBaruch Looks like we can skip doing anything about SystemVerilog then, and only add an attribute. What do you think? |
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Perhaps a good starting place would be |
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I've asked Clifford what would be the best approach here, your suggestion vs an attribute. |
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@RobertBaruch As I expected Clifford thinks this should be done using just attributes. |
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@RobertBaruch Friendly ping--have you looked into implementing this? |
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I have some time next week that I can devote to working on this. |
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Excellent, thanks! |
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I did find where the traces for cover mode are written (backends/smt2/smtio.py), and where the actual value is written (bv2bin), but that value appears to come from another process, No clue where that is, or whether those values are always assumed to be integers. Thoughts? |
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(and really, considering Clifford wrote yosys, wouldn't he be in the best position to just solve this in, like, a few minutes?) |
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I've written up a proposal at YosysHQ/yosys#1594. Hopefully this will start a discussion about the feature, and whether it's even feasible in yosys. |
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Thanks. |
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@RobertBaruch Yosys now has enum support! |
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This is no longer gated on upstream since YosysHQ/yosys#1642 was merged. It should be fairly straightforward to add support for RTLIL enum representation to nMigen, but I have a question about the syntax (YosysHQ/yosys#1594 (comment)). |
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Proposed new syntax in YosysHQ/yosys#1918. |
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The new syntax was accepted. |
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And nMigen now translates the attributes. E.g.: import enum
from nmigen import *
from nmigen.back import verilog
class Color(enum.IntEnum):
RED = 1
GREEN = 2
BLUE = 3
color = Signal(Color)
print(verilog.convert(Module(), ports=[color]))/* Generated by Yosys 0.9+2406 (git sha1 88c622b8f, clang 7.0.1-8 -fPIC -Os) */
(* generator = "nMigen" *)
(* top = 1 *)
(* \nmigen.hierarchy = "top" *)
module top(color);
(* enum_base_type = "Color" *)
(* enum_value_01 = "RED" *)
(* enum_value_10 = "GREEN" *)
(* enum_value_11 = "BLUE" *)
(* src = "bug.py:12" *)
input [1:0] color;
endmodule |
Monday Oct 14, 2019 at 14:23 GMT
Originally opened as m-labs/nmigen#254
When dumping the result of covers and counterexamples, Symbiyosys writes
.vcdfiles. However, any signals that were enums or FSM states are no longer strings, but just plain old binary.In
gtkwave, it's possible to select a signal and then Edit > Data Format > Translate Filter File. You can then select a filter file, which is just a map of original value to string value:The configuration can also be saved in a
.gtkwfile. However, this only affects displayed signals. If you delete the signal and display it again, it is not translated. This is horrible.Proposal:
Better might be to just go into the
vcdfile and edit the values. Although it would require an extra step, I wouldn't object to something like this:This would parse the input
vcdfile, replace numeric values with string values for enum and fsm states, and output the result.The text was updated successfully, but these errors were encountered: