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Computer Architecture - Archi2017_Project3

MIPS Cache-Memory-Page_Table Simulator

  • Based on the single-cycle CPU simulator, implement a MIPS CPU simulator with memory hierarchy, Translation-Lookaside Buffer (TLB), and virtual page table mechanism.
  • Design your own test case to verify the functionality of the memory hierarchy configuration.

Description

  • reduced MIPS R3000 ISA

Build Environment

  • Ubuntu 16.04.1 LTS
  • gcc 5.4.0