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Add design: Rocket Linux LiteX SoC with LiteDRAM and LiteEth (50T) #153

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HackerFoo opened this issue Jun 16, 2020 · 1 comment
Open

Add design: Rocket Linux LiteX SoC with LiteDRAM and LiteEth (50T) #153

HackerFoo opened this issue Jun 16, 2020 · 1 comment
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designs Related to designs being used to evaluate the performance in the FPGA Tool Perf enhancement New feature or request

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@HackerFoo HackerFoo changed the title Add design: Rocket Linux LiteX SoC with LiteDRAM and LiteEth Add design: Rocket Linux LiteX SoC with LiteDRAM and LiteEth (50T) Jun 17, 2020
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Related issue: timvideos/litex-buildenv#466

@HackerFoo HackerFoo self-assigned this Jun 23, 2020
@mithro mithro added enhancement New feature or request designs Related to designs being used to evaluate the performance in the FPGA Tool Perf labels Jun 25, 2020
pawelsag pushed a commit to antmicro/fpga-tool-perf that referenced this issue May 28, 2021
@imphil
Veriblelint: Support waivers
e84cc39 
Since chipsalliance/verible#293 Verible lint supports
(multiple) waiver files; add support for that to edalize.

I didn't add any version detection for Verible since we're currently
assuming `master` of Verible for edalize, as long as Verible hasn't done
a stable release yet.

Fixes chipsalliance#153
@HackerFoo HackerFoo removed their assignment Jun 23, 2021
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@mithro @HackerFoo