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Copy path00004-add-u-boot-stm32mp157a-sodimm2-mx.patch
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00004-add-u-boot-stm32mp157a-sodimm2-mx.patch
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diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 83677c3d4f..e04fb68ce6 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -959,7 +959,8 @@ dtb-$(CONFIG_STM32MP15x) += \
stm32mp157f-ed1.dtb \
stm32mp157f-ev1.dtb \
stm32mp15xx-dhcom-pdk2.dtb \
- stm32mp15xx-dhcor-avenger96.dtb
+ stm32mp15xx-dhcor-avenger96.dtb \
+ stm32mp157a-sodimm2-mx.dtb
dtb-$(CONFIG_SOC_K3_AM6) += k3-am654-base-board.dtb k3-am654-r5-base-board.dtb
dtb-$(CONFIG_SOC_K3_J721E) += k3-j721e-common-proc-board.dtb \
diff --git a/arch/arm/dts/stm32mp15-mx.dtsi b/arch/arm/dts/stm32mp15-mx.dtsi
new file mode 100644
index 0000000000..2b1e690de6
--- /dev/null
+++ b/arch/arm/dts/stm32mp15-mx.dtsi
@@ -0,0 +1,119 @@
+/*
+ * Copyright (C) 2015-2018, STMicroelectronics - All Rights Reserved
+ *
+ * SPDX-License-Identifier: GPL-2.0+ BSD-3-Clause
+ *
+ */
+
+/*
+ * File generated by STMicroelectronics STM32CubeMX DDR Tool for MPUs
+ * DDR type: DDR3 / DDR3L
+ * DDR width: 32bits
+ * DDR density: 8Gb
+ * System frequency: 533000kHz
+ * Relaxed Timing Mode: false
+ * Address mapping type: RBC
+ *
+ * Save Date: 2022.02.21, save Time: 13:47:46
+ */
+
+#define DDR_MEM_NAME "DDR3-DDR3L 32bits 533000kHz"
+#define DDR_MEM_SPEED 533000
+#define DDR_MEM_SIZE 0x40000000
+
+#define DDR_MSTR 0x00040401
+#define DDR_MRCTRL0 0x00000010
+#define DDR_MRCTRL1 0x00000000
+#define DDR_DERATEEN 0x00000000
+#define DDR_DERATEINT 0x00800000
+#define DDR_PWRCTL 0x00000000
+#define DDR_PWRTMG 0x00400010
+#define DDR_HWLPCTL 0x00000000
+#define DDR_RFSHCTL0 0x00210000
+#define DDR_RFSHCTL3 0x00000000
+#define DDR_RFSHTMG 0x0081008B
+#define DDR_CRCPARCTL0 0x00000000
+#define DDR_DRAMTMG0 0x121B2414
+#define DDR_DRAMTMG1 0x000A041C
+#define DDR_DRAMTMG2 0x0608090F
+#define DDR_DRAMTMG3 0x0050400C
+#define DDR_DRAMTMG4 0x08040608
+#define DDR_DRAMTMG5 0x06060403
+#define DDR_DRAMTMG6 0x02020002
+#define DDR_DRAMTMG7 0x00000202
+#define DDR_DRAMTMG8 0x00001005
+#define DDR_DRAMTMG14 0x000000A0
+#define DDR_ZQCTL0 0xC2000040
+#define DDR_DFITMG0 0x02060105
+#define DDR_DFITMG1 0x00000202
+#define DDR_DFILPCFG0 0x07000000
+#define DDR_DFIUPD0 0xC0400003
+#define DDR_DFIUPD1 0x00000000
+#define DDR_DFIUPD2 0x00000000
+#define DDR_DFIPHYMSTR 0x00000000
+#define DDR_ODTCFG 0x06000600
+#define DDR_ODTMAP 0x00000001
+#define DDR_SCHED 0x00000C01
+#define DDR_SCHED1 0x00000000
+#define DDR_PERFHPR1 0x01000001
+#define DDR_PERFLPR1 0x08000200
+#define DDR_PERFWR1 0x08000400
+#define DDR_DBG0 0x00000000
+#define DDR_DBG1 0x00000000
+#define DDR_DBGCMD 0x00000000
+#define DDR_POISONCFG 0x00000000
+#define DDR_PCCFG 0x00000010
+#define DDR_PCFGR_0 0x00010000
+#define DDR_PCFGW_0 0x00000000
+#define DDR_PCFGQOS0_0 0x02100C03
+#define DDR_PCFGQOS1_0 0x00800100
+#define DDR_PCFGWQOS0_0 0x01100C03
+#define DDR_PCFGWQOS1_0 0x01000200
+#define DDR_PCFGR_1 0x00010000
+#define DDR_PCFGW_1 0x00000000
+#define DDR_PCFGQOS0_1 0x02100C03
+#define DDR_PCFGQOS1_1 0x00800040
+#define DDR_PCFGWQOS0_1 0x01100C03
+#define DDR_PCFGWQOS1_1 0x01000200
+#define DDR_ADDRMAP1 0x00080808
+#define DDR_ADDRMAP2 0x00000000
+#define DDR_ADDRMAP3 0x00000000
+#define DDR_ADDRMAP4 0x00001F1F
+#define DDR_ADDRMAP5 0x07070707
+#define DDR_ADDRMAP6 0x0F070707
+#define DDR_ADDRMAP9 0x00000000
+#define DDR_ADDRMAP10 0x00000000
+#define DDR_ADDRMAP11 0x00000000
+#define DDR_PGCR 0x01442E02
+#define DDR_PTR0 0x0022AA5B
+#define DDR_PTR1 0x04841104
+#define DDR_PTR2 0x042DA068
+#define DDR_ACIOCR 0x10400812
+#define DDR_DXCCR 0x00000C40
+#define DDR_DSGCR 0xF200011F
+#define DDR_DCR 0x0000000B
+#define DDR_DTPR0 0x38D488D0
+#define DDR_DTPR1 0x098B00D8
+#define DDR_DTPR2 0x10023600
+#define DDR_MR0 0x00000840
+#define DDR_MR1 0x00000000
+#define DDR_MR2 0x00000208
+#define DDR_MR3 0x00000000
+#define DDR_ODTCR 0x00010000
+#define DDR_ZQ0CR1 0x00000038
+#define DDR_DX0GCR 0x0000CE81
+#define DDR_DX0DLLCR 0x40000000
+#define DDR_DX0DQTR 0xFFFFFFFF
+#define DDR_DX0DQSTR 0x3DB02000
+#define DDR_DX1GCR 0x0000CE81
+#define DDR_DX1DLLCR 0x40000000
+#define DDR_DX1DQTR 0xFFFFFFFF
+#define DDR_DX1DQSTR 0x3DB02000
+#define DDR_DX2GCR 0x0000CE81
+#define DDR_DX2DLLCR 0x40000000
+#define DDR_DX2DQTR 0xFFFFFFFF
+#define DDR_DX2DQSTR 0x3DB02000
+#define DDR_DX3GCR 0x0000CE81
+#define DDR_DX3DLLCR 0x40000000
+#define DDR_DX3DQTR 0xFFFFFFFF
+#define DDR_DX3DQSTR 0x3DB02000
diff --git a/arch/arm/dts/stm32mp157a-sodimm2-mx-u-boot.dtsi b/arch/arm/dts/stm32mp157a-sodimm2-mx-u-boot.dtsi
new file mode 100644
index 0000000000..cc3038b5a4
--- /dev/null
+++ b/arch/arm/dts/stm32mp157a-sodimm2-mx-u-boot.dtsi
@@ -0,0 +1,301 @@
+/* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause*/
+/*
+ * Copyright (C) 2022, STMicroelectronics - All Rights Reserved
+ * Author: STM32CubeMX code generation for STMicroelectronics.
+ */
+
+/* For more information on Device Tree configuration, please refer to
+ * https://wiki.st.com/stm32mpu/wiki/Category:Device_tree_configuration
+ */
+
+#include <dt-bindings/clock/stm32mp1-clksrc.h>
+#include "stm32mp15-mx.dtsi"
+
+#include "stm32mp15-u-boot.dtsi"
+#include "stm32mp15-ddr.dtsi"
+
+/* USER CODE BEGIN includes */
+/* USER CODE END includes */
+
+/ {
+
+ /* USER CODE BEGIN root */
+
+ aliases{
+ i2c3 = &i2c4;
+ mmc0 = &sdmmc1;
+ mmc1 = &sdmmc2;
+ gpio26 = &stmfx_pinctrl;
+ i2c1 = &i2c2;
+ i2c4 = &i2c5;
+ pinctrl2 = &stmfx_pinctrl;
+ spi0 = &qspi;
+ usb0 = &usbotg_hs;
+ };
+
+ config{
+ u-boot,boot-led = "heartbeat";
+ u-boot,error-led = "error";
+ u-boot,mmc-env-partition = "fip";
+ st,fastboot-gpios = <&gpioa 13 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
+ st,stm32prog-gpios = <&gpioa 14 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
+ };
+
+ led{
+
+ led-red{
+ label = "error";
+ gpios = <&gpioa 13 GPIO_ACTIVE_LOW>;
+ default-state = "off";
+ status = "okay";
+ };
+ };
+
+#ifdef CONFIG_STM32MP15x_STM32IMAGE
+
+ config{
+ u-boot,mmc-env-partition = "ssbl";
+ };
+
+ firmware{
+
+ optee{
+ compatible = "linaro,optee-tz";
+ method = "smc";
+ };
+ };
+
+ reserved-memory{
+
+ optee@fe000000{
+ reg = <0xfe000000 0x02000000>;
+ no-map;
+ };
+ };
+#endif
+ /* USER CODE END root */
+
+ clocks {
+ /* USER CODE BEGIN clocks */
+ /* USER CODE END clocks */
+
+#ifndef CONFIG_TFABOOT
+ clk_lsi: clk-lsi {
+
+ /* USER CODE BEGIN clk_lsi */
+ /* USER CODE END clk_lsi */
+ };
+ clk_hsi: clk-hsi {
+
+ /* USER CODE BEGIN clk_hsi */
+ /* USER CODE END clk_hsi */
+ };
+ clk_csi: clk-csi {
+ status = "disabled";
+
+ /* USER CODE BEGIN clk_csi */
+ /* USER CODE END clk_csi */
+ };
+ clk_lse: clk-lse {
+ st,drive = < LSEDRV_MEDIUM_HIGH >;
+
+ /* USER CODE BEGIN clk_lse */
+ /* USER CODE END clk_lse */
+ };
+ clk_hse: clk-hse {
+ st,digbypass;
+
+ /* USER CODE BEGIN clk_hse */
+ /* USER CODE END clk_hse */
+ };
+#endif /*CONFIG_TFABOOT*/
+ };
+
+}; /*root*/
+
+#ifndef CONFIG_TFABOOT
+
+&rcc{
+ u-boot,dm-pre-reloc;
+ st,clksrc = <
+ CLK_MPU_PLL1P
+ CLK_AXI_PLL2P
+ CLK_MCU_PLL3P
+ CLK_PLL12_HSE
+ CLK_PLL3_HSE
+ CLK_PLL4_HSE
+ CLK_RTC_LSE
+ CLK_MCO1_DISABLED
+ CLK_MCO2_DISABLED
+ >;
+ st,clkdiv = <
+ 1 /*MPU*/
+ 0 /*AXI*/
+ 0 /*MCU*/
+ 1 /*APB1*/
+ 1 /*APB2*/
+ 1 /*APB3*/
+ 1 /*APB4*/
+ 2 /*APB5*/
+ 23 /*RTC*/
+ 0 /*MCO1*/
+ 0 /*MCO2*/
+ >;
+ st,pkcs = <
+ CLK_CKPER_DISABLED
+ CLK_QSPI_ACLK
+ CLK_ETH_PLL4P
+ CLK_SDMMC12_PLL4P
+ CLK_STGEN_HSE
+ CLK_USBPHY_HSE
+ CLK_SPI2S1_DISABLED
+ CLK_SPI2S23_DISABLED
+ CLK_SPI45_DISABLED
+ CLK_SPI6_DISABLED
+ CLK_I2C46_HSI
+ CLK_SDMMC3_DISABLED
+ CLK_USBO_USBPHY
+ CLK_ADC_PLL4R
+ CLK_CEC_DISABLED
+ CLK_I2C12_HSI
+ CLK_I2C35_PCLK1
+ CLK_UART1_DISABLED
+ CLK_UART24_HSI
+ CLK_UART35_DISABLED
+ CLK_UART6_DISABLED
+ CLK_UART78_DISABLED
+ CLK_SPDIF_DISABLED
+ CLK_FDCAN_PLL3Q
+ CLK_SAI1_DISABLED
+ CLK_SAI2_DISABLED
+ CLK_SAI3_DISABLED
+ CLK_SAI4_DISABLED
+ CLK_RNG1_LSI
+ CLK_LPTIM1_DISABLED
+ CLK_LPTIM23_DISABLED
+ CLK_LPTIM45_DISABLED
+ >;
+ pll2:st,pll@1 {
+ compatible = "st,stm32mp1-pll";
+ reg = <1>;
+ cfg = < 2 65 1 0 0 PQR(1,1,1) >;
+ frac = < 0x1400 >;
+ u-boot,dm-pre-reloc;
+ };
+ pll3:st,pll@2 {
+ compatible = "st,stm32mp1-pll";
+ reg = <2>;
+ cfg = < 1 49 2 5 36 PQR(1,1,0) >;
+ u-boot,dm-pre-reloc;
+ };
+ pll4:st,pll@3 {
+ compatible = "st,stm32mp1-pll";
+ reg = <3>;
+ cfg = < 3 98 5 17 7 PQR(1,1,0) >;
+ u-boot,dm-pre-reloc;
+ };
+
+ /* USER CODE BEGIN rcc */
+ /* USER CODE END rcc */
+};
+
+&i2c4{
+ u-boot,dm-pre-reloc;
+
+ /* USER CODE BEGIN i2c4 */
+ /* USER CODE END i2c4 */
+};
+
+&qspi{
+ u-boot,dm-pre-reloc;
+
+ /* USER CODE BEGIN qspi */
+ /* USER CODE END qspi */
+};
+
+&sdmmc1{
+ u-boot,dm-pre-reloc;
+
+ /* USER CODE BEGIN sdmmc1 */
+ /* USER CODE END sdmmc1 */
+};
+
+&sdmmc2{
+ u-boot,dm-pre-reloc;
+
+ /* USER CODE BEGIN sdmmc2 */
+ /* USER CODE END sdmmc2 */
+};
+
+#endif /*CONFIG_TFABOOT*/
+
+&hash1{
+ u-boot,dm-pre-reloc;
+
+ /* USER CODE BEGIN hash1 */
+ /* USER CODE END hash1 */
+};
+
+&iwdg2{
+ u-boot,dm-pre-reloc;
+
+ /* USER CODE BEGIN iwdg2 */
+ /* USER CODE END iwdg2 */
+};
+
+&uart4{
+ u-boot,dm-pre-reloc;
+
+ /* USER CODE BEGIN uart4 */
+ /* USER CODE END uart4 */
+};
+
+&usbotg_hs{
+ u-boot,dm-pre-reloc;
+
+ /* USER CODE BEGIN usbotg_hs */
+ /* USER CODE END usbotg_hs */
+};
+
+&usbphyc{
+ u-boot,dm-pre-reloc;
+
+ /* USER CODE BEGIN usbphyc */
+ /* USER CODE END usbphyc */
+};
+
+&usbphyc_port0{
+ u-boot,dm-pre-reloc;
+
+ /* USER CODE BEGIN usbphyc_port0 */
+ /* USER CODE END usbphyc_port0 */
+};
+
+&usbphyc_port1{
+ u-boot,dm-pre-reloc;
+
+ /* USER CODE BEGIN usbphyc_port1 */
+ /* USER CODE END usbphyc_port1 */
+};
+
+/* USER CODE BEGIN addons */
+
+#ifndef CONFIG_TFABOOT
+
+&flash0{
+ u-boot,dm-spl;
+};
+
+&pmic{
+ u-boot,dm-pre-reloc;
+};
+
+#endif /*CONFIG_TFABOOT*/
+
+&uart4_pins_mx {
+ pins1 { /* UART4_RX */
+ /* pull-up on rx to avoid floating level */
+ bias-pull-up;
+ };
+};
+/* USER CODE END addons */
diff --git a/arch/arm/dts/stm32mp157a-sodimm2-mx.dts b/arch/arm/dts/stm32mp157a-sodimm2-mx.dts
new file mode 100644
index 0000000000..e8b04a2697
--- /dev/null
+++ b/arch/arm/dts/stm32mp157a-sodimm2-mx.dts
@@ -0,0 +1,1510 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
+/*
+ * Copyright (C) STMicroelectronics 2022 - All Rights Reserved
+ * Author: STM32CubeMX code generation for STMicroelectronics.
+ */
+
+/* For more information on Device Tree configuration, please refer to
+ * https://wiki.st.com/stm32mpu/wiki/Category:Device_tree_configuration
+ */
+
+/dts-v1/;
+#include <dt-bindings/pinctrl/stm32-pinfunc.h>
+
+#include "stm32mp157.dtsi"
+#include "stm32mp15xa.dtsi"
+#include "stm32mp15xxaa-pinctrl.dtsi"
+#include "stm32mp15-m4-srm.dtsi"
+
+/* USER CODE BEGIN includes */
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/mfd/st,stpmic1.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/soc/stm32-hdp.h>
+/* USER CODE END includes */
+
+/ {
+ model = "STMicroelectronics STM32MP157AAA3 SODIMM module";
+ compatible = "st,stm32mp157a-sodimm2-mx", "st,stm32mp157";
+
+ memory@c0000000 {
+ device_type = "memory";
+ reg = <0xc0000000 0x40000000>;
+
+ /* USER CODE BEGIN memory */
+ /* USER CODE END memory */
+ };
+
+ reserved-memory {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ /* USER CODE BEGIN reserved-memory */
+
+ mcuram2:mcuram2@10000000{
+ compatible = "shared-dma-pool";
+ reg = <0x10000000 0x40000>;
+ no-map;
+ };
+
+ vdev0vring0:vdev0vring0@10040000{
+ compatible = "shared-dma-pool";
+ reg = <0x10040000 0x1000>;
+ no-map;
+ };
+
+ vdev0vring1:vdev0vring1@10041000{
+ compatible = "shared-dma-pool";
+ reg = <0x10041000 0x1000>;
+ no-map;
+ };
+
+ vdev0buffer:vdev0buffer@10042000{
+ compatible = "shared-dma-pool";
+ reg = <0x10042000 0x4000>;
+ no-map;
+ };
+
+ mcu_rsc_table:mcu_rsc_table@10048000{
+ compatible = "shared-dma-pool";
+ reg = <0x10048000 0x8000>;
+ no-map;
+ };
+
+ mcuram:mcuram@30000000{
+ compatible = "shared-dma-pool";
+ reg = <0x30000000 0x40000>;
+ no-map;
+ };
+
+ retram:retram@38000000{
+ compatible = "shared-dma-pool";
+ reg = <0x38000000 0x10000>;
+ no-map;
+ };
+
+ gpu_reserved:gpu@f6000000{
+ reg = <0xf6000000 0x8000000>;
+ no-map;
+ };
+ /* USER CODE END reserved-memory */
+ };
+
+ /* USER CODE BEGIN root */
+
+ aliases{
+ serial0 = &uart4;
+ ethernet0 = ðernet0;
+ spi0 = &qspi;
+ display0 = &lcd0;
+ //serial1 = &usart3;
+ };
+
+ reg_5v_host: reg-5v-host {
+ compatible = "regulator-fixed";
+ regulator-name = "5v-host";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&usb_5v_power_pins_mx>;
+ pinctrl-1 = <&usb_5v_power_sleep_pins_mx>;
+ //gpio = <&gpioi 11 GPIO_ACTIVE_HIGH>; //power USB port
+ enable-active-high;
+ default-on;
+ status = "okay";
+ };
+
+ reg_5v_otg: reg-5v-otg {
+ compatible = "regulator-fixed";
+ regulator-name = "5v-otg";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&usb_otg_5v_power_pins_mx>;
+ pinctrl-1 = <&usb_otg_5v_power_sleep_pins_mx>;
+ //gpio = <&gpioc 13 GPIO_ACTIVE_HIGH>; //power for second port
+ enable-active-high;
+ default-on;
+ status = "okay";
+ };
+
+ reg_3v3_rgb: regulator-3v3-rgb {
+ compatible = "regulator-fixed";
+ regulator-name = "3v3-rgb";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&gpiog 2 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ status = "okay";
+ };
+
+ rgb_panel_backlight: rgb-panel-backlight {
+ compatible = "gpio-backlight";
+ gpios = <&gpioa 15 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ //default-on;
+ linux,default-trigger = "backlight";
+ status = "okay";
+ };
+
+ lcd0: display {
+ compatible = "ampire,am800480r3tmqwa1h", "panel-dpi";
+ //compatible = "bananapi,s070wv20-ct16", "panel-dpi";
+ //compatible = "panel-dpi";
+ //compatible = "startek,startek-kd050c", "panel-dpi";
+ label = "display";
+ power-supply = <®_3v3_rgb>;
+ backlight = <&rgb_panel_backlight>;
+ //bits-per-pixel = <32>;
+ //bus-width = <24>;
+ //connector-type = <17>;
+
+ status = "okay";
+
+ port {
+ dsi_in: endpoint {
+ remote-endpoint = <<dc_ep0_out>;
+ };
+ };
+
+ // panel-timing {
+ // clock-frequency = <33000000>;
+ // hactive = <800>;
+ // vactive = <480>;
+ // hfront-porch = <40>;
+ // hback-porch = <40>;
+ // hsync-len = <43>;
+ // vback-porch = <29>;
+ // vfront-porch = <13>;
+ // vsync-len = <3>;
+ // hsync-active = <0>;
+ // vsync-active = <0>;
+ // de-active = <1>;
+ // pixelclk-active = <1>;
+ // };
+
+ };
+
+ led {
+ compatible = "gpio-leds";
+ status = "okay";
+
+ green1 {
+ label = "heartbeat";
+ gpios = <&pcf8574a 3 GPIO_ACTIVE_LOW>;
+ linux,default-trigger = "heartbeat";
+ default-state = "on";
+ };
+
+ green2 {
+ label = "network";
+ gpios = <&pcf8574a 7 GPIO_ACTIVE_LOW>;
+ linux,default-trigger = "netdev";
+ default-state = "off";
+ };
+ };
+
+ vin:vin{
+ compatible = "regulator-fixed";
+ regulator-name = "vin";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ };
+
+ chosen{
+ stdout-path = "serial0:115200n8";
+ };
+
+ usb_phy_tuning:usb-phy-tuning{
+ st,hs-dc-level = <2>;
+ st,fs-rftime-tuning;
+ st,hs-rftime-reduction;
+ st,hs-current-trim = <15>;
+ st,hs-impedance-trim = <1>;
+ st,squelch-level = <3>;
+ st,hs-rx-offset = <2>;
+ st,no-lsfs-sc;
+ };
+ /* USER CODE END root */
+
+ clocks {
+ /* USER CODE BEGIN clocks */
+
+ clk_ext_camera:clk-ext-camera{
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <24000000>;
+ };
+ /* USER CODE END clocks */
+
+#ifndef CONFIG_TFABOOT
+ clk_lsi: clk-lsi {
+ clock-frequency = <32000>;
+ };
+ clk_hsi: clk-hsi {
+ clock-frequency = <64000000>;
+ };
+ clk_csi: clk-csi {
+ clock-frequency = <4000000>;
+ };
+ clk_lse: clk-lse {
+ clock-frequency = <32768>;
+ };
+ clk_hse: clk-hse {
+ clock-frequency = <24000000>;
+ };
+#endif /*CONFIG_TFABOOT*/
+ };
+
+}; /*root*/
+
+&pinctrl {
+ u-boot,dm-pre-reloc;
+
+ dcmi_pins_mx: dcmi_mx-0 {
+ pins {
+ pinmux = <STM32_PINMUX('A', 6, AF13)>, /* DCMI_PIXCLK */
+ <STM32_PINMUX('B', 7, AF13)>, /* DCMI_VSYNC */
+ <STM32_PINMUX('B', 8, AF13)>, /* DCMI_D6 */
+ <STM32_PINMUX('E', 6, AF13)>, /* DCMI_D7 */
+ <STM32_PINMUX('H', 8, AF13)>, /* DCMI_HSYNC */
+ <STM32_PINMUX('H', 9, AF13)>, /* DCMI_D0 */
+ <STM32_PINMUX('H', 10, AF13)>, /* DCMI_D1 */
+ <STM32_PINMUX('H', 11, AF13)>, /* DCMI_D2 */
+ <STM32_PINMUX('H', 12, AF13)>, /* DCMI_D3 */
+ <STM32_PINMUX('H', 14, AF13)>, /* DCMI_D4 */
+ <STM32_PINMUX('I', 4, AF13)>; /* DCMI_D5 */
+ bias-disable;
+ };
+ };
+
+ dcmi_sleep_pins_mx: dcmi_sleep_mx-0 {
+ pins {
+ pinmux = <STM32_PINMUX('A', 6, ANALOG)>, /* DCMI_PIXCLK */
+ <STM32_PINMUX('B', 7, ANALOG)>, /* DCMI_VSYNC */
+ <STM32_PINMUX('B', 8, ANALOG)>, /* DCMI_D6 */
+ <STM32_PINMUX('E', 6, ANALOG)>, /* DCMI_D7 */
+ <STM32_PINMUX('H', 8, ANALOG)>, /* DCMI_HSYNC */
+ <STM32_PINMUX('H', 9, ANALOG)>, /* DCMI_D0 */
+ <STM32_PINMUX('H', 10, ANALOG)>, /* DCMI_D1 */
+ <STM32_PINMUX('H', 11, ANALOG)>, /* DCMI_D2 */
+ <STM32_PINMUX('H', 12, ANALOG)>, /* DCMI_D3 */
+ <STM32_PINMUX('H', 14, ANALOG)>, /* DCMI_D4 */
+ <STM32_PINMUX('I', 4, ANALOG)>; /* DCMI_D5 */
+ };
+ };
+
+ eth1_pins_mx: eth1_mx-0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('A', 1, AF11)>, /* ETH1_RX_CLK */
+ <STM32_PINMUX('A', 7, AF11)>, /* ETH1_RX_CTL */
+ <STM32_PINMUX('B', 0, AF11)>, /* ETH1_RXD2 */
+ <STM32_PINMUX('B', 1, AF11)>, /* ETH1_RXD3 */
+ <STM32_PINMUX('C', 4, AF11)>, /* ETH1_RXD0 */
+ <STM32_PINMUX('C', 5, AF11)>; /* ETH1_RXD1 */
+ bias-disable;
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('A', 2, AF11)>; /* ETH1_MDIO */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <0>;
+ };
+ pins3 {
+ pinmux = <STM32_PINMUX('B', 11, AF11)>, /* ETH1_TX_CTL */
+ <STM32_PINMUX('C', 1, AF11)>, /* ETH1_MDC */
+ <STM32_PINMUX('C', 2, AF11)>, /* ETH1_TXD2 */
+ <STM32_PINMUX('E', 2, AF11)>, /* ETH1_TXD3 */
+ <STM32_PINMUX('G', 4, AF11)>, /* ETH1_GTX_CLK */
+ <STM32_PINMUX('G', 5, AF11)>, /* ETH1_CLK125 */
+ <STM32_PINMUX('G', 13, AF11)>, /* ETH1_TXD0 */
+ <STM32_PINMUX('G', 14, AF11)>; /* ETH1_TXD1 */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <2>;
+ };
+ };
+
+ eth1_sleep_pins_mx: eth1_sleep_mx-0 {
+ pins {
+ pinmux = <STM32_PINMUX('A', 1, ANALOG)>, /* ETH1_RX_CLK */
+ <STM32_PINMUX('A', 2, ANALOG)>, /* ETH1_MDIO */
+ <STM32_PINMUX('A', 7, ANALOG)>, /* ETH1_RX_CTL */
+ <STM32_PINMUX('B', 0, ANALOG)>, /* ETH1_RXD2 */
+ <STM32_PINMUX('B', 1, ANALOG)>, /* ETH1_RXD3 */
+ <STM32_PINMUX('B', 11, ANALOG)>, /* ETH1_TX_CTL */
+ <STM32_PINMUX('C', 1, ANALOG)>, /* ETH1_MDC */
+ <STM32_PINMUX('C', 2, ANALOG)>, /* ETH1_TXD2 */
+ <STM32_PINMUX('C', 4, ANALOG)>, /* ETH1_RXD0 */
+ <STM32_PINMUX('C', 5, ANALOG)>, /* ETH1_RXD1 */
+ <STM32_PINMUX('E', 2, ANALOG)>, /* ETH1_TXD3 */
+ <STM32_PINMUX('G', 4, ANALOG)>, /* ETH1_GTX_CLK */
+ <STM32_PINMUX('G', 5, ANALOG)>, /* ETH1_CLK125 */
+ <STM32_PINMUX('G', 13, ANALOG)>, /* ETH1_TXD0 */
+ <STM32_PINMUX('G', 14, ANALOG)>; /* ETH1_TXD1 */
+ };
+ };
+
+ fdcan1_pins_mx: fdcan1_mx-0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('H', 13, AF9)>; /* FDCAN1_TX */
+ bias-pull-up;
+ drive-push-pull;
+ slew-rate = <0>;
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('I', 9, AF9)>; /* FDCAN1_RX */
+ bias-pull-up;
+ };
+ };
+
+ fdcan1_sleep_pins_mx: fdcan1_sleep_mx-0 {
+ pins {
+ pinmux = <STM32_PINMUX('H', 13, ANALOG)>, /* FDCAN1_TX */
+ <STM32_PINMUX('I', 9, ANALOG)>; /* FDCAN1_RX */
+ };
+ };
+
+ fdcan2_pins_mx: fdcan2_mx-0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('B', 13, AF9)>; /* FDCAN2_TX */
+ bias-pull-up;
+ drive-push-pull;
+ slew-rate = <0>;
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('B', 5, AF9)>; /* FDCAN2_RX */
+ bias-pull-up;
+ };
+ };
+
+ fdcan2_sleep_pins_mx: fdcan2_sleep_mx-0 {
+ pins {
+ pinmux = <STM32_PINMUX('B', 5, ANALOG)>, /* FDCAN2_RX */
+ <STM32_PINMUX('B', 13, ANALOG)>; /* FDCAN2_TX */
+ };
+ };
+
+ i2c2_pins_mx: i2c2_mx-0 {
+ pins {
+ pinmux = <STM32_PINMUX('H', 4, AF4)>, /* I2C2_SCL */
+ <STM32_PINMUX('H', 5, AF4)>; /* I2C2_SDA */
+ bias-disable;
+ drive-open-drain;
+ slew-rate = <0>;
+ };
+ };
+
+ i2c2_sleep_pins_mx: i2c2_sleep_mx-0 {
+ pins {
+ pinmux = <STM32_PINMUX('H', 4, ANALOG)>, /* I2C2_SCL */
+ <STM32_PINMUX('H', 5, ANALOG)>; /* I2C2_SDA */
+ };
+ };
+
+ i2c5_pins_mx: i2c5_mx-0 {
+ pins {
+ pinmux = <STM32_PINMUX('A', 12, AF4)>, /* I2C5_SDA */
+ <STM32_PINMUX('D', 1, AF4)>; /* I2C5_SCL */
+ bias-disable;
+ drive-open-drain;
+ slew-rate = <0>;
+ };
+ };
+
+ i2c5_sleep_pins_mx: i2c5_sleep_mx-0 {
+ pins {
+ pinmux = <STM32_PINMUX('A', 12, ANALOG)>, /* I2C5_SDA */
+ <STM32_PINMUX('D', 1, ANALOG)>; /* I2C5_SCL */
+ };
+ };
+
+ ltdc_pins_mx: ltdc_mx-0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('C', 6, AF14)>, /* LTDC_HSYNC */
+ <STM32_PINMUX('I', 13, AF14)>, /* LTDC_VSYNC */
+ <STM32_PINMUX('I', 15, AF14)>, /* LTDC_R0 */
+ <STM32_PINMUX('J', 0, AF14)>, /* LTDC_R1 */
+ <STM32_PINMUX('J', 1, AF14)>, /* LTDC_R2 */
+ <STM32_PINMUX('J', 2, AF14)>, /* LTDC_R3 */
+ <STM32_PINMUX('J', 3, AF14)>, /* LTDC_R4 */
+ <STM32_PINMUX('J', 4, AF14)>, /* LTDC_R5 */
+ <STM32_PINMUX('J', 5, AF14)>, /* LTDC_R6 */
+ <STM32_PINMUX('J', 6, AF14)>, /* LTDC_R7 */
+ <STM32_PINMUX('J', 7, AF14)>, /* LTDC_G0 */
+ <STM32_PINMUX('J', 8, AF14)>, /* LTDC_G1 */
+ <STM32_PINMUX('J', 9, AF14)>, /* LTDC_G2 */
+ <STM32_PINMUX('J', 10, AF14)>, /* LTDC_G3 */
+ <STM32_PINMUX('J', 11, AF14)>, /* LTDC_G4 */
+ <STM32_PINMUX('J', 12, AF14)>, /* LTDC_B0 */
+ <STM32_PINMUX('J', 13, AF14)>, /* LTDC_B1 */
+ <STM32_PINMUX('J', 14, AF14)>, /* LTDC_B2 */
+ <STM32_PINMUX('J', 15, AF14)>, /* LTDC_B3 */
+ <STM32_PINMUX('K', 0, AF14)>, /* LTDC_G5 */
+ <STM32_PINMUX('K', 1, AF14)>, /* LTDC_G6 */
+ <STM32_PINMUX('K', 2, AF14)>, /* LTDC_G7 */
+ <STM32_PINMUX('K', 3, AF14)>, /* LTDC_B4 */
+ <STM32_PINMUX('K', 4, AF14)>, /* LTDC_B5 */
+ <STM32_PINMUX('K', 5, AF14)>, /* LTDC_B6 */
+ <STM32_PINMUX('K', 6, AF14)>, /* LTDC_B7 */
+ <STM32_PINMUX('K', 7, AF14)>; /* LTDC_DE */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <0>;
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('I', 14, AF14)>; /* LTDC_CLK */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <1>;
+ };
+ };
+
+ ltdc_sleep_pins_mx: ltdc_sleep_mx-0 {
+ pins {
+ pinmux = <STM32_PINMUX('C', 6, ANALOG)>, /* LTDC_HSYNC */
+ <STM32_PINMUX('I', 13, ANALOG)>, /* LTDC_VSYNC */
+ <STM32_PINMUX('I', 14, ANALOG)>, /* LTDC_CLK */
+ <STM32_PINMUX('I', 15, ANALOG)>, /* LTDC_R0 */
+ <STM32_PINMUX('J', 0, ANALOG)>, /* LTDC_R1 */
+ <STM32_PINMUX('J', 1, ANALOG)>, /* LTDC_R2 */
+ <STM32_PINMUX('J', 2, ANALOG)>, /* LTDC_R3 */
+ <STM32_PINMUX('J', 3, ANALOG)>, /* LTDC_R4 */
+ <STM32_PINMUX('J', 4, ANALOG)>, /* LTDC_R5 */
+ <STM32_PINMUX('J', 5, ANALOG)>, /* LTDC_R6 */
+ <STM32_PINMUX('J', 6, ANALOG)>, /* LTDC_R7 */
+ <STM32_PINMUX('J', 7, ANALOG)>, /* LTDC_G0 */
+ <STM32_PINMUX('J', 8, ANALOG)>, /* LTDC_G1 */
+ <STM32_PINMUX('J', 9, ANALOG)>, /* LTDC_G2 */
+ <STM32_PINMUX('J', 10, ANALOG)>, /* LTDC_G3 */
+ <STM32_PINMUX('J', 11, ANALOG)>, /* LTDC_G4 */
+ <STM32_PINMUX('J', 12, ANALOG)>, /* LTDC_B0 */
+ <STM32_PINMUX('J', 13, ANALOG)>, /* LTDC_B1 */
+ <STM32_PINMUX('J', 14, ANALOG)>, /* LTDC_B2 */
+ <STM32_PINMUX('J', 15, ANALOG)>, /* LTDC_B3 */
+ <STM32_PINMUX('K', 0, ANALOG)>, /* LTDC_G5 */
+ <STM32_PINMUX('K', 1, ANALOG)>, /* LTDC_G6 */
+ <STM32_PINMUX('K', 2, ANALOG)>, /* LTDC_G7 */
+ <STM32_PINMUX('K', 3, ANALOG)>, /* LTDC_B4 */
+ <STM32_PINMUX('K', 4, ANALOG)>, /* LTDC_B5 */
+ <STM32_PINMUX('K', 5, ANALOG)>, /* LTDC_B6 */
+ <STM32_PINMUX('K', 6, ANALOG)>, /* LTDC_B7 */
+ <STM32_PINMUX('K', 7, ANALOG)>; /* LTDC_DE */
+ };
+ };
+
+ quadspi_pins_mx: quadspi_mx-0 {
+ u-boot,dm-pre-reloc;
+ pins1 {
+ u-boot,dm-pre-reloc;
+ pinmux = <STM32_PINMUX('B', 6, AF10)>, /* QUADSPI_BK1_NCS */
+ <STM32_PINMUX('C', 0, AF10)>; /* QUADSPI_BK2_NCS */
+ bias-pull-up;
+ drive-push-pull;
+ slew-rate = <1>;
+ };
+ pins2 {
+ u-boot,dm-pre-reloc;
+ pinmux = <STM32_PINMUX('F', 10, AF9)>; /* QUADSPI_CLK */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <3>;
+ };
+ pins3 {
+ u-boot,dm-pre-reloc;
+ pinmux = <STM32_PINMUX('F', 6, AF9)>, /* QUADSPI_BK1_IO3 */
+ <STM32_PINMUX('F', 7, AF9)>, /* QUADSPI_BK1_IO2 */
+ <STM32_PINMUX('F', 8, AF10)>, /* QUADSPI_BK1_IO0 */
+ <STM32_PINMUX('F', 9, AF10)>, /* QUADSPI_BK1_IO1 */
+ <STM32_PINMUX('G', 7, AF11)>, /* QUADSPI_BK2_IO3 */
+ <STM32_PINMUX('G', 10, AF11)>, /* QUADSPI_BK2_IO2 */
+ <STM32_PINMUX('H', 2, AF9)>, /* QUADSPI_BK2_IO0 */
+ <STM32_PINMUX('H', 3, AF9)>; /* QUADSPI_BK2_IO1 */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <1>;
+ };
+ };
+
+ quadspi_sleep_pins_mx: quadspi_sleep_mx-0 {
+ u-boot,dm-pre-reloc;
+ pins {
+ u-boot,dm-pre-reloc;
+ pinmux = <STM32_PINMUX('B', 6, ANALOG)>, /* QUADSPI_BK1_NCS */
+ <STM32_PINMUX('C', 0, ANALOG)>, /* QUADSPI_BK2_NCS */
+ <STM32_PINMUX('F', 6, ANALOG)>, /* QUADSPI_BK1_IO3 */
+ <STM32_PINMUX('F', 7, ANALOG)>, /* QUADSPI_BK1_IO2 */
+ <STM32_PINMUX('F', 8, ANALOG)>, /* QUADSPI_BK1_IO0 */
+ <STM32_PINMUX('F', 9, ANALOG)>, /* QUADSPI_BK1_IO1 */
+ <STM32_PINMUX('F', 10, ANALOG)>, /* QUADSPI_CLK */
+ <STM32_PINMUX('G', 7, ANALOG)>, /* QUADSPI_BK2_IO3 */
+ <STM32_PINMUX('G', 10, ANALOG)>, /* QUADSPI_BK2_IO2 */
+ <STM32_PINMUX('H', 2, ANALOG)>, /* QUADSPI_BK2_IO0 */
+ <STM32_PINMUX('H', 3, ANALOG)>; /* QUADSPI_BK2_IO1 */
+ };
+ };
+