From 7c48cc9fea5458a30fa7b2e8e0a639f249c07a44 Mon Sep 17 00:00:00 2001 From: Dennis Muhlestein Date: Wed, 17 Sep 2014 09:08:29 -0600 Subject: [PATCH] Additional unisims to enable simulation in verilator of BRAMS. --- FD.v | 23 +++ FDC.v | 26 +++ FDE.v | 23 +++ FDP.v | 26 +++ FDR.v | 26 +++ FDRE.v | 26 +++ FDS.v | 26 +++ FDSE.v | 24 +++ GND.v | 11 ++ INV.v | 14 ++ LDC.v | 54 ++++++ LUT1.v | 17 ++ LUT2.v | 33 ++++ LUT3.v | 49 ++++++ LUT4.v | 57 +++++++ LUT5.v | 94 +++++++++++ LUT6.v | 70 ++++++++ LUT6_2.v | 121 ++++++++++++++ MULT_AND.v | 18 ++ MUXCY.v | 18 ++ MUXCY_L.v | 16 ++ MUXF5.v | 16 ++ MUXF6.v | 17 ++ MUXF7.v | 16 ++ RAM32X1D.v | 26 +++ RAMB16BWER.v | 459 +++++++++++++++++++++++++++++++++++++++++++++++++++ SRL16E.v | 28 ++++ VCC.v | 10 ++ XORCY.v | 14 ++ 29 files changed, 1358 insertions(+) create mode 100644 FD.v create mode 100644 FDC.v create mode 100644 FDE.v create mode 100644 FDP.v create mode 100644 FDR.v create mode 100644 FDRE.v create mode 100644 FDS.v create mode 100644 FDSE.v create mode 100644 GND.v create mode 100644 INV.v create mode 100644 LDC.v create mode 100644 LUT1.v create mode 100644 LUT2.v create mode 100644 LUT3.v create mode 100644 LUT4.v create mode 100644 LUT5.v create mode 100644 LUT6.v create mode 100644 LUT6_2.v create mode 100644 MULT_AND.v create mode 100644 MUXCY.v create mode 100644 MUXCY_L.v create mode 100644 MUXF5.v create mode 100644 MUXF6.v create mode 100644 MUXF7.v create mode 100644 RAM32X1D.v create mode 100644 RAMB16BWER.v create mode 100644 SRL16E.v create mode 100644 VCC.v create mode 100644 XORCY.v diff --git a/FD.v b/FD.v new file mode 100644 index 0000000..ef7eb0d --- /dev/null +++ b/FD.v @@ -0,0 +1,23 @@ + +`timescale 1 ps / 1 ps + + +module FD (Q, C, D); + + parameter INIT = 1'b0; + + output Q; + + input C, D; + + wire Q; + reg q_out; + + initial q_out = INIT; + + always @(posedge C) + q_out <= D; + + assign Q = q_out; + +endmodule diff --git a/FDC.v b/FDC.v new file mode 100644 index 0000000..dc93da7 --- /dev/null +++ b/FDC.v @@ -0,0 +1,26 @@ +`timescale 1 ps / 1 ps + + +module FDC (Q, C, CLR, D); + + parameter INIT = 1'b0; + + output Q; + + input C, CLR, D; + + wire Q; + reg q_out; + + initial q_out = INIT; + + + always @(posedge C or posedge CLR) + if (CLR) + q_out <= 0; + else + q_out <= D; + + assign Q = q_out; + +endmodule diff --git a/FDE.v b/FDE.v new file mode 100644 index 0000000..90fb8c2 --- /dev/null +++ b/FDE.v @@ -0,0 +1,23 @@ +`timescale 1 ps / 1 ps + +module FDE (Q, C, CE, D); + + parameter INIT = 1'b0; + + output Q; + + input C, CE, D; + + wire Q; + reg q_out; + + initial q_out = INIT; + + assign Q = q_out; + + + always @(posedge C) + if (CE) + q_out <= D; + +endmodule diff --git a/FDP.v b/FDP.v new file mode 100644 index 0000000..c2c36fe --- /dev/null +++ b/FDP.v @@ -0,0 +1,26 @@ + +`timescale 1 ps / 1 ps + + +module FDP (Q, C, D, PRE); + + parameter INIT = 1'b1; + + output Q; + + input C, D, PRE; + + wire Q; + reg q_out; + + initial q_out = INIT; + + assign Q = q_out; + + always @(posedge C or posedge PRE) + if (PRE) + q_out <= 1; + else + q_out <= D; + +endmodule diff --git a/FDR.v b/FDR.v new file mode 100644 index 0000000..6785c9b --- /dev/null +++ b/FDR.v @@ -0,0 +1,26 @@ + +`timescale 1 ps / 1 ps + + +module FDR (Q, C, D, R); + + parameter INIT = 1'b0; + + output Q; + + input C, D, R; + + wire Q; + reg q_out; + + initial q_out = INIT; + + assign Q = q_out; + + always @(posedge C ) + if (R) + q_out <= 0; + else + q_out <= D; + +endmodule diff --git a/FDRE.v b/FDRE.v new file mode 100644 index 0000000..0cea297 --- /dev/null +++ b/FDRE.v @@ -0,0 +1,26 @@ + +`timescale 1 ps / 1 ps + + +module FDRE (Q, C, CE, D, R); + + parameter INIT = 1'b0; + + output Q; + + input C, CE, D, R; + + wire Q; + reg q_out; + + initial q_out = INIT; + + assign Q = q_out; + + always @(posedge C ) + if (R) + q_out <= 0; + else if (CE) + q_out <= D; + +endmodule diff --git a/FDS.v b/FDS.v new file mode 100644 index 0000000..9bc02a9 --- /dev/null +++ b/FDS.v @@ -0,0 +1,26 @@ + +`timescale 1 ps / 1 ps + + +module FDS (Q, C, D, S); + + parameter INIT = 1'b1; + + output Q; + + input C, D, S; + + wire Q; + reg q_out; + + initial q_out = INIT; + + assign Q = q_out; + + always @(posedge C ) + if (S) + q_out <= 1; + else + q_out <= D; + +endmodule diff --git a/FDSE.v b/FDSE.v new file mode 100644 index 0000000..d4603fa --- /dev/null +++ b/FDSE.v @@ -0,0 +1,24 @@ +`timescale 1 ps / 1 ps + +module FDSE (Q, C, CE, D, S); + + parameter INIT = 1'b1; + + output Q; + + input C, CE, D, S; + + wire Q; + reg q_out; + + initial q_out = INIT; + + assign Q = q_out; + + always @(posedge C ) + if (S) + q_out <= 1; + else if (CE) + q_out <= D; + +endmodule diff --git a/GND.v b/GND.v new file mode 100644 index 0000000..adb4419 --- /dev/null +++ b/GND.v @@ -0,0 +1,11 @@ + +`timescale 1 ps / 1 ps + +module GND(G); + + output G; + + assign G = 1'b0; + +endmodule + diff --git a/INV.v b/INV.v new file mode 100644 index 0000000..0c67e4f --- /dev/null +++ b/INV.v @@ -0,0 +1,14 @@ + +`timescale 1 ps / 1 ps + + +module INV (O, I); + + output O; + + input I; + + not N1 (O, I); + +endmodule + diff --git a/LDC.v b/LDC.v new file mode 100644 index 0000000..8a12fbb --- /dev/null +++ b/LDC.v @@ -0,0 +1,54 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/LDC.v,v 1.12 2006/04/10 20:46:00 yanx Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Transparent Data Latch with Asynchronous Clear +// /___/ /\ Filename : LDC.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:52 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 02/04/05 - Rev 0.0.1 Remove input/output bufs; Seperate GSR from clock block. +// 08/09/05 - Add GSR to main block (CR 215196). +// 03/31/06 - Add specify block for 100ps delay. (CR 228298) +// End Revision + +`timescale 1 ps / 1 ps + + +module LDC (Q, CLR, D, G); + + parameter INIT = 1'b0; + + output Q; + wire Q; + + input CLR, D, G; + + reg q_out; + + initial q_out = INIT; + + assign Q = q_out; + + always @(CLR or D or G) + if (CLR) + q_out = 0; + else if (G) + q_out = D; + + specify + if (!CLR && G) + (D +=> Q) = (100, 100); + if (!CLR) + (posedge G => (Q +: D)) = (100, 100); + (posedge CLR => (Q +: 1'b0)) = (0, 0); + endspecify +endmodule diff --git a/LUT1.v b/LUT1.v new file mode 100644 index 0000000..3b22320 --- /dev/null +++ b/LUT1.v @@ -0,0 +1,17 @@ + +`timescale 1 ps / 1 ps + + +module LUT1 (O, I0); + + parameter INIT = 2'h0; + + input I0; + + output O; + + wire O; + + assign O = (INIT[0] == INIT[1]) ? INIT[0] : INIT[I0]; + +endmodule diff --git a/LUT2.v b/LUT2.v new file mode 100644 index 0000000..4e0d75c --- /dev/null +++ b/LUT2.v @@ -0,0 +1,33 @@ + +`timescale 1 ps / 1 ps + + +module LUT2 (O, I0, I1); + + parameter INIT = 4'h0; + + input I0, I1; + + output O; + + reg O; + wire [1:0] s; + + assign s = {I1, I0}; + + always @(s) + if ((s[1]^s[0] ==1) || (s[1]^s[0] ==0)) + O = INIT[s]; + else if ((INIT[0] == INIT[1]) && (INIT[2] == INIT[3]) && (INIT[0] == INIT[2])) + O = INIT[0]; + else if ((s[1] == 0) && (INIT[0] == INIT[1])) + O = INIT[0]; + else if ((s[1] == 1) && (INIT[2] == INIT[3])) + O = INIT[2]; + else if ((s[0] == 0) && (INIT[0] == INIT[2])) + O = INIT[0]; + else if ((s[0] == 1) && (INIT[1] == INIT[3])) + O = INIT[1]; + else + O = 1'bx; +endmodule diff --git a/LUT3.v b/LUT3.v new file mode 100644 index 0000000..8a4dbec --- /dev/null +++ b/LUT3.v @@ -0,0 +1,49 @@ + +`timescale 1 ps / 1 ps + + +module LUT3 (O, I0, I1, I2); + + parameter INIT = 8'h00; + + input I0, I1, I2; + + output O; + + reg O; + reg tmp; + + always @( I2 or I1 or I0 ) begin + tmp = I0 ^ I1 ^ I2; + if ( tmp == 0 || tmp == 1) + O = INIT[{I2, I1, I0}]; + else + O = lut3_mux4 ( {1'b0, 1'b0, lut3_mux4 (INIT[7:4], {I1, I0}), + lut3_mux4 (INIT[3:0], {I1, I0}) }, {1'b0, I2}); + end + + function lut3_mux4; + input [3:0] d; + input [1:0] s; + + begin + if ((s[1]^s[0] ==1) || (s[1]^s[0] ==0)) + lut3_mux4 = d[s]; + else if ((d[0] === d[1]) && (d[2] === d[3]) && (d[0] === d[2])) + lut3_mux4 = d[0]; + else if ((s[1] == 0) && (d[0] === d[1])) + lut3_mux4 = d[0]; + else if ((s[1] == 1) && (d[2] === d[3])) + lut3_mux4 = d[2]; + else if ((s[0] == 0) && (d[0] === d[2])) + lut3_mux4 = d[0]; + else if ((s[0] == 1) && (d[1] === d[3])) + lut3_mux4 = d[1]; + else + lut3_mux4 = 1'bx; + end + endfunction + +endmodule + + diff --git a/LUT4.v b/LUT4.v new file mode 100644 index 0000000..5f9d74e --- /dev/null +++ b/LUT4.v @@ -0,0 +1,57 @@ + +`timescale 1 ps / 1 ps + + +module LUT4 (O, I0, I1, I2, I3); + + parameter INIT = 16'h0000; + + input I0, I1, I2, I3; + + output O; + + reg O; + reg tmp; + + always @( I3 or I2 or I1 or I0 ) begin + + tmp = I0 ^ I1 ^ I2 ^ I3; + + if ( tmp == 0 || tmp == 1) + + O = INIT[{I3, I2, I1, I0}]; + + else + + O = lut4_mux4 ( {lut4_mux4 ( INIT[15:12], {I1, I0}), + lut4_mux4 ( INIT[11:8], {I1, I0}), + lut4_mux4 ( INIT[7:4], {I1, I0}), + lut4_mux4 ( INIT[3:0], {I1, I0}) }, {I3, I2}); + end + + function lut4_mux4; + input [3:0] d; + input [1:0] s; + + begin + + if ((s[1]^s[0] ==1) || (s[1]^s[0] ==0)) + + lut4_mux4 = d[s]; + + else if ((d[0] === d[1]) && (d[2] === d[3]) && (d[0] === d[2])) + lut4_mux4 = d[0]; + else if ((s[1] == 0) && (d[0] === d[1])) + lut4_mux4 = d[0]; + else if ((s[1] == 1) && (d[2] === d[3])) + lut4_mux4 = d[2]; + else if ((s[0] == 0) && (d[0] === d[2])) + lut4_mux4 = d[0]; + else if ((s[0] == 1) && (d[1] === d[3])) + lut4_mux4 = d[1]; + else + lut4_mux4 = 1'bx; + end + endfunction + +endmodule diff --git a/LUT5.v b/LUT5.v new file mode 100644 index 0000000..04fcc04 --- /dev/null +++ b/LUT5.v @@ -0,0 +1,94 @@ +`timescale 1 ps / 1 ps + + +module LUT5 (O, I0, I1, I2, I3, I4); + + parameter INIT = 32'h00000000; + + input I0, I1, I2, I3, I4; + + output O; + + reg O; + reg tmp; + + always @( I4 or I3 or I2 or I1 or I0 ) begin + + tmp = I0 ^ I1 ^ I2 ^ I3 ^ I4; + + if ( tmp == 0 || tmp == 1) + + O = INIT[{I4, I3, I2, I1, I0}]; + + else + + O = lut4_mux4 ( + { lut6_mux8 ( INIT[31:24], {I2, I1, I0}), + lut6_mux8 ( INIT[23:16], {I2, I1, I0}), + lut6_mux8 ( INIT[15:8], {I2, I1, I0}), + lut6_mux8 ( INIT[7:0], {I2, I1, I0}) }, { I4, I3}); + end + + function lut6_mux8; + input [7:0] d; + input [2:0] s; + + begin + + if ((s[2]^s[1]^s[0] ==1) || (s[2]^s[1]^s[0] ==0)) + + lut6_mux8 = d[s]; + + else + if ( ~(|d)) + lut6_mux8 = 1'b0; + else if ((&d)) + lut6_mux8 = 1'b1; + else if (((s[1]^s[0] ==1'b1) || (s[1]^s[0] ==1'b0)) && (d[{1'b0,s[1:0]}]===d[{1'b1,s[1:0]}])) + lut6_mux8 = d[{1'b0,s[1:0]}]; + else if (((s[2]^s[0] ==1) || (s[2]^s[0] ==0)) && (d[{s[2],1'b0,s[0]}]===d[{s[2],1'b1,s[0]}])) + lut6_mux8 = d[{s[2],1'b0,s[0]}]; + else if (((s[2]^s[1] ==1) || (s[2]^s[1] ==0)) && (d[{s[2],s[1],1'b0}]===d[{s[2],s[1],1'b1}])) + lut6_mux8 = d[{s[2],s[1],1'b0}]; + else if (((s[0] ==1) || (s[0] ==0)) && (d[{1'b0,1'b0,s[0]}]===d[{1'b0,1'b1,s[0]}]) && + (d[{1'b0,1'b0,s[0]}]===d[{1'b1,1'b0,s[0]}]) && (d[{1'b0,1'b0,s[0]}]===d[{1'b1,1'b1,s[0]}])) + lut6_mux8 = d[{1'b0,1'b0,s[0]}]; + else if (((s[1] ==1) || (s[1] ==0)) && (d[{1'b0,s[1],1'b0}]===d[{1'b0,s[1],1'b1}]) && + (d[{1'b0,s[1],1'b0}]===d[{1'b1,s[1],1'b0}]) && (d[{1'b0,s[1],1'b0}]===d[{1'b1,s[1],1'b1}])) + lut6_mux8 = d[{1'b0,s[1],1'b0}]; + else if (((s[2] ==1) || (s[2] ==0)) && (d[{s[2],1'b0,1'b0}]===d[{s[2],1'b0,1'b1}]) && + (d[{s[2],1'b0,1'b0}]===d[{s[2],1'b1,1'b0}]) && (d[{s[2],1'b0,1'b0}]===d[{s[2],1'b1,1'b1}])) + lut6_mux8 = d[{s[2],1'b0,1'b0}]; + else + lut6_mux8 = 1'bx; + end + endfunction + + + function lut4_mux4; + input [3:0] d; + input [1:0] s; + + begin + + if ((s[1]^s[0] ==1) || (s[1]^s[0] ==0)) + + lut4_mux4 = d[s]; + + else if ((d[0] === d[1]) && (d[2] === d[3]) && (d[0] === d[2]) ) + lut4_mux4 = d[0]; + else if ((s[1] == 0) && (d[0] === d[1])) + lut4_mux4 = d[0]; + else if ((s[1] == 1) && (d[2] === d[3])) + lut4_mux4 = d[2]; + else if ((s[0] == 0) && (d[0] === d[2])) + lut4_mux4 = d[0]; + else if ((s[0] == 1) && (d[1] === d[3])) + lut4_mux4 = d[1]; + else + lut4_mux4 = 1'bx; + + end + endfunction + +endmodule diff --git a/LUT6.v b/LUT6.v new file mode 100644 index 0000000..75a32b8 --- /dev/null +++ b/LUT6.v @@ -0,0 +1,70 @@ +`timescale 1 ps / 1 ps + + +module LUT6 (O, I0, I1, I2, I3, I4, I5); + + parameter INIT = 64'h0000000000000000; + + input I0, I1, I2, I3, I4, I5; + + output O; + + reg O; + reg tmp; + + always @( I5 or I4 or I3 or I2 or I1 or I0 ) begin + + tmp = I0 ^ I1 ^ I2 ^ I3 ^ I4 ^ I5; + + if ( tmp == 0 || tmp == 1) + + O = INIT[{I5, I4, I3, I2, I1, I0}]; + + else + + O = lut6_mux8 ( {lut6_mux8 ( INIT[63:56], {I2, I1, I0}), + lut6_mux8 ( INIT[55:48], {I2, I1, I0}), + lut6_mux8 ( INIT[47:40], {I2, I1, I0}), + lut6_mux8 ( INIT[39:32], {I2, I1, I0}), + lut6_mux8 ( INIT[31:24], {I2, I1, I0}), + lut6_mux8 ( INIT[23:16], {I2, I1, I0}), + lut6_mux8 ( INIT[15:8], {I2, I1, I0}), + lut6_mux8 ( INIT[7:0], {I2, I1, I0}) }, {I5, I4, I3}); + end + + function lut6_mux8; + input [7:0] d; + input [2:0] s; + + begin + + if ((s[2]^s[1]^s[0] ==1) || (s[2]^s[1]^s[0] ==0)) + + lut6_mux8 = d[s]; + + else + if ( ~(|d)) + lut6_mux8 = 1'b0; + else if ((&d)) + lut6_mux8 = 1'b1; + else if (((s[1]^s[0] ==1'b1) || (s[1]^s[0] ==1'b0)) && (d[{1'b0,s[1:0]}]==d[{1'b1,s[1:0]}])) + lut6_mux8 = d[{1'b0,s[1:0]}]; + else if (((s[2]^s[0] ==1) || (s[2]^s[0] ==0)) && (d[{s[2],1'b0,s[0]}]==d[{s[2],1'b1,s[0]}])) + lut6_mux8 = d[{s[2],1'b0,s[0]}]; + else if (((s[2]^s[1] ==1) || (s[2]^s[1] ==0)) && (d[{s[2],s[1],1'b0}]==d[{s[2],s[1],1'b1}])) + lut6_mux8 = d[{s[2],s[1],1'b0}]; + else if (((s[0] ==1) || (s[0] ==0)) && (d[{1'b0,1'b0,s[0]}]==d[{1'b0,1'b1,s[0]}]) && + (d[{1'b0,1'b0,s[0]}]==d[{1'b1,1'b0,s[0]}]) && (d[{1'b0,1'b0,s[0]}]==d[{1'b1,1'b1,s[0]}])) + lut6_mux8 = d[{1'b0,1'b0,s[0]}]; + else if (((s[1] ==1) || (s[1] ==0)) && (d[{1'b0,s[1],1'b0}]==d[{1'b0,s[1],1'b1}]) && + (d[{1'b0,s[1],1'b0}]==d[{1'b1,s[1],1'b0}]) && (d[{1'b0,s[1],1'b0}]==d[{1'b1,s[1],1'b1}])) + lut6_mux8 = d[{1'b0,s[1],1'b0}]; + else if (((s[2] ==1) || (s[2] ==0)) && (d[{s[2],1'b0,1'b0}]==d[{s[2],1'b0,1'b1}]) && + (d[{s[2],1'b0,1'b0}]==d[{s[2],1'b1,1'b0}]) && (d[{s[2],1'b0,1'b0}]==d[{s[2],1'b1,1'b1}])) + lut6_mux8 = d[{s[2],1'b0,1'b0}]; + else + lut6_mux8 = 1'bx; + end + endfunction + +endmodule diff --git a/LUT6_2.v b/LUT6_2.v new file mode 100644 index 0000000..3d11e06 --- /dev/null +++ b/LUT6_2.v @@ -0,0 +1,121 @@ +`timescale 1 ps / 1 ps + + +module LUT6_2 (O5, O6, I0, I1, I2, I3, I4, I5); + + parameter INIT = 64'h0000000000000000; + + input I0, I1, I2, I3, I4, I5; + + output O5, O6; + + reg [63:0] init_reg = INIT; + reg [31:0] init_l, init_h; + reg O_l, O_h, tmp; + reg O5, O6; + + initial begin + init_l = init_reg[31:0]; + init_h = init_reg[63:32]; + end + + always @(I5 or O_l or O_h) begin + O5 = O_l; + if (I5 == 1) + O6 = O_h; + else if (I5 == 0) + O6 = O_l; + else begin + if (O_h == 0 && O_l == 0) + O6 = 1'b0; + else if (O_h == 1 && O_l == 1) + O6 = 1'b1; + else + O6 = 1'bx; + end + end + + + always @( I4 or I3 or I2 or I1 or I0 ) begin + tmp = I0 ^ I1 ^ I2 ^ I3 ^ I4; + if ( tmp == 0 || tmp == 1) begin + O_l = init_l[{I4, I3, I2, I1, I0}]; + O_h = init_h[{I4, I3, I2, I1, I0}]; + end + else begin + O_l = lut4_mux4 ( + { lut6_mux8 ( init_l[31:24], {I2, I1, I0}), + lut6_mux8 ( init_l[23:16], {I2, I1, I0}), + lut6_mux8 ( init_l[15:8], {I2, I1, I0}), + lut6_mux8 ( init_l[7:0], {I2, I1, I0}) }, { I4, I3}); + O_h = lut4_mux4 ( + { lut6_mux8 ( init_h[31:24], {I2, I1, I0}), + lut6_mux8 ( init_h[23:16], {I2, I1, I0}), + lut6_mux8 ( init_h[15:8], {I2, I1, I0}), + lut6_mux8 ( init_h[7:0], {I2, I1, I0}) }, { I4, I3}); + end + end + + function lut6_mux8; + input [7:0] d; + input [2:0] s; + + begin + + if ((s[2]^s[1]^s[0] ==1) || (s[2]^s[1]^s[0] ==0)) + + lut6_mux8 = d[s]; + + else + if ( ~(|d)) + lut6_mux8 = 1'b0; + else if ((&d)) + lut6_mux8 = 1'b1; + else if (((s[1]^s[0] ==1'b1) || (s[1]^s[0] ==1'b0)) && (d[{1'b0,s[1:0]}]===d[{1'b1,s[1:0]}])) + lut6_mux8 = d[{1'b0,s[1:0]}]; + else if (((s[2]^s[0] ==1) || (s[2]^s[0] ==0)) && (d[{s[2],1'b0,s[0]}]===d[{s[2],1'b1,s[0]}])) + lut6_mux8 = d[{s[2],1'b0,s[0]}]; + else if (((s[2]^s[1] ==1) || (s[2]^s[1] ==0)) && (d[{s[2],s[1],1'b0}]===d[{s[2],s[1],1'b1}])) + lut6_mux8 = d[{s[2],s[1],1'b0}]; + else if (((s[0] ==1) || (s[0] ==0)) && (d[{1'b0,1'b0,s[0]}]===d[{1'b0,1'b1,s[0]}]) && + (d[{1'b0,1'b0,s[0]}]===d[{1'b1,1'b0,s[0]}]) && (d[{1'b0,1'b0,s[0]}]===d[{1'b1,1'b1,s[0]}])) + lut6_mux8 = d[{1'b0,1'b0,s[0]}]; + else if (((s[1] ==1) || (s[1] ==0)) && (d[{1'b0,s[1],1'b0}]===d[{1'b0,s[1],1'b1}]) && + (d[{1'b0,s[1],1'b0}]===d[{1'b1,s[1],1'b0}]) && (d[{1'b0,s[1],1'b0}]===d[{1'b1,s[1],1'b1}])) + lut6_mux8 = d[{1'b0,s[1],1'b0}]; + else if (((s[2] ==1) || (s[2] ==0)) && (d[{s[2],1'b0,1'b0}]===d[{s[2],1'b0,1'b1}]) && + (d[{s[2],1'b0,1'b0}]===d[{s[2],1'b1,1'b0}]) && (d[{s[2],1'b0,1'b0}]===d[{s[2],1'b1,1'b1}])) + lut6_mux8 = d[{s[2],1'b0,1'b0}]; + else + lut6_mux8 = 1'bx; + end + endfunction + + + function lut4_mux4; + input [3:0] d; + input [1:0] s; + + begin + + if ((s[1]^s[0] ==1) || (s[1]^s[0] ==0)) + + lut4_mux4 = d[s]; + + else if ((d[0] === d[1]) && (d[2] === d[3]) && (d[0] === d[2]) ) + lut4_mux4 = d[0]; + else if ((s[1] == 0) && (d[0] === d[1])) + lut4_mux4 = d[0]; + else if ((s[1] == 1) && (d[2] === d[3])) + lut4_mux4 = d[2]; + else if ((s[0] == 0) && (d[0] === d[2])) + lut4_mux4 = d[0]; + else if ((s[0] == 1) && (d[1] === d[3])) + lut4_mux4 = d[1]; + else + lut4_mux4 = 1'bx; + + end + endfunction + +endmodule diff --git a/MULT_AND.v b/MULT_AND.v new file mode 100644 index 0000000..e5b60ac --- /dev/null +++ b/MULT_AND.v @@ -0,0 +1,18 @@ +`timescale 1 ps / 1 ps + + +module MULT_AND (LO, I0, I1); + + output LO; + + input I0, I1; + + and A1 (LO, I0, I1); + + specify + (I0 *> LO) = (0, 0); + (I1 *> LO) = (0, 0); + endspecify + +endmodule + diff --git a/MUXCY.v b/MUXCY.v new file mode 100644 index 0000000..ad55738 --- /dev/null +++ b/MUXCY.v @@ -0,0 +1,18 @@ +`timescale 1 ps / 1 ps + + +module MUXCY (O, CI, DI, S); + + output O; + reg O; + + input CI, DI, S; + + always @(CI or DI or S) + if (S) + O = CI; + else + O = DI; + +endmodule + diff --git a/MUXCY_L.v b/MUXCY_L.v new file mode 100644 index 0000000..f98626e --- /dev/null +++ b/MUXCY_L.v @@ -0,0 +1,16 @@ +`timescale 1 ps / 1 ps + +module MUXCY_L (LO, CI, DI, S); + + output LO; + reg LO; + + input CI, DI, S; + + always @(CI or DI or S) + if (S) + LO = CI; + else + LO = DI; +endmodule + diff --git a/MUXF5.v b/MUXF5.v new file mode 100644 index 0000000..2819941 --- /dev/null +++ b/MUXF5.v @@ -0,0 +1,16 @@ +`timescale 1 ps / 1 ps + +module MUXF5 (O, I0, I1, S); + + output O; + reg O; + + input I0, I1, S; + + always @(I0 or I1 or S) + if (S) + O = I1; + else + O = I0; +endmodule + diff --git a/MUXF6.v b/MUXF6.v new file mode 100644 index 0000000..ab7e53d --- /dev/null +++ b/MUXF6.v @@ -0,0 +1,17 @@ +`timescale 1 ps / 1 ps + + +module MUXF6 (O, I0, I1, S); + + output O; + reg O; + + input I0, I1, S; + + always @(I0 or I1 or S) + if (S) + O = I1; + else + O = I0; +endmodule + diff --git a/MUXF7.v b/MUXF7.v new file mode 100644 index 0000000..f0700ae --- /dev/null +++ b/MUXF7.v @@ -0,0 +1,16 @@ +`timescale 1 ps / 1 ps + +module MUXF7 (O, I0, I1, S); + + output O; + reg O; + + input I0, I1, S; + + always @(I0 or I1 or S) + if (S) + O = I1; + else + O = I0; +endmodule + diff --git a/RAM32X1D.v b/RAM32X1D.v new file mode 100644 index 0000000..1683c84 --- /dev/null +++ b/RAM32X1D.v @@ -0,0 +1,26 @@ +`timescale 1 ps / 1 ps + +module RAM32X1D (DPO, SPO, A0, A1, A2, A3, A4, D, DPRA0, DPRA1, DPRA2, DPRA3, DPRA4, WCLK, WE); + + parameter INIT = 32'h00000000; + + output DPO, SPO; + + input A0, A1, A2, A3, A4, D, DPRA0, DPRA1, DPRA2, DPRA3, DPRA4, WCLK, WE; + + reg [31:0] mem; + wire [4:0] adr; + + assign adr = {A4, A3, A2, A1, A0}; + assign SPO = mem[adr]; + assign DPO = mem[{DPRA4, DPRA3, DPRA2, DPRA1, DPRA0}]; + + initial + mem = INIT; + + always @(posedge WCLK) + if (WE == 1'b1) + mem[adr] <= #100 D; + +endmodule + diff --git a/RAMB16BWER.v b/RAMB16BWER.v new file mode 100644 index 0000000..1c186bc --- /dev/null +++ b/RAMB16BWER.v @@ -0,0 +1,459 @@ + +`timescale 1 ps/1 ps + +module RAMB16BWER (DOA, DOB, DOPA, DOPB, + ADDRA, ADDRB, CLKA, CLKB, DIA, DIB, DIPA, DIPB, ENA, ENB, REGCEA, REGCEB, RSTA, RSTB, WEA, WEB); + + output [31:0] DOA; + output [31:0] DOB; + output [3:0] DOPA; + output [3:0] DOPB; + + input [13:0] ADDRA; + input [13:0] ADDRB; + input CLKA; + input CLKB; + input [31:0] DIA; + input [31:0] DIB; + input [3:0] DIPA; + input [3:0] DIPB; + input ENA; + input ENB; + input REGCEA; + input REGCEB; + input RSTA; + input RSTB; + input [3:0] WEA; + input [3:0] WEB; + + parameter integer DATA_WIDTH_A = 0; + parameter integer DATA_WIDTH_B = 0; + parameter integer DOA_REG = 0; + parameter integer DOB_REG = 0; + parameter EN_RSTRAM_A = "TRUE"; + parameter EN_RSTRAM_B = "TRUE"; + parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_A = 36'h0; + parameter INIT_B = 36'h0; + parameter INIT_FILE = "NONE"; + parameter RSTTYPE = "SYNC"; + parameter RST_PRIORITY_A = "CE"; + parameter RST_PRIORITY_B = "CE"; + parameter SETUP_ALL = 1000; + parameter SETUP_READ_FIRST = 3000; + parameter SIM_DEVICE = "SPARTAN3ADSP"; + parameter SIM_COLLISION_CHECK = "ALL"; + parameter SRVAL_A = 36'h0; + parameter SRVAL_B = 36'h0; + parameter WRITE_MODE_A = "WRITE_FIRST"; + parameter WRITE_MODE_B = "WRITE_FIRST"; + + +// verilator lint_off width +// verilator lint_off selrange +// verilator lint_off initialdly +// + + + localparam widest_width = (DATA_WIDTH_A >= DATA_WIDTH_B) ? DATA_WIDTH_A : DATA_WIDTH_B; + + localparam a_width = (DATA_WIDTH_A == 1) ? 1 : (DATA_WIDTH_A == 2) ? 2 : (DATA_WIDTH_A == 4) ? 4 : + (DATA_WIDTH_A == 9) ? 8 : (DATA_WIDTH_A == 18) ? 16 : (DATA_WIDTH_A == 36) ? 32 : 32; + + localparam b_width = (DATA_WIDTH_B == 1) ? 1 : (DATA_WIDTH_B == 2) ? 2 : (DATA_WIDTH_B == 4) ? 4 : + (DATA_WIDTH_B == 9) ? 8 : (DATA_WIDTH_B == 18) ? 16 : (DATA_WIDTH_B == 36) ? 32 : 32; + localparam width = (widest_width == 1) ? 1 : (widest_width == 2) ? 2 : (widest_width == 4) ? 4 : + (widest_width == 9) ? 8 : (widest_width == 18) ? 16 : (widest_width == 36) ? 32 : 32; + + localparam widthp = (widest_width == 9) ? 1 : (widest_width == 18) ? 2 : (widest_width == 36) ? 4 : 4; + localparam mem_depth = (widest_width == 1) ? 16384 : (widest_width == 2) ? 8192 : (widest_width == 4) ? 4096 : (widest_width == 9) ? 2048 : + (widest_width == 18) ? 1024 :(widest_width == 36) ? 512 : 16384; + + localparam memp_depth = (widest_width == 9) ? 2048 : (widest_width == 18) ? 1024 : (widest_width == 36) ? 512 : 2048; + + reg [widest_width-1:0] tmp_mem [mem_depth-1:0]; + + reg [width-1:0] mem [mem_depth-1:0]; + reg [widthp-1:0] memp [memp_depth-1:0]; + + integer count, countp, init_mult, initp_mult, large_width; + integer count1, countp1, i, i1, j, j1, i_p, i_mem; + + reg [1:0] wr_mode_a, wr_mode_b; + + reg [31:0] doado_out, doado_out_out; + reg [31:0] dobdo_out, dobdo_out_out; + reg finish_error = 0; + + + wire clkawrclk_in, clkbrdclk_in; + + wire rsta_in=RSTA; + wire rstbrst_in=RSTB; + + + assign clkawrclk_in = CLKA; + assign clkbrdclk_in = CLKB; + + + initial begin + + if (INIT_FILE == "NONE") begin + + init_mult = 256/width; + + for (count = 0; count < init_mult; count = count + 1) begin + for (count1 = 0; count1 < width; count1 = count1 + 1) begin + + mem[count][count1] = INIT_00[(count * width) + count1]; + mem[count + (init_mult * 1)][count1] = INIT_01[(count * width) + count1]; + mem[count + (init_mult * 2)][count1] = INIT_02[(count * width) + count1]; + mem[count + (init_mult * 3)][count1] = INIT_03[(count * width) + count1]; + mem[count + (init_mult * 4)][count1] = INIT_04[(count * width) + count1]; + mem[count + (init_mult * 5)][count1] = INIT_05[(count * width) + count1]; + mem[count + (init_mult * 6)][count1] = INIT_06[(count * width) + count1]; + mem[count + (init_mult * 7)][count1] = INIT_07[(count * width) + count1]; + mem[count + (init_mult * 8)][count1] = INIT_08[(count * width) + count1]; + mem[count + (init_mult * 9)][count1] = INIT_09[(count * width) + count1]; + mem[count + (init_mult * 10)][count1] = INIT_0A[(count * width) + count1]; + mem[count + (init_mult * 11)][count1] = INIT_0B[(count * width) + count1]; + mem[count + (init_mult * 12)][count1] = INIT_0C[(count * width) + count1]; + mem[count + (init_mult * 13)][count1] = INIT_0D[(count * width) + count1]; + mem[count + (init_mult * 14)][count1] = INIT_0E[(count * width) + count1]; + mem[count + (init_mult * 15)][count1] = INIT_0F[(count * width) + count1]; + mem[count + (init_mult * 16)][count1] = INIT_10[(count * width) + count1]; + mem[count + (init_mult * 17)][count1] = INIT_11[(count * width) + count1]; + mem[count + (init_mult * 18)][count1] = INIT_12[(count * width) + count1]; + mem[count + (init_mult * 19)][count1] = INIT_13[(count * width) + count1]; + mem[count + (init_mult * 20)][count1] = INIT_14[(count * width) + count1]; + mem[count + (init_mult * 21)][count1] = INIT_15[(count * width) + count1]; + mem[count + (init_mult * 22)][count1] = INIT_16[(count * width) + count1]; + mem[count + (init_mult * 23)][count1] = INIT_17[(count * width) + count1]; + mem[count + (init_mult * 24)][count1] = INIT_18[(count * width) + count1]; + mem[count + (init_mult * 25)][count1] = INIT_19[(count * width) + count1]; + mem[count + (init_mult * 26)][count1] = INIT_1A[(count * width) + count1]; + mem[count + (init_mult * 27)][count1] = INIT_1B[(count * width) + count1]; + mem[count + (init_mult * 28)][count1] = INIT_1C[(count * width) + count1]; + mem[count + (init_mult * 29)][count1] = INIT_1D[(count * width) + count1]; + mem[count + (init_mult * 30)][count1] = INIT_1E[(count * width) + count1]; + mem[count + (init_mult * 31)][count1] = INIT_1F[(count * width) + count1]; + mem[count + (init_mult * 32)][count1] = INIT_20[(count * width) + count1]; + mem[count + (init_mult * 33)][count1] = INIT_21[(count * width) + count1]; + mem[count + (init_mult * 34)][count1] = INIT_22[(count * width) + count1]; + mem[count + (init_mult * 35)][count1] = INIT_23[(count * width) + count1]; + mem[count + (init_mult * 36)][count1] = INIT_24[(count * width) + count1]; + mem[count + (init_mult * 37)][count1] = INIT_25[(count * width) + count1]; + mem[count + (init_mult * 38)][count1] = INIT_26[(count * width) + count1]; + mem[count + (init_mult * 39)][count1] = INIT_27[(count * width) + count1]; + mem[count + (init_mult * 40)][count1] = INIT_28[(count * width) + count1]; + mem[count + (init_mult * 41)][count1] = INIT_29[(count * width) + count1]; + mem[count + (init_mult * 42)][count1] = INIT_2A[(count * width) + count1]; + mem[count + (init_mult * 43)][count1] = INIT_2B[(count * width) + count1]; + mem[count + (init_mult * 44)][count1] = INIT_2C[(count * width) + count1]; + mem[count + (init_mult * 45)][count1] = INIT_2D[(count * width) + count1]; + mem[count + (init_mult * 46)][count1] = INIT_2E[(count * width) + count1]; + mem[count + (init_mult * 47)][count1] = INIT_2F[(count * width) + count1]; + mem[count + (init_mult * 48)][count1] = INIT_30[(count * width) + count1]; + mem[count + (init_mult * 49)][count1] = INIT_31[(count * width) + count1]; + mem[count + (init_mult * 50)][count1] = INIT_32[(count * width) + count1]; + mem[count + (init_mult * 51)][count1] = INIT_33[(count * width) + count1]; + mem[count + (init_mult * 52)][count1] = INIT_34[(count * width) + count1]; + mem[count + (init_mult * 53)][count1] = INIT_35[(count * width) + count1]; + mem[count + (init_mult * 54)][count1] = INIT_36[(count * width) + count1]; + mem[count + (init_mult * 55)][count1] = INIT_37[(count * width) + count1]; + mem[count + (init_mult * 56)][count1] = INIT_38[(count * width) + count1]; + mem[count + (init_mult * 57)][count1] = INIT_39[(count * width) + count1]; + mem[count + (init_mult * 58)][count1] = INIT_3A[(count * width) + count1]; + mem[count + (init_mult * 59)][count1] = INIT_3B[(count * width) + count1]; + mem[count + (init_mult * 60)][count1] = INIT_3C[(count * width) + count1]; + mem[count + (init_mult * 61)][count1] = INIT_3D[(count * width) + count1]; + mem[count + (init_mult * 62)][count1] = INIT_3E[(count * width) + count1]; + mem[count + (init_mult * 63)][count1] = INIT_3F[(count * width) + count1]; + end // for (count1 = 0; count1 < width; count1 = count1 + 1) + end // for (count = 0; count < init_mult; count = count + 1) + + + if (width >= 8) begin + + initp_mult = 256/widthp; + + for (countp = 0; countp < initp_mult; countp = countp + 1) begin + for (countp1 = 0; countp1 < widthp; countp1 = countp1 + 1) begin + + memp[countp][countp1] = INITP_00[(countp * widthp) + countp1]; + memp[countp + (initp_mult * 1)][countp1] = INITP_01[(countp * widthp) + countp1]; + memp[countp + (initp_mult * 2)][countp1] = INITP_02[(countp * widthp) + countp1]; + memp[countp + (initp_mult * 3)][countp1] = INITP_03[(countp * widthp) + countp1]; + memp[countp + (initp_mult * 4)][countp1] = INITP_04[(countp * widthp) + countp1]; + memp[countp + (initp_mult * 5)][countp1] = INITP_05[(countp * widthp) + countp1]; + memp[countp + (initp_mult * 6)][countp1] = INITP_06[(countp * widthp) + countp1]; + memp[countp + (initp_mult * 7)][countp1] = INITP_07[(countp * widthp) + countp1]; + + end // for (countp1 = 0; countp1 < widthp; countp1 = countp1 + 1) + end // for (countp = 0; countp < initp_mult; countp = countp + 1) + + end // if (width >= 8) + + end // if (INIT_FILE == "NONE") + + else begin + + for (j = 0; j < mem_depth; j = j + 1) begin + for (j1 = 0; j1 < widest_width; j1 = j1 + 1) begin + tmp_mem[j][j1] = 1'b0; + end + end + + $readmemh (INIT_FILE, tmp_mem); + case (widest_width) + + 1, 2, 4 : for (i_mem = 0; i_mem <= mem_depth; i_mem = i_mem + 1) + mem[i_mem] = tmp_mem [i_mem]; + + `ifndef verilator + 9 : for (i_mem = 0; i_mem <= mem_depth; i_mem = i_mem + 1) begin + mem[i_mem] = tmp_mem[i_mem][0 +: 8]; + memp[i_mem] = tmp_mem[i_mem][8 +: 1]; + end + + 18 : for (i_mem = 0; i_mem <= mem_depth; i_mem = i_mem + 1) begin + mem[i_mem] = tmp_mem[i_mem][0 +: 16]; + memp[i_mem] = tmp_mem[i_mem][16 +: 2]; + end + + 36 : for (i_mem = 0; i_mem <= mem_depth; i_mem = i_mem + 1) begin + mem[i_mem] = tmp_mem[i_mem][0 +: 32]; + memp[i_mem] = tmp_mem[i_mem][32 +: 4]; + end + `else + default: begin + $display ( "verilator impl needed %d", `__LINE__ ); + end + `endif + endcase // case(widest_width) + + //for (i=0;i<10;i=i+1) + // $display ( "mem [%d] %d", i, mem[i] ); + + end // else: !if(INIT_FILE == "NONE") + + + case (DATA_WIDTH_A) + + 0, 1, 2, 4, 9, 18, 36: ; + + default : begin + $display("Attribute Syntax Error : The attribute DATA_WIDTH_A on RAMB16BWER instance %m is set to %d. Legal values for this attribute are 0, 1, 2, 4, 9, 18 or 36.", DATA_WIDTH_A); + finish_error = 1; + end + + endcase // case(DATA_WIDTH_A) + + + case (DATA_WIDTH_B) + + 0, 1, 2, 4, 9, 18, 36: ; + + default : begin + $display("Attribute Syntax Error : The attribute DATA_WIDTH_B on RAMB16BWER instance %m is set to %d. Legal values for this attribute are 0, 1, 2, 4, 9, 18 or 36.", DATA_WIDTH_B); + finish_error = 1; + end + + endcase // case(DATA_WIDTH_B) + + + if (DATA_WIDTH_A == 0 && DATA_WIDTH_B == 0) begin + $display("Attribute Syntax Error : Attributes DATA_WIDTH_A and DATA_WIDTH_B on RAMB16BWER instance %m, both can not be 0."); + finish_error = 1; + end + + + case (WRITE_MODE_A) + "WRITE_FIRST" : wr_mode_a <= 2'b00; + "READ_FIRST" : wr_mode_a <= 2'b01; + "NO_CHANGE" : wr_mode_a <= 2'b10; + default : begin + $display("Attribute Syntax Error : The Attribute WRITE_MODE_A on RAMB16BWER instance %m is set to %s. Legal values for this attribute are WRITE_FIRST, READ_FIRST or NO_CHANGE.", WRITE_MODE_A); + finish_error = 1; + end + endcase + + + case (WRITE_MODE_B) + "WRITE_FIRST" : wr_mode_b <= 2'b00; + "READ_FIRST" : wr_mode_b <= 2'b01; + "NO_CHANGE" : wr_mode_b <= 2'b10; + default : begin + $display("Attribute Syntax Error : The Attribute WRITE_MODE_B on RAMB16BWER instance %m is set to %s. Legal values for this attribute are WRITE_FIRST, READ_FIRST or NO_CHANGE.", WRITE_MODE_B); + finish_error = 1; + end + endcase + + + if ((SIM_COLLISION_CHECK != "ALL") && (SIM_COLLISION_CHECK != "NONE") && (SIM_COLLISION_CHECK != "WARNING_ONLY") && (SIM_COLLISION_CHECK != "GENERATE_X_ONLY")) begin + + $display("Attribute Syntax Error : The attribute SIM_COLLISION_CHECK on RAMB16BWER instance %m is set to %s. Legal values for this attribute are ALL, NONE, WARNING_ONLY or GENERATE_X_ONLY.", SIM_COLLISION_CHECK); + finish_error = 1; + + end + + + if ((EN_RSTRAM_A != "TRUE") && (EN_RSTRAM_A != "FALSE")) begin + $display("Attribute Syntax Error : The attribute EN_RSTRAM_A on RAMB16BWER instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", EN_RSTRAM_A); + finish_error = 1; + end + + + if ((EN_RSTRAM_B != "TRUE") && (EN_RSTRAM_B != "FALSE")) begin + $display("Attribute Syntax Error : The attribute EN_RSTRAM_B on RAMB16BWER instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", EN_RSTRAM_B); + finish_error = 1; + end + + + if ((RST_PRIORITY_A != "SR") && (RST_PRIORITY_A != "CE")) begin + $display("Attribute Syntax Error : The attribute RST_PRIORITY_A on RAMB16BWER instance %m is set to %s. Legal values for this attribute are CE or SR.", RST_PRIORITY_A); + finish_error = 1; + end + + + if ((RST_PRIORITY_B != "SR") && (RST_PRIORITY_B != "CE")) begin + $display("Attribute Syntax Error : The attribute RST_PRIORITY_B on RAMB16BWER instance %m is set to %s. Legal values for this attribute are CE or SR.", RST_PRIORITY_B); + finish_error = 1; + end + + + if (!(SIM_DEVICE == "SPARTAN3ADSP" || SIM_DEVICE == "SPARTAN6")) begin + $display("Attribute Syntax Error : The Attribute SIM_DEVICE on RAMB16BWER instance %m is set to %s. Legal values for this attribute are SPARTAN3ADSP, or SPARTAN6.", SIM_DEVICE); + finish_error = 1; + end + + + if (finish_error == 1) + $finish; + + + end // initial begin + +// verilator lint_on selrange +// verilator lint_on initialdly + + assign DOA = DOA_REG>0 ? doado_out_out : doado_out; + wire ena = EN_RSTRAM_A == "TRUE" ? ENA : 1; + + wire [12:0] addra = width <= 8 ? ADDRA >> 1: + width <= 16 ? ADDRA >> 1 : + ADDRA >> 2; + wire [12:0] addrb = width <= 8 ? ADDRB >> 1: + width <= 16 ? ADDRB >> 1 : + ADDRB >> 2; + + wire write_a = |WEA && ena; + + always @(posedge clkawrclk_in or posedge rsta_in) begin + if (rsta_in) begin + doado_out <= 0; + doado_out_out <= 0; + end else begin + if (write_a) begin + mem[addra] <= DIA[width-1:0]; + if (! (&WEA)) $display ( "verilator impl needed %d",`__LINE__); + end + doado_out <= WRITE_MODE_A == "WRITE_FIRST" && write_a ? DIA : mem[addra]; + doado_out_out <= doado_out; + end + end + + assign DOB = DOB_REG>0 ? dobdo_out_out : dobdo_out; + wire enb = EN_RSTRAM_B == "TRUE" ? ENB : 1; + + wire write_b = |WEB && enb; + + always @(posedge clkbrdclk_in or posedge rstbrst_in) begin + if (rstbrst_in) begin + dobdo_out <= 0; + dobdo_out_out <= 0; + end else begin + if (write_b) begin + mem[addrb] <= DIB[width-1:0]; + if (! (&WEB)) $display ( "verilator impl needed %d",`__LINE__); + end + dobdo_out <= WRITE_MODE_B == "WRITE_FIRST" && write_b ? DIB : mem[addrb]; + dobdo_out_out <= dobdo_out; + end + end + + +endmodule // RAMB16BWER + +// verilator lint_on width diff --git a/SRL16E.v b/SRL16E.v new file mode 100644 index 0000000..692cda6 --- /dev/null +++ b/SRL16E.v @@ -0,0 +1,28 @@ +`timescale 1 ps / 1 ps + + +module SRL16E (Q, A0, A1, A2, A3, CE, CLK, D); + + parameter INIT = 16'h0000; + + output Q; + + input A0, A1, A2, A3, CE, CLK, D; + + reg [15:0] data; + + + assign Q = data[{A3, A2, A1, A0}]; + + initial data = INIT; + + always @(posedge CLK) + begin + if (CE == 1'b1) begin + {data[15:0]} <= /* NOTE #100 */ {data[14:0], D}; + end + end + + +endmodule + diff --git a/VCC.v b/VCC.v new file mode 100644 index 0000000..a4e59c5 --- /dev/null +++ b/VCC.v @@ -0,0 +1,10 @@ +`timescale 1 ps / 1 ps + +module VCC(P); + + output P; + + assign P = 1'b1; + +endmodule + diff --git a/XORCY.v b/XORCY.v new file mode 100644 index 0000000..acb55d1 --- /dev/null +++ b/XORCY.v @@ -0,0 +1,14 @@ +`timescale 1 ps / 1 ps + + +module XORCY (O, CI, LI); + + output O; + + input CI, LI; + + xor X1 (O, CI, LI); + + +endmodule +