diff --git a/DCM_SP.v b/DCM_SP.v
index b863c11..7e9b5da 100644
--- a/DCM_SP.v
+++ b/DCM_SP.v
@@ -29,94 +29,56 @@ output [7:0] STATUS;
    assign CLK2X180 = ~CLK2X;
    assign CLKFX180 = ~CLKFX;
 
-`ifndef verilator
-//`ifdef verilator
-   assign CLK2X = CLKIN;
-   assign CLK90 = CLKIN;
-   assign LOCKED = 1'b1;
-   assign CLKFX  = CLKIN;
-   assign CLKDV  = CLKIN;
-`else   
-   
-   reg x;     
-   always @(posedge CLKIN) begin
-      x = $c("m_DCM->posedge()");
-   end
-   assign CLK90 = $c("m_DCM->clk90(",CLKIN,")");
-   assign CLK2X = $c("m_DCM->clk2X(",CLKIN,")");
-   assign LOCKED = $c("m_DCM->locked(",CLKIN,")");
-   assign CLKFX = $c("m_DCM->clkFX(",CLKIN,",", CLKFX_MULTIPLY, ",", CLKFX_DIVIDE, ")");
-   assign CLKDV = $c("m_DCM->clkDV(",CLKIN,",", CLKDV_DIVIDE, ")");
-
-`systemc_header
-#ifndef __DCM_H__
-#define __DCM_H__
-extern unsigned int main_time;
-
-class t_DCM
-  {
+`ifdef verilator
 
- private:
-   int m_posedge2;
-   int m_posedge1;        
-   int m_locked;
-   int m_T;
- public:
-  // CONSTRUCTORS
-   t_DCM()
-   {
-    m_posedge2 = m_posedge1 = m_locked = 0;            
-    m_T = 10;
-    }
-  
-  ~t_DCM() {
-    
-  }
-  
-  inline bool posedge() {
-    if(m_locked < 10) {
-      m_locked++;
-
-      m_posedge1 = m_posedge2;
-      m_posedge2 = main_time;
-      m_T = m_posedge2 - m_posedge1;
-      if(m_T == 0) m_T = 10;
-//      printf("m_T=%d\n", m_T);
-    }
-    return true;
-  }
-     
-  inline bool clk90(bool x) {
-    return (((main_time-m_T/4) * 2 / m_T) % 2);
-  }   
-  inline bool clk2X(bool x) {
-    return ((main_time * 4 / m_T) % 2);
-  }
-  inline bool clkFX(bool x, int32_t m, int32_t d) {
-    return ((main_time * 2 * m / m_T / d) % 2);
-  }
-  inline bool clkDV(bool x, int32_t d) {
-    return ((main_time * 2 / m_T / d) % 2);
-  }
-  inline bool locked(bool x) {
-    return m_locked >= 10;
-  }
+   wire resetb = ~RST;
    
+   // 2x clock
+   wire clk2x, lock_2x;
+   PLL_sim
+   dcm_2x(
+      .input_clk( CLKIN ),
+      .output_clk ( clk2x ),
+      .pll_mult ( 2 ),
+      .pll_div  ( 1 ),
+      .locked ( lock_2x )
+   );
+   reg clk90;
+   reg [1:0] cnt;
+   always @(posedge clk2x or negedge clk2x or negedge resetb) begin
+      if (!resetb) begin
+         clk90 <= 0;
+         cnt <= 0;
+      end else begin
+         cnt <= cnt + 1;
+         if (!cnt[0]) clk90 <= ~clk90; 
+      end
+   end
+   assign CLK2X=clk2x;
+   assign CLK90=clk90;
 
-//  inline int32_t get_img_value(int32_t colAddr, int32_t rowAddr) {
-//    return MASK(m_img[rowAddr * COLS + colAddr], ADC_WIDTH);
-//  }
 
-};
-#endif
+   // clkfx 
+generate
+   wire lock_fx;
+   if (CLKFX_MULTIPLY==2 && CLKFX_DIVIDE==1) begin
+     assign CLKFX=clk2x;
+     assign lock_fx=lock_2x;
+   end else begin
+     PLL_sim
+     dcm_pll (
+        .input_clk( CLKIN ),
+        .output_clk ( CLKFX ),
+        .pll_mult ( CLKFX_MULTIPLY ),
+        .pll_div  ( CLKFX_DIVIDE ),
+        .locked ( lock_fx ),
+        .debug(0)
+     );
+   end
+endgenerate
+ 
+  assign LOCKED = lock_2x && lock_fx;
 
-`systemc_interface
-   t_DCM* m_DCM;        // Pointer to object we are embedding
-`systemc_ctor
-   m_DCM = new t_DCM(); // Construct contained object
-`systemc_dtor
-   delete m_DCM;    // Destruct contained object
-`verilog
 `endif
    
 endmodule