From cb707281e8ff566e922b8cb55f119819691b5172 Mon Sep 17 00:00:00 2001 From: Lane Brooks Date: Tue, 10 Jan 2017 16:19:04 -0700 Subject: [PATCH] made verilator happy --- BUFGMUX.v | 35 ++++++++++++++++++++--------------- 1 file changed, 20 insertions(+), 15 deletions(-) diff --git a/BUFGMUX.v b/BUFGMUX.v index b66033b..1f7afd9 100644 --- a/BUFGMUX.v +++ b/BUFGMUX.v @@ -28,48 +28,53 @@ module BUFGMUX (O, I0, I1, S); input I0, I1, S; reg q0, q1; - reg q0_enable, q1_enable; + /* verilator lint_off UNOPTFLAT */ + reg q0_enable, q1_enable; + /* verilator lint_on UNOPTFLAT */ wire q0_t, q1_t; reg clk_sel_in; - tri0 GSR = glbl.GSR; + wire GSR = 0;//tri0 GSR = glbl.GSR; - bufif1 B0 (O, I0, q0_t); - bufif1 B1 (O, I1, q1_t); - pulldown P1 (O); +// bufif1 B0 (O, I0, q0_t); +// bufif1 B1 (O, I1, q1_t); +// pulldown P1 (O); + assign O = (q0_t) ? I0 : (q1_t) ? I1 : 0; + /* verilator lint_off WIDTH */ initial clk_sel_in = (CLK_SEL_TYPE == "ASYNC") ? 1 : 0; + /* verilator lint_on WIDTH */ assign q0_t = (clk_sel_in) ? ~S : q0; assign q1_t = (clk_sel_in) ? S : q1; always @(GSR or I0 or S or q0_enable) if (GSR) - q0 <= 1; + q0 = 1; else if (!I0) - q0 <= !S && q0_enable; + q0 = !S && q0_enable; always @(GSR or I1 or S or q1_enable) if (GSR) - q1 <= 0; + q1 = 0; else if (!I1) - q1 <= S && q1_enable; + q1 = S && q1_enable; always @(GSR or q1 or I0) if (GSR) - q0_enable <= 1; + q0_enable = 1; else if (q1) - q0_enable <= 0; + q0_enable = 0; else if (I0) - q0_enable <= !q1; + q0_enable = !q1; always @(GSR or q0 or I1) if (GSR) - q1_enable <= 0; + q1_enable = 0; else if (q0) - q1_enable <= 0; + q1_enable = 0; else if (I1) - q1_enable <= !q0; + q1_enable = !q0; endmodule