diff --git a/README.md b/README.md
index 9a9c364..9286743 100644
--- a/README.md
+++ b/README.md
@@ -73,7 +73,9 @@ A curated list of amazingly awesome hardware description language projects.
    - [chisel](https://github.com/freechipsproject/chisel3) - Meta HDL, 2012+
    - [SpinalHDL](https://github.com/SpinalHDL/SpinalHDL) - Meta HDL 2012+
 
-
+* C#
+   - [Quokka](https://github.com/EvgenyMuryshkin/qusoc) - C# to low-level RTL translator (Verilog, VHDL) and simulation toolkit examples (gates, components, RISC-V, SoC) 
+    
 ## HLS
 
 * [hlslibs](https://github.com/hlslibs) - ac_math, ac_dsp, ac_types
@@ -91,6 +93,7 @@ A curated list of amazingly awesome hardware description language projects.
 * [DelayGraph](https://github.com/ni/DelayGraph) - 2016, C#, register assignment algorithms
 * [ahaHLS](https://github.com/dillonhuff/ahaHLS) - 2019, An open source high level synthesis (HLS) tool using LLVM
 * [combinatorylogic/soc](https://github.com/combinatorylogic/soc) - 2019, An experimental System-on-Chip with a custom compiler toolchain.
+* [Quokka](https://github.com/EvgenyMuryshkin/QuokkaEvaluation) - C# to HL RTL translator
 
 
 ## Other HDL languages
diff --git a/components.md b/components.md
index 17cd7b0..a2f4e89 100644
--- a/components.md
+++ b/components.md
@@ -14,3 +14,4 @@
 * [VexRiscv](https://github.com/SpinalHDL/VexRiscv) - RISC-V written in SpinalHDL
 * [TNoC](https://github.com/taichi-ishitani/tnoc) - Network on Chip router written in SystemVerilog
 * [Awesome Open Hardware Verification](https://github.com/ben-marshall/awesome-open-hardware-verification/) - A list of open source tools and frameworks for hardware verification.
+* [Quokka](https://github.com/EvgenyMuryshkin/qusoc) - RISC-V and SoC written in C#, translates to Verilog and VHDL