From 437a49d095812c2e36f34be3eb547f11ed0020ec Mon Sep 17 00:00:00 2001
From: cknizek <87683288+cknizek@users.noreply.github.com>
Date: Mon, 2 Sep 2024 14:44:08 -0700
Subject: [PATCH] updated verilator call with top-module specified as testbench
 (#459)

Added short change to Verilator template that specifies the top-level
module being used.
---
 bin/simulate_with_verilator.py       | 3 +++
 misc/verilator.mk.template           | 2 +-
 misc/verilator_testbench.sv.template | 2 +-
 3 files changed, 5 insertions(+), 2 deletions(-)

diff --git a/bin/simulate_with_verilator.py b/bin/simulate_with_verilator.py
index 4f70707a..f9fdda22 100644
--- a/bin/simulate_with_verilator.py
+++ b/bin/simulate_with_verilator.py
@@ -29,6 +29,7 @@ def simulate_with_verilator(
     clock_name: Optional[str] = None,
     include_dirs: List[Union[str, Path]] = [],
     extra_args: List[str] = [],
+    testbench_module_name: str = "testbench",
     max_num_tests=MAX_NUM_TESTS,
     ignore_missing_test_module_file: bool = False,
     expect_all_zero_outputs: bool = False,
@@ -96,6 +97,7 @@ def simulate_with_verilator(
             testbench_exe_filepath=testbench_exe_filepath,
             testbench_inputs_filepath=testbench_inputs_filepath,
             obj_dirpath=obj_dirpath,
+            top_module=testbench_module_name,
             extra_verilator_args=" ".join(
                 [str(path) for path in verilog_filepaths]
                 + [f"-I{dir}" for dir in include_dirs]
@@ -112,6 +114,7 @@ def simulate_with_verilator(
     testbench_source = testbench_template_source.format(
         max_input_bitwidth=max([bw for _, bw in module_inputs]),
         test_module_name=test_module_name,
+        testbench_module_name=testbench_module_name,
         ground_truth_module_name=ground_truth_module_name,
         test_module_port_list=",".join(
             [f".{name}({name})" for name, _ in module_inputs]
diff --git a/misc/verilator.mk.template b/misc/verilator.mk.template
index 2e601f47..7eaf3eca 100644
--- a/misc/verilator.mk.template
+++ b/misc/verilator.mk.template
@@ -9,4 +9,4 @@ simulate: {testbench_exe_filepath} {testbench_inputs_filepath}
 	{testbench_exe_filepath} < {testbench_inputs_filepath}
 
 {testbench_exe_filepath}: {testbench_filepath}
-	$(VERILATOR) -o {testbench_exe_filepath} --assert --main --timing --Mdir {obj_dirpath} --cc --exe --build $^ {extra_verilator_args}
\ No newline at end of file
+	$(VERILATOR) --top-module {top_module} -o {testbench_exe_filepath} --assert --main --timing --Mdir {obj_dirpath} --cc --exe --build $^ {extra_verilator_args}
\ No newline at end of file
diff --git a/misc/verilator_testbench.sv.template b/misc/verilator_testbench.sv.template
index aa805e15..f1345816 100644
--- a/misc/verilator_testbench.sv.template
+++ b/misc/verilator_testbench.sv.template
@@ -1,4 +1,4 @@
-module testbench;
+module {testbench_module_name};
 
 {input_output_declarations}