From e431979b2795afe0c9258918b12b121ca9f36f91 Mon Sep 17 00:00:00 2001 From: Alexander Williams Date: Sat, 28 Dec 2024 10:56:28 -0800 Subject: [PATCH] [ipgen] Generate cross-module references for top cores clkmgr, flash_ctrl, pwrmgr, and rstmgr all reference other ipgen cores. To enable simulating with the correct dependencies, have topgen add the correct prefixes for the implementing modules for those virtual references. This *still* isn't complete, since there are other virtual references that are *NOT* ipgen cores. Signed-off-by: Alexander Williams --- hw/ip_templates/clkmgr/clkmgr.core.tpl | 10 ++++ .../clkmgr/data/clkmgr.tpldesc.hjson | 48 +++++++++++-------- hw/ip_templates/clkmgr/dv/clkmgr_sim.core.tpl | 9 ++++ .../clkmgr/dv/clkmgr_sim_cfg.hjson.tpl | 2 +- .../flash_ctrl/data/flash_ctrl.tpldesc.hjson | 6 +++ .../dv/flash_ctrl_base_sim_cfg.hjson.tpl | 2 +- .../flash_ctrl/dv/flash_ctrl_sim.core.tpl | 14 ++++++ .../flash_ctrl/flash_ctrl.core.tpl | 10 ++++ .../pwrmgr/data/pwrmgr.tpldesc.hjson | 12 +++++ hw/ip_templates/pwrmgr/dv/pwrmgr_sim.core.tpl | 17 +++++++ .../pwrmgr/dv/pwrmgr_sim_cfg.hjson.tpl | 2 +- hw/ip_templates/pwrmgr/pwrmgr.core.tpl | 10 ++++ .../rstmgr/data/rstmgr.tpldesc.hjson | 12 +++++ hw/ip_templates/rstmgr/dv/rstmgr_sim.core.tpl | 18 +++++++ .../rstmgr/dv/rstmgr_sim_cfg.hjson.tpl | 2 +- hw/ip_templates/rstmgr/rstmgr.core.tpl | 19 ++++++++ .../ip_autogen/clkmgr/clkmgr.core | 6 +++ .../data/top_darjeeling_clkmgr.ipconfig.hjson | 1 + .../ip_autogen/clkmgr/dv/clkmgr_sim.core | 5 ++ .../ip_autogen/clkmgr/dv/clkmgr_sim_cfg.hjson | 2 +- .../data/top_darjeeling_pwrmgr.ipconfig.hjson | 2 + .../ip_autogen/pwrmgr/dv/env/pwrmgr_env.core | 1 + .../ip_autogen/pwrmgr/dv/pwrmgr_sim.core | 5 ++ .../ip_autogen/pwrmgr/dv/pwrmgr_sim_cfg.hjson | 2 +- .../ip_autogen/pwrmgr/pwrmgr.core | 6 +++ .../ip_autogen/pwrmgr/pwrmgr_components.core | 1 + .../data/top_darjeeling_rstmgr.ipconfig.hjson | 2 + .../ip_autogen/rstmgr/dv/rstmgr_sim.core | 6 +++ .../ip_autogen/rstmgr/dv/rstmgr_sim_cfg.hjson | 2 +- .../ip_autogen/rstmgr/rstmgr.core | 7 +++ .../dv/top_earlgrey_clkmgr_sim_top.core | 40 ---------------- .../dv/top_earlgrey_pwrmgr_sim_top.core | 41 ---------------- .../dv/top_earlgrey_rstmgr_sim_top.core | 41 ---------------- hw/top_earlgrey/ip_autogen/clkmgr/clkmgr.core | 6 +++ .../data/top_earlgrey_clkmgr.ipconfig.hjson | 1 + .../ip_autogen/clkmgr/dv/clkmgr_sim.core | 5 ++ .../ip_autogen/clkmgr/dv/clkmgr_sim_cfg.hjson | 2 +- .../top_earlgrey_flash_ctrl.ipconfig.hjson | 1 + .../dv/flash_ctrl_base_sim_cfg.hjson | 2 +- .../flash_ctrl/dv/flash_ctrl_sim.core | 8 ++++ .../ip_autogen/flash_ctrl/flash_ctrl.core | 6 +++ .../data/top_earlgrey_pwrmgr.ipconfig.hjson | 2 + .../ip_autogen/pwrmgr/dv/env/pwrmgr_env.core | 1 + .../ip_autogen/pwrmgr/dv/pwrmgr_sim.core | 5 ++ .../ip_autogen/pwrmgr/dv/pwrmgr_sim_cfg.hjson | 2 +- hw/top_earlgrey/ip_autogen/pwrmgr/pwrmgr.core | 6 +++ .../ip_autogen/pwrmgr/pwrmgr_components.core | 1 + .../data/top_earlgrey_rstmgr.ipconfig.hjson | 2 + .../ip_autogen/rstmgr/dv/rstmgr_sim.core | 6 +++ .../ip_autogen/rstmgr/dv/rstmgr_sim_cfg.hjson | 2 +- hw/top_earlgrey/ip_autogen/rstmgr/rstmgr.core | 7 +++ .../lint/top_earlgrey_lint_cfgs.hjson | 8 ++-- .../ip_autogen/clkmgr/clkmgr.core | 6 +++ ...top_englishbreakfast_clkmgr.ipconfig.hjson | 1 + .../ip_autogen/clkmgr/dv/clkmgr_sim.core | 5 ++ .../ip_autogen/clkmgr/dv/clkmgr_sim_cfg.hjson | 2 +- ...englishbreakfast_flash_ctrl.ipconfig.hjson | 1 + .../dv/flash_ctrl_base_sim_cfg.hjson | 2 +- .../flash_ctrl/dv/flash_ctrl_sim.core | 8 ++++ .../ip_autogen/flash_ctrl/flash_ctrl.core | 6 +++ ...top_englishbreakfast_pwrmgr.ipconfig.hjson | 2 + .../ip_autogen/pwrmgr/dv/env/pwrmgr_env.core | 1 + .../ip_autogen/pwrmgr/dv/pwrmgr_sim.core | 5 ++ .../ip_autogen/pwrmgr/dv/pwrmgr_sim_cfg.hjson | 2 +- .../ip_autogen/pwrmgr/pwrmgr.core | 6 +++ .../ip_autogen/pwrmgr/pwrmgr_components.core | 1 + ...top_englishbreakfast_rstmgr.ipconfig.hjson | 1 + .../ip_autogen/rstmgr/dv/rstmgr_sim.core | 5 ++ .../ip_autogen/rstmgr/dv/rstmgr_sim_cfg.hjson | 2 +- .../ip_autogen/rstmgr/rstmgr.core | 6 +++ util/ipgen/renderer.py | 9 +++- util/topgen.py | 9 +++- 72 files changed, 351 insertions(+), 165 deletions(-) delete mode 100644 hw/top_earlgrey/dv/top_earlgrey_clkmgr_sim_top.core delete mode 100644 hw/top_earlgrey/dv/top_earlgrey_pwrmgr_sim_top.core delete mode 100644 hw/top_earlgrey/dv/top_earlgrey_rstmgr_sim_top.core diff --git a/hw/ip_templates/clkmgr/clkmgr.core.tpl b/hw/ip_templates/clkmgr/clkmgr.core.tpl index 2ae17f2b1c725..48441de5ced56 100644 --- a/hw/ip_templates/clkmgr/clkmgr.core.tpl +++ b/hw/ip_templates/clkmgr/clkmgr.core.tpl @@ -33,6 +33,12 @@ filesets: - rtl/clkmgr_trans.sv file_type: systemVerilogSource +% if len(pwrmgr_instance_name) > 0: + files_top_lint: + depend: + - "fileset_top ? (${instance_vlnv("lowrisc:ip:pwrmgr_pkg:0.1", pwrmgr_instance_name)})" +% endif + files_verilator_waiver: depend: # common waivers @@ -63,6 +69,10 @@ targets: lint: <<: *default_target +% if len(pwrmgr_instance_name) > 0: + filesets_append: + - files_top_lint +% endif default_tool: verilator parameters: - SYNTHESIS=true diff --git a/hw/ip_templates/clkmgr/data/clkmgr.tpldesc.hjson b/hw/ip_templates/clkmgr/data/clkmgr.tpldesc.hjson index 7a8d2f77fe2a4..05b83960923c8 100644 --- a/hw/ip_templates/clkmgr/data/clkmgr.tpldesc.hjson +++ b/hw/ip_templates/clkmgr/data/clkmgr.tpldesc.hjson @@ -16,10 +16,10 @@ default: { io: { name: "io" - aon: "False" - freq: "96000000" - ref: "false" - } + aon: "False" + freq: "96000000" + ref: "false" + } } } { @@ -29,12 +29,12 @@ default: { main: { name: "io_div4" - aon: "False" - freq: "24000000" - ref: "false" - div: "4" - src: "io" - } + aon: "False" + freq: "24000000" + ref: "false" + div: "4" + src: "io" + } } } { @@ -43,12 +43,12 @@ type: "object" default: { hint_clks: { - name: "clk_main_aes" - signal: { - src_name: "main" - endpoint_ip: "aes" - } - } + name: "clk_main_aes" + signal: { + src_name: "main" + endpoint_ip: "aes" + } + } } } { @@ -73,11 +73,11 @@ type: "object" default: { intf: { - ep: [ - "clk1" - "clk2" - ] - } + ep: [ + "clk1" + "clk2" + ] + } } } { @@ -92,5 +92,11 @@ type: "bool" default: "1" } + { + name: "pwrmgr_instance_name" + desc: "Instance name for the pwrmgr dependencies, if available" + type: "string" + default: "" + } ] } diff --git a/hw/ip_templates/clkmgr/dv/clkmgr_sim.core.tpl b/hw/ip_templates/clkmgr/dv/clkmgr_sim.core.tpl index 9682184494db2..2f3c15edee79c 100644 --- a/hw/ip_templates/clkmgr/dv/clkmgr_sim.core.tpl +++ b/hw/ip_templates/clkmgr/dv/clkmgr_sim.core.tpl @@ -18,12 +18,21 @@ filesets: - cov/clkmgr_cov_bind.sv file_type: systemVerilogSource +% if len(pwrmgr_instance_name) > 0: + files_top_sim: + depend: + - "fileset_top ? (${instance_vlnv("lowrisc:ip:pwrmgr_pkg:0.1", pwrmgr_instance_name)})" +%endif + targets: sim: &sim_target toplevel: tb filesets: - files_rtl - files_dv +% if len(pwrmgr_instance_name) > 0: + - files_top_sim +% endif default_tool: vcs lint: diff --git a/hw/ip_templates/clkmgr/dv/clkmgr_sim_cfg.hjson.tpl b/hw/ip_templates/clkmgr/dv/clkmgr_sim_cfg.hjson.tpl index 347613daf0eb9..adb02de61b090 100644 --- a/hw/ip_templates/clkmgr/dv/clkmgr_sim_cfg.hjson.tpl +++ b/hw/ip_templates/clkmgr/dv/clkmgr_sim_cfg.hjson.tpl @@ -15,7 +15,7 @@ tool: vcs // Fusesoc core file used for building the file list. - fusesoc_core: ${instance_vlnv("lowrisc:dv:clkmgr_sim_top:0.1")} + fusesoc_core: ${instance_vlnv("lowrisc:dv:clkmgr_sim:0.1")} // Testplan hjson file. testplan: "{self_dir}/../data/clkmgr_testplan.hjson" diff --git a/hw/ip_templates/flash_ctrl/data/flash_ctrl.tpldesc.hjson b/hw/ip_templates/flash_ctrl/data/flash_ctrl.tpldesc.hjson index 273a06a4f965b..baba9a3a9b966 100644 --- a/hw/ip_templates/flash_ctrl/data/flash_ctrl.tpldesc.hjson +++ b/hw/ip_templates/flash_ctrl/data/flash_ctrl.tpldesc.hjson @@ -87,5 +87,11 @@ type: "int" default: "1048576" } + { + name: "pwrmgr_instance_name" + desc: "Instance name for the pwrmgr dependencies, if available" + type: "string" + default: "" + } ] } diff --git a/hw/ip_templates/flash_ctrl/dv/flash_ctrl_base_sim_cfg.hjson.tpl b/hw/ip_templates/flash_ctrl/dv/flash_ctrl_base_sim_cfg.hjson.tpl index b08607a93a85b..c60052eb98e1a 100644 --- a/hw/ip_templates/flash_ctrl/dv/flash_ctrl_base_sim_cfg.hjson.tpl +++ b/hw/ip_templates/flash_ctrl/dv/flash_ctrl_base_sim_cfg.hjson.tpl @@ -12,7 +12,7 @@ tb: tb // Fusesoc core file used for building the file list. - fusesoc_core: ${instance_vlnv("lowrisc:dv:flash_ctrl_sim_top:0.1")} + fusesoc_core: ${instance_vlnv("lowrisc:dv:flash_ctrl_sim:0.1")} // Testplan hjson file. testplan: "{self_dir}/../data/flash_ctrl_testplan.hjson" diff --git a/hw/ip_templates/flash_ctrl/dv/flash_ctrl_sim.core.tpl b/hw/ip_templates/flash_ctrl/dv/flash_ctrl_sim.core.tpl index 1f08d3ffa0b2c..e78fcb00a2dcf 100644 --- a/hw/ip_templates/flash_ctrl/dv/flash_ctrl_sim.core.tpl +++ b/hw/ip_templates/flash_ctrl/dv/flash_ctrl_sim.core.tpl @@ -22,6 +22,12 @@ filesets: - tb/tb.sv file_type: systemVerilogSource +% if len(pwrmgr_instance_name) > 0: + files_top_sim: + depend: + - "fileset_top ? (${instance_vlnv("lowrisc:ip:pwrmgr_pkg:0.1", pwrmgr_instance_name)})" +%endif + targets: default: &default_target toplevel: tb @@ -31,7 +37,15 @@ targets: sim: <<: *default_target +% if len(pwrmgr_instance_name) > 0: + filesets_append: + - files_top_sim +% endif default_tool: vcs lint: <<: *default_target +% if len(pwrmgr_instance_name) > 0: + filesets_append: + - files_top_sim +% endif diff --git a/hw/ip_templates/flash_ctrl/flash_ctrl.core.tpl b/hw/ip_templates/flash_ctrl/flash_ctrl.core.tpl index 72b5ab9c58143..66d5da113c9b9 100644 --- a/hw/ip_templates/flash_ctrl/flash_ctrl.core.tpl +++ b/hw/ip_templates/flash_ctrl/flash_ctrl.core.tpl @@ -46,6 +46,12 @@ filesets: - rtl/flash_phy_scramble.sv file_type: systemVerilogSource +% if len(pwrmgr_instance_name) > 0: + files_top_lint: + depend: + - "fileset_top ? (${instance_vlnv("lowrisc:ip:pwrmgr_pkg:0.1", pwrmgr_instance_name)})" +% endif + files_verilator_waiver: depend: # common waivers @@ -87,6 +93,10 @@ targets: lint: <<: *default_target +% if len(pwrmgr_instance_name) > 0: + filesets_append: + - files_top_lint +% endif default_tool: verilator parameters: - SYNTHESIS=true diff --git a/hw/ip_templates/pwrmgr/data/pwrmgr.tpldesc.hjson b/hw/ip_templates/pwrmgr/data/pwrmgr.tpldesc.hjson index 585632289279b..f931e04e60a41 100644 --- a/hw/ip_templates/pwrmgr/data/pwrmgr.tpldesc.hjson +++ b/hw/ip_templates/pwrmgr/data/pwrmgr.tpldesc.hjson @@ -64,5 +64,17 @@ type: "int" default: "1" } + { + name: "alert_handler_instance_name" + desc: "Instance name for the alert_handler dependencies, if available" + type: "string" + default: "" + } + { + name: "clkmgr_instance_name" + desc: "Instance name for the clkmgr dependencies, if available" + type: "string" + default: "" + } ] } diff --git a/hw/ip_templates/pwrmgr/dv/pwrmgr_sim.core.tpl b/hw/ip_templates/pwrmgr/dv/pwrmgr_sim.core.tpl index ed8ee095bb195..fade73ffd5b40 100644 --- a/hw/ip_templates/pwrmgr/dv/pwrmgr_sim.core.tpl +++ b/hw/ip_templates/pwrmgr/dv/pwrmgr_sim.core.tpl @@ -17,6 +17,20 @@ filesets: - tb.sv - cov/pwrmgr_cov_bind.sv file_type: systemVerilogSource +<% + have_files_top_sim = (len(clkmgr_instance_name) > 0 or + len(alert_handler_instance_name) > 0) +%>\ +% if have_files_top_sim: + files_top_sim: + depend: +% if len(alert_handler_instance_name) > 0: + - "fileset_top ? (${instance_vlnv("lowrisc:ip:alert_handler_pkg:0.1", alert_handler_instance_name)})" +% endif +% if len(clkmgr_instance_name) > 0: + - "fileset_top ? (${instance_vlnv("lowrisc:ip:clkmgr_pwrmgr_sva_if:0.1", clkmgr_instance_name)})" +% endif +% endif targets: sim: &sim_target @@ -24,6 +38,9 @@ targets: filesets: - files_rtl - files_dv +% if have_files_top_sim: + - files_top_sim +% endif default_tool: vcs lint: diff --git a/hw/ip_templates/pwrmgr/dv/pwrmgr_sim_cfg.hjson.tpl b/hw/ip_templates/pwrmgr/dv/pwrmgr_sim_cfg.hjson.tpl index 8f9d0a1c2dcbb..44ee3bb7cada5 100644 --- a/hw/ip_templates/pwrmgr/dv/pwrmgr_sim_cfg.hjson.tpl +++ b/hw/ip_templates/pwrmgr/dv/pwrmgr_sim_cfg.hjson.tpl @@ -15,7 +15,7 @@ tool: vcs // Fusesoc core file used for building the file list. - fusesoc_core: ${instance_vlnv("lowrisc:dv:pwrmgr_sim_top:0.1")} + fusesoc_core: ${instance_vlnv("lowrisc:dv:pwrmgr_sim:0.1")} // Testplan hjson file. testplan: "{self_dir}/../data/pwrmgr_testplan.hjson" diff --git a/hw/ip_templates/pwrmgr/pwrmgr.core.tpl b/hw/ip_templates/pwrmgr/pwrmgr.core.tpl index fb4925bf6a596..51ee2e7edc95a 100644 --- a/hw/ip_templates/pwrmgr/pwrmgr.core.tpl +++ b/hw/ip_templates/pwrmgr/pwrmgr.core.tpl @@ -15,6 +15,12 @@ filesets: - ${instance_vlnv("lowrisc:ip:pwrmgr_component:0.1")} file_type: systemVerilogSource +% if len(alert_handler_instance_name) > 0: + files_top_lint: + depend: + - "fileset_top ? (${instance_vlnv("lowrisc:ip:alert_handler_pkg:0.1", alert_handler_instance_name)})" +% endif + files_verilator_waiver: depend: # common waivers @@ -56,6 +62,10 @@ targets: lint: <<: *default_target +% if len(alert_handler_instance_name) > 0: + filesets_append: + - files_top_lint +% endif default_tool: verilator parameters: - SYNTHESIS=true diff --git a/hw/ip_templates/rstmgr/data/rstmgr.tpldesc.hjson b/hw/ip_templates/rstmgr/data/rstmgr.tpldesc.hjson index aa1db3ea83b4f..af581f8dc7f1d 100644 --- a/hw/ip_templates/rstmgr/data/rstmgr.tpldesc.hjson +++ b/hw/ip_templates/rstmgr/data/rstmgr.tpldesc.hjson @@ -117,5 +117,17 @@ type: "bool" default: "1" } + { + name: "alert_handler_instance_name" + desc: "Instance name for the alert_handler dependencies, if available" + type: "string" + default: "" + } + { + name: "pwrmgr_instance_name" + desc: "Instance name for the pwrmgr dependencies, if available" + type: "string" + default: "" + } ] } diff --git a/hw/ip_templates/rstmgr/dv/rstmgr_sim.core.tpl b/hw/ip_templates/rstmgr/dv/rstmgr_sim.core.tpl index cfbd2cad935a3..108e1f673c480 100644 --- a/hw/ip_templates/rstmgr/dv/rstmgr_sim.core.tpl +++ b/hw/ip_templates/rstmgr/dv/rstmgr_sim.core.tpl @@ -17,6 +17,21 @@ filesets: - tb.sv - cov/rstmgr_cov_bind.sv file_type: systemVerilogSource +<% + have_files_top_sim = (len(alert_handler_instance_name) > 0 or + len(pwrmgr_instance_name) > 0) +%>\ +% if have_files_top_sim: + files_top_sim: + depend: +% if len(alert_handler_instance_name) > 0: + - "fileset_top ? (${instance_vlnv("lowrisc:ip:alert_handler_pkg:0.1", alert_handler_instance_name)})" +% endif +% if len(pwrmgr_instance_name) > 0: + - "fileset_top ? (${instance_vlnv("lowrisc:ip:pwrmgr_pkg:0.1", pwrmgr_instance_name)})" + - "fileset_top ? (${instance_vlnv("lowrisc:ip:pwrmgr_rstmgr_sva_if:0.1", pwrmgr_instance_name)})" +% endif +% endif targets: sim: &sim_target @@ -24,6 +39,9 @@ targets: filesets: - files_rtl - files_dv +% if have_files_top_sim: + - files_top_sim +% endif default_tool: vcs lint: diff --git a/hw/ip_templates/rstmgr/dv/rstmgr_sim_cfg.hjson.tpl b/hw/ip_templates/rstmgr/dv/rstmgr_sim_cfg.hjson.tpl index 4eac24e967431..7f0a4da7f2c2c 100644 --- a/hw/ip_templates/rstmgr/dv/rstmgr_sim_cfg.hjson.tpl +++ b/hw/ip_templates/rstmgr/dv/rstmgr_sim_cfg.hjson.tpl @@ -15,7 +15,7 @@ tool: vcs // Fusesoc core file used for building the file list. - fusesoc_core: ${instance_vlnv("lowrisc:dv:rstmgr_sim_top:0.1")} + fusesoc_core: ${instance_vlnv("lowrisc:dv:rstmgr_sim:0.1")} // Testplan hjson file. testplan: "{self_dir}/../data/rstmgr_testplan.hjson" diff --git a/hw/ip_templates/rstmgr/rstmgr.core.tpl b/hw/ip_templates/rstmgr/rstmgr.core.tpl index 1a08c010593a2..738a7e4f3ff20 100644 --- a/hw/ip_templates/rstmgr/rstmgr.core.tpl +++ b/hw/ip_templates/rstmgr/rstmgr.core.tpl @@ -30,6 +30,21 @@ filesets: - rtl/rstmgr.sv file_type: systemVerilogSource +<% + have_files_top_lint = (len(alert_handler_instance_name) > 0 or + len(pwrmgr_instance_name) > 0) +%>\ +% if have_files_top_lint: + files_top_lint: + depend: +% if len(alert_handler_instance_name) > 0: + - "fileset_top ? (${instance_vlnv("lowrisc:ip:alert_handler_pkg:0.1", alert_handler_instance_name)})" +% endif +% if len(pwrmgr_instance_name) > 0: + - "fileset_top ? (${instance_vlnv("lowrisc:ip:pwrmgr_pkg:0.1", pwrmgr_instance_name)})" +% endif +% endif + files_verilator_waiver: depend: # common waivers @@ -61,6 +76,10 @@ targets: lint: <<: *default_target +% if have_files_top_lint: + filesets_append: + - files_top_lint +% endif default_tool: verilator parameters: - SYNTHESIS=true diff --git a/hw/top_darjeeling/ip_autogen/clkmgr/clkmgr.core b/hw/top_darjeeling/ip_autogen/clkmgr/clkmgr.core index dbca598dc0dcb..a7f8d1ff70b39 100644 --- a/hw/top_darjeeling/ip_autogen/clkmgr/clkmgr.core +++ b/hw/top_darjeeling/ip_autogen/clkmgr/clkmgr.core @@ -33,6 +33,10 @@ filesets: - rtl/clkmgr_trans.sv file_type: systemVerilogSource + files_top_lint: + depend: + - "fileset_top ? (lowrisc:opentitan:top_darjeeling_pwrmgr_pkg:0.1)" + files_verilator_waiver: depend: # common waivers @@ -63,6 +67,8 @@ targets: lint: <<: *default_target + filesets_append: + - files_top_lint default_tool: verilator parameters: - SYNTHESIS=true diff --git a/hw/top_darjeeling/ip_autogen/clkmgr/data/top_darjeeling_clkmgr.ipconfig.hjson b/hw/top_darjeeling/ip_autogen/clkmgr/data/top_darjeeling_clkmgr.ipconfig.hjson index f79a83f1ce2bf..fbd89cd3a9290 100644 --- a/hw/top_darjeeling/ip_autogen/clkmgr/data/top_darjeeling_clkmgr.ipconfig.hjson +++ b/hw/top_darjeeling/ip_autogen/clkmgr/data/top_darjeeling_clkmgr.ipconfig.hjson @@ -249,6 +249,7 @@ exported_clks: {} number_of_clock_groups: 7 with_alert_handler: true + pwrmgr_instance_name: top_darjeeling_ topname: darjeeling } } diff --git a/hw/top_darjeeling/ip_autogen/clkmgr/dv/clkmgr_sim.core b/hw/top_darjeeling/ip_autogen/clkmgr/dv/clkmgr_sim.core index 356660b524a3d..bf1983886e43a 100644 --- a/hw/top_darjeeling/ip_autogen/clkmgr/dv/clkmgr_sim.core +++ b/hw/top_darjeeling/ip_autogen/clkmgr/dv/clkmgr_sim.core @@ -18,12 +18,17 @@ filesets: - cov/clkmgr_cov_bind.sv file_type: systemVerilogSource + files_top_sim: + depend: + - "fileset_top ? (lowrisc:opentitan:top_darjeeling_pwrmgr_pkg:0.1)" + targets: sim: &sim_target toplevel: tb filesets: - files_rtl - files_dv + - files_top_sim default_tool: vcs lint: diff --git a/hw/top_darjeeling/ip_autogen/clkmgr/dv/clkmgr_sim_cfg.hjson b/hw/top_darjeeling/ip_autogen/clkmgr/dv/clkmgr_sim_cfg.hjson index 91c2064696ce1..8f4173eaa5d68 100644 --- a/hw/top_darjeeling/ip_autogen/clkmgr/dv/clkmgr_sim_cfg.hjson +++ b/hw/top_darjeeling/ip_autogen/clkmgr/dv/clkmgr_sim_cfg.hjson @@ -15,7 +15,7 @@ tool: vcs // Fusesoc core file used for building the file list. - fusesoc_core: lowrisc:opentitan:top_darjeeling_clkmgr_sim_top:0.1 + fusesoc_core: lowrisc:opentitan:top_darjeeling_clkmgr_sim:0.1 // Testplan hjson file. testplan: "{self_dir}/../data/clkmgr_testplan.hjson" diff --git a/hw/top_darjeeling/ip_autogen/pwrmgr/data/top_darjeeling_pwrmgr.ipconfig.hjson b/hw/top_darjeeling/ip_autogen/pwrmgr/data/top_darjeeling_pwrmgr.ipconfig.hjson index 6e9bf616f0d28..9a7c1dc8750ee 100644 --- a/hw/top_darjeeling/ip_autogen/pwrmgr/data/top_darjeeling_pwrmgr.ipconfig.hjson +++ b/hw/top_darjeeling/ip_autogen/pwrmgr/data/top_darjeeling_pwrmgr.ipconfig.hjson @@ -76,6 +76,8 @@ NumRstReqs: 2 wait_for_external_reset: true NumRomInputs: 3 + alert_handler_instance_name: top_darjeeling_ + clkmgr_instance_name: top_darjeeling_ topname: darjeeling } } diff --git a/hw/top_darjeeling/ip_autogen/pwrmgr/dv/env/pwrmgr_env.core b/hw/top_darjeeling/ip_autogen/pwrmgr/dv/env/pwrmgr_env.core index e81040138b373..3e30baa455440 100644 --- a/hw/top_darjeeling/ip_autogen/pwrmgr/dv/env/pwrmgr_env.core +++ b/hw/top_darjeeling/ip_autogen/pwrmgr/dv/env/pwrmgr_env.core @@ -9,6 +9,7 @@ filesets: depend: - lowrisc:dv:ralgen - lowrisc:dv:cip_lib + - lowrisc:ip:rv_core_ibex_pkg - lowrisc:opentitan:top_darjeeling_pwrmgr_pkg files: - pwrmgr_env_pkg.sv diff --git a/hw/top_darjeeling/ip_autogen/pwrmgr/dv/pwrmgr_sim.core b/hw/top_darjeeling/ip_autogen/pwrmgr/dv/pwrmgr_sim.core index cc4481f03a9f7..6d2a139965635 100644 --- a/hw/top_darjeeling/ip_autogen/pwrmgr/dv/pwrmgr_sim.core +++ b/hw/top_darjeeling/ip_autogen/pwrmgr/dv/pwrmgr_sim.core @@ -17,6 +17,10 @@ filesets: - tb.sv - cov/pwrmgr_cov_bind.sv file_type: systemVerilogSource + files_top_sim: + depend: + - "fileset_top ? (lowrisc:opentitan:top_darjeeling_alert_handler_pkg:0.1)" + - "fileset_top ? (lowrisc:opentitan:top_darjeeling_clkmgr_pwrmgr_sva_if:0.1)" targets: sim: &sim_target @@ -24,6 +28,7 @@ targets: filesets: - files_rtl - files_dv + - files_top_sim default_tool: vcs lint: diff --git a/hw/top_darjeeling/ip_autogen/pwrmgr/dv/pwrmgr_sim_cfg.hjson b/hw/top_darjeeling/ip_autogen/pwrmgr/dv/pwrmgr_sim_cfg.hjson index b9ab7a3829f54..60657a8f33975 100644 --- a/hw/top_darjeeling/ip_autogen/pwrmgr/dv/pwrmgr_sim_cfg.hjson +++ b/hw/top_darjeeling/ip_autogen/pwrmgr/dv/pwrmgr_sim_cfg.hjson @@ -15,7 +15,7 @@ tool: vcs // Fusesoc core file used for building the file list. - fusesoc_core: lowrisc:opentitan:top_darjeeling_pwrmgr_sim_top:0.1 + fusesoc_core: lowrisc:opentitan:top_darjeeling_pwrmgr_sim:0.1 // Testplan hjson file. testplan: "{self_dir}/../data/pwrmgr_testplan.hjson" diff --git a/hw/top_darjeeling/ip_autogen/pwrmgr/pwrmgr.core b/hw/top_darjeeling/ip_autogen/pwrmgr/pwrmgr.core index 1e4489aceb5b8..9792c62ab170f 100644 --- a/hw/top_darjeeling/ip_autogen/pwrmgr/pwrmgr.core +++ b/hw/top_darjeeling/ip_autogen/pwrmgr/pwrmgr.core @@ -15,6 +15,10 @@ filesets: - lowrisc:opentitan:top_darjeeling_pwrmgr_component:0.1 file_type: systemVerilogSource + files_top_lint: + depend: + - "fileset_top ? (lowrisc:opentitan:top_darjeeling_alert_handler_pkg:0.1)" + files_verilator_waiver: depend: # common waivers @@ -56,6 +60,8 @@ targets: lint: <<: *default_target + filesets_append: + - files_top_lint default_tool: verilator parameters: - SYNTHESIS=true diff --git a/hw/top_darjeeling/ip_autogen/pwrmgr/pwrmgr_components.core b/hw/top_darjeeling/ip_autogen/pwrmgr/pwrmgr_components.core index 6ffc3aefa364b..3b0b862657759 100644 --- a/hw/top_darjeeling/ip_autogen/pwrmgr/pwrmgr_components.core +++ b/hw/top_darjeeling/ip_autogen/pwrmgr/pwrmgr_components.core @@ -19,6 +19,7 @@ filesets: - lowrisc:prim:mubi - lowrisc:prim:clock_buf - lowrisc:prim:measure + - lowrisc:ip:rv_core_ibex_pkg - lowrisc:ip_interfaces:alert_handler_pkg - lowrisc:opentitan:top_darjeeling_pwrmgr_pkg files: diff --git a/hw/top_darjeeling/ip_autogen/rstmgr/data/top_darjeeling_rstmgr.ipconfig.hjson b/hw/top_darjeeling/ip_autogen/rstmgr/data/top_darjeeling_rstmgr.ipconfig.hjson index e897ff3b72ef0..5e6bfe0e4421c 100644 --- a/hw/top_darjeeling/ip_autogen/rstmgr/data/top_darjeeling_rstmgr.ipconfig.hjson +++ b/hw/top_darjeeling/ip_autogen/rstmgr/data/top_darjeeling_rstmgr.ipconfig.hjson @@ -544,6 +544,8 @@ rst_ni: lc_io_div4 export_rsts: {} with_alert_handler: true + pwrmgr_instance_name: top_darjeeling_ + alert_handler_instance_name: top_darjeeling_ topname: darjeeling } } diff --git a/hw/top_darjeeling/ip_autogen/rstmgr/dv/rstmgr_sim.core b/hw/top_darjeeling/ip_autogen/rstmgr/dv/rstmgr_sim.core index 0e7b8ec8e1e50..38bb1f1ee6099 100644 --- a/hw/top_darjeeling/ip_autogen/rstmgr/dv/rstmgr_sim.core +++ b/hw/top_darjeeling/ip_autogen/rstmgr/dv/rstmgr_sim.core @@ -17,6 +17,11 @@ filesets: - tb.sv - cov/rstmgr_cov_bind.sv file_type: systemVerilogSource + files_top_sim: + depend: + - "fileset_top ? (lowrisc:opentitan:top_darjeeling_alert_handler_pkg:0.1)" + - "fileset_top ? (lowrisc:opentitan:top_darjeeling_pwrmgr_pkg:0.1)" + - "fileset_top ? (lowrisc:opentitan:top_darjeeling_pwrmgr_rstmgr_sva_if:0.1)" targets: sim: &sim_target @@ -24,6 +29,7 @@ targets: filesets: - files_rtl - files_dv + - files_top_sim default_tool: vcs lint: diff --git a/hw/top_darjeeling/ip_autogen/rstmgr/dv/rstmgr_sim_cfg.hjson b/hw/top_darjeeling/ip_autogen/rstmgr/dv/rstmgr_sim_cfg.hjson index d0a1b99f8f7f7..d701389870a6d 100644 --- a/hw/top_darjeeling/ip_autogen/rstmgr/dv/rstmgr_sim_cfg.hjson +++ b/hw/top_darjeeling/ip_autogen/rstmgr/dv/rstmgr_sim_cfg.hjson @@ -15,7 +15,7 @@ tool: vcs // Fusesoc core file used for building the file list. - fusesoc_core: lowrisc:opentitan:top_darjeeling_rstmgr_sim_top:0.1 + fusesoc_core: lowrisc:opentitan:top_darjeeling_rstmgr_sim:0.1 // Testplan hjson file. testplan: "{self_dir}/../data/rstmgr_testplan.hjson" diff --git a/hw/top_darjeeling/ip_autogen/rstmgr/rstmgr.core b/hw/top_darjeeling/ip_autogen/rstmgr/rstmgr.core index 53eb42951e438..e14fe3d63f097 100644 --- a/hw/top_darjeeling/ip_autogen/rstmgr/rstmgr.core +++ b/hw/top_darjeeling/ip_autogen/rstmgr/rstmgr.core @@ -30,6 +30,11 @@ filesets: - rtl/rstmgr.sv file_type: systemVerilogSource + files_top_lint: + depend: + - "fileset_top ? (lowrisc:opentitan:top_darjeeling_alert_handler_pkg:0.1)" + - "fileset_top ? (lowrisc:opentitan:top_darjeeling_pwrmgr_pkg:0.1)" + files_verilator_waiver: depend: # common waivers @@ -61,6 +66,8 @@ targets: lint: <<: *default_target + filesets_append: + - files_top_lint default_tool: verilator parameters: - SYNTHESIS=true diff --git a/hw/top_earlgrey/dv/top_earlgrey_clkmgr_sim_top.core b/hw/top_earlgrey/dv/top_earlgrey_clkmgr_sim_top.core deleted file mode 100644 index 6abf2399d8119..0000000000000 --- a/hw/top_earlgrey/dv/top_earlgrey_clkmgr_sim_top.core +++ /dev/null @@ -1,40 +0,0 @@ -CAPI=2: -# Copyright lowRISC contributors (OpenTitan project). -# Licensed under the Apache License, Version 2.0, see LICENSE for details. -# SPDX-License-Identifier: Apache-2.0 -name: "lowrisc:opentitan:top_earlgrey_clkmgr_sim_top:0.1" -description: "Pseudo top-level for Earl Grey's clkmgr" -filesets: - files_rtl: - depend: - - lowrisc:opentitan:top_earlgrey_pwrmgr_pkg - - lowrisc:opentitan:top_earlgrey_clkmgr - files_dv: - depend: - - lowrisc:opentitan:top_earlgrey_clkmgr_sim - -parameters: - SYNTHESIS: - datatype: bool - paramtype: vlogdefine - -targets: - lint: - toplevel: clkmgr - filesets: - - files_rtl - default_tool: verilator - parameters: - - SYNTHESIS=true - tools: - verilator: - mode: lint-only - verilator_options: - - "-Wall" - - sim: - toplevel: tb - filesets: - - files_rtl - - files_dv - default_tool: vcs diff --git a/hw/top_earlgrey/dv/top_earlgrey_pwrmgr_sim_top.core b/hw/top_earlgrey/dv/top_earlgrey_pwrmgr_sim_top.core deleted file mode 100644 index 5e26f5cfec0a7..0000000000000 --- a/hw/top_earlgrey/dv/top_earlgrey_pwrmgr_sim_top.core +++ /dev/null @@ -1,41 +0,0 @@ -CAPI=2: -# Copyright lowRISC contributors (OpenTitan project). -# Licensed under the Apache License, Version 2.0, see LICENSE for details. -# SPDX-License-Identifier: Apache-2.0 -name: "lowrisc:opentitan:top_earlgrey_pwrmgr_sim_top:0.1" -description: "Pseudo top-level for Earl Grey's pwrmgr" -filesets: - files_rtl: - depend: - - lowrisc:opentitan:top_earlgrey_alert_handler_pkg - - lowrisc:opentitan:top_earlgrey_pwrmgr - files_dv: - depend: - - lowrisc:opentitan:top_earlgrey_pwrmgr_sim - - lowrisc:opentitan:top_earlgrey_clkmgr_pwrmgr_sva_if - -parameters: - SYNTHESIS: - datatype: bool - paramtype: vlogdefine - -targets: - lint: - toplevel: pwrmgr - filesets: - - files_rtl - default_tool: verilator - parameters: - - SYNTHESIS=true - tools: - verilator: - mode: lint-only - verilator_options: - - "-Wall" - - sim: - toplevel: tb - filesets: - - files_rtl - - files_dv - default_tool: vcs diff --git a/hw/top_earlgrey/dv/top_earlgrey_rstmgr_sim_top.core b/hw/top_earlgrey/dv/top_earlgrey_rstmgr_sim_top.core deleted file mode 100644 index d33e4ce564023..0000000000000 --- a/hw/top_earlgrey/dv/top_earlgrey_rstmgr_sim_top.core +++ /dev/null @@ -1,41 +0,0 @@ -CAPI=2: -# Copyright lowRISC contributors (OpenTitan project). -# Licensed under the Apache License, Version 2.0, see LICENSE for details. -# SPDX-License-Identifier: Apache-2.0 -name: "lowrisc:opentitan:top_earlgrey_rstmgr_sim_top:0.1" -description: "Pseudo top-level for Earl Grey's rstmgr" -filesets: - files_rtl: - depend: - - lowrisc:opentitan:top_earlgrey_pwrmgr_pkg - - lowrisc:opentitan:top_earlgrey_rstmgr - files_dv: - depend: - - lowrisc:opentitan:top_earlgrey_pwrmgr_rstmgr_sva_if - - lowrisc:opentitan:top_earlgrey_rstmgr_sim - -parameters: - SYNTHESIS: - datatype: bool - paramtype: vlogdefine - -targets: - lint: - toplevel: rstmgr - filesets: - - files_rtl - default_tool: verilator - parameters: - - SYNTHESIS=true - tools: - verilator: - mode: lint-only - verilator_options: - - "-Wall" - - sim: - toplevel: tb - filesets: - - files_rtl - - files_dv - default_tool: vcs diff --git a/hw/top_earlgrey/ip_autogen/clkmgr/clkmgr.core b/hw/top_earlgrey/ip_autogen/clkmgr/clkmgr.core index bbf3e7ff4bf82..86f43359442ae 100644 --- a/hw/top_earlgrey/ip_autogen/clkmgr/clkmgr.core +++ b/hw/top_earlgrey/ip_autogen/clkmgr/clkmgr.core @@ -33,6 +33,10 @@ filesets: - rtl/clkmgr_trans.sv file_type: systemVerilogSource + files_top_lint: + depend: + - "fileset_top ? (lowrisc:opentitan:top_earlgrey_pwrmgr_pkg:0.1)" + files_verilator_waiver: depend: # common waivers @@ -63,6 +67,8 @@ targets: lint: <<: *default_target + filesets_append: + - files_top_lint default_tool: verilator parameters: - SYNTHESIS=true diff --git a/hw/top_earlgrey/ip_autogen/clkmgr/data/top_earlgrey_clkmgr.ipconfig.hjson b/hw/top_earlgrey/ip_autogen/clkmgr/data/top_earlgrey_clkmgr.ipconfig.hjson index d2ef41314064d..6cb9e59ffaf7d 100644 --- a/hw/top_earlgrey/ip_autogen/clkmgr/data/top_earlgrey_clkmgr.ipconfig.hjson +++ b/hw/top_earlgrey/ip_autogen/clkmgr/data/top_earlgrey_clkmgr.ipconfig.hjson @@ -259,6 +259,7 @@ exported_clks: {} number_of_clock_groups: 7 with_alert_handler: true + pwrmgr_instance_name: top_earlgrey_ topname: earlgrey } } diff --git a/hw/top_earlgrey/ip_autogen/clkmgr/dv/clkmgr_sim.core b/hw/top_earlgrey/ip_autogen/clkmgr/dv/clkmgr_sim.core index fd0b6201a8e69..fde2c0651f1ae 100644 --- a/hw/top_earlgrey/ip_autogen/clkmgr/dv/clkmgr_sim.core +++ b/hw/top_earlgrey/ip_autogen/clkmgr/dv/clkmgr_sim.core @@ -18,12 +18,17 @@ filesets: - cov/clkmgr_cov_bind.sv file_type: systemVerilogSource + files_top_sim: + depend: + - "fileset_top ? (lowrisc:opentitan:top_earlgrey_pwrmgr_pkg:0.1)" + targets: sim: &sim_target toplevel: tb filesets: - files_rtl - files_dv + - files_top_sim default_tool: vcs lint: diff --git a/hw/top_earlgrey/ip_autogen/clkmgr/dv/clkmgr_sim_cfg.hjson b/hw/top_earlgrey/ip_autogen/clkmgr/dv/clkmgr_sim_cfg.hjson index f4dcb41553ceb..35b94b53aeca9 100644 --- a/hw/top_earlgrey/ip_autogen/clkmgr/dv/clkmgr_sim_cfg.hjson +++ b/hw/top_earlgrey/ip_autogen/clkmgr/dv/clkmgr_sim_cfg.hjson @@ -15,7 +15,7 @@ tool: vcs // Fusesoc core file used for building the file list. - fusesoc_core: lowrisc:opentitan:top_earlgrey_clkmgr_sim_top:0.1 + fusesoc_core: lowrisc:opentitan:top_earlgrey_clkmgr_sim:0.1 // Testplan hjson file. testplan: "{self_dir}/../data/clkmgr_testplan.hjson" diff --git a/hw/top_earlgrey/ip_autogen/flash_ctrl/data/top_earlgrey_flash_ctrl.ipconfig.hjson b/hw/top_earlgrey/ip_autogen/flash_ctrl/data/top_earlgrey_flash_ctrl.ipconfig.hjson index 1298910a223ec..2a109eaf2e67a 100644 --- a/hw/top_earlgrey/ip_autogen/flash_ctrl/data/top_earlgrey_flash_ctrl.ipconfig.hjson +++ b/hw/top_earlgrey/ip_autogen/flash_ctrl/data/top_earlgrey_flash_ctrl.ipconfig.hjson @@ -23,6 +23,7 @@ bytes_per_page: 2048 bytes_per_bank: 524288 size: 1048576 + pwrmgr_instance_name: top_earlgrey_ topname: earlgrey } } diff --git a/hw/top_earlgrey/ip_autogen/flash_ctrl/dv/flash_ctrl_base_sim_cfg.hjson b/hw/top_earlgrey/ip_autogen/flash_ctrl/dv/flash_ctrl_base_sim_cfg.hjson index 154b25dc0bd36..28a249ffed02b 100644 --- a/hw/top_earlgrey/ip_autogen/flash_ctrl/dv/flash_ctrl_base_sim_cfg.hjson +++ b/hw/top_earlgrey/ip_autogen/flash_ctrl/dv/flash_ctrl_base_sim_cfg.hjson @@ -12,7 +12,7 @@ tb: tb // Fusesoc core file used for building the file list. - fusesoc_core: lowrisc:opentitan:top_earlgrey_flash_ctrl_sim_top:0.1 + fusesoc_core: lowrisc:opentitan:top_earlgrey_flash_ctrl_sim:0.1 // Testplan hjson file. testplan: "{self_dir}/../data/flash_ctrl_testplan.hjson" diff --git a/hw/top_earlgrey/ip_autogen/flash_ctrl/dv/flash_ctrl_sim.core b/hw/top_earlgrey/ip_autogen/flash_ctrl/dv/flash_ctrl_sim.core index 165f371a92f6c..2ef5cf57bd6d3 100644 --- a/hw/top_earlgrey/ip_autogen/flash_ctrl/dv/flash_ctrl_sim.core +++ b/hw/top_earlgrey/ip_autogen/flash_ctrl/dv/flash_ctrl_sim.core @@ -22,6 +22,10 @@ filesets: - tb/tb.sv file_type: systemVerilogSource + files_top_sim: + depend: + - "fileset_top ? (lowrisc:opentitan:top_earlgrey_pwrmgr_pkg:0.1)" + targets: default: &default_target toplevel: tb @@ -31,7 +35,11 @@ targets: sim: <<: *default_target + filesets_append: + - files_top_sim default_tool: vcs lint: <<: *default_target + filesets_append: + - files_top_sim diff --git a/hw/top_earlgrey/ip_autogen/flash_ctrl/flash_ctrl.core b/hw/top_earlgrey/ip_autogen/flash_ctrl/flash_ctrl.core index 03e07aa98faac..6918ebd7426c0 100644 --- a/hw/top_earlgrey/ip_autogen/flash_ctrl/flash_ctrl.core +++ b/hw/top_earlgrey/ip_autogen/flash_ctrl/flash_ctrl.core @@ -46,6 +46,10 @@ filesets: - rtl/flash_phy_scramble.sv file_type: systemVerilogSource + files_top_lint: + depend: + - "fileset_top ? (lowrisc:opentitan:top_earlgrey_pwrmgr_pkg:0.1)" + files_verilator_waiver: depend: # common waivers @@ -87,6 +91,8 @@ targets: lint: <<: *default_target + filesets_append: + - files_top_lint default_tool: verilator parameters: - SYNTHESIS=true diff --git a/hw/top_earlgrey/ip_autogen/pwrmgr/data/top_earlgrey_pwrmgr.ipconfig.hjson b/hw/top_earlgrey/ip_autogen/pwrmgr/data/top_earlgrey_pwrmgr.ipconfig.hjson index d19e0f97e07ff..085dbf58bb138 100644 --- a/hw/top_earlgrey/ip_autogen/pwrmgr/data/top_earlgrey_pwrmgr.ipconfig.hjson +++ b/hw/top_earlgrey/ip_autogen/pwrmgr/data/top_earlgrey_pwrmgr.ipconfig.hjson @@ -81,6 +81,8 @@ NumRstReqs: 2 wait_for_external_reset: false NumRomInputs: 1 + alert_handler_instance_name: top_earlgrey_ + clkmgr_instance_name: top_earlgrey_ topname: earlgrey } } diff --git a/hw/top_earlgrey/ip_autogen/pwrmgr/dv/env/pwrmgr_env.core b/hw/top_earlgrey/ip_autogen/pwrmgr/dv/env/pwrmgr_env.core index ab7c8ae9634b3..0d3a14575cc8f 100644 --- a/hw/top_earlgrey/ip_autogen/pwrmgr/dv/env/pwrmgr_env.core +++ b/hw/top_earlgrey/ip_autogen/pwrmgr/dv/env/pwrmgr_env.core @@ -9,6 +9,7 @@ filesets: depend: - lowrisc:dv:ralgen - lowrisc:dv:cip_lib + - lowrisc:ip:rv_core_ibex_pkg - lowrisc:opentitan:top_earlgrey_pwrmgr_pkg files: - pwrmgr_env_pkg.sv diff --git a/hw/top_earlgrey/ip_autogen/pwrmgr/dv/pwrmgr_sim.core b/hw/top_earlgrey/ip_autogen/pwrmgr/dv/pwrmgr_sim.core index 5ff0cdf257430..9694595a9e5f3 100644 --- a/hw/top_earlgrey/ip_autogen/pwrmgr/dv/pwrmgr_sim.core +++ b/hw/top_earlgrey/ip_autogen/pwrmgr/dv/pwrmgr_sim.core @@ -17,6 +17,10 @@ filesets: - tb.sv - cov/pwrmgr_cov_bind.sv file_type: systemVerilogSource + files_top_sim: + depend: + - "fileset_top ? (lowrisc:opentitan:top_earlgrey_alert_handler_pkg:0.1)" + - "fileset_top ? (lowrisc:opentitan:top_earlgrey_clkmgr_pwrmgr_sva_if:0.1)" targets: sim: &sim_target @@ -24,6 +28,7 @@ targets: filesets: - files_rtl - files_dv + - files_top_sim default_tool: vcs lint: diff --git a/hw/top_earlgrey/ip_autogen/pwrmgr/dv/pwrmgr_sim_cfg.hjson b/hw/top_earlgrey/ip_autogen/pwrmgr/dv/pwrmgr_sim_cfg.hjson index e45191216e44c..55f1a107ccaef 100644 --- a/hw/top_earlgrey/ip_autogen/pwrmgr/dv/pwrmgr_sim_cfg.hjson +++ b/hw/top_earlgrey/ip_autogen/pwrmgr/dv/pwrmgr_sim_cfg.hjson @@ -15,7 +15,7 @@ tool: vcs // Fusesoc core file used for building the file list. - fusesoc_core: lowrisc:opentitan:top_earlgrey_pwrmgr_sim_top:0.1 + fusesoc_core: lowrisc:opentitan:top_earlgrey_pwrmgr_sim:0.1 // Testplan hjson file. testplan: "{self_dir}/../data/pwrmgr_testplan.hjson" diff --git a/hw/top_earlgrey/ip_autogen/pwrmgr/pwrmgr.core b/hw/top_earlgrey/ip_autogen/pwrmgr/pwrmgr.core index 5684137eadce9..a2c5aecad7d93 100644 --- a/hw/top_earlgrey/ip_autogen/pwrmgr/pwrmgr.core +++ b/hw/top_earlgrey/ip_autogen/pwrmgr/pwrmgr.core @@ -15,6 +15,10 @@ filesets: - lowrisc:opentitan:top_earlgrey_pwrmgr_component:0.1 file_type: systemVerilogSource + files_top_lint: + depend: + - "fileset_top ? (lowrisc:opentitan:top_earlgrey_alert_handler_pkg:0.1)" + files_verilator_waiver: depend: # common waivers @@ -56,6 +60,8 @@ targets: lint: <<: *default_target + filesets_append: + - files_top_lint default_tool: verilator parameters: - SYNTHESIS=true diff --git a/hw/top_earlgrey/ip_autogen/pwrmgr/pwrmgr_components.core b/hw/top_earlgrey/ip_autogen/pwrmgr/pwrmgr_components.core index ab7b43d3d824b..a0813a8af8aae 100644 --- a/hw/top_earlgrey/ip_autogen/pwrmgr/pwrmgr_components.core +++ b/hw/top_earlgrey/ip_autogen/pwrmgr/pwrmgr_components.core @@ -19,6 +19,7 @@ filesets: - lowrisc:prim:mubi - lowrisc:prim:clock_buf - lowrisc:prim:measure + - lowrisc:ip:rv_core_ibex_pkg - lowrisc:ip_interfaces:alert_handler_pkg - lowrisc:opentitan:top_earlgrey_pwrmgr_pkg files: diff --git a/hw/top_earlgrey/ip_autogen/rstmgr/data/top_earlgrey_rstmgr.ipconfig.hjson b/hw/top_earlgrey/ip_autogen/rstmgr/data/top_earlgrey_rstmgr.ipconfig.hjson index 2a94324782441..9210ae5f22ed3 100644 --- a/hw/top_earlgrey/ip_autogen/rstmgr/data/top_earlgrey_rstmgr.ipconfig.hjson +++ b/hw/top_earlgrey/ip_autogen/rstmgr/data/top_earlgrey_rstmgr.ipconfig.hjson @@ -691,6 +691,8 @@ rst_ni: lc_io_div4 export_rsts: {} with_alert_handler: true + pwrmgr_instance_name: top_earlgrey_ + alert_handler_instance_name: top_earlgrey_ topname: earlgrey } } diff --git a/hw/top_earlgrey/ip_autogen/rstmgr/dv/rstmgr_sim.core b/hw/top_earlgrey/ip_autogen/rstmgr/dv/rstmgr_sim.core index 71c93d278eb87..e66d672b7182d 100644 --- a/hw/top_earlgrey/ip_autogen/rstmgr/dv/rstmgr_sim.core +++ b/hw/top_earlgrey/ip_autogen/rstmgr/dv/rstmgr_sim.core @@ -17,6 +17,11 @@ filesets: - tb.sv - cov/rstmgr_cov_bind.sv file_type: systemVerilogSource + files_top_sim: + depend: + - "fileset_top ? (lowrisc:opentitan:top_earlgrey_alert_handler_pkg:0.1)" + - "fileset_top ? (lowrisc:opentitan:top_earlgrey_pwrmgr_pkg:0.1)" + - "fileset_top ? (lowrisc:opentitan:top_earlgrey_pwrmgr_rstmgr_sva_if:0.1)" targets: sim: &sim_target @@ -24,6 +29,7 @@ targets: filesets: - files_rtl - files_dv + - files_top_sim default_tool: vcs lint: diff --git a/hw/top_earlgrey/ip_autogen/rstmgr/dv/rstmgr_sim_cfg.hjson b/hw/top_earlgrey/ip_autogen/rstmgr/dv/rstmgr_sim_cfg.hjson index 1fd447beb0edc..a9c4185dcebf7 100644 --- a/hw/top_earlgrey/ip_autogen/rstmgr/dv/rstmgr_sim_cfg.hjson +++ b/hw/top_earlgrey/ip_autogen/rstmgr/dv/rstmgr_sim_cfg.hjson @@ -15,7 +15,7 @@ tool: vcs // Fusesoc core file used for building the file list. - fusesoc_core: lowrisc:opentitan:top_earlgrey_rstmgr_sim_top:0.1 + fusesoc_core: lowrisc:opentitan:top_earlgrey_rstmgr_sim:0.1 // Testplan hjson file. testplan: "{self_dir}/../data/rstmgr_testplan.hjson" diff --git a/hw/top_earlgrey/ip_autogen/rstmgr/rstmgr.core b/hw/top_earlgrey/ip_autogen/rstmgr/rstmgr.core index c36b53ed3c94d..67707db194234 100644 --- a/hw/top_earlgrey/ip_autogen/rstmgr/rstmgr.core +++ b/hw/top_earlgrey/ip_autogen/rstmgr/rstmgr.core @@ -30,6 +30,11 @@ filesets: - rtl/rstmgr.sv file_type: systemVerilogSource + files_top_lint: + depend: + - "fileset_top ? (lowrisc:opentitan:top_earlgrey_alert_handler_pkg:0.1)" + - "fileset_top ? (lowrisc:opentitan:top_earlgrey_pwrmgr_pkg:0.1)" + files_verilator_waiver: depend: # common waivers @@ -61,6 +66,8 @@ targets: lint: <<: *default_target + filesets_append: + - files_top_lint default_tool: verilator parameters: - SYNTHESIS=true diff --git a/hw/top_earlgrey/lint/top_earlgrey_lint_cfgs.hjson b/hw/top_earlgrey/lint/top_earlgrey_lint_cfgs.hjson index f36c7ac645e07..3e3b7abd9b31f 100644 --- a/hw/top_earlgrey/lint/top_earlgrey_lint_cfgs.hjson +++ b/hw/top_earlgrey/lint/top_earlgrey_lint_cfgs.hjson @@ -64,7 +64,7 @@ rel_path: "hw/ip/entropy_src/lint/{tool}" }, { name: clkmgr - fusesoc_core: lowrisc:opentitan:top_earlgrey_clkmgr_sim_top + fusesoc_core: lowrisc:opentitan:top_earlgrey_clkmgr_sim import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"], rel_path: "hw/top_earlgrey/ip_autogen/clkmgr/lint/{tool}", overrides: [ @@ -90,7 +90,7 @@ rel_path: "hw/ip/edn/lint/{tool}" }, { name: flash_ctrl - fusesoc_core: lowrisc:opentitan:top_earlgrey_flash_ctrl_sim_top + fusesoc_core: lowrisc:opentitan:top_earlgrey_flash_ctrl_sim import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"] rel_path: "hw/top_earlgrey/ip_autogen/flash_ctrl/lint/{tool}" overrides: [ @@ -180,7 +180,7 @@ ] }, { name: pwrmgr - fusesoc_core: lowrisc:opentitan:top_earlgrey_pwrmgr_sim_top + fusesoc_core: lowrisc:opentitan:top_earlgrey_pwrmgr_sim import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"], rel_path: "hw/top_earlgrey/ip_autogen/pwrmgr/lint/{tool}", overrides: [ @@ -196,7 +196,7 @@ rel_path: "hw/ip/rom_ctrl/lint/{tool}" }, { name: rstmgr - fusesoc_core: lowrisc:opentitan:top_earlgrey_rstmgr_sim_top + fusesoc_core: lowrisc:opentitan:top_earlgrey_rstmgr_sim import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"], rel_path: "hw/top_earlgrey/ip_autogen/rstmgr/lint/{tool}", overrides: [ diff --git a/hw/top_englishbreakfast/ip_autogen/clkmgr/clkmgr.core b/hw/top_englishbreakfast/ip_autogen/clkmgr/clkmgr.core index 7e1c431228c2f..0588cafcce347 100644 --- a/hw/top_englishbreakfast/ip_autogen/clkmgr/clkmgr.core +++ b/hw/top_englishbreakfast/ip_autogen/clkmgr/clkmgr.core @@ -33,6 +33,10 @@ filesets: - rtl/clkmgr_trans.sv file_type: systemVerilogSource + files_top_lint: + depend: + - "fileset_top ? (lowrisc:opentitan:top_englishbreakfast_pwrmgr_pkg:0.1)" + files_verilator_waiver: depend: # common waivers @@ -63,6 +67,8 @@ targets: lint: <<: *default_target + filesets_append: + - files_top_lint default_tool: verilator parameters: - SYNTHESIS=true diff --git a/hw/top_englishbreakfast/ip_autogen/clkmgr/data/top_englishbreakfast_clkmgr.ipconfig.hjson b/hw/top_englishbreakfast/ip_autogen/clkmgr/data/top_englishbreakfast_clkmgr.ipconfig.hjson index c8aa95e9d0a06..c272dd834b45b 100644 --- a/hw/top_englishbreakfast/ip_autogen/clkmgr/data/top_englishbreakfast_clkmgr.ipconfig.hjson +++ b/hw/top_englishbreakfast/ip_autogen/clkmgr/data/top_englishbreakfast_clkmgr.ipconfig.hjson @@ -236,6 +236,7 @@ exported_clks: {} number_of_clock_groups: 8 with_alert_handler: false + pwrmgr_instance_name: top_englishbreakfast_ topname: englishbreakfast } } diff --git a/hw/top_englishbreakfast/ip_autogen/clkmgr/dv/clkmgr_sim.core b/hw/top_englishbreakfast/ip_autogen/clkmgr/dv/clkmgr_sim.core index 06cf747760ef2..7cbf3b11b39a0 100644 --- a/hw/top_englishbreakfast/ip_autogen/clkmgr/dv/clkmgr_sim.core +++ b/hw/top_englishbreakfast/ip_autogen/clkmgr/dv/clkmgr_sim.core @@ -18,12 +18,17 @@ filesets: - cov/clkmgr_cov_bind.sv file_type: systemVerilogSource + files_top_sim: + depend: + - "fileset_top ? (lowrisc:opentitan:top_englishbreakfast_pwrmgr_pkg:0.1)" + targets: sim: &sim_target toplevel: tb filesets: - files_rtl - files_dv + - files_top_sim default_tool: vcs lint: diff --git a/hw/top_englishbreakfast/ip_autogen/clkmgr/dv/clkmgr_sim_cfg.hjson b/hw/top_englishbreakfast/ip_autogen/clkmgr/dv/clkmgr_sim_cfg.hjson index 390f9f902072f..8b0923c9aafed 100644 --- a/hw/top_englishbreakfast/ip_autogen/clkmgr/dv/clkmgr_sim_cfg.hjson +++ b/hw/top_englishbreakfast/ip_autogen/clkmgr/dv/clkmgr_sim_cfg.hjson @@ -15,7 +15,7 @@ tool: vcs // Fusesoc core file used for building the file list. - fusesoc_core: lowrisc:opentitan:top_englishbreakfast_clkmgr_sim_top:0.1 + fusesoc_core: lowrisc:opentitan:top_englishbreakfast_clkmgr_sim:0.1 // Testplan hjson file. testplan: "{self_dir}/../data/clkmgr_testplan.hjson" diff --git a/hw/top_englishbreakfast/ip_autogen/flash_ctrl/data/top_englishbreakfast_flash_ctrl.ipconfig.hjson b/hw/top_englishbreakfast/ip_autogen/flash_ctrl/data/top_englishbreakfast_flash_ctrl.ipconfig.hjson index 166b6e1c02cc6..9ff864170933b 100644 --- a/hw/top_englishbreakfast/ip_autogen/flash_ctrl/data/top_englishbreakfast_flash_ctrl.ipconfig.hjson +++ b/hw/top_englishbreakfast/ip_autogen/flash_ctrl/data/top_englishbreakfast_flash_ctrl.ipconfig.hjson @@ -23,6 +23,7 @@ bytes_per_page: 2048 bytes_per_bank: 32768 size: 65536 + pwrmgr_instance_name: top_englishbreakfast_ topname: englishbreakfast } } diff --git a/hw/top_englishbreakfast/ip_autogen/flash_ctrl/dv/flash_ctrl_base_sim_cfg.hjson b/hw/top_englishbreakfast/ip_autogen/flash_ctrl/dv/flash_ctrl_base_sim_cfg.hjson index e2fedda3df460..ccb3368730578 100644 --- a/hw/top_englishbreakfast/ip_autogen/flash_ctrl/dv/flash_ctrl_base_sim_cfg.hjson +++ b/hw/top_englishbreakfast/ip_autogen/flash_ctrl/dv/flash_ctrl_base_sim_cfg.hjson @@ -12,7 +12,7 @@ tb: tb // Fusesoc core file used for building the file list. - fusesoc_core: lowrisc:opentitan:top_englishbreakfast_flash_ctrl_sim_top:0.1 + fusesoc_core: lowrisc:opentitan:top_englishbreakfast_flash_ctrl_sim:0.1 // Testplan hjson file. testplan: "{self_dir}/../data/flash_ctrl_testplan.hjson" diff --git a/hw/top_englishbreakfast/ip_autogen/flash_ctrl/dv/flash_ctrl_sim.core b/hw/top_englishbreakfast/ip_autogen/flash_ctrl/dv/flash_ctrl_sim.core index 6ed5eca4927f8..d0c35710b30a8 100644 --- a/hw/top_englishbreakfast/ip_autogen/flash_ctrl/dv/flash_ctrl_sim.core +++ b/hw/top_englishbreakfast/ip_autogen/flash_ctrl/dv/flash_ctrl_sim.core @@ -22,6 +22,10 @@ filesets: - tb/tb.sv file_type: systemVerilogSource + files_top_sim: + depend: + - "fileset_top ? (lowrisc:opentitan:top_englishbreakfast_pwrmgr_pkg:0.1)" + targets: default: &default_target toplevel: tb @@ -31,7 +35,11 @@ targets: sim: <<: *default_target + filesets_append: + - files_top_sim default_tool: vcs lint: <<: *default_target + filesets_append: + - files_top_sim diff --git a/hw/top_englishbreakfast/ip_autogen/flash_ctrl/flash_ctrl.core b/hw/top_englishbreakfast/ip_autogen/flash_ctrl/flash_ctrl.core index 91658f7e19b35..4dcae766ea9d9 100644 --- a/hw/top_englishbreakfast/ip_autogen/flash_ctrl/flash_ctrl.core +++ b/hw/top_englishbreakfast/ip_autogen/flash_ctrl/flash_ctrl.core @@ -46,6 +46,10 @@ filesets: - rtl/flash_phy_scramble.sv file_type: systemVerilogSource + files_top_lint: + depend: + - "fileset_top ? (lowrisc:opentitan:top_englishbreakfast_pwrmgr_pkg:0.1)" + files_verilator_waiver: depend: # common waivers @@ -87,6 +91,8 @@ targets: lint: <<: *default_target + filesets_append: + - files_top_lint default_tool: verilator parameters: - SYNTHESIS=true diff --git a/hw/top_englishbreakfast/ip_autogen/pwrmgr/data/top_englishbreakfast_pwrmgr.ipconfig.hjson b/hw/top_englishbreakfast/ip_autogen/pwrmgr/data/top_englishbreakfast_pwrmgr.ipconfig.hjson index a69c00c1928ba..0683872adda48 100644 --- a/hw/top_englishbreakfast/ip_autogen/pwrmgr/data/top_englishbreakfast_pwrmgr.ipconfig.hjson +++ b/hw/top_englishbreakfast/ip_autogen/pwrmgr/data/top_englishbreakfast_pwrmgr.ipconfig.hjson @@ -60,6 +60,8 @@ NumRstReqs: 1 wait_for_external_reset: false NumRomInputs: 1 + alert_handler_instance_name: top_englishbreakfast_ + clkmgr_instance_name: top_englishbreakfast_ topname: englishbreakfast } } diff --git a/hw/top_englishbreakfast/ip_autogen/pwrmgr/dv/env/pwrmgr_env.core b/hw/top_englishbreakfast/ip_autogen/pwrmgr/dv/env/pwrmgr_env.core index e1251b5d8ca86..4f5349c7a5a0a 100644 --- a/hw/top_englishbreakfast/ip_autogen/pwrmgr/dv/env/pwrmgr_env.core +++ b/hw/top_englishbreakfast/ip_autogen/pwrmgr/dv/env/pwrmgr_env.core @@ -9,6 +9,7 @@ filesets: depend: - lowrisc:dv:ralgen - lowrisc:dv:cip_lib + - lowrisc:ip:rv_core_ibex_pkg - lowrisc:opentitan:top_englishbreakfast_pwrmgr_pkg files: - pwrmgr_env_pkg.sv diff --git a/hw/top_englishbreakfast/ip_autogen/pwrmgr/dv/pwrmgr_sim.core b/hw/top_englishbreakfast/ip_autogen/pwrmgr/dv/pwrmgr_sim.core index 63f81c3200bbb..6e7f7bfdb874b 100644 --- a/hw/top_englishbreakfast/ip_autogen/pwrmgr/dv/pwrmgr_sim.core +++ b/hw/top_englishbreakfast/ip_autogen/pwrmgr/dv/pwrmgr_sim.core @@ -17,6 +17,10 @@ filesets: - tb.sv - cov/pwrmgr_cov_bind.sv file_type: systemVerilogSource + files_top_sim: + depend: + - "fileset_top ? (lowrisc:opentitan:top_englishbreakfast_alert_handler_pkg:0.1)" + - "fileset_top ? (lowrisc:opentitan:top_englishbreakfast_clkmgr_pwrmgr_sva_if:0.1)" targets: sim: &sim_target @@ -24,6 +28,7 @@ targets: filesets: - files_rtl - files_dv + - files_top_sim default_tool: vcs lint: diff --git a/hw/top_englishbreakfast/ip_autogen/pwrmgr/dv/pwrmgr_sim_cfg.hjson b/hw/top_englishbreakfast/ip_autogen/pwrmgr/dv/pwrmgr_sim_cfg.hjson index f77215335c262..c0dbeecc54817 100644 --- a/hw/top_englishbreakfast/ip_autogen/pwrmgr/dv/pwrmgr_sim_cfg.hjson +++ b/hw/top_englishbreakfast/ip_autogen/pwrmgr/dv/pwrmgr_sim_cfg.hjson @@ -15,7 +15,7 @@ tool: vcs // Fusesoc core file used for building the file list. - fusesoc_core: lowrisc:opentitan:top_englishbreakfast_pwrmgr_sim_top:0.1 + fusesoc_core: lowrisc:opentitan:top_englishbreakfast_pwrmgr_sim:0.1 // Testplan hjson file. testplan: "{self_dir}/../data/pwrmgr_testplan.hjson" diff --git a/hw/top_englishbreakfast/ip_autogen/pwrmgr/pwrmgr.core b/hw/top_englishbreakfast/ip_autogen/pwrmgr/pwrmgr.core index 7a2917351372e..5bd6c18ebfb9e 100644 --- a/hw/top_englishbreakfast/ip_autogen/pwrmgr/pwrmgr.core +++ b/hw/top_englishbreakfast/ip_autogen/pwrmgr/pwrmgr.core @@ -15,6 +15,10 @@ filesets: - lowrisc:opentitan:top_englishbreakfast_pwrmgr_component:0.1 file_type: systemVerilogSource + files_top_lint: + depend: + - "fileset_top ? (lowrisc:opentitan:top_englishbreakfast_alert_handler_pkg:0.1)" + files_verilator_waiver: depend: # common waivers @@ -56,6 +60,8 @@ targets: lint: <<: *default_target + filesets_append: + - files_top_lint default_tool: verilator parameters: - SYNTHESIS=true diff --git a/hw/top_englishbreakfast/ip_autogen/pwrmgr/pwrmgr_components.core b/hw/top_englishbreakfast/ip_autogen/pwrmgr/pwrmgr_components.core index 8c60d906bd288..7cc63540f57e8 100644 --- a/hw/top_englishbreakfast/ip_autogen/pwrmgr/pwrmgr_components.core +++ b/hw/top_englishbreakfast/ip_autogen/pwrmgr/pwrmgr_components.core @@ -19,6 +19,7 @@ filesets: - lowrisc:prim:mubi - lowrisc:prim:clock_buf - lowrisc:prim:measure + - lowrisc:ip:rv_core_ibex_pkg - lowrisc:ip_interfaces:alert_handler_pkg - lowrisc:opentitan:top_englishbreakfast_pwrmgr_pkg files: diff --git a/hw/top_englishbreakfast/ip_autogen/rstmgr/data/top_englishbreakfast_rstmgr.ipconfig.hjson b/hw/top_englishbreakfast/ip_autogen/rstmgr/data/top_englishbreakfast_rstmgr.ipconfig.hjson index e4c88bb28c18d..f7bfe59d1c1d3 100644 --- a/hw/top_englishbreakfast/ip_autogen/rstmgr/data/top_englishbreakfast_rstmgr.ipconfig.hjson +++ b/hw/top_englishbreakfast/ip_autogen/rstmgr/data/top_englishbreakfast_rstmgr.ipconfig.hjson @@ -451,6 +451,7 @@ rst_ni: lc_io_div4 export_rsts: {} with_alert_handler: false + pwrmgr_instance_name: top_englishbreakfast_ topname: englishbreakfast } } diff --git a/hw/top_englishbreakfast/ip_autogen/rstmgr/dv/rstmgr_sim.core b/hw/top_englishbreakfast/ip_autogen/rstmgr/dv/rstmgr_sim.core index 9edbcbd955fde..09ce2429465a9 100644 --- a/hw/top_englishbreakfast/ip_autogen/rstmgr/dv/rstmgr_sim.core +++ b/hw/top_englishbreakfast/ip_autogen/rstmgr/dv/rstmgr_sim.core @@ -17,6 +17,10 @@ filesets: - tb.sv - cov/rstmgr_cov_bind.sv file_type: systemVerilogSource + files_top_sim: + depend: + - "fileset_top ? (lowrisc:opentitan:top_englishbreakfast_pwrmgr_pkg:0.1)" + - "fileset_top ? (lowrisc:opentitan:top_englishbreakfast_pwrmgr_rstmgr_sva_if:0.1)" targets: sim: &sim_target @@ -24,6 +28,7 @@ targets: filesets: - files_rtl - files_dv + - files_top_sim default_tool: vcs lint: diff --git a/hw/top_englishbreakfast/ip_autogen/rstmgr/dv/rstmgr_sim_cfg.hjson b/hw/top_englishbreakfast/ip_autogen/rstmgr/dv/rstmgr_sim_cfg.hjson index 2be126bc7920f..7865f569bd99e 100644 --- a/hw/top_englishbreakfast/ip_autogen/rstmgr/dv/rstmgr_sim_cfg.hjson +++ b/hw/top_englishbreakfast/ip_autogen/rstmgr/dv/rstmgr_sim_cfg.hjson @@ -15,7 +15,7 @@ tool: vcs // Fusesoc core file used for building the file list. - fusesoc_core: lowrisc:opentitan:top_englishbreakfast_rstmgr_sim_top:0.1 + fusesoc_core: lowrisc:opentitan:top_englishbreakfast_rstmgr_sim:0.1 // Testplan hjson file. testplan: "{self_dir}/../data/rstmgr_testplan.hjson" diff --git a/hw/top_englishbreakfast/ip_autogen/rstmgr/rstmgr.core b/hw/top_englishbreakfast/ip_autogen/rstmgr/rstmgr.core index 7d33b9ad9f28f..0d501b043adc8 100644 --- a/hw/top_englishbreakfast/ip_autogen/rstmgr/rstmgr.core +++ b/hw/top_englishbreakfast/ip_autogen/rstmgr/rstmgr.core @@ -30,6 +30,10 @@ filesets: - rtl/rstmgr.sv file_type: systemVerilogSource + files_top_lint: + depend: + - "fileset_top ? (lowrisc:opentitan:top_englishbreakfast_pwrmgr_pkg:0.1)" + files_verilator_waiver: depend: # common waivers @@ -61,6 +65,8 @@ targets: lint: <<: *default_target + filesets_append: + - files_top_lint default_tool: verilator parameters: - SYNTHESIS=true diff --git a/util/ipgen/renderer.py b/util/ipgen/renderer.py index 7b2543a5eb7fe..0f5b38163b94c 100644 --- a/util/ipgen/renderer.py +++ b/util/ipgen/renderer.py @@ -98,7 +98,7 @@ def _get_mako_template_lookup(self) -> MakoTemplateLookup: strict_undefined=True) return self._lookup - def _tplfunc_instance_vlnv(self, template_vlnv_str: str) -> str: + def _tplfunc_instance_vlnv(self, template_vlnv_str: str, prefix: str = None) -> str: """Makes a vlnv into an instance specific one. A vlnv is a string of the form vendor:library:name[:version] where @@ -125,6 +125,11 @@ def _tplfunc_instance_vlnv(self, template_vlnv_str: str) -> str: template_core_version = (template_vlnv[3] if len(template_vlnv) == 4 else None) + if prefix is None: + template_core_prefix = self.ip_config.instance_name + else: + template_core_prefix = prefix + if "module_instance_name" in self.ip_config.param_values: if not template_core_name.startswith( self.ip_config.param_values["module_instance_name"]): @@ -137,7 +142,7 @@ def _tplfunc_instance_vlnv(self, template_vlnv_str: str) -> str: template_core_name = template_core_name[len(self.ip_template.name ):] - instance_core_name = self.ip_config.instance_name + template_core_name + instance_core_name = template_core_prefix + template_core_name instance_vlnv = ['lowrisc', 'opentitan', instance_core_name] if template_core_version is not None: diff --git a/util/topgen.py b/util/topgen.py index d42d53a71166d..8cabee966f474 100755 --- a/util/topgen.py +++ b/util/topgen.py @@ -393,6 +393,7 @@ def generate_clkmgr(topcfg: Dict[str, object], out_path: Path) -> None: "exported_clks": topcfg["exported_clks"], "number_of_clock_groups": len(clocks.groups), "with_alert_handler": with_alert_handler, + "pwrmgr_instance_name": f"top_{topname}_", } ipgen_render("clkmgr", topname, params, out_path) @@ -434,6 +435,8 @@ def generate_pwrmgr(top: Dict[str, object], out_path: Path) -> None: "NumRstReqs": n_rstreqs, "wait_for_external_reset": top['power']['wait_for_external_reset'], "NumRomInputs": n_rom_ctrl, + "alert_handler_instance_name": f"top_{topname}_", + "clkmgr_instance_name": f"top_{topname}_", } ipgen_render("pwrmgr", topname, params, out_path) @@ -487,7 +490,10 @@ def generate_rstmgr(topcfg: Dict[str, object], out_path: Path) -> None: "rst_ni": rst_ni['rst_ni']['name'], "export_rsts": topcfg["exported_rsts"], "with_alert_handler": with_alert_handler, + "pwrmgr_instance_name": f"top_{topname}_", } + if with_alert_handler: + params.update({"alert_handler_instance_name": f"top_{topname}_"}) ipgen_render("rstmgr", topname, params, out_path) @@ -513,7 +519,8 @@ def generate_flash(topcfg: Dict[str, object], out_path: Path) -> None: params.update({ "metadata_width": 12, "info_types": 3, - "infos_per_bank": [10, 1, 2] + "infos_per_bank": [10, 1, 2], + "pwrmgr_instance_name": f"top_{topname}_", }) params.pop('base_addrs', None)