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Antti Lukats edited this page Jan 26, 2019
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| Category | Prize pool $ | Other prizes | Sponsor(s) |
|---|---|---|---|
| Embedded MCU/Open | |||
| Microcode/Open | |||
| Bit Serial | |||
| Retro-2018 |
Microcontroller Class design with open specification. There is no fixed specification or detailed requirements, the design should be competing with existing FPGA Soft CPU's used as small micro controllers, like:
- Xilinx Microblaze MCS
- Intel NIOS/e
- Lattice Mico8/32
- Actel ABC
Requirements mandatory
- must execute object code (ELF) compiled with mainstream RISC-V compiler
- must include specification document about the implementation
Requirements optional
- at least one output port with write strobe (like AXI-S TVALID)
- at least one input port with ready handshake (like AXI-S TREADY)
- at least one asynchronous output port (GPIO like)
- at least one asynchronous input port (GPIO like)
Notes:
- It is assumed this is not microcode based design, but microcode is not directly excluded
- If heavily optimized for (multi) FPGA vendor technology a separate simulator friendly generic code should be provided
Here the rules as initially published for the soft CPU contest in 2018 should be applied. Some requirements are relaxed.