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miner_hw.tcl
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# TCL File Generated by Component Editor 18.1
# Sat Aug 15 22:15:43 EDT 2020
# DO NOT MODIFY
#
# miner "miner" v1.1
# jcyr 2020.08.15.22:15:43
# SHA3-256 Miner Avalon Slave
#
#
# request TCL package from ACDS 16.1
#
package require -exact qsys 16.1
#
# module miner
#
set_module_property DESCRIPTION "SHA3-256 Miner Avalon Slave"
set_module_property NAME miner
set_module_property VERSION 1.1
set_module_property INTERNAL false
set_module_property OPAQUE_ADDRESS_MAP true
set_module_property AUTHOR jcyr
set_module_property DISPLAY_NAME miner
set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
set_module_property EDITABLE true
set_module_property REPORT_TO_TALKBACK false
set_module_property ALLOW_GREYBOX_GENERATION false
set_module_property REPORT_HIERARCHY false
#
# file sets
#
add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" ""
set_fileset_property QUARTUS_SYNTH TOP_LEVEL miner
set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE false
add_fileset_file miner.v VERILOG PATH miner_ip/miner.v TOP_LEVEL_FILE
add_fileset_file sha3_256_miner.v VERILOG PATH miner_ip/sha3_256_miner.v
add_fileset_file permutation.v VERILOG PATH miner_ip/permutation.v
#
# documentation links
#
add_documentation_link miner file:///doc/miner.html
#
# parameters
#
add_parameter MINER_CLK_MHZ STRING "60 MHz" "Miner clock frequency"
set_parameter_property MINER_CLK_MHZ DEFAULT_VALUE "60 MHz"
set_parameter_property MINER_CLK_MHZ DISPLAY_NAME MINER_CLK_MHZ
set_parameter_property MINER_CLK_MHZ TYPE STRING
set_parameter_property MINER_CLK_MHZ UNITS None
set_parameter_property MINER_CLK_MHZ DESCRIPTION "Miner clock frequency"
set_parameter_property MINER_CLK_MHZ HDL_PARAMETER true
add_parameter MINER_MAJ_VER INTEGER 1 "Miner major version"
set_parameter_property MINER_MAJ_VER DEFAULT_VALUE 1
set_parameter_property MINER_MAJ_VER DISPLAY_NAME MINER_MAJ_VER
set_parameter_property MINER_MAJ_VER TYPE INTEGER
set_parameter_property MINER_MAJ_VER ENABLED false
set_parameter_property MINER_MAJ_VER UNITS None
set_parameter_property MINER_MAJ_VER ALLOWED_RANGES -2147483648:2147483647
set_parameter_property MINER_MAJ_VER DESCRIPTION "Miner major version"
set_parameter_property MINER_MAJ_VER HDL_PARAMETER true
add_parameter MINER_MIN_VER INTEGER 1 "Miner minor version"
set_parameter_property MINER_MIN_VER DEFAULT_VALUE 1
set_parameter_property MINER_MIN_VER DISPLAY_NAME MINER_MIN_VER
set_parameter_property MINER_MIN_VER TYPE INTEGER
set_parameter_property MINER_MIN_VER ENABLED false
set_parameter_property MINER_MIN_VER UNITS None
set_parameter_property MINER_MIN_VER ALLOWED_RANGES -2147483648:2147483647
set_parameter_property MINER_MIN_VER DESCRIPTION "Miner minor version"
set_parameter_property MINER_MIN_VER HDL_PARAMETER true
add_parameter STAGES INTEGER 8 "# of pipeline stages (8.4.or 2)"
set_parameter_property STAGES DEFAULT_VALUE 8
set_parameter_property STAGES DISPLAY_NAME STAGES
set_parameter_property STAGES TYPE INTEGER
set_parameter_property STAGES UNITS None
set_parameter_property STAGES ALLOWED_RANGES -2147483648:2147483647
set_parameter_property STAGES DESCRIPTION "# of pipeline stages (8.4.or 2)"
set_parameter_property STAGES HDL_PARAMETER true
#
# module assignments
#
set_module_assignment embeddedsw.dts.compatible dev,miner
set_module_assignment embeddedsw.dts.group miner
set_module_assignment embeddedsw.dts.vendor cyr
#
# display items
#
#
# connection point sl
#
add_interface sl avalon end
set_interface_property sl addressUnits WORDS
set_interface_property sl associatedClock clk
set_interface_property sl associatedReset reset
set_interface_property sl bitsPerSymbol 8
set_interface_property sl burstOnBurstBoundariesOnly false
set_interface_property sl burstcountUnits WORDS
set_interface_property sl explicitAddressSpan 0
set_interface_property sl holdTime 0
set_interface_property sl linewrapBursts false
set_interface_property sl maximumPendingReadTransactions 0
set_interface_property sl maximumPendingWriteTransactions 0
set_interface_property sl readLatency 0
set_interface_property sl readWaitTime 1
set_interface_property sl setupTime 0
set_interface_property sl timingUnits Cycles
set_interface_property sl writeWaitTime 0
set_interface_property sl ENABLED true
set_interface_property sl EXPORT_OF ""
set_interface_property sl PORT_NAME_MAP ""
set_interface_property sl CMSIS_SVD_VARIABLES ""
set_interface_property sl SVD_ADDRESS_GROUP ""
add_interface_port sl address address Input 5
add_interface_port sl read read Input 1
add_interface_port sl readdata readdata Output 32
add_interface_port sl write write Input 1
add_interface_port sl writedata writedata Input 32
set_interface_assignment sl embeddedsw.configuration.isFlash 0
set_interface_assignment sl embeddedsw.configuration.isMemoryDevice 0
set_interface_assignment sl embeddedsw.configuration.isNonVolatileStorage 0
set_interface_assignment sl embeddedsw.configuration.isPrintableDevice 0
#
# connection point irq
#
add_interface irq interrupt end
set_interface_property irq associatedAddressablePoint sl
set_interface_property irq associatedClock clk
set_interface_property irq associatedReset reset
set_interface_property irq bridgedReceiverOffset ""
set_interface_property irq bridgesToReceiver ""
set_interface_property irq ENABLED true
set_interface_property irq EXPORT_OF ""
set_interface_property irq PORT_NAME_MAP ""
set_interface_property irq CMSIS_SVD_VARIABLES ""
set_interface_property irq SVD_ADDRESS_GROUP ""
add_interface_port irq irq irq Output 1
#
# connection point clk
#
add_interface clk clock end
set_interface_property clk clockRate 0
set_interface_property clk ENABLED true
set_interface_property clk EXPORT_OF ""
set_interface_property clk PORT_NAME_MAP ""
set_interface_property clk CMSIS_SVD_VARIABLES ""
set_interface_property clk SVD_ADDRESS_GROUP ""
add_interface_port clk clk clk Input 1
#
# connection point reset
#
add_interface reset reset end
set_interface_property reset associatedClock clk
set_interface_property reset synchronousEdges DEASSERT
set_interface_property reset ENABLED true
set_interface_property reset EXPORT_OF ""
set_interface_property reset PORT_NAME_MAP ""
set_interface_property reset CMSIS_SVD_VARIABLES ""
set_interface_property reset SVD_ADDRESS_GROUP ""
add_interface_port reset rst reset Input 1