diff --git a/.cargo/config b/.cargo/config.toml similarity index 100% rename from .cargo/config rename to .cargo/config.toml diff --git a/Cargo.toml b/Cargo.toml index 46c79b71..a8dd079c 100644 --- a/Cargo.toml +++ b/Cargo.toml @@ -17,4 +17,4 @@ cortex-m-rt = ">=0.6.15,<0.8" # meta-dependencies (upgrade as needed, they apply to all PACs): # @svd2rust = 0.25.1 -# @form = 0.10.0 +# @form = 0.12.1 diff --git a/README.md b/README.md index aff2b808..aba4047e 100644 --- a/README.md +++ b/README.md @@ -31,6 +31,7 @@ Every nRF chip has its own PAC, listed below: | `nrf5340-app-pac` | [![docs.rs](https://docs.rs/nrf5340-app-pac/badge.svg)](https://docs.rs/nrf5340-app-pac) | [![crates.io](https://img.shields.io/crates/d/nrf5340-app-pac.svg)](https://crates.io/crates/nrf5340-app-pac) | `thumbv8m.main-none-eabihf` | | `nrf5340-net-pac` | [![docs.rs](https://docs.rs/nrf5340-net-pac/badge.svg)](https://docs.rs/nrf5340-net-pac) | [![crates.io](https://img.shields.io/crates/d/nrf5340-net-pac.svg)](https://crates.io/crates/nrf5340-net-pac) | `thumbv8m.main-none-eabihf` | | `nrf9160-pac` | [![docs.rs](https://docs.rs/nrf9160-pac/badge.svg)](https://docs.rs/nrf9160-pac) | [![crates.io](https://img.shields.io/crates/d/nrf9160-pac.svg)](https://crates.io/crates/nrf9160-pac) | `thumbv8m.main-none-eabihf` | +| `nrf9120-pac` | [![docs.rs](https://docs.rs/nrf9120-pac/badge.svg)](https://docs.rs/nrf9120-pac) | [![crates.io](https://img.shields.io/crates/d/nrf9120-pac.svg)](https://crates.io/crates/nrf9120-pac) | `thumbv8m.main-none-eabihf` | ## Device Reference Manuals from Nordic @@ -46,5 +47,9 @@ Every nRF chip has its own PAC, listed below: | [`nRF52840`](https://www.nordicsemi.com/Products/nRF52840) | [`v1.1`](https://infocenter.nordicsemi.com/pdf/nRF52840_PS_v1.1.pdf) | [`v1.2`](https://infocenter.nordicsemi.com/pdf/nRF52840_DK_User_Guide_v1.2.pdf) | | [`nRF5340`](https://www.nordicsemi.com/Products/nRF5340) | [`v1.1`](https://infocenter.nordicsemi.com/pdf/nRF5340_PS_v1.1.pdf) | [`v1.0.0`](https://infocenter.nordicsemi.com/pdf/nRF5340_DK_User_Guide_20210304.pdf) | | [`nRF9160`](https://www.nordicsemi.com/Products/nrf9160) | [`v2.0`](https://infocenter.nordicsemi.com/pdf/nRF9160_PS_v2.0.pdf) | [`v0.9.3`](https://infocenter.nordicsemi.com/pdf/nRF9160_DK_HW_User_Guide_v0.9.3.pdf) | +| [`nRF9161 (nrf9120)`](https://www.nordicsemi.com/Products/nRF9161) | [`v1.0`](https://infocenter.nordicsemi.com/pdf/nRF9161_PS_v1.0.pdf) | [`v0.9.1`](https://infocenter.nordicsemi.com/pdf/nRF9161_DK_HW_User_Guide_v0.9.1.pdf) | +| [`nRF9151 (nrf9120)`](https://www.nordicsemi.com/Products/nRF9151) | ** | ** | \* These devices do not have a separate development kit and share the [NRF52 DK](https://www.nordicsemi.com/Software-and-tools/Development-Kits/nRF52-DK) + +\*\* As of 2024-6-28, the Product Specification and the DK Reference Guide have not been published for the nRF9151. diff --git a/pacs/nrf51-pac/src/lib.rs b/pacs/nrf51-pac/src/lib.rs index ff61ca7c..d578c759 100644 --- a/pacs/nrf51-pac/src/lib.rs +++ b/pacs/nrf51-pac/src/lib.rs @@ -1,6 +1,5 @@ #![doc = "Peripheral access API for NRF51 microcontrollers (generated using svd2rust v0.25.1 ( ))\n\nYou can find an overview of the generated API [here].\n\nAPI features to be included in the [next] svd2rust release can be generated by cloning the svd2rust [repository], checking out the above commit, and running `cargo doc --open`.\n\n[here]: https://docs.rs/svd2rust/0.25.1/svd2rust/#peripheral-api\n[next]: https://github.com/rust-embedded/svd2rust/blob/master/CHANGELOG.md#unreleased\n[repository]: https://github.com/rust-embedded/svd2rust"] -#![deny(const_err)] #![deny(dead_code)] #![deny(improper_ctypes)] #![deny(missing_docs)] @@ -9,7 +8,6 @@ svd2rust release can be generated by cloning the svd2rust [repository], checking #![deny(overflowing_literals)] #![deny(path_statements)] #![deny(patterns_in_fns_without_body)] -#![deny(private_in_public)] #![deny(unconditional_recursion)] #![deny(unused_allocation)] #![deny(unused_comparisons)] diff --git a/pacs/nrf52805-pac/src/lib.rs b/pacs/nrf52805-pac/src/lib.rs index d3fb2028..c3ea7cf9 100644 --- a/pacs/nrf52805-pac/src/lib.rs +++ b/pacs/nrf52805-pac/src/lib.rs @@ -1,6 +1,5 @@ #![doc = "Peripheral access API for NRF52805 microcontrollers (generated using svd2rust v0.25.1 ( ))\n\nYou can find an overview of the generated API [here].\n\nAPI features to be included in the [next] svd2rust release can be generated by cloning the svd2rust [repository], checking out the above commit, and running `cargo doc --open`.\n\n[here]: https://docs.rs/svd2rust/0.25.1/svd2rust/#peripheral-api\n[next]: https://github.com/rust-embedded/svd2rust/blob/master/CHANGELOG.md#unreleased\n[repository]: https://github.com/rust-embedded/svd2rust"] -#![deny(const_err)] #![deny(dead_code)] #![deny(improper_ctypes)] #![deny(missing_docs)] @@ -9,7 +8,6 @@ svd2rust release can be generated by cloning the svd2rust [repository], checking #![deny(overflowing_literals)] #![deny(path_statements)] #![deny(patterns_in_fns_without_body)] -#![deny(private_in_public)] #![deny(unconditional_recursion)] #![deny(unused_allocation)] #![deny(unused_comparisons)] diff --git a/pacs/nrf52810-pac/src/lib.rs b/pacs/nrf52810-pac/src/lib.rs index 3f24e8b7..344c8b05 100644 --- a/pacs/nrf52810-pac/src/lib.rs +++ b/pacs/nrf52810-pac/src/lib.rs @@ -1,6 +1,5 @@ #![doc = "Peripheral access API for NRF52810 microcontrollers (generated using svd2rust v0.25.1 ( ))\n\nYou can find an overview of the generated API [here].\n\nAPI features to be included in the [next] svd2rust release can be generated by cloning the svd2rust [repository], checking out the above commit, and running `cargo doc --open`.\n\n[here]: https://docs.rs/svd2rust/0.25.1/svd2rust/#peripheral-api\n[next]: https://github.com/rust-embedded/svd2rust/blob/master/CHANGELOG.md#unreleased\n[repository]: https://github.com/rust-embedded/svd2rust"] -#![deny(const_err)] #![deny(dead_code)] #![deny(improper_ctypes)] #![deny(missing_docs)] @@ -9,7 +8,6 @@ svd2rust release can be generated by cloning the svd2rust [repository], checking #![deny(overflowing_literals)] #![deny(path_statements)] #![deny(patterns_in_fns_without_body)] -#![deny(private_in_public)] #![deny(unconditional_recursion)] #![deny(unused_allocation)] #![deny(unused_comparisons)] diff --git a/pacs/nrf52811-pac/src/lib.rs b/pacs/nrf52811-pac/src/lib.rs index 7c2530fb..0fa6f06a 100644 --- a/pacs/nrf52811-pac/src/lib.rs +++ b/pacs/nrf52811-pac/src/lib.rs @@ -1,6 +1,5 @@ #![doc = "Peripheral access API for NRF52811 microcontrollers (generated using svd2rust v0.25.1 ( ))\n\nYou can find an overview of the generated API [here].\n\nAPI features to be included in the [next] svd2rust release can be generated by cloning the svd2rust [repository], checking out the above commit, and running `cargo doc --open`.\n\n[here]: https://docs.rs/svd2rust/0.25.1/svd2rust/#peripheral-api\n[next]: https://github.com/rust-embedded/svd2rust/blob/master/CHANGELOG.md#unreleased\n[repository]: https://github.com/rust-embedded/svd2rust"] -#![deny(const_err)] #![deny(dead_code)] #![deny(improper_ctypes)] #![deny(missing_docs)] @@ -9,7 +8,6 @@ svd2rust release can be generated by cloning the svd2rust [repository], checking #![deny(overflowing_literals)] #![deny(path_statements)] #![deny(patterns_in_fns_without_body)] -#![deny(private_in_public)] #![deny(unconditional_recursion)] #![deny(unused_allocation)] #![deny(unused_comparisons)] diff --git a/pacs/nrf52820-pac/src/lib.rs b/pacs/nrf52820-pac/src/lib.rs index 84549d0b..d96cec56 100644 --- a/pacs/nrf52820-pac/src/lib.rs +++ b/pacs/nrf52820-pac/src/lib.rs @@ -1,6 +1,5 @@ #![doc = "Peripheral access API for NRF52820 microcontrollers (generated using svd2rust v0.25.1 ( ))\n\nYou can find an overview of the generated API [here].\n\nAPI features to be included in the [next] svd2rust release can be generated by cloning the svd2rust [repository], checking out the above commit, and running `cargo doc --open`.\n\n[here]: https://docs.rs/svd2rust/0.25.1/svd2rust/#peripheral-api\n[next]: https://github.com/rust-embedded/svd2rust/blob/master/CHANGELOG.md#unreleased\n[repository]: https://github.com/rust-embedded/svd2rust"] -#![deny(const_err)] #![deny(dead_code)] #![deny(improper_ctypes)] #![deny(missing_docs)] @@ -9,7 +8,6 @@ svd2rust release can be generated by cloning the svd2rust [repository], checking #![deny(overflowing_literals)] #![deny(path_statements)] #![deny(patterns_in_fns_without_body)] -#![deny(private_in_public)] #![deny(unconditional_recursion)] #![deny(unused_allocation)] #![deny(unused_comparisons)] diff --git a/pacs/nrf52832-pac/src/lib.rs b/pacs/nrf52832-pac/src/lib.rs index e99d161e..fcb7d9c0 100644 --- a/pacs/nrf52832-pac/src/lib.rs +++ b/pacs/nrf52832-pac/src/lib.rs @@ -1,6 +1,5 @@ #![doc = "Peripheral access API for NRF52 microcontrollers (generated using svd2rust v0.25.1 ( ))\n\nYou can find an overview of the generated API [here].\n\nAPI features to be included in the [next] svd2rust release can be generated by cloning the svd2rust [repository], checking out the above commit, and running `cargo doc --open`.\n\n[here]: https://docs.rs/svd2rust/0.25.1/svd2rust/#peripheral-api\n[next]: https://github.com/rust-embedded/svd2rust/blob/master/CHANGELOG.md#unreleased\n[repository]: https://github.com/rust-embedded/svd2rust"] -#![deny(const_err)] #![deny(dead_code)] #![deny(improper_ctypes)] #![deny(missing_docs)] @@ -9,7 +8,6 @@ svd2rust release can be generated by cloning the svd2rust [repository], checking #![deny(overflowing_literals)] #![deny(path_statements)] #![deny(patterns_in_fns_without_body)] -#![deny(private_in_public)] #![deny(unconditional_recursion)] #![deny(unused_allocation)] #![deny(unused_comparisons)] diff --git a/pacs/nrf52833-pac/src/lib.rs b/pacs/nrf52833-pac/src/lib.rs index 30b4774f..f713c7d5 100644 --- a/pacs/nrf52833-pac/src/lib.rs +++ b/pacs/nrf52833-pac/src/lib.rs @@ -1,6 +1,5 @@ #![doc = "Peripheral access API for NRF52833 microcontrollers (generated using svd2rust v0.25.1 ( ))\n\nYou can find an overview of the generated API [here].\n\nAPI features to be included in the [next] svd2rust release can be generated by cloning the svd2rust [repository], checking out the above commit, and running `cargo doc --open`.\n\n[here]: https://docs.rs/svd2rust/0.25.1/svd2rust/#peripheral-api\n[next]: https://github.com/rust-embedded/svd2rust/blob/master/CHANGELOG.md#unreleased\n[repository]: https://github.com/rust-embedded/svd2rust"] -#![deny(const_err)] #![deny(dead_code)] #![deny(improper_ctypes)] #![deny(missing_docs)] @@ -9,7 +8,6 @@ svd2rust release can be generated by cloning the svd2rust [repository], checking #![deny(overflowing_literals)] #![deny(path_statements)] #![deny(patterns_in_fns_without_body)] -#![deny(private_in_public)] #![deny(unconditional_recursion)] #![deny(unused_allocation)] #![deny(unused_comparisons)] diff --git a/pacs/nrf52840-pac/src/lib.rs b/pacs/nrf52840-pac/src/lib.rs index 9b6d348d..48c7f842 100644 --- a/pacs/nrf52840-pac/src/lib.rs +++ b/pacs/nrf52840-pac/src/lib.rs @@ -1,6 +1,5 @@ #![doc = "Peripheral access API for NRF52840 microcontrollers (generated using svd2rust v0.25.1 ( ))\n\nYou can find an overview of the generated API [here].\n\nAPI features to be included in the [next] svd2rust release can be generated by cloning the svd2rust [repository], checking out the above commit, and running `cargo doc --open`.\n\n[here]: https://docs.rs/svd2rust/0.25.1/svd2rust/#peripheral-api\n[next]: https://github.com/rust-embedded/svd2rust/blob/master/CHANGELOG.md#unreleased\n[repository]: https://github.com/rust-embedded/svd2rust"] -#![deny(const_err)] #![deny(dead_code)] #![deny(improper_ctypes)] #![deny(missing_docs)] @@ -9,7 +8,6 @@ svd2rust release can be generated by cloning the svd2rust [repository], checking #![deny(overflowing_literals)] #![deny(path_statements)] #![deny(patterns_in_fns_without_body)] -#![deny(private_in_public)] #![deny(unconditional_recursion)] #![deny(unused_allocation)] #![deny(unused_comparisons)] diff --git a/pacs/nrf5340-app-pac/src/lib.rs b/pacs/nrf5340-app-pac/src/lib.rs index 599fe96f..873fad13 100644 --- a/pacs/nrf5340-app-pac/src/lib.rs +++ b/pacs/nrf5340-app-pac/src/lib.rs @@ -1,6 +1,5 @@ #![doc = "Peripheral access API for NRF5340_APPLICATION microcontrollers (generated using svd2rust v0.25.1 ( ))\n\nYou can find an overview of the generated API [here].\n\nAPI features to be included in the [next] svd2rust release can be generated by cloning the svd2rust [repository], checking out the above commit, and running `cargo doc --open`.\n\n[here]: https://docs.rs/svd2rust/0.25.1/svd2rust/#peripheral-api\n[next]: https://github.com/rust-embedded/svd2rust/blob/master/CHANGELOG.md#unreleased\n[repository]: https://github.com/rust-embedded/svd2rust"] -#![deny(const_err)] #![deny(dead_code)] #![deny(improper_ctypes)] #![deny(missing_docs)] @@ -9,7 +8,6 @@ svd2rust release can be generated by cloning the svd2rust [repository], checking #![deny(overflowing_literals)] #![deny(path_statements)] #![deny(patterns_in_fns_without_body)] -#![deny(private_in_public)] #![deny(unconditional_recursion)] #![deny(unused_allocation)] #![deny(unused_comparisons)] diff --git a/pacs/nrf5340-net-pac/src/lib.rs b/pacs/nrf5340-net-pac/src/lib.rs index 7d02f90b..47ef8229 100644 --- a/pacs/nrf5340-net-pac/src/lib.rs +++ b/pacs/nrf5340-net-pac/src/lib.rs @@ -1,6 +1,5 @@ #![doc = "Peripheral access API for NRF5340_NETWORK microcontrollers (generated using svd2rust v0.25.1 ( ))\n\nYou can find an overview of the generated API [here].\n\nAPI features to be included in the [next] svd2rust release can be generated by cloning the svd2rust [repository], checking out the above commit, and running `cargo doc --open`.\n\n[here]: https://docs.rs/svd2rust/0.25.1/svd2rust/#peripheral-api\n[next]: https://github.com/rust-embedded/svd2rust/blob/master/CHANGELOG.md#unreleased\n[repository]: https://github.com/rust-embedded/svd2rust"] -#![deny(const_err)] #![deny(dead_code)] #![deny(improper_ctypes)] #![deny(missing_docs)] @@ -9,7 +8,6 @@ svd2rust release can be generated by cloning the svd2rust [repository], checking #![deny(overflowing_literals)] #![deny(path_statements)] #![deny(patterns_in_fns_without_body)] -#![deny(private_in_public)] #![deny(unconditional_recursion)] #![deny(unused_allocation)] #![deny(unused_comparisons)] diff --git a/pacs/nrf9120-pac/Cargo.toml b/pacs/nrf9120-pac/Cargo.toml new file mode 100644 index 00000000..062a9a83 --- /dev/null +++ b/pacs/nrf9120-pac/Cargo.toml @@ -0,0 +1,21 @@ +[package] +name = "nrf9120-pac" +description = "Peripheral Access Crate for Nordic's nrf9120 microcontroller" +documentation = "https://docs.rs/nrf9120-pac" +version.workspace = true +edition.workspace = true +keywords.workspace = true +license.workspace = true +repository.workspace = true +readme.workspace = true + +[dependencies] +cortex-m.workspace = true +vcell.workspace = true + +[dependencies.cortex-m-rt] +optional = true +workspace = true + +[features] +rt = ["cortex-m-rt/device"] diff --git a/pacs/nrf9120-pac/build.rs b/pacs/nrf9120-pac/build.rs new file mode 100644 index 00000000..597923f5 --- /dev/null +++ b/pacs/nrf9120-pac/build.rs @@ -0,0 +1,16 @@ +use std::env; +use std::fs::File; +use std::io::Write; +use std::path::PathBuf; +fn main() { + if env::var_os("CARGO_FEATURE_RT").is_some() { + let out = &PathBuf::from(env::var_os("OUT_DIR").unwrap()); + File::create(out.join("device.x")) + .unwrap() + .write_all(include_bytes!("device.x")) + .unwrap(); + println!("cargo:rustc-link-search={}", out.display()); + println!("cargo:rerun-if-changed=device.x"); + } + println!("cargo:rerun-if-changed=build.rs"); +} diff --git a/pacs/nrf9120-pac/device.x b/pacs/nrf9120-pac/device.x new file mode 100644 index 00000000..da832759 --- /dev/null +++ b/pacs/nrf9120-pac/device.x @@ -0,0 +1,32 @@ +PROVIDE(SPU = DefaultHandler); +PROVIDE(CLOCK_POWER = DefaultHandler); +PROVIDE(SPIM0_SPIS0_TWIM0_TWIS0_UARTE0 = DefaultHandler); +PROVIDE(SPIM1_SPIS1_TWIM1_TWIS1_UARTE1 = DefaultHandler); +PROVIDE(SPIM2_SPIS2_TWIM2_TWIS2_UARTE2 = DefaultHandler); +PROVIDE(SPIM3_SPIS3_TWIM3_TWIS3_UARTE3 = DefaultHandler); +PROVIDE(GPIOTE0 = DefaultHandler); +PROVIDE(SAADC = DefaultHandler); +PROVIDE(TIMER0 = DefaultHandler); +PROVIDE(TIMER1 = DefaultHandler); +PROVIDE(TIMER2 = DefaultHandler); +PROVIDE(RTC0 = DefaultHandler); +PROVIDE(RTC1 = DefaultHandler); +PROVIDE(WDT = DefaultHandler); +PROVIDE(EGU0 = DefaultHandler); +PROVIDE(EGU1 = DefaultHandler); +PROVIDE(EGU2 = DefaultHandler); +PROVIDE(EGU3 = DefaultHandler); +PROVIDE(EGU4 = DefaultHandler); +PROVIDE(EGU5 = DefaultHandler); +PROVIDE(PWM0 = DefaultHandler); +PROVIDE(PWM1 = DefaultHandler); +PROVIDE(PWM2 = DefaultHandler); +PROVIDE(PWM3 = DefaultHandler); +PROVIDE(PDM = DefaultHandler); +PROVIDE(I2S = DefaultHandler); +PROVIDE(IPC = DefaultHandler); +PROVIDE(FPU = DefaultHandler); +PROVIDE(GPIOTE1 = DefaultHandler); +PROVIDE(KMU = DefaultHandler); +PROVIDE(CRYPTOCELL = DefaultHandler); + diff --git a/pacs/nrf9120-pac/src/approtect_ns.rs b/pacs/nrf9120-pac/src/approtect_ns.rs new file mode 100644 index 00000000..199b28a2 --- /dev/null +++ b/pacs/nrf9120-pac/src/approtect_ns.rs @@ -0,0 +1,20 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + _reserved0: [u8; 0x0e00], + #[doc = "0xe00 - Unspecified"] + pub secureapprotect: SECUREAPPROTECT, + _reserved1: [u8; 0x0c], + #[doc = "0xe10 - Unspecified"] + pub approtect: APPROTECT, +} +#[doc = "Unspecified"] +pub use secureapprotect::SECUREAPPROTECT; +#[doc = r"Cluster"] +#[doc = "Unspecified"] +pub mod secureapprotect; +#[doc = "Unspecified"] +pub use approtect::APPROTECT; +#[doc = r"Cluster"] +#[doc = "Unspecified"] +pub mod approtect; diff --git a/pacs/nrf9120-pac/src/approtect_ns/approtect.rs b/pacs/nrf9120-pac/src/approtect_ns/approtect.rs new file mode 100644 index 00000000..559ce8b1 --- /dev/null +++ b/pacs/nrf9120-pac/src/approtect_ns/approtect.rs @@ -0,0 +1,25 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct APPROTECT { + _reserved_0_disable: [u8; 0x04], +} +impl APPROTECT { + #[doc = "0x00 - Software force APPROTECT mechanism"] + #[inline(always)] + pub fn forceprotect(&self) -> &FORCEPROTECT { + unsafe { &*(((self as *const Self) as *const u8).add(0usize) as *const FORCEPROTECT) } + } + #[doc = "0x00 - Software disable APPROTECT mechanism"] + #[inline(always)] + pub fn disable(&self) -> &DISABLE { + unsafe { &*(((self as *const Self) as *const u8).add(0usize) as *const DISABLE) } + } +} +#[doc = "DISABLE (rw) register accessor: an alias for `Reg`"] +pub type DISABLE = crate::Reg; +#[doc = "Software disable APPROTECT mechanism"] +pub mod disable; +#[doc = "FORCEPROTECT (rw) register accessor: an alias for `Reg`"] +pub type FORCEPROTECT = crate::Reg; +#[doc = "Software force APPROTECT mechanism"] +pub mod forceprotect; diff --git a/pacs/nrf9120-pac/src/approtect_ns/approtect/disable.rs b/pacs/nrf9120-pac/src/approtect_ns/approtect/disable.rs new file mode 100644 index 00000000..cafe3892 --- /dev/null +++ b/pacs/nrf9120-pac/src/approtect_ns/approtect/disable.rs @@ -0,0 +1,116 @@ +#[doc = "Register `DISABLE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DISABLE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DISABLE` reader - Software disable APPROTECT mechanism"] +pub type DISABLE_R = crate::FieldReader; +#[doc = "Software disable APPROTECT mechanism\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum DISABLE_A { + #[doc = "90: Software disable APPROTECT mechanism"] + SW_UNPROTECTED = 90, +} +impl From for u8 { + #[inline(always)] + fn from(variant: DISABLE_A) -> Self { + variant as _ + } +} +impl DISABLE_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 90 => Some(DISABLE_A::SW_UNPROTECTED), + _ => None, + } + } + #[doc = "Checks if the value of the field is `SW_UNPROTECTED`"] + #[inline(always)] + pub fn is_sw_unprotected(&self) -> bool { + *self == DISABLE_A::SW_UNPROTECTED + } +} +#[doc = "Field `DISABLE` writer - Software disable APPROTECT mechanism"] +pub type DISABLE_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, DISABLE_SPEC, u8, DISABLE_A, 8, O>; +impl<'a, const O: u8> DISABLE_W<'a, O> { + #[doc = "Software disable APPROTECT mechanism"] + #[inline(always)] + pub fn sw_unprotected(self) -> &'a mut W { + self.variant(DISABLE_A::SW_UNPROTECTED) + } +} +impl R { + #[doc = "Bits 0:7 - Software disable APPROTECT mechanism"] + #[inline(always)] + pub fn disable(&self) -> DISABLE_R { + DISABLE_R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Software disable APPROTECT mechanism"] + #[inline(always)] + pub fn disable(&mut self) -> DISABLE_W<0> { + DISABLE_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Software disable APPROTECT mechanism\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [disable](index.html) module"] +pub struct DISABLE_SPEC; +impl crate::RegisterSpec for DISABLE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [disable::R](R) reader structure"] +impl crate::Readable for DISABLE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [disable::W](W) writer structure"] +impl crate::Writable for DISABLE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DISABLE to value 0x01"] +impl crate::Resettable for DISABLE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x01 + } +} diff --git a/pacs/nrf9120-pac/src/approtect_ns/approtect/forceprotect.rs b/pacs/nrf9120-pac/src/approtect_ns/approtect/forceprotect.rs new file mode 100644 index 00000000..989343d4 --- /dev/null +++ b/pacs/nrf9120-pac/src/approtect_ns/approtect/forceprotect.rs @@ -0,0 +1,115 @@ +#[doc = "Register `FORCEPROTECT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `FORCEPROTECT` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `FORCEPROTECT` reader - Write 0x1 to force enable APPROTECT mechanism"] +pub type FORCEPROTECT_R = crate::BitReader; +#[doc = "Write 0x1 to force enable APPROTECT mechanism\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum FORCEPROTECT_A { + #[doc = "1: Software force enable APPROTECT mechanism"] + FORCE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: FORCEPROTECT_A) -> Self { + variant as u8 != 0 + } +} +impl FORCEPROTECT_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + true => Some(FORCEPROTECT_A::FORCE), + _ => None, + } + } + #[doc = "Checks if the value of the field is `FORCE`"] + #[inline(always)] + pub fn is_force(&self) -> bool { + *self == FORCEPROTECT_A::FORCE + } +} +#[doc = "Field `FORCEPROTECT` writer - Write 0x1 to force enable APPROTECT mechanism"] +pub type FORCEPROTECT_W<'a, const O: u8> = + crate::BitWriter1S<'a, u32, FORCEPROTECT_SPEC, FORCEPROTECT_A, O>; +impl<'a, const O: u8> FORCEPROTECT_W<'a, O> { + #[doc = "Software force enable APPROTECT mechanism"] + #[inline(always)] + pub fn force(self) -> &'a mut W { + self.variant(FORCEPROTECT_A::FORCE) + } +} +impl R { + #[doc = "Bit 9 - Write 0x1 to force enable APPROTECT mechanism"] + #[inline(always)] + pub fn forceprotect(&self) -> FORCEPROTECT_R { + FORCEPROTECT_R::new(((self.bits >> 9) & 1) != 0) + } +} +impl W { + #[doc = "Bit 9 - Write 0x1 to force enable APPROTECT mechanism"] + #[inline(always)] + pub fn forceprotect(&mut self) -> FORCEPROTECT_W<9> { + FORCEPROTECT_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Software force APPROTECT mechanism\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [forceprotect](index.html) module"] +pub struct FORCEPROTECT_SPEC; +impl crate::RegisterSpec for FORCEPROTECT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [forceprotect::R](R) reader structure"] +impl crate::Readable for FORCEPROTECT_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [forceprotect::W](W) writer structure"] +impl crate::Writable for FORCEPROTECT_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets FORCEPROTECT to value 0x01"] +impl crate::Resettable for FORCEPROTECT_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x01 + } +} diff --git a/pacs/nrf9120-pac/src/approtect_ns/secureapprotect.rs b/pacs/nrf9120-pac/src/approtect_ns/secureapprotect.rs new file mode 100644 index 00000000..12d356a7 --- /dev/null +++ b/pacs/nrf9120-pac/src/approtect_ns/secureapprotect.rs @@ -0,0 +1,25 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct SECUREAPPROTECT { + _reserved_0_disable: [u8; 0x04], +} +impl SECUREAPPROTECT { + #[doc = "0x00 - Software force SECUREAPPROTECT mechanism"] + #[inline(always)] + pub fn forceprotect(&self) -> &FORCEPROTECT { + unsafe { &*(((self as *const Self) as *const u8).add(0usize) as *const FORCEPROTECT) } + } + #[doc = "0x00 - Software disable SECUREAPPROTECT mechanism"] + #[inline(always)] + pub fn disable(&self) -> &DISABLE { + unsafe { &*(((self as *const Self) as *const u8).add(0usize) as *const DISABLE) } + } +} +#[doc = "DISABLE (rw) register accessor: an alias for `Reg`"] +pub type DISABLE = crate::Reg; +#[doc = "Software disable SECUREAPPROTECT mechanism"] +pub mod disable; +#[doc = "FORCEPROTECT (rw) register accessor: an alias for `Reg`"] +pub type FORCEPROTECT = crate::Reg; +#[doc = "Software force SECUREAPPROTECT mechanism"] +pub mod forceprotect; diff --git a/pacs/nrf9120-pac/src/approtect_ns/secureapprotect/disable.rs b/pacs/nrf9120-pac/src/approtect_ns/secureapprotect/disable.rs new file mode 100644 index 00000000..88d8144b --- /dev/null +++ b/pacs/nrf9120-pac/src/approtect_ns/secureapprotect/disable.rs @@ -0,0 +1,116 @@ +#[doc = "Register `DISABLE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DISABLE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DISABLE` reader - Software disable SECUREAPPROTECT mechanism"] +pub type DISABLE_R = crate::FieldReader; +#[doc = "Software disable SECUREAPPROTECT mechanism\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum DISABLE_A { + #[doc = "90: Software disable SECUREAPPROTECT mechanism"] + SW_UNPROTECTED = 90, +} +impl From for u8 { + #[inline(always)] + fn from(variant: DISABLE_A) -> Self { + variant as _ + } +} +impl DISABLE_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 90 => Some(DISABLE_A::SW_UNPROTECTED), + _ => None, + } + } + #[doc = "Checks if the value of the field is `SW_UNPROTECTED`"] + #[inline(always)] + pub fn is_sw_unprotected(&self) -> bool { + *self == DISABLE_A::SW_UNPROTECTED + } +} +#[doc = "Field `DISABLE` writer - Software disable SECUREAPPROTECT mechanism"] +pub type DISABLE_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, DISABLE_SPEC, u8, DISABLE_A, 8, O>; +impl<'a, const O: u8> DISABLE_W<'a, O> { + #[doc = "Software disable SECUREAPPROTECT mechanism"] + #[inline(always)] + pub fn sw_unprotected(self) -> &'a mut W { + self.variant(DISABLE_A::SW_UNPROTECTED) + } +} +impl R { + #[doc = "Bits 0:7 - Software disable SECUREAPPROTECT mechanism"] + #[inline(always)] + pub fn disable(&self) -> DISABLE_R { + DISABLE_R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Software disable SECUREAPPROTECT mechanism"] + #[inline(always)] + pub fn disable(&mut self) -> DISABLE_W<0> { + DISABLE_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Software disable SECUREAPPROTECT mechanism\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [disable](index.html) module"] +pub struct DISABLE_SPEC; +impl crate::RegisterSpec for DISABLE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [disable::R](R) reader structure"] +impl crate::Readable for DISABLE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [disable::W](W) writer structure"] +impl crate::Writable for DISABLE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DISABLE to value 0x01"] +impl crate::Resettable for DISABLE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x01 + } +} diff --git a/pacs/nrf9120-pac/src/approtect_ns/secureapprotect/forceprotect.rs b/pacs/nrf9120-pac/src/approtect_ns/secureapprotect/forceprotect.rs new file mode 100644 index 00000000..f8ed1dca --- /dev/null +++ b/pacs/nrf9120-pac/src/approtect_ns/secureapprotect/forceprotect.rs @@ -0,0 +1,115 @@ +#[doc = "Register `FORCEPROTECT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `FORCEPROTECT` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `FORCEPROTECT` reader - Write 0x1 to force enable SECUREAPPROTECT mechanism"] +pub type FORCEPROTECT_R = crate::BitReader; +#[doc = "Write 0x1 to force enable SECUREAPPROTECT mechanism\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum FORCEPROTECT_A { + #[doc = "1: Software force enable SECUREAPPROTECT mechanism"] + FORCE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: FORCEPROTECT_A) -> Self { + variant as u8 != 0 + } +} +impl FORCEPROTECT_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + true => Some(FORCEPROTECT_A::FORCE), + _ => None, + } + } + #[doc = "Checks if the value of the field is `FORCE`"] + #[inline(always)] + pub fn is_force(&self) -> bool { + *self == FORCEPROTECT_A::FORCE + } +} +#[doc = "Field `FORCEPROTECT` writer - Write 0x1 to force enable SECUREAPPROTECT mechanism"] +pub type FORCEPROTECT_W<'a, const O: u8> = + crate::BitWriter1S<'a, u32, FORCEPROTECT_SPEC, FORCEPROTECT_A, O>; +impl<'a, const O: u8> FORCEPROTECT_W<'a, O> { + #[doc = "Software force enable SECUREAPPROTECT mechanism"] + #[inline(always)] + pub fn force(self) -> &'a mut W { + self.variant(FORCEPROTECT_A::FORCE) + } +} +impl R { + #[doc = "Bit 9 - Write 0x1 to force enable SECUREAPPROTECT mechanism"] + #[inline(always)] + pub fn forceprotect(&self) -> FORCEPROTECT_R { + FORCEPROTECT_R::new(((self.bits >> 9) & 1) != 0) + } +} +impl W { + #[doc = "Bit 9 - Write 0x1 to force enable SECUREAPPROTECT mechanism"] + #[inline(always)] + pub fn forceprotect(&mut self) -> FORCEPROTECT_W<9> { + FORCEPROTECT_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Software force SECUREAPPROTECT mechanism\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [forceprotect](index.html) module"] +pub struct FORCEPROTECT_SPEC; +impl crate::RegisterSpec for FORCEPROTECT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [forceprotect::R](R) reader structure"] +impl crate::Readable for FORCEPROTECT_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [forceprotect::W](W) writer structure"] +impl crate::Writable for FORCEPROTECT_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets FORCEPROTECT to value 0x01"] +impl crate::Resettable for FORCEPROTECT_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x01 + } +} diff --git a/pacs/nrf9120-pac/src/cc_host_rgf_s.rs b/pacs/nrf9120-pac/src/cc_host_rgf_s.rs new file mode 100644 index 00000000..cb66d517 --- /dev/null +++ b/pacs/nrf9120-pac/src/cc_host_rgf_s.rs @@ -0,0 +1,48 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + _reserved0: [u8; 0x1a38], + #[doc = "0x1a38 - AES hardware key select"] + pub host_cryptokey_sel: HOST_CRYPTOKEY_SEL, + _reserved1: [u8; 0x10], + #[doc = "0x1a4c - This write-once register is the K_PRTL lock register. When this register is set, K_PRTL cannot be used and a zeroed key will be used instead. The value of this register is saved in the CRYPTOCELL AO power domain."] + pub host_iot_kprtl_lock: HOST_IOT_KPRTL_LOCK, + #[doc = "0x1a50 - This register holds bits 31:0 of K_DR. The value of this register is saved in the CRYPTOCELL AO power domain. Reading from this address returns the K_DR valid status indicating if K_DR is successfully retained."] + pub host_iot_kdr0: HOST_IOT_KDR0, + #[doc = "0x1a54 - This register holds bits 63:32 of K_DR. The value of this register is saved in the CRYPTOCELL AO power domain."] + pub host_iot_kdr1: HOST_IOT_KDR1, + #[doc = "0x1a58 - This register holds bits 95:64 of K_DR. The value of this register is saved in the CRYPTOCELL AO power domain."] + pub host_iot_kdr2: HOST_IOT_KDR2, + #[doc = "0x1a5c - This register holds bits 127:96 of K_DR. The value of this register is saved in the CRYPTOCELL AO power domain."] + pub host_iot_kdr3: HOST_IOT_KDR3, + #[doc = "0x1a60 - Controls lifecycle state (LCS) for CRYPTOCELL subsystem"] + pub host_iot_lcs: HOST_IOT_LCS, +} +#[doc = "HOST_CRYPTOKEY_SEL (rw) register accessor: an alias for `Reg`"] +pub type HOST_CRYPTOKEY_SEL = crate::Reg; +#[doc = "AES hardware key select"] +pub mod host_cryptokey_sel; +#[doc = "HOST_IOT_KPRTL_LOCK (rw) register accessor: an alias for `Reg`"] +pub type HOST_IOT_KPRTL_LOCK = crate::Reg; +#[doc = "This write-once register is the K_PRTL lock register. When this register is set, K_PRTL cannot be used and a zeroed key will be used instead. The value of this register is saved in the CRYPTOCELL AO power domain."] +pub mod host_iot_kprtl_lock; +#[doc = "HOST_IOT_KDR0 (rw) register accessor: an alias for `Reg`"] +pub type HOST_IOT_KDR0 = crate::Reg; +#[doc = "This register holds bits 31:0 of K_DR. The value of this register is saved in the CRYPTOCELL AO power domain. Reading from this address returns the K_DR valid status indicating if K_DR is successfully retained."] +pub mod host_iot_kdr0; +#[doc = "HOST_IOT_KDR1 (w) register accessor: an alias for `Reg`"] +pub type HOST_IOT_KDR1 = crate::Reg; +#[doc = "This register holds bits 63:32 of K_DR. The value of this register is saved in the CRYPTOCELL AO power domain."] +pub mod host_iot_kdr1; +#[doc = "HOST_IOT_KDR2 (w) register accessor: an alias for `Reg`"] +pub type HOST_IOT_KDR2 = crate::Reg; +#[doc = "This register holds bits 95:64 of K_DR. The value of this register is saved in the CRYPTOCELL AO power domain."] +pub mod host_iot_kdr2; +#[doc = "HOST_IOT_KDR3 (w) register accessor: an alias for `Reg`"] +pub type HOST_IOT_KDR3 = crate::Reg; +#[doc = "This register holds bits 127:96 of K_DR. The value of this register is saved in the CRYPTOCELL AO power domain."] +pub mod host_iot_kdr3; +#[doc = "HOST_IOT_LCS (rw) register accessor: an alias for `Reg`"] +pub type HOST_IOT_LCS = crate::Reg; +#[doc = "Controls lifecycle state (LCS) for CRYPTOCELL subsystem"] +pub mod host_iot_lcs; diff --git a/pacs/nrf9120-pac/src/cc_host_rgf_s/host_cryptokey_sel.rs b/pacs/nrf9120-pac/src/cc_host_rgf_s/host_cryptokey_sel.rs new file mode 100644 index 00000000..9ea783e9 --- /dev/null +++ b/pacs/nrf9120-pac/src/cc_host_rgf_s/host_cryptokey_sel.rs @@ -0,0 +1,142 @@ +#[doc = "Register `HOST_CRYPTOKEY_SEL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `HOST_CRYPTOKEY_SEL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `HOST_CRYPTOKEY_SEL` reader - Select the source of the HW key that is used by the AES engine"] +pub type HOST_CRYPTOKEY_SEL_R = crate::FieldReader; +#[doc = "Select the source of the HW key that is used by the AES engine\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum HOST_CRYPTOKEY_SEL_A { + #[doc = "0: Use device root key K_DR from CRYPTOCELL AO power domain"] + K_DR = 0, + #[doc = "1: Use hard-coded RTL key K_PRTL"] + K_PRTL = 1, + #[doc = "2: Use provided session key"] + SESSION = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: HOST_CRYPTOKEY_SEL_A) -> Self { + variant as _ + } +} +impl HOST_CRYPTOKEY_SEL_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(HOST_CRYPTOKEY_SEL_A::K_DR), + 1 => Some(HOST_CRYPTOKEY_SEL_A::K_PRTL), + 2 => Some(HOST_CRYPTOKEY_SEL_A::SESSION), + _ => None, + } + } + #[doc = "Checks if the value of the field is `K_DR`"] + #[inline(always)] + pub fn is_k_dr(&self) -> bool { + *self == HOST_CRYPTOKEY_SEL_A::K_DR + } + #[doc = "Checks if the value of the field is `K_PRTL`"] + #[inline(always)] + pub fn is_k_prtl(&self) -> bool { + *self == HOST_CRYPTOKEY_SEL_A::K_PRTL + } + #[doc = "Checks if the value of the field is `SESSION`"] + #[inline(always)] + pub fn is_session(&self) -> bool { + *self == HOST_CRYPTOKEY_SEL_A::SESSION + } +} +#[doc = "Field `HOST_CRYPTOKEY_SEL` writer - Select the source of the HW key that is used by the AES engine"] +pub type HOST_CRYPTOKEY_SEL_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, HOST_CRYPTOKEY_SEL_SPEC, u8, HOST_CRYPTOKEY_SEL_A, 2, O>; +impl<'a, const O: u8> HOST_CRYPTOKEY_SEL_W<'a, O> { + #[doc = "Use device root key K_DR from CRYPTOCELL AO power domain"] + #[inline(always)] + pub fn k_dr(self) -> &'a mut W { + self.variant(HOST_CRYPTOKEY_SEL_A::K_DR) + } + #[doc = "Use hard-coded RTL key K_PRTL"] + #[inline(always)] + pub fn k_prtl(self) -> &'a mut W { + self.variant(HOST_CRYPTOKEY_SEL_A::K_PRTL) + } + #[doc = "Use provided session key"] + #[inline(always)] + pub fn session(self) -> &'a mut W { + self.variant(HOST_CRYPTOKEY_SEL_A::SESSION) + } +} +impl R { + #[doc = "Bits 0:1 - Select the source of the HW key that is used by the AES engine"] + #[inline(always)] + pub fn host_cryptokey_sel(&self) -> HOST_CRYPTOKEY_SEL_R { + HOST_CRYPTOKEY_SEL_R::new((self.bits & 3) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Select the source of the HW key that is used by the AES engine"] + #[inline(always)] + pub fn host_cryptokey_sel(&mut self) -> HOST_CRYPTOKEY_SEL_W<0> { + HOST_CRYPTOKEY_SEL_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "AES hardware key select\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [host_cryptokey_sel](index.html) module"] +pub struct HOST_CRYPTOKEY_SEL_SPEC; +impl crate::RegisterSpec for HOST_CRYPTOKEY_SEL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [host_cryptokey_sel::R](R) reader structure"] +impl crate::Readable for HOST_CRYPTOKEY_SEL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [host_cryptokey_sel::W](W) writer structure"] +impl crate::Writable for HOST_CRYPTOKEY_SEL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets HOST_CRYPTOKEY_SEL to value 0"] +impl crate::Resettable for HOST_CRYPTOKEY_SEL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/cc_host_rgf_s/host_iot_kdr0.rs b/pacs/nrf9120-pac/src/cc_host_rgf_s/host_iot_kdr0.rs new file mode 100644 index 00000000..0080dff7 --- /dev/null +++ b/pacs/nrf9120-pac/src/cc_host_rgf_s/host_iot_kdr0.rs @@ -0,0 +1,81 @@ +#[doc = "Register `HOST_IOT_KDR0` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `HOST_IOT_KDR0` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `HOST_IOT_KDR0` reader - Write: K_DR bits 31:0. Read: 0x00000000 when 128-bit K_DR key value is not yet retained in the CRYPTOCELL AO power domain. Read: 0x00000001 when 128-bit K_DR key value is successfully retained in the CRYPTOCELL AO power domain."] +pub type HOST_IOT_KDR0_R = crate::FieldReader; +#[doc = "Field `HOST_IOT_KDR0` writer - Write: K_DR bits 31:0. Read: 0x00000000 when 128-bit K_DR key value is not yet retained in the CRYPTOCELL AO power domain. Read: 0x00000001 when 128-bit K_DR key value is successfully retained in the CRYPTOCELL AO power domain."] +pub type HOST_IOT_KDR0_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, HOST_IOT_KDR0_SPEC, u32, u32, 32, O>; +impl R { + #[doc = "Bits 0:31 - Write: K_DR bits 31:0. Read: 0x00000000 when 128-bit K_DR key value is not yet retained in the CRYPTOCELL AO power domain. Read: 0x00000001 when 128-bit K_DR key value is successfully retained in the CRYPTOCELL AO power domain."] + #[inline(always)] + pub fn host_iot_kdr0(&self) -> HOST_IOT_KDR0_R { + HOST_IOT_KDR0_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Write: K_DR bits 31:0. Read: 0x00000000 when 128-bit K_DR key value is not yet retained in the CRYPTOCELL AO power domain. Read: 0x00000001 when 128-bit K_DR key value is successfully retained in the CRYPTOCELL AO power domain."] + #[inline(always)] + pub fn host_iot_kdr0(&mut self) -> HOST_IOT_KDR0_W<0> { + HOST_IOT_KDR0_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "This register holds bits 31:0 of K_DR. The value of this register is saved in the CRYPTOCELL AO power domain. Reading from this address returns the K_DR valid status indicating if K_DR is successfully retained.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [host_iot_kdr0](index.html) module"] +pub struct HOST_IOT_KDR0_SPEC; +impl crate::RegisterSpec for HOST_IOT_KDR0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [host_iot_kdr0::R](R) reader structure"] +impl crate::Readable for HOST_IOT_KDR0_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [host_iot_kdr0::W](W) writer structure"] +impl crate::Writable for HOST_IOT_KDR0_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets HOST_IOT_KDR0 to value 0"] +impl crate::Resettable for HOST_IOT_KDR0_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/cc_host_rgf_s/host_iot_kdr1.rs b/pacs/nrf9120-pac/src/cc_host_rgf_s/host_iot_kdr1.rs new file mode 100644 index 00000000..47c69644 --- /dev/null +++ b/pacs/nrf9120-pac/src/cc_host_rgf_s/host_iot_kdr1.rs @@ -0,0 +1,53 @@ +#[doc = "Register `HOST_IOT_KDR1` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `HOST_IOT_KDR1` writer - K_DR bits 63:32"] +pub type HOST_IOT_KDR1_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, HOST_IOT_KDR1_SPEC, u32, u32, 32, O>; +impl W { + #[doc = "Bits 0:31 - K_DR bits 63:32"] + #[inline(always)] + pub fn host_iot_kdr1(&mut self) -> HOST_IOT_KDR1_W<0> { + HOST_IOT_KDR1_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "This register holds bits 63:32 of K_DR. The value of this register is saved in the CRYPTOCELL AO power domain.\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [host_iot_kdr1](index.html) module"] +pub struct HOST_IOT_KDR1_SPEC; +impl crate::RegisterSpec for HOST_IOT_KDR1_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [host_iot_kdr1::W](W) writer structure"] +impl crate::Writable for HOST_IOT_KDR1_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets HOST_IOT_KDR1 to value 0"] +impl crate::Resettable for HOST_IOT_KDR1_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/cc_host_rgf_s/host_iot_kdr2.rs b/pacs/nrf9120-pac/src/cc_host_rgf_s/host_iot_kdr2.rs new file mode 100644 index 00000000..d46de80d --- /dev/null +++ b/pacs/nrf9120-pac/src/cc_host_rgf_s/host_iot_kdr2.rs @@ -0,0 +1,53 @@ +#[doc = "Register `HOST_IOT_KDR2` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `HOST_IOT_KDR2` writer - K_DR bits 95:64"] +pub type HOST_IOT_KDR2_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, HOST_IOT_KDR2_SPEC, u32, u32, 32, O>; +impl W { + #[doc = "Bits 0:31 - K_DR bits 95:64"] + #[inline(always)] + pub fn host_iot_kdr2(&mut self) -> HOST_IOT_KDR2_W<0> { + HOST_IOT_KDR2_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "This register holds bits 95:64 of K_DR. The value of this register is saved in the CRYPTOCELL AO power domain.\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [host_iot_kdr2](index.html) module"] +pub struct HOST_IOT_KDR2_SPEC; +impl crate::RegisterSpec for HOST_IOT_KDR2_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [host_iot_kdr2::W](W) writer structure"] +impl crate::Writable for HOST_IOT_KDR2_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets HOST_IOT_KDR2 to value 0"] +impl crate::Resettable for HOST_IOT_KDR2_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/cc_host_rgf_s/host_iot_kdr3.rs b/pacs/nrf9120-pac/src/cc_host_rgf_s/host_iot_kdr3.rs new file mode 100644 index 00000000..cf43d4fa --- /dev/null +++ b/pacs/nrf9120-pac/src/cc_host_rgf_s/host_iot_kdr3.rs @@ -0,0 +1,53 @@ +#[doc = "Register `HOST_IOT_KDR3` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `HOST_IOT_KDR3` writer - K_DR bits 127:96"] +pub type HOST_IOT_KDR3_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, HOST_IOT_KDR3_SPEC, u32, u32, 32, O>; +impl W { + #[doc = "Bits 0:31 - K_DR bits 127:96"] + #[inline(always)] + pub fn host_iot_kdr3(&mut self) -> HOST_IOT_KDR3_W<0> { + HOST_IOT_KDR3_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "This register holds bits 127:96 of K_DR. The value of this register is saved in the CRYPTOCELL AO power domain.\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [host_iot_kdr3](index.html) module"] +pub struct HOST_IOT_KDR3_SPEC; +impl crate::RegisterSpec for HOST_IOT_KDR3_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [host_iot_kdr3::W](W) writer structure"] +impl crate::Writable for HOST_IOT_KDR3_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets HOST_IOT_KDR3 to value 0"] +impl crate::Resettable for HOST_IOT_KDR3_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/cc_host_rgf_s/host_iot_kprtl_lock.rs b/pacs/nrf9120-pac/src/cc_host_rgf_s/host_iot_kprtl_lock.rs new file mode 100644 index 00000000..774802ea --- /dev/null +++ b/pacs/nrf9120-pac/src/cc_host_rgf_s/host_iot_kprtl_lock.rs @@ -0,0 +1,127 @@ +#[doc = "Register `HOST_IOT_KPRTL_LOCK` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `HOST_IOT_KPRTL_LOCK` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `HOST_IOT_KPRTL_LOCK` reader - This register is the K_PRTL lock register. When this register is set, K_PRTL cannot be used and a zeroed key will be used instead. The value of this register is saved in the CRYPTOCELL AO power domain."] +pub type HOST_IOT_KPRTL_LOCK_R = crate::BitReader; +#[doc = "This register is the K_PRTL lock register. When this register is set, K_PRTL cannot be used and a zeroed key will be used instead. The value of this register is saved in the CRYPTOCELL AO power domain.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum HOST_IOT_KPRTL_LOCK_A { + #[doc = "0: K_PRTL can be selected for use from register HOST_CRYPTOKEY_SEL"] + DISABLED = 0, + #[doc = "1: K_PRTL has been locked until next power-on reset (POR). If K_PRTL is selected anyway, a zeroed key will be used instead."] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: HOST_IOT_KPRTL_LOCK_A) -> Self { + variant as u8 != 0 + } +} +impl HOST_IOT_KPRTL_LOCK_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> HOST_IOT_KPRTL_LOCK_A { + match self.bits { + false => HOST_IOT_KPRTL_LOCK_A::DISABLED, + true => HOST_IOT_KPRTL_LOCK_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == HOST_IOT_KPRTL_LOCK_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == HOST_IOT_KPRTL_LOCK_A::ENABLED + } +} +#[doc = "Field `HOST_IOT_KPRTL_LOCK` writer - This register is the K_PRTL lock register. When this register is set, K_PRTL cannot be used and a zeroed key will be used instead. The value of this register is saved in the CRYPTOCELL AO power domain."] +pub type HOST_IOT_KPRTL_LOCK_W<'a, const O: u8> = + crate::BitWriter<'a, u32, HOST_IOT_KPRTL_LOCK_SPEC, HOST_IOT_KPRTL_LOCK_A, O>; +impl<'a, const O: u8> HOST_IOT_KPRTL_LOCK_W<'a, O> { + #[doc = "K_PRTL can be selected for use from register HOST_CRYPTOKEY_SEL"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(HOST_IOT_KPRTL_LOCK_A::DISABLED) + } + #[doc = "K_PRTL has been locked until next power-on reset (POR). If K_PRTL is selected anyway, a zeroed key will be used instead."] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(HOST_IOT_KPRTL_LOCK_A::ENABLED) + } +} +impl R { + #[doc = "Bit 0 - This register is the K_PRTL lock register. When this register is set, K_PRTL cannot be used and a zeroed key will be used instead. The value of this register is saved in the CRYPTOCELL AO power domain."] + #[inline(always)] + pub fn host_iot_kprtl_lock(&self) -> HOST_IOT_KPRTL_LOCK_R { + HOST_IOT_KPRTL_LOCK_R::new((self.bits & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - This register is the K_PRTL lock register. When this register is set, K_PRTL cannot be used and a zeroed key will be used instead. The value of this register is saved in the CRYPTOCELL AO power domain."] + #[inline(always)] + pub fn host_iot_kprtl_lock(&mut self) -> HOST_IOT_KPRTL_LOCK_W<0> { + HOST_IOT_KPRTL_LOCK_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "This write-once register is the K_PRTL lock register. When this register is set, K_PRTL cannot be used and a zeroed key will be used instead. The value of this register is saved in the CRYPTOCELL AO power domain.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [host_iot_kprtl_lock](index.html) module"] +pub struct HOST_IOT_KPRTL_LOCK_SPEC; +impl crate::RegisterSpec for HOST_IOT_KPRTL_LOCK_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [host_iot_kprtl_lock::R](R) reader structure"] +impl crate::Readable for HOST_IOT_KPRTL_LOCK_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [host_iot_kprtl_lock::W](W) writer structure"] +impl crate::Writable for HOST_IOT_KPRTL_LOCK_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets HOST_IOT_KPRTL_LOCK to value 0"] +impl crate::Resettable for HOST_IOT_KPRTL_LOCK_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/cc_host_rgf_s/host_iot_lcs.rs b/pacs/nrf9120-pac/src/cc_host_rgf_s/host_iot_lcs.rs new file mode 100644 index 00000000..4653d6bd --- /dev/null +++ b/pacs/nrf9120-pac/src/cc_host_rgf_s/host_iot_lcs.rs @@ -0,0 +1,189 @@ +#[doc = "Register `HOST_IOT_LCS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `HOST_IOT_LCS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `LCS` reader - Lifecycle state value. This field is write-once per reset."] +pub type LCS_R = crate::FieldReader; +#[doc = "Lifecycle state value. This field is write-once per reset.\n\nValue on reset: 2"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum LCS_A { + #[doc = "0: CC310 operates in debug mode"] + DEBUG = 0, + #[doc = "2: CC310 operates in secure mode"] + SECURE = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LCS_A) -> Self { + variant as _ + } +} +impl LCS_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(LCS_A::DEBUG), + 2 => Some(LCS_A::SECURE), + _ => None, + } + } + #[doc = "Checks if the value of the field is `DEBUG`"] + #[inline(always)] + pub fn is_debug(&self) -> bool { + *self == LCS_A::DEBUG + } + #[doc = "Checks if the value of the field is `SECURE`"] + #[inline(always)] + pub fn is_secure(&self) -> bool { + *self == LCS_A::SECURE + } +} +#[doc = "Field `LCS` writer - Lifecycle state value. This field is write-once per reset."] +pub type LCS_W<'a, const O: u8> = crate::FieldWriter<'a, u32, HOST_IOT_LCS_SPEC, u8, LCS_A, 3, O>; +impl<'a, const O: u8> LCS_W<'a, O> { + #[doc = "CC310 operates in debug mode"] + #[inline(always)] + pub fn debug(self) -> &'a mut W { + self.variant(LCS_A::DEBUG) + } + #[doc = "CC310 operates in secure mode"] + #[inline(always)] + pub fn secure(self) -> &'a mut W { + self.variant(LCS_A::SECURE) + } +} +#[doc = "Field `LCS_IS_VALID` reader - Read-only field. Indicates if CRYPTOCELL LCS has been successfully configured since last reset."] +pub type LCS_IS_VALID_R = crate::BitReader; +#[doc = "Read-only field. Indicates if CRYPTOCELL LCS has been successfully configured since last reset.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum LCS_IS_VALID_A { + #[doc = "0: Valid LCS not yet retained in the CRYPTOCELL AO power domain"] + INVALID = 0, + #[doc = "1: Valid LCS successfully retained in the CRYPTOCELL AO power domain"] + VALID = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: LCS_IS_VALID_A) -> Self { + variant as u8 != 0 + } +} +impl LCS_IS_VALID_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> LCS_IS_VALID_A { + match self.bits { + false => LCS_IS_VALID_A::INVALID, + true => LCS_IS_VALID_A::VALID, + } + } + #[doc = "Checks if the value of the field is `INVALID`"] + #[inline(always)] + pub fn is_invalid(&self) -> bool { + *self == LCS_IS_VALID_A::INVALID + } + #[doc = "Checks if the value of the field is `VALID`"] + #[inline(always)] + pub fn is_valid(&self) -> bool { + *self == LCS_IS_VALID_A::VALID + } +} +#[doc = "Field `LCS_IS_VALID` writer - Read-only field. Indicates if CRYPTOCELL LCS has been successfully configured since last reset."] +pub type LCS_IS_VALID_W<'a, const O: u8> = + crate::BitWriter<'a, u32, HOST_IOT_LCS_SPEC, LCS_IS_VALID_A, O>; +impl<'a, const O: u8> LCS_IS_VALID_W<'a, O> { + #[doc = "Valid LCS not yet retained in the CRYPTOCELL AO power domain"] + #[inline(always)] + pub fn invalid(self) -> &'a mut W { + self.variant(LCS_IS_VALID_A::INVALID) + } + #[doc = "Valid LCS successfully retained in the CRYPTOCELL AO power domain"] + #[inline(always)] + pub fn valid(self) -> &'a mut W { + self.variant(LCS_IS_VALID_A::VALID) + } +} +impl R { + #[doc = "Bits 0:2 - Lifecycle state value. This field is write-once per reset."] + #[inline(always)] + pub fn lcs(&self) -> LCS_R { + LCS_R::new((self.bits & 7) as u8) + } + #[doc = "Bit 8 - Read-only field. Indicates if CRYPTOCELL LCS has been successfully configured since last reset."] + #[inline(always)] + pub fn lcs_is_valid(&self) -> LCS_IS_VALID_R { + LCS_IS_VALID_R::new(((self.bits >> 8) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:2 - Lifecycle state value. This field is write-once per reset."] + #[inline(always)] + pub fn lcs(&mut self) -> LCS_W<0> { + LCS_W::new(self) + } + #[doc = "Bit 8 - Read-only field. Indicates if CRYPTOCELL LCS has been successfully configured since last reset."] + #[inline(always)] + pub fn lcs_is_valid(&mut self) -> LCS_IS_VALID_W<8> { + LCS_IS_VALID_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Controls lifecycle state (LCS) for CRYPTOCELL subsystem\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [host_iot_lcs](index.html) module"] +pub struct HOST_IOT_LCS_SPEC; +impl crate::RegisterSpec for HOST_IOT_LCS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [host_iot_lcs::R](R) reader structure"] +impl crate::Readable for HOST_IOT_LCS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [host_iot_lcs::W](W) writer structure"] +impl crate::Writable for HOST_IOT_LCS_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets HOST_IOT_LCS to value 0x02"] +impl crate::Resettable for HOST_IOT_LCS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x02 + } +} diff --git a/pacs/nrf9120-pac/src/clock_ns.rs b/pacs/nrf9120-pac/src/clock_ns.rs new file mode 100644 index 00000000..676d2408 --- /dev/null +++ b/pacs/nrf9120-pac/src/clock_ns.rs @@ -0,0 +1,143 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Start HFCLK source"] + pub tasks_hfclkstart: TASKS_HFCLKSTART, + #[doc = "0x04 - Stop HFCLK source"] + pub tasks_hfclkstop: TASKS_HFCLKSTOP, + #[doc = "0x08 - Start LFCLK source"] + pub tasks_lfclkstart: TASKS_LFCLKSTART, + #[doc = "0x0c - Stop LFCLK source"] + pub tasks_lfclkstop: TASKS_LFCLKSTOP, + _reserved4: [u8; 0x70], + #[doc = "0x80 - Subscribe configuration for task HFCLKSTART"] + pub subscribe_hfclkstart: SUBSCRIBE_HFCLKSTART, + #[doc = "0x84 - Subscribe configuration for task HFCLKSTOP"] + pub subscribe_hfclkstop: SUBSCRIBE_HFCLKSTOP, + #[doc = "0x88 - Subscribe configuration for task LFCLKSTART"] + pub subscribe_lfclkstart: SUBSCRIBE_LFCLKSTART, + #[doc = "0x8c - Subscribe configuration for task LFCLKSTOP"] + pub subscribe_lfclkstop: SUBSCRIBE_LFCLKSTOP, + _reserved8: [u8; 0x70], + #[doc = "0x100 - HFCLK oscillator started"] + pub events_hfclkstarted: EVENTS_HFCLKSTARTED, + #[doc = "0x104 - LFCLK started"] + pub events_lfclkstarted: EVENTS_LFCLKSTARTED, + _reserved10: [u8; 0x78], + #[doc = "0x180 - Publish configuration for event HFCLKSTARTED"] + pub publish_hfclkstarted: PUBLISH_HFCLKSTARTED, + #[doc = "0x184 - Publish configuration for event LFCLKSTARTED"] + pub publish_lfclkstarted: PUBLISH_LFCLKSTARTED, + _reserved12: [u8; 0x0178], + #[doc = "0x300 - Enable or disable interrupt"] + pub inten: INTEN, + #[doc = "0x304 - Enable interrupt"] + pub intenset: INTENSET, + #[doc = "0x308 - Disable interrupt"] + pub intenclr: INTENCLR, + #[doc = "0x30c - Pending interrupts"] + pub intpend: INTPEND, + _reserved16: [u8; 0xf8], + #[doc = "0x408 - Status indicating that HFCLKSTART task has been triggered"] + pub hfclkrun: HFCLKRUN, + #[doc = "0x40c - The register shows if HFXO has been requested by triggering HFCLKSTART task and if it has been started (STATE)"] + pub hfclkstat: HFCLKSTAT, + _reserved18: [u8; 0x04], + #[doc = "0x414 - Status indicating that LFCLKSTART task has been triggered"] + pub lfclkrun: LFCLKRUN, + #[doc = "0x418 - The register shows which LFCLK source has been requested (SRC) when triggering LFCLKSTART task and if the source has been started (STATE)"] + pub lfclkstat: LFCLKSTAT, + #[doc = "0x41c - Copy of LFCLKSRC register, set after LFCLKSTART task has been triggered"] + pub lfclksrccopy: LFCLKSRCCOPY, + _reserved21: [u8; 0xf8], + #[doc = "0x518 - Clock source for the LFCLK. LFCLKSTART task starts starts a clock source selected with this register."] + pub lfclksrc: LFCLKSRC, +} +#[doc = "TASKS_HFCLKSTART (w) register accessor: an alias for `Reg`"] +pub type TASKS_HFCLKSTART = crate::Reg; +#[doc = "Start HFCLK source"] +pub mod tasks_hfclkstart; +#[doc = "TASKS_HFCLKSTOP (w) register accessor: an alias for `Reg`"] +pub type TASKS_HFCLKSTOP = crate::Reg; +#[doc = "Stop HFCLK source"] +pub mod tasks_hfclkstop; +#[doc = "TASKS_LFCLKSTART (w) register accessor: an alias for `Reg`"] +pub type TASKS_LFCLKSTART = crate::Reg; +#[doc = "Start LFCLK source"] +pub mod tasks_lfclkstart; +#[doc = "TASKS_LFCLKSTOP (w) register accessor: an alias for `Reg`"] +pub type TASKS_LFCLKSTOP = crate::Reg; +#[doc = "Stop LFCLK source"] +pub mod tasks_lfclkstop; +#[doc = "SUBSCRIBE_HFCLKSTART (rw) register accessor: an alias for `Reg`"] +pub type SUBSCRIBE_HFCLKSTART = crate::Reg; +#[doc = "Subscribe configuration for task HFCLKSTART"] +pub mod subscribe_hfclkstart; +#[doc = "SUBSCRIBE_HFCLKSTOP (rw) register accessor: an alias for `Reg`"] +pub type SUBSCRIBE_HFCLKSTOP = crate::Reg; +#[doc = "Subscribe configuration for task HFCLKSTOP"] +pub mod subscribe_hfclkstop; +#[doc = "SUBSCRIBE_LFCLKSTART (rw) register accessor: an alias for `Reg`"] +pub type SUBSCRIBE_LFCLKSTART = crate::Reg; +#[doc = "Subscribe configuration for task LFCLKSTART"] +pub mod subscribe_lfclkstart; +#[doc = "SUBSCRIBE_LFCLKSTOP (rw) register accessor: an alias for `Reg`"] +pub type SUBSCRIBE_LFCLKSTOP = crate::Reg; +#[doc = "Subscribe configuration for task LFCLKSTOP"] +pub mod subscribe_lfclkstop; +#[doc = "EVENTS_HFCLKSTARTED (rw) register accessor: an alias for `Reg`"] +pub type EVENTS_HFCLKSTARTED = crate::Reg; +#[doc = "HFCLK oscillator started"] +pub mod events_hfclkstarted; +#[doc = "EVENTS_LFCLKSTARTED (rw) register accessor: an alias for `Reg`"] +pub type EVENTS_LFCLKSTARTED = crate::Reg; +#[doc = "LFCLK started"] +pub mod events_lfclkstarted; +#[doc = "PUBLISH_HFCLKSTARTED (rw) register accessor: an alias for `Reg`"] +pub type PUBLISH_HFCLKSTARTED = crate::Reg; +#[doc = "Publish configuration for event HFCLKSTARTED"] +pub mod publish_hfclkstarted; +#[doc = "PUBLISH_LFCLKSTARTED (rw) register accessor: an alias for `Reg`"] +pub type PUBLISH_LFCLKSTARTED = crate::Reg; +#[doc = "Publish configuration for event LFCLKSTARTED"] +pub mod publish_lfclkstarted; +#[doc = "INTEN (rw) register accessor: an alias for `Reg`"] +pub type INTEN = crate::Reg; +#[doc = "Enable or disable interrupt"] +pub mod inten; +#[doc = "INTENSET (rw) register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "Enable interrupt"] +pub mod intenset; +#[doc = "INTENCLR (rw) register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "Disable interrupt"] +pub mod intenclr; +#[doc = "INTPEND (r) register accessor: an alias for `Reg`"] +pub type INTPEND = crate::Reg; +#[doc = "Pending interrupts"] +pub mod intpend; +#[doc = "HFCLKRUN (r) register accessor: an alias for `Reg`"] +pub type HFCLKRUN = crate::Reg; +#[doc = "Status indicating that HFCLKSTART task has been triggered"] +pub mod hfclkrun; +#[doc = "HFCLKSTAT (r) register accessor: an alias for `Reg`"] +pub type HFCLKSTAT = crate::Reg; +#[doc = "The register shows if HFXO has been requested by triggering HFCLKSTART task and if it has been started (STATE)"] +pub mod hfclkstat; +#[doc = "LFCLKRUN (r) register accessor: an alias for `Reg`"] +pub type LFCLKRUN = crate::Reg; +#[doc = "Status indicating that LFCLKSTART task has been triggered"] +pub mod lfclkrun; +#[doc = "LFCLKSTAT (r) register accessor: an alias for `Reg`"] +pub type LFCLKSTAT = crate::Reg; +#[doc = "The register shows which LFCLK source has been requested (SRC) when triggering LFCLKSTART task and if the source has been started (STATE)"] +pub mod lfclkstat; +#[doc = "LFCLKSRCCOPY (r) register accessor: an alias for `Reg`"] +pub type LFCLKSRCCOPY = crate::Reg; +#[doc = "Copy of LFCLKSRC register, set after LFCLKSTART task has been triggered"] +pub mod lfclksrccopy; +#[doc = "LFCLKSRC (rw) register accessor: an alias for `Reg`"] +pub type LFCLKSRC = crate::Reg; +#[doc = "Clock source for the LFCLK. LFCLKSTART task starts starts a clock source selected with this register."] +pub mod lfclksrc; diff --git a/pacs/nrf9120-pac/src/clock_ns/events_hfclkstarted.rs b/pacs/nrf9120-pac/src/clock_ns/events_hfclkstarted.rs new file mode 100644 index 00000000..a0daba7b --- /dev/null +++ b/pacs/nrf9120-pac/src/clock_ns/events_hfclkstarted.rs @@ -0,0 +1,127 @@ +#[doc = "Register `EVENTS_HFCLKSTARTED` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVENTS_HFCLKSTARTED` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `EVENTS_HFCLKSTARTED` reader - HFCLK oscillator started"] +pub type EVENTS_HFCLKSTARTED_R = crate::BitReader; +#[doc = "HFCLK oscillator started\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum EVENTS_HFCLKSTARTED_A { + #[doc = "0: Event not generated"] + NOT_GENERATED = 0, + #[doc = "1: Event generated"] + GENERATED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: EVENTS_HFCLKSTARTED_A) -> Self { + variant as u8 != 0 + } +} +impl EVENTS_HFCLKSTARTED_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EVENTS_HFCLKSTARTED_A { + match self.bits { + false => EVENTS_HFCLKSTARTED_A::NOT_GENERATED, + true => EVENTS_HFCLKSTARTED_A::GENERATED, + } + } + #[doc = "Checks if the value of the field is `NOT_GENERATED`"] + #[inline(always)] + pub fn is_not_generated(&self) -> bool { + *self == EVENTS_HFCLKSTARTED_A::NOT_GENERATED + } + #[doc = "Checks if the value of the field is `GENERATED`"] + #[inline(always)] + pub fn is_generated(&self) -> bool { + *self == EVENTS_HFCLKSTARTED_A::GENERATED + } +} +#[doc = "Field `EVENTS_HFCLKSTARTED` writer - HFCLK oscillator started"] +pub type EVENTS_HFCLKSTARTED_W<'a, const O: u8> = + crate::BitWriter<'a, u32, EVENTS_HFCLKSTARTED_SPEC, EVENTS_HFCLKSTARTED_A, O>; +impl<'a, const O: u8> EVENTS_HFCLKSTARTED_W<'a, O> { + #[doc = "Event not generated"] + #[inline(always)] + pub fn not_generated(self) -> &'a mut W { + self.variant(EVENTS_HFCLKSTARTED_A::NOT_GENERATED) + } + #[doc = "Event generated"] + #[inline(always)] + pub fn generated(self) -> &'a mut W { + self.variant(EVENTS_HFCLKSTARTED_A::GENERATED) + } +} +impl R { + #[doc = "Bit 0 - HFCLK oscillator started"] + #[inline(always)] + pub fn events_hfclkstarted(&self) -> EVENTS_HFCLKSTARTED_R { + EVENTS_HFCLKSTARTED_R::new((self.bits & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - HFCLK oscillator started"] + #[inline(always)] + pub fn events_hfclkstarted(&mut self) -> EVENTS_HFCLKSTARTED_W<0> { + EVENTS_HFCLKSTARTED_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "HFCLK oscillator started\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [events_hfclkstarted](index.html) module"] +pub struct EVENTS_HFCLKSTARTED_SPEC; +impl crate::RegisterSpec for EVENTS_HFCLKSTARTED_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [events_hfclkstarted::R](R) reader structure"] +impl crate::Readable for EVENTS_HFCLKSTARTED_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [events_hfclkstarted::W](W) writer structure"] +impl crate::Writable for EVENTS_HFCLKSTARTED_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EVENTS_HFCLKSTARTED to value 0"] +impl crate::Resettable for EVENTS_HFCLKSTARTED_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/clock_ns/events_lfclkstarted.rs b/pacs/nrf9120-pac/src/clock_ns/events_lfclkstarted.rs new file mode 100644 index 00000000..0991bf45 --- /dev/null +++ b/pacs/nrf9120-pac/src/clock_ns/events_lfclkstarted.rs @@ -0,0 +1,127 @@ +#[doc = "Register `EVENTS_LFCLKSTARTED` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVENTS_LFCLKSTARTED` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `EVENTS_LFCLKSTARTED` reader - LFCLK started"] +pub type EVENTS_LFCLKSTARTED_R = crate::BitReader; +#[doc = "LFCLK started\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum EVENTS_LFCLKSTARTED_A { + #[doc = "0: Event not generated"] + NOT_GENERATED = 0, + #[doc = "1: Event generated"] + GENERATED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: EVENTS_LFCLKSTARTED_A) -> Self { + variant as u8 != 0 + } +} +impl EVENTS_LFCLKSTARTED_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EVENTS_LFCLKSTARTED_A { + match self.bits { + false => EVENTS_LFCLKSTARTED_A::NOT_GENERATED, + true => EVENTS_LFCLKSTARTED_A::GENERATED, + } + } + #[doc = "Checks if the value of the field is `NOT_GENERATED`"] + #[inline(always)] + pub fn is_not_generated(&self) -> bool { + *self == EVENTS_LFCLKSTARTED_A::NOT_GENERATED + } + #[doc = "Checks if the value of the field is `GENERATED`"] + #[inline(always)] + pub fn is_generated(&self) -> bool { + *self == EVENTS_LFCLKSTARTED_A::GENERATED + } +} +#[doc = "Field `EVENTS_LFCLKSTARTED` writer - LFCLK started"] +pub type EVENTS_LFCLKSTARTED_W<'a, const O: u8> = + crate::BitWriter<'a, u32, EVENTS_LFCLKSTARTED_SPEC, EVENTS_LFCLKSTARTED_A, O>; +impl<'a, const O: u8> EVENTS_LFCLKSTARTED_W<'a, O> { + #[doc = "Event not generated"] + #[inline(always)] + pub fn not_generated(self) -> &'a mut W { + self.variant(EVENTS_LFCLKSTARTED_A::NOT_GENERATED) + } + #[doc = "Event generated"] + #[inline(always)] + pub fn generated(self) -> &'a mut W { + self.variant(EVENTS_LFCLKSTARTED_A::GENERATED) + } +} +impl R { + #[doc = "Bit 0 - LFCLK started"] + #[inline(always)] + pub fn events_lfclkstarted(&self) -> EVENTS_LFCLKSTARTED_R { + EVENTS_LFCLKSTARTED_R::new((self.bits & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - LFCLK started"] + #[inline(always)] + pub fn events_lfclkstarted(&mut self) -> EVENTS_LFCLKSTARTED_W<0> { + EVENTS_LFCLKSTARTED_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "LFCLK started\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [events_lfclkstarted](index.html) module"] +pub struct EVENTS_LFCLKSTARTED_SPEC; +impl crate::RegisterSpec for EVENTS_LFCLKSTARTED_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [events_lfclkstarted::R](R) reader structure"] +impl crate::Readable for EVENTS_LFCLKSTARTED_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [events_lfclkstarted::W](W) writer structure"] +impl crate::Writable for EVENTS_LFCLKSTARTED_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EVENTS_LFCLKSTARTED to value 0"] +impl crate::Resettable for EVENTS_LFCLKSTARTED_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/clock_ns/hfclkrun.rs b/pacs/nrf9120-pac/src/clock_ns/hfclkrun.rs new file mode 100644 index 00000000..60e16059 --- /dev/null +++ b/pacs/nrf9120-pac/src/clock_ns/hfclkrun.rs @@ -0,0 +1,74 @@ +#[doc = "Register `HFCLKRUN` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `STATUS` reader - HFCLKSTART task triggered or not"] +pub type STATUS_R = crate::BitReader; +#[doc = "HFCLKSTART task triggered or not\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum STATUS_A { + #[doc = "0: Task not triggered"] + NOT_TRIGGERED = 0, + #[doc = "1: Task triggered"] + TRIGGERED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: STATUS_A) -> Self { + variant as u8 != 0 + } +} +impl STATUS_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> STATUS_A { + match self.bits { + false => STATUS_A::NOT_TRIGGERED, + true => STATUS_A::TRIGGERED, + } + } + #[doc = "Checks if the value of the field is `NOT_TRIGGERED`"] + #[inline(always)] + pub fn is_not_triggered(&self) -> bool { + *self == STATUS_A::NOT_TRIGGERED + } + #[doc = "Checks if the value of the field is `TRIGGERED`"] + #[inline(always)] + pub fn is_triggered(&self) -> bool { + *self == STATUS_A::TRIGGERED + } +} +impl R { + #[doc = "Bit 0 - HFCLKSTART task triggered or not"] + #[inline(always)] + pub fn status(&self) -> STATUS_R { + STATUS_R::new((self.bits & 1) != 0) + } +} +#[doc = "Status indicating that HFCLKSTART task has been triggered\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hfclkrun](index.html) module"] +pub struct HFCLKRUN_SPEC; +impl crate::RegisterSpec for HFCLKRUN_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [hfclkrun::R](R) reader structure"] +impl crate::Readable for HFCLKRUN_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets HFCLKRUN to value 0"] +impl crate::Resettable for HFCLKRUN_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/clock_ns/hfclkstat.rs b/pacs/nrf9120-pac/src/clock_ns/hfclkstat.rs new file mode 100644 index 00000000..faece9d8 --- /dev/null +++ b/pacs/nrf9120-pac/src/clock_ns/hfclkstat.rs @@ -0,0 +1,115 @@ +#[doc = "Register `HFCLKSTAT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SRC` reader - Active clock source"] +pub type SRC_R = crate::BitReader; +#[doc = "Active clock source\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum SRC_A { + #[doc = "0: HFINT - 64 MHz on-chip oscillator"] + HFINT = 0, + #[doc = "1: HFXO - 64 MHz clock derived from external 32 MHz crystal oscillator"] + HFXO = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: SRC_A) -> Self { + variant as u8 != 0 + } +} +impl SRC_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> SRC_A { + match self.bits { + false => SRC_A::HFINT, + true => SRC_A::HFXO, + } + } + #[doc = "Checks if the value of the field is `HFINT`"] + #[inline(always)] + pub fn is_hfint(&self) -> bool { + *self == SRC_A::HFINT + } + #[doc = "Checks if the value of the field is `HFXO`"] + #[inline(always)] + pub fn is_hfxo(&self) -> bool { + *self == SRC_A::HFXO + } +} +#[doc = "Field `STATE` reader - HFCLK state"] +pub type STATE_R = crate::BitReader; +#[doc = "HFCLK state\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum STATE_A { + #[doc = "0: HFXO has not been started or HFCLKSTOP task has been triggered"] + NOT_RUNNING = 0, + #[doc = "1: HFXO has been started (HFCLKSTARTED event has been generated)"] + RUNNING = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: STATE_A) -> Self { + variant as u8 != 0 + } +} +impl STATE_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> STATE_A { + match self.bits { + false => STATE_A::NOT_RUNNING, + true => STATE_A::RUNNING, + } + } + #[doc = "Checks if the value of the field is `NOT_RUNNING`"] + #[inline(always)] + pub fn is_not_running(&self) -> bool { + *self == STATE_A::NOT_RUNNING + } + #[doc = "Checks if the value of the field is `RUNNING`"] + #[inline(always)] + pub fn is_running(&self) -> bool { + *self == STATE_A::RUNNING + } +} +impl R { + #[doc = "Bit 0 - Active clock source"] + #[inline(always)] + pub fn src(&self) -> SRC_R { + SRC_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 16 - HFCLK state"] + #[inline(always)] + pub fn state(&self) -> STATE_R { + STATE_R::new(((self.bits >> 16) & 1) != 0) + } +} +#[doc = "The register shows if HFXO has been requested by triggering HFCLKSTART task and if it has been started (STATE)\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hfclkstat](index.html) module"] +pub struct HFCLKSTAT_SPEC; +impl crate::RegisterSpec for HFCLKSTAT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [hfclkstat::R](R) reader structure"] +impl crate::Readable for HFCLKSTAT_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets HFCLKSTAT to value 0"] +impl crate::Resettable for HFCLKSTAT_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/clock_ns/inten.rs b/pacs/nrf9120-pac/src/clock_ns/inten.rs new file mode 100644 index 00000000..e3aef574 --- /dev/null +++ b/pacs/nrf9120-pac/src/clock_ns/inten.rs @@ -0,0 +1,186 @@ +#[doc = "Register `INTEN` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTEN` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `HFCLKSTARTED` reader - Enable or disable interrupt for event HFCLKSTARTED"] +pub type HFCLKSTARTED_R = crate::BitReader; +#[doc = "Enable or disable interrupt for event HFCLKSTARTED\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum HFCLKSTARTED_A { + #[doc = "0: Disable"] + DISABLED = 0, + #[doc = "1: Enable"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: HFCLKSTARTED_A) -> Self { + variant as u8 != 0 + } +} +impl HFCLKSTARTED_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> HFCLKSTARTED_A { + match self.bits { + false => HFCLKSTARTED_A::DISABLED, + true => HFCLKSTARTED_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == HFCLKSTARTED_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == HFCLKSTARTED_A::ENABLED + } +} +#[doc = "Field `HFCLKSTARTED` writer - Enable or disable interrupt for event HFCLKSTARTED"] +pub type HFCLKSTARTED_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTEN_SPEC, HFCLKSTARTED_A, O>; +impl<'a, const O: u8> HFCLKSTARTED_W<'a, O> { + #[doc = "Disable"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(HFCLKSTARTED_A::DISABLED) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(HFCLKSTARTED_A::ENABLED) + } +} +#[doc = "Field `LFCLKSTARTED` reader - Enable or disable interrupt for event LFCLKSTARTED"] +pub type LFCLKSTARTED_R = crate::BitReader; +#[doc = "Enable or disable interrupt for event LFCLKSTARTED\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum LFCLKSTARTED_A { + #[doc = "0: Disable"] + DISABLED = 0, + #[doc = "1: Enable"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: LFCLKSTARTED_A) -> Self { + variant as u8 != 0 + } +} +impl LFCLKSTARTED_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> LFCLKSTARTED_A { + match self.bits { + false => LFCLKSTARTED_A::DISABLED, + true => LFCLKSTARTED_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == LFCLKSTARTED_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == LFCLKSTARTED_A::ENABLED + } +} +#[doc = "Field `LFCLKSTARTED` writer - Enable or disable interrupt for event LFCLKSTARTED"] +pub type LFCLKSTARTED_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTEN_SPEC, LFCLKSTARTED_A, O>; +impl<'a, const O: u8> LFCLKSTARTED_W<'a, O> { + #[doc = "Disable"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(LFCLKSTARTED_A::DISABLED) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(LFCLKSTARTED_A::ENABLED) + } +} +impl R { + #[doc = "Bit 0 - Enable or disable interrupt for event HFCLKSTARTED"] + #[inline(always)] + pub fn hfclkstarted(&self) -> HFCLKSTARTED_R { + HFCLKSTARTED_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Enable or disable interrupt for event LFCLKSTARTED"] + #[inline(always)] + pub fn lfclkstarted(&self) -> LFCLKSTARTED_R { + LFCLKSTARTED_R::new(((self.bits >> 1) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Enable or disable interrupt for event HFCLKSTARTED"] + #[inline(always)] + pub fn hfclkstarted(&mut self) -> HFCLKSTARTED_W<0> { + HFCLKSTARTED_W::new(self) + } + #[doc = "Bit 1 - Enable or disable interrupt for event LFCLKSTARTED"] + #[inline(always)] + pub fn lfclkstarted(&mut self) -> LFCLKSTARTED_W<1> { + LFCLKSTARTED_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Enable or disable interrupt\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [inten](index.html) module"] +pub struct INTEN_SPEC; +impl crate::RegisterSpec for INTEN_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [inten::R](R) reader structure"] +impl crate::Readable for INTEN_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [inten::W](W) writer structure"] +impl crate::Writable for INTEN_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTEN to value 0"] +impl crate::Resettable for INTEN_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/clock_ns/intenclr.rs b/pacs/nrf9120-pac/src/clock_ns/intenclr.rs new file mode 100644 index 00000000..93d64a28 --- /dev/null +++ b/pacs/nrf9120-pac/src/clock_ns/intenclr.rs @@ -0,0 +1,202 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `HFCLKSTARTED` reader - Write '1' to disable interrupt for event HFCLKSTARTED"] +pub type HFCLKSTARTED_R = crate::BitReader; +#[doc = "Write '1' to disable interrupt for event HFCLKSTARTED\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum HFCLKSTARTED_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: HFCLKSTARTED_A) -> Self { + variant as u8 != 0 + } +} +impl HFCLKSTARTED_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> HFCLKSTARTED_A { + match self.bits { + false => HFCLKSTARTED_A::DISABLED, + true => HFCLKSTARTED_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == HFCLKSTARTED_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == HFCLKSTARTED_A::ENABLED + } +} +#[doc = "Write '1' to disable interrupt for event HFCLKSTARTED\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum HFCLKSTARTED_AW { + #[doc = "1: Disable"] + CLEAR = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: HFCLKSTARTED_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `HFCLKSTARTED` writer - Write '1' to disable interrupt for event HFCLKSTARTED"] +pub type HFCLKSTARTED_W<'a, const O: u8> = + crate::BitWriter<'a, u32, INTENCLR_SPEC, HFCLKSTARTED_AW, O>; +impl<'a, const O: u8> HFCLKSTARTED_W<'a, O> { + #[doc = "Disable"] + #[inline(always)] + pub fn clear(self) -> &'a mut W { + self.variant(HFCLKSTARTED_AW::CLEAR) + } +} +#[doc = "Field `LFCLKSTARTED` reader - Write '1' to disable interrupt for event LFCLKSTARTED"] +pub type LFCLKSTARTED_R = crate::BitReader; +#[doc = "Write '1' to disable interrupt for event LFCLKSTARTED\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum LFCLKSTARTED_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: LFCLKSTARTED_A) -> Self { + variant as u8 != 0 + } +} +impl LFCLKSTARTED_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> LFCLKSTARTED_A { + match self.bits { + false => LFCLKSTARTED_A::DISABLED, + true => LFCLKSTARTED_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == LFCLKSTARTED_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == LFCLKSTARTED_A::ENABLED + } +} +#[doc = "Write '1' to disable interrupt for event LFCLKSTARTED\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum LFCLKSTARTED_AW { + #[doc = "1: Disable"] + CLEAR = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: LFCLKSTARTED_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LFCLKSTARTED` writer - Write '1' to disable interrupt for event LFCLKSTARTED"] +pub type LFCLKSTARTED_W<'a, const O: u8> = + crate::BitWriter<'a, u32, INTENCLR_SPEC, LFCLKSTARTED_AW, O>; +impl<'a, const O: u8> LFCLKSTARTED_W<'a, O> { + #[doc = "Disable"] + #[inline(always)] + pub fn clear(self) -> &'a mut W { + self.variant(LFCLKSTARTED_AW::CLEAR) + } +} +impl R { + #[doc = "Bit 0 - Write '1' to disable interrupt for event HFCLKSTARTED"] + #[inline(always)] + pub fn hfclkstarted(&self) -> HFCLKSTARTED_R { + HFCLKSTARTED_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Write '1' to disable interrupt for event LFCLKSTARTED"] + #[inline(always)] + pub fn lfclkstarted(&self) -> LFCLKSTARTED_R { + LFCLKSTARTED_R::new(((self.bits >> 1) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Write '1' to disable interrupt for event HFCLKSTARTED"] + #[inline(always)] + pub fn hfclkstarted(&mut self) -> HFCLKSTARTED_W<0> { + HFCLKSTARTED_W::new(self) + } + #[doc = "Bit 1 - Write '1' to disable interrupt for event LFCLKSTARTED"] + #[inline(always)] + pub fn lfclkstarted(&mut self) -> LFCLKSTARTED_W<1> { + LFCLKSTARTED_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Disable interrupt\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/clock_ns/intenset.rs b/pacs/nrf9120-pac/src/clock_ns/intenset.rs new file mode 100644 index 00000000..ec495364 --- /dev/null +++ b/pacs/nrf9120-pac/src/clock_ns/intenset.rs @@ -0,0 +1,202 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `HFCLKSTARTED` reader - Write '1' to enable interrupt for event HFCLKSTARTED"] +pub type HFCLKSTARTED_R = crate::BitReader; +#[doc = "Write '1' to enable interrupt for event HFCLKSTARTED\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum HFCLKSTARTED_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: HFCLKSTARTED_A) -> Self { + variant as u8 != 0 + } +} +impl HFCLKSTARTED_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> HFCLKSTARTED_A { + match self.bits { + false => HFCLKSTARTED_A::DISABLED, + true => HFCLKSTARTED_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == HFCLKSTARTED_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == HFCLKSTARTED_A::ENABLED + } +} +#[doc = "Write '1' to enable interrupt for event HFCLKSTARTED\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum HFCLKSTARTED_AW { + #[doc = "1: Enable"] + SET = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: HFCLKSTARTED_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `HFCLKSTARTED` writer - Write '1' to enable interrupt for event HFCLKSTARTED"] +pub type HFCLKSTARTED_W<'a, const O: u8> = + crate::BitWriter<'a, u32, INTENSET_SPEC, HFCLKSTARTED_AW, O>; +impl<'a, const O: u8> HFCLKSTARTED_W<'a, O> { + #[doc = "Enable"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(HFCLKSTARTED_AW::SET) + } +} +#[doc = "Field `LFCLKSTARTED` reader - Write '1' to enable interrupt for event LFCLKSTARTED"] +pub type LFCLKSTARTED_R = crate::BitReader; +#[doc = "Write '1' to enable interrupt for event LFCLKSTARTED\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum LFCLKSTARTED_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: LFCLKSTARTED_A) -> Self { + variant as u8 != 0 + } +} +impl LFCLKSTARTED_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> LFCLKSTARTED_A { + match self.bits { + false => LFCLKSTARTED_A::DISABLED, + true => LFCLKSTARTED_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == LFCLKSTARTED_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == LFCLKSTARTED_A::ENABLED + } +} +#[doc = "Write '1' to enable interrupt for event LFCLKSTARTED\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum LFCLKSTARTED_AW { + #[doc = "1: Enable"] + SET = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: LFCLKSTARTED_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LFCLKSTARTED` writer - Write '1' to enable interrupt for event LFCLKSTARTED"] +pub type LFCLKSTARTED_W<'a, const O: u8> = + crate::BitWriter<'a, u32, INTENSET_SPEC, LFCLKSTARTED_AW, O>; +impl<'a, const O: u8> LFCLKSTARTED_W<'a, O> { + #[doc = "Enable"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(LFCLKSTARTED_AW::SET) + } +} +impl R { + #[doc = "Bit 0 - Write '1' to enable interrupt for event HFCLKSTARTED"] + #[inline(always)] + pub fn hfclkstarted(&self) -> HFCLKSTARTED_R { + HFCLKSTARTED_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Write '1' to enable interrupt for event LFCLKSTARTED"] + #[inline(always)] + pub fn lfclkstarted(&self) -> LFCLKSTARTED_R { + LFCLKSTARTED_R::new(((self.bits >> 1) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Write '1' to enable interrupt for event HFCLKSTARTED"] + #[inline(always)] + pub fn hfclkstarted(&mut self) -> HFCLKSTARTED_W<0> { + HFCLKSTARTED_W::new(self) + } + #[doc = "Bit 1 - Write '1' to enable interrupt for event LFCLKSTARTED"] + #[inline(always)] + pub fn lfclkstarted(&mut self) -> LFCLKSTARTED_W<1> { + LFCLKSTARTED_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Enable interrupt\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/clock_ns/intpend.rs b/pacs/nrf9120-pac/src/clock_ns/intpend.rs new file mode 100644 index 00000000..d90b03c1 --- /dev/null +++ b/pacs/nrf9120-pac/src/clock_ns/intpend.rs @@ -0,0 +1,115 @@ +#[doc = "Register `INTPEND` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `HFCLKSTARTED` reader - Read pending status of interrupt for event HFCLKSTARTED"] +pub type HFCLKSTARTED_R = crate::BitReader; +#[doc = "Read pending status of interrupt for event HFCLKSTARTED\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum HFCLKSTARTED_A { + #[doc = "0: Read: Not pending"] + NOT_PENDING = 0, + #[doc = "1: Read: Pending"] + PENDING = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: HFCLKSTARTED_A) -> Self { + variant as u8 != 0 + } +} +impl HFCLKSTARTED_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> HFCLKSTARTED_A { + match self.bits { + false => HFCLKSTARTED_A::NOT_PENDING, + true => HFCLKSTARTED_A::PENDING, + } + } + #[doc = "Checks if the value of the field is `NOT_PENDING`"] + #[inline(always)] + pub fn is_not_pending(&self) -> bool { + *self == HFCLKSTARTED_A::NOT_PENDING + } + #[doc = "Checks if the value of the field is `PENDING`"] + #[inline(always)] + pub fn is_pending(&self) -> bool { + *self == HFCLKSTARTED_A::PENDING + } +} +#[doc = "Field `LFCLKSTARTED` reader - Read pending status of interrupt for event LFCLKSTARTED"] +pub type LFCLKSTARTED_R = crate::BitReader; +#[doc = "Read pending status of interrupt for event LFCLKSTARTED\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum LFCLKSTARTED_A { + #[doc = "0: Read: Not pending"] + NOT_PENDING = 0, + #[doc = "1: Read: Pending"] + PENDING = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: LFCLKSTARTED_A) -> Self { + variant as u8 != 0 + } +} +impl LFCLKSTARTED_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> LFCLKSTARTED_A { + match self.bits { + false => LFCLKSTARTED_A::NOT_PENDING, + true => LFCLKSTARTED_A::PENDING, + } + } + #[doc = "Checks if the value of the field is `NOT_PENDING`"] + #[inline(always)] + pub fn is_not_pending(&self) -> bool { + *self == LFCLKSTARTED_A::NOT_PENDING + } + #[doc = "Checks if the value of the field is `PENDING`"] + #[inline(always)] + pub fn is_pending(&self) -> bool { + *self == LFCLKSTARTED_A::PENDING + } +} +impl R { + #[doc = "Bit 0 - Read pending status of interrupt for event HFCLKSTARTED"] + #[inline(always)] + pub fn hfclkstarted(&self) -> HFCLKSTARTED_R { + HFCLKSTARTED_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Read pending status of interrupt for event LFCLKSTARTED"] + #[inline(always)] + pub fn lfclkstarted(&self) -> LFCLKSTARTED_R { + LFCLKSTARTED_R::new(((self.bits >> 1) & 1) != 0) + } +} +#[doc = "Pending interrupts\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intpend](index.html) module"] +pub struct INTPEND_SPEC; +impl crate::RegisterSpec for INTPEND_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intpend::R](R) reader structure"] +impl crate::Readable for INTPEND_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets INTPEND to value 0"] +impl crate::Resettable for INTPEND_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/clock_ns/lfclkrun.rs b/pacs/nrf9120-pac/src/clock_ns/lfclkrun.rs new file mode 100644 index 00000000..4e94c2a1 --- /dev/null +++ b/pacs/nrf9120-pac/src/clock_ns/lfclkrun.rs @@ -0,0 +1,74 @@ +#[doc = "Register `LFCLKRUN` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `STATUS` reader - LFCLKSTART task triggered or not"] +pub type STATUS_R = crate::BitReader; +#[doc = "LFCLKSTART task triggered or not\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum STATUS_A { + #[doc = "0: Task not triggered"] + NOT_TRIGGERED = 0, + #[doc = "1: Task triggered"] + TRIGGERED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: STATUS_A) -> Self { + variant as u8 != 0 + } +} +impl STATUS_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> STATUS_A { + match self.bits { + false => STATUS_A::NOT_TRIGGERED, + true => STATUS_A::TRIGGERED, + } + } + #[doc = "Checks if the value of the field is `NOT_TRIGGERED`"] + #[inline(always)] + pub fn is_not_triggered(&self) -> bool { + *self == STATUS_A::NOT_TRIGGERED + } + #[doc = "Checks if the value of the field is `TRIGGERED`"] + #[inline(always)] + pub fn is_triggered(&self) -> bool { + *self == STATUS_A::TRIGGERED + } +} +impl R { + #[doc = "Bit 0 - LFCLKSTART task triggered or not"] + #[inline(always)] + pub fn status(&self) -> STATUS_R { + STATUS_R::new((self.bits & 1) != 0) + } +} +#[doc = "Status indicating that LFCLKSTART task has been triggered\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [lfclkrun](index.html) module"] +pub struct LFCLKRUN_SPEC; +impl crate::RegisterSpec for LFCLKRUN_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [lfclkrun::R](R) reader structure"] +impl crate::Readable for LFCLKRUN_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets LFCLKRUN to value 0"] +impl crate::Resettable for LFCLKRUN_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/clock_ns/lfclksrc.rs b/pacs/nrf9120-pac/src/clock_ns/lfclksrc.rs new file mode 100644 index 00000000..0f73fc57 --- /dev/null +++ b/pacs/nrf9120-pac/src/clock_ns/lfclksrc.rs @@ -0,0 +1,141 @@ +#[doc = "Register `LFCLKSRC` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `LFCLKSRC` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SRC` reader - Clock source"] +pub type SRC_R = crate::FieldReader; +#[doc = "Clock source\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SRC_A { + #[doc = "0: Reserved for future use (equals selecting LFRC)"] + RFU = 0, + #[doc = "1: 32.768 kHz RC oscillator"] + LFRC = 1, + #[doc = "2: 32.768 kHz crystal oscillator"] + LFXO = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SRC_A) -> Self { + variant as _ + } +} +impl SRC_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SRC_A::RFU), + 1 => Some(SRC_A::LFRC), + 2 => Some(SRC_A::LFXO), + _ => None, + } + } + #[doc = "Checks if the value of the field is `RFU`"] + #[inline(always)] + pub fn is_rfu(&self) -> bool { + *self == SRC_A::RFU + } + #[doc = "Checks if the value of the field is `LFRC`"] + #[inline(always)] + pub fn is_lfrc(&self) -> bool { + *self == SRC_A::LFRC + } + #[doc = "Checks if the value of the field is `LFXO`"] + #[inline(always)] + pub fn is_lfxo(&self) -> bool { + *self == SRC_A::LFXO + } +} +#[doc = "Field `SRC` writer - Clock source"] +pub type SRC_W<'a, const O: u8> = crate::FieldWriter<'a, u32, LFCLKSRC_SPEC, u8, SRC_A, 2, O>; +impl<'a, const O: u8> SRC_W<'a, O> { + #[doc = "Reserved for future use (equals selecting LFRC)"] + #[inline(always)] + pub fn rfu(self) -> &'a mut W { + self.variant(SRC_A::RFU) + } + #[doc = "32.768 kHz RC oscillator"] + #[inline(always)] + pub fn lfrc(self) -> &'a mut W { + self.variant(SRC_A::LFRC) + } + #[doc = "32.768 kHz crystal oscillator"] + #[inline(always)] + pub fn lfxo(self) -> &'a mut W { + self.variant(SRC_A::LFXO) + } +} +impl R { + #[doc = "Bits 0:1 - Clock source"] + #[inline(always)] + pub fn src(&self) -> SRC_R { + SRC_R::new((self.bits & 3) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Clock source"] + #[inline(always)] + pub fn src(&mut self) -> SRC_W<0> { + SRC_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Clock source for the LFCLK. LFCLKSTART task starts starts a clock source selected with this register.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [lfclksrc](index.html) module"] +pub struct LFCLKSRC_SPEC; +impl crate::RegisterSpec for LFCLKSRC_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [lfclksrc::R](R) reader structure"] +impl crate::Readable for LFCLKSRC_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [lfclksrc::W](W) writer structure"] +impl crate::Writable for LFCLKSRC_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets LFCLKSRC to value 0x01"] +impl crate::Resettable for LFCLKSRC_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x01 + } +} diff --git a/pacs/nrf9120-pac/src/clock_ns/lfclksrccopy.rs b/pacs/nrf9120-pac/src/clock_ns/lfclksrccopy.rs new file mode 100644 index 00000000..d75df8f3 --- /dev/null +++ b/pacs/nrf9120-pac/src/clock_ns/lfclksrccopy.rs @@ -0,0 +1,84 @@ +#[doc = "Register `LFCLKSRCCOPY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SRC` reader - Clock source"] +pub type SRC_R = crate::FieldReader; +#[doc = "Clock source\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SRC_A { + #[doc = "0: Reserved for future use"] + RFU = 0, + #[doc = "1: 32.768 kHz RC oscillator"] + LFRC = 1, + #[doc = "2: 32.768 kHz crystal oscillator"] + LFXO = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SRC_A) -> Self { + variant as _ + } +} +impl SRC_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SRC_A::RFU), + 1 => Some(SRC_A::LFRC), + 2 => Some(SRC_A::LFXO), + _ => None, + } + } + #[doc = "Checks if the value of the field is `RFU`"] + #[inline(always)] + pub fn is_rfu(&self) -> bool { + *self == SRC_A::RFU + } + #[doc = "Checks if the value of the field is `LFRC`"] + #[inline(always)] + pub fn is_lfrc(&self) -> bool { + *self == SRC_A::LFRC + } + #[doc = "Checks if the value of the field is `LFXO`"] + #[inline(always)] + pub fn is_lfxo(&self) -> bool { + *self == SRC_A::LFXO + } +} +impl R { + #[doc = "Bits 0:1 - Clock source"] + #[inline(always)] + pub fn src(&self) -> SRC_R { + SRC_R::new((self.bits & 3) as u8) + } +} +#[doc = "Copy of LFCLKSRC register, set after LFCLKSTART task has been triggered\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [lfclksrccopy](index.html) module"] +pub struct LFCLKSRCCOPY_SPEC; +impl crate::RegisterSpec for LFCLKSRCCOPY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [lfclksrccopy::R](R) reader structure"] +impl crate::Readable for LFCLKSRCCOPY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets LFCLKSRCCOPY to value 0x01"] +impl crate::Resettable for LFCLKSRCCOPY_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x01 + } +} diff --git a/pacs/nrf9120-pac/src/clock_ns/lfclkstat.rs b/pacs/nrf9120-pac/src/clock_ns/lfclkstat.rs new file mode 100644 index 00000000..a141e230 --- /dev/null +++ b/pacs/nrf9120-pac/src/clock_ns/lfclkstat.rs @@ -0,0 +1,125 @@ +#[doc = "Register `LFCLKSTAT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SRC` reader - Active clock source"] +pub type SRC_R = crate::FieldReader; +#[doc = "Active clock source\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SRC_A { + #[doc = "0: Reserved for future use"] + RFU = 0, + #[doc = "1: 32.768 kHz RC oscillator"] + LFRC = 1, + #[doc = "2: 32.768 kHz crystal oscillator"] + LFXO = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SRC_A) -> Self { + variant as _ + } +} +impl SRC_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SRC_A::RFU), + 1 => Some(SRC_A::LFRC), + 2 => Some(SRC_A::LFXO), + _ => None, + } + } + #[doc = "Checks if the value of the field is `RFU`"] + #[inline(always)] + pub fn is_rfu(&self) -> bool { + *self == SRC_A::RFU + } + #[doc = "Checks if the value of the field is `LFRC`"] + #[inline(always)] + pub fn is_lfrc(&self) -> bool { + *self == SRC_A::LFRC + } + #[doc = "Checks if the value of the field is `LFXO`"] + #[inline(always)] + pub fn is_lfxo(&self) -> bool { + *self == SRC_A::LFXO + } +} +#[doc = "Field `STATE` reader - LFCLK state"] +pub type STATE_R = crate::BitReader; +#[doc = "LFCLK state\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum STATE_A { + #[doc = "0: Requested LFCLK source has not been started or LFCLKSTOP task has been triggered"] + NOT_RUNNING = 0, + #[doc = "1: Requested LFCLK source has been started (LFCLKSTARTED event has been generated)"] + RUNNING = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: STATE_A) -> Self { + variant as u8 != 0 + } +} +impl STATE_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> STATE_A { + match self.bits { + false => STATE_A::NOT_RUNNING, + true => STATE_A::RUNNING, + } + } + #[doc = "Checks if the value of the field is `NOT_RUNNING`"] + #[inline(always)] + pub fn is_not_running(&self) -> bool { + *self == STATE_A::NOT_RUNNING + } + #[doc = "Checks if the value of the field is `RUNNING`"] + #[inline(always)] + pub fn is_running(&self) -> bool { + *self == STATE_A::RUNNING + } +} +impl R { + #[doc = "Bits 0:1 - Active clock source"] + #[inline(always)] + pub fn src(&self) -> SRC_R { + SRC_R::new((self.bits & 3) as u8) + } + #[doc = "Bit 16 - LFCLK state"] + #[inline(always)] + pub fn state(&self) -> STATE_R { + STATE_R::new(((self.bits >> 16) & 1) != 0) + } +} +#[doc = "The register shows which LFCLK source has been requested (SRC) when triggering LFCLKSTART task and if the source has been started (STATE)\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [lfclkstat](index.html) module"] +pub struct LFCLKSTAT_SPEC; +impl crate::RegisterSpec for LFCLKSTAT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [lfclkstat::R](R) reader structure"] +impl crate::Readable for LFCLKSTAT_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets LFCLKSTAT to value 0"] +impl crate::Resettable for LFCLKSTAT_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/clock_ns/publish_hfclkstarted.rs b/pacs/nrf9120-pac/src/clock_ns/publish_hfclkstarted.rs new file mode 100644 index 00000000..85df5fee --- /dev/null +++ b/pacs/nrf9120-pac/src/clock_ns/publish_hfclkstarted.rs @@ -0,0 +1,141 @@ +#[doc = "Register `PUBLISH_HFCLKSTARTED` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PUBLISH_HFCLKSTARTED` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CHIDX` reader - DPPI channel that event HFCLKSTARTED will publish to"] +pub type CHIDX_R = crate::FieldReader; +#[doc = "Field `CHIDX` writer - DPPI channel that event HFCLKSTARTED will publish to"] +pub type CHIDX_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, PUBLISH_HFCLKSTARTED_SPEC, u8, u8, 8, O>; +#[doc = "Field `EN` reader - "] +pub type EN_R = crate::BitReader; +#[doc = "\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum EN_A { + #[doc = "0: Disable publishing"] + DISABLED = 0, + #[doc = "1: Enable publishing"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: EN_A) -> Self { + variant as u8 != 0 + } +} +impl EN_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EN_A { + match self.bits { + false => EN_A::DISABLED, + true => EN_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == EN_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == EN_A::ENABLED + } +} +#[doc = "Field `EN` writer - "] +pub type EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, PUBLISH_HFCLKSTARTED_SPEC, EN_A, O>; +impl<'a, const O: u8> EN_W<'a, O> { + #[doc = "Disable publishing"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(EN_A::DISABLED) + } + #[doc = "Enable publishing"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(EN_A::ENABLED) + } +} +impl R { + #[doc = "Bits 0:7 - DPPI channel that event HFCLKSTARTED will publish to"] + #[inline(always)] + pub fn chidx(&self) -> CHIDX_R { + CHIDX_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&self) -> EN_R { + EN_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:7 - DPPI channel that event HFCLKSTARTED will publish to"] + #[inline(always)] + pub fn chidx(&mut self) -> CHIDX_W<0> { + CHIDX_W::new(self) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&mut self) -> EN_W<31> { + EN_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Publish configuration for event HFCLKSTARTED\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [publish_hfclkstarted](index.html) module"] +pub struct PUBLISH_HFCLKSTARTED_SPEC; +impl crate::RegisterSpec for PUBLISH_HFCLKSTARTED_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [publish_hfclkstarted::R](R) reader structure"] +impl crate::Readable for PUBLISH_HFCLKSTARTED_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [publish_hfclkstarted::W](W) writer structure"] +impl crate::Writable for PUBLISH_HFCLKSTARTED_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PUBLISH_HFCLKSTARTED to value 0"] +impl crate::Resettable for PUBLISH_HFCLKSTARTED_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/clock_ns/publish_lfclkstarted.rs b/pacs/nrf9120-pac/src/clock_ns/publish_lfclkstarted.rs new file mode 100644 index 00000000..1776cb56 --- /dev/null +++ b/pacs/nrf9120-pac/src/clock_ns/publish_lfclkstarted.rs @@ -0,0 +1,141 @@ +#[doc = "Register `PUBLISH_LFCLKSTARTED` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PUBLISH_LFCLKSTARTED` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CHIDX` reader - DPPI channel that event LFCLKSTARTED will publish to"] +pub type CHIDX_R = crate::FieldReader; +#[doc = "Field `CHIDX` writer - DPPI channel that event LFCLKSTARTED will publish to"] +pub type CHIDX_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, PUBLISH_LFCLKSTARTED_SPEC, u8, u8, 8, O>; +#[doc = "Field `EN` reader - "] +pub type EN_R = crate::BitReader; +#[doc = "\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum EN_A { + #[doc = "0: Disable publishing"] + DISABLED = 0, + #[doc = "1: Enable publishing"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: EN_A) -> Self { + variant as u8 != 0 + } +} +impl EN_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EN_A { + match self.bits { + false => EN_A::DISABLED, + true => EN_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == EN_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == EN_A::ENABLED + } +} +#[doc = "Field `EN` writer - "] +pub type EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, PUBLISH_LFCLKSTARTED_SPEC, EN_A, O>; +impl<'a, const O: u8> EN_W<'a, O> { + #[doc = "Disable publishing"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(EN_A::DISABLED) + } + #[doc = "Enable publishing"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(EN_A::ENABLED) + } +} +impl R { + #[doc = "Bits 0:7 - DPPI channel that event LFCLKSTARTED will publish to"] + #[inline(always)] + pub fn chidx(&self) -> CHIDX_R { + CHIDX_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&self) -> EN_R { + EN_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:7 - DPPI channel that event LFCLKSTARTED will publish to"] + #[inline(always)] + pub fn chidx(&mut self) -> CHIDX_W<0> { + CHIDX_W::new(self) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&mut self) -> EN_W<31> { + EN_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Publish configuration for event LFCLKSTARTED\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [publish_lfclkstarted](index.html) module"] +pub struct PUBLISH_LFCLKSTARTED_SPEC; +impl crate::RegisterSpec for PUBLISH_LFCLKSTARTED_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [publish_lfclkstarted::R](R) reader structure"] +impl crate::Readable for PUBLISH_LFCLKSTARTED_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [publish_lfclkstarted::W](W) writer structure"] +impl crate::Writable for PUBLISH_LFCLKSTARTED_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PUBLISH_LFCLKSTARTED to value 0"] +impl crate::Resettable for PUBLISH_LFCLKSTARTED_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/clock_ns/subscribe_hfclkstart.rs b/pacs/nrf9120-pac/src/clock_ns/subscribe_hfclkstart.rs new file mode 100644 index 00000000..98f36a0f --- /dev/null +++ b/pacs/nrf9120-pac/src/clock_ns/subscribe_hfclkstart.rs @@ -0,0 +1,141 @@ +#[doc = "Register `SUBSCRIBE_HFCLKSTART` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SUBSCRIBE_HFCLKSTART` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CHIDX` reader - DPPI channel that task HFCLKSTART will subscribe to"] +pub type CHIDX_R = crate::FieldReader; +#[doc = "Field `CHIDX` writer - DPPI channel that task HFCLKSTART will subscribe to"] +pub type CHIDX_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, SUBSCRIBE_HFCLKSTART_SPEC, u8, u8, 8, O>; +#[doc = "Field `EN` reader - "] +pub type EN_R = crate::BitReader; +#[doc = "\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum EN_A { + #[doc = "0: Disable subscription"] + DISABLED = 0, + #[doc = "1: Enable subscription"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: EN_A) -> Self { + variant as u8 != 0 + } +} +impl EN_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EN_A { + match self.bits { + false => EN_A::DISABLED, + true => EN_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == EN_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == EN_A::ENABLED + } +} +#[doc = "Field `EN` writer - "] +pub type EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, SUBSCRIBE_HFCLKSTART_SPEC, EN_A, O>; +impl<'a, const O: u8> EN_W<'a, O> { + #[doc = "Disable subscription"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(EN_A::DISABLED) + } + #[doc = "Enable subscription"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(EN_A::ENABLED) + } +} +impl R { + #[doc = "Bits 0:7 - DPPI channel that task HFCLKSTART will subscribe to"] + #[inline(always)] + pub fn chidx(&self) -> CHIDX_R { + CHIDX_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&self) -> EN_R { + EN_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:7 - DPPI channel that task HFCLKSTART will subscribe to"] + #[inline(always)] + pub fn chidx(&mut self) -> CHIDX_W<0> { + CHIDX_W::new(self) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&mut self) -> EN_W<31> { + EN_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Subscribe configuration for task HFCLKSTART\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [subscribe_hfclkstart](index.html) module"] +pub struct SUBSCRIBE_HFCLKSTART_SPEC; +impl crate::RegisterSpec for SUBSCRIBE_HFCLKSTART_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [subscribe_hfclkstart::R](R) reader structure"] +impl crate::Readable for SUBSCRIBE_HFCLKSTART_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [subscribe_hfclkstart::W](W) writer structure"] +impl crate::Writable for SUBSCRIBE_HFCLKSTART_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SUBSCRIBE_HFCLKSTART to value 0"] +impl crate::Resettable for SUBSCRIBE_HFCLKSTART_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/clock_ns/subscribe_hfclkstop.rs b/pacs/nrf9120-pac/src/clock_ns/subscribe_hfclkstop.rs new file mode 100644 index 00000000..e65f0f58 --- /dev/null +++ b/pacs/nrf9120-pac/src/clock_ns/subscribe_hfclkstop.rs @@ -0,0 +1,141 @@ +#[doc = "Register `SUBSCRIBE_HFCLKSTOP` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SUBSCRIBE_HFCLKSTOP` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CHIDX` reader - DPPI channel that task HFCLKSTOP will subscribe to"] +pub type CHIDX_R = crate::FieldReader; +#[doc = "Field `CHIDX` writer - DPPI channel that task HFCLKSTOP will subscribe to"] +pub type CHIDX_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, SUBSCRIBE_HFCLKSTOP_SPEC, u8, u8, 8, O>; +#[doc = "Field `EN` reader - "] +pub type EN_R = crate::BitReader; +#[doc = "\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum EN_A { + #[doc = "0: Disable subscription"] + DISABLED = 0, + #[doc = "1: Enable subscription"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: EN_A) -> Self { + variant as u8 != 0 + } +} +impl EN_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EN_A { + match self.bits { + false => EN_A::DISABLED, + true => EN_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == EN_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == EN_A::ENABLED + } +} +#[doc = "Field `EN` writer - "] +pub type EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, SUBSCRIBE_HFCLKSTOP_SPEC, EN_A, O>; +impl<'a, const O: u8> EN_W<'a, O> { + #[doc = "Disable subscription"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(EN_A::DISABLED) + } + #[doc = "Enable subscription"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(EN_A::ENABLED) + } +} +impl R { + #[doc = "Bits 0:7 - DPPI channel that task HFCLKSTOP will subscribe to"] + #[inline(always)] + pub fn chidx(&self) -> CHIDX_R { + CHIDX_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&self) -> EN_R { + EN_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:7 - DPPI channel that task HFCLKSTOP will subscribe to"] + #[inline(always)] + pub fn chidx(&mut self) -> CHIDX_W<0> { + CHIDX_W::new(self) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&mut self) -> EN_W<31> { + EN_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Subscribe configuration for task HFCLKSTOP\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [subscribe_hfclkstop](index.html) module"] +pub struct SUBSCRIBE_HFCLKSTOP_SPEC; +impl crate::RegisterSpec for SUBSCRIBE_HFCLKSTOP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [subscribe_hfclkstop::R](R) reader structure"] +impl crate::Readable for SUBSCRIBE_HFCLKSTOP_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [subscribe_hfclkstop::W](W) writer structure"] +impl crate::Writable for SUBSCRIBE_HFCLKSTOP_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SUBSCRIBE_HFCLKSTOP to value 0"] +impl crate::Resettable for SUBSCRIBE_HFCLKSTOP_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/clock_ns/subscribe_lfclkstart.rs b/pacs/nrf9120-pac/src/clock_ns/subscribe_lfclkstart.rs new file mode 100644 index 00000000..50888661 --- /dev/null +++ b/pacs/nrf9120-pac/src/clock_ns/subscribe_lfclkstart.rs @@ -0,0 +1,141 @@ +#[doc = "Register `SUBSCRIBE_LFCLKSTART` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SUBSCRIBE_LFCLKSTART` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CHIDX` reader - DPPI channel that task LFCLKSTART will subscribe to"] +pub type CHIDX_R = crate::FieldReader; +#[doc = "Field `CHIDX` writer - DPPI channel that task LFCLKSTART will subscribe to"] +pub type CHIDX_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, SUBSCRIBE_LFCLKSTART_SPEC, u8, u8, 8, O>; +#[doc = "Field `EN` reader - "] +pub type EN_R = crate::BitReader; +#[doc = "\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum EN_A { + #[doc = "0: Disable subscription"] + DISABLED = 0, + #[doc = "1: Enable subscription"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: EN_A) -> Self { + variant as u8 != 0 + } +} +impl EN_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EN_A { + match self.bits { + false => EN_A::DISABLED, + true => EN_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == EN_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == EN_A::ENABLED + } +} +#[doc = "Field `EN` writer - "] +pub type EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, SUBSCRIBE_LFCLKSTART_SPEC, EN_A, O>; +impl<'a, const O: u8> EN_W<'a, O> { + #[doc = "Disable subscription"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(EN_A::DISABLED) + } + #[doc = "Enable subscription"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(EN_A::ENABLED) + } +} +impl R { + #[doc = "Bits 0:7 - DPPI channel that task LFCLKSTART will subscribe to"] + #[inline(always)] + pub fn chidx(&self) -> CHIDX_R { + CHIDX_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&self) -> EN_R { + EN_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:7 - DPPI channel that task LFCLKSTART will subscribe to"] + #[inline(always)] + pub fn chidx(&mut self) -> CHIDX_W<0> { + CHIDX_W::new(self) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&mut self) -> EN_W<31> { + EN_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Subscribe configuration for task LFCLKSTART\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [subscribe_lfclkstart](index.html) module"] +pub struct SUBSCRIBE_LFCLKSTART_SPEC; +impl crate::RegisterSpec for SUBSCRIBE_LFCLKSTART_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [subscribe_lfclkstart::R](R) reader structure"] +impl crate::Readable for SUBSCRIBE_LFCLKSTART_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [subscribe_lfclkstart::W](W) writer structure"] +impl crate::Writable for SUBSCRIBE_LFCLKSTART_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SUBSCRIBE_LFCLKSTART to value 0"] +impl crate::Resettable for SUBSCRIBE_LFCLKSTART_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/clock_ns/subscribe_lfclkstop.rs b/pacs/nrf9120-pac/src/clock_ns/subscribe_lfclkstop.rs new file mode 100644 index 00000000..9a06e30f --- /dev/null +++ b/pacs/nrf9120-pac/src/clock_ns/subscribe_lfclkstop.rs @@ -0,0 +1,141 @@ +#[doc = "Register `SUBSCRIBE_LFCLKSTOP` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SUBSCRIBE_LFCLKSTOP` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CHIDX` reader - DPPI channel that task LFCLKSTOP will subscribe to"] +pub type CHIDX_R = crate::FieldReader; +#[doc = "Field `CHIDX` writer - DPPI channel that task LFCLKSTOP will subscribe to"] +pub type CHIDX_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, SUBSCRIBE_LFCLKSTOP_SPEC, u8, u8, 8, O>; +#[doc = "Field `EN` reader - "] +pub type EN_R = crate::BitReader; +#[doc = "\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum EN_A { + #[doc = "0: Disable subscription"] + DISABLED = 0, + #[doc = "1: Enable subscription"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: EN_A) -> Self { + variant as u8 != 0 + } +} +impl EN_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EN_A { + match self.bits { + false => EN_A::DISABLED, + true => EN_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == EN_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == EN_A::ENABLED + } +} +#[doc = "Field `EN` writer - "] +pub type EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, SUBSCRIBE_LFCLKSTOP_SPEC, EN_A, O>; +impl<'a, const O: u8> EN_W<'a, O> { + #[doc = "Disable subscription"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(EN_A::DISABLED) + } + #[doc = "Enable subscription"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(EN_A::ENABLED) + } +} +impl R { + #[doc = "Bits 0:7 - DPPI channel that task LFCLKSTOP will subscribe to"] + #[inline(always)] + pub fn chidx(&self) -> CHIDX_R { + CHIDX_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&self) -> EN_R { + EN_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:7 - DPPI channel that task LFCLKSTOP will subscribe to"] + #[inline(always)] + pub fn chidx(&mut self) -> CHIDX_W<0> { + CHIDX_W::new(self) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&mut self) -> EN_W<31> { + EN_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Subscribe configuration for task LFCLKSTOP\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [subscribe_lfclkstop](index.html) module"] +pub struct SUBSCRIBE_LFCLKSTOP_SPEC; +impl crate::RegisterSpec for SUBSCRIBE_LFCLKSTOP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [subscribe_lfclkstop::R](R) reader structure"] +impl crate::Readable for SUBSCRIBE_LFCLKSTOP_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [subscribe_lfclkstop::W](W) writer structure"] +impl crate::Writable for SUBSCRIBE_LFCLKSTOP_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SUBSCRIBE_LFCLKSTOP to value 0"] +impl crate::Resettable for SUBSCRIBE_LFCLKSTOP_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/clock_ns/tasks_hfclkstart.rs b/pacs/nrf9120-pac/src/clock_ns/tasks_hfclkstart.rs new file mode 100644 index 00000000..2bd5af0f --- /dev/null +++ b/pacs/nrf9120-pac/src/clock_ns/tasks_hfclkstart.rs @@ -0,0 +1,72 @@ +#[doc = "Register `TASKS_HFCLKSTART` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Start HFCLK source\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum TASKS_HFCLKSTART_AW { + #[doc = "1: Trigger task"] + TRIGGER = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TASKS_HFCLKSTART_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TASKS_HFCLKSTART` writer - Start HFCLK source"] +pub type TASKS_HFCLKSTART_W<'a, const O: u8> = + crate::BitWriter<'a, u32, TASKS_HFCLKSTART_SPEC, TASKS_HFCLKSTART_AW, O>; +impl<'a, const O: u8> TASKS_HFCLKSTART_W<'a, O> { + #[doc = "Trigger task"] + #[inline(always)] + pub fn trigger(self) -> &'a mut W { + self.variant(TASKS_HFCLKSTART_AW::TRIGGER) + } +} +impl W { + #[doc = "Bit 0 - Start HFCLK source"] + #[inline(always)] + pub fn tasks_hfclkstart(&mut self) -> TASKS_HFCLKSTART_W<0> { + TASKS_HFCLKSTART_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Start HFCLK source\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tasks_hfclkstart](index.html) module"] +pub struct TASKS_HFCLKSTART_SPEC; +impl crate::RegisterSpec for TASKS_HFCLKSTART_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [tasks_hfclkstart::W](W) writer structure"] +impl crate::Writable for TASKS_HFCLKSTART_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets TASKS_HFCLKSTART to value 0"] +impl crate::Resettable for TASKS_HFCLKSTART_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/clock_ns/tasks_hfclkstop.rs b/pacs/nrf9120-pac/src/clock_ns/tasks_hfclkstop.rs new file mode 100644 index 00000000..1b9710c4 --- /dev/null +++ b/pacs/nrf9120-pac/src/clock_ns/tasks_hfclkstop.rs @@ -0,0 +1,72 @@ +#[doc = "Register `TASKS_HFCLKSTOP` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Stop HFCLK source\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum TASKS_HFCLKSTOP_AW { + #[doc = "1: Trigger task"] + TRIGGER = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TASKS_HFCLKSTOP_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TASKS_HFCLKSTOP` writer - Stop HFCLK source"] +pub type TASKS_HFCLKSTOP_W<'a, const O: u8> = + crate::BitWriter<'a, u32, TASKS_HFCLKSTOP_SPEC, TASKS_HFCLKSTOP_AW, O>; +impl<'a, const O: u8> TASKS_HFCLKSTOP_W<'a, O> { + #[doc = "Trigger task"] + #[inline(always)] + pub fn trigger(self) -> &'a mut W { + self.variant(TASKS_HFCLKSTOP_AW::TRIGGER) + } +} +impl W { + #[doc = "Bit 0 - Stop HFCLK source"] + #[inline(always)] + pub fn tasks_hfclkstop(&mut self) -> TASKS_HFCLKSTOP_W<0> { + TASKS_HFCLKSTOP_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Stop HFCLK source\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tasks_hfclkstop](index.html) module"] +pub struct TASKS_HFCLKSTOP_SPEC; +impl crate::RegisterSpec for TASKS_HFCLKSTOP_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [tasks_hfclkstop::W](W) writer structure"] +impl crate::Writable for TASKS_HFCLKSTOP_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets TASKS_HFCLKSTOP to value 0"] +impl crate::Resettable for TASKS_HFCLKSTOP_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/clock_ns/tasks_lfclkstart.rs b/pacs/nrf9120-pac/src/clock_ns/tasks_lfclkstart.rs new file mode 100644 index 00000000..5baba46f --- /dev/null +++ b/pacs/nrf9120-pac/src/clock_ns/tasks_lfclkstart.rs @@ -0,0 +1,72 @@ +#[doc = "Register `TASKS_LFCLKSTART` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Start LFCLK source\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum TASKS_LFCLKSTART_AW { + #[doc = "1: Trigger task"] + TRIGGER = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TASKS_LFCLKSTART_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TASKS_LFCLKSTART` writer - Start LFCLK source"] +pub type TASKS_LFCLKSTART_W<'a, const O: u8> = + crate::BitWriter<'a, u32, TASKS_LFCLKSTART_SPEC, TASKS_LFCLKSTART_AW, O>; +impl<'a, const O: u8> TASKS_LFCLKSTART_W<'a, O> { + #[doc = "Trigger task"] + #[inline(always)] + pub fn trigger(self) -> &'a mut W { + self.variant(TASKS_LFCLKSTART_AW::TRIGGER) + } +} +impl W { + #[doc = "Bit 0 - Start LFCLK source"] + #[inline(always)] + pub fn tasks_lfclkstart(&mut self) -> TASKS_LFCLKSTART_W<0> { + TASKS_LFCLKSTART_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Start LFCLK source\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tasks_lfclkstart](index.html) module"] +pub struct TASKS_LFCLKSTART_SPEC; +impl crate::RegisterSpec for TASKS_LFCLKSTART_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [tasks_lfclkstart::W](W) writer structure"] +impl crate::Writable for TASKS_LFCLKSTART_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets TASKS_LFCLKSTART to value 0"] +impl crate::Resettable for TASKS_LFCLKSTART_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/clock_ns/tasks_lfclkstop.rs b/pacs/nrf9120-pac/src/clock_ns/tasks_lfclkstop.rs new file mode 100644 index 00000000..8bd38b8c --- /dev/null +++ b/pacs/nrf9120-pac/src/clock_ns/tasks_lfclkstop.rs @@ -0,0 +1,72 @@ +#[doc = "Register `TASKS_LFCLKSTOP` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Stop LFCLK source\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum TASKS_LFCLKSTOP_AW { + #[doc = "1: Trigger task"] + TRIGGER = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TASKS_LFCLKSTOP_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TASKS_LFCLKSTOP` writer - Stop LFCLK source"] +pub type TASKS_LFCLKSTOP_W<'a, const O: u8> = + crate::BitWriter<'a, u32, TASKS_LFCLKSTOP_SPEC, TASKS_LFCLKSTOP_AW, O>; +impl<'a, const O: u8> TASKS_LFCLKSTOP_W<'a, O> { + #[doc = "Trigger task"] + #[inline(always)] + pub fn trigger(self) -> &'a mut W { + self.variant(TASKS_LFCLKSTOP_AW::TRIGGER) + } +} +impl W { + #[doc = "Bit 0 - Stop LFCLK source"] + #[inline(always)] + pub fn tasks_lfclkstop(&mut self) -> TASKS_LFCLKSTOP_W<0> { + TASKS_LFCLKSTOP_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Stop LFCLK source\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tasks_lfclkstop](index.html) module"] +pub struct TASKS_LFCLKSTOP_SPEC; +impl crate::RegisterSpec for TASKS_LFCLKSTOP_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [tasks_lfclkstop::W](W) writer structure"] +impl crate::Writable for TASKS_LFCLKSTOP_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets TASKS_LFCLKSTOP to value 0"] +impl crate::Resettable for TASKS_LFCLKSTOP_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/cryptocell_s.rs b/pacs/nrf9120-pac/src/cryptocell_s.rs new file mode 100644 index 00000000..1cc70ed0 --- /dev/null +++ b/pacs/nrf9120-pac/src/cryptocell_s.rs @@ -0,0 +1,11 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + _reserved0: [u8; 0x0500], + #[doc = "0x500 - Enable CRYPTOCELL subsystem"] + pub enable: ENABLE, +} +#[doc = "ENABLE (rw) register accessor: an alias for `Reg`"] +pub type ENABLE = crate::Reg; +#[doc = "Enable CRYPTOCELL subsystem"] +pub mod enable; diff --git a/pacs/nrf9120-pac/src/cryptocell_s/enable.rs b/pacs/nrf9120-pac/src/cryptocell_s/enable.rs new file mode 100644 index 00000000..12695727 --- /dev/null +++ b/pacs/nrf9120-pac/src/cryptocell_s/enable.rs @@ -0,0 +1,126 @@ +#[doc = "Register `ENABLE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `ENABLE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ENABLE` reader - Enable or disable the CRYPTOCELL subsystem"] +pub type ENABLE_R = crate::BitReader; +#[doc = "Enable or disable the CRYPTOCELL subsystem\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum ENABLE_A { + #[doc = "0: CRYPTOCELL subsystem disabled"] + DISABLED = 0, + #[doc = "1: CRYPTOCELL subsystem enabled."] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: ENABLE_A) -> Self { + variant as u8 != 0 + } +} +impl ENABLE_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> ENABLE_A { + match self.bits { + false => ENABLE_A::DISABLED, + true => ENABLE_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == ENABLE_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == ENABLE_A::ENABLED + } +} +#[doc = "Field `ENABLE` writer - Enable or disable the CRYPTOCELL subsystem"] +pub type ENABLE_W<'a, const O: u8> = crate::BitWriter<'a, u32, ENABLE_SPEC, ENABLE_A, O>; +impl<'a, const O: u8> ENABLE_W<'a, O> { + #[doc = "CRYPTOCELL subsystem disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(ENABLE_A::DISABLED) + } + #[doc = "CRYPTOCELL subsystem enabled."] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(ENABLE_A::ENABLED) + } +} +impl R { + #[doc = "Bit 0 - Enable or disable the CRYPTOCELL subsystem"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new((self.bits & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Enable or disable the CRYPTOCELL subsystem"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W<0> { + ENABLE_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Enable CRYPTOCELL subsystem\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [enable](index.html) module"] +pub struct ENABLE_SPEC; +impl crate::RegisterSpec for ENABLE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [enable::R](R) reader structure"] +impl crate::Readable for ENABLE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [enable::W](W) writer structure"] +impl crate::Writable for ENABLE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets ENABLE to value 0"] +impl crate::Resettable for ENABLE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/ctrl_ap_peri_s.rs b/pacs/nrf9120-pac/src/ctrl_ap_peri_s.rs new file mode 100644 index 00000000..555a2c67 --- /dev/null +++ b/pacs/nrf9120-pac/src/ctrl_ap_peri_s.rs @@ -0,0 +1,20 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + _reserved0: [u8; 0x0400], + #[doc = "0x400..0x488 - Unspecified"] + pub mailbox: MAILBOX, + _reserved1: [u8; 0x78], + #[doc = "0x500..0x508 - Unspecified"] + pub eraseprotect: ERASEPROTECT, +} +#[doc = "Unspecified"] +pub use mailbox::MAILBOX; +#[doc = r"Cluster"] +#[doc = "Unspecified"] +pub mod mailbox; +#[doc = "Unspecified"] +pub use eraseprotect::ERASEPROTECT; +#[doc = r"Cluster"] +#[doc = "Unspecified"] +pub mod eraseprotect; diff --git a/pacs/nrf9120-pac/src/ctrl_ap_peri_s/eraseprotect.rs b/pacs/nrf9120-pac/src/ctrl_ap_peri_s/eraseprotect.rs new file mode 100644 index 00000000..780b1ef1 --- /dev/null +++ b/pacs/nrf9120-pac/src/ctrl_ap_peri_s/eraseprotect.rs @@ -0,0 +1,16 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct ERASEPROTECT { + #[doc = "0x00 - This register locks the ERASEPROTECT.DISABLE register from being written until next reset."] + pub lock: LOCK, + #[doc = "0x04 - This register disables the ERASEPROTECT register and performs an ERASEALL operation."] + pub disable: DISABLE, +} +#[doc = "LOCK (rw) register accessor: an alias for `Reg`"] +pub type LOCK = crate::Reg; +#[doc = "This register locks the ERASEPROTECT.DISABLE register from being written until next reset."] +pub mod lock; +#[doc = "DISABLE (rw) register accessor: an alias for `Reg`"] +pub type DISABLE = crate::Reg; +#[doc = "This register disables the ERASEPROTECT register and performs an ERASEALL operation."] +pub mod disable; diff --git a/pacs/nrf9120-pac/src/ctrl_ap_peri_s/eraseprotect/disable.rs b/pacs/nrf9120-pac/src/ctrl_ap_peri_s/eraseprotect/disable.rs new file mode 100644 index 00000000..9907158d --- /dev/null +++ b/pacs/nrf9120-pac/src/ctrl_ap_peri_s/eraseprotect/disable.rs @@ -0,0 +1,80 @@ +#[doc = "Register `DISABLE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DISABLE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `KEY` reader - The ERASEALL sequence is initiated if the value of the KEY fields are non-zero and the KEY fields match on both the CPU and debugger sides."] +pub type KEY_R = crate::FieldReader; +#[doc = "Field `KEY` writer - The ERASEALL sequence is initiated if the value of the KEY fields are non-zero and the KEY fields match on both the CPU and debugger sides."] +pub type KEY_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DISABLE_SPEC, u32, u32, 32, O>; +impl R { + #[doc = "Bits 0:31 - The ERASEALL sequence is initiated if the value of the KEY fields are non-zero and the KEY fields match on both the CPU and debugger sides."] + #[inline(always)] + pub fn key(&self) -> KEY_R { + KEY_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - The ERASEALL sequence is initiated if the value of the KEY fields are non-zero and the KEY fields match on both the CPU and debugger sides."] + #[inline(always)] + pub fn key(&mut self) -> KEY_W<0> { + KEY_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "This register disables the ERASEPROTECT register and performs an ERASEALL operation.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [disable](index.html) module"] +pub struct DISABLE_SPEC; +impl crate::RegisterSpec for DISABLE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [disable::R](R) reader structure"] +impl crate::Readable for DISABLE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [disable::W](W) writer structure"] +impl crate::Writable for DISABLE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DISABLE to value 0"] +impl crate::Resettable for DISABLE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/ctrl_ap_peri_s/eraseprotect/lock.rs b/pacs/nrf9120-pac/src/ctrl_ap_peri_s/eraseprotect/lock.rs new file mode 100644 index 00000000..abc4a78a --- /dev/null +++ b/pacs/nrf9120-pac/src/ctrl_ap_peri_s/eraseprotect/lock.rs @@ -0,0 +1,126 @@ +#[doc = "Register `LOCK` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `LOCK` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `LOCK` reader - Lock ERASEPROTECT.DISABLE register from being written until next reset"] +pub type LOCK_R = crate::BitReader; +#[doc = "Lock ERASEPROTECT.DISABLE register from being written until next reset\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum LOCK_A { + #[doc = "0: Register ERASEPROTECT.DISABLE is writeable"] + UNLOCKED = 0, + #[doc = "1: Register ERASEPROTECT.DISABLE is read-only"] + LOCKED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: LOCK_A) -> Self { + variant as u8 != 0 + } +} +impl LOCK_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> LOCK_A { + match self.bits { + false => LOCK_A::UNLOCKED, + true => LOCK_A::LOCKED, + } + } + #[doc = "Checks if the value of the field is `UNLOCKED`"] + #[inline(always)] + pub fn is_unlocked(&self) -> bool { + *self == LOCK_A::UNLOCKED + } + #[doc = "Checks if the value of the field is `LOCKED`"] + #[inline(always)] + pub fn is_locked(&self) -> bool { + *self == LOCK_A::LOCKED + } +} +#[doc = "Field `LOCK` writer - Lock ERASEPROTECT.DISABLE register from being written until next reset"] +pub type LOCK_W<'a, const O: u8> = crate::BitWriter<'a, u32, LOCK_SPEC, LOCK_A, O>; +impl<'a, const O: u8> LOCK_W<'a, O> { + #[doc = "Register ERASEPROTECT.DISABLE is writeable"] + #[inline(always)] + pub fn unlocked(self) -> &'a mut W { + self.variant(LOCK_A::UNLOCKED) + } + #[doc = "Register ERASEPROTECT.DISABLE is read-only"] + #[inline(always)] + pub fn locked(self) -> &'a mut W { + self.variant(LOCK_A::LOCKED) + } +} +impl R { + #[doc = "Bit 0 - Lock ERASEPROTECT.DISABLE register from being written until next reset"] + #[inline(always)] + pub fn lock(&self) -> LOCK_R { + LOCK_R::new((self.bits & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Lock ERASEPROTECT.DISABLE register from being written until next reset"] + #[inline(always)] + pub fn lock(&mut self) -> LOCK_W<0> { + LOCK_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "This register locks the ERASEPROTECT.DISABLE register from being written until next reset.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [lock](index.html) module"] +pub struct LOCK_SPEC; +impl crate::RegisterSpec for LOCK_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [lock::R](R) reader structure"] +impl crate::Readable for LOCK_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [lock::W](W) writer structure"] +impl crate::Writable for LOCK_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets LOCK to value 0"] +impl crate::Resettable for LOCK_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/ctrl_ap_peri_s/mailbox.rs b/pacs/nrf9120-pac/src/ctrl_ap_peri_s/mailbox.rs new file mode 100644 index 00000000..514d42d1 --- /dev/null +++ b/pacs/nrf9120-pac/src/ctrl_ap_peri_s/mailbox.rs @@ -0,0 +1,29 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct MAILBOX { + #[doc = "0x00 - Data sent from the debugger to the CPU."] + pub rxdata: RXDATA, + #[doc = "0x04 - This register shows a status that indicates if data sent from the debugger to the CPU has been read."] + pub rxstatus: RXSTATUS, + _reserved2: [u8; 0x78], + #[doc = "0x80 - Data sent from the CPU to the debugger."] + pub txdata: TXDATA, + #[doc = "0x84 - This register shows a status that indicates if the data sent from the CPU to the debugger has been read."] + pub txstatus: TXSTATUS, +} +#[doc = "RXDATA (r) register accessor: an alias for `Reg`"] +pub type RXDATA = crate::Reg; +#[doc = "Data sent from the debugger to the CPU."] +pub mod rxdata; +#[doc = "RXSTATUS (r) register accessor: an alias for `Reg`"] +pub type RXSTATUS = crate::Reg; +#[doc = "This register shows a status that indicates if data sent from the debugger to the CPU has been read."] +pub mod rxstatus; +#[doc = "TXDATA (rw) register accessor: an alias for `Reg`"] +pub type TXDATA = crate::Reg; +#[doc = "Data sent from the CPU to the debugger."] +pub mod txdata; +#[doc = "TXSTATUS (r) register accessor: an alias for `Reg`"] +pub type TXSTATUS = crate::Reg; +#[doc = "This register shows a status that indicates if the data sent from the CPU to the debugger has been read."] +pub mod txstatus; diff --git a/pacs/nrf9120-pac/src/ctrl_ap_peri_s/mailbox/rxdata.rs b/pacs/nrf9120-pac/src/ctrl_ap_peri_s/mailbox/rxdata.rs new file mode 100644 index 00000000..be452935 --- /dev/null +++ b/pacs/nrf9120-pac/src/ctrl_ap_peri_s/mailbox/rxdata.rs @@ -0,0 +1,40 @@ +#[doc = "Register `RXDATA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `RXDATA` reader - Data received from debugger"] +pub type RXDATA_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Data received from debugger"] + #[inline(always)] + pub fn rxdata(&self) -> RXDATA_R { + RXDATA_R::new(self.bits) + } +} +#[doc = "Data sent from the debugger to the CPU.\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rxdata](index.html) module"] +pub struct RXDATA_SPEC; +impl crate::RegisterSpec for RXDATA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [rxdata::R](R) reader structure"] +impl crate::Readable for RXDATA_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets RXDATA to value 0"] +impl crate::Resettable for RXDATA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/ctrl_ap_peri_s/mailbox/rxstatus.rs b/pacs/nrf9120-pac/src/ctrl_ap_peri_s/mailbox/rxstatus.rs new file mode 100644 index 00000000..4d0bd7ae --- /dev/null +++ b/pacs/nrf9120-pac/src/ctrl_ap_peri_s/mailbox/rxstatus.rs @@ -0,0 +1,74 @@ +#[doc = "Register `RXSTATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `RXSTATUS` reader - Status of data in register RXDATA"] +pub type RXSTATUS_R = crate::BitReader; +#[doc = "Status of data in register RXDATA\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RXSTATUS_A { + #[doc = "0: No data pending in register RXDATA"] + NO_DATA_PENDING = 0, + #[doc = "1: Data pending in register RXDATA"] + DATA_PENDING = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RXSTATUS_A) -> Self { + variant as u8 != 0 + } +} +impl RXSTATUS_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RXSTATUS_A { + match self.bits { + false => RXSTATUS_A::NO_DATA_PENDING, + true => RXSTATUS_A::DATA_PENDING, + } + } + #[doc = "Checks if the value of the field is `NO_DATA_PENDING`"] + #[inline(always)] + pub fn is_no_data_pending(&self) -> bool { + *self == RXSTATUS_A::NO_DATA_PENDING + } + #[doc = "Checks if the value of the field is `DATA_PENDING`"] + #[inline(always)] + pub fn is_data_pending(&self) -> bool { + *self == RXSTATUS_A::DATA_PENDING + } +} +impl R { + #[doc = "Bit 0 - Status of data in register RXDATA"] + #[inline(always)] + pub fn rxstatus(&self) -> RXSTATUS_R { + RXSTATUS_R::new((self.bits & 1) != 0) + } +} +#[doc = "This register shows a status that indicates if data sent from the debugger to the CPU has been read.\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rxstatus](index.html) module"] +pub struct RXSTATUS_SPEC; +impl crate::RegisterSpec for RXSTATUS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [rxstatus::R](R) reader structure"] +impl crate::Readable for RXSTATUS_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets RXSTATUS to value 0"] +impl crate::Resettable for RXSTATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/ctrl_ap_peri_s/mailbox/txdata.rs b/pacs/nrf9120-pac/src/ctrl_ap_peri_s/mailbox/txdata.rs new file mode 100644 index 00000000..bedd68a2 --- /dev/null +++ b/pacs/nrf9120-pac/src/ctrl_ap_peri_s/mailbox/txdata.rs @@ -0,0 +1,80 @@ +#[doc = "Register `TXDATA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `TXDATA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `TXDATA` reader - Data sent to debugger"] +pub type TXDATA_R = crate::FieldReader; +#[doc = "Field `TXDATA` writer - Data sent to debugger"] +pub type TXDATA_W<'a, const O: u8> = crate::FieldWriter<'a, u32, TXDATA_SPEC, u32, u32, 32, O>; +impl R { + #[doc = "Bits 0:31 - Data sent to debugger"] + #[inline(always)] + pub fn txdata(&self) -> TXDATA_R { + TXDATA_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Data sent to debugger"] + #[inline(always)] + pub fn txdata(&mut self) -> TXDATA_W<0> { + TXDATA_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Data sent from the CPU to the debugger.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [txdata](index.html) module"] +pub struct TXDATA_SPEC; +impl crate::RegisterSpec for TXDATA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [txdata::R](R) reader structure"] +impl crate::Readable for TXDATA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [txdata::W](W) writer structure"] +impl crate::Writable for TXDATA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets TXDATA to value 0"] +impl crate::Resettable for TXDATA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/ctrl_ap_peri_s/mailbox/txstatus.rs b/pacs/nrf9120-pac/src/ctrl_ap_peri_s/mailbox/txstatus.rs new file mode 100644 index 00000000..86f49e84 --- /dev/null +++ b/pacs/nrf9120-pac/src/ctrl_ap_peri_s/mailbox/txstatus.rs @@ -0,0 +1,74 @@ +#[doc = "Register `TXSTATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `TXSTATUS` reader - Status of data in register TXDATA"] +pub type TXSTATUS_R = crate::BitReader; +#[doc = "Status of data in register TXDATA\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum TXSTATUS_A { + #[doc = "0: No data pending in register TXDATA"] + NO_DATA_PENDING = 0, + #[doc = "1: Data pending in register TXDATA"] + DATA_PENDING = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TXSTATUS_A) -> Self { + variant as u8 != 0 + } +} +impl TXSTATUS_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> TXSTATUS_A { + match self.bits { + false => TXSTATUS_A::NO_DATA_PENDING, + true => TXSTATUS_A::DATA_PENDING, + } + } + #[doc = "Checks if the value of the field is `NO_DATA_PENDING`"] + #[inline(always)] + pub fn is_no_data_pending(&self) -> bool { + *self == TXSTATUS_A::NO_DATA_PENDING + } + #[doc = "Checks if the value of the field is `DATA_PENDING`"] + #[inline(always)] + pub fn is_data_pending(&self) -> bool { + *self == TXSTATUS_A::DATA_PENDING + } +} +impl R { + #[doc = "Bit 0 - Status of data in register TXDATA"] + #[inline(always)] + pub fn txstatus(&self) -> TXSTATUS_R { + TXSTATUS_R::new((self.bits & 1) != 0) + } +} +#[doc = "This register shows a status that indicates if the data sent from the CPU to the debugger has been read.\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [txstatus](index.html) module"] +pub struct TXSTATUS_SPEC; +impl crate::RegisterSpec for TXSTATUS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [txstatus::R](R) reader structure"] +impl crate::Readable for TXSTATUS_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets TXSTATUS to value 0"] +impl crate::Resettable for TXSTATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/dppic_ns.rs b/pacs/nrf9120-pac/src/dppic_ns.rs new file mode 100644 index 00000000..8c13811d --- /dev/null +++ b/pacs/nrf9120-pac/src/dppic_ns.rs @@ -0,0 +1,45 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00..0x30 - Channel group tasks"] + pub tasks_chg: [TASKS_CHG; 6], + _reserved1: [u8; 0x50], + #[doc = "0x80..0xb0 - Subscribe configuration for tasks"] + pub subscribe_chg: [SUBSCRIBE_CHG; 6], + _reserved2: [u8; 0x0450], + #[doc = "0x500 - Channel enable register"] + pub chen: CHEN, + #[doc = "0x504 - Channel enable set register"] + pub chenset: CHENSET, + #[doc = "0x508 - Channel enable clear register"] + pub chenclr: CHENCLR, + _reserved5: [u8; 0x02f4], + #[doc = "0x800..0x818 - Description collection: Channel group n Note: Writes to this register are ignored if either SUBSCRIBE_CHG\\[n\\].EN or SUBSCRIBE_CHG\\[n\\].DIS is enabled"] + pub chg: [CHG; 6], +} +#[doc = "Channel group tasks"] +pub use tasks_chg::TASKS_CHG; +#[doc = r"Cluster"] +#[doc = "Channel group tasks"] +pub mod tasks_chg; +#[doc = "Subscribe configuration for tasks"] +pub use subscribe_chg::SUBSCRIBE_CHG; +#[doc = r"Cluster"] +#[doc = "Subscribe configuration for tasks"] +pub mod subscribe_chg; +#[doc = "CHEN (rw) register accessor: an alias for `Reg`"] +pub type CHEN = crate::Reg; +#[doc = "Channel enable register"] +pub mod chen; +#[doc = "CHENSET (rw) register accessor: an alias for `Reg`"] +pub type CHENSET = crate::Reg; +#[doc = "Channel enable set register"] +pub mod chenset; +#[doc = "CHENCLR (rw) register accessor: an alias for `Reg`"] +pub type CHENCLR = crate::Reg; +#[doc = "Channel enable clear register"] +pub mod chenclr; +#[doc = "CHG (rw) register accessor: an alias for `Reg`"] +pub type CHG = crate::Reg; +#[doc = "Description collection: Channel group n Note: Writes to this register are ignored if either SUBSCRIBE_CHG\\[n\\].EN or SUBSCRIBE_CHG\\[n\\].DIS is enabled"] +pub mod chg; diff --git a/pacs/nrf9120-pac/src/dppic_ns/chen.rs b/pacs/nrf9120-pac/src/dppic_ns/chen.rs new file mode 100644 index 00000000..b4c60aaa --- /dev/null +++ b/pacs/nrf9120-pac/src/dppic_ns/chen.rs @@ -0,0 +1,1026 @@ +#[doc = "Register `CHEN` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CHEN` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CH0` reader - Enable or disable channel 0"] +pub type CH0_R = crate::BitReader; +#[doc = "Enable or disable channel 0\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CH0_A { + #[doc = "0: Disable channel"] + DISABLED = 0, + #[doc = "1: Enable channel"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CH0_A) -> Self { + variant as u8 != 0 + } +} +impl CH0_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CH0_A { + match self.bits { + false => CH0_A::DISABLED, + true => CH0_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == CH0_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == CH0_A::ENABLED + } +} +#[doc = "Field `CH0` writer - Enable or disable channel 0"] +pub type CH0_W<'a, const O: u8> = crate::BitWriter<'a, u32, CHEN_SPEC, CH0_A, O>; +impl<'a, const O: u8> CH0_W<'a, O> { + #[doc = "Disable channel"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(CH0_A::DISABLED) + } + #[doc = "Enable channel"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(CH0_A::ENABLED) + } +} +#[doc = "Field `CH1` reader - Enable or disable channel 1"] +pub type CH1_R = crate::BitReader; +#[doc = "Enable or disable channel 1\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CH1_A { + #[doc = "0: Disable channel"] + DISABLED = 0, + #[doc = "1: Enable channel"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CH1_A) -> Self { + variant as u8 != 0 + } +} +impl CH1_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CH1_A { + match self.bits { + false => CH1_A::DISABLED, + true => CH1_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == CH1_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == CH1_A::ENABLED + } +} +#[doc = "Field `CH1` writer - Enable or disable channel 1"] +pub type CH1_W<'a, const O: u8> = crate::BitWriter<'a, u32, CHEN_SPEC, CH1_A, O>; +impl<'a, const O: u8> CH1_W<'a, O> { + #[doc = "Disable channel"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(CH1_A::DISABLED) + } + #[doc = "Enable channel"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(CH1_A::ENABLED) + } +} +#[doc = "Field `CH2` reader - Enable or disable channel 2"] +pub type CH2_R = crate::BitReader; +#[doc = "Enable or disable channel 2\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CH2_A { + #[doc = "0: Disable channel"] + DISABLED = 0, + #[doc = "1: Enable channel"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CH2_A) -> Self { + variant as u8 != 0 + } +} +impl CH2_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CH2_A { + match self.bits { + false => CH2_A::DISABLED, + true => CH2_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == CH2_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == CH2_A::ENABLED + } +} +#[doc = "Field `CH2` writer - Enable or disable channel 2"] +pub type CH2_W<'a, const O: u8> = crate::BitWriter<'a, u32, CHEN_SPEC, CH2_A, O>; +impl<'a, const O: u8> CH2_W<'a, O> { + #[doc = "Disable channel"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(CH2_A::DISABLED) + } + #[doc = "Enable channel"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(CH2_A::ENABLED) + } +} +#[doc = "Field `CH3` reader - Enable or disable channel 3"] +pub type CH3_R = crate::BitReader; +#[doc = "Enable or disable channel 3\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CH3_A { + #[doc = "0: Disable channel"] + DISABLED = 0, + #[doc = "1: Enable channel"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CH3_A) -> Self { + variant as u8 != 0 + } +} +impl CH3_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CH3_A { + match self.bits { + false => CH3_A::DISABLED, + true => CH3_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == CH3_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == CH3_A::ENABLED + } +} +#[doc = "Field `CH3` writer - Enable or disable channel 3"] +pub type CH3_W<'a, const O: u8> = crate::BitWriter<'a, u32, CHEN_SPEC, CH3_A, O>; +impl<'a, const O: u8> CH3_W<'a, O> { + #[doc = "Disable channel"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(CH3_A::DISABLED) + } + #[doc = "Enable channel"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(CH3_A::ENABLED) + } +} +#[doc = "Field `CH4` reader - Enable or disable channel 4"] +pub type CH4_R = crate::BitReader; +#[doc = "Enable or disable channel 4\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CH4_A { + #[doc = "0: Disable channel"] + DISABLED = 0, + #[doc = "1: Enable channel"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CH4_A) -> Self { + variant as u8 != 0 + } +} +impl CH4_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CH4_A { + match self.bits { + false => CH4_A::DISABLED, + true => CH4_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == CH4_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == CH4_A::ENABLED + } +} +#[doc = "Field `CH4` writer - Enable or disable channel 4"] +pub type CH4_W<'a, const O: u8> = crate::BitWriter<'a, u32, CHEN_SPEC, CH4_A, O>; +impl<'a, const O: u8> CH4_W<'a, O> { + #[doc = "Disable channel"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(CH4_A::DISABLED) + } + #[doc = "Enable channel"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(CH4_A::ENABLED) + } +} +#[doc = "Field `CH5` reader - Enable or disable channel 5"] +pub type CH5_R = crate::BitReader; +#[doc = "Enable or disable channel 5\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CH5_A { + #[doc = "0: Disable channel"] + DISABLED = 0, + #[doc = "1: Enable channel"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CH5_A) -> Self { + variant as u8 != 0 + } +} +impl CH5_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CH5_A { + match self.bits { + false => CH5_A::DISABLED, + true => CH5_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == CH5_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == CH5_A::ENABLED + } +} +#[doc = "Field `CH5` writer - Enable or disable channel 5"] +pub type CH5_W<'a, const O: u8> = crate::BitWriter<'a, u32, CHEN_SPEC, CH5_A, O>; +impl<'a, const O: u8> CH5_W<'a, O> { + #[doc = "Disable channel"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(CH5_A::DISABLED) + } + #[doc = "Enable channel"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(CH5_A::ENABLED) + } +} +#[doc = "Field `CH6` reader - Enable or disable channel 6"] +pub type CH6_R = crate::BitReader; +#[doc = "Enable or disable channel 6\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CH6_A { + #[doc = "0: Disable channel"] + DISABLED = 0, + #[doc = "1: Enable channel"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CH6_A) -> Self { + variant as u8 != 0 + } +} +impl CH6_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CH6_A { + match self.bits { + false => CH6_A::DISABLED, + true => CH6_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == CH6_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == CH6_A::ENABLED + } +} +#[doc = "Field `CH6` writer - Enable or disable channel 6"] +pub type CH6_W<'a, const O: u8> = crate::BitWriter<'a, u32, CHEN_SPEC, CH6_A, O>; +impl<'a, const O: u8> CH6_W<'a, O> { + #[doc = "Disable channel"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(CH6_A::DISABLED) + } + #[doc = "Enable channel"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(CH6_A::ENABLED) + } +} +#[doc = "Field `CH7` reader - Enable or disable channel 7"] +pub type CH7_R = crate::BitReader; +#[doc = "Enable or disable channel 7\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CH7_A { + #[doc = "0: Disable channel"] + DISABLED = 0, + #[doc = "1: Enable channel"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CH7_A) -> Self { + variant as u8 != 0 + } +} +impl CH7_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CH7_A { + match self.bits { + false => CH7_A::DISABLED, + true => CH7_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == CH7_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == CH7_A::ENABLED + } +} +#[doc = "Field `CH7` writer - Enable or disable channel 7"] +pub type CH7_W<'a, const O: u8> = crate::BitWriter<'a, u32, CHEN_SPEC, CH7_A, O>; +impl<'a, const O: u8> CH7_W<'a, O> { + #[doc = "Disable channel"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(CH7_A::DISABLED) + } + #[doc = "Enable channel"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(CH7_A::ENABLED) + } +} +#[doc = "Field `CH8` reader - Enable or disable channel 8"] +pub type CH8_R = crate::BitReader; +#[doc = "Enable or disable channel 8\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CH8_A { + #[doc = "0: Disable channel"] + DISABLED = 0, + #[doc = "1: Enable channel"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CH8_A) -> Self { + variant as u8 != 0 + } +} +impl CH8_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CH8_A { + match self.bits { + false => CH8_A::DISABLED, + true => CH8_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == CH8_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == CH8_A::ENABLED + } +} +#[doc = "Field `CH8` writer - Enable or disable channel 8"] +pub type CH8_W<'a, const O: u8> = crate::BitWriter<'a, u32, CHEN_SPEC, CH8_A, O>; +impl<'a, const O: u8> CH8_W<'a, O> { + #[doc = "Disable channel"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(CH8_A::DISABLED) + } + #[doc = "Enable channel"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(CH8_A::ENABLED) + } +} +#[doc = "Field `CH9` reader - Enable or disable channel 9"] +pub type CH9_R = crate::BitReader; +#[doc = "Enable or disable channel 9\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CH9_A { + #[doc = "0: Disable channel"] + DISABLED = 0, + #[doc = "1: Enable channel"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CH9_A) -> Self { + variant as u8 != 0 + } +} +impl CH9_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CH9_A { + match self.bits { + false => CH9_A::DISABLED, + true => CH9_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == CH9_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == CH9_A::ENABLED + } +} +#[doc = "Field `CH9` writer - Enable or disable channel 9"] +pub type CH9_W<'a, const O: u8> = crate::BitWriter<'a, u32, CHEN_SPEC, CH9_A, O>; +impl<'a, const O: u8> CH9_W<'a, O> { + #[doc = "Disable channel"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(CH9_A::DISABLED) + } + #[doc = "Enable channel"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(CH9_A::ENABLED) + } +} +#[doc = "Field `CH10` reader - Enable or disable channel 10"] +pub type CH10_R = crate::BitReader; +#[doc = "Enable or disable channel 10\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CH10_A { + #[doc = "0: Disable channel"] + DISABLED = 0, + #[doc = "1: Enable channel"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CH10_A) -> Self { + variant as u8 != 0 + } +} +impl CH10_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CH10_A { + match self.bits { + false => CH10_A::DISABLED, + true => CH10_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == CH10_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == CH10_A::ENABLED + } +} +#[doc = "Field `CH10` writer - Enable or disable channel 10"] +pub type CH10_W<'a, const O: u8> = crate::BitWriter<'a, u32, CHEN_SPEC, CH10_A, O>; +impl<'a, const O: u8> CH10_W<'a, O> { + #[doc = "Disable channel"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(CH10_A::DISABLED) + } + #[doc = "Enable channel"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(CH10_A::ENABLED) + } +} +#[doc = "Field `CH11` reader - Enable or disable channel 11"] +pub type CH11_R = crate::BitReader; +#[doc = "Enable or disable channel 11\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CH11_A { + #[doc = "0: Disable channel"] + DISABLED = 0, + #[doc = "1: Enable channel"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CH11_A) -> Self { + variant as u8 != 0 + } +} +impl CH11_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CH11_A { + match self.bits { + false => CH11_A::DISABLED, + true => CH11_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == CH11_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == CH11_A::ENABLED + } +} +#[doc = "Field `CH11` writer - Enable or disable channel 11"] +pub type CH11_W<'a, const O: u8> = crate::BitWriter<'a, u32, CHEN_SPEC, CH11_A, O>; +impl<'a, const O: u8> CH11_W<'a, O> { + #[doc = "Disable channel"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(CH11_A::DISABLED) + } + #[doc = "Enable channel"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(CH11_A::ENABLED) + } +} +#[doc = "Field `CH12` reader - Enable or disable channel 12"] +pub type CH12_R = crate::BitReader; +#[doc = "Enable or disable channel 12\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CH12_A { + #[doc = "0: Disable channel"] + DISABLED = 0, + #[doc = "1: Enable channel"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CH12_A) -> Self { + variant as u8 != 0 + } +} +impl CH12_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CH12_A { + match self.bits { + false => CH12_A::DISABLED, + true => CH12_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == CH12_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == CH12_A::ENABLED + } +} +#[doc = "Field `CH12` writer - Enable or disable channel 12"] +pub type CH12_W<'a, const O: u8> = crate::BitWriter<'a, u32, CHEN_SPEC, CH12_A, O>; +impl<'a, const O: u8> CH12_W<'a, O> { + #[doc = "Disable channel"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(CH12_A::DISABLED) + } + #[doc = "Enable channel"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(CH12_A::ENABLED) + } +} +#[doc = "Field `CH13` reader - Enable or disable channel 13"] +pub type CH13_R = crate::BitReader; +#[doc = "Enable or disable channel 13\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CH13_A { + #[doc = "0: Disable channel"] + DISABLED = 0, + #[doc = "1: Enable channel"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CH13_A) -> Self { + variant as u8 != 0 + } +} +impl CH13_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CH13_A { + match self.bits { + false => CH13_A::DISABLED, + true => CH13_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == CH13_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == CH13_A::ENABLED + } +} +#[doc = "Field `CH13` writer - Enable or disable channel 13"] +pub type CH13_W<'a, const O: u8> = crate::BitWriter<'a, u32, CHEN_SPEC, CH13_A, O>; +impl<'a, const O: u8> CH13_W<'a, O> { + #[doc = "Disable channel"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(CH13_A::DISABLED) + } + #[doc = "Enable channel"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(CH13_A::ENABLED) + } +} +#[doc = "Field `CH14` reader - Enable or disable channel 14"] +pub type CH14_R = crate::BitReader; +#[doc = "Enable or disable channel 14\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CH14_A { + #[doc = "0: Disable channel"] + DISABLED = 0, + #[doc = "1: Enable channel"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CH14_A) -> Self { + variant as u8 != 0 + } +} +impl CH14_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CH14_A { + match self.bits { + false => CH14_A::DISABLED, + true => CH14_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == CH14_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == CH14_A::ENABLED + } +} +#[doc = "Field `CH14` writer - Enable or disable channel 14"] +pub type CH14_W<'a, const O: u8> = crate::BitWriter<'a, u32, CHEN_SPEC, CH14_A, O>; +impl<'a, const O: u8> CH14_W<'a, O> { + #[doc = "Disable channel"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(CH14_A::DISABLED) + } + #[doc = "Enable channel"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(CH14_A::ENABLED) + } +} +#[doc = "Field `CH15` reader - Enable or disable channel 15"] +pub type CH15_R = crate::BitReader; +#[doc = "Enable or disable channel 15\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CH15_A { + #[doc = "0: Disable channel"] + DISABLED = 0, + #[doc = "1: Enable channel"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CH15_A) -> Self { + variant as u8 != 0 + } +} +impl CH15_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CH15_A { + match self.bits { + false => CH15_A::DISABLED, + true => CH15_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == CH15_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == CH15_A::ENABLED + } +} +#[doc = "Field `CH15` writer - Enable or disable channel 15"] +pub type CH15_W<'a, const O: u8> = crate::BitWriter<'a, u32, CHEN_SPEC, CH15_A, O>; +impl<'a, const O: u8> CH15_W<'a, O> { + #[doc = "Disable channel"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(CH15_A::DISABLED) + } + #[doc = "Enable channel"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(CH15_A::ENABLED) + } +} +impl R { + #[doc = "Bit 0 - Enable or disable channel 0"] + #[inline(always)] + pub fn ch0(&self) -> CH0_R { + CH0_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Enable or disable channel 1"] + #[inline(always)] + pub fn ch1(&self) -> CH1_R { + CH1_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Enable or disable channel 2"] + #[inline(always)] + pub fn ch2(&self) -> CH2_R { + CH2_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Enable or disable channel 3"] + #[inline(always)] + pub fn ch3(&self) -> CH3_R { + CH3_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Enable or disable channel 4"] + #[inline(always)] + pub fn ch4(&self) -> CH4_R { + CH4_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Enable or disable channel 5"] + #[inline(always)] + pub fn ch5(&self) -> CH5_R { + CH5_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Enable or disable channel 6"] + #[inline(always)] + pub fn ch6(&self) -> CH6_R { + CH6_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Enable or disable channel 7"] + #[inline(always)] + pub fn ch7(&self) -> CH7_R { + CH7_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Enable or disable channel 8"] + #[inline(always)] + pub fn ch8(&self) -> CH8_R { + CH8_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Enable or disable channel 9"] + #[inline(always)] + pub fn ch9(&self) -> CH9_R { + CH9_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Enable or disable channel 10"] + #[inline(always)] + pub fn ch10(&self) -> CH10_R { + CH10_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Enable or disable channel 11"] + #[inline(always)] + pub fn ch11(&self) -> CH11_R { + CH11_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Enable or disable channel 12"] + #[inline(always)] + pub fn ch12(&self) -> CH12_R { + CH12_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Enable or disable channel 13"] + #[inline(always)] + pub fn ch13(&self) -> CH13_R { + CH13_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Enable or disable channel 14"] + #[inline(always)] + pub fn ch14(&self) -> CH14_R { + CH14_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Enable or disable channel 15"] + #[inline(always)] + pub fn ch15(&self) -> CH15_R { + CH15_R::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Enable or disable channel 0"] + #[inline(always)] + pub fn ch0(&mut self) -> CH0_W<0> { + CH0_W::new(self) + } + #[doc = "Bit 1 - Enable or disable channel 1"] + #[inline(always)] + pub fn ch1(&mut self) -> CH1_W<1> { + CH1_W::new(self) + } + #[doc = "Bit 2 - Enable or disable channel 2"] + #[inline(always)] + pub fn ch2(&mut self) -> CH2_W<2> { + CH2_W::new(self) + } + #[doc = "Bit 3 - Enable or disable channel 3"] + #[inline(always)] + pub fn ch3(&mut self) -> CH3_W<3> { + CH3_W::new(self) + } + #[doc = "Bit 4 - Enable or disable channel 4"] + #[inline(always)] + pub fn ch4(&mut self) -> CH4_W<4> { + CH4_W::new(self) + } + #[doc = "Bit 5 - Enable or disable channel 5"] + #[inline(always)] + pub fn ch5(&mut self) -> CH5_W<5> { + CH5_W::new(self) + } + #[doc = "Bit 6 - Enable or disable channel 6"] + #[inline(always)] + pub fn ch6(&mut self) -> CH6_W<6> { + CH6_W::new(self) + } + #[doc = "Bit 7 - Enable or disable channel 7"] + #[inline(always)] + pub fn ch7(&mut self) -> CH7_W<7> { + CH7_W::new(self) + } + #[doc = "Bit 8 - Enable or disable channel 8"] + #[inline(always)] + pub fn ch8(&mut self) -> CH8_W<8> { + CH8_W::new(self) + } + #[doc = "Bit 9 - Enable or disable channel 9"] + #[inline(always)] + pub fn ch9(&mut self) -> CH9_W<9> { + CH9_W::new(self) + } + #[doc = "Bit 10 - Enable or disable channel 10"] + #[inline(always)] + pub fn ch10(&mut self) -> CH10_W<10> { + CH10_W::new(self) + } + #[doc = "Bit 11 - Enable or disable channel 11"] + #[inline(always)] + pub fn ch11(&mut self) -> CH11_W<11> { + CH11_W::new(self) + } + #[doc = "Bit 12 - Enable or disable channel 12"] + #[inline(always)] + pub fn ch12(&mut self) -> CH12_W<12> { + CH12_W::new(self) + } + #[doc = "Bit 13 - Enable or disable channel 13"] + #[inline(always)] + pub fn ch13(&mut self) -> CH13_W<13> { + CH13_W::new(self) + } + #[doc = "Bit 14 - Enable or disable channel 14"] + #[inline(always)] + pub fn ch14(&mut self) -> CH14_W<14> { + CH14_W::new(self) + } + #[doc = "Bit 15 - Enable or disable channel 15"] + #[inline(always)] + pub fn ch15(&mut self) -> CH15_W<15> { + CH15_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Channel enable register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [chen](index.html) module"] +pub struct CHEN_SPEC; +impl crate::RegisterSpec for CHEN_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [chen::R](R) reader structure"] +impl crate::Readable for CHEN_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [chen::W](W) writer structure"] +impl crate::Writable for CHEN_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CHEN to value 0"] +impl crate::Resettable for CHEN_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/dppic_ns/chenclr.rs b/pacs/nrf9120-pac/src/dppic_ns/chenclr.rs new file mode 100644 index 00000000..db0d34cd --- /dev/null +++ b/pacs/nrf9120-pac/src/dppic_ns/chenclr.rs @@ -0,0 +1,1138 @@ +#[doc = "Register `CHENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CHENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CH0` reader - Channel 0 enable clear register. Writing 0 has no effect."] +pub type CH0_R = crate::BitReader; +#[doc = "Channel 0 enable clear register. Writing 0 has no effect.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CH0_A { + #[doc = "0: Read: Channel disabled"] + DISABLED = 0, + #[doc = "1: Read: Channel enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CH0_A) -> Self { + variant as u8 != 0 + } +} +impl CH0_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CH0_A { + match self.bits { + false => CH0_A::DISABLED, + true => CH0_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == CH0_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == CH0_A::ENABLED + } +} +#[doc = "Channel 0 enable clear register. Writing 0 has no effect.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CH0_AW { + #[doc = "1: Write: Disable channel"] + CLEAR = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CH0_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CH0` writer - Channel 0 enable clear register. Writing 0 has no effect."] +pub type CH0_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, CHENCLR_SPEC, CH0_AW, O>; +impl<'a, const O: u8> CH0_W<'a, O> { + #[doc = "Write: Disable channel"] + #[inline(always)] + pub fn clear(self) -> &'a mut W { + self.variant(CH0_AW::CLEAR) + } +} +#[doc = "Field `CH1` reader - Channel 1 enable clear register. Writing 0 has no effect."] +pub type CH1_R = crate::BitReader; +#[doc = "Channel 1 enable clear register. Writing 0 has no effect.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CH1_A { + #[doc = "0: Read: Channel disabled"] + DISABLED = 0, + #[doc = "1: Read: Channel enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CH1_A) -> Self { + variant as u8 != 0 + } +} +impl CH1_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CH1_A { + match self.bits { + false => CH1_A::DISABLED, + true => CH1_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == CH1_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == CH1_A::ENABLED + } +} +#[doc = "Channel 1 enable clear register. Writing 0 has no effect.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CH1_AW { + #[doc = "1: Write: Disable channel"] + CLEAR = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CH1_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CH1` writer - Channel 1 enable clear register. Writing 0 has no effect."] +pub type CH1_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, CHENCLR_SPEC, CH1_AW, O>; +impl<'a, const O: u8> CH1_W<'a, O> { + #[doc = "Write: Disable channel"] + #[inline(always)] + pub fn clear(self) -> &'a mut W { + self.variant(CH1_AW::CLEAR) + } +} +#[doc = "Field `CH2` reader - Channel 2 enable clear register. Writing 0 has no effect."] +pub type CH2_R = crate::BitReader; +#[doc = "Channel 2 enable clear register. Writing 0 has no effect.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CH2_A { + #[doc = "0: Read: Channel disabled"] + DISABLED = 0, + #[doc = "1: Read: Channel enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CH2_A) -> Self { + variant as u8 != 0 + } +} +impl CH2_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CH2_A { + match self.bits { + false => CH2_A::DISABLED, + true => CH2_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == CH2_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == CH2_A::ENABLED + } +} +#[doc = "Channel 2 enable clear register. Writing 0 has no effect.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CH2_AW { + #[doc = "1: Write: Disable channel"] + CLEAR = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CH2_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CH2` writer - Channel 2 enable clear register. Writing 0 has no effect."] +pub type CH2_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, CHENCLR_SPEC, CH2_AW, O>; +impl<'a, const O: u8> CH2_W<'a, O> { + #[doc = "Write: Disable channel"] + #[inline(always)] + pub fn clear(self) -> &'a mut W { + self.variant(CH2_AW::CLEAR) + } +} +#[doc = "Field `CH3` reader - Channel 3 enable clear register. Writing 0 has no effect."] +pub type CH3_R = crate::BitReader; +#[doc = "Channel 3 enable clear register. Writing 0 has no effect.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CH3_A { + #[doc = "0: Read: Channel disabled"] + DISABLED = 0, + #[doc = "1: Read: Channel enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CH3_A) -> Self { + variant as u8 != 0 + } +} +impl CH3_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CH3_A { + match self.bits { + false => CH3_A::DISABLED, + true => CH3_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == CH3_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == CH3_A::ENABLED + } +} +#[doc = "Channel 3 enable clear register. Writing 0 has no effect.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CH3_AW { + #[doc = "1: Write: Disable channel"] + CLEAR = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CH3_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CH3` writer - Channel 3 enable clear register. Writing 0 has no effect."] +pub type CH3_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, CHENCLR_SPEC, CH3_AW, O>; +impl<'a, const O: u8> CH3_W<'a, O> { + #[doc = "Write: Disable channel"] + #[inline(always)] + pub fn clear(self) -> &'a mut W { + self.variant(CH3_AW::CLEAR) + } +} +#[doc = "Field `CH4` reader - Channel 4 enable clear register. Writing 0 has no effect."] +pub type CH4_R = crate::BitReader; +#[doc = "Channel 4 enable clear register. Writing 0 has no effect.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CH4_A { + #[doc = "0: Read: Channel disabled"] + DISABLED = 0, + #[doc = "1: Read: Channel enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CH4_A) -> Self { + variant as u8 != 0 + } +} +impl CH4_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CH4_A { + match self.bits { + false => CH4_A::DISABLED, + true => CH4_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == CH4_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == CH4_A::ENABLED + } +} +#[doc = "Channel 4 enable clear register. Writing 0 has no effect.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CH4_AW { + #[doc = "1: Write: Disable channel"] + CLEAR = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CH4_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CH4` writer - Channel 4 enable clear register. Writing 0 has no effect."] +pub type CH4_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, CHENCLR_SPEC, CH4_AW, O>; +impl<'a, const O: u8> CH4_W<'a, O> { + #[doc = "Write: Disable channel"] + #[inline(always)] + pub fn clear(self) -> &'a mut W { + self.variant(CH4_AW::CLEAR) + } +} +#[doc = "Field `CH5` reader - Channel 5 enable clear register. Writing 0 has no effect."] +pub type CH5_R = crate::BitReader; +#[doc = "Channel 5 enable clear register. Writing 0 has no effect.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CH5_A { + #[doc = "0: Read: Channel disabled"] + DISABLED = 0, + #[doc = "1: Read: Channel enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CH5_A) -> Self { + variant as u8 != 0 + } +} +impl CH5_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CH5_A { + match self.bits { + false => CH5_A::DISABLED, + true => CH5_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == CH5_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == CH5_A::ENABLED + } +} +#[doc = "Channel 5 enable clear register. Writing 0 has no effect.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CH5_AW { + #[doc = "1: Write: Disable channel"] + CLEAR = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CH5_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CH5` writer - Channel 5 enable clear register. Writing 0 has no effect."] +pub type CH5_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, CHENCLR_SPEC, CH5_AW, O>; +impl<'a, const O: u8> CH5_W<'a, O> { + #[doc = "Write: Disable channel"] + #[inline(always)] + pub fn clear(self) -> &'a mut W { + self.variant(CH5_AW::CLEAR) + } +} +#[doc = "Field `CH6` reader - Channel 6 enable clear register. Writing 0 has no effect."] +pub type CH6_R = crate::BitReader; +#[doc = "Channel 6 enable clear register. Writing 0 has no effect.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CH6_A { + #[doc = "0: Read: Channel disabled"] + DISABLED = 0, + #[doc = "1: Read: Channel enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CH6_A) -> Self { + variant as u8 != 0 + } +} +impl CH6_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CH6_A { + match self.bits { + false => CH6_A::DISABLED, + true => CH6_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == CH6_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == CH6_A::ENABLED + } +} +#[doc = "Channel 6 enable clear register. Writing 0 has no effect.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CH6_AW { + #[doc = "1: Write: Disable channel"] + CLEAR = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CH6_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CH6` writer - Channel 6 enable clear register. Writing 0 has no effect."] +pub type CH6_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, CHENCLR_SPEC, CH6_AW, O>; +impl<'a, const O: u8> CH6_W<'a, O> { + #[doc = "Write: Disable channel"] + #[inline(always)] + pub fn clear(self) -> &'a mut W { + self.variant(CH6_AW::CLEAR) + } +} +#[doc = "Field `CH7` reader - Channel 7 enable clear register. Writing 0 has no effect."] +pub type CH7_R = crate::BitReader; +#[doc = "Channel 7 enable clear register. Writing 0 has no effect.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CH7_A { + #[doc = "0: Read: Channel disabled"] + DISABLED = 0, + #[doc = "1: Read: Channel enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CH7_A) -> Self { + variant as u8 != 0 + } +} +impl CH7_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CH7_A { + match self.bits { + false => CH7_A::DISABLED, + true => CH7_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == CH7_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == CH7_A::ENABLED + } +} +#[doc = "Channel 7 enable clear register. Writing 0 has no effect.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CH7_AW { + #[doc = "1: Write: Disable channel"] + CLEAR = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CH7_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CH7` writer - Channel 7 enable clear register. Writing 0 has no effect."] +pub type CH7_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, CHENCLR_SPEC, CH7_AW, O>; +impl<'a, const O: u8> CH7_W<'a, O> { + #[doc = "Write: Disable channel"] + #[inline(always)] + pub fn clear(self) -> &'a mut W { + self.variant(CH7_AW::CLEAR) + } +} +#[doc = "Field `CH8` reader - Channel 8 enable clear register. Writing 0 has no effect."] +pub type CH8_R = crate::BitReader; +#[doc = "Channel 8 enable clear register. Writing 0 has no effect.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CH8_A { + #[doc = "0: Read: Channel disabled"] + DISABLED = 0, + #[doc = "1: Read: Channel enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CH8_A) -> Self { + variant as u8 != 0 + } +} +impl CH8_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CH8_A { + match self.bits { + false => CH8_A::DISABLED, + true => CH8_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == CH8_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == CH8_A::ENABLED + } +} +#[doc = "Channel 8 enable clear register. Writing 0 has no effect.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CH8_AW { + #[doc = "1: Write: Disable channel"] + CLEAR = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CH8_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CH8` writer - Channel 8 enable clear register. Writing 0 has no effect."] +pub type CH8_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, CHENCLR_SPEC, CH8_AW, O>; +impl<'a, const O: u8> CH8_W<'a, O> { + #[doc = "Write: Disable channel"] + #[inline(always)] + pub fn clear(self) -> &'a mut W { + self.variant(CH8_AW::CLEAR) + } +} +#[doc = "Field `CH9` reader - Channel 9 enable clear register. Writing 0 has no effect."] +pub type CH9_R = crate::BitReader; +#[doc = "Channel 9 enable clear register. Writing 0 has no effect.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CH9_A { + #[doc = "0: Read: Channel disabled"] + DISABLED = 0, + #[doc = "1: Read: Channel enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CH9_A) -> Self { + variant as u8 != 0 + } +} +impl CH9_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CH9_A { + match self.bits { + false => CH9_A::DISABLED, + true => CH9_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == CH9_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == CH9_A::ENABLED + } +} +#[doc = "Channel 9 enable clear register. Writing 0 has no effect.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CH9_AW { + #[doc = "1: Write: Disable channel"] + CLEAR = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CH9_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CH9` writer - Channel 9 enable clear register. Writing 0 has no effect."] +pub type CH9_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, CHENCLR_SPEC, CH9_AW, O>; +impl<'a, const O: u8> CH9_W<'a, O> { + #[doc = "Write: Disable channel"] + #[inline(always)] + pub fn clear(self) -> &'a mut W { + self.variant(CH9_AW::CLEAR) + } +} +#[doc = "Field `CH10` reader - Channel 10 enable clear register. Writing 0 has no effect."] +pub type CH10_R = crate::BitReader; +#[doc = "Channel 10 enable clear register. Writing 0 has no effect.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CH10_A { + #[doc = "0: Read: Channel disabled"] + DISABLED = 0, + #[doc = "1: Read: Channel enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CH10_A) -> Self { + variant as u8 != 0 + } +} +impl CH10_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CH10_A { + match self.bits { + false => CH10_A::DISABLED, + true => CH10_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == CH10_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == CH10_A::ENABLED + } +} +#[doc = "Channel 10 enable clear register. Writing 0 has no effect.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CH10_AW { + #[doc = "1: Write: Disable channel"] + CLEAR = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CH10_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CH10` writer - Channel 10 enable clear register. Writing 0 has no effect."] +pub type CH10_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, CHENCLR_SPEC, CH10_AW, O>; +impl<'a, const O: u8> CH10_W<'a, O> { + #[doc = "Write: Disable channel"] + #[inline(always)] + pub fn clear(self) -> &'a mut W { + self.variant(CH10_AW::CLEAR) + } +} +#[doc = "Field `CH11` reader - Channel 11 enable clear register. Writing 0 has no effect."] +pub type CH11_R = crate::BitReader; +#[doc = "Channel 11 enable clear register. Writing 0 has no effect.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CH11_A { + #[doc = "0: Read: Channel disabled"] + DISABLED = 0, + #[doc = "1: Read: Channel enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CH11_A) -> Self { + variant as u8 != 0 + } +} +impl CH11_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CH11_A { + match self.bits { + false => CH11_A::DISABLED, + true => CH11_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == CH11_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == CH11_A::ENABLED + } +} +#[doc = "Channel 11 enable clear register. Writing 0 has no effect.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CH11_AW { + #[doc = "1: Write: Disable channel"] + CLEAR = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CH11_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CH11` writer - Channel 11 enable clear register. Writing 0 has no effect."] +pub type CH11_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, CHENCLR_SPEC, CH11_AW, O>; +impl<'a, const O: u8> CH11_W<'a, O> { + #[doc = "Write: Disable channel"] + #[inline(always)] + pub fn clear(self) -> &'a mut W { + self.variant(CH11_AW::CLEAR) + } +} +#[doc = "Field `CH12` reader - Channel 12 enable clear register. Writing 0 has no effect."] +pub type CH12_R = crate::BitReader; +#[doc = "Channel 12 enable clear register. Writing 0 has no effect.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CH12_A { + #[doc = "0: Read: Channel disabled"] + DISABLED = 0, + #[doc = "1: Read: Channel enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CH12_A) -> Self { + variant as u8 != 0 + } +} +impl CH12_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CH12_A { + match self.bits { + false => CH12_A::DISABLED, + true => CH12_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == CH12_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == CH12_A::ENABLED + } +} +#[doc = "Channel 12 enable clear register. Writing 0 has no effect.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CH12_AW { + #[doc = "1: Write: Disable channel"] + CLEAR = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CH12_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CH12` writer - Channel 12 enable clear register. Writing 0 has no effect."] +pub type CH12_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, CHENCLR_SPEC, CH12_AW, O>; +impl<'a, const O: u8> CH12_W<'a, O> { + #[doc = "Write: Disable channel"] + #[inline(always)] + pub fn clear(self) -> &'a mut W { + self.variant(CH12_AW::CLEAR) + } +} +#[doc = "Field `CH13` reader - Channel 13 enable clear register. Writing 0 has no effect."] +pub type CH13_R = crate::BitReader; +#[doc = "Channel 13 enable clear register. Writing 0 has no effect.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CH13_A { + #[doc = "0: Read: Channel disabled"] + DISABLED = 0, + #[doc = "1: Read: Channel enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CH13_A) -> Self { + variant as u8 != 0 + } +} +impl CH13_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CH13_A { + match self.bits { + false => CH13_A::DISABLED, + true => CH13_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == CH13_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == CH13_A::ENABLED + } +} +#[doc = "Channel 13 enable clear register. Writing 0 has no effect.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CH13_AW { + #[doc = "1: Write: Disable channel"] + CLEAR = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CH13_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CH13` writer - Channel 13 enable clear register. Writing 0 has no effect."] +pub type CH13_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, CHENCLR_SPEC, CH13_AW, O>; +impl<'a, const O: u8> CH13_W<'a, O> { + #[doc = "Write: Disable channel"] + #[inline(always)] + pub fn clear(self) -> &'a mut W { + self.variant(CH13_AW::CLEAR) + } +} +#[doc = "Field `CH14` reader - Channel 14 enable clear register. Writing 0 has no effect."] +pub type CH14_R = crate::BitReader; +#[doc = "Channel 14 enable clear register. Writing 0 has no effect.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CH14_A { + #[doc = "0: Read: Channel disabled"] + DISABLED = 0, + #[doc = "1: Read: Channel enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CH14_A) -> Self { + variant as u8 != 0 + } +} +impl CH14_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CH14_A { + match self.bits { + false => CH14_A::DISABLED, + true => CH14_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == CH14_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == CH14_A::ENABLED + } +} +#[doc = "Channel 14 enable clear register. Writing 0 has no effect.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CH14_AW { + #[doc = "1: Write: Disable channel"] + CLEAR = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CH14_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CH14` writer - Channel 14 enable clear register. Writing 0 has no effect."] +pub type CH14_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, CHENCLR_SPEC, CH14_AW, O>; +impl<'a, const O: u8> CH14_W<'a, O> { + #[doc = "Write: Disable channel"] + #[inline(always)] + pub fn clear(self) -> &'a mut W { + self.variant(CH14_AW::CLEAR) + } +} +#[doc = "Field `CH15` reader - Channel 15 enable clear register. Writing 0 has no effect."] +pub type CH15_R = crate::BitReader; +#[doc = "Channel 15 enable clear register. Writing 0 has no effect.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CH15_A { + #[doc = "0: Read: Channel disabled"] + DISABLED = 0, + #[doc = "1: Read: Channel enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CH15_A) -> Self { + variant as u8 != 0 + } +} +impl CH15_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CH15_A { + match self.bits { + false => CH15_A::DISABLED, + true => CH15_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == CH15_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == CH15_A::ENABLED + } +} +#[doc = "Channel 15 enable clear register. Writing 0 has no effect.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CH15_AW { + #[doc = "1: Write: Disable channel"] + CLEAR = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CH15_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CH15` writer - Channel 15 enable clear register. Writing 0 has no effect."] +pub type CH15_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, CHENCLR_SPEC, CH15_AW, O>; +impl<'a, const O: u8> CH15_W<'a, O> { + #[doc = "Write: Disable channel"] + #[inline(always)] + pub fn clear(self) -> &'a mut W { + self.variant(CH15_AW::CLEAR) + } +} +impl R { + #[doc = "Bit 0 - Channel 0 enable clear register. Writing 0 has no effect."] + #[inline(always)] + pub fn ch0(&self) -> CH0_R { + CH0_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Channel 1 enable clear register. Writing 0 has no effect."] + #[inline(always)] + pub fn ch1(&self) -> CH1_R { + CH1_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Channel 2 enable clear register. Writing 0 has no effect."] + #[inline(always)] + pub fn ch2(&self) -> CH2_R { + CH2_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Channel 3 enable clear register. Writing 0 has no effect."] + #[inline(always)] + pub fn ch3(&self) -> CH3_R { + CH3_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Channel 4 enable clear register. Writing 0 has no effect."] + #[inline(always)] + pub fn ch4(&self) -> CH4_R { + CH4_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Channel 5 enable clear register. Writing 0 has no effect."] + #[inline(always)] + pub fn ch5(&self) -> CH5_R { + CH5_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Channel 6 enable clear register. Writing 0 has no effect."] + #[inline(always)] + pub fn ch6(&self) -> CH6_R { + CH6_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Channel 7 enable clear register. Writing 0 has no effect."] + #[inline(always)] + pub fn ch7(&self) -> CH7_R { + CH7_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Channel 8 enable clear register. Writing 0 has no effect."] + #[inline(always)] + pub fn ch8(&self) -> CH8_R { + CH8_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Channel 9 enable clear register. Writing 0 has no effect."] + #[inline(always)] + pub fn ch9(&self) -> CH9_R { + CH9_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Channel 10 enable clear register. Writing 0 has no effect."] + #[inline(always)] + pub fn ch10(&self) -> CH10_R { + CH10_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Channel 11 enable clear register. Writing 0 has no effect."] + #[inline(always)] + pub fn ch11(&self) -> CH11_R { + CH11_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Channel 12 enable clear register. Writing 0 has no effect."] + #[inline(always)] + pub fn ch12(&self) -> CH12_R { + CH12_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Channel 13 enable clear register. Writing 0 has no effect."] + #[inline(always)] + pub fn ch13(&self) -> CH13_R { + CH13_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Channel 14 enable clear register. Writing 0 has no effect."] + #[inline(always)] + pub fn ch14(&self) -> CH14_R { + CH14_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Channel 15 enable clear register. Writing 0 has no effect."] + #[inline(always)] + pub fn ch15(&self) -> CH15_R { + CH15_R::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Channel 0 enable clear register. Writing 0 has no effect."] + #[inline(always)] + pub fn ch0(&mut self) -> CH0_W<0> { + CH0_W::new(self) + } + #[doc = "Bit 1 - Channel 1 enable clear register. Writing 0 has no effect."] + #[inline(always)] + pub fn ch1(&mut self) -> CH1_W<1> { + CH1_W::new(self) + } + #[doc = "Bit 2 - Channel 2 enable clear register. Writing 0 has no effect."] + #[inline(always)] + pub fn ch2(&mut self) -> CH2_W<2> { + CH2_W::new(self) + } + #[doc = "Bit 3 - Channel 3 enable clear register. Writing 0 has no effect."] + #[inline(always)] + pub fn ch3(&mut self) -> CH3_W<3> { + CH3_W::new(self) + } + #[doc = "Bit 4 - Channel 4 enable clear register. Writing 0 has no effect."] + #[inline(always)] + pub fn ch4(&mut self) -> CH4_W<4> { + CH4_W::new(self) + } + #[doc = "Bit 5 - Channel 5 enable clear register. Writing 0 has no effect."] + #[inline(always)] + pub fn ch5(&mut self) -> CH5_W<5> { + CH5_W::new(self) + } + #[doc = "Bit 6 - Channel 6 enable clear register. Writing 0 has no effect."] + #[inline(always)] + pub fn ch6(&mut self) -> CH6_W<6> { + CH6_W::new(self) + } + #[doc = "Bit 7 - Channel 7 enable clear register. Writing 0 has no effect."] + #[inline(always)] + pub fn ch7(&mut self) -> CH7_W<7> { + CH7_W::new(self) + } + #[doc = "Bit 8 - Channel 8 enable clear register. Writing 0 has no effect."] + #[inline(always)] + pub fn ch8(&mut self) -> CH8_W<8> { + CH8_W::new(self) + } + #[doc = "Bit 9 - Channel 9 enable clear register. Writing 0 has no effect."] + #[inline(always)] + pub fn ch9(&mut self) -> CH9_W<9> { + CH9_W::new(self) + } + #[doc = "Bit 10 - Channel 10 enable clear register. Writing 0 has no effect."] + #[inline(always)] + pub fn ch10(&mut self) -> CH10_W<10> { + CH10_W::new(self) + } + #[doc = "Bit 11 - Channel 11 enable clear register. Writing 0 has no effect."] + #[inline(always)] + pub fn ch11(&mut self) -> CH11_W<11> { + CH11_W::new(self) + } + #[doc = "Bit 12 - Channel 12 enable clear register. Writing 0 has no effect."] + #[inline(always)] + pub fn ch12(&mut self) -> CH12_W<12> { + CH12_W::new(self) + } + #[doc = "Bit 13 - Channel 13 enable clear register. Writing 0 has no effect."] + #[inline(always)] + pub fn ch13(&mut self) -> CH13_W<13> { + CH13_W::new(self) + } + #[doc = "Bit 14 - Channel 14 enable clear register. Writing 0 has no effect."] + #[inline(always)] + pub fn ch14(&mut self) -> CH14_W<14> { + CH14_W::new(self) + } + #[doc = "Bit 15 - Channel 15 enable clear register. Writing 0 has no effect."] + #[inline(always)] + pub fn ch15(&mut self) -> CH15_W<15> { + CH15_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Channel enable clear register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [chenclr](index.html) module"] +pub struct CHENCLR_SPEC; +impl crate::RegisterSpec for CHENCLR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [chenclr::R](R) reader structure"] +impl crate::Readable for CHENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [chenclr::W](W) writer structure"] +impl crate::Writable for CHENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CHENCLR to value 0"] +impl crate::Resettable for CHENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/dppic_ns/chenset.rs b/pacs/nrf9120-pac/src/dppic_ns/chenset.rs new file mode 100644 index 00000000..6c09de0b --- /dev/null +++ b/pacs/nrf9120-pac/src/dppic_ns/chenset.rs @@ -0,0 +1,1138 @@ +#[doc = "Register `CHENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CHENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CH0` reader - Channel 0 enable set register. Writing 0 has no effect."] +pub type CH0_R = crate::BitReader; +#[doc = "Channel 0 enable set register. Writing 0 has no effect.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CH0_A { + #[doc = "0: Read: Channel disabled"] + DISABLED = 0, + #[doc = "1: Read: Channel enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CH0_A) -> Self { + variant as u8 != 0 + } +} +impl CH0_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CH0_A { + match self.bits { + false => CH0_A::DISABLED, + true => CH0_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == CH0_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == CH0_A::ENABLED + } +} +#[doc = "Channel 0 enable set register. Writing 0 has no effect.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CH0_AW { + #[doc = "1: Write: Enable channel"] + SET = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CH0_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CH0` writer - Channel 0 enable set register. Writing 0 has no effect."] +pub type CH0_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, CHENSET_SPEC, CH0_AW, O>; +impl<'a, const O: u8> CH0_W<'a, O> { + #[doc = "Write: Enable channel"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(CH0_AW::SET) + } +} +#[doc = "Field `CH1` reader - Channel 1 enable set register. Writing 0 has no effect."] +pub type CH1_R = crate::BitReader; +#[doc = "Channel 1 enable set register. Writing 0 has no effect.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CH1_A { + #[doc = "0: Read: Channel disabled"] + DISABLED = 0, + #[doc = "1: Read: Channel enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CH1_A) -> Self { + variant as u8 != 0 + } +} +impl CH1_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CH1_A { + match self.bits { + false => CH1_A::DISABLED, + true => CH1_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == CH1_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == CH1_A::ENABLED + } +} +#[doc = "Channel 1 enable set register. Writing 0 has no effect.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CH1_AW { + #[doc = "1: Write: Enable channel"] + SET = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CH1_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CH1` writer - Channel 1 enable set register. Writing 0 has no effect."] +pub type CH1_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, CHENSET_SPEC, CH1_AW, O>; +impl<'a, const O: u8> CH1_W<'a, O> { + #[doc = "Write: Enable channel"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(CH1_AW::SET) + } +} +#[doc = "Field `CH2` reader - Channel 2 enable set register. Writing 0 has no effect."] +pub type CH2_R = crate::BitReader; +#[doc = "Channel 2 enable set register. Writing 0 has no effect.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CH2_A { + #[doc = "0: Read: Channel disabled"] + DISABLED = 0, + #[doc = "1: Read: Channel enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CH2_A) -> Self { + variant as u8 != 0 + } +} +impl CH2_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CH2_A { + match self.bits { + false => CH2_A::DISABLED, + true => CH2_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == CH2_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == CH2_A::ENABLED + } +} +#[doc = "Channel 2 enable set register. Writing 0 has no effect.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CH2_AW { + #[doc = "1: Write: Enable channel"] + SET = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CH2_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CH2` writer - Channel 2 enable set register. Writing 0 has no effect."] +pub type CH2_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, CHENSET_SPEC, CH2_AW, O>; +impl<'a, const O: u8> CH2_W<'a, O> { + #[doc = "Write: Enable channel"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(CH2_AW::SET) + } +} +#[doc = "Field `CH3` reader - Channel 3 enable set register. Writing 0 has no effect."] +pub type CH3_R = crate::BitReader; +#[doc = "Channel 3 enable set register. Writing 0 has no effect.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CH3_A { + #[doc = "0: Read: Channel disabled"] + DISABLED = 0, + #[doc = "1: Read: Channel enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CH3_A) -> Self { + variant as u8 != 0 + } +} +impl CH3_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CH3_A { + match self.bits { + false => CH3_A::DISABLED, + true => CH3_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == CH3_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == CH3_A::ENABLED + } +} +#[doc = "Channel 3 enable set register. Writing 0 has no effect.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CH3_AW { + #[doc = "1: Write: Enable channel"] + SET = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CH3_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CH3` writer - Channel 3 enable set register. Writing 0 has no effect."] +pub type CH3_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, CHENSET_SPEC, CH3_AW, O>; +impl<'a, const O: u8> CH3_W<'a, O> { + #[doc = "Write: Enable channel"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(CH3_AW::SET) + } +} +#[doc = "Field `CH4` reader - Channel 4 enable set register. Writing 0 has no effect."] +pub type CH4_R = crate::BitReader; +#[doc = "Channel 4 enable set register. Writing 0 has no effect.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CH4_A { + #[doc = "0: Read: Channel disabled"] + DISABLED = 0, + #[doc = "1: Read: Channel enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CH4_A) -> Self { + variant as u8 != 0 + } +} +impl CH4_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CH4_A { + match self.bits { + false => CH4_A::DISABLED, + true => CH4_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == CH4_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == CH4_A::ENABLED + } +} +#[doc = "Channel 4 enable set register. Writing 0 has no effect.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CH4_AW { + #[doc = "1: Write: Enable channel"] + SET = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CH4_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CH4` writer - Channel 4 enable set register. Writing 0 has no effect."] +pub type CH4_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, CHENSET_SPEC, CH4_AW, O>; +impl<'a, const O: u8> CH4_W<'a, O> { + #[doc = "Write: Enable channel"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(CH4_AW::SET) + } +} +#[doc = "Field `CH5` reader - Channel 5 enable set register. Writing 0 has no effect."] +pub type CH5_R = crate::BitReader; +#[doc = "Channel 5 enable set register. Writing 0 has no effect.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CH5_A { + #[doc = "0: Read: Channel disabled"] + DISABLED = 0, + #[doc = "1: Read: Channel enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CH5_A) -> Self { + variant as u8 != 0 + } +} +impl CH5_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CH5_A { + match self.bits { + false => CH5_A::DISABLED, + true => CH5_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == CH5_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == CH5_A::ENABLED + } +} +#[doc = "Channel 5 enable set register. Writing 0 has no effect.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CH5_AW { + #[doc = "1: Write: Enable channel"] + SET = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CH5_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CH5` writer - Channel 5 enable set register. Writing 0 has no effect."] +pub type CH5_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, CHENSET_SPEC, CH5_AW, O>; +impl<'a, const O: u8> CH5_W<'a, O> { + #[doc = "Write: Enable channel"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(CH5_AW::SET) + } +} +#[doc = "Field `CH6` reader - Channel 6 enable set register. Writing 0 has no effect."] +pub type CH6_R = crate::BitReader; +#[doc = "Channel 6 enable set register. Writing 0 has no effect.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CH6_A { + #[doc = "0: Read: Channel disabled"] + DISABLED = 0, + #[doc = "1: Read: Channel enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CH6_A) -> Self { + variant as u8 != 0 + } +} +impl CH6_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CH6_A { + match self.bits { + false => CH6_A::DISABLED, + true => CH6_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == CH6_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == CH6_A::ENABLED + } +} +#[doc = "Channel 6 enable set register. Writing 0 has no effect.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CH6_AW { + #[doc = "1: Write: Enable channel"] + SET = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CH6_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CH6` writer - Channel 6 enable set register. Writing 0 has no effect."] +pub type CH6_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, CHENSET_SPEC, CH6_AW, O>; +impl<'a, const O: u8> CH6_W<'a, O> { + #[doc = "Write: Enable channel"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(CH6_AW::SET) + } +} +#[doc = "Field `CH7` reader - Channel 7 enable set register. Writing 0 has no effect."] +pub type CH7_R = crate::BitReader; +#[doc = "Channel 7 enable set register. Writing 0 has no effect.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CH7_A { + #[doc = "0: Read: Channel disabled"] + DISABLED = 0, + #[doc = "1: Read: Channel enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CH7_A) -> Self { + variant as u8 != 0 + } +} +impl CH7_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CH7_A { + match self.bits { + false => CH7_A::DISABLED, + true => CH7_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == CH7_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == CH7_A::ENABLED + } +} +#[doc = "Channel 7 enable set register. Writing 0 has no effect.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CH7_AW { + #[doc = "1: Write: Enable channel"] + SET = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CH7_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CH7` writer - Channel 7 enable set register. Writing 0 has no effect."] +pub type CH7_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, CHENSET_SPEC, CH7_AW, O>; +impl<'a, const O: u8> CH7_W<'a, O> { + #[doc = "Write: Enable channel"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(CH7_AW::SET) + } +} +#[doc = "Field `CH8` reader - Channel 8 enable set register. Writing 0 has no effect."] +pub type CH8_R = crate::BitReader; +#[doc = "Channel 8 enable set register. Writing 0 has no effect.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CH8_A { + #[doc = "0: Read: Channel disabled"] + DISABLED = 0, + #[doc = "1: Read: Channel enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CH8_A) -> Self { + variant as u8 != 0 + } +} +impl CH8_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CH8_A { + match self.bits { + false => CH8_A::DISABLED, + true => CH8_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == CH8_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == CH8_A::ENABLED + } +} +#[doc = "Channel 8 enable set register. Writing 0 has no effect.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CH8_AW { + #[doc = "1: Write: Enable channel"] + SET = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CH8_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CH8` writer - Channel 8 enable set register. Writing 0 has no effect."] +pub type CH8_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, CHENSET_SPEC, CH8_AW, O>; +impl<'a, const O: u8> CH8_W<'a, O> { + #[doc = "Write: Enable channel"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(CH8_AW::SET) + } +} +#[doc = "Field `CH9` reader - Channel 9 enable set register. Writing 0 has no effect."] +pub type CH9_R = crate::BitReader; +#[doc = "Channel 9 enable set register. Writing 0 has no effect.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CH9_A { + #[doc = "0: Read: Channel disabled"] + DISABLED = 0, + #[doc = "1: Read: Channel enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CH9_A) -> Self { + variant as u8 != 0 + } +} +impl CH9_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CH9_A { + match self.bits { + false => CH9_A::DISABLED, + true => CH9_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == CH9_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == CH9_A::ENABLED + } +} +#[doc = "Channel 9 enable set register. Writing 0 has no effect.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CH9_AW { + #[doc = "1: Write: Enable channel"] + SET = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CH9_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CH9` writer - Channel 9 enable set register. Writing 0 has no effect."] +pub type CH9_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, CHENSET_SPEC, CH9_AW, O>; +impl<'a, const O: u8> CH9_W<'a, O> { + #[doc = "Write: Enable channel"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(CH9_AW::SET) + } +} +#[doc = "Field `CH10` reader - Channel 10 enable set register. Writing 0 has no effect."] +pub type CH10_R = crate::BitReader; +#[doc = "Channel 10 enable set register. Writing 0 has no effect.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CH10_A { + #[doc = "0: Read: Channel disabled"] + DISABLED = 0, + #[doc = "1: Read: Channel enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CH10_A) -> Self { + variant as u8 != 0 + } +} +impl CH10_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CH10_A { + match self.bits { + false => CH10_A::DISABLED, + true => CH10_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == CH10_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == CH10_A::ENABLED + } +} +#[doc = "Channel 10 enable set register. Writing 0 has no effect.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CH10_AW { + #[doc = "1: Write: Enable channel"] + SET = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CH10_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CH10` writer - Channel 10 enable set register. Writing 0 has no effect."] +pub type CH10_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, CHENSET_SPEC, CH10_AW, O>; +impl<'a, const O: u8> CH10_W<'a, O> { + #[doc = "Write: Enable channel"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(CH10_AW::SET) + } +} +#[doc = "Field `CH11` reader - Channel 11 enable set register. Writing 0 has no effect."] +pub type CH11_R = crate::BitReader; +#[doc = "Channel 11 enable set register. Writing 0 has no effect.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CH11_A { + #[doc = "0: Read: Channel disabled"] + DISABLED = 0, + #[doc = "1: Read: Channel enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CH11_A) -> Self { + variant as u8 != 0 + } +} +impl CH11_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CH11_A { + match self.bits { + false => CH11_A::DISABLED, + true => CH11_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == CH11_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == CH11_A::ENABLED + } +} +#[doc = "Channel 11 enable set register. Writing 0 has no effect.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CH11_AW { + #[doc = "1: Write: Enable channel"] + SET = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CH11_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CH11` writer - Channel 11 enable set register. Writing 0 has no effect."] +pub type CH11_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, CHENSET_SPEC, CH11_AW, O>; +impl<'a, const O: u8> CH11_W<'a, O> { + #[doc = "Write: Enable channel"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(CH11_AW::SET) + } +} +#[doc = "Field `CH12` reader - Channel 12 enable set register. Writing 0 has no effect."] +pub type CH12_R = crate::BitReader; +#[doc = "Channel 12 enable set register. Writing 0 has no effect.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CH12_A { + #[doc = "0: Read: Channel disabled"] + DISABLED = 0, + #[doc = "1: Read: Channel enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CH12_A) -> Self { + variant as u8 != 0 + } +} +impl CH12_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CH12_A { + match self.bits { + false => CH12_A::DISABLED, + true => CH12_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == CH12_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == CH12_A::ENABLED + } +} +#[doc = "Channel 12 enable set register. Writing 0 has no effect.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CH12_AW { + #[doc = "1: Write: Enable channel"] + SET = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CH12_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CH12` writer - Channel 12 enable set register. Writing 0 has no effect."] +pub type CH12_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, CHENSET_SPEC, CH12_AW, O>; +impl<'a, const O: u8> CH12_W<'a, O> { + #[doc = "Write: Enable channel"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(CH12_AW::SET) + } +} +#[doc = "Field `CH13` reader - Channel 13 enable set register. Writing 0 has no effect."] +pub type CH13_R = crate::BitReader; +#[doc = "Channel 13 enable set register. Writing 0 has no effect.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CH13_A { + #[doc = "0: Read: Channel disabled"] + DISABLED = 0, + #[doc = "1: Read: Channel enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CH13_A) -> Self { + variant as u8 != 0 + } +} +impl CH13_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CH13_A { + match self.bits { + false => CH13_A::DISABLED, + true => CH13_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == CH13_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == CH13_A::ENABLED + } +} +#[doc = "Channel 13 enable set register. Writing 0 has no effect.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CH13_AW { + #[doc = "1: Write: Enable channel"] + SET = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CH13_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CH13` writer - Channel 13 enable set register. Writing 0 has no effect."] +pub type CH13_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, CHENSET_SPEC, CH13_AW, O>; +impl<'a, const O: u8> CH13_W<'a, O> { + #[doc = "Write: Enable channel"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(CH13_AW::SET) + } +} +#[doc = "Field `CH14` reader - Channel 14 enable set register. Writing 0 has no effect."] +pub type CH14_R = crate::BitReader; +#[doc = "Channel 14 enable set register. Writing 0 has no effect.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CH14_A { + #[doc = "0: Read: Channel disabled"] + DISABLED = 0, + #[doc = "1: Read: Channel enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CH14_A) -> Self { + variant as u8 != 0 + } +} +impl CH14_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CH14_A { + match self.bits { + false => CH14_A::DISABLED, + true => CH14_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == CH14_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == CH14_A::ENABLED + } +} +#[doc = "Channel 14 enable set register. Writing 0 has no effect.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CH14_AW { + #[doc = "1: Write: Enable channel"] + SET = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CH14_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CH14` writer - Channel 14 enable set register. Writing 0 has no effect."] +pub type CH14_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, CHENSET_SPEC, CH14_AW, O>; +impl<'a, const O: u8> CH14_W<'a, O> { + #[doc = "Write: Enable channel"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(CH14_AW::SET) + } +} +#[doc = "Field `CH15` reader - Channel 15 enable set register. Writing 0 has no effect."] +pub type CH15_R = crate::BitReader; +#[doc = "Channel 15 enable set register. Writing 0 has no effect.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CH15_A { + #[doc = "0: Read: Channel disabled"] + DISABLED = 0, + #[doc = "1: Read: Channel enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CH15_A) -> Self { + variant as u8 != 0 + } +} +impl CH15_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CH15_A { + match self.bits { + false => CH15_A::DISABLED, + true => CH15_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == CH15_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == CH15_A::ENABLED + } +} +#[doc = "Channel 15 enable set register. Writing 0 has no effect.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CH15_AW { + #[doc = "1: Write: Enable channel"] + SET = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CH15_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CH15` writer - Channel 15 enable set register. Writing 0 has no effect."] +pub type CH15_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, CHENSET_SPEC, CH15_AW, O>; +impl<'a, const O: u8> CH15_W<'a, O> { + #[doc = "Write: Enable channel"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(CH15_AW::SET) + } +} +impl R { + #[doc = "Bit 0 - Channel 0 enable set register. Writing 0 has no effect."] + #[inline(always)] + pub fn ch0(&self) -> CH0_R { + CH0_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Channel 1 enable set register. Writing 0 has no effect."] + #[inline(always)] + pub fn ch1(&self) -> CH1_R { + CH1_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Channel 2 enable set register. Writing 0 has no effect."] + #[inline(always)] + pub fn ch2(&self) -> CH2_R { + CH2_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Channel 3 enable set register. Writing 0 has no effect."] + #[inline(always)] + pub fn ch3(&self) -> CH3_R { + CH3_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Channel 4 enable set register. Writing 0 has no effect."] + #[inline(always)] + pub fn ch4(&self) -> CH4_R { + CH4_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Channel 5 enable set register. Writing 0 has no effect."] + #[inline(always)] + pub fn ch5(&self) -> CH5_R { + CH5_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Channel 6 enable set register. Writing 0 has no effect."] + #[inline(always)] + pub fn ch6(&self) -> CH6_R { + CH6_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Channel 7 enable set register. Writing 0 has no effect."] + #[inline(always)] + pub fn ch7(&self) -> CH7_R { + CH7_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Channel 8 enable set register. Writing 0 has no effect."] + #[inline(always)] + pub fn ch8(&self) -> CH8_R { + CH8_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Channel 9 enable set register. Writing 0 has no effect."] + #[inline(always)] + pub fn ch9(&self) -> CH9_R { + CH9_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Channel 10 enable set register. Writing 0 has no effect."] + #[inline(always)] + pub fn ch10(&self) -> CH10_R { + CH10_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Channel 11 enable set register. Writing 0 has no effect."] + #[inline(always)] + pub fn ch11(&self) -> CH11_R { + CH11_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Channel 12 enable set register. Writing 0 has no effect."] + #[inline(always)] + pub fn ch12(&self) -> CH12_R { + CH12_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Channel 13 enable set register. Writing 0 has no effect."] + #[inline(always)] + pub fn ch13(&self) -> CH13_R { + CH13_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Channel 14 enable set register. Writing 0 has no effect."] + #[inline(always)] + pub fn ch14(&self) -> CH14_R { + CH14_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Channel 15 enable set register. Writing 0 has no effect."] + #[inline(always)] + pub fn ch15(&self) -> CH15_R { + CH15_R::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Channel 0 enable set register. Writing 0 has no effect."] + #[inline(always)] + pub fn ch0(&mut self) -> CH0_W<0> { + CH0_W::new(self) + } + #[doc = "Bit 1 - Channel 1 enable set register. Writing 0 has no effect."] + #[inline(always)] + pub fn ch1(&mut self) -> CH1_W<1> { + CH1_W::new(self) + } + #[doc = "Bit 2 - Channel 2 enable set register. Writing 0 has no effect."] + #[inline(always)] + pub fn ch2(&mut self) -> CH2_W<2> { + CH2_W::new(self) + } + #[doc = "Bit 3 - Channel 3 enable set register. Writing 0 has no effect."] + #[inline(always)] + pub fn ch3(&mut self) -> CH3_W<3> { + CH3_W::new(self) + } + #[doc = "Bit 4 - Channel 4 enable set register. Writing 0 has no effect."] + #[inline(always)] + pub fn ch4(&mut self) -> CH4_W<4> { + CH4_W::new(self) + } + #[doc = "Bit 5 - Channel 5 enable set register. Writing 0 has no effect."] + #[inline(always)] + pub fn ch5(&mut self) -> CH5_W<5> { + CH5_W::new(self) + } + #[doc = "Bit 6 - Channel 6 enable set register. Writing 0 has no effect."] + #[inline(always)] + pub fn ch6(&mut self) -> CH6_W<6> { + CH6_W::new(self) + } + #[doc = "Bit 7 - Channel 7 enable set register. Writing 0 has no effect."] + #[inline(always)] + pub fn ch7(&mut self) -> CH7_W<7> { + CH7_W::new(self) + } + #[doc = "Bit 8 - Channel 8 enable set register. Writing 0 has no effect."] + #[inline(always)] + pub fn ch8(&mut self) -> CH8_W<8> { + CH8_W::new(self) + } + #[doc = "Bit 9 - Channel 9 enable set register. Writing 0 has no effect."] + #[inline(always)] + pub fn ch9(&mut self) -> CH9_W<9> { + CH9_W::new(self) + } + #[doc = "Bit 10 - Channel 10 enable set register. Writing 0 has no effect."] + #[inline(always)] + pub fn ch10(&mut self) -> CH10_W<10> { + CH10_W::new(self) + } + #[doc = "Bit 11 - Channel 11 enable set register. Writing 0 has no effect."] + #[inline(always)] + pub fn ch11(&mut self) -> CH11_W<11> { + CH11_W::new(self) + } + #[doc = "Bit 12 - Channel 12 enable set register. Writing 0 has no effect."] + #[inline(always)] + pub fn ch12(&mut self) -> CH12_W<12> { + CH12_W::new(self) + } + #[doc = "Bit 13 - Channel 13 enable set register. Writing 0 has no effect."] + #[inline(always)] + pub fn ch13(&mut self) -> CH13_W<13> { + CH13_W::new(self) + } + #[doc = "Bit 14 - Channel 14 enable set register. Writing 0 has no effect."] + #[inline(always)] + pub fn ch14(&mut self) -> CH14_W<14> { + CH14_W::new(self) + } + #[doc = "Bit 15 - Channel 15 enable set register. Writing 0 has no effect."] + #[inline(always)] + pub fn ch15(&mut self) -> CH15_W<15> { + CH15_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Channel enable set register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [chenset](index.html) module"] +pub struct CHENSET_SPEC; +impl crate::RegisterSpec for CHENSET_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [chenset::R](R) reader structure"] +impl crate::Readable for CHENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [chenset::W](W) writer structure"] +impl crate::Writable for CHENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CHENSET to value 0"] +impl crate::Resettable for CHENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/dppic_ns/chg.rs b/pacs/nrf9120-pac/src/dppic_ns/chg.rs new file mode 100644 index 00000000..0dcce8b3 --- /dev/null +++ b/pacs/nrf9120-pac/src/dppic_ns/chg.rs @@ -0,0 +1,1027 @@ +#[doc = "Register `CHG[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CHG[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CH0` reader - Include or exclude channel 0"] +pub type CH0_R = crate::BitReader; +#[doc = "Include or exclude channel 0\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CH0_A { + #[doc = "0: Exclude"] + EXCLUDED = 0, + #[doc = "1: Include"] + INCLUDED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CH0_A) -> Self { + variant as u8 != 0 + } +} +impl CH0_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CH0_A { + match self.bits { + false => CH0_A::EXCLUDED, + true => CH0_A::INCLUDED, + } + } + #[doc = "Checks if the value of the field is `EXCLUDED`"] + #[inline(always)] + pub fn is_excluded(&self) -> bool { + *self == CH0_A::EXCLUDED + } + #[doc = "Checks if the value of the field is `INCLUDED`"] + #[inline(always)] + pub fn is_included(&self) -> bool { + *self == CH0_A::INCLUDED + } +} +#[doc = "Field `CH0` writer - Include or exclude channel 0"] +pub type CH0_W<'a, const O: u8> = crate::BitWriter<'a, u32, CHG_SPEC, CH0_A, O>; +impl<'a, const O: u8> CH0_W<'a, O> { + #[doc = "Exclude"] + #[inline(always)] + pub fn excluded(self) -> &'a mut W { + self.variant(CH0_A::EXCLUDED) + } + #[doc = "Include"] + #[inline(always)] + pub fn included(self) -> &'a mut W { + self.variant(CH0_A::INCLUDED) + } +} +#[doc = "Field `CH1` reader - Include or exclude channel 1"] +pub type CH1_R = crate::BitReader; +#[doc = "Include or exclude channel 1\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CH1_A { + #[doc = "0: Exclude"] + EXCLUDED = 0, + #[doc = "1: Include"] + INCLUDED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CH1_A) -> Self { + variant as u8 != 0 + } +} +impl CH1_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CH1_A { + match self.bits { + false => CH1_A::EXCLUDED, + true => CH1_A::INCLUDED, + } + } + #[doc = "Checks if the value of the field is `EXCLUDED`"] + #[inline(always)] + pub fn is_excluded(&self) -> bool { + *self == CH1_A::EXCLUDED + } + #[doc = "Checks if the value of the field is `INCLUDED`"] + #[inline(always)] + pub fn is_included(&self) -> bool { + *self == CH1_A::INCLUDED + } +} +#[doc = "Field `CH1` writer - Include or exclude channel 1"] +pub type CH1_W<'a, const O: u8> = crate::BitWriter<'a, u32, CHG_SPEC, CH1_A, O>; +impl<'a, const O: u8> CH1_W<'a, O> { + #[doc = "Exclude"] + #[inline(always)] + pub fn excluded(self) -> &'a mut W { + self.variant(CH1_A::EXCLUDED) + } + #[doc = "Include"] + #[inline(always)] + pub fn included(self) -> &'a mut W { + self.variant(CH1_A::INCLUDED) + } +} +#[doc = "Field `CH2` reader - Include or exclude channel 2"] +pub type CH2_R = crate::BitReader; +#[doc = "Include or exclude channel 2\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CH2_A { + #[doc = "0: Exclude"] + EXCLUDED = 0, + #[doc = "1: Include"] + INCLUDED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CH2_A) -> Self { + variant as u8 != 0 + } +} +impl CH2_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CH2_A { + match self.bits { + false => CH2_A::EXCLUDED, + true => CH2_A::INCLUDED, + } + } + #[doc = "Checks if the value of the field is `EXCLUDED`"] + #[inline(always)] + pub fn is_excluded(&self) -> bool { + *self == CH2_A::EXCLUDED + } + #[doc = "Checks if the value of the field is `INCLUDED`"] + #[inline(always)] + pub fn is_included(&self) -> bool { + *self == CH2_A::INCLUDED + } +} +#[doc = "Field `CH2` writer - Include or exclude channel 2"] +pub type CH2_W<'a, const O: u8> = crate::BitWriter<'a, u32, CHG_SPEC, CH2_A, O>; +impl<'a, const O: u8> CH2_W<'a, O> { + #[doc = "Exclude"] + #[inline(always)] + pub fn excluded(self) -> &'a mut W { + self.variant(CH2_A::EXCLUDED) + } + #[doc = "Include"] + #[inline(always)] + pub fn included(self) -> &'a mut W { + self.variant(CH2_A::INCLUDED) + } +} +#[doc = "Field `CH3` reader - Include or exclude channel 3"] +pub type CH3_R = crate::BitReader; +#[doc = "Include or exclude channel 3\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CH3_A { + #[doc = "0: Exclude"] + EXCLUDED = 0, + #[doc = "1: Include"] + INCLUDED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CH3_A) -> Self { + variant as u8 != 0 + } +} +impl CH3_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CH3_A { + match self.bits { + false => CH3_A::EXCLUDED, + true => CH3_A::INCLUDED, + } + } + #[doc = "Checks if the value of the field is `EXCLUDED`"] + #[inline(always)] + pub fn is_excluded(&self) -> bool { + *self == CH3_A::EXCLUDED + } + #[doc = "Checks if the value of the field is `INCLUDED`"] + #[inline(always)] + pub fn is_included(&self) -> bool { + *self == CH3_A::INCLUDED + } +} +#[doc = "Field `CH3` writer - Include or exclude channel 3"] +pub type CH3_W<'a, const O: u8> = crate::BitWriter<'a, u32, CHG_SPEC, CH3_A, O>; +impl<'a, const O: u8> CH3_W<'a, O> { + #[doc = "Exclude"] + #[inline(always)] + pub fn excluded(self) -> &'a mut W { + self.variant(CH3_A::EXCLUDED) + } + #[doc = "Include"] + #[inline(always)] + pub fn included(self) -> &'a mut W { + self.variant(CH3_A::INCLUDED) + } +} +#[doc = "Field `CH4` reader - Include or exclude channel 4"] +pub type CH4_R = crate::BitReader; +#[doc = "Include or exclude channel 4\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CH4_A { + #[doc = "0: Exclude"] + EXCLUDED = 0, + #[doc = "1: Include"] + INCLUDED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CH4_A) -> Self { + variant as u8 != 0 + } +} +impl CH4_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CH4_A { + match self.bits { + false => CH4_A::EXCLUDED, + true => CH4_A::INCLUDED, + } + } + #[doc = "Checks if the value of the field is `EXCLUDED`"] + #[inline(always)] + pub fn is_excluded(&self) -> bool { + *self == CH4_A::EXCLUDED + } + #[doc = "Checks if the value of the field is `INCLUDED`"] + #[inline(always)] + pub fn is_included(&self) -> bool { + *self == CH4_A::INCLUDED + } +} +#[doc = "Field `CH4` writer - Include or exclude channel 4"] +pub type CH4_W<'a, const O: u8> = crate::BitWriter<'a, u32, CHG_SPEC, CH4_A, O>; +impl<'a, const O: u8> CH4_W<'a, O> { + #[doc = "Exclude"] + #[inline(always)] + pub fn excluded(self) -> &'a mut W { + self.variant(CH4_A::EXCLUDED) + } + #[doc = "Include"] + #[inline(always)] + pub fn included(self) -> &'a mut W { + self.variant(CH4_A::INCLUDED) + } +} +#[doc = "Field `CH5` reader - Include or exclude channel 5"] +pub type CH5_R = crate::BitReader; +#[doc = "Include or exclude channel 5\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CH5_A { + #[doc = "0: Exclude"] + EXCLUDED = 0, + #[doc = "1: Include"] + INCLUDED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CH5_A) -> Self { + variant as u8 != 0 + } +} +impl CH5_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CH5_A { + match self.bits { + false => CH5_A::EXCLUDED, + true => CH5_A::INCLUDED, + } + } + #[doc = "Checks if the value of the field is `EXCLUDED`"] + #[inline(always)] + pub fn is_excluded(&self) -> bool { + *self == CH5_A::EXCLUDED + } + #[doc = "Checks if the value of the field is `INCLUDED`"] + #[inline(always)] + pub fn is_included(&self) -> bool { + *self == CH5_A::INCLUDED + } +} +#[doc = "Field `CH5` writer - Include or exclude channel 5"] +pub type CH5_W<'a, const O: u8> = crate::BitWriter<'a, u32, CHG_SPEC, CH5_A, O>; +impl<'a, const O: u8> CH5_W<'a, O> { + #[doc = "Exclude"] + #[inline(always)] + pub fn excluded(self) -> &'a mut W { + self.variant(CH5_A::EXCLUDED) + } + #[doc = "Include"] + #[inline(always)] + pub fn included(self) -> &'a mut W { + self.variant(CH5_A::INCLUDED) + } +} +#[doc = "Field `CH6` reader - Include or exclude channel 6"] +pub type CH6_R = crate::BitReader; +#[doc = "Include or exclude channel 6\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CH6_A { + #[doc = "0: Exclude"] + EXCLUDED = 0, + #[doc = "1: Include"] + INCLUDED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CH6_A) -> Self { + variant as u8 != 0 + } +} +impl CH6_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CH6_A { + match self.bits { + false => CH6_A::EXCLUDED, + true => CH6_A::INCLUDED, + } + } + #[doc = "Checks if the value of the field is `EXCLUDED`"] + #[inline(always)] + pub fn is_excluded(&self) -> bool { + *self == CH6_A::EXCLUDED + } + #[doc = "Checks if the value of the field is `INCLUDED`"] + #[inline(always)] + pub fn is_included(&self) -> bool { + *self == CH6_A::INCLUDED + } +} +#[doc = "Field `CH6` writer - Include or exclude channel 6"] +pub type CH6_W<'a, const O: u8> = crate::BitWriter<'a, u32, CHG_SPEC, CH6_A, O>; +impl<'a, const O: u8> CH6_W<'a, O> { + #[doc = "Exclude"] + #[inline(always)] + pub fn excluded(self) -> &'a mut W { + self.variant(CH6_A::EXCLUDED) + } + #[doc = "Include"] + #[inline(always)] + pub fn included(self) -> &'a mut W { + self.variant(CH6_A::INCLUDED) + } +} +#[doc = "Field `CH7` reader - Include or exclude channel 7"] +pub type CH7_R = crate::BitReader; +#[doc = "Include or exclude channel 7\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CH7_A { + #[doc = "0: Exclude"] + EXCLUDED = 0, + #[doc = "1: Include"] + INCLUDED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CH7_A) -> Self { + variant as u8 != 0 + } +} +impl CH7_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CH7_A { + match self.bits { + false => CH7_A::EXCLUDED, + true => CH7_A::INCLUDED, + } + } + #[doc = "Checks if the value of the field is `EXCLUDED`"] + #[inline(always)] + pub fn is_excluded(&self) -> bool { + *self == CH7_A::EXCLUDED + } + #[doc = "Checks if the value of the field is `INCLUDED`"] + #[inline(always)] + pub fn is_included(&self) -> bool { + *self == CH7_A::INCLUDED + } +} +#[doc = "Field `CH7` writer - Include or exclude channel 7"] +pub type CH7_W<'a, const O: u8> = crate::BitWriter<'a, u32, CHG_SPEC, CH7_A, O>; +impl<'a, const O: u8> CH7_W<'a, O> { + #[doc = "Exclude"] + #[inline(always)] + pub fn excluded(self) -> &'a mut W { + self.variant(CH7_A::EXCLUDED) + } + #[doc = "Include"] + #[inline(always)] + pub fn included(self) -> &'a mut W { + self.variant(CH7_A::INCLUDED) + } +} +#[doc = "Field `CH8` reader - Include or exclude channel 8"] +pub type CH8_R = crate::BitReader; +#[doc = "Include or exclude channel 8\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CH8_A { + #[doc = "0: Exclude"] + EXCLUDED = 0, + #[doc = "1: Include"] + INCLUDED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CH8_A) -> Self { + variant as u8 != 0 + } +} +impl CH8_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CH8_A { + match self.bits { + false => CH8_A::EXCLUDED, + true => CH8_A::INCLUDED, + } + } + #[doc = "Checks if the value of the field is `EXCLUDED`"] + #[inline(always)] + pub fn is_excluded(&self) -> bool { + *self == CH8_A::EXCLUDED + } + #[doc = "Checks if the value of the field is `INCLUDED`"] + #[inline(always)] + pub fn is_included(&self) -> bool { + *self == CH8_A::INCLUDED + } +} +#[doc = "Field `CH8` writer - Include or exclude channel 8"] +pub type CH8_W<'a, const O: u8> = crate::BitWriter<'a, u32, CHG_SPEC, CH8_A, O>; +impl<'a, const O: u8> CH8_W<'a, O> { + #[doc = "Exclude"] + #[inline(always)] + pub fn excluded(self) -> &'a mut W { + self.variant(CH8_A::EXCLUDED) + } + #[doc = "Include"] + #[inline(always)] + pub fn included(self) -> &'a mut W { + self.variant(CH8_A::INCLUDED) + } +} +#[doc = "Field `CH9` reader - Include or exclude channel 9"] +pub type CH9_R = crate::BitReader; +#[doc = "Include or exclude channel 9\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CH9_A { + #[doc = "0: Exclude"] + EXCLUDED = 0, + #[doc = "1: Include"] + INCLUDED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CH9_A) -> Self { + variant as u8 != 0 + } +} +impl CH9_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CH9_A { + match self.bits { + false => CH9_A::EXCLUDED, + true => CH9_A::INCLUDED, + } + } + #[doc = "Checks if the value of the field is `EXCLUDED`"] + #[inline(always)] + pub fn is_excluded(&self) -> bool { + *self == CH9_A::EXCLUDED + } + #[doc = "Checks if the value of the field is `INCLUDED`"] + #[inline(always)] + pub fn is_included(&self) -> bool { + *self == CH9_A::INCLUDED + } +} +#[doc = "Field `CH9` writer - Include or exclude channel 9"] +pub type CH9_W<'a, const O: u8> = crate::BitWriter<'a, u32, CHG_SPEC, CH9_A, O>; +impl<'a, const O: u8> CH9_W<'a, O> { + #[doc = "Exclude"] + #[inline(always)] + pub fn excluded(self) -> &'a mut W { + self.variant(CH9_A::EXCLUDED) + } + #[doc = "Include"] + #[inline(always)] + pub fn included(self) -> &'a mut W { + self.variant(CH9_A::INCLUDED) + } +} +#[doc = "Field `CH10` reader - Include or exclude channel 10"] +pub type CH10_R = crate::BitReader; +#[doc = "Include or exclude channel 10\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CH10_A { + #[doc = "0: Exclude"] + EXCLUDED = 0, + #[doc = "1: Include"] + INCLUDED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CH10_A) -> Self { + variant as u8 != 0 + } +} +impl CH10_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CH10_A { + match self.bits { + false => CH10_A::EXCLUDED, + true => CH10_A::INCLUDED, + } + } + #[doc = "Checks if the value of the field is `EXCLUDED`"] + #[inline(always)] + pub fn is_excluded(&self) -> bool { + *self == CH10_A::EXCLUDED + } + #[doc = "Checks if the value of the field is `INCLUDED`"] + #[inline(always)] + pub fn is_included(&self) -> bool { + *self == CH10_A::INCLUDED + } +} +#[doc = "Field `CH10` writer - Include or exclude channel 10"] +pub type CH10_W<'a, const O: u8> = crate::BitWriter<'a, u32, CHG_SPEC, CH10_A, O>; +impl<'a, const O: u8> CH10_W<'a, O> { + #[doc = "Exclude"] + #[inline(always)] + pub fn excluded(self) -> &'a mut W { + self.variant(CH10_A::EXCLUDED) + } + #[doc = "Include"] + #[inline(always)] + pub fn included(self) -> &'a mut W { + self.variant(CH10_A::INCLUDED) + } +} +#[doc = "Field `CH11` reader - Include or exclude channel 11"] +pub type CH11_R = crate::BitReader; +#[doc = "Include or exclude channel 11\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CH11_A { + #[doc = "0: Exclude"] + EXCLUDED = 0, + #[doc = "1: Include"] + INCLUDED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CH11_A) -> Self { + variant as u8 != 0 + } +} +impl CH11_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CH11_A { + match self.bits { + false => CH11_A::EXCLUDED, + true => CH11_A::INCLUDED, + } + } + #[doc = "Checks if the value of the field is `EXCLUDED`"] + #[inline(always)] + pub fn is_excluded(&self) -> bool { + *self == CH11_A::EXCLUDED + } + #[doc = "Checks if the value of the field is `INCLUDED`"] + #[inline(always)] + pub fn is_included(&self) -> bool { + *self == CH11_A::INCLUDED + } +} +#[doc = "Field `CH11` writer - Include or exclude channel 11"] +pub type CH11_W<'a, const O: u8> = crate::BitWriter<'a, u32, CHG_SPEC, CH11_A, O>; +impl<'a, const O: u8> CH11_W<'a, O> { + #[doc = "Exclude"] + #[inline(always)] + pub fn excluded(self) -> &'a mut W { + self.variant(CH11_A::EXCLUDED) + } + #[doc = "Include"] + #[inline(always)] + pub fn included(self) -> &'a mut W { + self.variant(CH11_A::INCLUDED) + } +} +#[doc = "Field `CH12` reader - Include or exclude channel 12"] +pub type CH12_R = crate::BitReader; +#[doc = "Include or exclude channel 12\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CH12_A { + #[doc = "0: Exclude"] + EXCLUDED = 0, + #[doc = "1: Include"] + INCLUDED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CH12_A) -> Self { + variant as u8 != 0 + } +} +impl CH12_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CH12_A { + match self.bits { + false => CH12_A::EXCLUDED, + true => CH12_A::INCLUDED, + } + } + #[doc = "Checks if the value of the field is `EXCLUDED`"] + #[inline(always)] + pub fn is_excluded(&self) -> bool { + *self == CH12_A::EXCLUDED + } + #[doc = "Checks if the value of the field is `INCLUDED`"] + #[inline(always)] + pub fn is_included(&self) -> bool { + *self == CH12_A::INCLUDED + } +} +#[doc = "Field `CH12` writer - Include or exclude channel 12"] +pub type CH12_W<'a, const O: u8> = crate::BitWriter<'a, u32, CHG_SPEC, CH12_A, O>; +impl<'a, const O: u8> CH12_W<'a, O> { + #[doc = "Exclude"] + #[inline(always)] + pub fn excluded(self) -> &'a mut W { + self.variant(CH12_A::EXCLUDED) + } + #[doc = "Include"] + #[inline(always)] + pub fn included(self) -> &'a mut W { + self.variant(CH12_A::INCLUDED) + } +} +#[doc = "Field `CH13` reader - Include or exclude channel 13"] +pub type CH13_R = crate::BitReader; +#[doc = "Include or exclude channel 13\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CH13_A { + #[doc = "0: Exclude"] + EXCLUDED = 0, + #[doc = "1: Include"] + INCLUDED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CH13_A) -> Self { + variant as u8 != 0 + } +} +impl CH13_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CH13_A { + match self.bits { + false => CH13_A::EXCLUDED, + true => CH13_A::INCLUDED, + } + } + #[doc = "Checks if the value of the field is `EXCLUDED`"] + #[inline(always)] + pub fn is_excluded(&self) -> bool { + *self == CH13_A::EXCLUDED + } + #[doc = "Checks if the value of the field is `INCLUDED`"] + #[inline(always)] + pub fn is_included(&self) -> bool { + *self == CH13_A::INCLUDED + } +} +#[doc = "Field `CH13` writer - Include or exclude channel 13"] +pub type CH13_W<'a, const O: u8> = crate::BitWriter<'a, u32, CHG_SPEC, CH13_A, O>; +impl<'a, const O: u8> CH13_W<'a, O> { + #[doc = "Exclude"] + #[inline(always)] + pub fn excluded(self) -> &'a mut W { + self.variant(CH13_A::EXCLUDED) + } + #[doc = "Include"] + #[inline(always)] + pub fn included(self) -> &'a mut W { + self.variant(CH13_A::INCLUDED) + } +} +#[doc = "Field `CH14` reader - Include or exclude channel 14"] +pub type CH14_R = crate::BitReader; +#[doc = "Include or exclude channel 14\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CH14_A { + #[doc = "0: Exclude"] + EXCLUDED = 0, + #[doc = "1: Include"] + INCLUDED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CH14_A) -> Self { + variant as u8 != 0 + } +} +impl CH14_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CH14_A { + match self.bits { + false => CH14_A::EXCLUDED, + true => CH14_A::INCLUDED, + } + } + #[doc = "Checks if the value of the field is `EXCLUDED`"] + #[inline(always)] + pub fn is_excluded(&self) -> bool { + *self == CH14_A::EXCLUDED + } + #[doc = "Checks if the value of the field is `INCLUDED`"] + #[inline(always)] + pub fn is_included(&self) -> bool { + *self == CH14_A::INCLUDED + } +} +#[doc = "Field `CH14` writer - Include or exclude channel 14"] +pub type CH14_W<'a, const O: u8> = crate::BitWriter<'a, u32, CHG_SPEC, CH14_A, O>; +impl<'a, const O: u8> CH14_W<'a, O> { + #[doc = "Exclude"] + #[inline(always)] + pub fn excluded(self) -> &'a mut W { + self.variant(CH14_A::EXCLUDED) + } + #[doc = "Include"] + #[inline(always)] + pub fn included(self) -> &'a mut W { + self.variant(CH14_A::INCLUDED) + } +} +#[doc = "Field `CH15` reader - Include or exclude channel 15"] +pub type CH15_R = crate::BitReader; +#[doc = "Include or exclude channel 15\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CH15_A { + #[doc = "0: Exclude"] + EXCLUDED = 0, + #[doc = "1: Include"] + INCLUDED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CH15_A) -> Self { + variant as u8 != 0 + } +} +impl CH15_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CH15_A { + match self.bits { + false => CH15_A::EXCLUDED, + true => CH15_A::INCLUDED, + } + } + #[doc = "Checks if the value of the field is `EXCLUDED`"] + #[inline(always)] + pub fn is_excluded(&self) -> bool { + *self == CH15_A::EXCLUDED + } + #[doc = "Checks if the value of the field is `INCLUDED`"] + #[inline(always)] + pub fn is_included(&self) -> bool { + *self == CH15_A::INCLUDED + } +} +#[doc = "Field `CH15` writer - Include or exclude channel 15"] +pub type CH15_W<'a, const O: u8> = crate::BitWriter<'a, u32, CHG_SPEC, CH15_A, O>; +impl<'a, const O: u8> CH15_W<'a, O> { + #[doc = "Exclude"] + #[inline(always)] + pub fn excluded(self) -> &'a mut W { + self.variant(CH15_A::EXCLUDED) + } + #[doc = "Include"] + #[inline(always)] + pub fn included(self) -> &'a mut W { + self.variant(CH15_A::INCLUDED) + } +} +impl R { + #[doc = "Bit 0 - Include or exclude channel 0"] + #[inline(always)] + pub fn ch0(&self) -> CH0_R { + CH0_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Include or exclude channel 1"] + #[inline(always)] + pub fn ch1(&self) -> CH1_R { + CH1_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Include or exclude channel 2"] + #[inline(always)] + pub fn ch2(&self) -> CH2_R { + CH2_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Include or exclude channel 3"] + #[inline(always)] + pub fn ch3(&self) -> CH3_R { + CH3_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Include or exclude channel 4"] + #[inline(always)] + pub fn ch4(&self) -> CH4_R { + CH4_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Include or exclude channel 5"] + #[inline(always)] + pub fn ch5(&self) -> CH5_R { + CH5_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Include or exclude channel 6"] + #[inline(always)] + pub fn ch6(&self) -> CH6_R { + CH6_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Include or exclude channel 7"] + #[inline(always)] + pub fn ch7(&self) -> CH7_R { + CH7_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Include or exclude channel 8"] + #[inline(always)] + pub fn ch8(&self) -> CH8_R { + CH8_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Include or exclude channel 9"] + #[inline(always)] + pub fn ch9(&self) -> CH9_R { + CH9_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Include or exclude channel 10"] + #[inline(always)] + pub fn ch10(&self) -> CH10_R { + CH10_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Include or exclude channel 11"] + #[inline(always)] + pub fn ch11(&self) -> CH11_R { + CH11_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Include or exclude channel 12"] + #[inline(always)] + pub fn ch12(&self) -> CH12_R { + CH12_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Include or exclude channel 13"] + #[inline(always)] + pub fn ch13(&self) -> CH13_R { + CH13_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Include or exclude channel 14"] + #[inline(always)] + pub fn ch14(&self) -> CH14_R { + CH14_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Include or exclude channel 15"] + #[inline(always)] + pub fn ch15(&self) -> CH15_R { + CH15_R::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Include or exclude channel 0"] + #[inline(always)] + pub fn ch0(&mut self) -> CH0_W<0> { + CH0_W::new(self) + } + #[doc = "Bit 1 - Include or exclude channel 1"] + #[inline(always)] + pub fn ch1(&mut self) -> CH1_W<1> { + CH1_W::new(self) + } + #[doc = "Bit 2 - Include or exclude channel 2"] + #[inline(always)] + pub fn ch2(&mut self) -> CH2_W<2> { + CH2_W::new(self) + } + #[doc = "Bit 3 - Include or exclude channel 3"] + #[inline(always)] + pub fn ch3(&mut self) -> CH3_W<3> { + CH3_W::new(self) + } + #[doc = "Bit 4 - Include or exclude channel 4"] + #[inline(always)] + pub fn ch4(&mut self) -> CH4_W<4> { + CH4_W::new(self) + } + #[doc = "Bit 5 - Include or exclude channel 5"] + #[inline(always)] + pub fn ch5(&mut self) -> CH5_W<5> { + CH5_W::new(self) + } + #[doc = "Bit 6 - Include or exclude channel 6"] + #[inline(always)] + pub fn ch6(&mut self) -> CH6_W<6> { + CH6_W::new(self) + } + #[doc = "Bit 7 - Include or exclude channel 7"] + #[inline(always)] + pub fn ch7(&mut self) -> CH7_W<7> { + CH7_W::new(self) + } + #[doc = "Bit 8 - Include or exclude channel 8"] + #[inline(always)] + pub fn ch8(&mut self) -> CH8_W<8> { + CH8_W::new(self) + } + #[doc = "Bit 9 - Include or exclude channel 9"] + #[inline(always)] + pub fn ch9(&mut self) -> CH9_W<9> { + CH9_W::new(self) + } + #[doc = "Bit 10 - Include or exclude channel 10"] + #[inline(always)] + pub fn ch10(&mut self) -> CH10_W<10> { + CH10_W::new(self) + } + #[doc = "Bit 11 - Include or exclude channel 11"] + #[inline(always)] + pub fn ch11(&mut self) -> CH11_W<11> { + CH11_W::new(self) + } + #[doc = "Bit 12 - Include or exclude channel 12"] + #[inline(always)] + pub fn ch12(&mut self) -> CH12_W<12> { + CH12_W::new(self) + } + #[doc = "Bit 13 - Include or exclude channel 13"] + #[inline(always)] + pub fn ch13(&mut self) -> CH13_W<13> { + CH13_W::new(self) + } + #[doc = "Bit 14 - Include or exclude channel 14"] + #[inline(always)] + pub fn ch14(&mut self) -> CH14_W<14> { + CH14_W::new(self) + } + #[doc = "Bit 15 - Include or exclude channel 15"] + #[inline(always)] + pub fn ch15(&mut self) -> CH15_W<15> { + CH15_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Description collection: Channel group n Note: Writes to this register are ignored if either SUBSCRIBE_CHG\\[n\\].EN or SUBSCRIBE_CHG\\[n\\].DIS is enabled\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [chg](index.html) module"] +pub struct CHG_SPEC; +impl crate::RegisterSpec for CHG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [chg::R](R) reader structure"] +impl crate::Readable for CHG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [chg::W](W) writer structure"] +impl crate::Writable for CHG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CHG[%s] +to value 0"] +impl crate::Resettable for CHG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/dppic_ns/subscribe_chg.rs b/pacs/nrf9120-pac/src/dppic_ns/subscribe_chg.rs new file mode 100644 index 00000000..702fca30 --- /dev/null +++ b/pacs/nrf9120-pac/src/dppic_ns/subscribe_chg.rs @@ -0,0 +1,16 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct SUBSCRIBE_CHG { + #[doc = "0x00 - Description cluster: Subscribe configuration for task CHG\\[n\\].EN"] + pub en: EN, + #[doc = "0x04 - Description cluster: Subscribe configuration for task CHG\\[n\\].DIS"] + pub dis: DIS, +} +#[doc = "EN (rw) register accessor: an alias for `Reg`"] +pub type EN = crate::Reg; +#[doc = "Description cluster: Subscribe configuration for task CHG\\[n\\].EN"] +pub mod en; +#[doc = "DIS (rw) register accessor: an alias for `Reg`"] +pub type DIS = crate::Reg; +#[doc = "Description cluster: Subscribe configuration for task CHG\\[n\\].DIS"] +pub mod dis; diff --git a/pacs/nrf9120-pac/src/dppic_ns/subscribe_chg/dis.rs b/pacs/nrf9120-pac/src/dppic_ns/subscribe_chg/dis.rs new file mode 100644 index 00000000..6da54cc4 --- /dev/null +++ b/pacs/nrf9120-pac/src/dppic_ns/subscribe_chg/dis.rs @@ -0,0 +1,140 @@ +#[doc = "Register `DIS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DIS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CHIDX` reader - DPPI channel that task CHG\\[n\\].DIS will subscribe to"] +pub type CHIDX_R = crate::FieldReader; +#[doc = "Field `CHIDX` writer - DPPI channel that task CHG\\[n\\].DIS will subscribe to"] +pub type CHIDX_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DIS_SPEC, u8, u8, 8, O>; +#[doc = "Field `EN` reader - "] +pub type EN_R = crate::BitReader; +#[doc = "\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum EN_A { + #[doc = "0: Disable subscription"] + DISABLED = 0, + #[doc = "1: Enable subscription"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: EN_A) -> Self { + variant as u8 != 0 + } +} +impl EN_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EN_A { + match self.bits { + false => EN_A::DISABLED, + true => EN_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == EN_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == EN_A::ENABLED + } +} +#[doc = "Field `EN` writer - "] +pub type EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIS_SPEC, EN_A, O>; +impl<'a, const O: u8> EN_W<'a, O> { + #[doc = "Disable subscription"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(EN_A::DISABLED) + } + #[doc = "Enable subscription"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(EN_A::ENABLED) + } +} +impl R { + #[doc = "Bits 0:7 - DPPI channel that task CHG\\[n\\].DIS will subscribe to"] + #[inline(always)] + pub fn chidx(&self) -> CHIDX_R { + CHIDX_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&self) -> EN_R { + EN_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:7 - DPPI channel that task CHG\\[n\\].DIS will subscribe to"] + #[inline(always)] + pub fn chidx(&mut self) -> CHIDX_W<0> { + CHIDX_W::new(self) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&mut self) -> EN_W<31> { + EN_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Description cluster: Subscribe configuration for task CHG\\[n\\].DIS\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dis](index.html) module"] +pub struct DIS_SPEC; +impl crate::RegisterSpec for DIS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dis::R](R) reader structure"] +impl crate::Readable for DIS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dis::W](W) writer structure"] +impl crate::Writable for DIS_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DIS to value 0"] +impl crate::Resettable for DIS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/dppic_ns/subscribe_chg/en.rs b/pacs/nrf9120-pac/src/dppic_ns/subscribe_chg/en.rs new file mode 100644 index 00000000..136544b3 --- /dev/null +++ b/pacs/nrf9120-pac/src/dppic_ns/subscribe_chg/en.rs @@ -0,0 +1,140 @@ +#[doc = "Register `EN` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EN` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CHIDX` reader - DPPI channel that task CHG\\[n\\].EN will subscribe to"] +pub type CHIDX_R = crate::FieldReader; +#[doc = "Field `CHIDX` writer - DPPI channel that task CHG\\[n\\].EN will subscribe to"] +pub type CHIDX_W<'a, const O: u8> = crate::FieldWriter<'a, u32, EN_SPEC, u8, u8, 8, O>; +#[doc = "Field `EN` reader - "] +pub type EN_R = crate::BitReader; +#[doc = "\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum EN_A { + #[doc = "0: Disable subscription"] + DISABLED = 0, + #[doc = "1: Enable subscription"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: EN_A) -> Self { + variant as u8 != 0 + } +} +impl EN_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EN_A { + match self.bits { + false => EN_A::DISABLED, + true => EN_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == EN_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == EN_A::ENABLED + } +} +#[doc = "Field `EN` writer - "] +pub type EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, EN_SPEC, EN_A, O>; +impl<'a, const O: u8> EN_W<'a, O> { + #[doc = "Disable subscription"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(EN_A::DISABLED) + } + #[doc = "Enable subscription"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(EN_A::ENABLED) + } +} +impl R { + #[doc = "Bits 0:7 - DPPI channel that task CHG\\[n\\].EN will subscribe to"] + #[inline(always)] + pub fn chidx(&self) -> CHIDX_R { + CHIDX_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&self) -> EN_R { + EN_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:7 - DPPI channel that task CHG\\[n\\].EN will subscribe to"] + #[inline(always)] + pub fn chidx(&mut self) -> CHIDX_W<0> { + CHIDX_W::new(self) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&mut self) -> EN_W<31> { + EN_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Description cluster: Subscribe configuration for task CHG\\[n\\].EN\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [en](index.html) module"] +pub struct EN_SPEC; +impl crate::RegisterSpec for EN_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [en::R](R) reader structure"] +impl crate::Readable for EN_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [en::W](W) writer structure"] +impl crate::Writable for EN_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EN to value 0"] +impl crate::Resettable for EN_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/dppic_ns/tasks_chg.rs b/pacs/nrf9120-pac/src/dppic_ns/tasks_chg.rs new file mode 100644 index 00000000..9915b809 --- /dev/null +++ b/pacs/nrf9120-pac/src/dppic_ns/tasks_chg.rs @@ -0,0 +1,16 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct TASKS_CHG { + #[doc = "0x00 - Description cluster: Enable channel group n"] + pub en: EN, + #[doc = "0x04 - Description cluster: Disable channel group n"] + pub dis: DIS, +} +#[doc = "EN (w) register accessor: an alias for `Reg`"] +pub type EN = crate::Reg; +#[doc = "Description cluster: Enable channel group n"] +pub mod en; +#[doc = "DIS (w) register accessor: an alias for `Reg`"] +pub type DIS = crate::Reg; +#[doc = "Description cluster: Disable channel group n"] +pub mod dis; diff --git a/pacs/nrf9120-pac/src/dppic_ns/tasks_chg/dis.rs b/pacs/nrf9120-pac/src/dppic_ns/tasks_chg/dis.rs new file mode 100644 index 00000000..3348dff9 --- /dev/null +++ b/pacs/nrf9120-pac/src/dppic_ns/tasks_chg/dis.rs @@ -0,0 +1,71 @@ +#[doc = "Register `DIS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Disable channel group n\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum DIS_AW { + #[doc = "1: Trigger task"] + TRIGGER = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: DIS_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DIS` writer - Disable channel group n"] +pub type DIS_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIS_SPEC, DIS_AW, O>; +impl<'a, const O: u8> DIS_W<'a, O> { + #[doc = "Trigger task"] + #[inline(always)] + pub fn trigger(self) -> &'a mut W { + self.variant(DIS_AW::TRIGGER) + } +} +impl W { + #[doc = "Bit 0 - Disable channel group n"] + #[inline(always)] + pub fn dis(&mut self) -> DIS_W<0> { + DIS_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Description cluster: Disable channel group n\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dis](index.html) module"] +pub struct DIS_SPEC; +impl crate::RegisterSpec for DIS_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [dis::W](W) writer structure"] +impl crate::Writable for DIS_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DIS to value 0"] +impl crate::Resettable for DIS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/dppic_ns/tasks_chg/en.rs b/pacs/nrf9120-pac/src/dppic_ns/tasks_chg/en.rs new file mode 100644 index 00000000..3ad0ec0c --- /dev/null +++ b/pacs/nrf9120-pac/src/dppic_ns/tasks_chg/en.rs @@ -0,0 +1,71 @@ +#[doc = "Register `EN` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Enable channel group n\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum EN_AW { + #[doc = "1: Trigger task"] + TRIGGER = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: EN_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `EN` writer - Enable channel group n"] +pub type EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, EN_SPEC, EN_AW, O>; +impl<'a, const O: u8> EN_W<'a, O> { + #[doc = "Trigger task"] + #[inline(always)] + pub fn trigger(self) -> &'a mut W { + self.variant(EN_AW::TRIGGER) + } +} +impl W { + #[doc = "Bit 0 - Enable channel group n"] + #[inline(always)] + pub fn en(&mut self) -> EN_W<0> { + EN_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Description cluster: Enable channel group n\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [en](index.html) module"] +pub struct EN_SPEC; +impl crate::RegisterSpec for EN_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [en::W](W) writer structure"] +impl crate::Writable for EN_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EN to value 0"] +impl crate::Resettable for EN_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/egu0_ns.rs b/pacs/nrf9120-pac/src/egu0_ns.rs new file mode 100644 index 00000000..a7981723 --- /dev/null +++ b/pacs/nrf9120-pac/src/egu0_ns.rs @@ -0,0 +1,54 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00..0x40 - Description collection: Trigger n for triggering the corresponding TRIGGERED\\[n\\] +event"] + pub tasks_trigger: [TASKS_TRIGGER; 16], + _reserved1: [u8; 0x40], + #[doc = "0x80..0xc0 - Description collection: Subscribe configuration for task TRIGGER\\[n\\]"] + pub subscribe_trigger: [SUBSCRIBE_TRIGGER; 16], + _reserved2: [u8; 0x40], + #[doc = "0x100..0x140 - Description collection: Event number n generated by triggering the corresponding TRIGGER\\[n\\] +task"] + pub events_triggered: [EVENTS_TRIGGERED; 16], + _reserved3: [u8; 0x40], + #[doc = "0x180..0x1c0 - Description collection: Publish configuration for event TRIGGERED\\[n\\]"] + pub publish_triggered: [PUBLISH_TRIGGERED; 16], + _reserved4: [u8; 0x0140], + #[doc = "0x300 - Enable or disable interrupt"] + pub inten: INTEN, + #[doc = "0x304 - Enable interrupt"] + pub intenset: INTENSET, + #[doc = "0x308 - Disable interrupt"] + pub intenclr: INTENCLR, +} +#[doc = "TASKS_TRIGGER (w) register accessor: an alias for `Reg`"] +pub type TASKS_TRIGGER = crate::Reg; +#[doc = "Description collection: Trigger n for triggering the corresponding TRIGGERED\\[n\\] +event"] +pub mod tasks_trigger; +#[doc = "SUBSCRIBE_TRIGGER (rw) register accessor: an alias for `Reg`"] +pub type SUBSCRIBE_TRIGGER = crate::Reg; +#[doc = "Description collection: Subscribe configuration for task TRIGGER\\[n\\]"] +pub mod subscribe_trigger; +#[doc = "EVENTS_TRIGGERED (rw) register accessor: an alias for `Reg`"] +pub type EVENTS_TRIGGERED = crate::Reg; +#[doc = "Description collection: Event number n generated by triggering the corresponding TRIGGER\\[n\\] +task"] +pub mod events_triggered; +#[doc = "PUBLISH_TRIGGERED (rw) register accessor: an alias for `Reg`"] +pub type PUBLISH_TRIGGERED = crate::Reg; +#[doc = "Description collection: Publish configuration for event TRIGGERED\\[n\\]"] +pub mod publish_triggered; +#[doc = "INTEN (rw) register accessor: an alias for `Reg`"] +pub type INTEN = crate::Reg; +#[doc = "Enable or disable interrupt"] +pub mod inten; +#[doc = "INTENSET (rw) register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "Enable interrupt"] +pub mod intenset; +#[doc = "INTENCLR (rw) register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "Disable interrupt"] +pub mod intenclr; diff --git a/pacs/nrf9120-pac/src/egu0_ns/events_triggered.rs b/pacs/nrf9120-pac/src/egu0_ns/events_triggered.rs new file mode 100644 index 00000000..29de2292 --- /dev/null +++ b/pacs/nrf9120-pac/src/egu0_ns/events_triggered.rs @@ -0,0 +1,134 @@ +#[doc = "Register `EVENTS_TRIGGERED[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVENTS_TRIGGERED[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `EVENTS_TRIGGERED` reader - Event number n generated by triggering the corresponding TRIGGER\\[n\\] +task"] +pub type EVENTS_TRIGGERED_R = crate::BitReader; +#[doc = "Event number n generated by triggering the corresponding TRIGGER\\[n\\] +task\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum EVENTS_TRIGGERED_A { + #[doc = "0: Event not generated"] + NOT_GENERATED = 0, + #[doc = "1: Event generated"] + GENERATED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: EVENTS_TRIGGERED_A) -> Self { + variant as u8 != 0 + } +} +impl EVENTS_TRIGGERED_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EVENTS_TRIGGERED_A { + match self.bits { + false => EVENTS_TRIGGERED_A::NOT_GENERATED, + true => EVENTS_TRIGGERED_A::GENERATED, + } + } + #[doc = "Checks if the value of the field is `NOT_GENERATED`"] + #[inline(always)] + pub fn is_not_generated(&self) -> bool { + *self == EVENTS_TRIGGERED_A::NOT_GENERATED + } + #[doc = "Checks if the value of the field is `GENERATED`"] + #[inline(always)] + pub fn is_generated(&self) -> bool { + *self == EVENTS_TRIGGERED_A::GENERATED + } +} +#[doc = "Field `EVENTS_TRIGGERED` writer - Event number n generated by triggering the corresponding TRIGGER\\[n\\] +task"] +pub type EVENTS_TRIGGERED_W<'a, const O: u8> = + crate::BitWriter<'a, u32, EVENTS_TRIGGERED_SPEC, EVENTS_TRIGGERED_A, O>; +impl<'a, const O: u8> EVENTS_TRIGGERED_W<'a, O> { + #[doc = "Event not generated"] + #[inline(always)] + pub fn not_generated(self) -> &'a mut W { + self.variant(EVENTS_TRIGGERED_A::NOT_GENERATED) + } + #[doc = "Event generated"] + #[inline(always)] + pub fn generated(self) -> &'a mut W { + self.variant(EVENTS_TRIGGERED_A::GENERATED) + } +} +impl R { + #[doc = "Bit 0 - Event number n generated by triggering the corresponding TRIGGER\\[n\\] +task"] + #[inline(always)] + pub fn events_triggered(&self) -> EVENTS_TRIGGERED_R { + EVENTS_TRIGGERED_R::new((self.bits & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Event number n generated by triggering the corresponding TRIGGER\\[n\\] +task"] + #[inline(always)] + pub fn events_triggered(&mut self) -> EVENTS_TRIGGERED_W<0> { + EVENTS_TRIGGERED_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Description collection: Event number n generated by triggering the corresponding TRIGGER\\[n\\] +task\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [events_triggered](index.html) module"] +pub struct EVENTS_TRIGGERED_SPEC; +impl crate::RegisterSpec for EVENTS_TRIGGERED_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [events_triggered::R](R) reader structure"] +impl crate::Readable for EVENTS_TRIGGERED_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [events_triggered::W](W) writer structure"] +impl crate::Writable for EVENTS_TRIGGERED_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EVENTS_TRIGGERED[%s] +to value 0"] +impl crate::Resettable for EVENTS_TRIGGERED_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/egu0_ns/inten.rs b/pacs/nrf9120-pac/src/egu0_ns/inten.rs new file mode 100644 index 00000000..56a3128f --- /dev/null +++ b/pacs/nrf9120-pac/src/egu0_ns/inten.rs @@ -0,0 +1,1026 @@ +#[doc = "Register `INTEN` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTEN` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `TRIGGERED0` reader - Enable or disable interrupt for event TRIGGERED\\[0\\]"] +pub type TRIGGERED0_R = crate::BitReader; +#[doc = "Enable or disable interrupt for event TRIGGERED\\[0\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum TRIGGERED0_A { + #[doc = "0: Disable"] + DISABLED = 0, + #[doc = "1: Enable"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TRIGGERED0_A) -> Self { + variant as u8 != 0 + } +} +impl TRIGGERED0_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> TRIGGERED0_A { + match self.bits { + false => TRIGGERED0_A::DISABLED, + true => TRIGGERED0_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == TRIGGERED0_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == TRIGGERED0_A::ENABLED + } +} +#[doc = "Field `TRIGGERED0` writer - Enable or disable interrupt for event TRIGGERED\\[0\\]"] +pub type TRIGGERED0_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTEN_SPEC, TRIGGERED0_A, O>; +impl<'a, const O: u8> TRIGGERED0_W<'a, O> { + #[doc = "Disable"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(TRIGGERED0_A::DISABLED) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(TRIGGERED0_A::ENABLED) + } +} +#[doc = "Field `TRIGGERED1` reader - Enable or disable interrupt for event TRIGGERED\\[1\\]"] +pub type TRIGGERED1_R = crate::BitReader; +#[doc = "Enable or disable interrupt for event TRIGGERED\\[1\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum TRIGGERED1_A { + #[doc = "0: Disable"] + DISABLED = 0, + #[doc = "1: Enable"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TRIGGERED1_A) -> Self { + variant as u8 != 0 + } +} +impl TRIGGERED1_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> TRIGGERED1_A { + match self.bits { + false => TRIGGERED1_A::DISABLED, + true => TRIGGERED1_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == TRIGGERED1_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == TRIGGERED1_A::ENABLED + } +} +#[doc = "Field `TRIGGERED1` writer - Enable or disable interrupt for event TRIGGERED\\[1\\]"] +pub type TRIGGERED1_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTEN_SPEC, TRIGGERED1_A, O>; +impl<'a, const O: u8> TRIGGERED1_W<'a, O> { + #[doc = "Disable"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(TRIGGERED1_A::DISABLED) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(TRIGGERED1_A::ENABLED) + } +} +#[doc = "Field `TRIGGERED2` reader - Enable or disable interrupt for event TRIGGERED\\[2\\]"] +pub type TRIGGERED2_R = crate::BitReader; +#[doc = "Enable or disable interrupt for event TRIGGERED\\[2\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum TRIGGERED2_A { + #[doc = "0: Disable"] + DISABLED = 0, + #[doc = "1: Enable"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TRIGGERED2_A) -> Self { + variant as u8 != 0 + } +} +impl TRIGGERED2_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> TRIGGERED2_A { + match self.bits { + false => TRIGGERED2_A::DISABLED, + true => TRIGGERED2_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == TRIGGERED2_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == TRIGGERED2_A::ENABLED + } +} +#[doc = "Field `TRIGGERED2` writer - Enable or disable interrupt for event TRIGGERED\\[2\\]"] +pub type TRIGGERED2_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTEN_SPEC, TRIGGERED2_A, O>; +impl<'a, const O: u8> TRIGGERED2_W<'a, O> { + #[doc = "Disable"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(TRIGGERED2_A::DISABLED) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(TRIGGERED2_A::ENABLED) + } +} +#[doc = "Field `TRIGGERED3` reader - Enable or disable interrupt for event TRIGGERED\\[3\\]"] +pub type TRIGGERED3_R = crate::BitReader; +#[doc = "Enable or disable interrupt for event TRIGGERED\\[3\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum TRIGGERED3_A { + #[doc = "0: Disable"] + DISABLED = 0, + #[doc = "1: Enable"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TRIGGERED3_A) -> Self { + variant as u8 != 0 + } +} +impl TRIGGERED3_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> TRIGGERED3_A { + match self.bits { + false => TRIGGERED3_A::DISABLED, + true => TRIGGERED3_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == TRIGGERED3_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == TRIGGERED3_A::ENABLED + } +} +#[doc = "Field `TRIGGERED3` writer - Enable or disable interrupt for event TRIGGERED\\[3\\]"] +pub type TRIGGERED3_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTEN_SPEC, TRIGGERED3_A, O>; +impl<'a, const O: u8> TRIGGERED3_W<'a, O> { + #[doc = "Disable"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(TRIGGERED3_A::DISABLED) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(TRIGGERED3_A::ENABLED) + } +} +#[doc = "Field `TRIGGERED4` reader - Enable or disable interrupt for event TRIGGERED\\[4\\]"] +pub type TRIGGERED4_R = crate::BitReader; +#[doc = "Enable or disable interrupt for event TRIGGERED\\[4\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum TRIGGERED4_A { + #[doc = "0: Disable"] + DISABLED = 0, + #[doc = "1: Enable"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TRIGGERED4_A) -> Self { + variant as u8 != 0 + } +} +impl TRIGGERED4_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> TRIGGERED4_A { + match self.bits { + false => TRIGGERED4_A::DISABLED, + true => TRIGGERED4_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == TRIGGERED4_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == TRIGGERED4_A::ENABLED + } +} +#[doc = "Field `TRIGGERED4` writer - Enable or disable interrupt for event TRIGGERED\\[4\\]"] +pub type TRIGGERED4_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTEN_SPEC, TRIGGERED4_A, O>; +impl<'a, const O: u8> TRIGGERED4_W<'a, O> { + #[doc = "Disable"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(TRIGGERED4_A::DISABLED) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(TRIGGERED4_A::ENABLED) + } +} +#[doc = "Field `TRIGGERED5` reader - Enable or disable interrupt for event TRIGGERED\\[5\\]"] +pub type TRIGGERED5_R = crate::BitReader; +#[doc = "Enable or disable interrupt for event TRIGGERED\\[5\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum TRIGGERED5_A { + #[doc = "0: Disable"] + DISABLED = 0, + #[doc = "1: Enable"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TRIGGERED5_A) -> Self { + variant as u8 != 0 + } +} +impl TRIGGERED5_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> TRIGGERED5_A { + match self.bits { + false => TRIGGERED5_A::DISABLED, + true => TRIGGERED5_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == TRIGGERED5_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == TRIGGERED5_A::ENABLED + } +} +#[doc = "Field `TRIGGERED5` writer - Enable or disable interrupt for event TRIGGERED\\[5\\]"] +pub type TRIGGERED5_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTEN_SPEC, TRIGGERED5_A, O>; +impl<'a, const O: u8> TRIGGERED5_W<'a, O> { + #[doc = "Disable"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(TRIGGERED5_A::DISABLED) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(TRIGGERED5_A::ENABLED) + } +} +#[doc = "Field `TRIGGERED6` reader - Enable or disable interrupt for event TRIGGERED\\[6\\]"] +pub type TRIGGERED6_R = crate::BitReader; +#[doc = "Enable or disable interrupt for event TRIGGERED\\[6\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum TRIGGERED6_A { + #[doc = "0: Disable"] + DISABLED = 0, + #[doc = "1: Enable"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TRIGGERED6_A) -> Self { + variant as u8 != 0 + } +} +impl TRIGGERED6_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> TRIGGERED6_A { + match self.bits { + false => TRIGGERED6_A::DISABLED, + true => TRIGGERED6_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == TRIGGERED6_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == TRIGGERED6_A::ENABLED + } +} +#[doc = "Field `TRIGGERED6` writer - Enable or disable interrupt for event TRIGGERED\\[6\\]"] +pub type TRIGGERED6_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTEN_SPEC, TRIGGERED6_A, O>; +impl<'a, const O: u8> TRIGGERED6_W<'a, O> { + #[doc = "Disable"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(TRIGGERED6_A::DISABLED) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(TRIGGERED6_A::ENABLED) + } +} +#[doc = "Field `TRIGGERED7` reader - Enable or disable interrupt for event TRIGGERED\\[7\\]"] +pub type TRIGGERED7_R = crate::BitReader; +#[doc = "Enable or disable interrupt for event TRIGGERED\\[7\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum TRIGGERED7_A { + #[doc = "0: Disable"] + DISABLED = 0, + #[doc = "1: Enable"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TRIGGERED7_A) -> Self { + variant as u8 != 0 + } +} +impl TRIGGERED7_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> TRIGGERED7_A { + match self.bits { + false => TRIGGERED7_A::DISABLED, + true => TRIGGERED7_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == TRIGGERED7_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == TRIGGERED7_A::ENABLED + } +} +#[doc = "Field `TRIGGERED7` writer - Enable or disable interrupt for event TRIGGERED\\[7\\]"] +pub type TRIGGERED7_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTEN_SPEC, TRIGGERED7_A, O>; +impl<'a, const O: u8> TRIGGERED7_W<'a, O> { + #[doc = "Disable"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(TRIGGERED7_A::DISABLED) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(TRIGGERED7_A::ENABLED) + } +} +#[doc = "Field `TRIGGERED8` reader - Enable or disable interrupt for event TRIGGERED\\[8\\]"] +pub type TRIGGERED8_R = crate::BitReader; +#[doc = "Enable or disable interrupt for event TRIGGERED\\[8\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum TRIGGERED8_A { + #[doc = "0: Disable"] + DISABLED = 0, + #[doc = "1: Enable"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TRIGGERED8_A) -> Self { + variant as u8 != 0 + } +} +impl TRIGGERED8_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> TRIGGERED8_A { + match self.bits { + false => TRIGGERED8_A::DISABLED, + true => TRIGGERED8_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == TRIGGERED8_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == TRIGGERED8_A::ENABLED + } +} +#[doc = "Field `TRIGGERED8` writer - Enable or disable interrupt for event TRIGGERED\\[8\\]"] +pub type TRIGGERED8_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTEN_SPEC, TRIGGERED8_A, O>; +impl<'a, const O: u8> TRIGGERED8_W<'a, O> { + #[doc = "Disable"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(TRIGGERED8_A::DISABLED) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(TRIGGERED8_A::ENABLED) + } +} +#[doc = "Field `TRIGGERED9` reader - Enable or disable interrupt for event TRIGGERED\\[9\\]"] +pub type TRIGGERED9_R = crate::BitReader; +#[doc = "Enable or disable interrupt for event TRIGGERED\\[9\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum TRIGGERED9_A { + #[doc = "0: Disable"] + DISABLED = 0, + #[doc = "1: Enable"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TRIGGERED9_A) -> Self { + variant as u8 != 0 + } +} +impl TRIGGERED9_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> TRIGGERED9_A { + match self.bits { + false => TRIGGERED9_A::DISABLED, + true => TRIGGERED9_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == TRIGGERED9_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == TRIGGERED9_A::ENABLED + } +} +#[doc = "Field `TRIGGERED9` writer - Enable or disable interrupt for event TRIGGERED\\[9\\]"] +pub type TRIGGERED9_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTEN_SPEC, TRIGGERED9_A, O>; +impl<'a, const O: u8> TRIGGERED9_W<'a, O> { + #[doc = "Disable"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(TRIGGERED9_A::DISABLED) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(TRIGGERED9_A::ENABLED) + } +} +#[doc = "Field `TRIGGERED10` reader - Enable or disable interrupt for event TRIGGERED\\[10\\]"] +pub type TRIGGERED10_R = crate::BitReader; +#[doc = "Enable or disable interrupt for event TRIGGERED\\[10\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum TRIGGERED10_A { + #[doc = "0: Disable"] + DISABLED = 0, + #[doc = "1: Enable"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TRIGGERED10_A) -> Self { + variant as u8 != 0 + } +} +impl TRIGGERED10_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> TRIGGERED10_A { + match self.bits { + false => TRIGGERED10_A::DISABLED, + true => TRIGGERED10_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == TRIGGERED10_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == TRIGGERED10_A::ENABLED + } +} +#[doc = "Field `TRIGGERED10` writer - Enable or disable interrupt for event TRIGGERED\\[10\\]"] +pub type TRIGGERED10_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTEN_SPEC, TRIGGERED10_A, O>; +impl<'a, const O: u8> TRIGGERED10_W<'a, O> { + #[doc = "Disable"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(TRIGGERED10_A::DISABLED) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(TRIGGERED10_A::ENABLED) + } +} +#[doc = "Field `TRIGGERED11` reader - Enable or disable interrupt for event TRIGGERED\\[11\\]"] +pub type TRIGGERED11_R = crate::BitReader; +#[doc = "Enable or disable interrupt for event TRIGGERED\\[11\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum TRIGGERED11_A { + #[doc = "0: Disable"] + DISABLED = 0, + #[doc = "1: Enable"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TRIGGERED11_A) -> Self { + variant as u8 != 0 + } +} +impl TRIGGERED11_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> TRIGGERED11_A { + match self.bits { + false => TRIGGERED11_A::DISABLED, + true => TRIGGERED11_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == TRIGGERED11_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == TRIGGERED11_A::ENABLED + } +} +#[doc = "Field `TRIGGERED11` writer - Enable or disable interrupt for event TRIGGERED\\[11\\]"] +pub type TRIGGERED11_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTEN_SPEC, TRIGGERED11_A, O>; +impl<'a, const O: u8> TRIGGERED11_W<'a, O> { + #[doc = "Disable"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(TRIGGERED11_A::DISABLED) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(TRIGGERED11_A::ENABLED) + } +} +#[doc = "Field `TRIGGERED12` reader - Enable or disable interrupt for event TRIGGERED\\[12\\]"] +pub type TRIGGERED12_R = crate::BitReader; +#[doc = "Enable or disable interrupt for event TRIGGERED\\[12\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum TRIGGERED12_A { + #[doc = "0: Disable"] + DISABLED = 0, + #[doc = "1: Enable"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TRIGGERED12_A) -> Self { + variant as u8 != 0 + } +} +impl TRIGGERED12_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> TRIGGERED12_A { + match self.bits { + false => TRIGGERED12_A::DISABLED, + true => TRIGGERED12_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == TRIGGERED12_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == TRIGGERED12_A::ENABLED + } +} +#[doc = "Field `TRIGGERED12` writer - Enable or disable interrupt for event TRIGGERED\\[12\\]"] +pub type TRIGGERED12_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTEN_SPEC, TRIGGERED12_A, O>; +impl<'a, const O: u8> TRIGGERED12_W<'a, O> { + #[doc = "Disable"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(TRIGGERED12_A::DISABLED) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(TRIGGERED12_A::ENABLED) + } +} +#[doc = "Field `TRIGGERED13` reader - Enable or disable interrupt for event TRIGGERED\\[13\\]"] +pub type TRIGGERED13_R = crate::BitReader; +#[doc = "Enable or disable interrupt for event TRIGGERED\\[13\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum TRIGGERED13_A { + #[doc = "0: Disable"] + DISABLED = 0, + #[doc = "1: Enable"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TRIGGERED13_A) -> Self { + variant as u8 != 0 + } +} +impl TRIGGERED13_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> TRIGGERED13_A { + match self.bits { + false => TRIGGERED13_A::DISABLED, + true => TRIGGERED13_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == TRIGGERED13_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == TRIGGERED13_A::ENABLED + } +} +#[doc = "Field `TRIGGERED13` writer - Enable or disable interrupt for event TRIGGERED\\[13\\]"] +pub type TRIGGERED13_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTEN_SPEC, TRIGGERED13_A, O>; +impl<'a, const O: u8> TRIGGERED13_W<'a, O> { + #[doc = "Disable"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(TRIGGERED13_A::DISABLED) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(TRIGGERED13_A::ENABLED) + } +} +#[doc = "Field `TRIGGERED14` reader - Enable or disable interrupt for event TRIGGERED\\[14\\]"] +pub type TRIGGERED14_R = crate::BitReader; +#[doc = "Enable or disable interrupt for event TRIGGERED\\[14\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum TRIGGERED14_A { + #[doc = "0: Disable"] + DISABLED = 0, + #[doc = "1: Enable"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TRIGGERED14_A) -> Self { + variant as u8 != 0 + } +} +impl TRIGGERED14_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> TRIGGERED14_A { + match self.bits { + false => TRIGGERED14_A::DISABLED, + true => TRIGGERED14_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == TRIGGERED14_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == TRIGGERED14_A::ENABLED + } +} +#[doc = "Field `TRIGGERED14` writer - Enable or disable interrupt for event TRIGGERED\\[14\\]"] +pub type TRIGGERED14_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTEN_SPEC, TRIGGERED14_A, O>; +impl<'a, const O: u8> TRIGGERED14_W<'a, O> { + #[doc = "Disable"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(TRIGGERED14_A::DISABLED) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(TRIGGERED14_A::ENABLED) + } +} +#[doc = "Field `TRIGGERED15` reader - Enable or disable interrupt for event TRIGGERED\\[15\\]"] +pub type TRIGGERED15_R = crate::BitReader; +#[doc = "Enable or disable interrupt for event TRIGGERED\\[15\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum TRIGGERED15_A { + #[doc = "0: Disable"] + DISABLED = 0, + #[doc = "1: Enable"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TRIGGERED15_A) -> Self { + variant as u8 != 0 + } +} +impl TRIGGERED15_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> TRIGGERED15_A { + match self.bits { + false => TRIGGERED15_A::DISABLED, + true => TRIGGERED15_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == TRIGGERED15_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == TRIGGERED15_A::ENABLED + } +} +#[doc = "Field `TRIGGERED15` writer - Enable or disable interrupt for event TRIGGERED\\[15\\]"] +pub type TRIGGERED15_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTEN_SPEC, TRIGGERED15_A, O>; +impl<'a, const O: u8> TRIGGERED15_W<'a, O> { + #[doc = "Disable"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(TRIGGERED15_A::DISABLED) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(TRIGGERED15_A::ENABLED) + } +} +impl R { + #[doc = "Bit 0 - Enable or disable interrupt for event TRIGGERED\\[0\\]"] + #[inline(always)] + pub fn triggered0(&self) -> TRIGGERED0_R { + TRIGGERED0_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Enable or disable interrupt for event TRIGGERED\\[1\\]"] + #[inline(always)] + pub fn triggered1(&self) -> TRIGGERED1_R { + TRIGGERED1_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Enable or disable interrupt for event TRIGGERED\\[2\\]"] + #[inline(always)] + pub fn triggered2(&self) -> TRIGGERED2_R { + TRIGGERED2_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Enable or disable interrupt for event TRIGGERED\\[3\\]"] + #[inline(always)] + pub fn triggered3(&self) -> TRIGGERED3_R { + TRIGGERED3_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Enable or disable interrupt for event TRIGGERED\\[4\\]"] + #[inline(always)] + pub fn triggered4(&self) -> TRIGGERED4_R { + TRIGGERED4_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Enable or disable interrupt for event TRIGGERED\\[5\\]"] + #[inline(always)] + pub fn triggered5(&self) -> TRIGGERED5_R { + TRIGGERED5_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Enable or disable interrupt for event TRIGGERED\\[6\\]"] + #[inline(always)] + pub fn triggered6(&self) -> TRIGGERED6_R { + TRIGGERED6_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Enable or disable interrupt for event TRIGGERED\\[7\\]"] + #[inline(always)] + pub fn triggered7(&self) -> TRIGGERED7_R { + TRIGGERED7_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Enable or disable interrupt for event TRIGGERED\\[8\\]"] + #[inline(always)] + pub fn triggered8(&self) -> TRIGGERED8_R { + TRIGGERED8_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Enable or disable interrupt for event TRIGGERED\\[9\\]"] + #[inline(always)] + pub fn triggered9(&self) -> TRIGGERED9_R { + TRIGGERED9_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Enable or disable interrupt for event TRIGGERED\\[10\\]"] + #[inline(always)] + pub fn triggered10(&self) -> TRIGGERED10_R { + TRIGGERED10_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Enable or disable interrupt for event TRIGGERED\\[11\\]"] + #[inline(always)] + pub fn triggered11(&self) -> TRIGGERED11_R { + TRIGGERED11_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Enable or disable interrupt for event TRIGGERED\\[12\\]"] + #[inline(always)] + pub fn triggered12(&self) -> TRIGGERED12_R { + TRIGGERED12_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Enable or disable interrupt for event TRIGGERED\\[13\\]"] + #[inline(always)] + pub fn triggered13(&self) -> TRIGGERED13_R { + TRIGGERED13_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Enable or disable interrupt for event TRIGGERED\\[14\\]"] + #[inline(always)] + pub fn triggered14(&self) -> TRIGGERED14_R { + TRIGGERED14_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Enable or disable interrupt for event TRIGGERED\\[15\\]"] + #[inline(always)] + pub fn triggered15(&self) -> TRIGGERED15_R { + TRIGGERED15_R::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Enable or disable interrupt for event TRIGGERED\\[0\\]"] + #[inline(always)] + pub fn triggered0(&mut self) -> TRIGGERED0_W<0> { + TRIGGERED0_W::new(self) + } + #[doc = "Bit 1 - Enable or disable interrupt for event TRIGGERED\\[1\\]"] + #[inline(always)] + pub fn triggered1(&mut self) -> TRIGGERED1_W<1> { + TRIGGERED1_W::new(self) + } + #[doc = "Bit 2 - Enable or disable interrupt for event TRIGGERED\\[2\\]"] + #[inline(always)] + pub fn triggered2(&mut self) -> TRIGGERED2_W<2> { + TRIGGERED2_W::new(self) + } + #[doc = "Bit 3 - Enable or disable interrupt for event TRIGGERED\\[3\\]"] + #[inline(always)] + pub fn triggered3(&mut self) -> TRIGGERED3_W<3> { + TRIGGERED3_W::new(self) + } + #[doc = "Bit 4 - Enable or disable interrupt for event TRIGGERED\\[4\\]"] + #[inline(always)] + pub fn triggered4(&mut self) -> TRIGGERED4_W<4> { + TRIGGERED4_W::new(self) + } + #[doc = "Bit 5 - Enable or disable interrupt for event TRIGGERED\\[5\\]"] + #[inline(always)] + pub fn triggered5(&mut self) -> TRIGGERED5_W<5> { + TRIGGERED5_W::new(self) + } + #[doc = "Bit 6 - Enable or disable interrupt for event TRIGGERED\\[6\\]"] + #[inline(always)] + pub fn triggered6(&mut self) -> TRIGGERED6_W<6> { + TRIGGERED6_W::new(self) + } + #[doc = "Bit 7 - Enable or disable interrupt for event TRIGGERED\\[7\\]"] + #[inline(always)] + pub fn triggered7(&mut self) -> TRIGGERED7_W<7> { + TRIGGERED7_W::new(self) + } + #[doc = "Bit 8 - Enable or disable interrupt for event TRIGGERED\\[8\\]"] + #[inline(always)] + pub fn triggered8(&mut self) -> TRIGGERED8_W<8> { + TRIGGERED8_W::new(self) + } + #[doc = "Bit 9 - Enable or disable interrupt for event TRIGGERED\\[9\\]"] + #[inline(always)] + pub fn triggered9(&mut self) -> TRIGGERED9_W<9> { + TRIGGERED9_W::new(self) + } + #[doc = "Bit 10 - Enable or disable interrupt for event TRIGGERED\\[10\\]"] + #[inline(always)] + pub fn triggered10(&mut self) -> TRIGGERED10_W<10> { + TRIGGERED10_W::new(self) + } + #[doc = "Bit 11 - Enable or disable interrupt for event TRIGGERED\\[11\\]"] + #[inline(always)] + pub fn triggered11(&mut self) -> TRIGGERED11_W<11> { + TRIGGERED11_W::new(self) + } + #[doc = "Bit 12 - Enable or disable interrupt for event TRIGGERED\\[12\\]"] + #[inline(always)] + pub fn triggered12(&mut self) -> TRIGGERED12_W<12> { + TRIGGERED12_W::new(self) + } + #[doc = "Bit 13 - Enable or disable interrupt for event TRIGGERED\\[13\\]"] + #[inline(always)] + pub fn triggered13(&mut self) -> TRIGGERED13_W<13> { + TRIGGERED13_W::new(self) + } + #[doc = "Bit 14 - Enable or disable interrupt for event TRIGGERED\\[14\\]"] + #[inline(always)] + pub fn triggered14(&mut self) -> TRIGGERED14_W<14> { + TRIGGERED14_W::new(self) + } + #[doc = "Bit 15 - Enable or disable interrupt for event TRIGGERED\\[15\\]"] + #[inline(always)] + pub fn triggered15(&mut self) -> TRIGGERED15_W<15> { + TRIGGERED15_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Enable or disable interrupt\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [inten](index.html) module"] +pub struct INTEN_SPEC; +impl crate::RegisterSpec for INTEN_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [inten::R](R) reader structure"] +impl crate::Readable for INTEN_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [inten::W](W) writer structure"] +impl crate::Writable for INTEN_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTEN to value 0"] +impl crate::Resettable for INTEN_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/egu0_ns/intenclr.rs b/pacs/nrf9120-pac/src/egu0_ns/intenclr.rs new file mode 100644 index 00000000..3022248c --- /dev/null +++ b/pacs/nrf9120-pac/src/egu0_ns/intenclr.rs @@ -0,0 +1,1144 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `TRIGGERED0` reader - Write '1' to disable interrupt for event TRIGGERED\\[0\\]"] +pub type TRIGGERED0_R = crate::BitReader; +#[doc = "Write '1' to disable interrupt for event TRIGGERED\\[0\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum TRIGGERED0_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TRIGGERED0_A) -> Self { + variant as u8 != 0 + } +} +impl TRIGGERED0_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> TRIGGERED0_A { + match self.bits { + false => TRIGGERED0_A::DISABLED, + true => TRIGGERED0_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == TRIGGERED0_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == TRIGGERED0_A::ENABLED + } +} +#[doc = "Write '1' to disable interrupt for event TRIGGERED\\[0\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum TRIGGERED0_AW { + #[doc = "1: Disable"] + CLEAR = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TRIGGERED0_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TRIGGERED0` writer - Write '1' to disable interrupt for event TRIGGERED\\[0\\]"] +pub type TRIGGERED0_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENCLR_SPEC, TRIGGERED0_AW, O>; +impl<'a, const O: u8> TRIGGERED0_W<'a, O> { + #[doc = "Disable"] + #[inline(always)] + pub fn clear(self) -> &'a mut W { + self.variant(TRIGGERED0_AW::CLEAR) + } +} +#[doc = "Field `TRIGGERED1` reader - Write '1' to disable interrupt for event TRIGGERED\\[1\\]"] +pub type TRIGGERED1_R = crate::BitReader; +#[doc = "Write '1' to disable interrupt for event TRIGGERED\\[1\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum TRIGGERED1_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TRIGGERED1_A) -> Self { + variant as u8 != 0 + } +} +impl TRIGGERED1_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> TRIGGERED1_A { + match self.bits { + false => TRIGGERED1_A::DISABLED, + true => TRIGGERED1_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == TRIGGERED1_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == TRIGGERED1_A::ENABLED + } +} +#[doc = "Write '1' to disable interrupt for event TRIGGERED\\[1\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum TRIGGERED1_AW { + #[doc = "1: Disable"] + CLEAR = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TRIGGERED1_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TRIGGERED1` writer - Write '1' to disable interrupt for event TRIGGERED\\[1\\]"] +pub type TRIGGERED1_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENCLR_SPEC, TRIGGERED1_AW, O>; +impl<'a, const O: u8> TRIGGERED1_W<'a, O> { + #[doc = "Disable"] + #[inline(always)] + pub fn clear(self) -> &'a mut W { + self.variant(TRIGGERED1_AW::CLEAR) + } +} +#[doc = "Field `TRIGGERED2` reader - Write '1' to disable interrupt for event TRIGGERED\\[2\\]"] +pub type TRIGGERED2_R = crate::BitReader; +#[doc = "Write '1' to disable interrupt for event TRIGGERED\\[2\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum TRIGGERED2_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TRIGGERED2_A) -> Self { + variant as u8 != 0 + } +} +impl TRIGGERED2_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> TRIGGERED2_A { + match self.bits { + false => TRIGGERED2_A::DISABLED, + true => TRIGGERED2_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == TRIGGERED2_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == TRIGGERED2_A::ENABLED + } +} +#[doc = "Write '1' to disable interrupt for event TRIGGERED\\[2\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum TRIGGERED2_AW { + #[doc = "1: Disable"] + CLEAR = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TRIGGERED2_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TRIGGERED2` writer - Write '1' to disable interrupt for event TRIGGERED\\[2\\]"] +pub type TRIGGERED2_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENCLR_SPEC, TRIGGERED2_AW, O>; +impl<'a, const O: u8> TRIGGERED2_W<'a, O> { + #[doc = "Disable"] + #[inline(always)] + pub fn clear(self) -> &'a mut W { + self.variant(TRIGGERED2_AW::CLEAR) + } +} +#[doc = "Field `TRIGGERED3` reader - Write '1' to disable interrupt for event TRIGGERED\\[3\\]"] +pub type TRIGGERED3_R = crate::BitReader; +#[doc = "Write '1' to disable interrupt for event TRIGGERED\\[3\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum TRIGGERED3_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TRIGGERED3_A) -> Self { + variant as u8 != 0 + } +} +impl TRIGGERED3_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> TRIGGERED3_A { + match self.bits { + false => TRIGGERED3_A::DISABLED, + true => TRIGGERED3_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == TRIGGERED3_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == TRIGGERED3_A::ENABLED + } +} +#[doc = "Write '1' to disable interrupt for event TRIGGERED\\[3\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum TRIGGERED3_AW { + #[doc = "1: Disable"] + CLEAR = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TRIGGERED3_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TRIGGERED3` writer - Write '1' to disable interrupt for event TRIGGERED\\[3\\]"] +pub type TRIGGERED3_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENCLR_SPEC, TRIGGERED3_AW, O>; +impl<'a, const O: u8> TRIGGERED3_W<'a, O> { + #[doc = "Disable"] + #[inline(always)] + pub fn clear(self) -> &'a mut W { + self.variant(TRIGGERED3_AW::CLEAR) + } +} +#[doc = "Field `TRIGGERED4` reader - Write '1' to disable interrupt for event TRIGGERED\\[4\\]"] +pub type TRIGGERED4_R = crate::BitReader; +#[doc = "Write '1' to disable interrupt for event TRIGGERED\\[4\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum TRIGGERED4_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TRIGGERED4_A) -> Self { + variant as u8 != 0 + } +} +impl TRIGGERED4_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> TRIGGERED4_A { + match self.bits { + false => TRIGGERED4_A::DISABLED, + true => TRIGGERED4_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == TRIGGERED4_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == TRIGGERED4_A::ENABLED + } +} +#[doc = "Write '1' to disable interrupt for event TRIGGERED\\[4\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum TRIGGERED4_AW { + #[doc = "1: Disable"] + CLEAR = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TRIGGERED4_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TRIGGERED4` writer - Write '1' to disable interrupt for event TRIGGERED\\[4\\]"] +pub type TRIGGERED4_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENCLR_SPEC, TRIGGERED4_AW, O>; +impl<'a, const O: u8> TRIGGERED4_W<'a, O> { + #[doc = "Disable"] + #[inline(always)] + pub fn clear(self) -> &'a mut W { + self.variant(TRIGGERED4_AW::CLEAR) + } +} +#[doc = "Field `TRIGGERED5` reader - Write '1' to disable interrupt for event TRIGGERED\\[5\\]"] +pub type TRIGGERED5_R = crate::BitReader; +#[doc = "Write '1' to disable interrupt for event TRIGGERED\\[5\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum TRIGGERED5_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TRIGGERED5_A) -> Self { + variant as u8 != 0 + } +} +impl TRIGGERED5_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> TRIGGERED5_A { + match self.bits { + false => TRIGGERED5_A::DISABLED, + true => TRIGGERED5_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == TRIGGERED5_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == TRIGGERED5_A::ENABLED + } +} +#[doc = "Write '1' to disable interrupt for event TRIGGERED\\[5\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum TRIGGERED5_AW { + #[doc = "1: Disable"] + CLEAR = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TRIGGERED5_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TRIGGERED5` writer - Write '1' to disable interrupt for event TRIGGERED\\[5\\]"] +pub type TRIGGERED5_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENCLR_SPEC, TRIGGERED5_AW, O>; +impl<'a, const O: u8> TRIGGERED5_W<'a, O> { + #[doc = "Disable"] + #[inline(always)] + pub fn clear(self) -> &'a mut W { + self.variant(TRIGGERED5_AW::CLEAR) + } +} +#[doc = "Field `TRIGGERED6` reader - Write '1' to disable interrupt for event TRIGGERED\\[6\\]"] +pub type TRIGGERED6_R = crate::BitReader; +#[doc = "Write '1' to disable interrupt for event TRIGGERED\\[6\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum TRIGGERED6_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TRIGGERED6_A) -> Self { + variant as u8 != 0 + } +} +impl TRIGGERED6_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> TRIGGERED6_A { + match self.bits { + false => TRIGGERED6_A::DISABLED, + true => TRIGGERED6_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == TRIGGERED6_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == TRIGGERED6_A::ENABLED + } +} +#[doc = "Write '1' to disable interrupt for event TRIGGERED\\[6\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum TRIGGERED6_AW { + #[doc = "1: Disable"] + CLEAR = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TRIGGERED6_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TRIGGERED6` writer - Write '1' to disable interrupt for event TRIGGERED\\[6\\]"] +pub type TRIGGERED6_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENCLR_SPEC, TRIGGERED6_AW, O>; +impl<'a, const O: u8> TRIGGERED6_W<'a, O> { + #[doc = "Disable"] + #[inline(always)] + pub fn clear(self) -> &'a mut W { + self.variant(TRIGGERED6_AW::CLEAR) + } +} +#[doc = "Field `TRIGGERED7` reader - Write '1' to disable interrupt for event TRIGGERED\\[7\\]"] +pub type TRIGGERED7_R = crate::BitReader; +#[doc = "Write '1' to disable interrupt for event TRIGGERED\\[7\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum TRIGGERED7_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TRIGGERED7_A) -> Self { + variant as u8 != 0 + } +} +impl TRIGGERED7_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> TRIGGERED7_A { + match self.bits { + false => TRIGGERED7_A::DISABLED, + true => TRIGGERED7_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == TRIGGERED7_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == TRIGGERED7_A::ENABLED + } +} +#[doc = "Write '1' to disable interrupt for event TRIGGERED\\[7\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum TRIGGERED7_AW { + #[doc = "1: Disable"] + CLEAR = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TRIGGERED7_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TRIGGERED7` writer - Write '1' to disable interrupt for event TRIGGERED\\[7\\]"] +pub type TRIGGERED7_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENCLR_SPEC, TRIGGERED7_AW, O>; +impl<'a, const O: u8> TRIGGERED7_W<'a, O> { + #[doc = "Disable"] + #[inline(always)] + pub fn clear(self) -> &'a mut W { + self.variant(TRIGGERED7_AW::CLEAR) + } +} +#[doc = "Field `TRIGGERED8` reader - Write '1' to disable interrupt for event TRIGGERED\\[8\\]"] +pub type TRIGGERED8_R = crate::BitReader; +#[doc = "Write '1' to disable interrupt for event TRIGGERED\\[8\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum TRIGGERED8_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TRIGGERED8_A) -> Self { + variant as u8 != 0 + } +} +impl TRIGGERED8_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> TRIGGERED8_A { + match self.bits { + false => TRIGGERED8_A::DISABLED, + true => TRIGGERED8_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == TRIGGERED8_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == TRIGGERED8_A::ENABLED + } +} +#[doc = "Write '1' to disable interrupt for event TRIGGERED\\[8\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum TRIGGERED8_AW { + #[doc = "1: Disable"] + CLEAR = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TRIGGERED8_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TRIGGERED8` writer - Write '1' to disable interrupt for event TRIGGERED\\[8\\]"] +pub type TRIGGERED8_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENCLR_SPEC, TRIGGERED8_AW, O>; +impl<'a, const O: u8> TRIGGERED8_W<'a, O> { + #[doc = "Disable"] + #[inline(always)] + pub fn clear(self) -> &'a mut W { + self.variant(TRIGGERED8_AW::CLEAR) + } +} +#[doc = "Field `TRIGGERED9` reader - Write '1' to disable interrupt for event TRIGGERED\\[9\\]"] +pub type TRIGGERED9_R = crate::BitReader; +#[doc = "Write '1' to disable interrupt for event TRIGGERED\\[9\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum TRIGGERED9_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TRIGGERED9_A) -> Self { + variant as u8 != 0 + } +} +impl TRIGGERED9_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> TRIGGERED9_A { + match self.bits { + false => TRIGGERED9_A::DISABLED, + true => TRIGGERED9_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == TRIGGERED9_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == TRIGGERED9_A::ENABLED + } +} +#[doc = "Write '1' to disable interrupt for event TRIGGERED\\[9\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum TRIGGERED9_AW { + #[doc = "1: Disable"] + CLEAR = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TRIGGERED9_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TRIGGERED9` writer - Write '1' to disable interrupt for event TRIGGERED\\[9\\]"] +pub type TRIGGERED9_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENCLR_SPEC, TRIGGERED9_AW, O>; +impl<'a, const O: u8> TRIGGERED9_W<'a, O> { + #[doc = "Disable"] + #[inline(always)] + pub fn clear(self) -> &'a mut W { + self.variant(TRIGGERED9_AW::CLEAR) + } +} +#[doc = "Field `TRIGGERED10` reader - Write '1' to disable interrupt for event TRIGGERED\\[10\\]"] +pub type TRIGGERED10_R = crate::BitReader; +#[doc = "Write '1' to disable interrupt for event TRIGGERED\\[10\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum TRIGGERED10_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TRIGGERED10_A) -> Self { + variant as u8 != 0 + } +} +impl TRIGGERED10_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> TRIGGERED10_A { + match self.bits { + false => TRIGGERED10_A::DISABLED, + true => TRIGGERED10_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == TRIGGERED10_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == TRIGGERED10_A::ENABLED + } +} +#[doc = "Write '1' to disable interrupt for event TRIGGERED\\[10\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum TRIGGERED10_AW { + #[doc = "1: Disable"] + CLEAR = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TRIGGERED10_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TRIGGERED10` writer - Write '1' to disable interrupt for event TRIGGERED\\[10\\]"] +pub type TRIGGERED10_W<'a, const O: u8> = + crate::BitWriter<'a, u32, INTENCLR_SPEC, TRIGGERED10_AW, O>; +impl<'a, const O: u8> TRIGGERED10_W<'a, O> { + #[doc = "Disable"] + #[inline(always)] + pub fn clear(self) -> &'a mut W { + self.variant(TRIGGERED10_AW::CLEAR) + } +} +#[doc = "Field `TRIGGERED11` reader - Write '1' to disable interrupt for event TRIGGERED\\[11\\]"] +pub type TRIGGERED11_R = crate::BitReader; +#[doc = "Write '1' to disable interrupt for event TRIGGERED\\[11\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum TRIGGERED11_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TRIGGERED11_A) -> Self { + variant as u8 != 0 + } +} +impl TRIGGERED11_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> TRIGGERED11_A { + match self.bits { + false => TRIGGERED11_A::DISABLED, + true => TRIGGERED11_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == TRIGGERED11_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == TRIGGERED11_A::ENABLED + } +} +#[doc = "Write '1' to disable interrupt for event TRIGGERED\\[11\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum TRIGGERED11_AW { + #[doc = "1: Disable"] + CLEAR = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TRIGGERED11_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TRIGGERED11` writer - Write '1' to disable interrupt for event TRIGGERED\\[11\\]"] +pub type TRIGGERED11_W<'a, const O: u8> = + crate::BitWriter<'a, u32, INTENCLR_SPEC, TRIGGERED11_AW, O>; +impl<'a, const O: u8> TRIGGERED11_W<'a, O> { + #[doc = "Disable"] + #[inline(always)] + pub fn clear(self) -> &'a mut W { + self.variant(TRIGGERED11_AW::CLEAR) + } +} +#[doc = "Field `TRIGGERED12` reader - Write '1' to disable interrupt for event TRIGGERED\\[12\\]"] +pub type TRIGGERED12_R = crate::BitReader; +#[doc = "Write '1' to disable interrupt for event TRIGGERED\\[12\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum TRIGGERED12_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TRIGGERED12_A) -> Self { + variant as u8 != 0 + } +} +impl TRIGGERED12_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> TRIGGERED12_A { + match self.bits { + false => TRIGGERED12_A::DISABLED, + true => TRIGGERED12_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == TRIGGERED12_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == TRIGGERED12_A::ENABLED + } +} +#[doc = "Write '1' to disable interrupt for event TRIGGERED\\[12\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum TRIGGERED12_AW { + #[doc = "1: Disable"] + CLEAR = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TRIGGERED12_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TRIGGERED12` writer - Write '1' to disable interrupt for event TRIGGERED\\[12\\]"] +pub type TRIGGERED12_W<'a, const O: u8> = + crate::BitWriter<'a, u32, INTENCLR_SPEC, TRIGGERED12_AW, O>; +impl<'a, const O: u8> TRIGGERED12_W<'a, O> { + #[doc = "Disable"] + #[inline(always)] + pub fn clear(self) -> &'a mut W { + self.variant(TRIGGERED12_AW::CLEAR) + } +} +#[doc = "Field `TRIGGERED13` reader - Write '1' to disable interrupt for event TRIGGERED\\[13\\]"] +pub type TRIGGERED13_R = crate::BitReader; +#[doc = "Write '1' to disable interrupt for event TRIGGERED\\[13\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum TRIGGERED13_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TRIGGERED13_A) -> Self { + variant as u8 != 0 + } +} +impl TRIGGERED13_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> TRIGGERED13_A { + match self.bits { + false => TRIGGERED13_A::DISABLED, + true => TRIGGERED13_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == TRIGGERED13_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == TRIGGERED13_A::ENABLED + } +} +#[doc = "Write '1' to disable interrupt for event TRIGGERED\\[13\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum TRIGGERED13_AW { + #[doc = "1: Disable"] + CLEAR = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TRIGGERED13_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TRIGGERED13` writer - Write '1' to disable interrupt for event TRIGGERED\\[13\\]"] +pub type TRIGGERED13_W<'a, const O: u8> = + crate::BitWriter<'a, u32, INTENCLR_SPEC, TRIGGERED13_AW, O>; +impl<'a, const O: u8> TRIGGERED13_W<'a, O> { + #[doc = "Disable"] + #[inline(always)] + pub fn clear(self) -> &'a mut W { + self.variant(TRIGGERED13_AW::CLEAR) + } +} +#[doc = "Field `TRIGGERED14` reader - Write '1' to disable interrupt for event TRIGGERED\\[14\\]"] +pub type TRIGGERED14_R = crate::BitReader; +#[doc = "Write '1' to disable interrupt for event TRIGGERED\\[14\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum TRIGGERED14_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TRIGGERED14_A) -> Self { + variant as u8 != 0 + } +} +impl TRIGGERED14_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> TRIGGERED14_A { + match self.bits { + false => TRIGGERED14_A::DISABLED, + true => TRIGGERED14_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == TRIGGERED14_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == TRIGGERED14_A::ENABLED + } +} +#[doc = "Write '1' to disable interrupt for event TRIGGERED\\[14\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum TRIGGERED14_AW { + #[doc = "1: Disable"] + CLEAR = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TRIGGERED14_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TRIGGERED14` writer - Write '1' to disable interrupt for event TRIGGERED\\[14\\]"] +pub type TRIGGERED14_W<'a, const O: u8> = + crate::BitWriter<'a, u32, INTENCLR_SPEC, TRIGGERED14_AW, O>; +impl<'a, const O: u8> TRIGGERED14_W<'a, O> { + #[doc = "Disable"] + #[inline(always)] + pub fn clear(self) -> &'a mut W { + self.variant(TRIGGERED14_AW::CLEAR) + } +} +#[doc = "Field `TRIGGERED15` reader - Write '1' to disable interrupt for event TRIGGERED\\[15\\]"] +pub type TRIGGERED15_R = crate::BitReader; +#[doc = "Write '1' to disable interrupt for event TRIGGERED\\[15\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum TRIGGERED15_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TRIGGERED15_A) -> Self { + variant as u8 != 0 + } +} +impl TRIGGERED15_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> TRIGGERED15_A { + match self.bits { + false => TRIGGERED15_A::DISABLED, + true => TRIGGERED15_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == TRIGGERED15_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == TRIGGERED15_A::ENABLED + } +} +#[doc = "Write '1' to disable interrupt for event TRIGGERED\\[15\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum TRIGGERED15_AW { + #[doc = "1: Disable"] + CLEAR = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TRIGGERED15_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TRIGGERED15` writer - Write '1' to disable interrupt for event TRIGGERED\\[15\\]"] +pub type TRIGGERED15_W<'a, const O: u8> = + crate::BitWriter<'a, u32, INTENCLR_SPEC, TRIGGERED15_AW, O>; +impl<'a, const O: u8> TRIGGERED15_W<'a, O> { + #[doc = "Disable"] + #[inline(always)] + pub fn clear(self) -> &'a mut W { + self.variant(TRIGGERED15_AW::CLEAR) + } +} +impl R { + #[doc = "Bit 0 - Write '1' to disable interrupt for event TRIGGERED\\[0\\]"] + #[inline(always)] + pub fn triggered0(&self) -> TRIGGERED0_R { + TRIGGERED0_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Write '1' to disable interrupt for event TRIGGERED\\[1\\]"] + #[inline(always)] + pub fn triggered1(&self) -> TRIGGERED1_R { + TRIGGERED1_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Write '1' to disable interrupt for event TRIGGERED\\[2\\]"] + #[inline(always)] + pub fn triggered2(&self) -> TRIGGERED2_R { + TRIGGERED2_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Write '1' to disable interrupt for event TRIGGERED\\[3\\]"] + #[inline(always)] + pub fn triggered3(&self) -> TRIGGERED3_R { + TRIGGERED3_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Write '1' to disable interrupt for event TRIGGERED\\[4\\]"] + #[inline(always)] + pub fn triggered4(&self) -> TRIGGERED4_R { + TRIGGERED4_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Write '1' to disable interrupt for event TRIGGERED\\[5\\]"] + #[inline(always)] + pub fn triggered5(&self) -> TRIGGERED5_R { + TRIGGERED5_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Write '1' to disable interrupt for event TRIGGERED\\[6\\]"] + #[inline(always)] + pub fn triggered6(&self) -> TRIGGERED6_R { + TRIGGERED6_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Write '1' to disable interrupt for event TRIGGERED\\[7\\]"] + #[inline(always)] + pub fn triggered7(&self) -> TRIGGERED7_R { + TRIGGERED7_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Write '1' to disable interrupt for event TRIGGERED\\[8\\]"] + #[inline(always)] + pub fn triggered8(&self) -> TRIGGERED8_R { + TRIGGERED8_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Write '1' to disable interrupt for event TRIGGERED\\[9\\]"] + #[inline(always)] + pub fn triggered9(&self) -> TRIGGERED9_R { + TRIGGERED9_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Write '1' to disable interrupt for event TRIGGERED\\[10\\]"] + #[inline(always)] + pub fn triggered10(&self) -> TRIGGERED10_R { + TRIGGERED10_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Write '1' to disable interrupt for event TRIGGERED\\[11\\]"] + #[inline(always)] + pub fn triggered11(&self) -> TRIGGERED11_R { + TRIGGERED11_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Write '1' to disable interrupt for event TRIGGERED\\[12\\]"] + #[inline(always)] + pub fn triggered12(&self) -> TRIGGERED12_R { + TRIGGERED12_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Write '1' to disable interrupt for event TRIGGERED\\[13\\]"] + #[inline(always)] + pub fn triggered13(&self) -> TRIGGERED13_R { + TRIGGERED13_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Write '1' to disable interrupt for event TRIGGERED\\[14\\]"] + #[inline(always)] + pub fn triggered14(&self) -> TRIGGERED14_R { + TRIGGERED14_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Write '1' to disable interrupt for event TRIGGERED\\[15\\]"] + #[inline(always)] + pub fn triggered15(&self) -> TRIGGERED15_R { + TRIGGERED15_R::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Write '1' to disable interrupt for event TRIGGERED\\[0\\]"] + #[inline(always)] + pub fn triggered0(&mut self) -> TRIGGERED0_W<0> { + TRIGGERED0_W::new(self) + } + #[doc = "Bit 1 - Write '1' to disable interrupt for event TRIGGERED\\[1\\]"] + #[inline(always)] + pub fn triggered1(&mut self) -> TRIGGERED1_W<1> { + TRIGGERED1_W::new(self) + } + #[doc = "Bit 2 - Write '1' to disable interrupt for event TRIGGERED\\[2\\]"] + #[inline(always)] + pub fn triggered2(&mut self) -> TRIGGERED2_W<2> { + TRIGGERED2_W::new(self) + } + #[doc = "Bit 3 - Write '1' to disable interrupt for event TRIGGERED\\[3\\]"] + #[inline(always)] + pub fn triggered3(&mut self) -> TRIGGERED3_W<3> { + TRIGGERED3_W::new(self) + } + #[doc = "Bit 4 - Write '1' to disable interrupt for event TRIGGERED\\[4\\]"] + #[inline(always)] + pub fn triggered4(&mut self) -> TRIGGERED4_W<4> { + TRIGGERED4_W::new(self) + } + #[doc = "Bit 5 - Write '1' to disable interrupt for event TRIGGERED\\[5\\]"] + #[inline(always)] + pub fn triggered5(&mut self) -> TRIGGERED5_W<5> { + TRIGGERED5_W::new(self) + } + #[doc = "Bit 6 - Write '1' to disable interrupt for event TRIGGERED\\[6\\]"] + #[inline(always)] + pub fn triggered6(&mut self) -> TRIGGERED6_W<6> { + TRIGGERED6_W::new(self) + } + #[doc = "Bit 7 - Write '1' to disable interrupt for event TRIGGERED\\[7\\]"] + #[inline(always)] + pub fn triggered7(&mut self) -> TRIGGERED7_W<7> { + TRIGGERED7_W::new(self) + } + #[doc = "Bit 8 - Write '1' to disable interrupt for event TRIGGERED\\[8\\]"] + #[inline(always)] + pub fn triggered8(&mut self) -> TRIGGERED8_W<8> { + TRIGGERED8_W::new(self) + } + #[doc = "Bit 9 - Write '1' to disable interrupt for event TRIGGERED\\[9\\]"] + #[inline(always)] + pub fn triggered9(&mut self) -> TRIGGERED9_W<9> { + TRIGGERED9_W::new(self) + } + #[doc = "Bit 10 - Write '1' to disable interrupt for event TRIGGERED\\[10\\]"] + #[inline(always)] + pub fn triggered10(&mut self) -> TRIGGERED10_W<10> { + TRIGGERED10_W::new(self) + } + #[doc = "Bit 11 - Write '1' to disable interrupt for event TRIGGERED\\[11\\]"] + #[inline(always)] + pub fn triggered11(&mut self) -> TRIGGERED11_W<11> { + TRIGGERED11_W::new(self) + } + #[doc = "Bit 12 - Write '1' to disable interrupt for event TRIGGERED\\[12\\]"] + #[inline(always)] + pub fn triggered12(&mut self) -> TRIGGERED12_W<12> { + TRIGGERED12_W::new(self) + } + #[doc = "Bit 13 - Write '1' to disable interrupt for event TRIGGERED\\[13\\]"] + #[inline(always)] + pub fn triggered13(&mut self) -> TRIGGERED13_W<13> { + TRIGGERED13_W::new(self) + } + #[doc = "Bit 14 - Write '1' to disable interrupt for event TRIGGERED\\[14\\]"] + #[inline(always)] + pub fn triggered14(&mut self) -> TRIGGERED14_W<14> { + TRIGGERED14_W::new(self) + } + #[doc = "Bit 15 - Write '1' to disable interrupt for event TRIGGERED\\[15\\]"] + #[inline(always)] + pub fn triggered15(&mut self) -> TRIGGERED15_W<15> { + TRIGGERED15_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Disable interrupt\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/egu0_ns/intenset.rs b/pacs/nrf9120-pac/src/egu0_ns/intenset.rs new file mode 100644 index 00000000..7473c4fb --- /dev/null +++ b/pacs/nrf9120-pac/src/egu0_ns/intenset.rs @@ -0,0 +1,1144 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `TRIGGERED0` reader - Write '1' to enable interrupt for event TRIGGERED\\[0\\]"] +pub type TRIGGERED0_R = crate::BitReader; +#[doc = "Write '1' to enable interrupt for event TRIGGERED\\[0\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum TRIGGERED0_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TRIGGERED0_A) -> Self { + variant as u8 != 0 + } +} +impl TRIGGERED0_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> TRIGGERED0_A { + match self.bits { + false => TRIGGERED0_A::DISABLED, + true => TRIGGERED0_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == TRIGGERED0_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == TRIGGERED0_A::ENABLED + } +} +#[doc = "Write '1' to enable interrupt for event TRIGGERED\\[0\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum TRIGGERED0_AW { + #[doc = "1: Enable"] + SET = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TRIGGERED0_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TRIGGERED0` writer - Write '1' to enable interrupt for event TRIGGERED\\[0\\]"] +pub type TRIGGERED0_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENSET_SPEC, TRIGGERED0_AW, O>; +impl<'a, const O: u8> TRIGGERED0_W<'a, O> { + #[doc = "Enable"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(TRIGGERED0_AW::SET) + } +} +#[doc = "Field `TRIGGERED1` reader - Write '1' to enable interrupt for event TRIGGERED\\[1\\]"] +pub type TRIGGERED1_R = crate::BitReader; +#[doc = "Write '1' to enable interrupt for event TRIGGERED\\[1\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum TRIGGERED1_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TRIGGERED1_A) -> Self { + variant as u8 != 0 + } +} +impl TRIGGERED1_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> TRIGGERED1_A { + match self.bits { + false => TRIGGERED1_A::DISABLED, + true => TRIGGERED1_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == TRIGGERED1_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == TRIGGERED1_A::ENABLED + } +} +#[doc = "Write '1' to enable interrupt for event TRIGGERED\\[1\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum TRIGGERED1_AW { + #[doc = "1: Enable"] + SET = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TRIGGERED1_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TRIGGERED1` writer - Write '1' to enable interrupt for event TRIGGERED\\[1\\]"] +pub type TRIGGERED1_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENSET_SPEC, TRIGGERED1_AW, O>; +impl<'a, const O: u8> TRIGGERED1_W<'a, O> { + #[doc = "Enable"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(TRIGGERED1_AW::SET) + } +} +#[doc = "Field `TRIGGERED2` reader - Write '1' to enable interrupt for event TRIGGERED\\[2\\]"] +pub type TRIGGERED2_R = crate::BitReader; +#[doc = "Write '1' to enable interrupt for event TRIGGERED\\[2\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum TRIGGERED2_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TRIGGERED2_A) -> Self { + variant as u8 != 0 + } +} +impl TRIGGERED2_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> TRIGGERED2_A { + match self.bits { + false => TRIGGERED2_A::DISABLED, + true => TRIGGERED2_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == TRIGGERED2_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == TRIGGERED2_A::ENABLED + } +} +#[doc = "Write '1' to enable interrupt for event TRIGGERED\\[2\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum TRIGGERED2_AW { + #[doc = "1: Enable"] + SET = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TRIGGERED2_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TRIGGERED2` writer - Write '1' to enable interrupt for event TRIGGERED\\[2\\]"] +pub type TRIGGERED2_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENSET_SPEC, TRIGGERED2_AW, O>; +impl<'a, const O: u8> TRIGGERED2_W<'a, O> { + #[doc = "Enable"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(TRIGGERED2_AW::SET) + } +} +#[doc = "Field `TRIGGERED3` reader - Write '1' to enable interrupt for event TRIGGERED\\[3\\]"] +pub type TRIGGERED3_R = crate::BitReader; +#[doc = "Write '1' to enable interrupt for event TRIGGERED\\[3\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum TRIGGERED3_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TRIGGERED3_A) -> Self { + variant as u8 != 0 + } +} +impl TRIGGERED3_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> TRIGGERED3_A { + match self.bits { + false => TRIGGERED3_A::DISABLED, + true => TRIGGERED3_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == TRIGGERED3_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == TRIGGERED3_A::ENABLED + } +} +#[doc = "Write '1' to enable interrupt for event TRIGGERED\\[3\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum TRIGGERED3_AW { + #[doc = "1: Enable"] + SET = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TRIGGERED3_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TRIGGERED3` writer - Write '1' to enable interrupt for event TRIGGERED\\[3\\]"] +pub type TRIGGERED3_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENSET_SPEC, TRIGGERED3_AW, O>; +impl<'a, const O: u8> TRIGGERED3_W<'a, O> { + #[doc = "Enable"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(TRIGGERED3_AW::SET) + } +} +#[doc = "Field `TRIGGERED4` reader - Write '1' to enable interrupt for event TRIGGERED\\[4\\]"] +pub type TRIGGERED4_R = crate::BitReader; +#[doc = "Write '1' to enable interrupt for event TRIGGERED\\[4\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum TRIGGERED4_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TRIGGERED4_A) -> Self { + variant as u8 != 0 + } +} +impl TRIGGERED4_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> TRIGGERED4_A { + match self.bits { + false => TRIGGERED4_A::DISABLED, + true => TRIGGERED4_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == TRIGGERED4_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == TRIGGERED4_A::ENABLED + } +} +#[doc = "Write '1' to enable interrupt for event TRIGGERED\\[4\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum TRIGGERED4_AW { + #[doc = "1: Enable"] + SET = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TRIGGERED4_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TRIGGERED4` writer - Write '1' to enable interrupt for event TRIGGERED\\[4\\]"] +pub type TRIGGERED4_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENSET_SPEC, TRIGGERED4_AW, O>; +impl<'a, const O: u8> TRIGGERED4_W<'a, O> { + #[doc = "Enable"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(TRIGGERED4_AW::SET) + } +} +#[doc = "Field `TRIGGERED5` reader - Write '1' to enable interrupt for event TRIGGERED\\[5\\]"] +pub type TRIGGERED5_R = crate::BitReader; +#[doc = "Write '1' to enable interrupt for event TRIGGERED\\[5\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum TRIGGERED5_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TRIGGERED5_A) -> Self { + variant as u8 != 0 + } +} +impl TRIGGERED5_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> TRIGGERED5_A { + match self.bits { + false => TRIGGERED5_A::DISABLED, + true => TRIGGERED5_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == TRIGGERED5_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == TRIGGERED5_A::ENABLED + } +} +#[doc = "Write '1' to enable interrupt for event TRIGGERED\\[5\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum TRIGGERED5_AW { + #[doc = "1: Enable"] + SET = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TRIGGERED5_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TRIGGERED5` writer - Write '1' to enable interrupt for event TRIGGERED\\[5\\]"] +pub type TRIGGERED5_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENSET_SPEC, TRIGGERED5_AW, O>; +impl<'a, const O: u8> TRIGGERED5_W<'a, O> { + #[doc = "Enable"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(TRIGGERED5_AW::SET) + } +} +#[doc = "Field `TRIGGERED6` reader - Write '1' to enable interrupt for event TRIGGERED\\[6\\]"] +pub type TRIGGERED6_R = crate::BitReader; +#[doc = "Write '1' to enable interrupt for event TRIGGERED\\[6\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum TRIGGERED6_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TRIGGERED6_A) -> Self { + variant as u8 != 0 + } +} +impl TRIGGERED6_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> TRIGGERED6_A { + match self.bits { + false => TRIGGERED6_A::DISABLED, + true => TRIGGERED6_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == TRIGGERED6_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == TRIGGERED6_A::ENABLED + } +} +#[doc = "Write '1' to enable interrupt for event TRIGGERED\\[6\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum TRIGGERED6_AW { + #[doc = "1: Enable"] + SET = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TRIGGERED6_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TRIGGERED6` writer - Write '1' to enable interrupt for event TRIGGERED\\[6\\]"] +pub type TRIGGERED6_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENSET_SPEC, TRIGGERED6_AW, O>; +impl<'a, const O: u8> TRIGGERED6_W<'a, O> { + #[doc = "Enable"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(TRIGGERED6_AW::SET) + } +} +#[doc = "Field `TRIGGERED7` reader - Write '1' to enable interrupt for event TRIGGERED\\[7\\]"] +pub type TRIGGERED7_R = crate::BitReader; +#[doc = "Write '1' to enable interrupt for event TRIGGERED\\[7\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum TRIGGERED7_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TRIGGERED7_A) -> Self { + variant as u8 != 0 + } +} +impl TRIGGERED7_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> TRIGGERED7_A { + match self.bits { + false => TRIGGERED7_A::DISABLED, + true => TRIGGERED7_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == TRIGGERED7_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == TRIGGERED7_A::ENABLED + } +} +#[doc = "Write '1' to enable interrupt for event TRIGGERED\\[7\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum TRIGGERED7_AW { + #[doc = "1: Enable"] + SET = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TRIGGERED7_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TRIGGERED7` writer - Write '1' to enable interrupt for event TRIGGERED\\[7\\]"] +pub type TRIGGERED7_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENSET_SPEC, TRIGGERED7_AW, O>; +impl<'a, const O: u8> TRIGGERED7_W<'a, O> { + #[doc = "Enable"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(TRIGGERED7_AW::SET) + } +} +#[doc = "Field `TRIGGERED8` reader - Write '1' to enable interrupt for event TRIGGERED\\[8\\]"] +pub type TRIGGERED8_R = crate::BitReader; +#[doc = "Write '1' to enable interrupt for event TRIGGERED\\[8\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum TRIGGERED8_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TRIGGERED8_A) -> Self { + variant as u8 != 0 + } +} +impl TRIGGERED8_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> TRIGGERED8_A { + match self.bits { + false => TRIGGERED8_A::DISABLED, + true => TRIGGERED8_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == TRIGGERED8_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == TRIGGERED8_A::ENABLED + } +} +#[doc = "Write '1' to enable interrupt for event TRIGGERED\\[8\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum TRIGGERED8_AW { + #[doc = "1: Enable"] + SET = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TRIGGERED8_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TRIGGERED8` writer - Write '1' to enable interrupt for event TRIGGERED\\[8\\]"] +pub type TRIGGERED8_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENSET_SPEC, TRIGGERED8_AW, O>; +impl<'a, const O: u8> TRIGGERED8_W<'a, O> { + #[doc = "Enable"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(TRIGGERED8_AW::SET) + } +} +#[doc = "Field `TRIGGERED9` reader - Write '1' to enable interrupt for event TRIGGERED\\[9\\]"] +pub type TRIGGERED9_R = crate::BitReader; +#[doc = "Write '1' to enable interrupt for event TRIGGERED\\[9\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum TRIGGERED9_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TRIGGERED9_A) -> Self { + variant as u8 != 0 + } +} +impl TRIGGERED9_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> TRIGGERED9_A { + match self.bits { + false => TRIGGERED9_A::DISABLED, + true => TRIGGERED9_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == TRIGGERED9_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == TRIGGERED9_A::ENABLED + } +} +#[doc = "Write '1' to enable interrupt for event TRIGGERED\\[9\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum TRIGGERED9_AW { + #[doc = "1: Enable"] + SET = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TRIGGERED9_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TRIGGERED9` writer - Write '1' to enable interrupt for event TRIGGERED\\[9\\]"] +pub type TRIGGERED9_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENSET_SPEC, TRIGGERED9_AW, O>; +impl<'a, const O: u8> TRIGGERED9_W<'a, O> { + #[doc = "Enable"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(TRIGGERED9_AW::SET) + } +} +#[doc = "Field `TRIGGERED10` reader - Write '1' to enable interrupt for event TRIGGERED\\[10\\]"] +pub type TRIGGERED10_R = crate::BitReader; +#[doc = "Write '1' to enable interrupt for event TRIGGERED\\[10\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum TRIGGERED10_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TRIGGERED10_A) -> Self { + variant as u8 != 0 + } +} +impl TRIGGERED10_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> TRIGGERED10_A { + match self.bits { + false => TRIGGERED10_A::DISABLED, + true => TRIGGERED10_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == TRIGGERED10_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == TRIGGERED10_A::ENABLED + } +} +#[doc = "Write '1' to enable interrupt for event TRIGGERED\\[10\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum TRIGGERED10_AW { + #[doc = "1: Enable"] + SET = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TRIGGERED10_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TRIGGERED10` writer - Write '1' to enable interrupt for event TRIGGERED\\[10\\]"] +pub type TRIGGERED10_W<'a, const O: u8> = + crate::BitWriter<'a, u32, INTENSET_SPEC, TRIGGERED10_AW, O>; +impl<'a, const O: u8> TRIGGERED10_W<'a, O> { + #[doc = "Enable"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(TRIGGERED10_AW::SET) + } +} +#[doc = "Field `TRIGGERED11` reader - Write '1' to enable interrupt for event TRIGGERED\\[11\\]"] +pub type TRIGGERED11_R = crate::BitReader; +#[doc = "Write '1' to enable interrupt for event TRIGGERED\\[11\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum TRIGGERED11_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TRIGGERED11_A) -> Self { + variant as u8 != 0 + } +} +impl TRIGGERED11_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> TRIGGERED11_A { + match self.bits { + false => TRIGGERED11_A::DISABLED, + true => TRIGGERED11_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == TRIGGERED11_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == TRIGGERED11_A::ENABLED + } +} +#[doc = "Write '1' to enable interrupt for event TRIGGERED\\[11\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum TRIGGERED11_AW { + #[doc = "1: Enable"] + SET = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TRIGGERED11_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TRIGGERED11` writer - Write '1' to enable interrupt for event TRIGGERED\\[11\\]"] +pub type TRIGGERED11_W<'a, const O: u8> = + crate::BitWriter<'a, u32, INTENSET_SPEC, TRIGGERED11_AW, O>; +impl<'a, const O: u8> TRIGGERED11_W<'a, O> { + #[doc = "Enable"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(TRIGGERED11_AW::SET) + } +} +#[doc = "Field `TRIGGERED12` reader - Write '1' to enable interrupt for event TRIGGERED\\[12\\]"] +pub type TRIGGERED12_R = crate::BitReader; +#[doc = "Write '1' to enable interrupt for event TRIGGERED\\[12\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum TRIGGERED12_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TRIGGERED12_A) -> Self { + variant as u8 != 0 + } +} +impl TRIGGERED12_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> TRIGGERED12_A { + match self.bits { + false => TRIGGERED12_A::DISABLED, + true => TRIGGERED12_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == TRIGGERED12_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == TRIGGERED12_A::ENABLED + } +} +#[doc = "Write '1' to enable interrupt for event TRIGGERED\\[12\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum TRIGGERED12_AW { + #[doc = "1: Enable"] + SET = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TRIGGERED12_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TRIGGERED12` writer - Write '1' to enable interrupt for event TRIGGERED\\[12\\]"] +pub type TRIGGERED12_W<'a, const O: u8> = + crate::BitWriter<'a, u32, INTENSET_SPEC, TRIGGERED12_AW, O>; +impl<'a, const O: u8> TRIGGERED12_W<'a, O> { + #[doc = "Enable"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(TRIGGERED12_AW::SET) + } +} +#[doc = "Field `TRIGGERED13` reader - Write '1' to enable interrupt for event TRIGGERED\\[13\\]"] +pub type TRIGGERED13_R = crate::BitReader; +#[doc = "Write '1' to enable interrupt for event TRIGGERED\\[13\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum TRIGGERED13_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TRIGGERED13_A) -> Self { + variant as u8 != 0 + } +} +impl TRIGGERED13_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> TRIGGERED13_A { + match self.bits { + false => TRIGGERED13_A::DISABLED, + true => TRIGGERED13_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == TRIGGERED13_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == TRIGGERED13_A::ENABLED + } +} +#[doc = "Write '1' to enable interrupt for event TRIGGERED\\[13\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum TRIGGERED13_AW { + #[doc = "1: Enable"] + SET = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TRIGGERED13_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TRIGGERED13` writer - Write '1' to enable interrupt for event TRIGGERED\\[13\\]"] +pub type TRIGGERED13_W<'a, const O: u8> = + crate::BitWriter<'a, u32, INTENSET_SPEC, TRIGGERED13_AW, O>; +impl<'a, const O: u8> TRIGGERED13_W<'a, O> { + #[doc = "Enable"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(TRIGGERED13_AW::SET) + } +} +#[doc = "Field `TRIGGERED14` reader - Write '1' to enable interrupt for event TRIGGERED\\[14\\]"] +pub type TRIGGERED14_R = crate::BitReader; +#[doc = "Write '1' to enable interrupt for event TRIGGERED\\[14\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum TRIGGERED14_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TRIGGERED14_A) -> Self { + variant as u8 != 0 + } +} +impl TRIGGERED14_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> TRIGGERED14_A { + match self.bits { + false => TRIGGERED14_A::DISABLED, + true => TRIGGERED14_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == TRIGGERED14_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == TRIGGERED14_A::ENABLED + } +} +#[doc = "Write '1' to enable interrupt for event TRIGGERED\\[14\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum TRIGGERED14_AW { + #[doc = "1: Enable"] + SET = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TRIGGERED14_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TRIGGERED14` writer - Write '1' to enable interrupt for event TRIGGERED\\[14\\]"] +pub type TRIGGERED14_W<'a, const O: u8> = + crate::BitWriter<'a, u32, INTENSET_SPEC, TRIGGERED14_AW, O>; +impl<'a, const O: u8> TRIGGERED14_W<'a, O> { + #[doc = "Enable"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(TRIGGERED14_AW::SET) + } +} +#[doc = "Field `TRIGGERED15` reader - Write '1' to enable interrupt for event TRIGGERED\\[15\\]"] +pub type TRIGGERED15_R = crate::BitReader; +#[doc = "Write '1' to enable interrupt for event TRIGGERED\\[15\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum TRIGGERED15_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TRIGGERED15_A) -> Self { + variant as u8 != 0 + } +} +impl TRIGGERED15_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> TRIGGERED15_A { + match self.bits { + false => TRIGGERED15_A::DISABLED, + true => TRIGGERED15_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == TRIGGERED15_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == TRIGGERED15_A::ENABLED + } +} +#[doc = "Write '1' to enable interrupt for event TRIGGERED\\[15\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum TRIGGERED15_AW { + #[doc = "1: Enable"] + SET = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TRIGGERED15_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TRIGGERED15` writer - Write '1' to enable interrupt for event TRIGGERED\\[15\\]"] +pub type TRIGGERED15_W<'a, const O: u8> = + crate::BitWriter<'a, u32, INTENSET_SPEC, TRIGGERED15_AW, O>; +impl<'a, const O: u8> TRIGGERED15_W<'a, O> { + #[doc = "Enable"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(TRIGGERED15_AW::SET) + } +} +impl R { + #[doc = "Bit 0 - Write '1' to enable interrupt for event TRIGGERED\\[0\\]"] + #[inline(always)] + pub fn triggered0(&self) -> TRIGGERED0_R { + TRIGGERED0_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Write '1' to enable interrupt for event TRIGGERED\\[1\\]"] + #[inline(always)] + pub fn triggered1(&self) -> TRIGGERED1_R { + TRIGGERED1_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Write '1' to enable interrupt for event TRIGGERED\\[2\\]"] + #[inline(always)] + pub fn triggered2(&self) -> TRIGGERED2_R { + TRIGGERED2_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Write '1' to enable interrupt for event TRIGGERED\\[3\\]"] + #[inline(always)] + pub fn triggered3(&self) -> TRIGGERED3_R { + TRIGGERED3_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Write '1' to enable interrupt for event TRIGGERED\\[4\\]"] + #[inline(always)] + pub fn triggered4(&self) -> TRIGGERED4_R { + TRIGGERED4_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Write '1' to enable interrupt for event TRIGGERED\\[5\\]"] + #[inline(always)] + pub fn triggered5(&self) -> TRIGGERED5_R { + TRIGGERED5_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Write '1' to enable interrupt for event TRIGGERED\\[6\\]"] + #[inline(always)] + pub fn triggered6(&self) -> TRIGGERED6_R { + TRIGGERED6_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Write '1' to enable interrupt for event TRIGGERED\\[7\\]"] + #[inline(always)] + pub fn triggered7(&self) -> TRIGGERED7_R { + TRIGGERED7_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Write '1' to enable interrupt for event TRIGGERED\\[8\\]"] + #[inline(always)] + pub fn triggered8(&self) -> TRIGGERED8_R { + TRIGGERED8_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Write '1' to enable interrupt for event TRIGGERED\\[9\\]"] + #[inline(always)] + pub fn triggered9(&self) -> TRIGGERED9_R { + TRIGGERED9_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Write '1' to enable interrupt for event TRIGGERED\\[10\\]"] + #[inline(always)] + pub fn triggered10(&self) -> TRIGGERED10_R { + TRIGGERED10_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Write '1' to enable interrupt for event TRIGGERED\\[11\\]"] + #[inline(always)] + pub fn triggered11(&self) -> TRIGGERED11_R { + TRIGGERED11_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Write '1' to enable interrupt for event TRIGGERED\\[12\\]"] + #[inline(always)] + pub fn triggered12(&self) -> TRIGGERED12_R { + TRIGGERED12_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Write '1' to enable interrupt for event TRIGGERED\\[13\\]"] + #[inline(always)] + pub fn triggered13(&self) -> TRIGGERED13_R { + TRIGGERED13_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Write '1' to enable interrupt for event TRIGGERED\\[14\\]"] + #[inline(always)] + pub fn triggered14(&self) -> TRIGGERED14_R { + TRIGGERED14_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Write '1' to enable interrupt for event TRIGGERED\\[15\\]"] + #[inline(always)] + pub fn triggered15(&self) -> TRIGGERED15_R { + TRIGGERED15_R::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Write '1' to enable interrupt for event TRIGGERED\\[0\\]"] + #[inline(always)] + pub fn triggered0(&mut self) -> TRIGGERED0_W<0> { + TRIGGERED0_W::new(self) + } + #[doc = "Bit 1 - Write '1' to enable interrupt for event TRIGGERED\\[1\\]"] + #[inline(always)] + pub fn triggered1(&mut self) -> TRIGGERED1_W<1> { + TRIGGERED1_W::new(self) + } + #[doc = "Bit 2 - Write '1' to enable interrupt for event TRIGGERED\\[2\\]"] + #[inline(always)] + pub fn triggered2(&mut self) -> TRIGGERED2_W<2> { + TRIGGERED2_W::new(self) + } + #[doc = "Bit 3 - Write '1' to enable interrupt for event TRIGGERED\\[3\\]"] + #[inline(always)] + pub fn triggered3(&mut self) -> TRIGGERED3_W<3> { + TRIGGERED3_W::new(self) + } + #[doc = "Bit 4 - Write '1' to enable interrupt for event TRIGGERED\\[4\\]"] + #[inline(always)] + pub fn triggered4(&mut self) -> TRIGGERED4_W<4> { + TRIGGERED4_W::new(self) + } + #[doc = "Bit 5 - Write '1' to enable interrupt for event TRIGGERED\\[5\\]"] + #[inline(always)] + pub fn triggered5(&mut self) -> TRIGGERED5_W<5> { + TRIGGERED5_W::new(self) + } + #[doc = "Bit 6 - Write '1' to enable interrupt for event TRIGGERED\\[6\\]"] + #[inline(always)] + pub fn triggered6(&mut self) -> TRIGGERED6_W<6> { + TRIGGERED6_W::new(self) + } + #[doc = "Bit 7 - Write '1' to enable interrupt for event TRIGGERED\\[7\\]"] + #[inline(always)] + pub fn triggered7(&mut self) -> TRIGGERED7_W<7> { + TRIGGERED7_W::new(self) + } + #[doc = "Bit 8 - Write '1' to enable interrupt for event TRIGGERED\\[8\\]"] + #[inline(always)] + pub fn triggered8(&mut self) -> TRIGGERED8_W<8> { + TRIGGERED8_W::new(self) + } + #[doc = "Bit 9 - Write '1' to enable interrupt for event TRIGGERED\\[9\\]"] + #[inline(always)] + pub fn triggered9(&mut self) -> TRIGGERED9_W<9> { + TRIGGERED9_W::new(self) + } + #[doc = "Bit 10 - Write '1' to enable interrupt for event TRIGGERED\\[10\\]"] + #[inline(always)] + pub fn triggered10(&mut self) -> TRIGGERED10_W<10> { + TRIGGERED10_W::new(self) + } + #[doc = "Bit 11 - Write '1' to enable interrupt for event TRIGGERED\\[11\\]"] + #[inline(always)] + pub fn triggered11(&mut self) -> TRIGGERED11_W<11> { + TRIGGERED11_W::new(self) + } + #[doc = "Bit 12 - Write '1' to enable interrupt for event TRIGGERED\\[12\\]"] + #[inline(always)] + pub fn triggered12(&mut self) -> TRIGGERED12_W<12> { + TRIGGERED12_W::new(self) + } + #[doc = "Bit 13 - Write '1' to enable interrupt for event TRIGGERED\\[13\\]"] + #[inline(always)] + pub fn triggered13(&mut self) -> TRIGGERED13_W<13> { + TRIGGERED13_W::new(self) + } + #[doc = "Bit 14 - Write '1' to enable interrupt for event TRIGGERED\\[14\\]"] + #[inline(always)] + pub fn triggered14(&mut self) -> TRIGGERED14_W<14> { + TRIGGERED14_W::new(self) + } + #[doc = "Bit 15 - Write '1' to enable interrupt for event TRIGGERED\\[15\\]"] + #[inline(always)] + pub fn triggered15(&mut self) -> TRIGGERED15_W<15> { + TRIGGERED15_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Enable interrupt\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/egu0_ns/publish_triggered.rs b/pacs/nrf9120-pac/src/egu0_ns/publish_triggered.rs new file mode 100644 index 00000000..b807b57e --- /dev/null +++ b/pacs/nrf9120-pac/src/egu0_ns/publish_triggered.rs @@ -0,0 +1,146 @@ +#[doc = "Register `PUBLISH_TRIGGERED[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PUBLISH_TRIGGERED[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CHIDX` reader - DPPI channel that event TRIGGERED\\[n\\] +will publish to"] +pub type CHIDX_R = crate::FieldReader; +#[doc = "Field `CHIDX` writer - DPPI channel that event TRIGGERED\\[n\\] +will publish to"] +pub type CHIDX_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, PUBLISH_TRIGGERED_SPEC, u8, u8, 8, O>; +#[doc = "Field `EN` reader - "] +pub type EN_R = crate::BitReader; +#[doc = "\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum EN_A { + #[doc = "0: Disable publishing"] + DISABLED = 0, + #[doc = "1: Enable publishing"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: EN_A) -> Self { + variant as u8 != 0 + } +} +impl EN_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EN_A { + match self.bits { + false => EN_A::DISABLED, + true => EN_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == EN_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == EN_A::ENABLED + } +} +#[doc = "Field `EN` writer - "] +pub type EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, PUBLISH_TRIGGERED_SPEC, EN_A, O>; +impl<'a, const O: u8> EN_W<'a, O> { + #[doc = "Disable publishing"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(EN_A::DISABLED) + } + #[doc = "Enable publishing"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(EN_A::ENABLED) + } +} +impl R { + #[doc = "Bits 0:7 - DPPI channel that event TRIGGERED\\[n\\] +will publish to"] + #[inline(always)] + pub fn chidx(&self) -> CHIDX_R { + CHIDX_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&self) -> EN_R { + EN_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:7 - DPPI channel that event TRIGGERED\\[n\\] +will publish to"] + #[inline(always)] + pub fn chidx(&mut self) -> CHIDX_W<0> { + CHIDX_W::new(self) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&mut self) -> EN_W<31> { + EN_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Description collection: Publish configuration for event TRIGGERED\\[n\\]\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [publish_triggered](index.html) module"] +pub struct PUBLISH_TRIGGERED_SPEC; +impl crate::RegisterSpec for PUBLISH_TRIGGERED_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [publish_triggered::R](R) reader structure"] +impl crate::Readable for PUBLISH_TRIGGERED_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [publish_triggered::W](W) writer structure"] +impl crate::Writable for PUBLISH_TRIGGERED_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PUBLISH_TRIGGERED[%s] +to value 0"] +impl crate::Resettable for PUBLISH_TRIGGERED_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/egu0_ns/subscribe_trigger.rs b/pacs/nrf9120-pac/src/egu0_ns/subscribe_trigger.rs new file mode 100644 index 00000000..6e93994a --- /dev/null +++ b/pacs/nrf9120-pac/src/egu0_ns/subscribe_trigger.rs @@ -0,0 +1,146 @@ +#[doc = "Register `SUBSCRIBE_TRIGGER[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SUBSCRIBE_TRIGGER[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CHIDX` reader - DPPI channel that task TRIGGER\\[n\\] +will subscribe to"] +pub type CHIDX_R = crate::FieldReader; +#[doc = "Field `CHIDX` writer - DPPI channel that task TRIGGER\\[n\\] +will subscribe to"] +pub type CHIDX_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, SUBSCRIBE_TRIGGER_SPEC, u8, u8, 8, O>; +#[doc = "Field `EN` reader - "] +pub type EN_R = crate::BitReader; +#[doc = "\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum EN_A { + #[doc = "0: Disable subscription"] + DISABLED = 0, + #[doc = "1: Enable subscription"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: EN_A) -> Self { + variant as u8 != 0 + } +} +impl EN_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EN_A { + match self.bits { + false => EN_A::DISABLED, + true => EN_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == EN_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == EN_A::ENABLED + } +} +#[doc = "Field `EN` writer - "] +pub type EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, SUBSCRIBE_TRIGGER_SPEC, EN_A, O>; +impl<'a, const O: u8> EN_W<'a, O> { + #[doc = "Disable subscription"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(EN_A::DISABLED) + } + #[doc = "Enable subscription"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(EN_A::ENABLED) + } +} +impl R { + #[doc = "Bits 0:7 - DPPI channel that task TRIGGER\\[n\\] +will subscribe to"] + #[inline(always)] + pub fn chidx(&self) -> CHIDX_R { + CHIDX_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&self) -> EN_R { + EN_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:7 - DPPI channel that task TRIGGER\\[n\\] +will subscribe to"] + #[inline(always)] + pub fn chidx(&mut self) -> CHIDX_W<0> { + CHIDX_W::new(self) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&mut self) -> EN_W<31> { + EN_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Description collection: Subscribe configuration for task TRIGGER\\[n\\]\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [subscribe_trigger](index.html) module"] +pub struct SUBSCRIBE_TRIGGER_SPEC; +impl crate::RegisterSpec for SUBSCRIBE_TRIGGER_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [subscribe_trigger::R](R) reader structure"] +impl crate::Readable for SUBSCRIBE_TRIGGER_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [subscribe_trigger::W](W) writer structure"] +impl crate::Writable for SUBSCRIBE_TRIGGER_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SUBSCRIBE_TRIGGER[%s] +to value 0"] +impl crate::Resettable for SUBSCRIBE_TRIGGER_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/egu0_ns/tasks_trigger.rs b/pacs/nrf9120-pac/src/egu0_ns/tasks_trigger.rs new file mode 100644 index 00000000..637df5a5 --- /dev/null +++ b/pacs/nrf9120-pac/src/egu0_ns/tasks_trigger.rs @@ -0,0 +1,77 @@ +#[doc = "Register `TASKS_TRIGGER[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Trigger n for triggering the corresponding TRIGGERED\\[n\\] +event\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum TASKS_TRIGGER_AW { + #[doc = "1: Trigger task"] + TRIGGER = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TASKS_TRIGGER_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TASKS_TRIGGER` writer - Trigger n for triggering the corresponding TRIGGERED\\[n\\] +event"] +pub type TASKS_TRIGGER_W<'a, const O: u8> = + crate::BitWriter<'a, u32, TASKS_TRIGGER_SPEC, TASKS_TRIGGER_AW, O>; +impl<'a, const O: u8> TASKS_TRIGGER_W<'a, O> { + #[doc = "Trigger task"] + #[inline(always)] + pub fn trigger(self) -> &'a mut W { + self.variant(TASKS_TRIGGER_AW::TRIGGER) + } +} +impl W { + #[doc = "Bit 0 - Trigger n for triggering the corresponding TRIGGERED\\[n\\] +event"] + #[inline(always)] + pub fn tasks_trigger(&mut self) -> TASKS_TRIGGER_W<0> { + TASKS_TRIGGER_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Description collection: Trigger n for triggering the corresponding TRIGGERED\\[n\\] +event\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tasks_trigger](index.html) module"] +pub struct TASKS_TRIGGER_SPEC; +impl crate::RegisterSpec for TASKS_TRIGGER_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [tasks_trigger::W](W) writer structure"] +impl crate::Writable for TASKS_TRIGGER_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets TASKS_TRIGGER[%s] +to value 0"] +impl crate::Resettable for TASKS_TRIGGER_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/ficr_s.rs b/pacs/nrf9120-pac/src/ficr_s.rs new file mode 100644 index 00000000..98e5bd51 --- /dev/null +++ b/pacs/nrf9120-pac/src/ficr_s.rs @@ -0,0 +1,36 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + _reserved0: [u8; 0x0140], + #[doc = "0x140..0x14c - SIP-specific device info"] + pub sipinfo: SIPINFO, + _reserved1: [u8; 0xb4], + #[doc = "0x200..0x22c - Device info"] + pub info: INFO, + _reserved2: [u8; 0xd4], + #[doc = "0x300..0xb00 - Unspecified"] + pub trimcnf: [TRIMCNF; 256], + _reserved3: [u8; 0x0100], + #[doc = "0xc00..0xc20 - NIST800-90B RNG calibration data"] + pub trng90b: TRNG90B, +} +#[doc = "SIP-specific device info"] +pub use sipinfo::SIPINFO; +#[doc = r"Cluster"] +#[doc = "SIP-specific device info"] +pub mod sipinfo; +#[doc = "Device info"] +pub use info::INFO; +#[doc = r"Cluster"] +#[doc = "Device info"] +pub mod info; +#[doc = "Unspecified"] +pub use trimcnf::TRIMCNF; +#[doc = r"Cluster"] +#[doc = "Unspecified"] +pub mod trimcnf; +#[doc = "NIST800-90B RNG calibration data"] +pub use trng90b::TRNG90B; +#[doc = r"Cluster"] +#[doc = "NIST800-90B RNG calibration data"] +pub mod trng90b; diff --git a/pacs/nrf9120-pac/src/ficr_s/info.rs b/pacs/nrf9120-pac/src/ficr_s/info.rs new file mode 100644 index 00000000..e2b19d8d --- /dev/null +++ b/pacs/nrf9120-pac/src/ficr_s/info.rs @@ -0,0 +1,59 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct INFO { + _reserved0: [u8; 0x04], + #[doc = "0x04..0x0c - Description collection: Device identifier"] + pub deviceid: [DEVICEID; 2], + #[doc = "0x0c - Part code"] + pub part: PART, + #[doc = "0x10 - Part Variant, Hardware version and Production configuration"] + pub variant: VARIANT, + #[doc = "0x14 - Package option"] + pub package: PACKAGE, + #[doc = "0x18 - RAM variant"] + pub ram: RAM, + #[doc = "0x1c - Flash variant"] + pub flash: FLASH, + #[doc = "0x20 - Code memory page size"] + pub codepagesize: CODEPAGESIZE, + #[doc = "0x24 - Code memory size"] + pub codesize: CODESIZE, + #[doc = "0x28 - Device type"] + pub devicetype: DEVICETYPE, +} +#[doc = "DEVICEID (r) register accessor: an alias for `Reg`"] +pub type DEVICEID = crate::Reg; +#[doc = "Description collection: Device identifier"] +pub mod deviceid; +#[doc = "PART (r) register accessor: an alias for `Reg`"] +pub type PART = crate::Reg; +#[doc = "Part code"] +pub mod part; +#[doc = "VARIANT (r) register accessor: an alias for `Reg`"] +pub type VARIANT = crate::Reg; +#[doc = "Part Variant, Hardware version and Production configuration"] +pub mod variant; +#[doc = "PACKAGE (r) register accessor: an alias for `Reg`"] +pub type PACKAGE = crate::Reg; +#[doc = "Package option"] +pub mod package; +#[doc = "RAM (r) register accessor: an alias for `Reg`"] +pub type RAM = crate::Reg; +#[doc = "RAM variant"] +pub mod ram; +#[doc = "FLASH (r) register accessor: an alias for `Reg`"] +pub type FLASH = crate::Reg; +#[doc = "Flash variant"] +pub mod flash; +#[doc = "CODEPAGESIZE (r) register accessor: an alias for `Reg`"] +pub type CODEPAGESIZE = crate::Reg; +#[doc = "Code memory page size"] +pub mod codepagesize; +#[doc = "CODESIZE (r) register accessor: an alias for `Reg`"] +pub type CODESIZE = crate::Reg; +#[doc = "Code memory size"] +pub mod codesize; +#[doc = "DEVICETYPE (r) register accessor: an alias for `Reg`"] +pub type DEVICETYPE = crate::Reg; +#[doc = "Device type"] +pub mod devicetype; diff --git a/pacs/nrf9120-pac/src/ficr_s/info/codepagesize.rs b/pacs/nrf9120-pac/src/ficr_s/info/codepagesize.rs new file mode 100644 index 00000000..098ba13f --- /dev/null +++ b/pacs/nrf9120-pac/src/ficr_s/info/codepagesize.rs @@ -0,0 +1,68 @@ +#[doc = "Register `CODEPAGESIZE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `CODEPAGESIZE` reader - Code memory page size"] +pub type CODEPAGESIZE_R = crate::FieldReader; +#[doc = "Code memory page size\n\nValue on reset: 4096"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u32)] +pub enum CODEPAGESIZE_A { + #[doc = "4096: 4 kByte"] + K4096 = 4096, +} +impl From for u32 { + #[inline(always)] + fn from(variant: CODEPAGESIZE_A) -> Self { + variant as _ + } +} +impl CODEPAGESIZE_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 4096 => Some(CODEPAGESIZE_A::K4096), + _ => None, + } + } + #[doc = "Checks if the value of the field is `K4096`"] + #[inline(always)] + pub fn is_k4096(&self) -> bool { + *self == CODEPAGESIZE_A::K4096 + } +} +impl R { + #[doc = "Bits 0:31 - Code memory page size"] + #[inline(always)] + pub fn codepagesize(&self) -> CODEPAGESIZE_R { + CODEPAGESIZE_R::new(self.bits) + } +} +#[doc = "Code memory page size\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [codepagesize](index.html) module"] +pub struct CODEPAGESIZE_SPEC; +impl crate::RegisterSpec for CODEPAGESIZE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [codepagesize::R](R) reader structure"] +impl crate::Readable for CODEPAGESIZE_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets CODEPAGESIZE to value 0x1000"] +impl crate::Resettable for CODEPAGESIZE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x1000 + } +} diff --git a/pacs/nrf9120-pac/src/ficr_s/info/codesize.rs b/pacs/nrf9120-pac/src/ficr_s/info/codesize.rs new file mode 100644 index 00000000..dcba4268 --- /dev/null +++ b/pacs/nrf9120-pac/src/ficr_s/info/codesize.rs @@ -0,0 +1,68 @@ +#[doc = "Register `CODESIZE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `CODESIZE` reader - Code memory size in number of pages Total code space is: CODEPAGESIZE * CODESIZE"] +pub type CODESIZE_R = crate::FieldReader; +#[doc = "Code memory size in number of pages Total code space is: CODEPAGESIZE * CODESIZE\n\nValue on reset: 256"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u32)] +pub enum CODESIZE_A { + #[doc = "256: 256 pages"] + P256 = 256, +} +impl From for u32 { + #[inline(always)] + fn from(variant: CODESIZE_A) -> Self { + variant as _ + } +} +impl CODESIZE_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 256 => Some(CODESIZE_A::P256), + _ => None, + } + } + #[doc = "Checks if the value of the field is `P256`"] + #[inline(always)] + pub fn is_p256(&self) -> bool { + *self == CODESIZE_A::P256 + } +} +impl R { + #[doc = "Bits 0:31 - Code memory size in number of pages Total code space is: CODEPAGESIZE * CODESIZE"] + #[inline(always)] + pub fn codesize(&self) -> CODESIZE_R { + CODESIZE_R::new(self.bits) + } +} +#[doc = "Code memory size\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [codesize](index.html) module"] +pub struct CODESIZE_SPEC; +impl crate::RegisterSpec for CODESIZE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [codesize::R](R) reader structure"] +impl crate::Readable for CODESIZE_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets CODESIZE to value 0x0100"] +impl crate::Resettable for CODESIZE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x0100 + } +} diff --git a/pacs/nrf9120-pac/src/ficr_s/info/deviceid.rs b/pacs/nrf9120-pac/src/ficr_s/info/deviceid.rs new file mode 100644 index 00000000..b277e959 --- /dev/null +++ b/pacs/nrf9120-pac/src/ficr_s/info/deviceid.rs @@ -0,0 +1,41 @@ +#[doc = "Register `DEVICEID[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `DEVICEID` reader - 64 bit unique device identifier"] +pub type DEVICEID_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - 64 bit unique device identifier"] + #[inline(always)] + pub fn deviceid(&self) -> DEVICEID_R { + DEVICEID_R::new(self.bits) + } +} +#[doc = "Description collection: Device identifier\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [deviceid](index.html) module"] +pub struct DEVICEID_SPEC; +impl crate::RegisterSpec for DEVICEID_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [deviceid::R](R) reader structure"] +impl crate::Readable for DEVICEID_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets DEVICEID[%s] +to value 0xffff_ffff"] +impl crate::Resettable for DEVICEID_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0xffff_ffff + } +} diff --git a/pacs/nrf9120-pac/src/ficr_s/info/devicetype.rs b/pacs/nrf9120-pac/src/ficr_s/info/devicetype.rs new file mode 100644 index 00000000..e2266301 --- /dev/null +++ b/pacs/nrf9120-pac/src/ficr_s/info/devicetype.rs @@ -0,0 +1,76 @@ +#[doc = "Register `DEVICETYPE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `DEVICETYPE` reader - Device type"] +pub type DEVICETYPE_R = crate::FieldReader; +#[doc = "Device type\n\nValue on reset: 4294967295"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u32)] +pub enum DEVICETYPE_A { + #[doc = "0: Device is an physical DIE"] + DIE = 0, + #[doc = "4294967295: Device is an FPGA"] + FPGA = 4294967295, +} +impl From for u32 { + #[inline(always)] + fn from(variant: DEVICETYPE_A) -> Self { + variant as _ + } +} +impl DEVICETYPE_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(DEVICETYPE_A::DIE), + 4294967295 => Some(DEVICETYPE_A::FPGA), + _ => None, + } + } + #[doc = "Checks if the value of the field is `DIE`"] + #[inline(always)] + pub fn is_die(&self) -> bool { + *self == DEVICETYPE_A::DIE + } + #[doc = "Checks if the value of the field is `FPGA`"] + #[inline(always)] + pub fn is_fpga(&self) -> bool { + *self == DEVICETYPE_A::FPGA + } +} +impl R { + #[doc = "Bits 0:31 - Device type"] + #[inline(always)] + pub fn devicetype(&self) -> DEVICETYPE_R { + DEVICETYPE_R::new(self.bits) + } +} +#[doc = "Device type\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [devicetype](index.html) module"] +pub struct DEVICETYPE_SPEC; +impl crate::RegisterSpec for DEVICETYPE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [devicetype::R](R) reader structure"] +impl crate::Readable for DEVICETYPE_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets DEVICETYPE to value 0xffff_ffff"] +impl crate::Resettable for DEVICETYPE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0xffff_ffff + } +} diff --git a/pacs/nrf9120-pac/src/ficr_s/info/flash.rs b/pacs/nrf9120-pac/src/ficr_s/info/flash.rs new file mode 100644 index 00000000..bf67a4ca --- /dev/null +++ b/pacs/nrf9120-pac/src/ficr_s/info/flash.rs @@ -0,0 +1,68 @@ +#[doc = "Register `FLASH` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `FLASH` reader - Flash variant"] +pub type FLASH_R = crate::FieldReader; +#[doc = "Flash variant\n\nValue on reset: 1024"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u32)] +pub enum FLASH_A { + #[doc = "1024: 1 MByte FLASH"] + K1024 = 1024, +} +impl From for u32 { + #[inline(always)] + fn from(variant: FLASH_A) -> Self { + variant as _ + } +} +impl FLASH_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 1024 => Some(FLASH_A::K1024), + _ => None, + } + } + #[doc = "Checks if the value of the field is `K1024`"] + #[inline(always)] + pub fn is_k1024(&self) -> bool { + *self == FLASH_A::K1024 + } +} +impl R { + #[doc = "Bits 0:31 - Flash variant"] + #[inline(always)] + pub fn flash(&self) -> FLASH_R { + FLASH_R::new(self.bits) + } +} +#[doc = "Flash variant\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [flash](index.html) module"] +pub struct FLASH_SPEC; +impl crate::RegisterSpec for FLASH_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [flash::R](R) reader structure"] +impl crate::Readable for FLASH_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets FLASH to value 0x0400"] +impl crate::Resettable for FLASH_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x0400 + } +} diff --git a/pacs/nrf9120-pac/src/ficr_s/info/package.rs b/pacs/nrf9120-pac/src/ficr_s/info/package.rs new file mode 100644 index 00000000..852cd167 --- /dev/null +++ b/pacs/nrf9120-pac/src/ficr_s/info/package.rs @@ -0,0 +1,68 @@ +#[doc = "Register `PACKAGE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `PACKAGE` reader - Package option"] +pub type PACKAGE_R = crate::FieldReader; +#[doc = "Package option\n\nValue on reset: 8192"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u32)] +pub enum PACKAGE_A { + #[doc = "8194: CFxx - 236 ball wlCSP"] + CF = 8194, +} +impl From for u32 { + #[inline(always)] + fn from(variant: PACKAGE_A) -> Self { + variant as _ + } +} +impl PACKAGE_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 8194 => Some(PACKAGE_A::CF), + _ => None, + } + } + #[doc = "Checks if the value of the field is `CF`"] + #[inline(always)] + pub fn is_cf(&self) -> bool { + *self == PACKAGE_A::CF + } +} +impl R { + #[doc = "Bits 0:31 - Package option"] + #[inline(always)] + pub fn package(&self) -> PACKAGE_R { + PACKAGE_R::new(self.bits) + } +} +#[doc = "Package option\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [package](index.html) module"] +pub struct PACKAGE_SPEC; +impl crate::RegisterSpec for PACKAGE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [package::R](R) reader structure"] +impl crate::Readable for PACKAGE_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PACKAGE to value 0x2000"] +impl crate::Resettable for PACKAGE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x2000 + } +} diff --git a/pacs/nrf9120-pac/src/ficr_s/info/part.rs b/pacs/nrf9120-pac/src/ficr_s/info/part.rs new file mode 100644 index 00000000..b625a686 --- /dev/null +++ b/pacs/nrf9120-pac/src/ficr_s/info/part.rs @@ -0,0 +1,76 @@ +#[doc = "Register `PART` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `PART` reader - Part code"] +pub type PART_R = crate::FieldReader; +#[doc = "Part code\n\nValue on reset: 4294967295"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u32)] +pub enum PART_A { + #[doc = "37216: nRF9160"] + N9160 = 37216, + #[doc = "37152: nRF9120"] + N9120 = 37152, +} +impl From for u32 { + #[inline(always)] + fn from(variant: PART_A) -> Self { + variant as _ + } +} +impl PART_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 37216 => Some(PART_A::N9160), + 37152 => Some(PART_A::N9120), + _ => None, + } + } + #[doc = "Checks if the value of the field is `N9160`"] + #[inline(always)] + pub fn is_n9160(&self) -> bool { + *self == PART_A::N9160 + } + #[doc = "Checks if the value of the field is `N9120`"] + #[inline(always)] + pub fn is_n9120(&self) -> bool { + *self == PART_A::N9120 + } +} +impl R { + #[doc = "Bits 0:31 - Part code"] + #[inline(always)] + pub fn part(&self) -> PART_R { + PART_R::new(self.bits) + } +} +#[doc = "Part code\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [part](index.html) module"] +pub struct PART_SPEC; +impl crate::RegisterSpec for PART_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [part::R](R) reader structure"] +impl crate::Readable for PART_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PART to value 0xffff_ffff"] +impl crate::Resettable for PART_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0xffff_ffff + } +} diff --git a/pacs/nrf9120-pac/src/ficr_s/info/ram.rs b/pacs/nrf9120-pac/src/ficr_s/info/ram.rs new file mode 100644 index 00000000..67f444a9 --- /dev/null +++ b/pacs/nrf9120-pac/src/ficr_s/info/ram.rs @@ -0,0 +1,76 @@ +#[doc = "Register `RAM` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `RAM` reader - RAM variant"] +pub type RAM_R = crate::FieldReader; +#[doc = "RAM variant\n\nValue on reset: 256"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u32)] +pub enum RAM_A { + #[doc = "256: 256 kByte RAM"] + K256 = 256, + #[doc = "4294967295: Unspecified"] + UNSPECIFIED = 4294967295, +} +impl From for u32 { + #[inline(always)] + fn from(variant: RAM_A) -> Self { + variant as _ + } +} +impl RAM_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 256 => Some(RAM_A::K256), + 4294967295 => Some(RAM_A::UNSPECIFIED), + _ => None, + } + } + #[doc = "Checks if the value of the field is `K256`"] + #[inline(always)] + pub fn is_k256(&self) -> bool { + *self == RAM_A::K256 + } + #[doc = "Checks if the value of the field is `UNSPECIFIED`"] + #[inline(always)] + pub fn is_unspecified(&self) -> bool { + *self == RAM_A::UNSPECIFIED + } +} +impl R { + #[doc = "Bits 0:31 - RAM variant"] + #[inline(always)] + pub fn ram(&self) -> RAM_R { + RAM_R::new(self.bits) + } +} +#[doc = "RAM variant\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ram](index.html) module"] +pub struct RAM_SPEC; +impl crate::RegisterSpec for RAM_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ram::R](R) reader structure"] +impl crate::Readable for RAM_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets RAM to value 0x0100"] +impl crate::Resettable for RAM_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x0100 + } +} diff --git a/pacs/nrf9120-pac/src/ficr_s/info/variant.rs b/pacs/nrf9120-pac/src/ficr_s/info/variant.rs new file mode 100644 index 00000000..715d7893 --- /dev/null +++ b/pacs/nrf9120-pac/src/ficr_s/info/variant.rs @@ -0,0 +1,92 @@ +#[doc = "Register `VARIANT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `VARIANT` reader - Part Variant, Hardware version and Production configuration, encoded as ASCII"] +pub type VARIANT_R = crate::FieldReader; +#[doc = "Part Variant, Hardware version and Production configuration, encoded as ASCII\n\nValue on reset: 268435455"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u32)] +pub enum VARIANT_A { + #[doc = "1094795585: AAAA"] + AAAA = 1094795585, + #[doc = "1094795568: AAA0"] + AAA0 = 1094795568, + #[doc = "1094795824: AAB0"] + AAB0 = 1094795824, + #[doc = "1094796080: AAC0"] + AAC0 = 1094796080, +} +impl From for u32 { + #[inline(always)] + fn from(variant: VARIANT_A) -> Self { + variant as _ + } +} +impl VARIANT_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 1094795585 => Some(VARIANT_A::AAAA), + 1094795568 => Some(VARIANT_A::AAA0), + 1094795824 => Some(VARIANT_A::AAB0), + 1094796080 => Some(VARIANT_A::AAC0), + _ => None, + } + } + #[doc = "Checks if the value of the field is `AAAA`"] + #[inline(always)] + pub fn is_aaaa(&self) -> bool { + *self == VARIANT_A::AAAA + } + #[doc = "Checks if the value of the field is `AAA0`"] + #[inline(always)] + pub fn is_aaa0(&self) -> bool { + *self == VARIANT_A::AAA0 + } + #[doc = "Checks if the value of the field is `AAB0`"] + #[inline(always)] + pub fn is_aab0(&self) -> bool { + *self == VARIANT_A::AAB0 + } + #[doc = "Checks if the value of the field is `AAC0`"] + #[inline(always)] + pub fn is_aac0(&self) -> bool { + *self == VARIANT_A::AAC0 + } +} +impl R { + #[doc = "Bits 0:31 - Part Variant, Hardware version and Production configuration, encoded as ASCII"] + #[inline(always)] + pub fn variant(&self) -> VARIANT_R { + VARIANT_R::new(self.bits) + } +} +#[doc = "Part Variant, Hardware version and Production configuration\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [variant](index.html) module"] +pub struct VARIANT_SPEC; +impl crate::RegisterSpec for VARIANT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [variant::R](R) reader structure"] +impl crate::Readable for VARIANT_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets VARIANT to value 0x0fff_ffff"] +impl crate::Resettable for VARIANT_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x0fff_ffff + } +} diff --git a/pacs/nrf9120-pac/src/ficr_s/sipinfo.rs b/pacs/nrf9120-pac/src/ficr_s/sipinfo.rs new file mode 100644 index 00000000..7503fda6 --- /dev/null +++ b/pacs/nrf9120-pac/src/ficr_s/sipinfo.rs @@ -0,0 +1,22 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct SIPINFO { + #[doc = "0x00 - SIP part number"] + pub partno: PARTNO, + #[doc = "0x04 - Description collection: SIP hardware revision, encoded in ASCII, ex B0A or B1A"] + pub hwrevision: [HWREVISION; 4], + #[doc = "0x08 - Description collection: SIP VARIANT, encoded in ASCII, ex SIAA, SIBA or SICA"] + pub variant: [VARIANT; 4], +} +#[doc = "PARTNO (r) register accessor: an alias for `Reg`"] +pub type PARTNO = crate::Reg; +#[doc = "SIP part number"] +pub mod partno; +#[doc = "HWREVISION (r) register accessor: an alias for `Reg`"] +pub type HWREVISION = crate::Reg; +#[doc = "Description collection: SIP hardware revision, encoded in ASCII, ex B0A or B1A"] +pub mod hwrevision; +#[doc = "VARIANT (r) register accessor: an alias for `Reg`"] +pub type VARIANT = crate::Reg; +#[doc = "Description collection: SIP VARIANT, encoded in ASCII, ex SIAA, SIBA or SICA"] +pub mod variant; diff --git a/pacs/nrf9120-pac/src/ficr_s/sipinfo/hwrevision.rs b/pacs/nrf9120-pac/src/ficr_s/sipinfo/hwrevision.rs new file mode 100644 index 00000000..549c268d --- /dev/null +++ b/pacs/nrf9120-pac/src/ficr_s/sipinfo/hwrevision.rs @@ -0,0 +1,41 @@ +#[doc = "Register `HWREVISION[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `HWREVISION` reader - "] +pub type HWREVISION_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:7"] + #[inline(always)] + pub fn hwrevision(&self) -> HWREVISION_R { + HWREVISION_R::new(self.bits) + } +} +#[doc = "Description collection: SIP hardware revision, encoded in ASCII, ex B0A or B1A\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hwrevision](index.html) module"] +pub struct HWREVISION_SPEC; +impl crate::RegisterSpec for HWREVISION_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [hwrevision::R](R) reader structure"] +impl crate::Readable for HWREVISION_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets HWREVISION[%s] +to value 0xff"] +impl crate::Resettable for HWREVISION_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0xff + } +} diff --git a/pacs/nrf9120-pac/src/ficr_s/sipinfo/partno.rs b/pacs/nrf9120-pac/src/ficr_s/sipinfo/partno.rs new file mode 100644 index 00000000..e67338a3 --- /dev/null +++ b/pacs/nrf9120-pac/src/ficr_s/sipinfo/partno.rs @@ -0,0 +1,68 @@ +#[doc = "Register `PARTNO` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `PARTNO` reader - "] +pub type PARTNO_R = crate::FieldReader; +#[doc = "\n\nValue on reset: 4294967295"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u32)] +pub enum PARTNO_A { + #[doc = "37216: Device is an nRF9160 sip"] + _9160 = 37216, +} +impl From for u32 { + #[inline(always)] + fn from(variant: PARTNO_A) -> Self { + variant as _ + } +} +impl PARTNO_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 37216 => Some(PARTNO_A::_9160), + _ => None, + } + } + #[doc = "Checks if the value of the field is `_9160`"] + #[inline(always)] + pub fn is_9160(&self) -> bool { + *self == PARTNO_A::_9160 + } +} +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn partno(&self) -> PARTNO_R { + PARTNO_R::new(self.bits) + } +} +#[doc = "SIP part number\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [partno](index.html) module"] +pub struct PARTNO_SPEC; +impl crate::RegisterSpec for PARTNO_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [partno::R](R) reader structure"] +impl crate::Readable for PARTNO_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PARTNO to value 0xffff_ffff"] +impl crate::Resettable for PARTNO_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0xffff_ffff + } +} diff --git a/pacs/nrf9120-pac/src/ficr_s/sipinfo/variant.rs b/pacs/nrf9120-pac/src/ficr_s/sipinfo/variant.rs new file mode 100644 index 00000000..dac8cd56 --- /dev/null +++ b/pacs/nrf9120-pac/src/ficr_s/sipinfo/variant.rs @@ -0,0 +1,41 @@ +#[doc = "Register `VARIANT[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `VARIANT` reader - "] +pub type VARIANT_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:7"] + #[inline(always)] + pub fn variant(&self) -> VARIANT_R { + VARIANT_R::new(self.bits) + } +} +#[doc = "Description collection: SIP VARIANT, encoded in ASCII, ex SIAA, SIBA or SICA\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [variant](index.html) module"] +pub struct VARIANT_SPEC; +impl crate::RegisterSpec for VARIANT_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [variant::R](R) reader structure"] +impl crate::Readable for VARIANT_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets VARIANT[%s] +to value 0xff"] +impl crate::Resettable for VARIANT_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0xff + } +} diff --git a/pacs/nrf9120-pac/src/ficr_s/trimcnf.rs b/pacs/nrf9120-pac/src/ficr_s/trimcnf.rs new file mode 100644 index 00000000..dd5e2fb4 --- /dev/null +++ b/pacs/nrf9120-pac/src/ficr_s/trimcnf.rs @@ -0,0 +1,16 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct TRIMCNF { + #[doc = "0x00 - Description cluster: Address"] + pub addr: ADDR, + #[doc = "0x04 - Description cluster: Data"] + pub data: DATA, +} +#[doc = "ADDR (r) register accessor: an alias for `Reg`"] +pub type ADDR = crate::Reg; +#[doc = "Description cluster: Address"] +pub mod addr; +#[doc = "DATA (r) register accessor: an alias for `Reg`"] +pub type DATA = crate::Reg; +#[doc = "Description cluster: Data"] +pub mod data; diff --git a/pacs/nrf9120-pac/src/ficr_s/trimcnf/addr.rs b/pacs/nrf9120-pac/src/ficr_s/trimcnf/addr.rs new file mode 100644 index 00000000..3c9b2c6b --- /dev/null +++ b/pacs/nrf9120-pac/src/ficr_s/trimcnf/addr.rs @@ -0,0 +1,40 @@ +#[doc = "Register `ADDR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `Address` reader - Address"] +pub type ADDRESS_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Address"] + #[inline(always)] + pub fn address(&self) -> ADDRESS_R { + ADDRESS_R::new(self.bits) + } +} +#[doc = "Description cluster: Address\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [addr](index.html) module"] +pub struct ADDR_SPEC; +impl crate::RegisterSpec for ADDR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [addr::R](R) reader structure"] +impl crate::Readable for ADDR_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets ADDR to value 0xffff_ffff"] +impl crate::Resettable for ADDR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0xffff_ffff + } +} diff --git a/pacs/nrf9120-pac/src/ficr_s/trimcnf/data.rs b/pacs/nrf9120-pac/src/ficr_s/trimcnf/data.rs new file mode 100644 index 00000000..1e75eaeb --- /dev/null +++ b/pacs/nrf9120-pac/src/ficr_s/trimcnf/data.rs @@ -0,0 +1,40 @@ +#[doc = "Register `DATA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `Data` reader - Data"] +pub type DATA_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Data"] + #[inline(always)] + pub fn data(&self) -> DATA_R { + DATA_R::new(self.bits) + } +} +#[doc = "Description cluster: Data\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [data](index.html) module"] +pub struct DATA_SPEC; +impl crate::RegisterSpec for DATA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [data::R](R) reader structure"] +impl crate::Readable for DATA_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets DATA to value 0xffff_ffff"] +impl crate::Resettable for DATA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0xffff_ffff + } +} diff --git a/pacs/nrf9120-pac/src/ficr_s/trng90b.rs b/pacs/nrf9120-pac/src/ficr_s/trng90b.rs new file mode 100644 index 00000000..105b07ef --- /dev/null +++ b/pacs/nrf9120-pac/src/ficr_s/trng90b.rs @@ -0,0 +1,52 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct TRNG90B { + #[doc = "0x00 - Amount of bytes for the required entropy bits"] + pub bytes: BYTES, + #[doc = "0x04 - Repetition counter cutoff"] + pub rccutoff: RCCUTOFF, + #[doc = "0x08 - Adaptive proportion cutoff"] + pub apcutoff: APCUTOFF, + #[doc = "0x0c - Amount of bytes for the startup tests"] + pub startup: STARTUP, + #[doc = "0x10 - Sample count for ring oscillator 1"] + pub rosc1: ROSC1, + #[doc = "0x14 - Sample count for ring oscillator 2"] + pub rosc2: ROSC2, + #[doc = "0x18 - Sample count for ring oscillator 3"] + pub rosc3: ROSC3, + #[doc = "0x1c - Sample count for ring oscillator 4"] + pub rosc4: ROSC4, +} +#[doc = "BYTES (r) register accessor: an alias for `Reg`"] +pub type BYTES = crate::Reg; +#[doc = "Amount of bytes for the required entropy bits"] +pub mod bytes; +#[doc = "RCCUTOFF (r) register accessor: an alias for `Reg`"] +pub type RCCUTOFF = crate::Reg; +#[doc = "Repetition counter cutoff"] +pub mod rccutoff; +#[doc = "APCUTOFF (r) register accessor: an alias for `Reg`"] +pub type APCUTOFF = crate::Reg; +#[doc = "Adaptive proportion cutoff"] +pub mod apcutoff; +#[doc = "STARTUP (r) register accessor: an alias for `Reg`"] +pub type STARTUP = crate::Reg; +#[doc = "Amount of bytes for the startup tests"] +pub mod startup; +#[doc = "ROSC1 (r) register accessor: an alias for `Reg`"] +pub type ROSC1 = crate::Reg; +#[doc = "Sample count for ring oscillator 1"] +pub mod rosc1; +#[doc = "ROSC2 (r) register accessor: an alias for `Reg`"] +pub type ROSC2 = crate::Reg; +#[doc = "Sample count for ring oscillator 2"] +pub mod rosc2; +#[doc = "ROSC3 (r) register accessor: an alias for `Reg`"] +pub type ROSC3 = crate::Reg; +#[doc = "Sample count for ring oscillator 3"] +pub mod rosc3; +#[doc = "ROSC4 (r) register accessor: an alias for `Reg`"] +pub type ROSC4 = crate::Reg; +#[doc = "Sample count for ring oscillator 4"] +pub mod rosc4; diff --git a/pacs/nrf9120-pac/src/ficr_s/trng90b/apcutoff.rs b/pacs/nrf9120-pac/src/ficr_s/trng90b/apcutoff.rs new file mode 100644 index 00000000..f231b82d --- /dev/null +++ b/pacs/nrf9120-pac/src/ficr_s/trng90b/apcutoff.rs @@ -0,0 +1,40 @@ +#[doc = "Register `APCUTOFF` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `APCUTOFF` reader - Adaptive proportion cutoff"] +pub type APCUTOFF_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Adaptive proportion cutoff"] + #[inline(always)] + pub fn apcutoff(&self) -> APCUTOFF_R { + APCUTOFF_R::new(self.bits) + } +} +#[doc = "Adaptive proportion cutoff\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [apcutoff](index.html) module"] +pub struct APCUTOFF_SPEC; +impl crate::RegisterSpec for APCUTOFF_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [apcutoff::R](R) reader structure"] +impl crate::Readable for APCUTOFF_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets APCUTOFF to value 0xffff_ffff"] +impl crate::Resettable for APCUTOFF_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0xffff_ffff + } +} diff --git a/pacs/nrf9120-pac/src/ficr_s/trng90b/bytes.rs b/pacs/nrf9120-pac/src/ficr_s/trng90b/bytes.rs new file mode 100644 index 00000000..1e09d51c --- /dev/null +++ b/pacs/nrf9120-pac/src/ficr_s/trng90b/bytes.rs @@ -0,0 +1,40 @@ +#[doc = "Register `BYTES` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `BYTES` reader - Amount of bytes for the required entropy bits"] +pub type BYTES_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Amount of bytes for the required entropy bits"] + #[inline(always)] + pub fn bytes(&self) -> BYTES_R { + BYTES_R::new(self.bits) + } +} +#[doc = "Amount of bytes for the required entropy bits\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [bytes](index.html) module"] +pub struct BYTES_SPEC; +impl crate::RegisterSpec for BYTES_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [bytes::R](R) reader structure"] +impl crate::Readable for BYTES_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets BYTES to value 0xffff_ffff"] +impl crate::Resettable for BYTES_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0xffff_ffff + } +} diff --git a/pacs/nrf9120-pac/src/ficr_s/trng90b/rccutoff.rs b/pacs/nrf9120-pac/src/ficr_s/trng90b/rccutoff.rs new file mode 100644 index 00000000..43269110 --- /dev/null +++ b/pacs/nrf9120-pac/src/ficr_s/trng90b/rccutoff.rs @@ -0,0 +1,40 @@ +#[doc = "Register `RCCUTOFF` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `RCCUTOFF` reader - Repetition counter cutoff"] +pub type RCCUTOFF_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Repetition counter cutoff"] + #[inline(always)] + pub fn rccutoff(&self) -> RCCUTOFF_R { + RCCUTOFF_R::new(self.bits) + } +} +#[doc = "Repetition counter cutoff\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rccutoff](index.html) module"] +pub struct RCCUTOFF_SPEC; +impl crate::RegisterSpec for RCCUTOFF_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [rccutoff::R](R) reader structure"] +impl crate::Readable for RCCUTOFF_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets RCCUTOFF to value 0xffff_ffff"] +impl crate::Resettable for RCCUTOFF_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0xffff_ffff + } +} diff --git a/pacs/nrf9120-pac/src/ficr_s/trng90b/rosc1.rs b/pacs/nrf9120-pac/src/ficr_s/trng90b/rosc1.rs new file mode 100644 index 00000000..129e79dd --- /dev/null +++ b/pacs/nrf9120-pac/src/ficr_s/trng90b/rosc1.rs @@ -0,0 +1,40 @@ +#[doc = "Register `ROSC1` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `ROSC1` reader - Sample count for ring oscillator 1"] +pub type ROSC1_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Sample count for ring oscillator 1"] + #[inline(always)] + pub fn rosc1(&self) -> ROSC1_R { + ROSC1_R::new(self.bits) + } +} +#[doc = "Sample count for ring oscillator 1\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rosc1](index.html) module"] +pub struct ROSC1_SPEC; +impl crate::RegisterSpec for ROSC1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [rosc1::R](R) reader structure"] +impl crate::Readable for ROSC1_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets ROSC1 to value 0xffff_ffff"] +impl crate::Resettable for ROSC1_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0xffff_ffff + } +} diff --git a/pacs/nrf9120-pac/src/ficr_s/trng90b/rosc2.rs b/pacs/nrf9120-pac/src/ficr_s/trng90b/rosc2.rs new file mode 100644 index 00000000..339ff07e --- /dev/null +++ b/pacs/nrf9120-pac/src/ficr_s/trng90b/rosc2.rs @@ -0,0 +1,40 @@ +#[doc = "Register `ROSC2` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `ROSC2` reader - Sample count for ring oscillator 2"] +pub type ROSC2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Sample count for ring oscillator 2"] + #[inline(always)] + pub fn rosc2(&self) -> ROSC2_R { + ROSC2_R::new(self.bits) + } +} +#[doc = "Sample count for ring oscillator 2\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rosc2](index.html) module"] +pub struct ROSC2_SPEC; +impl crate::RegisterSpec for ROSC2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [rosc2::R](R) reader structure"] +impl crate::Readable for ROSC2_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets ROSC2 to value 0xffff_ffff"] +impl crate::Resettable for ROSC2_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0xffff_ffff + } +} diff --git a/pacs/nrf9120-pac/src/ficr_s/trng90b/rosc3.rs b/pacs/nrf9120-pac/src/ficr_s/trng90b/rosc3.rs new file mode 100644 index 00000000..d4a5f091 --- /dev/null +++ b/pacs/nrf9120-pac/src/ficr_s/trng90b/rosc3.rs @@ -0,0 +1,40 @@ +#[doc = "Register `ROSC3` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `ROSC3` reader - Sample count for ring oscillator 3"] +pub type ROSC3_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Sample count for ring oscillator 3"] + #[inline(always)] + pub fn rosc3(&self) -> ROSC3_R { + ROSC3_R::new(self.bits) + } +} +#[doc = "Sample count for ring oscillator 3\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rosc3](index.html) module"] +pub struct ROSC3_SPEC; +impl crate::RegisterSpec for ROSC3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [rosc3::R](R) reader structure"] +impl crate::Readable for ROSC3_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets ROSC3 to value 0xffff_ffff"] +impl crate::Resettable for ROSC3_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0xffff_ffff + } +} diff --git a/pacs/nrf9120-pac/src/ficr_s/trng90b/rosc4.rs b/pacs/nrf9120-pac/src/ficr_s/trng90b/rosc4.rs new file mode 100644 index 00000000..4749176a --- /dev/null +++ b/pacs/nrf9120-pac/src/ficr_s/trng90b/rosc4.rs @@ -0,0 +1,40 @@ +#[doc = "Register `ROSC4` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `ROSC4` reader - Sample count for ring oscillator 4"] +pub type ROSC4_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Sample count for ring oscillator 4"] + #[inline(always)] + pub fn rosc4(&self) -> ROSC4_R { + ROSC4_R::new(self.bits) + } +} +#[doc = "Sample count for ring oscillator 4\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rosc4](index.html) module"] +pub struct ROSC4_SPEC; +impl crate::RegisterSpec for ROSC4_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [rosc4::R](R) reader structure"] +impl crate::Readable for ROSC4_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets ROSC4 to value 0xffff_ffff"] +impl crate::Resettable for ROSC4_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0xffff_ffff + } +} diff --git a/pacs/nrf9120-pac/src/ficr_s/trng90b/startup.rs b/pacs/nrf9120-pac/src/ficr_s/trng90b/startup.rs new file mode 100644 index 00000000..f45f184e --- /dev/null +++ b/pacs/nrf9120-pac/src/ficr_s/trng90b/startup.rs @@ -0,0 +1,40 @@ +#[doc = "Register `STARTUP` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `STARTUP` reader - Amount of bytes for the startup tests"] +pub type STARTUP_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Amount of bytes for the startup tests"] + #[inline(always)] + pub fn startup(&self) -> STARTUP_R { + STARTUP_R::new(self.bits) + } +} +#[doc = "Amount of bytes for the startup tests\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [startup](index.html) module"] +pub struct STARTUP_SPEC; +impl crate::RegisterSpec for STARTUP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [startup::R](R) reader structure"] +impl crate::Readable for STARTUP_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets STARTUP to value 0xffff_ffff"] +impl crate::Resettable for STARTUP_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0xffff_ffff + } +} diff --git a/pacs/nrf9120-pac/src/fpu_ns.rs b/pacs/nrf9120-pac/src/fpu_ns.rs new file mode 100644 index 00000000..ad42ba64 --- /dev/null +++ b/pacs/nrf9120-pac/src/fpu_ns.rs @@ -0,0 +1,10 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Unused."] + pub unused: UNUSED, +} +#[doc = "UNUSED (r) register accessor: an alias for `Reg`"] +pub type UNUSED = crate::Reg; +#[doc = "Unused."] +pub mod unused; diff --git a/pacs/nrf9120-pac/src/fpu_ns/unused.rs b/pacs/nrf9120-pac/src/fpu_ns/unused.rs new file mode 100644 index 00000000..fe6dc9fa --- /dev/null +++ b/pacs/nrf9120-pac/src/fpu_ns/unused.rs @@ -0,0 +1,31 @@ +#[doc = "Register `UNUSED` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Unused.\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [unused](index.html) module"] +pub struct UNUSED_SPEC; +impl crate::RegisterSpec for UNUSED_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [unused::R](R) reader structure"] +impl crate::Readable for UNUSED_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets UNUSED to value 0"] +impl crate::Resettable for UNUSED_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/generic.rs b/pacs/nrf9120-pac/src/generic.rs new file mode 100644 index 00000000..be0600c9 --- /dev/null +++ b/pacs/nrf9120-pac/src/generic.rs @@ -0,0 +1,574 @@ +use core::marker; +#[doc = " Raw register type"] +pub trait RegisterSpec { + #[doc = " Raw register type (`u8`, `u16`, `u32`, ...)."] + type Ux: Copy; +} +#[doc = " Trait implemented by readable registers to enable the `read` method."] +#[doc = ""] +#[doc = " Registers marked with `Writable` can be also `modify`'ed."] +pub trait Readable: RegisterSpec { + #[doc = " Result from a call to `read` and argument to `modify`."] + type Reader: From> + core::ops::Deref>; +} +#[doc = " Trait implemented by writeable registers."] +#[doc = ""] +#[doc = " This enables the `write`, `write_with_zero` and `reset` methods."] +#[doc = ""] +#[doc = " Registers marked with `Readable` can be also `modify`'ed."] +pub trait Writable: RegisterSpec { + #[doc = " Writer type argument to `write`, et al."] + type Writer: From> + core::ops::DerefMut>; +} +#[doc = " Reset value of the register."] +#[doc = ""] +#[doc = " This value is the initial value for the `write` method. It can also be directly written to the"] +#[doc = " register by using the `reset` method."] +pub trait Resettable: RegisterSpec { + #[doc = " Reset value of the register."] + fn reset_value() -> Self::Ux; +} +#[doc = " This structure provides volatile access to registers."] +#[repr(transparent)] +pub struct Reg { + register: vcell::VolatileCell, + _marker: marker::PhantomData, +} +unsafe impl Send for Reg where REG::Ux: Send {} +impl Reg { + #[doc = " Returns the underlying memory address of register."] + #[doc = ""] + #[doc = " ```ignore"] + #[doc = " let reg_ptr = periph.reg.as_ptr();"] + #[doc = " ```"] + #[inline(always)] + pub fn as_ptr(&self) -> *mut REG::Ux { + self.register.as_ptr() + } +} +impl Reg { + #[doc = " Reads the contents of a `Readable` register."] + #[doc = ""] + #[doc = " You can read the raw contents of a register by using `bits`:"] + #[doc = " ```ignore"] + #[doc = " let bits = periph.reg.read().bits();"] + #[doc = " ```"] + #[doc = " or get the content of a particular field of a register:"] + #[doc = " ```ignore"] + #[doc = " let reader = periph.reg.read();"] + #[doc = " let bits = reader.field1().bits();"] + #[doc = " let flag = reader.field2().bit_is_set();"] + #[doc = " ```"] + #[inline(always)] + pub fn read(&self) -> REG::Reader { + REG::Reader::from(R { + bits: self.register.get(), + _reg: marker::PhantomData, + }) + } +} +impl Reg { + #[doc = " Writes the reset value to `Writable` register."] + #[doc = ""] + #[doc = " Resets the register to its initial state."] + #[inline(always)] + pub fn reset(&self) { + self.register.set(REG::reset_value()) + } + #[doc = " Writes bits to a `Writable` register."] + #[doc = ""] + #[doc = " You can write raw bits into a register:"] + #[doc = " ```ignore"] + #[doc = " periph.reg.write(|w| unsafe { w.bits(rawbits) });"] + #[doc = " ```"] + #[doc = " or write only the fields you need:"] + #[doc = " ```ignore"] + #[doc = " periph.reg.write(|w| w"] + #[doc = " .field1().bits(newfield1bits)"] + #[doc = " .field2().set_bit()"] + #[doc = " .field3().variant(VARIANT)"] + #[doc = " );"] + #[doc = " ```"] + #[doc = " or an alternative way of saying the same:"] + #[doc = " ```ignore"] + #[doc = " periph.reg.write(|w| {"] + #[doc = " w.field1().bits(newfield1bits);"] + #[doc = " w.field2().set_bit();"] + #[doc = " w.field3().variant(VARIANT)"] + #[doc = " });"] + #[doc = " ```"] + #[doc = " In the latter case, other fields will be set to their reset value."] + #[inline(always)] + pub fn write(&self, f: F) + where + F: FnOnce(&mut REG::Writer) -> &mut W, + { + self.register.set( + f(&mut REG::Writer::from(W { + bits: REG::reset_value(), + _reg: marker::PhantomData, + })) + .bits, + ); + } +} +impl Reg +where + REG::Ux: Default, +{ + #[doc = " Writes 0 to a `Writable` register."] + #[doc = ""] + #[doc = " Similar to `write`, but unused bits will contain 0."] + #[inline(always)] + pub unsafe fn write_with_zero(&self, f: F) + where + F: FnOnce(&mut REG::Writer) -> &mut W, + { + self.register.set( + (*f(&mut REG::Writer::from(W { + bits: REG::Ux::default(), + _reg: marker::PhantomData, + }))) + .bits, + ); + } +} +impl Reg { + #[doc = " Modifies the contents of the register by reading and then writing it."] + #[doc = ""] + #[doc = " E.g. to do a read-modify-write sequence to change parts of a register:"] + #[doc = " ```ignore"] + #[doc = " periph.reg.modify(|r, w| unsafe { w.bits("] + #[doc = " r.bits() | 3"] + #[doc = " ) });"] + #[doc = " ```"] + #[doc = " or"] + #[doc = " ```ignore"] + #[doc = " periph.reg.modify(|_, w| w"] + #[doc = " .field1().bits(newfield1bits)"] + #[doc = " .field2().set_bit()"] + #[doc = " .field3().variant(VARIANT)"] + #[doc = " );"] + #[doc = " ```"] + #[doc = " or an alternative way of saying the same:"] + #[doc = " ```ignore"] + #[doc = " periph.reg.modify(|_, w| {"] + #[doc = " w.field1().bits(newfield1bits);"] + #[doc = " w.field2().set_bit();"] + #[doc = " w.field3().variant(VARIANT)"] + #[doc = " });"] + #[doc = " ```"] + #[doc = " Other fields will have the value they had before the call to `modify`."] + #[inline(always)] + pub fn modify(&self, f: F) + where + for<'w> F: FnOnce(®::Reader, &'w mut REG::Writer) -> &'w mut W, + { + let bits = self.register.get(); + self.register.set( + f( + ®::Reader::from(R { + bits, + _reg: marker::PhantomData, + }), + &mut REG::Writer::from(W { + bits, + _reg: marker::PhantomData, + }), + ) + .bits, + ); + } +} +#[doc = " Register reader."] +#[doc = ""] +#[doc = " Result of the `read` methods of registers. Also used as a closure argument in the `modify`"] +#[doc = " method."] +pub struct R { + pub(crate) bits: REG::Ux, + _reg: marker::PhantomData, +} +impl R { + #[doc = " Reads raw bits from register."] + #[inline(always)] + pub fn bits(&self) -> REG::Ux { + self.bits + } +} +impl PartialEq for R +where + REG::Ux: PartialEq, + FI: Copy + Into, +{ + #[inline(always)] + fn eq(&self, other: &FI) -> bool { + self.bits.eq(&(*other).into()) + } +} +#[doc = " Register writer."] +#[doc = ""] +#[doc = " Used as an argument to the closures in the `write` and `modify` methods of the register."] +pub struct W { + #[doc = "Writable bits"] + pub(crate) bits: REG::Ux, + _reg: marker::PhantomData, +} +impl W { + #[doc = " Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: REG::Ux) -> &mut Self { + self.bits = bits; + self + } +} +#[doc(hidden)] +pub struct FieldReaderRaw { + pub(crate) bits: U, + _reg: marker::PhantomData, +} +impl FieldReaderRaw +where + U: Copy, +{ + #[doc = " Creates a new instance of the reader."] + #[allow(unused)] + #[inline(always)] + pub(crate) fn new(bits: U) -> Self { + Self { + bits, + _reg: marker::PhantomData, + } + } +} +#[doc(hidden)] +pub struct BitReaderRaw { + pub(crate) bits: bool, + _reg: marker::PhantomData, +} +impl BitReaderRaw { + #[doc = " Creates a new instance of the reader."] + #[allow(unused)] + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + Self { + bits, + _reg: marker::PhantomData, + } + } +} +#[doc = " Field reader."] +#[doc = ""] +#[doc = " Result of the `read` methods of fields."] +pub type FieldReader = FieldReaderRaw; +#[doc = " Bit-wise field reader"] +pub type BitReader = BitReaderRaw; +impl FieldReader +where + U: Copy, +{ + #[doc = " Reads raw bits from field."] + #[inline(always)] + pub fn bits(&self) -> U { + self.bits + } +} +impl PartialEq for FieldReader +where + U: PartialEq, + FI: Copy + Into, +{ + #[inline(always)] + fn eq(&self, other: &FI) -> bool { + self.bits.eq(&(*other).into()) + } +} +impl PartialEq for BitReader +where + FI: Copy + Into, +{ + #[inline(always)] + fn eq(&self, other: &FI) -> bool { + self.bits.eq(&(*other).into()) + } +} +impl BitReader { + #[doc = " Value of the field as raw bits."] + #[inline(always)] + pub fn bit(&self) -> bool { + self.bits + } + #[doc = " Returns `true` if the bit is clear (0)."] + #[inline(always)] + pub fn bit_is_clear(&self) -> bool { + !self.bit() + } + #[doc = " Returns `true` if the bit is set (1)."] + #[inline(always)] + pub fn bit_is_set(&self) -> bool { + self.bit() + } +} +#[doc(hidden)] +pub struct Safe; +#[doc(hidden)] +pub struct Unsafe; +#[doc(hidden)] +pub struct FieldWriterRaw<'a, U, REG, N, FI, Safety, const WI: u8, const O: u8> +where + REG: Writable + RegisterSpec, + FI: Into, +{ + pub(crate) w: &'a mut REG::Writer, + _field: marker::PhantomData<(N, FI, Safety)>, +} +impl<'a, U, REG, N, FI, Safety, const WI: u8, const O: u8> + FieldWriterRaw<'a, U, REG, N, FI, Safety, WI, O> +where + REG: Writable + RegisterSpec, + FI: Into, +{ + #[doc = " Creates a new instance of the writer"] + #[allow(unused)] + #[inline(always)] + pub(crate) fn new(w: &'a mut REG::Writer) -> Self { + Self { + w, + _field: marker::PhantomData, + } + } +} +#[doc(hidden)] +pub struct BitWriterRaw<'a, U, REG, FI, M, const O: u8> +where + REG: Writable + RegisterSpec, + FI: Into, +{ + pub(crate) w: &'a mut REG::Writer, + _field: marker::PhantomData<(FI, M)>, +} +impl<'a, U, REG, FI, M, const O: u8> BitWriterRaw<'a, U, REG, FI, M, O> +where + REG: Writable + RegisterSpec, + FI: Into, +{ + #[doc = " Creates a new instance of the writer"] + #[allow(unused)] + #[inline(always)] + pub(crate) fn new(w: &'a mut REG::Writer) -> Self { + Self { + w, + _field: marker::PhantomData, + } + } +} +#[doc = " Write field Proxy with unsafe `bits`"] +pub type FieldWriter<'a, U, REG, N, FI, const WI: u8, const O: u8> = + FieldWriterRaw<'a, U, REG, N, FI, Unsafe, WI, O>; +#[doc = " Write field Proxy with safe `bits`"] +pub type FieldWriterSafe<'a, U, REG, N, FI, const WI: u8, const O: u8> = + FieldWriterRaw<'a, U, REG, N, FI, Safe, WI, O>; +impl<'a, U, REG, N, FI, const WI: u8, const OF: u8> FieldWriter<'a, U, REG, N, FI, WI, OF> +where + REG: Writable + RegisterSpec, + FI: Into, +{ + #[doc = " Field width"] + pub const WIDTH: u8 = WI; + #[doc = " Field offset"] + pub const OFFSET: u8 = OF; +} +impl<'a, U, REG, N, FI, const WI: u8, const OF: u8> FieldWriterSafe<'a, U, REG, N, FI, WI, OF> +where + REG: Writable + RegisterSpec, + FI: Into, +{ + #[doc = " Field width"] + pub const WIDTH: u8 = WI; + #[doc = " Field offset"] + pub const OFFSET: u8 = OF; +} +macro_rules! bit_proxy { + ($ writer : ident , $ mwv : ident) => { + #[doc(hidden)] + pub struct $mwv; + #[doc = " Bit-wise write field proxy"] + pub type $writer<'a, U, REG, FI, const O: u8> = BitWriterRaw<'a, U, REG, FI, $mwv, O>; + impl<'a, U, REG, FI, const OF: u8> $writer<'a, U, REG, FI, OF> + where + REG: Writable + RegisterSpec, + FI: Into, + { + #[doc = " Field width"] + pub const WIDTH: u8 = 1; + #[doc = " Field offset"] + pub const OFFSET: u8 = OF; + } + }; +} +macro_rules! impl_bit_proxy { + ($ writer : ident , $ U : ty) => { + impl<'a, REG, FI, const OF: u8> $writer<'a, $U, REG, FI, OF> + where + REG: Writable + RegisterSpec, + FI: Into, + { + #[doc = " Writes bit to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut REG::Writer { + self.w.bits = (self.w.bits & !(1 << { OF })) | ((<$U>::from(value) & 1) << { OF }); + self.w + } + #[doc = " Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: FI) -> &'a mut REG::Writer { + self.bit(variant.into()) + } + } + }; +} +bit_proxy!(BitWriter, BitM); +bit_proxy!(BitWriter1S, Bit1S); +bit_proxy!(BitWriter0C, Bit0C); +bit_proxy!(BitWriter1C, Bit1C); +bit_proxy!(BitWriter0S, Bit0S); +bit_proxy!(BitWriter1T, Bit1T); +bit_proxy!(BitWriter0T, Bit0T); +macro_rules! impl_proxy { + ($ U : ty) => { + impl<'a, REG, N, FI, const WI: u8, const OF: u8> FieldWriter<'a, $U, REG, N, FI, WI, OF> + where + REG: Writable + RegisterSpec, + N: Into<$U>, + FI: Into, + { + const MASK: $U = <$U>::MAX >> (<$U>::MAX.leading_ones() as u8 - { WI }); + #[doc = " Writes raw bits to the field"] + #[doc = ""] + #[doc = " # Safety"] + #[doc = ""] + #[doc = " Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(self, value: N) -> &'a mut REG::Writer { + self.w.bits = (self.w.bits & !(Self::MASK << { OF })) + | ((value.into() & Self::MASK) << { OF }); + self.w + } + #[doc = " Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: FI) -> &'a mut REG::Writer { + unsafe { self.bits(variant.into()) } + } + } + impl<'a, REG, N, FI, const WI: u8, const OF: u8> FieldWriterSafe<'a, $U, REG, N, FI, WI, OF> + where + REG: Writable + RegisterSpec, + N: Into<$U>, + FI: Into, + { + const MASK: $U = <$U>::MAX >> (<$U>::MAX.leading_ones() as u8 - { WI }); + #[doc = " Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: N) -> &'a mut REG::Writer { + self.w.bits = (self.w.bits & !(Self::MASK << { OF })) + | ((value.into() & Self::MASK) << { OF }); + self.w + } + #[doc = " Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: FI) -> &'a mut REG::Writer { + self.bits(variant.into()) + } + } + impl_bit_proxy!(BitWriter, $U); + impl_bit_proxy!(BitWriter1S, $U); + impl_bit_proxy!(BitWriter0C, $U); + impl_bit_proxy!(BitWriter1C, $U); + impl_bit_proxy!(BitWriter0S, $U); + impl_bit_proxy!(BitWriter1T, $U); + impl_bit_proxy!(BitWriter0T, $U); + impl<'a, REG, FI, const OF: u8> BitWriter<'a, $U, REG, FI, OF> + where + REG: Writable + RegisterSpec, + FI: Into, + { + #[doc = " Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut REG::Writer { + self.bit(true) + } + #[doc = " Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut REG::Writer { + self.bit(false) + } + } + impl<'a, REG, FI, const OF: u8> BitWriter1S<'a, $U, REG, FI, OF> + where + REG: Writable + RegisterSpec, + FI: Into, + { + #[doc = " Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut REG::Writer { + self.bit(true) + } + } + impl<'a, REG, FI, const OF: u8> BitWriter0C<'a, $U, REG, FI, OF> + where + REG: Writable + RegisterSpec, + FI: Into, + { + #[doc = " Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut REG::Writer { + self.bit(false) + } + } + impl<'a, REG, FI, const OF: u8> BitWriter1C<'a, $U, REG, FI, OF> + where + REG: Writable + RegisterSpec, + FI: Into, + { + #[doc = "Clears the field bit by passing one"] + #[inline(always)] + pub fn clear_bit_by_one(self) -> &'a mut REG::Writer { + self.bit(true) + } + } + impl<'a, REG, FI, const OF: u8> BitWriter0S<'a, $U, REG, FI, OF> + where + REG: Writable + RegisterSpec, + FI: Into, + { + #[doc = "Sets the field bit by passing zero"] + #[inline(always)] + pub fn set_bit_by_zero(self) -> &'a mut REG::Writer { + self.bit(false) + } + } + impl<'a, REG, FI, const OF: u8> BitWriter1T<'a, $U, REG, FI, OF> + where + REG: Writable + RegisterSpec, + FI: Into, + { + #[doc = "Toggle the field bit by passing one"] + #[inline(always)] + pub fn toggle_bit(self) -> &'a mut REG::Writer { + self.bit(true) + } + } + impl<'a, REG, FI, const OF: u8> BitWriter0T<'a, $U, REG, FI, OF> + where + REG: Writable + RegisterSpec, + FI: Into, + { + #[doc = "Toggle the field bit by passing zero"] + #[inline(always)] + pub fn toggle_bit(self) -> &'a mut REG::Writer { + self.bit(false) + } + } + }; +} +impl_proxy!(u8); +impl_proxy!(u32); diff --git a/pacs/nrf9120-pac/src/generic/raw.rs b/pacs/nrf9120-pac/src/generic/raw.rs new file mode 100644 index 00000000..81f57795 --- /dev/null +++ b/pacs/nrf9120-pac/src/generic/raw.rs @@ -0,0 +1,93 @@ +use super::{marker, BitM, FieldSpec, RegisterSpec, Unsafe, Writable}; +pub struct R { + pub(crate) bits: REG::Ux, + pub(super) _reg: marker::PhantomData, +} +pub struct W { + #[doc = "Writable bits"] + pub(crate) bits: REG::Ux, + pub(super) _reg: marker::PhantomData, +} +pub struct FieldReader +where + FI: FieldSpec, +{ + pub(crate) bits: FI::Ux, + _reg: marker::PhantomData, +} +impl FieldReader { + #[doc = " Creates a new instance of the reader."] + #[allow(unused)] + #[inline(always)] + pub(crate) const fn new(bits: FI::Ux) -> Self { + Self { + bits, + _reg: marker::PhantomData, + } + } +} +pub struct BitReader { + pub(crate) bits: bool, + _reg: marker::PhantomData, +} +impl BitReader { + #[doc = " Creates a new instance of the reader."] + #[allow(unused)] + #[inline(always)] + pub(crate) const fn new(bits: bool) -> Self { + Self { + bits, + _reg: marker::PhantomData, + } + } +} +pub struct FieldWriter<'a, REG, const WI: u8, FI = u8, Safety = Unsafe> +where + REG: Writable + RegisterSpec, + FI: FieldSpec, +{ + pub(crate) w: &'a mut W, + pub(crate) o: u8, + _field: marker::PhantomData<(FI, Safety)>, +} +impl<'a, REG, const WI: u8, FI, Safety> FieldWriter<'a, REG, WI, FI, Safety> +where + REG: Writable + RegisterSpec, + FI: FieldSpec, +{ + #[doc = " Creates a new instance of the writer"] + #[allow(unused)] + #[inline(always)] + pub(crate) fn new(w: &'a mut W, o: u8) -> Self { + Self { + w, + o, + _field: marker::PhantomData, + } + } +} +pub struct BitWriter<'a, REG, FI = bool, M = BitM> +where + REG: Writable + RegisterSpec, + bool: From, +{ + pub(crate) w: &'a mut W, + pub(crate) o: u8, + _field: marker::PhantomData<(FI, M)>, +} +impl<'a, REG, FI, M> BitWriter<'a, REG, FI, M> +where + REG: Writable + RegisterSpec, + bool: From, +{ + #[doc = " Creates a new instance of the writer"] + #[allow(unused)] + #[inline(always)] + pub(crate) fn new(w: &'a mut W, o: u8) -> Self { + Self { + w, + o, + _field: marker::PhantomData, + } + } +} diff --git a/pacs/nrf9120-pac/src/gpiote0_s.rs b/pacs/nrf9120-pac/src/gpiote0_s.rs new file mode 100644 index 00000000..dd2c7a44 --- /dev/null +++ b/pacs/nrf9120-pac/src/gpiote0_s.rs @@ -0,0 +1,94 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00..0x20 - Description collection: Task for writing to pin specified in CONFIG\\[n\\].PSEL. Action on pin is configured in CONFIG\\[n\\].POLARITY."] + pub tasks_out: [TASKS_OUT; 8], + _reserved1: [u8; 0x10], + #[doc = "0x30..0x50 - Description collection: Task for writing to pin specified in CONFIG\\[n\\].PSEL. Action on pin is to set it high."] + pub tasks_set: [TASKS_SET; 8], + _reserved2: [u8; 0x10], + #[doc = "0x60..0x80 - Description collection: Task for writing to pin specified in CONFIG\\[n\\].PSEL. Action on pin is to set it low."] + pub tasks_clr: [TASKS_CLR; 8], + #[doc = "0x80..0xa0 - Description collection: Subscribe configuration for task OUT\\[n\\]"] + pub subscribe_out: [SUBSCRIBE_OUT; 8], + _reserved4: [u8; 0x10], + #[doc = "0xb0..0xd0 - Description collection: Subscribe configuration for task SET\\[n\\]"] + pub subscribe_set: [SUBSCRIBE_SET; 8], + _reserved5: [u8; 0x10], + #[doc = "0xe0..0x100 - Description collection: Subscribe configuration for task CLR\\[n\\]"] + pub subscribe_clr: [SUBSCRIBE_CLR; 8], + #[doc = "0x100..0x120 - Description collection: Event generated from pin specified in CONFIG\\[n\\].PSEL"] + pub events_in: [EVENTS_IN; 8], + _reserved7: [u8; 0x5c], + #[doc = "0x17c - Event generated from multiple input GPIO pins with SENSE mechanism enabled"] + pub events_port: EVENTS_PORT, + #[doc = "0x180..0x1a0 - Description collection: Publish configuration for event IN\\[n\\]"] + pub publish_in: [PUBLISH_IN; 8], + _reserved9: [u8; 0x5c], + #[doc = "0x1fc - Publish configuration for event PORT"] + pub publish_port: PUBLISH_PORT, + _reserved10: [u8; 0x0104], + #[doc = "0x304 - Enable interrupt"] + pub intenset: INTENSET, + #[doc = "0x308 - Disable interrupt"] + pub intenclr: INTENCLR, + _reserved12: [u8; 0x0204], + #[doc = "0x510..0x530 - Description collection: Configuration for OUT\\[n\\], SET\\[n\\], and CLR\\[n\\] +tasks and IN\\[n\\] +event"] + pub config: [CONFIG; 8], +} +#[doc = "TASKS_OUT (w) register accessor: an alias for `Reg`"] +pub type TASKS_OUT = crate::Reg; +#[doc = "Description collection: Task for writing to pin specified in CONFIG\\[n\\].PSEL. Action on pin is configured in CONFIG\\[n\\].POLARITY."] +pub mod tasks_out; +#[doc = "TASKS_SET (w) register accessor: an alias for `Reg`"] +pub type TASKS_SET = crate::Reg; +#[doc = "Description collection: Task for writing to pin specified in CONFIG\\[n\\].PSEL. Action on pin is to set it high."] +pub mod tasks_set; +#[doc = "TASKS_CLR (w) register accessor: an alias for `Reg`"] +pub type TASKS_CLR = crate::Reg; +#[doc = "Description collection: Task for writing to pin specified in CONFIG\\[n\\].PSEL. Action on pin is to set it low."] +pub mod tasks_clr; +#[doc = "SUBSCRIBE_OUT (rw) register accessor: an alias for `Reg`"] +pub type SUBSCRIBE_OUT = crate::Reg; +#[doc = "Description collection: Subscribe configuration for task OUT\\[n\\]"] +pub mod subscribe_out; +#[doc = "SUBSCRIBE_SET (rw) register accessor: an alias for `Reg`"] +pub type SUBSCRIBE_SET = crate::Reg; +#[doc = "Description collection: Subscribe configuration for task SET\\[n\\]"] +pub mod subscribe_set; +#[doc = "SUBSCRIBE_CLR (rw) register accessor: an alias for `Reg`"] +pub type SUBSCRIBE_CLR = crate::Reg; +#[doc = "Description collection: Subscribe configuration for task CLR\\[n\\]"] +pub mod subscribe_clr; +#[doc = "EVENTS_IN (rw) register accessor: an alias for `Reg`"] +pub type EVENTS_IN = crate::Reg; +#[doc = "Description collection: Event generated from pin specified in CONFIG\\[n\\].PSEL"] +pub mod events_in; +#[doc = "EVENTS_PORT (rw) register accessor: an alias for `Reg`"] +pub type EVENTS_PORT = crate::Reg; +#[doc = "Event generated from multiple input GPIO pins with SENSE mechanism enabled"] +pub mod events_port; +#[doc = "PUBLISH_IN (rw) register accessor: an alias for `Reg`"] +pub type PUBLISH_IN = crate::Reg; +#[doc = "Description collection: Publish configuration for event IN\\[n\\]"] +pub mod publish_in; +#[doc = "PUBLISH_PORT (rw) register accessor: an alias for `Reg`"] +pub type PUBLISH_PORT = crate::Reg; +#[doc = "Publish configuration for event PORT"] +pub mod publish_port; +#[doc = "INTENSET (rw) register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "Enable interrupt"] +pub mod intenset; +#[doc = "INTENCLR (rw) register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "Disable interrupt"] +pub mod intenclr; +#[doc = "CONFIG (rw) register accessor: an alias for `Reg`"] +pub type CONFIG = crate::Reg; +#[doc = "Description collection: Configuration for OUT\\[n\\], SET\\[n\\], and CLR\\[n\\] +tasks and IN\\[n\\] +event"] +pub mod config; diff --git a/pacs/nrf9120-pac/src/gpiote0_s/config.rs b/pacs/nrf9120-pac/src/gpiote0_s/config.rs new file mode 100644 index 00000000..f26c8632 --- /dev/null +++ b/pacs/nrf9120-pac/src/gpiote0_s/config.rs @@ -0,0 +1,339 @@ +#[doc = "Register `CONFIG[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CONFIG[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `MODE` reader - Mode"] +pub type MODE_R = crate::FieldReader; +#[doc = "Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum MODE_A { + #[doc = "0: Disabled. Pin specified by PSEL will not be acquired by the GPIOTE module."] + DISABLED = 0, + #[doc = "1: Event mode"] + EVENT = 1, + #[doc = "3: Task mode"] + TASK = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: MODE_A) -> Self { + variant as _ + } +} +impl MODE_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(MODE_A::DISABLED), + 1 => Some(MODE_A::EVENT), + 3 => Some(MODE_A::TASK), + _ => None, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == MODE_A::DISABLED + } + #[doc = "Checks if the value of the field is `EVENT`"] + #[inline(always)] + pub fn is_event(&self) -> bool { + *self == MODE_A::EVENT + } + #[doc = "Checks if the value of the field is `TASK`"] + #[inline(always)] + pub fn is_task(&self) -> bool { + *self == MODE_A::TASK + } +} +#[doc = "Field `MODE` writer - Mode"] +pub type MODE_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CONFIG_SPEC, u8, MODE_A, 2, O>; +impl<'a, const O: u8> MODE_W<'a, O> { + #[doc = "Disabled. Pin specified by PSEL will not be acquired by the GPIOTE module."] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(MODE_A::DISABLED) + } + #[doc = "Event mode"] + #[inline(always)] + pub fn event(self) -> &'a mut W { + self.variant(MODE_A::EVENT) + } + #[doc = "Task mode"] + #[inline(always)] + pub fn task(self) -> &'a mut W { + self.variant(MODE_A::TASK) + } +} +#[doc = "Field `PSEL` reader - GPIO number associated with SET\\[n\\], CLR\\[n\\], and OUT\\[n\\] +tasks and IN\\[n\\] +event"] +pub type PSEL_R = crate::FieldReader; +#[doc = "Field `PSEL` writer - GPIO number associated with SET\\[n\\], CLR\\[n\\], and OUT\\[n\\] +tasks and IN\\[n\\] +event"] +pub type PSEL_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CONFIG_SPEC, u8, u8, 5, O>; +#[doc = "Field `POLARITY` reader - When In task mode: Operation to be performed on output when OUT\\[n\\] +task is triggered. When In event mode: Operation on input that shall trigger IN\\[n\\] +event."] +pub type POLARITY_R = crate::FieldReader; +#[doc = "When In task mode: Operation to be performed on output when OUT\\[n\\] +task is triggered. When In event mode: Operation on input that shall trigger IN\\[n\\] +event.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum POLARITY_A { + #[doc = "0: Task mode: No effect on pin from OUT\\[n\\] +task. Event mode: no IN\\[n\\] +event generated on pin activity."] + NONE = 0, + #[doc = "1: Task mode: Set pin from OUT\\[n\\] +task. Event mode: Generate IN\\[n\\] +event when rising edge on pin."] + LO_TO_HI = 1, + #[doc = "2: Task mode: Clear pin from OUT\\[n\\] +task. Event mode: Generate IN\\[n\\] +event when falling edge on pin."] + HI_TO_LO = 2, + #[doc = "3: Task mode: Toggle pin from OUT\\[n\\]. Event mode: Generate IN\\[n\\] +when any change on pin."] + TOGGLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: POLARITY_A) -> Self { + variant as _ + } +} +impl POLARITY_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> POLARITY_A { + match self.bits { + 0 => POLARITY_A::NONE, + 1 => POLARITY_A::LO_TO_HI, + 2 => POLARITY_A::HI_TO_LO, + 3 => POLARITY_A::TOGGLE, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + *self == POLARITY_A::NONE + } + #[doc = "Checks if the value of the field is `LO_TO_HI`"] + #[inline(always)] + pub fn is_lo_to_hi(&self) -> bool { + *self == POLARITY_A::LO_TO_HI + } + #[doc = "Checks if the value of the field is `HI_TO_LO`"] + #[inline(always)] + pub fn is_hi_to_lo(&self) -> bool { + *self == POLARITY_A::HI_TO_LO + } + #[doc = "Checks if the value of the field is `TOGGLE`"] + #[inline(always)] + pub fn is_toggle(&self) -> bool { + *self == POLARITY_A::TOGGLE + } +} +#[doc = "Field `POLARITY` writer - When In task mode: Operation to be performed on output when OUT\\[n\\] +task is triggered. When In event mode: Operation on input that shall trigger IN\\[n\\] +event."] +pub type POLARITY_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u32, CONFIG_SPEC, u8, POLARITY_A, 2, O>; +impl<'a, const O: u8> POLARITY_W<'a, O> { + #[doc = "Task mode: No effect on pin from OUT\\[n\\] +task. Event mode: no IN\\[n\\] +event generated on pin activity."] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(POLARITY_A::NONE) + } + #[doc = "Task mode: Set pin from OUT\\[n\\] +task. Event mode: Generate IN\\[n\\] +event when rising edge on pin."] + #[inline(always)] + pub fn lo_to_hi(self) -> &'a mut W { + self.variant(POLARITY_A::LO_TO_HI) + } + #[doc = "Task mode: Clear pin from OUT\\[n\\] +task. Event mode: Generate IN\\[n\\] +event when falling edge on pin."] + #[inline(always)] + pub fn hi_to_lo(self) -> &'a mut W { + self.variant(POLARITY_A::HI_TO_LO) + } + #[doc = "Task mode: Toggle pin from OUT\\[n\\]. Event mode: Generate IN\\[n\\] +when any change on pin."] + #[inline(always)] + pub fn toggle(self) -> &'a mut W { + self.variant(POLARITY_A::TOGGLE) + } +} +#[doc = "Field `OUTINIT` reader - When in task mode: Initial value of the output when the GPIOTE channel is configured. When in event mode: No effect."] +pub type OUTINIT_R = crate::BitReader; +#[doc = "When in task mode: Initial value of the output when the GPIOTE channel is configured. When in event mode: No effect.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum OUTINIT_A { + #[doc = "0: Task mode: Initial value of pin before task triggering is low"] + LOW = 0, + #[doc = "1: Task mode: Initial value of pin before task triggering is high"] + HIGH = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: OUTINIT_A) -> Self { + variant as u8 != 0 + } +} +impl OUTINIT_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> OUTINIT_A { + match self.bits { + false => OUTINIT_A::LOW, + true => OUTINIT_A::HIGH, + } + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + *self == OUTINIT_A::LOW + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + *self == OUTINIT_A::HIGH + } +} +#[doc = "Field `OUTINIT` writer - When in task mode: Initial value of the output when the GPIOTE channel is configured. When in event mode: No effect."] +pub type OUTINIT_W<'a, const O: u8> = crate::BitWriter<'a, u32, CONFIG_SPEC, OUTINIT_A, O>; +impl<'a, const O: u8> OUTINIT_W<'a, O> { + #[doc = "Task mode: Initial value of pin before task triggering is low"] + #[inline(always)] + pub fn low(self) -> &'a mut W { + self.variant(OUTINIT_A::LOW) + } + #[doc = "Task mode: Initial value of pin before task triggering is high"] + #[inline(always)] + pub fn high(self) -> &'a mut W { + self.variant(OUTINIT_A::HIGH) + } +} +impl R { + #[doc = "Bits 0:1 - Mode"] + #[inline(always)] + pub fn mode(&self) -> MODE_R { + MODE_R::new((self.bits & 3) as u8) + } + #[doc = "Bits 8:12 - GPIO number associated with SET\\[n\\], CLR\\[n\\], and OUT\\[n\\] +tasks and IN\\[n\\] +event"] + #[inline(always)] + pub fn psel(&self) -> PSEL_R { + PSEL_R::new(((self.bits >> 8) & 0x1f) as u8) + } + #[doc = "Bits 16:17 - When In task mode: Operation to be performed on output when OUT\\[n\\] +task is triggered. When In event mode: Operation on input that shall trigger IN\\[n\\] +event."] + #[inline(always)] + pub fn polarity(&self) -> POLARITY_R { + POLARITY_R::new(((self.bits >> 16) & 3) as u8) + } + #[doc = "Bit 20 - When in task mode: Initial value of the output when the GPIOTE channel is configured. When in event mode: No effect."] + #[inline(always)] + pub fn outinit(&self) -> OUTINIT_R { + OUTINIT_R::new(((self.bits >> 20) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:1 - Mode"] + #[inline(always)] + pub fn mode(&mut self) -> MODE_W<0> { + MODE_W::new(self) + } + #[doc = "Bits 8:12 - GPIO number associated with SET\\[n\\], CLR\\[n\\], and OUT\\[n\\] +tasks and IN\\[n\\] +event"] + #[inline(always)] + pub fn psel(&mut self) -> PSEL_W<8> { + PSEL_W::new(self) + } + #[doc = "Bits 16:17 - When In task mode: Operation to be performed on output when OUT\\[n\\] +task is triggered. When In event mode: Operation on input that shall trigger IN\\[n\\] +event."] + #[inline(always)] + pub fn polarity(&mut self) -> POLARITY_W<16> { + POLARITY_W::new(self) + } + #[doc = "Bit 20 - When in task mode: Initial value of the output when the GPIOTE channel is configured. When in event mode: No effect."] + #[inline(always)] + pub fn outinit(&mut self) -> OUTINIT_W<20> { + OUTINIT_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Description collection: Configuration for OUT\\[n\\], SET\\[n\\], and CLR\\[n\\] +tasks and IN\\[n\\] +event\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [config](index.html) module"] +pub struct CONFIG_SPEC; +impl crate::RegisterSpec for CONFIG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [config::R](R) reader structure"] +impl crate::Readable for CONFIG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [config::W](W) writer structure"] +impl crate::Writable for CONFIG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CONFIG[%s] +to value 0"] +impl crate::Resettable for CONFIG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/gpiote0_s/events_in.rs b/pacs/nrf9120-pac/src/gpiote0_s/events_in.rs new file mode 100644 index 00000000..b2887ac3 --- /dev/null +++ b/pacs/nrf9120-pac/src/gpiote0_s/events_in.rs @@ -0,0 +1,127 @@ +#[doc = "Register `EVENTS_IN[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVENTS_IN[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `EVENTS_IN` reader - Event generated from pin specified in CONFIG\\[n\\].PSEL"] +pub type EVENTS_IN_R = crate::BitReader; +#[doc = "Event generated from pin specified in CONFIG\\[n\\].PSEL\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum EVENTS_IN_A { + #[doc = "0: Event not generated"] + NOT_GENERATED = 0, + #[doc = "1: Event generated"] + GENERATED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: EVENTS_IN_A) -> Self { + variant as u8 != 0 + } +} +impl EVENTS_IN_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EVENTS_IN_A { + match self.bits { + false => EVENTS_IN_A::NOT_GENERATED, + true => EVENTS_IN_A::GENERATED, + } + } + #[doc = "Checks if the value of the field is `NOT_GENERATED`"] + #[inline(always)] + pub fn is_not_generated(&self) -> bool { + *self == EVENTS_IN_A::NOT_GENERATED + } + #[doc = "Checks if the value of the field is `GENERATED`"] + #[inline(always)] + pub fn is_generated(&self) -> bool { + *self == EVENTS_IN_A::GENERATED + } +} +#[doc = "Field `EVENTS_IN` writer - Event generated from pin specified in CONFIG\\[n\\].PSEL"] +pub type EVENTS_IN_W<'a, const O: u8> = crate::BitWriter<'a, u32, EVENTS_IN_SPEC, EVENTS_IN_A, O>; +impl<'a, const O: u8> EVENTS_IN_W<'a, O> { + #[doc = "Event not generated"] + #[inline(always)] + pub fn not_generated(self) -> &'a mut W { + self.variant(EVENTS_IN_A::NOT_GENERATED) + } + #[doc = "Event generated"] + #[inline(always)] + pub fn generated(self) -> &'a mut W { + self.variant(EVENTS_IN_A::GENERATED) + } +} +impl R { + #[doc = "Bit 0 - Event generated from pin specified in CONFIG\\[n\\].PSEL"] + #[inline(always)] + pub fn events_in(&self) -> EVENTS_IN_R { + EVENTS_IN_R::new((self.bits & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Event generated from pin specified in CONFIG\\[n\\].PSEL"] + #[inline(always)] + pub fn events_in(&mut self) -> EVENTS_IN_W<0> { + EVENTS_IN_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Description collection: Event generated from pin specified in CONFIG\\[n\\].PSEL\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [events_in](index.html) module"] +pub struct EVENTS_IN_SPEC; +impl crate::RegisterSpec for EVENTS_IN_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [events_in::R](R) reader structure"] +impl crate::Readable for EVENTS_IN_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [events_in::W](W) writer structure"] +impl crate::Writable for EVENTS_IN_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EVENTS_IN[%s] +to value 0"] +impl crate::Resettable for EVENTS_IN_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/gpiote0_s/events_port.rs b/pacs/nrf9120-pac/src/gpiote0_s/events_port.rs new file mode 100644 index 00000000..ce79a70f --- /dev/null +++ b/pacs/nrf9120-pac/src/gpiote0_s/events_port.rs @@ -0,0 +1,127 @@ +#[doc = "Register `EVENTS_PORT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVENTS_PORT` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `EVENTS_PORT` reader - Event generated from multiple input GPIO pins with SENSE mechanism enabled"] +pub type EVENTS_PORT_R = crate::BitReader; +#[doc = "Event generated from multiple input GPIO pins with SENSE mechanism enabled\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum EVENTS_PORT_A { + #[doc = "0: Event not generated"] + NOT_GENERATED = 0, + #[doc = "1: Event generated"] + GENERATED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: EVENTS_PORT_A) -> Self { + variant as u8 != 0 + } +} +impl EVENTS_PORT_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EVENTS_PORT_A { + match self.bits { + false => EVENTS_PORT_A::NOT_GENERATED, + true => EVENTS_PORT_A::GENERATED, + } + } + #[doc = "Checks if the value of the field is `NOT_GENERATED`"] + #[inline(always)] + pub fn is_not_generated(&self) -> bool { + *self == EVENTS_PORT_A::NOT_GENERATED + } + #[doc = "Checks if the value of the field is `GENERATED`"] + #[inline(always)] + pub fn is_generated(&self) -> bool { + *self == EVENTS_PORT_A::GENERATED + } +} +#[doc = "Field `EVENTS_PORT` writer - Event generated from multiple input GPIO pins with SENSE mechanism enabled"] +pub type EVENTS_PORT_W<'a, const O: u8> = + crate::BitWriter<'a, u32, EVENTS_PORT_SPEC, EVENTS_PORT_A, O>; +impl<'a, const O: u8> EVENTS_PORT_W<'a, O> { + #[doc = "Event not generated"] + #[inline(always)] + pub fn not_generated(self) -> &'a mut W { + self.variant(EVENTS_PORT_A::NOT_GENERATED) + } + #[doc = "Event generated"] + #[inline(always)] + pub fn generated(self) -> &'a mut W { + self.variant(EVENTS_PORT_A::GENERATED) + } +} +impl R { + #[doc = "Bit 0 - Event generated from multiple input GPIO pins with SENSE mechanism enabled"] + #[inline(always)] + pub fn events_port(&self) -> EVENTS_PORT_R { + EVENTS_PORT_R::new((self.bits & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Event generated from multiple input GPIO pins with SENSE mechanism enabled"] + #[inline(always)] + pub fn events_port(&mut self) -> EVENTS_PORT_W<0> { + EVENTS_PORT_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Event generated from multiple input GPIO pins with SENSE mechanism enabled\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [events_port](index.html) module"] +pub struct EVENTS_PORT_SPEC; +impl crate::RegisterSpec for EVENTS_PORT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [events_port::R](R) reader structure"] +impl crate::Readable for EVENTS_PORT_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [events_port::W](W) writer structure"] +impl crate::Writable for EVENTS_PORT_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EVENTS_PORT to value 0"] +impl crate::Resettable for EVENTS_PORT_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/gpiote0_s/intenclr.rs b/pacs/nrf9120-pac/src/gpiote0_s/intenclr.rs new file mode 100644 index 00000000..de4b1c92 --- /dev/null +++ b/pacs/nrf9120-pac/src/gpiote0_s/intenclr.rs @@ -0,0 +1,669 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `IN0` reader - Write '1' to disable interrupt for event IN\\[0\\]"] +pub type IN0_R = crate::BitReader; +#[doc = "Write '1' to disable interrupt for event IN\\[0\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum IN0_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: IN0_A) -> Self { + variant as u8 != 0 + } +} +impl IN0_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> IN0_A { + match self.bits { + false => IN0_A::DISABLED, + true => IN0_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == IN0_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == IN0_A::ENABLED + } +} +#[doc = "Write '1' to disable interrupt for event IN\\[0\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum IN0_AW { + #[doc = "1: Disable"] + CLEAR = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: IN0_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `IN0` writer - Write '1' to disable interrupt for event IN\\[0\\]"] +pub type IN0_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENCLR_SPEC, IN0_AW, O>; +impl<'a, const O: u8> IN0_W<'a, O> { + #[doc = "Disable"] + #[inline(always)] + pub fn clear(self) -> &'a mut W { + self.variant(IN0_AW::CLEAR) + } +} +#[doc = "Field `IN1` reader - Write '1' to disable interrupt for event IN\\[1\\]"] +pub type IN1_R = crate::BitReader; +#[doc = "Write '1' to disable interrupt for event IN\\[1\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum IN1_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: IN1_A) -> Self { + variant as u8 != 0 + } +} +impl IN1_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> IN1_A { + match self.bits { + false => IN1_A::DISABLED, + true => IN1_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == IN1_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == IN1_A::ENABLED + } +} +#[doc = "Write '1' to disable interrupt for event IN\\[1\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum IN1_AW { + #[doc = "1: Disable"] + CLEAR = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: IN1_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `IN1` writer - Write '1' to disable interrupt for event IN\\[1\\]"] +pub type IN1_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENCLR_SPEC, IN1_AW, O>; +impl<'a, const O: u8> IN1_W<'a, O> { + #[doc = "Disable"] + #[inline(always)] + pub fn clear(self) -> &'a mut W { + self.variant(IN1_AW::CLEAR) + } +} +#[doc = "Field `IN2` reader - Write '1' to disable interrupt for event IN\\[2\\]"] +pub type IN2_R = crate::BitReader; +#[doc = "Write '1' to disable interrupt for event IN\\[2\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum IN2_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: IN2_A) -> Self { + variant as u8 != 0 + } +} +impl IN2_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> IN2_A { + match self.bits { + false => IN2_A::DISABLED, + true => IN2_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == IN2_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == IN2_A::ENABLED + } +} +#[doc = "Write '1' to disable interrupt for event IN\\[2\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum IN2_AW { + #[doc = "1: Disable"] + CLEAR = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: IN2_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `IN2` writer - Write '1' to disable interrupt for event IN\\[2\\]"] +pub type IN2_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENCLR_SPEC, IN2_AW, O>; +impl<'a, const O: u8> IN2_W<'a, O> { + #[doc = "Disable"] + #[inline(always)] + pub fn clear(self) -> &'a mut W { + self.variant(IN2_AW::CLEAR) + } +} +#[doc = "Field `IN3` reader - Write '1' to disable interrupt for event IN\\[3\\]"] +pub type IN3_R = crate::BitReader; +#[doc = "Write '1' to disable interrupt for event IN\\[3\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum IN3_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: IN3_A) -> Self { + variant as u8 != 0 + } +} +impl IN3_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> IN3_A { + match self.bits { + false => IN3_A::DISABLED, + true => IN3_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == IN3_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == IN3_A::ENABLED + } +} +#[doc = "Write '1' to disable interrupt for event IN\\[3\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum IN3_AW { + #[doc = "1: Disable"] + CLEAR = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: IN3_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `IN3` writer - Write '1' to disable interrupt for event IN\\[3\\]"] +pub type IN3_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENCLR_SPEC, IN3_AW, O>; +impl<'a, const O: u8> IN3_W<'a, O> { + #[doc = "Disable"] + #[inline(always)] + pub fn clear(self) -> &'a mut W { + self.variant(IN3_AW::CLEAR) + } +} +#[doc = "Field `IN4` reader - Write '1' to disable interrupt for event IN\\[4\\]"] +pub type IN4_R = crate::BitReader; +#[doc = "Write '1' to disable interrupt for event IN\\[4\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum IN4_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: IN4_A) -> Self { + variant as u8 != 0 + } +} +impl IN4_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> IN4_A { + match self.bits { + false => IN4_A::DISABLED, + true => IN4_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == IN4_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == IN4_A::ENABLED + } +} +#[doc = "Write '1' to disable interrupt for event IN\\[4\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum IN4_AW { + #[doc = "1: Disable"] + CLEAR = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: IN4_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `IN4` writer - Write '1' to disable interrupt for event IN\\[4\\]"] +pub type IN4_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENCLR_SPEC, IN4_AW, O>; +impl<'a, const O: u8> IN4_W<'a, O> { + #[doc = "Disable"] + #[inline(always)] + pub fn clear(self) -> &'a mut W { + self.variant(IN4_AW::CLEAR) + } +} +#[doc = "Field `IN5` reader - Write '1' to disable interrupt for event IN\\[5\\]"] +pub type IN5_R = crate::BitReader; +#[doc = "Write '1' to disable interrupt for event IN\\[5\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum IN5_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: IN5_A) -> Self { + variant as u8 != 0 + } +} +impl IN5_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> IN5_A { + match self.bits { + false => IN5_A::DISABLED, + true => IN5_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == IN5_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == IN5_A::ENABLED + } +} +#[doc = "Write '1' to disable interrupt for event IN\\[5\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum IN5_AW { + #[doc = "1: Disable"] + CLEAR = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: IN5_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `IN5` writer - Write '1' to disable interrupt for event IN\\[5\\]"] +pub type IN5_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENCLR_SPEC, IN5_AW, O>; +impl<'a, const O: u8> IN5_W<'a, O> { + #[doc = "Disable"] + #[inline(always)] + pub fn clear(self) -> &'a mut W { + self.variant(IN5_AW::CLEAR) + } +} +#[doc = "Field `IN6` reader - Write '1' to disable interrupt for event IN\\[6\\]"] +pub type IN6_R = crate::BitReader; +#[doc = "Write '1' to disable interrupt for event IN\\[6\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum IN6_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: IN6_A) -> Self { + variant as u8 != 0 + } +} +impl IN6_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> IN6_A { + match self.bits { + false => IN6_A::DISABLED, + true => IN6_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == IN6_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == IN6_A::ENABLED + } +} +#[doc = "Write '1' to disable interrupt for event IN\\[6\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum IN6_AW { + #[doc = "1: Disable"] + CLEAR = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: IN6_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `IN6` writer - Write '1' to disable interrupt for event IN\\[6\\]"] +pub type IN6_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENCLR_SPEC, IN6_AW, O>; +impl<'a, const O: u8> IN6_W<'a, O> { + #[doc = "Disable"] + #[inline(always)] + pub fn clear(self) -> &'a mut W { + self.variant(IN6_AW::CLEAR) + } +} +#[doc = "Field `IN7` reader - Write '1' to disable interrupt for event IN\\[7\\]"] +pub type IN7_R = crate::BitReader; +#[doc = "Write '1' to disable interrupt for event IN\\[7\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum IN7_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: IN7_A) -> Self { + variant as u8 != 0 + } +} +impl IN7_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> IN7_A { + match self.bits { + false => IN7_A::DISABLED, + true => IN7_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == IN7_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == IN7_A::ENABLED + } +} +#[doc = "Write '1' to disable interrupt for event IN\\[7\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum IN7_AW { + #[doc = "1: Disable"] + CLEAR = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: IN7_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `IN7` writer - Write '1' to disable interrupt for event IN\\[7\\]"] +pub type IN7_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENCLR_SPEC, IN7_AW, O>; +impl<'a, const O: u8> IN7_W<'a, O> { + #[doc = "Disable"] + #[inline(always)] + pub fn clear(self) -> &'a mut W { + self.variant(IN7_AW::CLEAR) + } +} +#[doc = "Field `PORT` reader - Write '1' to disable interrupt for event PORT"] +pub type PORT_R = crate::BitReader; +#[doc = "Write '1' to disable interrupt for event PORT\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PORT_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PORT_A) -> Self { + variant as u8 != 0 + } +} +impl PORT_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PORT_A { + match self.bits { + false => PORT_A::DISABLED, + true => PORT_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == PORT_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == PORT_A::ENABLED + } +} +#[doc = "Write '1' to disable interrupt for event PORT\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PORT_AW { + #[doc = "1: Disable"] + CLEAR = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PORT_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PORT` writer - Write '1' to disable interrupt for event PORT"] +pub type PORT_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENCLR_SPEC, PORT_AW, O>; +impl<'a, const O: u8> PORT_W<'a, O> { + #[doc = "Disable"] + #[inline(always)] + pub fn clear(self) -> &'a mut W { + self.variant(PORT_AW::CLEAR) + } +} +impl R { + #[doc = "Bit 0 - Write '1' to disable interrupt for event IN\\[0\\]"] + #[inline(always)] + pub fn in0(&self) -> IN0_R { + IN0_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Write '1' to disable interrupt for event IN\\[1\\]"] + #[inline(always)] + pub fn in1(&self) -> IN1_R { + IN1_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Write '1' to disable interrupt for event IN\\[2\\]"] + #[inline(always)] + pub fn in2(&self) -> IN2_R { + IN2_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Write '1' to disable interrupt for event IN\\[3\\]"] + #[inline(always)] + pub fn in3(&self) -> IN3_R { + IN3_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Write '1' to disable interrupt for event IN\\[4\\]"] + #[inline(always)] + pub fn in4(&self) -> IN4_R { + IN4_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Write '1' to disable interrupt for event IN\\[5\\]"] + #[inline(always)] + pub fn in5(&self) -> IN5_R { + IN5_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Write '1' to disable interrupt for event IN\\[6\\]"] + #[inline(always)] + pub fn in6(&self) -> IN6_R { + IN6_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Write '1' to disable interrupt for event IN\\[7\\]"] + #[inline(always)] + pub fn in7(&self) -> IN7_R { + IN7_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 31 - Write '1' to disable interrupt for event PORT"] + #[inline(always)] + pub fn port(&self) -> PORT_R { + PORT_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Write '1' to disable interrupt for event IN\\[0\\]"] + #[inline(always)] + pub fn in0(&mut self) -> IN0_W<0> { + IN0_W::new(self) + } + #[doc = "Bit 1 - Write '1' to disable interrupt for event IN\\[1\\]"] + #[inline(always)] + pub fn in1(&mut self) -> IN1_W<1> { + IN1_W::new(self) + } + #[doc = "Bit 2 - Write '1' to disable interrupt for event IN\\[2\\]"] + #[inline(always)] + pub fn in2(&mut self) -> IN2_W<2> { + IN2_W::new(self) + } + #[doc = "Bit 3 - Write '1' to disable interrupt for event IN\\[3\\]"] + #[inline(always)] + pub fn in3(&mut self) -> IN3_W<3> { + IN3_W::new(self) + } + #[doc = "Bit 4 - Write '1' to disable interrupt for event IN\\[4\\]"] + #[inline(always)] + pub fn in4(&mut self) -> IN4_W<4> { + IN4_W::new(self) + } + #[doc = "Bit 5 - Write '1' to disable interrupt for event IN\\[5\\]"] + #[inline(always)] + pub fn in5(&mut self) -> IN5_W<5> { + IN5_W::new(self) + } + #[doc = "Bit 6 - Write '1' to disable interrupt for event IN\\[6\\]"] + #[inline(always)] + pub fn in6(&mut self) -> IN6_W<6> { + IN6_W::new(self) + } + #[doc = "Bit 7 - Write '1' to disable interrupt for event IN\\[7\\]"] + #[inline(always)] + pub fn in7(&mut self) -> IN7_W<7> { + IN7_W::new(self) + } + #[doc = "Bit 31 - Write '1' to disable interrupt for event PORT"] + #[inline(always)] + pub fn port(&mut self) -> PORT_W<31> { + PORT_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Disable interrupt\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/gpiote0_s/intenset.rs b/pacs/nrf9120-pac/src/gpiote0_s/intenset.rs new file mode 100644 index 00000000..60088f9c --- /dev/null +++ b/pacs/nrf9120-pac/src/gpiote0_s/intenset.rs @@ -0,0 +1,669 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `IN0` reader - Write '1' to enable interrupt for event IN\\[0\\]"] +pub type IN0_R = crate::BitReader; +#[doc = "Write '1' to enable interrupt for event IN\\[0\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum IN0_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: IN0_A) -> Self { + variant as u8 != 0 + } +} +impl IN0_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> IN0_A { + match self.bits { + false => IN0_A::DISABLED, + true => IN0_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == IN0_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == IN0_A::ENABLED + } +} +#[doc = "Write '1' to enable interrupt for event IN\\[0\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum IN0_AW { + #[doc = "1: Enable"] + SET = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: IN0_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `IN0` writer - Write '1' to enable interrupt for event IN\\[0\\]"] +pub type IN0_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENSET_SPEC, IN0_AW, O>; +impl<'a, const O: u8> IN0_W<'a, O> { + #[doc = "Enable"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(IN0_AW::SET) + } +} +#[doc = "Field `IN1` reader - Write '1' to enable interrupt for event IN\\[1\\]"] +pub type IN1_R = crate::BitReader; +#[doc = "Write '1' to enable interrupt for event IN\\[1\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum IN1_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: IN1_A) -> Self { + variant as u8 != 0 + } +} +impl IN1_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> IN1_A { + match self.bits { + false => IN1_A::DISABLED, + true => IN1_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == IN1_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == IN1_A::ENABLED + } +} +#[doc = "Write '1' to enable interrupt for event IN\\[1\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum IN1_AW { + #[doc = "1: Enable"] + SET = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: IN1_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `IN1` writer - Write '1' to enable interrupt for event IN\\[1\\]"] +pub type IN1_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENSET_SPEC, IN1_AW, O>; +impl<'a, const O: u8> IN1_W<'a, O> { + #[doc = "Enable"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(IN1_AW::SET) + } +} +#[doc = "Field `IN2` reader - Write '1' to enable interrupt for event IN\\[2\\]"] +pub type IN2_R = crate::BitReader; +#[doc = "Write '1' to enable interrupt for event IN\\[2\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum IN2_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: IN2_A) -> Self { + variant as u8 != 0 + } +} +impl IN2_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> IN2_A { + match self.bits { + false => IN2_A::DISABLED, + true => IN2_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == IN2_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == IN2_A::ENABLED + } +} +#[doc = "Write '1' to enable interrupt for event IN\\[2\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum IN2_AW { + #[doc = "1: Enable"] + SET = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: IN2_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `IN2` writer - Write '1' to enable interrupt for event IN\\[2\\]"] +pub type IN2_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENSET_SPEC, IN2_AW, O>; +impl<'a, const O: u8> IN2_W<'a, O> { + #[doc = "Enable"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(IN2_AW::SET) + } +} +#[doc = "Field `IN3` reader - Write '1' to enable interrupt for event IN\\[3\\]"] +pub type IN3_R = crate::BitReader; +#[doc = "Write '1' to enable interrupt for event IN\\[3\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum IN3_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: IN3_A) -> Self { + variant as u8 != 0 + } +} +impl IN3_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> IN3_A { + match self.bits { + false => IN3_A::DISABLED, + true => IN3_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == IN3_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == IN3_A::ENABLED + } +} +#[doc = "Write '1' to enable interrupt for event IN\\[3\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum IN3_AW { + #[doc = "1: Enable"] + SET = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: IN3_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `IN3` writer - Write '1' to enable interrupt for event IN\\[3\\]"] +pub type IN3_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENSET_SPEC, IN3_AW, O>; +impl<'a, const O: u8> IN3_W<'a, O> { + #[doc = "Enable"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(IN3_AW::SET) + } +} +#[doc = "Field `IN4` reader - Write '1' to enable interrupt for event IN\\[4\\]"] +pub type IN4_R = crate::BitReader; +#[doc = "Write '1' to enable interrupt for event IN\\[4\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum IN4_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: IN4_A) -> Self { + variant as u8 != 0 + } +} +impl IN4_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> IN4_A { + match self.bits { + false => IN4_A::DISABLED, + true => IN4_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == IN4_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == IN4_A::ENABLED + } +} +#[doc = "Write '1' to enable interrupt for event IN\\[4\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum IN4_AW { + #[doc = "1: Enable"] + SET = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: IN4_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `IN4` writer - Write '1' to enable interrupt for event IN\\[4\\]"] +pub type IN4_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENSET_SPEC, IN4_AW, O>; +impl<'a, const O: u8> IN4_W<'a, O> { + #[doc = "Enable"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(IN4_AW::SET) + } +} +#[doc = "Field `IN5` reader - Write '1' to enable interrupt for event IN\\[5\\]"] +pub type IN5_R = crate::BitReader; +#[doc = "Write '1' to enable interrupt for event IN\\[5\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum IN5_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: IN5_A) -> Self { + variant as u8 != 0 + } +} +impl IN5_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> IN5_A { + match self.bits { + false => IN5_A::DISABLED, + true => IN5_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == IN5_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == IN5_A::ENABLED + } +} +#[doc = "Write '1' to enable interrupt for event IN\\[5\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum IN5_AW { + #[doc = "1: Enable"] + SET = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: IN5_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `IN5` writer - Write '1' to enable interrupt for event IN\\[5\\]"] +pub type IN5_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENSET_SPEC, IN5_AW, O>; +impl<'a, const O: u8> IN5_W<'a, O> { + #[doc = "Enable"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(IN5_AW::SET) + } +} +#[doc = "Field `IN6` reader - Write '1' to enable interrupt for event IN\\[6\\]"] +pub type IN6_R = crate::BitReader; +#[doc = "Write '1' to enable interrupt for event IN\\[6\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum IN6_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: IN6_A) -> Self { + variant as u8 != 0 + } +} +impl IN6_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> IN6_A { + match self.bits { + false => IN6_A::DISABLED, + true => IN6_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == IN6_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == IN6_A::ENABLED + } +} +#[doc = "Write '1' to enable interrupt for event IN\\[6\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum IN6_AW { + #[doc = "1: Enable"] + SET = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: IN6_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `IN6` writer - Write '1' to enable interrupt for event IN\\[6\\]"] +pub type IN6_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENSET_SPEC, IN6_AW, O>; +impl<'a, const O: u8> IN6_W<'a, O> { + #[doc = "Enable"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(IN6_AW::SET) + } +} +#[doc = "Field `IN7` reader - Write '1' to enable interrupt for event IN\\[7\\]"] +pub type IN7_R = crate::BitReader; +#[doc = "Write '1' to enable interrupt for event IN\\[7\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum IN7_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: IN7_A) -> Self { + variant as u8 != 0 + } +} +impl IN7_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> IN7_A { + match self.bits { + false => IN7_A::DISABLED, + true => IN7_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == IN7_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == IN7_A::ENABLED + } +} +#[doc = "Write '1' to enable interrupt for event IN\\[7\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum IN7_AW { + #[doc = "1: Enable"] + SET = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: IN7_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `IN7` writer - Write '1' to enable interrupt for event IN\\[7\\]"] +pub type IN7_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENSET_SPEC, IN7_AW, O>; +impl<'a, const O: u8> IN7_W<'a, O> { + #[doc = "Enable"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(IN7_AW::SET) + } +} +#[doc = "Field `PORT` reader - Write '1' to enable interrupt for event PORT"] +pub type PORT_R = crate::BitReader; +#[doc = "Write '1' to enable interrupt for event PORT\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PORT_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PORT_A) -> Self { + variant as u8 != 0 + } +} +impl PORT_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PORT_A { + match self.bits { + false => PORT_A::DISABLED, + true => PORT_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == PORT_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == PORT_A::ENABLED + } +} +#[doc = "Write '1' to enable interrupt for event PORT\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PORT_AW { + #[doc = "1: Enable"] + SET = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PORT_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PORT` writer - Write '1' to enable interrupt for event PORT"] +pub type PORT_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENSET_SPEC, PORT_AW, O>; +impl<'a, const O: u8> PORT_W<'a, O> { + #[doc = "Enable"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(PORT_AW::SET) + } +} +impl R { + #[doc = "Bit 0 - Write '1' to enable interrupt for event IN\\[0\\]"] + #[inline(always)] + pub fn in0(&self) -> IN0_R { + IN0_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Write '1' to enable interrupt for event IN\\[1\\]"] + #[inline(always)] + pub fn in1(&self) -> IN1_R { + IN1_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Write '1' to enable interrupt for event IN\\[2\\]"] + #[inline(always)] + pub fn in2(&self) -> IN2_R { + IN2_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Write '1' to enable interrupt for event IN\\[3\\]"] + #[inline(always)] + pub fn in3(&self) -> IN3_R { + IN3_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Write '1' to enable interrupt for event IN\\[4\\]"] + #[inline(always)] + pub fn in4(&self) -> IN4_R { + IN4_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Write '1' to enable interrupt for event IN\\[5\\]"] + #[inline(always)] + pub fn in5(&self) -> IN5_R { + IN5_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Write '1' to enable interrupt for event IN\\[6\\]"] + #[inline(always)] + pub fn in6(&self) -> IN6_R { + IN6_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Write '1' to enable interrupt for event IN\\[7\\]"] + #[inline(always)] + pub fn in7(&self) -> IN7_R { + IN7_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 31 - Write '1' to enable interrupt for event PORT"] + #[inline(always)] + pub fn port(&self) -> PORT_R { + PORT_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Write '1' to enable interrupt for event IN\\[0\\]"] + #[inline(always)] + pub fn in0(&mut self) -> IN0_W<0> { + IN0_W::new(self) + } + #[doc = "Bit 1 - Write '1' to enable interrupt for event IN\\[1\\]"] + #[inline(always)] + pub fn in1(&mut self) -> IN1_W<1> { + IN1_W::new(self) + } + #[doc = "Bit 2 - Write '1' to enable interrupt for event IN\\[2\\]"] + #[inline(always)] + pub fn in2(&mut self) -> IN2_W<2> { + IN2_W::new(self) + } + #[doc = "Bit 3 - Write '1' to enable interrupt for event IN\\[3\\]"] + #[inline(always)] + pub fn in3(&mut self) -> IN3_W<3> { + IN3_W::new(self) + } + #[doc = "Bit 4 - Write '1' to enable interrupt for event IN\\[4\\]"] + #[inline(always)] + pub fn in4(&mut self) -> IN4_W<4> { + IN4_W::new(self) + } + #[doc = "Bit 5 - Write '1' to enable interrupt for event IN\\[5\\]"] + #[inline(always)] + pub fn in5(&mut self) -> IN5_W<5> { + IN5_W::new(self) + } + #[doc = "Bit 6 - Write '1' to enable interrupt for event IN\\[6\\]"] + #[inline(always)] + pub fn in6(&mut self) -> IN6_W<6> { + IN6_W::new(self) + } + #[doc = "Bit 7 - Write '1' to enable interrupt for event IN\\[7\\]"] + #[inline(always)] + pub fn in7(&mut self) -> IN7_W<7> { + IN7_W::new(self) + } + #[doc = "Bit 31 - Write '1' to enable interrupt for event PORT"] + #[inline(always)] + pub fn port(&mut self) -> PORT_W<31> { + PORT_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Enable interrupt\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/gpiote0_s/publish_in.rs b/pacs/nrf9120-pac/src/gpiote0_s/publish_in.rs new file mode 100644 index 00000000..4ba1a936 --- /dev/null +++ b/pacs/nrf9120-pac/src/gpiote0_s/publish_in.rs @@ -0,0 +1,145 @@ +#[doc = "Register `PUBLISH_IN[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PUBLISH_IN[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CHIDX` reader - DPPI channel that event IN\\[n\\] +will publish to"] +pub type CHIDX_R = crate::FieldReader; +#[doc = "Field `CHIDX` writer - DPPI channel that event IN\\[n\\] +will publish to"] +pub type CHIDX_W<'a, const O: u8> = crate::FieldWriter<'a, u32, PUBLISH_IN_SPEC, u8, u8, 8, O>; +#[doc = "Field `EN` reader - "] +pub type EN_R = crate::BitReader; +#[doc = "\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum EN_A { + #[doc = "0: Disable publishing"] + DISABLED = 0, + #[doc = "1: Enable publishing"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: EN_A) -> Self { + variant as u8 != 0 + } +} +impl EN_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EN_A { + match self.bits { + false => EN_A::DISABLED, + true => EN_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == EN_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == EN_A::ENABLED + } +} +#[doc = "Field `EN` writer - "] +pub type EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, PUBLISH_IN_SPEC, EN_A, O>; +impl<'a, const O: u8> EN_W<'a, O> { + #[doc = "Disable publishing"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(EN_A::DISABLED) + } + #[doc = "Enable publishing"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(EN_A::ENABLED) + } +} +impl R { + #[doc = "Bits 0:7 - DPPI channel that event IN\\[n\\] +will publish to"] + #[inline(always)] + pub fn chidx(&self) -> CHIDX_R { + CHIDX_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&self) -> EN_R { + EN_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:7 - DPPI channel that event IN\\[n\\] +will publish to"] + #[inline(always)] + pub fn chidx(&mut self) -> CHIDX_W<0> { + CHIDX_W::new(self) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&mut self) -> EN_W<31> { + EN_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Description collection: Publish configuration for event IN\\[n\\]\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [publish_in](index.html) module"] +pub struct PUBLISH_IN_SPEC; +impl crate::RegisterSpec for PUBLISH_IN_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [publish_in::R](R) reader structure"] +impl crate::Readable for PUBLISH_IN_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [publish_in::W](W) writer structure"] +impl crate::Writable for PUBLISH_IN_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PUBLISH_IN[%s] +to value 0"] +impl crate::Resettable for PUBLISH_IN_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/gpiote0_s/publish_port.rs b/pacs/nrf9120-pac/src/gpiote0_s/publish_port.rs new file mode 100644 index 00000000..6d9980f4 --- /dev/null +++ b/pacs/nrf9120-pac/src/gpiote0_s/publish_port.rs @@ -0,0 +1,140 @@ +#[doc = "Register `PUBLISH_PORT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PUBLISH_PORT` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CHIDX` reader - DPPI channel that event PORT will publish to"] +pub type CHIDX_R = crate::FieldReader; +#[doc = "Field `CHIDX` writer - DPPI channel that event PORT will publish to"] +pub type CHIDX_W<'a, const O: u8> = crate::FieldWriter<'a, u32, PUBLISH_PORT_SPEC, u8, u8, 8, O>; +#[doc = "Field `EN` reader - "] +pub type EN_R = crate::BitReader; +#[doc = "\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum EN_A { + #[doc = "0: Disable publishing"] + DISABLED = 0, + #[doc = "1: Enable publishing"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: EN_A) -> Self { + variant as u8 != 0 + } +} +impl EN_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EN_A { + match self.bits { + false => EN_A::DISABLED, + true => EN_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == EN_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == EN_A::ENABLED + } +} +#[doc = "Field `EN` writer - "] +pub type EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, PUBLISH_PORT_SPEC, EN_A, O>; +impl<'a, const O: u8> EN_W<'a, O> { + #[doc = "Disable publishing"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(EN_A::DISABLED) + } + #[doc = "Enable publishing"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(EN_A::ENABLED) + } +} +impl R { + #[doc = "Bits 0:7 - DPPI channel that event PORT will publish to"] + #[inline(always)] + pub fn chidx(&self) -> CHIDX_R { + CHIDX_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&self) -> EN_R { + EN_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:7 - DPPI channel that event PORT will publish to"] + #[inline(always)] + pub fn chidx(&mut self) -> CHIDX_W<0> { + CHIDX_W::new(self) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&mut self) -> EN_W<31> { + EN_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Publish configuration for event PORT\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [publish_port](index.html) module"] +pub struct PUBLISH_PORT_SPEC; +impl crate::RegisterSpec for PUBLISH_PORT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [publish_port::R](R) reader structure"] +impl crate::Readable for PUBLISH_PORT_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [publish_port::W](W) writer structure"] +impl crate::Writable for PUBLISH_PORT_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PUBLISH_PORT to value 0"] +impl crate::Resettable for PUBLISH_PORT_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/gpiote0_s/subscribe_clr.rs b/pacs/nrf9120-pac/src/gpiote0_s/subscribe_clr.rs new file mode 100644 index 00000000..7c79b2f7 --- /dev/null +++ b/pacs/nrf9120-pac/src/gpiote0_s/subscribe_clr.rs @@ -0,0 +1,145 @@ +#[doc = "Register `SUBSCRIBE_CLR[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SUBSCRIBE_CLR[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CHIDX` reader - DPPI channel that task CLR\\[n\\] +will subscribe to"] +pub type CHIDX_R = crate::FieldReader; +#[doc = "Field `CHIDX` writer - DPPI channel that task CLR\\[n\\] +will subscribe to"] +pub type CHIDX_W<'a, const O: u8> = crate::FieldWriter<'a, u32, SUBSCRIBE_CLR_SPEC, u8, u8, 8, O>; +#[doc = "Field `EN` reader - "] +pub type EN_R = crate::BitReader; +#[doc = "\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum EN_A { + #[doc = "0: Disable subscription"] + DISABLED = 0, + #[doc = "1: Enable subscription"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: EN_A) -> Self { + variant as u8 != 0 + } +} +impl EN_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EN_A { + match self.bits { + false => EN_A::DISABLED, + true => EN_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == EN_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == EN_A::ENABLED + } +} +#[doc = "Field `EN` writer - "] +pub type EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, SUBSCRIBE_CLR_SPEC, EN_A, O>; +impl<'a, const O: u8> EN_W<'a, O> { + #[doc = "Disable subscription"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(EN_A::DISABLED) + } + #[doc = "Enable subscription"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(EN_A::ENABLED) + } +} +impl R { + #[doc = "Bits 0:7 - DPPI channel that task CLR\\[n\\] +will subscribe to"] + #[inline(always)] + pub fn chidx(&self) -> CHIDX_R { + CHIDX_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&self) -> EN_R { + EN_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:7 - DPPI channel that task CLR\\[n\\] +will subscribe to"] + #[inline(always)] + pub fn chidx(&mut self) -> CHIDX_W<0> { + CHIDX_W::new(self) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&mut self) -> EN_W<31> { + EN_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Description collection: Subscribe configuration for task CLR\\[n\\]\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [subscribe_clr](index.html) module"] +pub struct SUBSCRIBE_CLR_SPEC; +impl crate::RegisterSpec for SUBSCRIBE_CLR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [subscribe_clr::R](R) reader structure"] +impl crate::Readable for SUBSCRIBE_CLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [subscribe_clr::W](W) writer structure"] +impl crate::Writable for SUBSCRIBE_CLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SUBSCRIBE_CLR[%s] +to value 0"] +impl crate::Resettable for SUBSCRIBE_CLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/gpiote0_s/subscribe_out.rs b/pacs/nrf9120-pac/src/gpiote0_s/subscribe_out.rs new file mode 100644 index 00000000..53ff64b3 --- /dev/null +++ b/pacs/nrf9120-pac/src/gpiote0_s/subscribe_out.rs @@ -0,0 +1,145 @@ +#[doc = "Register `SUBSCRIBE_OUT[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SUBSCRIBE_OUT[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CHIDX` reader - DPPI channel that task OUT\\[n\\] +will subscribe to"] +pub type CHIDX_R = crate::FieldReader; +#[doc = "Field `CHIDX` writer - DPPI channel that task OUT\\[n\\] +will subscribe to"] +pub type CHIDX_W<'a, const O: u8> = crate::FieldWriter<'a, u32, SUBSCRIBE_OUT_SPEC, u8, u8, 8, O>; +#[doc = "Field `EN` reader - "] +pub type EN_R = crate::BitReader; +#[doc = "\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum EN_A { + #[doc = "0: Disable subscription"] + DISABLED = 0, + #[doc = "1: Enable subscription"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: EN_A) -> Self { + variant as u8 != 0 + } +} +impl EN_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EN_A { + match self.bits { + false => EN_A::DISABLED, + true => EN_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == EN_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == EN_A::ENABLED + } +} +#[doc = "Field `EN` writer - "] +pub type EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, SUBSCRIBE_OUT_SPEC, EN_A, O>; +impl<'a, const O: u8> EN_W<'a, O> { + #[doc = "Disable subscription"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(EN_A::DISABLED) + } + #[doc = "Enable subscription"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(EN_A::ENABLED) + } +} +impl R { + #[doc = "Bits 0:7 - DPPI channel that task OUT\\[n\\] +will subscribe to"] + #[inline(always)] + pub fn chidx(&self) -> CHIDX_R { + CHIDX_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&self) -> EN_R { + EN_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:7 - DPPI channel that task OUT\\[n\\] +will subscribe to"] + #[inline(always)] + pub fn chidx(&mut self) -> CHIDX_W<0> { + CHIDX_W::new(self) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&mut self) -> EN_W<31> { + EN_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Description collection: Subscribe configuration for task OUT\\[n\\]\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [subscribe_out](index.html) module"] +pub struct SUBSCRIBE_OUT_SPEC; +impl crate::RegisterSpec for SUBSCRIBE_OUT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [subscribe_out::R](R) reader structure"] +impl crate::Readable for SUBSCRIBE_OUT_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [subscribe_out::W](W) writer structure"] +impl crate::Writable for SUBSCRIBE_OUT_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SUBSCRIBE_OUT[%s] +to value 0"] +impl crate::Resettable for SUBSCRIBE_OUT_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/gpiote0_s/subscribe_set.rs b/pacs/nrf9120-pac/src/gpiote0_s/subscribe_set.rs new file mode 100644 index 00000000..1c35dfe9 --- /dev/null +++ b/pacs/nrf9120-pac/src/gpiote0_s/subscribe_set.rs @@ -0,0 +1,145 @@ +#[doc = "Register `SUBSCRIBE_SET[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SUBSCRIBE_SET[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CHIDX` reader - DPPI channel that task SET\\[n\\] +will subscribe to"] +pub type CHIDX_R = crate::FieldReader; +#[doc = "Field `CHIDX` writer - DPPI channel that task SET\\[n\\] +will subscribe to"] +pub type CHIDX_W<'a, const O: u8> = crate::FieldWriter<'a, u32, SUBSCRIBE_SET_SPEC, u8, u8, 8, O>; +#[doc = "Field `EN` reader - "] +pub type EN_R = crate::BitReader; +#[doc = "\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum EN_A { + #[doc = "0: Disable subscription"] + DISABLED = 0, + #[doc = "1: Enable subscription"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: EN_A) -> Self { + variant as u8 != 0 + } +} +impl EN_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EN_A { + match self.bits { + false => EN_A::DISABLED, + true => EN_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == EN_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == EN_A::ENABLED + } +} +#[doc = "Field `EN` writer - "] +pub type EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, SUBSCRIBE_SET_SPEC, EN_A, O>; +impl<'a, const O: u8> EN_W<'a, O> { + #[doc = "Disable subscription"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(EN_A::DISABLED) + } + #[doc = "Enable subscription"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(EN_A::ENABLED) + } +} +impl R { + #[doc = "Bits 0:7 - DPPI channel that task SET\\[n\\] +will subscribe to"] + #[inline(always)] + pub fn chidx(&self) -> CHIDX_R { + CHIDX_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&self) -> EN_R { + EN_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:7 - DPPI channel that task SET\\[n\\] +will subscribe to"] + #[inline(always)] + pub fn chidx(&mut self) -> CHIDX_W<0> { + CHIDX_W::new(self) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&mut self) -> EN_W<31> { + EN_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Description collection: Subscribe configuration for task SET\\[n\\]\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [subscribe_set](index.html) module"] +pub struct SUBSCRIBE_SET_SPEC; +impl crate::RegisterSpec for SUBSCRIBE_SET_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [subscribe_set::R](R) reader structure"] +impl crate::Readable for SUBSCRIBE_SET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [subscribe_set::W](W) writer structure"] +impl crate::Writable for SUBSCRIBE_SET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SUBSCRIBE_SET[%s] +to value 0"] +impl crate::Resettable for SUBSCRIBE_SET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/gpiote0_s/tasks_clr.rs b/pacs/nrf9120-pac/src/gpiote0_s/tasks_clr.rs new file mode 100644 index 00000000..38e839f1 --- /dev/null +++ b/pacs/nrf9120-pac/src/gpiote0_s/tasks_clr.rs @@ -0,0 +1,72 @@ +#[doc = "Register `TASKS_CLR[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Task for writing to pin specified in CONFIG\\[n\\].PSEL. Action on pin is to set it low.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum TASKS_CLR_AW { + #[doc = "1: Trigger task"] + TRIGGER = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TASKS_CLR_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TASKS_CLR` writer - Task for writing to pin specified in CONFIG\\[n\\].PSEL. Action on pin is to set it low."] +pub type TASKS_CLR_W<'a, const O: u8> = crate::BitWriter<'a, u32, TASKS_CLR_SPEC, TASKS_CLR_AW, O>; +impl<'a, const O: u8> TASKS_CLR_W<'a, O> { + #[doc = "Trigger task"] + #[inline(always)] + pub fn trigger(self) -> &'a mut W { + self.variant(TASKS_CLR_AW::TRIGGER) + } +} +impl W { + #[doc = "Bit 0 - Task for writing to pin specified in CONFIG\\[n\\].PSEL. Action on pin is to set it low."] + #[inline(always)] + pub fn tasks_clr(&mut self) -> TASKS_CLR_W<0> { + TASKS_CLR_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Description collection: Task for writing to pin specified in CONFIG\\[n\\].PSEL. Action on pin is to set it low.\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tasks_clr](index.html) module"] +pub struct TASKS_CLR_SPEC; +impl crate::RegisterSpec for TASKS_CLR_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [tasks_clr::W](W) writer structure"] +impl crate::Writable for TASKS_CLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets TASKS_CLR[%s] +to value 0"] +impl crate::Resettable for TASKS_CLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/gpiote0_s/tasks_out.rs b/pacs/nrf9120-pac/src/gpiote0_s/tasks_out.rs new file mode 100644 index 00000000..12f6fc83 --- /dev/null +++ b/pacs/nrf9120-pac/src/gpiote0_s/tasks_out.rs @@ -0,0 +1,72 @@ +#[doc = "Register `TASKS_OUT[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Task for writing to pin specified in CONFIG\\[n\\].PSEL. Action on pin is configured in CONFIG\\[n\\].POLARITY.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum TASKS_OUT_AW { + #[doc = "1: Trigger task"] + TRIGGER = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TASKS_OUT_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TASKS_OUT` writer - Task for writing to pin specified in CONFIG\\[n\\].PSEL. Action on pin is configured in CONFIG\\[n\\].POLARITY."] +pub type TASKS_OUT_W<'a, const O: u8> = crate::BitWriter<'a, u32, TASKS_OUT_SPEC, TASKS_OUT_AW, O>; +impl<'a, const O: u8> TASKS_OUT_W<'a, O> { + #[doc = "Trigger task"] + #[inline(always)] + pub fn trigger(self) -> &'a mut W { + self.variant(TASKS_OUT_AW::TRIGGER) + } +} +impl W { + #[doc = "Bit 0 - Task for writing to pin specified in CONFIG\\[n\\].PSEL. Action on pin is configured in CONFIG\\[n\\].POLARITY."] + #[inline(always)] + pub fn tasks_out(&mut self) -> TASKS_OUT_W<0> { + TASKS_OUT_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Description collection: Task for writing to pin specified in CONFIG\\[n\\].PSEL. Action on pin is configured in CONFIG\\[n\\].POLARITY.\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tasks_out](index.html) module"] +pub struct TASKS_OUT_SPEC; +impl crate::RegisterSpec for TASKS_OUT_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [tasks_out::W](W) writer structure"] +impl crate::Writable for TASKS_OUT_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets TASKS_OUT[%s] +to value 0"] +impl crate::Resettable for TASKS_OUT_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/gpiote0_s/tasks_set.rs b/pacs/nrf9120-pac/src/gpiote0_s/tasks_set.rs new file mode 100644 index 00000000..3c0fd5e6 --- /dev/null +++ b/pacs/nrf9120-pac/src/gpiote0_s/tasks_set.rs @@ -0,0 +1,72 @@ +#[doc = "Register `TASKS_SET[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Task for writing to pin specified in CONFIG\\[n\\].PSEL. Action on pin is to set it high.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum TASKS_SET_AW { + #[doc = "1: Trigger task"] + TRIGGER = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TASKS_SET_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TASKS_SET` writer - Task for writing to pin specified in CONFIG\\[n\\].PSEL. Action on pin is to set it high."] +pub type TASKS_SET_W<'a, const O: u8> = crate::BitWriter<'a, u32, TASKS_SET_SPEC, TASKS_SET_AW, O>; +impl<'a, const O: u8> TASKS_SET_W<'a, O> { + #[doc = "Trigger task"] + #[inline(always)] + pub fn trigger(self) -> &'a mut W { + self.variant(TASKS_SET_AW::TRIGGER) + } +} +impl W { + #[doc = "Bit 0 - Task for writing to pin specified in CONFIG\\[n\\].PSEL. Action on pin is to set it high."] + #[inline(always)] + pub fn tasks_set(&mut self) -> TASKS_SET_W<0> { + TASKS_SET_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Description collection: Task for writing to pin specified in CONFIG\\[n\\].PSEL. Action on pin is to set it high.\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tasks_set](index.html) module"] +pub struct TASKS_SET_SPEC; +impl crate::RegisterSpec for TASKS_SET_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [tasks_set::W](W) writer structure"] +impl crate::Writable for TASKS_SET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets TASKS_SET[%s] +to value 0"] +impl crate::Resettable for TASKS_SET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/i2s_ns.rs b/pacs/nrf9120-pac/src/i2s_ns.rs new file mode 100644 index 00000000..c5b203b1 --- /dev/null +++ b/pacs/nrf9120-pac/src/i2s_ns.rs @@ -0,0 +1,134 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Starts continuous I2S transfer. Also starts MCK generator when this is enabled."] + pub tasks_start: TASKS_START, + #[doc = "0x04 - Stops I2S transfer. Also stops MCK generator. Triggering this task will cause the STOPPED event to be generated."] + pub tasks_stop: TASKS_STOP, + _reserved2: [u8; 0x78], + #[doc = "0x80 - Subscribe configuration for task START"] + pub subscribe_start: SUBSCRIBE_START, + #[doc = "0x84 - Subscribe configuration for task STOP"] + pub subscribe_stop: SUBSCRIBE_STOP, + _reserved4: [u8; 0x7c], + #[doc = "0x104 - The RXD.PTR register has been copied to internal double-buffers. When the I2S module is started and RX is enabled, this event will be generated for every RXTXD.MAXCNT words that are received on the SDIN pin."] + pub events_rxptrupd: EVENTS_RXPTRUPD, + #[doc = "0x108 - I2S transfer stopped."] + pub events_stopped: EVENTS_STOPPED, + _reserved6: [u8; 0x08], + #[doc = "0x114 - The TDX.PTR register has been copied to internal double-buffers. When the I2S module is started and TX is enabled, this event will be generated for every RXTXD.MAXCNT words that are sent on the SDOUT pin."] + pub events_txptrupd: EVENTS_TXPTRUPD, + _reserved7: [u8; 0x6c], + #[doc = "0x184 - Publish configuration for event RXPTRUPD"] + pub publish_rxptrupd: PUBLISH_RXPTRUPD, + #[doc = "0x188 - Publish configuration for event STOPPED"] + pub publish_stopped: PUBLISH_STOPPED, + _reserved9: [u8; 0x08], + #[doc = "0x194 - Publish configuration for event TXPTRUPD"] + pub publish_txptrupd: PUBLISH_TXPTRUPD, + _reserved10: [u8; 0x0168], + #[doc = "0x300 - Enable or disable interrupt"] + pub inten: INTEN, + #[doc = "0x304 - Enable interrupt"] + pub intenset: INTENSET, + #[doc = "0x308 - Disable interrupt"] + pub intenclr: INTENCLR, + _reserved13: [u8; 0x01f4], + #[doc = "0x500 - Enable I2S module."] + pub enable: ENABLE, + #[doc = "0x504..0x52c - Unspecified"] + pub config: CONFIG, + _reserved15: [u8; 0x0c], + #[doc = "0x538 - Unspecified"] + pub rxd: RXD, + _reserved16: [u8; 0x04], + #[doc = "0x540 - Unspecified"] + pub txd: TXD, + _reserved17: [u8; 0x0c], + #[doc = "0x550 - Unspecified"] + pub rxtxd: RXTXD, + _reserved18: [u8; 0x0c], + #[doc = "0x560..0x574 - Unspecified"] + pub psel: PSEL, +} +#[doc = "TASKS_START (w) register accessor: an alias for `Reg`"] +pub type TASKS_START = crate::Reg; +#[doc = "Starts continuous I2S transfer. Also starts MCK generator when this is enabled."] +pub mod tasks_start; +#[doc = "TASKS_STOP (w) register accessor: an alias for `Reg`"] +pub type TASKS_STOP = crate::Reg; +#[doc = "Stops I2S transfer. Also stops MCK generator. Triggering this task will cause the STOPPED event to be generated."] +pub mod tasks_stop; +#[doc = "SUBSCRIBE_START (rw) register accessor: an alias for `Reg`"] +pub type SUBSCRIBE_START = crate::Reg; +#[doc = "Subscribe configuration for task START"] +pub mod subscribe_start; +#[doc = "SUBSCRIBE_STOP (rw) register accessor: an alias for `Reg`"] +pub type SUBSCRIBE_STOP = crate::Reg; +#[doc = "Subscribe configuration for task STOP"] +pub mod subscribe_stop; +#[doc = "EVENTS_RXPTRUPD (rw) register accessor: an alias for `Reg`"] +pub type EVENTS_RXPTRUPD = crate::Reg; +#[doc = "The RXD.PTR register has been copied to internal double-buffers. When the I2S module is started and RX is enabled, this event will be generated for every RXTXD.MAXCNT words that are received on the SDIN pin."] +pub mod events_rxptrupd; +#[doc = "EVENTS_STOPPED (rw) register accessor: an alias for `Reg`"] +pub type EVENTS_STOPPED = crate::Reg; +#[doc = "I2S transfer stopped."] +pub mod events_stopped; +#[doc = "EVENTS_TXPTRUPD (rw) register accessor: an alias for `Reg`"] +pub type EVENTS_TXPTRUPD = crate::Reg; +#[doc = "The TDX.PTR register has been copied to internal double-buffers. When the I2S module is started and TX is enabled, this event will be generated for every RXTXD.MAXCNT words that are sent on the SDOUT pin."] +pub mod events_txptrupd; +#[doc = "PUBLISH_RXPTRUPD (rw) register accessor: an alias for `Reg`"] +pub type PUBLISH_RXPTRUPD = crate::Reg; +#[doc = "Publish configuration for event RXPTRUPD"] +pub mod publish_rxptrupd; +#[doc = "PUBLISH_STOPPED (rw) register accessor: an alias for `Reg`"] +pub type PUBLISH_STOPPED = crate::Reg; +#[doc = "Publish configuration for event STOPPED"] +pub mod publish_stopped; +#[doc = "PUBLISH_TXPTRUPD (rw) register accessor: an alias for `Reg`"] +pub type PUBLISH_TXPTRUPD = crate::Reg; +#[doc = "Publish configuration for event TXPTRUPD"] +pub mod publish_txptrupd; +#[doc = "INTEN (rw) register accessor: an alias for `Reg`"] +pub type INTEN = crate::Reg; +#[doc = "Enable or disable interrupt"] +pub mod inten; +#[doc = "INTENSET (rw) register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "Enable interrupt"] +pub mod intenset; +#[doc = "INTENCLR (rw) register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "Disable interrupt"] +pub mod intenclr; +#[doc = "ENABLE (rw) register accessor: an alias for `Reg`"] +pub type ENABLE = crate::Reg; +#[doc = "Enable I2S module."] +pub mod enable; +#[doc = "Unspecified"] +pub use config::CONFIG; +#[doc = r"Cluster"] +#[doc = "Unspecified"] +pub mod config; +#[doc = "Unspecified"] +pub use rxd::RXD; +#[doc = r"Cluster"] +#[doc = "Unspecified"] +pub mod rxd; +#[doc = "Unspecified"] +pub use txd::TXD; +#[doc = r"Cluster"] +#[doc = "Unspecified"] +pub mod txd; +#[doc = "Unspecified"] +pub use rxtxd::RXTXD; +#[doc = r"Cluster"] +#[doc = "Unspecified"] +pub mod rxtxd; +#[doc = "Unspecified"] +pub use psel::PSEL; +#[doc = r"Cluster"] +#[doc = "Unspecified"] +pub mod psel; diff --git a/pacs/nrf9120-pac/src/i2s_ns/config.rs b/pacs/nrf9120-pac/src/i2s_ns/config.rs new file mode 100644 index 00000000..38d9d519 --- /dev/null +++ b/pacs/nrf9120-pac/src/i2s_ns/config.rs @@ -0,0 +1,64 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct CONFIG { + #[doc = "0x00 - I2S mode."] + pub mode: MODE, + #[doc = "0x04 - Reception (RX) enable."] + pub rxen: RXEN, + #[doc = "0x08 - Transmission (TX) enable."] + pub txen: TXEN, + #[doc = "0x0c - Master clock generator enable."] + pub mcken: MCKEN, + #[doc = "0x10 - Master clock generator frequency."] + pub mckfreq: MCKFREQ, + #[doc = "0x14 - MCK / LRCK ratio."] + pub ratio: RATIO, + #[doc = "0x18 - Sample width."] + pub swidth: SWIDTH, + #[doc = "0x1c - Alignment of sample within a frame."] + pub align: ALIGN, + #[doc = "0x20 - Frame format."] + pub format: FORMAT, + #[doc = "0x24 - Enable channels."] + pub channels: CHANNELS, +} +#[doc = "MODE (rw) register accessor: an alias for `Reg`"] +pub type MODE = crate::Reg; +#[doc = "I2S mode."] +pub mod mode; +#[doc = "RXEN (rw) register accessor: an alias for `Reg`"] +pub type RXEN = crate::Reg; +#[doc = "Reception (RX) enable."] +pub mod rxen; +#[doc = "TXEN (rw) register accessor: an alias for `Reg`"] +pub type TXEN = crate::Reg; +#[doc = "Transmission (TX) enable."] +pub mod txen; +#[doc = "MCKEN (rw) register accessor: an alias for `Reg`"] +pub type MCKEN = crate::Reg; +#[doc = "Master clock generator enable."] +pub mod mcken; +#[doc = "MCKFREQ (rw) register accessor: an alias for `Reg`"] +pub type MCKFREQ = crate::Reg; +#[doc = "Master clock generator frequency."] +pub mod mckfreq; +#[doc = "RATIO (rw) register accessor: an alias for `Reg`"] +pub type RATIO = crate::Reg; +#[doc = "MCK / LRCK ratio."] +pub mod ratio; +#[doc = "SWIDTH (rw) register accessor: an alias for `Reg`"] +pub type SWIDTH = crate::Reg; +#[doc = "Sample width."] +pub mod swidth; +#[doc = "ALIGN (rw) register accessor: an alias for `Reg`"] +pub type ALIGN = crate::Reg; +#[doc = "Alignment of sample within a frame."] +pub mod align; +#[doc = "FORMAT (rw) register accessor: an alias for `Reg`"] +pub type FORMAT = crate::Reg; +#[doc = "Frame format."] +pub mod format; +#[doc = "CHANNELS (rw) register accessor: an alias for `Reg`"] +pub type CHANNELS = crate::Reg; +#[doc = "Enable channels."] +pub mod channels; diff --git a/pacs/nrf9120-pac/src/i2s_ns/config/align.rs b/pacs/nrf9120-pac/src/i2s_ns/config/align.rs new file mode 100644 index 00000000..d4e4d417 --- /dev/null +++ b/pacs/nrf9120-pac/src/i2s_ns/config/align.rs @@ -0,0 +1,126 @@ +#[doc = "Register `ALIGN` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `ALIGN` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ALIGN` reader - Alignment of sample within a frame."] +pub type ALIGN_R = crate::BitReader; +#[doc = "Alignment of sample within a frame.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum ALIGN_A { + #[doc = "0: Left-aligned."] + LEFT = 0, + #[doc = "1: Right-aligned."] + RIGHT = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: ALIGN_A) -> Self { + variant as u8 != 0 + } +} +impl ALIGN_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> ALIGN_A { + match self.bits { + false => ALIGN_A::LEFT, + true => ALIGN_A::RIGHT, + } + } + #[doc = "Checks if the value of the field is `LEFT`"] + #[inline(always)] + pub fn is_left(&self) -> bool { + *self == ALIGN_A::LEFT + } + #[doc = "Checks if the value of the field is `RIGHT`"] + #[inline(always)] + pub fn is_right(&self) -> bool { + *self == ALIGN_A::RIGHT + } +} +#[doc = "Field `ALIGN` writer - Alignment of sample within a frame."] +pub type ALIGN_W<'a, const O: u8> = crate::BitWriter<'a, u32, ALIGN_SPEC, ALIGN_A, O>; +impl<'a, const O: u8> ALIGN_W<'a, O> { + #[doc = "Left-aligned."] + #[inline(always)] + pub fn left(self) -> &'a mut W { + self.variant(ALIGN_A::LEFT) + } + #[doc = "Right-aligned."] + #[inline(always)] + pub fn right(self) -> &'a mut W { + self.variant(ALIGN_A::RIGHT) + } +} +impl R { + #[doc = "Bit 0 - Alignment of sample within a frame."] + #[inline(always)] + pub fn align(&self) -> ALIGN_R { + ALIGN_R::new((self.bits & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Alignment of sample within a frame."] + #[inline(always)] + pub fn align(&mut self) -> ALIGN_W<0> { + ALIGN_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Alignment of sample within a frame.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [align](index.html) module"] +pub struct ALIGN_SPEC; +impl crate::RegisterSpec for ALIGN_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [align::R](R) reader structure"] +impl crate::Readable for ALIGN_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [align::W](W) writer structure"] +impl crate::Writable for ALIGN_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets ALIGN to value 0"] +impl crate::Resettable for ALIGN_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/i2s_ns/config/channels.rs b/pacs/nrf9120-pac/src/i2s_ns/config/channels.rs new file mode 100644 index 00000000..750658dd --- /dev/null +++ b/pacs/nrf9120-pac/src/i2s_ns/config/channels.rs @@ -0,0 +1,142 @@ +#[doc = "Register `CHANNELS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CHANNELS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CHANNELS` reader - Enable channels."] +pub type CHANNELS_R = crate::FieldReader; +#[doc = "Enable channels.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CHANNELS_A { + #[doc = "0: Stereo."] + STEREO = 0, + #[doc = "1: Left only."] + LEFT = 1, + #[doc = "2: Right only."] + RIGHT = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CHANNELS_A) -> Self { + variant as _ + } +} +impl CHANNELS_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(CHANNELS_A::STEREO), + 1 => Some(CHANNELS_A::LEFT), + 2 => Some(CHANNELS_A::RIGHT), + _ => None, + } + } + #[doc = "Checks if the value of the field is `STEREO`"] + #[inline(always)] + pub fn is_stereo(&self) -> bool { + *self == CHANNELS_A::STEREO + } + #[doc = "Checks if the value of the field is `LEFT`"] + #[inline(always)] + pub fn is_left(&self) -> bool { + *self == CHANNELS_A::LEFT + } + #[doc = "Checks if the value of the field is `RIGHT`"] + #[inline(always)] + pub fn is_right(&self) -> bool { + *self == CHANNELS_A::RIGHT + } +} +#[doc = "Field `CHANNELS` writer - Enable channels."] +pub type CHANNELS_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, CHANNELS_SPEC, u8, CHANNELS_A, 2, O>; +impl<'a, const O: u8> CHANNELS_W<'a, O> { + #[doc = "Stereo."] + #[inline(always)] + pub fn stereo(self) -> &'a mut W { + self.variant(CHANNELS_A::STEREO) + } + #[doc = "Left only."] + #[inline(always)] + pub fn left(self) -> &'a mut W { + self.variant(CHANNELS_A::LEFT) + } + #[doc = "Right only."] + #[inline(always)] + pub fn right(self) -> &'a mut W { + self.variant(CHANNELS_A::RIGHT) + } +} +impl R { + #[doc = "Bits 0:1 - Enable channels."] + #[inline(always)] + pub fn channels(&self) -> CHANNELS_R { + CHANNELS_R::new((self.bits & 3) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Enable channels."] + #[inline(always)] + pub fn channels(&mut self) -> CHANNELS_W<0> { + CHANNELS_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Enable channels.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [channels](index.html) module"] +pub struct CHANNELS_SPEC; +impl crate::RegisterSpec for CHANNELS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [channels::R](R) reader structure"] +impl crate::Readable for CHANNELS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [channels::W](W) writer structure"] +impl crate::Writable for CHANNELS_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CHANNELS to value 0"] +impl crate::Resettable for CHANNELS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/i2s_ns/config/format.rs b/pacs/nrf9120-pac/src/i2s_ns/config/format.rs new file mode 100644 index 00000000..b25d5a54 --- /dev/null +++ b/pacs/nrf9120-pac/src/i2s_ns/config/format.rs @@ -0,0 +1,126 @@ +#[doc = "Register `FORMAT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `FORMAT` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `FORMAT` reader - Frame format."] +pub type FORMAT_R = crate::BitReader; +#[doc = "Frame format.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum FORMAT_A { + #[doc = "0: Original I2S format."] + I2S = 0, + #[doc = "1: Alternate (left- or right-aligned) format."] + ALIGNED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: FORMAT_A) -> Self { + variant as u8 != 0 + } +} +impl FORMAT_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> FORMAT_A { + match self.bits { + false => FORMAT_A::I2S, + true => FORMAT_A::ALIGNED, + } + } + #[doc = "Checks if the value of the field is `I2S`"] + #[inline(always)] + pub fn is_i2s(&self) -> bool { + *self == FORMAT_A::I2S + } + #[doc = "Checks if the value of the field is `ALIGNED`"] + #[inline(always)] + pub fn is_aligned(&self) -> bool { + *self == FORMAT_A::ALIGNED + } +} +#[doc = "Field `FORMAT` writer - Frame format."] +pub type FORMAT_W<'a, const O: u8> = crate::BitWriter<'a, u32, FORMAT_SPEC, FORMAT_A, O>; +impl<'a, const O: u8> FORMAT_W<'a, O> { + #[doc = "Original I2S format."] + #[inline(always)] + pub fn i2s(self) -> &'a mut W { + self.variant(FORMAT_A::I2S) + } + #[doc = "Alternate (left- or right-aligned) format."] + #[inline(always)] + pub fn aligned(self) -> &'a mut W { + self.variant(FORMAT_A::ALIGNED) + } +} +impl R { + #[doc = "Bit 0 - Frame format."] + #[inline(always)] + pub fn format(&self) -> FORMAT_R { + FORMAT_R::new((self.bits & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Frame format."] + #[inline(always)] + pub fn format(&mut self) -> FORMAT_W<0> { + FORMAT_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Frame format.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [format](index.html) module"] +pub struct FORMAT_SPEC; +impl crate::RegisterSpec for FORMAT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [format::R](R) reader structure"] +impl crate::Readable for FORMAT_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [format::W](W) writer structure"] +impl crate::Writable for FORMAT_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets FORMAT to value 0"] +impl crate::Resettable for FORMAT_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/i2s_ns/config/mcken.rs b/pacs/nrf9120-pac/src/i2s_ns/config/mcken.rs new file mode 100644 index 00000000..6379005d --- /dev/null +++ b/pacs/nrf9120-pac/src/i2s_ns/config/mcken.rs @@ -0,0 +1,126 @@ +#[doc = "Register `MCKEN` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `MCKEN` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `MCKEN` reader - Master clock generator enable."] +pub type MCKEN_R = crate::BitReader; +#[doc = "Master clock generator enable.\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum MCKEN_A { + #[doc = "0: Master clock generator disabled and PSEL.MCK not connected(available as GPIO)."] + DISABLED = 0, + #[doc = "1: Master clock generator running and MCK output on PSEL.MCK."] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: MCKEN_A) -> Self { + variant as u8 != 0 + } +} +impl MCKEN_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> MCKEN_A { + match self.bits { + false => MCKEN_A::DISABLED, + true => MCKEN_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == MCKEN_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == MCKEN_A::ENABLED + } +} +#[doc = "Field `MCKEN` writer - Master clock generator enable."] +pub type MCKEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, MCKEN_SPEC, MCKEN_A, O>; +impl<'a, const O: u8> MCKEN_W<'a, O> { + #[doc = "Master clock generator disabled and PSEL.MCK not connected(available as GPIO)."] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(MCKEN_A::DISABLED) + } + #[doc = "Master clock generator running and MCK output on PSEL.MCK."] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(MCKEN_A::ENABLED) + } +} +impl R { + #[doc = "Bit 0 - Master clock generator enable."] + #[inline(always)] + pub fn mcken(&self) -> MCKEN_R { + MCKEN_R::new((self.bits & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Master clock generator enable."] + #[inline(always)] + pub fn mcken(&mut self) -> MCKEN_W<0> { + MCKEN_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Master clock generator enable.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [mcken](index.html) module"] +pub struct MCKEN_SPEC; +impl crate::RegisterSpec for MCKEN_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [mcken::R](R) reader structure"] +impl crate::Readable for MCKEN_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [mcken::W](W) writer structure"] +impl crate::Writable for MCKEN_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets MCKEN to value 0x01"] +impl crate::Resettable for MCKEN_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x01 + } +} diff --git a/pacs/nrf9120-pac/src/i2s_ns/config/mckfreq.rs b/pacs/nrf9120-pac/src/i2s_ns/config/mckfreq.rs new file mode 100644 index 00000000..e7bd7384 --- /dev/null +++ b/pacs/nrf9120-pac/src/i2s_ns/config/mckfreq.rs @@ -0,0 +1,272 @@ +#[doc = "Register `MCKFREQ` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `MCKFREQ` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `MCKFREQ` reader - Master clock generator frequency."] +pub type MCKFREQ_R = crate::FieldReader; +#[doc = "Master clock generator frequency.\n\nValue on reset: 536870912"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u32)] +pub enum MCKFREQ_A { + #[doc = "536870912: 32 MHz / 8 = 4.0 MHz"] + _32MDIV8 = 536870912, + #[doc = "402653184: 32 MHz / 10 = 3.2 MHz"] + _32MDIV10 = 402653184, + #[doc = "369098752: 32 MHz / 11 = 2.9090909 MHz"] + _32MDIV11 = 369098752, + #[doc = "285212672: 32 MHz / 15 = 2.1333333 MHz"] + _32MDIV15 = 285212672, + #[doc = "268435456: 32 MHz / 16 = 2.0 MHz"] + _32MDIV16 = 268435456, + #[doc = "201326592: 32 MHz / 21 = 1.5238095"] + _32MDIV21 = 201326592, + #[doc = "184549376: 32 MHz / 23 = 1.3913043 MHz"] + _32MDIV23 = 184549376, + #[doc = "142606336: 32 MHz / 30 = 1.0666667 MHz"] + _32MDIV30 = 142606336, + #[doc = "138412032: 32 MHz / 31 = 1.0322581 MHz"] + _32MDIV31 = 138412032, + #[doc = "134217728: 32 MHz / 32 = 1.0 MHz"] + _32MDIV32 = 134217728, + #[doc = "100663296: 32 MHz / 42 = 0.7619048 MHz"] + _32MDIV42 = 100663296, + #[doc = "68157440: 32 MHz / 63 = 0.5079365 MHz"] + _32MDIV63 = 68157440, + #[doc = "34340864: 32 MHz / 125 = 0.256 MHz"] + _32MDIV125 = 34340864, +} +impl From for u32 { + #[inline(always)] + fn from(variant: MCKFREQ_A) -> Self { + variant as _ + } +} +impl MCKFREQ_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 536870912 => Some(MCKFREQ_A::_32MDIV8), + 402653184 => Some(MCKFREQ_A::_32MDIV10), + 369098752 => Some(MCKFREQ_A::_32MDIV11), + 285212672 => Some(MCKFREQ_A::_32MDIV15), + 268435456 => Some(MCKFREQ_A::_32MDIV16), + 201326592 => Some(MCKFREQ_A::_32MDIV21), + 184549376 => Some(MCKFREQ_A::_32MDIV23), + 142606336 => Some(MCKFREQ_A::_32MDIV30), + 138412032 => Some(MCKFREQ_A::_32MDIV31), + 134217728 => Some(MCKFREQ_A::_32MDIV32), + 100663296 => Some(MCKFREQ_A::_32MDIV42), + 68157440 => Some(MCKFREQ_A::_32MDIV63), + 34340864 => Some(MCKFREQ_A::_32MDIV125), + _ => None, + } + } + #[doc = "Checks if the value of the field is `_32MDIV8`"] + #[inline(always)] + pub fn is_32mdiv8(&self) -> bool { + *self == MCKFREQ_A::_32MDIV8 + } + #[doc = "Checks if the value of the field is `_32MDIV10`"] + #[inline(always)] + pub fn is_32mdiv10(&self) -> bool { + *self == MCKFREQ_A::_32MDIV10 + } + #[doc = "Checks if the value of the field is `_32MDIV11`"] + #[inline(always)] + pub fn is_32mdiv11(&self) -> bool { + *self == MCKFREQ_A::_32MDIV11 + } + #[doc = "Checks if the value of the field is `_32MDIV15`"] + #[inline(always)] + pub fn is_32mdiv15(&self) -> bool { + *self == MCKFREQ_A::_32MDIV15 + } + #[doc = "Checks if the value of the field is `_32MDIV16`"] + #[inline(always)] + pub fn is_32mdiv16(&self) -> bool { + *self == MCKFREQ_A::_32MDIV16 + } + #[doc = "Checks if the value of the field is `_32MDIV21`"] + #[inline(always)] + pub fn is_32mdiv21(&self) -> bool { + *self == MCKFREQ_A::_32MDIV21 + } + #[doc = "Checks if the value of the field is `_32MDIV23`"] + #[inline(always)] + pub fn is_32mdiv23(&self) -> bool { + *self == MCKFREQ_A::_32MDIV23 + } + #[doc = "Checks if the value of the field is `_32MDIV30`"] + #[inline(always)] + pub fn is_32mdiv30(&self) -> bool { + *self == MCKFREQ_A::_32MDIV30 + } + #[doc = "Checks if the value of the field is `_32MDIV31`"] + #[inline(always)] + pub fn is_32mdiv31(&self) -> bool { + *self == MCKFREQ_A::_32MDIV31 + } + #[doc = "Checks if the value of the field is `_32MDIV32`"] + #[inline(always)] + pub fn is_32mdiv32(&self) -> bool { + *self == MCKFREQ_A::_32MDIV32 + } + #[doc = "Checks if the value of the field is `_32MDIV42`"] + #[inline(always)] + pub fn is_32mdiv42(&self) -> bool { + *self == MCKFREQ_A::_32MDIV42 + } + #[doc = "Checks if the value of the field is `_32MDIV63`"] + #[inline(always)] + pub fn is_32mdiv63(&self) -> bool { + *self == MCKFREQ_A::_32MDIV63 + } + #[doc = "Checks if the value of the field is `_32MDIV125`"] + #[inline(always)] + pub fn is_32mdiv125(&self) -> bool { + *self == MCKFREQ_A::_32MDIV125 + } +} +#[doc = "Field `MCKFREQ` writer - Master clock generator frequency."] +pub type MCKFREQ_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, MCKFREQ_SPEC, u32, MCKFREQ_A, 32, O>; +impl<'a, const O: u8> MCKFREQ_W<'a, O> { + #[doc = "32 MHz / 8 = 4.0 MHz"] + #[inline(always)] + pub fn _32mdiv8(self) -> &'a mut W { + self.variant(MCKFREQ_A::_32MDIV8) + } + #[doc = "32 MHz / 10 = 3.2 MHz"] + #[inline(always)] + pub fn _32mdiv10(self) -> &'a mut W { + self.variant(MCKFREQ_A::_32MDIV10) + } + #[doc = "32 MHz / 11 = 2.9090909 MHz"] + #[inline(always)] + pub fn _32mdiv11(self) -> &'a mut W { + self.variant(MCKFREQ_A::_32MDIV11) + } + #[doc = "32 MHz / 15 = 2.1333333 MHz"] + #[inline(always)] + pub fn _32mdiv15(self) -> &'a mut W { + self.variant(MCKFREQ_A::_32MDIV15) + } + #[doc = "32 MHz / 16 = 2.0 MHz"] + #[inline(always)] + pub fn _32mdiv16(self) -> &'a mut W { + self.variant(MCKFREQ_A::_32MDIV16) + } + #[doc = "32 MHz / 21 = 1.5238095"] + #[inline(always)] + pub fn _32mdiv21(self) -> &'a mut W { + self.variant(MCKFREQ_A::_32MDIV21) + } + #[doc = "32 MHz / 23 = 1.3913043 MHz"] + #[inline(always)] + pub fn _32mdiv23(self) -> &'a mut W { + self.variant(MCKFREQ_A::_32MDIV23) + } + #[doc = "32 MHz / 30 = 1.0666667 MHz"] + #[inline(always)] + pub fn _32mdiv30(self) -> &'a mut W { + self.variant(MCKFREQ_A::_32MDIV30) + } + #[doc = "32 MHz / 31 = 1.0322581 MHz"] + #[inline(always)] + pub fn _32mdiv31(self) -> &'a mut W { + self.variant(MCKFREQ_A::_32MDIV31) + } + #[doc = "32 MHz / 32 = 1.0 MHz"] + #[inline(always)] + pub fn _32mdiv32(self) -> &'a mut W { + self.variant(MCKFREQ_A::_32MDIV32) + } + #[doc = "32 MHz / 42 = 0.7619048 MHz"] + #[inline(always)] + pub fn _32mdiv42(self) -> &'a mut W { + self.variant(MCKFREQ_A::_32MDIV42) + } + #[doc = "32 MHz / 63 = 0.5079365 MHz"] + #[inline(always)] + pub fn _32mdiv63(self) -> &'a mut W { + self.variant(MCKFREQ_A::_32MDIV63) + } + #[doc = "32 MHz / 125 = 0.256 MHz"] + #[inline(always)] + pub fn _32mdiv125(self) -> &'a mut W { + self.variant(MCKFREQ_A::_32MDIV125) + } +} +impl R { + #[doc = "Bits 0:31 - Master clock generator frequency."] + #[inline(always)] + pub fn mckfreq(&self) -> MCKFREQ_R { + MCKFREQ_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Master clock generator frequency."] + #[inline(always)] + pub fn mckfreq(&mut self) -> MCKFREQ_W<0> { + MCKFREQ_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Master clock generator frequency.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [mckfreq](index.html) module"] +pub struct MCKFREQ_SPEC; +impl crate::RegisterSpec for MCKFREQ_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [mckfreq::R](R) reader structure"] +impl crate::Readable for MCKFREQ_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [mckfreq::W](W) writer structure"] +impl crate::Writable for MCKFREQ_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets MCKFREQ to value 0x2000_0000"] +impl crate::Resettable for MCKFREQ_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x2000_0000 + } +} diff --git a/pacs/nrf9120-pac/src/i2s_ns/config/mode.rs b/pacs/nrf9120-pac/src/i2s_ns/config/mode.rs new file mode 100644 index 00000000..19b3df52 --- /dev/null +++ b/pacs/nrf9120-pac/src/i2s_ns/config/mode.rs @@ -0,0 +1,126 @@ +#[doc = "Register `MODE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `MODE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `MODE` reader - I2S mode."] +pub type MODE_R = crate::BitReader; +#[doc = "I2S mode.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum MODE_A { + #[doc = "0: Master mode. SCK and LRCK generated from internal master clcok (MCK) and output on pins defined by PSEL.xxx."] + MASTER = 0, + #[doc = "1: Slave mode. SCK and LRCK generated by external master and received on pins defined by PSEL.xxx"] + SLAVE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: MODE_A) -> Self { + variant as u8 != 0 + } +} +impl MODE_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> MODE_A { + match self.bits { + false => MODE_A::MASTER, + true => MODE_A::SLAVE, + } + } + #[doc = "Checks if the value of the field is `MASTER`"] + #[inline(always)] + pub fn is_master(&self) -> bool { + *self == MODE_A::MASTER + } + #[doc = "Checks if the value of the field is `SLAVE`"] + #[inline(always)] + pub fn is_slave(&self) -> bool { + *self == MODE_A::SLAVE + } +} +#[doc = "Field `MODE` writer - I2S mode."] +pub type MODE_W<'a, const O: u8> = crate::BitWriter<'a, u32, MODE_SPEC, MODE_A, O>; +impl<'a, const O: u8> MODE_W<'a, O> { + #[doc = "Master mode. SCK and LRCK generated from internal master clcok (MCK) and output on pins defined by PSEL.xxx."] + #[inline(always)] + pub fn master(self) -> &'a mut W { + self.variant(MODE_A::MASTER) + } + #[doc = "Slave mode. SCK and LRCK generated by external master and received on pins defined by PSEL.xxx"] + #[inline(always)] + pub fn slave(self) -> &'a mut W { + self.variant(MODE_A::SLAVE) + } +} +impl R { + #[doc = "Bit 0 - I2S mode."] + #[inline(always)] + pub fn mode(&self) -> MODE_R { + MODE_R::new((self.bits & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - I2S mode."] + #[inline(always)] + pub fn mode(&mut self) -> MODE_W<0> { + MODE_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "I2S mode.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [mode](index.html) module"] +pub struct MODE_SPEC; +impl crate::RegisterSpec for MODE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [mode::R](R) reader structure"] +impl crate::Readable for MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [mode::W](W) writer structure"] +impl crate::Writable for MODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets MODE to value 0"] +impl crate::Resettable for MODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/i2s_ns/config/ratio.rs b/pacs/nrf9120-pac/src/i2s_ns/config/ratio.rs new file mode 100644 index 00000000..baa8fe29 --- /dev/null +++ b/pacs/nrf9120-pac/src/i2s_ns/config/ratio.rs @@ -0,0 +1,219 @@ +#[doc = "Register `RATIO` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `RATIO` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `RATIO` reader - MCK / LRCK ratio."] +pub type RATIO_R = crate::FieldReader; +#[doc = "MCK / LRCK ratio.\n\nValue on reset: 6"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum RATIO_A { + #[doc = "0: LRCK = MCK / 32"] + _32X = 0, + #[doc = "1: LRCK = MCK / 48"] + _48X = 1, + #[doc = "2: LRCK = MCK / 64"] + _64X = 2, + #[doc = "3: LRCK = MCK / 96"] + _96X = 3, + #[doc = "4: LRCK = MCK / 128"] + _128X = 4, + #[doc = "5: LRCK = MCK / 192"] + _192X = 5, + #[doc = "6: LRCK = MCK / 256"] + _256X = 6, + #[doc = "7: LRCK = MCK / 384"] + _384X = 7, + #[doc = "8: LRCK = MCK / 512"] + _512X = 8, +} +impl From for u8 { + #[inline(always)] + fn from(variant: RATIO_A) -> Self { + variant as _ + } +} +impl RATIO_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(RATIO_A::_32X), + 1 => Some(RATIO_A::_48X), + 2 => Some(RATIO_A::_64X), + 3 => Some(RATIO_A::_96X), + 4 => Some(RATIO_A::_128X), + 5 => Some(RATIO_A::_192X), + 6 => Some(RATIO_A::_256X), + 7 => Some(RATIO_A::_384X), + 8 => Some(RATIO_A::_512X), + _ => None, + } + } + #[doc = "Checks if the value of the field is `_32X`"] + #[inline(always)] + pub fn is_32x(&self) -> bool { + *self == RATIO_A::_32X + } + #[doc = "Checks if the value of the field is `_48X`"] + #[inline(always)] + pub fn is_48x(&self) -> bool { + *self == RATIO_A::_48X + } + #[doc = "Checks if the value of the field is `_64X`"] + #[inline(always)] + pub fn is_64x(&self) -> bool { + *self == RATIO_A::_64X + } + #[doc = "Checks if the value of the field is `_96X`"] + #[inline(always)] + pub fn is_96x(&self) -> bool { + *self == RATIO_A::_96X + } + #[doc = "Checks if the value of the field is `_128X`"] + #[inline(always)] + pub fn is_128x(&self) -> bool { + *self == RATIO_A::_128X + } + #[doc = "Checks if the value of the field is `_192X`"] + #[inline(always)] + pub fn is_192x(&self) -> bool { + *self == RATIO_A::_192X + } + #[doc = "Checks if the value of the field is `_256X`"] + #[inline(always)] + pub fn is_256x(&self) -> bool { + *self == RATIO_A::_256X + } + #[doc = "Checks if the value of the field is `_384X`"] + #[inline(always)] + pub fn is_384x(&self) -> bool { + *self == RATIO_A::_384X + } + #[doc = "Checks if the value of the field is `_512X`"] + #[inline(always)] + pub fn is_512x(&self) -> bool { + *self == RATIO_A::_512X + } +} +#[doc = "Field `RATIO` writer - MCK / LRCK ratio."] +pub type RATIO_W<'a, const O: u8> = crate::FieldWriter<'a, u32, RATIO_SPEC, u8, RATIO_A, 4, O>; +impl<'a, const O: u8> RATIO_W<'a, O> { + #[doc = "LRCK = MCK / 32"] + #[inline(always)] + pub fn _32x(self) -> &'a mut W { + self.variant(RATIO_A::_32X) + } + #[doc = "LRCK = MCK / 48"] + #[inline(always)] + pub fn _48x(self) -> &'a mut W { + self.variant(RATIO_A::_48X) + } + #[doc = "LRCK = MCK / 64"] + #[inline(always)] + pub fn _64x(self) -> &'a mut W { + self.variant(RATIO_A::_64X) + } + #[doc = "LRCK = MCK / 96"] + #[inline(always)] + pub fn _96x(self) -> &'a mut W { + self.variant(RATIO_A::_96X) + } + #[doc = "LRCK = MCK / 128"] + #[inline(always)] + pub fn _128x(self) -> &'a mut W { + self.variant(RATIO_A::_128X) + } + #[doc = "LRCK = MCK / 192"] + #[inline(always)] + pub fn _192x(self) -> &'a mut W { + self.variant(RATIO_A::_192X) + } + #[doc = "LRCK = MCK / 256"] + #[inline(always)] + pub fn _256x(self) -> &'a mut W { + self.variant(RATIO_A::_256X) + } + #[doc = "LRCK = MCK / 384"] + #[inline(always)] + pub fn _384x(self) -> &'a mut W { + self.variant(RATIO_A::_384X) + } + #[doc = "LRCK = MCK / 512"] + #[inline(always)] + pub fn _512x(self) -> &'a mut W { + self.variant(RATIO_A::_512X) + } +} +impl R { + #[doc = "Bits 0:3 - MCK / LRCK ratio."] + #[inline(always)] + pub fn ratio(&self) -> RATIO_R { + RATIO_R::new((self.bits & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - MCK / LRCK ratio."] + #[inline(always)] + pub fn ratio(&mut self) -> RATIO_W<0> { + RATIO_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MCK / LRCK ratio.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ratio](index.html) module"] +pub struct RATIO_SPEC; +impl crate::RegisterSpec for RATIO_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ratio::R](R) reader structure"] +impl crate::Readable for RATIO_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ratio::W](W) writer structure"] +impl crate::Writable for RATIO_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets RATIO to value 0x06"] +impl crate::Resettable for RATIO_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x06 + } +} diff --git a/pacs/nrf9120-pac/src/i2s_ns/config/rxen.rs b/pacs/nrf9120-pac/src/i2s_ns/config/rxen.rs new file mode 100644 index 00000000..2e4cf1e7 --- /dev/null +++ b/pacs/nrf9120-pac/src/i2s_ns/config/rxen.rs @@ -0,0 +1,126 @@ +#[doc = "Register `RXEN` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `RXEN` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `RXEN` reader - Reception (RX) enable."] +pub type RXEN_R = crate::BitReader; +#[doc = "Reception (RX) enable.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RXEN_A { + #[doc = "0: Reception disabled and now data will be written to the RXD.PTR address."] + DISABLED = 0, + #[doc = "1: Reception enabled."] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RXEN_A) -> Self { + variant as u8 != 0 + } +} +impl RXEN_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RXEN_A { + match self.bits { + false => RXEN_A::DISABLED, + true => RXEN_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == RXEN_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == RXEN_A::ENABLED + } +} +#[doc = "Field `RXEN` writer - Reception (RX) enable."] +pub type RXEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, RXEN_SPEC, RXEN_A, O>; +impl<'a, const O: u8> RXEN_W<'a, O> { + #[doc = "Reception disabled and now data will be written to the RXD.PTR address."] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(RXEN_A::DISABLED) + } + #[doc = "Reception enabled."] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(RXEN_A::ENABLED) + } +} +impl R { + #[doc = "Bit 0 - Reception (RX) enable."] + #[inline(always)] + pub fn rxen(&self) -> RXEN_R { + RXEN_R::new((self.bits & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Reception (RX) enable."] + #[inline(always)] + pub fn rxen(&mut self) -> RXEN_W<0> { + RXEN_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Reception (RX) enable.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rxen](index.html) module"] +pub struct RXEN_SPEC; +impl crate::RegisterSpec for RXEN_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [rxen::R](R) reader structure"] +impl crate::Readable for RXEN_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [rxen::W](W) writer structure"] +impl crate::Writable for RXEN_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets RXEN to value 0"] +impl crate::Resettable for RXEN_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/i2s_ns/config/swidth.rs b/pacs/nrf9120-pac/src/i2s_ns/config/swidth.rs new file mode 100644 index 00000000..48998ff8 --- /dev/null +++ b/pacs/nrf9120-pac/src/i2s_ns/config/swidth.rs @@ -0,0 +1,141 @@ +#[doc = "Register `SWIDTH` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SWIDTH` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWIDTH` reader - Sample width."] +pub type SWIDTH_R = crate::FieldReader; +#[doc = "Sample width.\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SWIDTH_A { + #[doc = "0: 8 bit."] + _8BIT = 0, + #[doc = "1: 16 bit."] + _16BIT = 1, + #[doc = "2: 24 bit."] + _24BIT = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SWIDTH_A) -> Self { + variant as _ + } +} +impl SWIDTH_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SWIDTH_A::_8BIT), + 1 => Some(SWIDTH_A::_16BIT), + 2 => Some(SWIDTH_A::_24BIT), + _ => None, + } + } + #[doc = "Checks if the value of the field is `_8BIT`"] + #[inline(always)] + pub fn is_8bit(&self) -> bool { + *self == SWIDTH_A::_8BIT + } + #[doc = "Checks if the value of the field is `_16BIT`"] + #[inline(always)] + pub fn is_16bit(&self) -> bool { + *self == SWIDTH_A::_16BIT + } + #[doc = "Checks if the value of the field is `_24BIT`"] + #[inline(always)] + pub fn is_24bit(&self) -> bool { + *self == SWIDTH_A::_24BIT + } +} +#[doc = "Field `SWIDTH` writer - Sample width."] +pub type SWIDTH_W<'a, const O: u8> = crate::FieldWriter<'a, u32, SWIDTH_SPEC, u8, SWIDTH_A, 2, O>; +impl<'a, const O: u8> SWIDTH_W<'a, O> { + #[doc = "8 bit."] + #[inline(always)] + pub fn _8bit(self) -> &'a mut W { + self.variant(SWIDTH_A::_8BIT) + } + #[doc = "16 bit."] + #[inline(always)] + pub fn _16bit(self) -> &'a mut W { + self.variant(SWIDTH_A::_16BIT) + } + #[doc = "24 bit."] + #[inline(always)] + pub fn _24bit(self) -> &'a mut W { + self.variant(SWIDTH_A::_24BIT) + } +} +impl R { + #[doc = "Bits 0:1 - Sample width."] + #[inline(always)] + pub fn swidth(&self) -> SWIDTH_R { + SWIDTH_R::new((self.bits & 3) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Sample width."] + #[inline(always)] + pub fn swidth(&mut self) -> SWIDTH_W<0> { + SWIDTH_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Sample width.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [swidth](index.html) module"] +pub struct SWIDTH_SPEC; +impl crate::RegisterSpec for SWIDTH_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [swidth::R](R) reader structure"] +impl crate::Readable for SWIDTH_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [swidth::W](W) writer structure"] +impl crate::Writable for SWIDTH_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SWIDTH to value 0x01"] +impl crate::Resettable for SWIDTH_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x01 + } +} diff --git a/pacs/nrf9120-pac/src/i2s_ns/config/txen.rs b/pacs/nrf9120-pac/src/i2s_ns/config/txen.rs new file mode 100644 index 00000000..58a469d6 --- /dev/null +++ b/pacs/nrf9120-pac/src/i2s_ns/config/txen.rs @@ -0,0 +1,126 @@ +#[doc = "Register `TXEN` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `TXEN` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `TXEN` reader - Transmission (TX) enable."] +pub type TXEN_R = crate::BitReader; +#[doc = "Transmission (TX) enable.\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum TXEN_A { + #[doc = "0: Transmission disabled and now data will be read from the RXD.TXD address."] + DISABLED = 0, + #[doc = "1: Transmission enabled."] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TXEN_A) -> Self { + variant as u8 != 0 + } +} +impl TXEN_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> TXEN_A { + match self.bits { + false => TXEN_A::DISABLED, + true => TXEN_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == TXEN_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == TXEN_A::ENABLED + } +} +#[doc = "Field `TXEN` writer - Transmission (TX) enable."] +pub type TXEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, TXEN_SPEC, TXEN_A, O>; +impl<'a, const O: u8> TXEN_W<'a, O> { + #[doc = "Transmission disabled and now data will be read from the RXD.TXD address."] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(TXEN_A::DISABLED) + } + #[doc = "Transmission enabled."] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(TXEN_A::ENABLED) + } +} +impl R { + #[doc = "Bit 0 - Transmission (TX) enable."] + #[inline(always)] + pub fn txen(&self) -> TXEN_R { + TXEN_R::new((self.bits & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Transmission (TX) enable."] + #[inline(always)] + pub fn txen(&mut self) -> TXEN_W<0> { + TXEN_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Transmission (TX) enable.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [txen](index.html) module"] +pub struct TXEN_SPEC; +impl crate::RegisterSpec for TXEN_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [txen::R](R) reader structure"] +impl crate::Readable for TXEN_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [txen::W](W) writer structure"] +impl crate::Writable for TXEN_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets TXEN to value 0x01"] +impl crate::Resettable for TXEN_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x01 + } +} diff --git a/pacs/nrf9120-pac/src/i2s_ns/enable.rs b/pacs/nrf9120-pac/src/i2s_ns/enable.rs new file mode 100644 index 00000000..3257da49 --- /dev/null +++ b/pacs/nrf9120-pac/src/i2s_ns/enable.rs @@ -0,0 +1,126 @@ +#[doc = "Register `ENABLE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `ENABLE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ENABLE` reader - Enable I2S module."] +pub type ENABLE_R = crate::BitReader; +#[doc = "Enable I2S module.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum ENABLE_A { + #[doc = "0: Disable"] + DISABLED = 0, + #[doc = "1: Enable"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: ENABLE_A) -> Self { + variant as u8 != 0 + } +} +impl ENABLE_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> ENABLE_A { + match self.bits { + false => ENABLE_A::DISABLED, + true => ENABLE_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == ENABLE_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == ENABLE_A::ENABLED + } +} +#[doc = "Field `ENABLE` writer - Enable I2S module."] +pub type ENABLE_W<'a, const O: u8> = crate::BitWriter<'a, u32, ENABLE_SPEC, ENABLE_A, O>; +impl<'a, const O: u8> ENABLE_W<'a, O> { + #[doc = "Disable"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(ENABLE_A::DISABLED) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(ENABLE_A::ENABLED) + } +} +impl R { + #[doc = "Bit 0 - Enable I2S module."] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new((self.bits & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Enable I2S module."] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W<0> { + ENABLE_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Enable I2S module.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [enable](index.html) module"] +pub struct ENABLE_SPEC; +impl crate::RegisterSpec for ENABLE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [enable::R](R) reader structure"] +impl crate::Readable for ENABLE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [enable::W](W) writer structure"] +impl crate::Writable for ENABLE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets ENABLE to value 0"] +impl crate::Resettable for ENABLE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/i2s_ns/events_rxptrupd.rs b/pacs/nrf9120-pac/src/i2s_ns/events_rxptrupd.rs new file mode 100644 index 00000000..5c7fe675 --- /dev/null +++ b/pacs/nrf9120-pac/src/i2s_ns/events_rxptrupd.rs @@ -0,0 +1,127 @@ +#[doc = "Register `EVENTS_RXPTRUPD` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVENTS_RXPTRUPD` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `EVENTS_RXPTRUPD` reader - The RXD.PTR register has been copied to internal double-buffers. When the I2S module is started and RX is enabled, this event will be generated for every RXTXD.MAXCNT words that are received on the SDIN pin."] +pub type EVENTS_RXPTRUPD_R = crate::BitReader; +#[doc = "The RXD.PTR register has been copied to internal double-buffers. When the I2S module is started and RX is enabled, this event will be generated for every RXTXD.MAXCNT words that are received on the SDIN pin.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum EVENTS_RXPTRUPD_A { + #[doc = "0: Event not generated"] + NOT_GENERATED = 0, + #[doc = "1: Event generated"] + GENERATED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: EVENTS_RXPTRUPD_A) -> Self { + variant as u8 != 0 + } +} +impl EVENTS_RXPTRUPD_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EVENTS_RXPTRUPD_A { + match self.bits { + false => EVENTS_RXPTRUPD_A::NOT_GENERATED, + true => EVENTS_RXPTRUPD_A::GENERATED, + } + } + #[doc = "Checks if the value of the field is `NOT_GENERATED`"] + #[inline(always)] + pub fn is_not_generated(&self) -> bool { + *self == EVENTS_RXPTRUPD_A::NOT_GENERATED + } + #[doc = "Checks if the value of the field is `GENERATED`"] + #[inline(always)] + pub fn is_generated(&self) -> bool { + *self == EVENTS_RXPTRUPD_A::GENERATED + } +} +#[doc = "Field `EVENTS_RXPTRUPD` writer - The RXD.PTR register has been copied to internal double-buffers. When the I2S module is started and RX is enabled, this event will be generated for every RXTXD.MAXCNT words that are received on the SDIN pin."] +pub type EVENTS_RXPTRUPD_W<'a, const O: u8> = + crate::BitWriter<'a, u32, EVENTS_RXPTRUPD_SPEC, EVENTS_RXPTRUPD_A, O>; +impl<'a, const O: u8> EVENTS_RXPTRUPD_W<'a, O> { + #[doc = "Event not generated"] + #[inline(always)] + pub fn not_generated(self) -> &'a mut W { + self.variant(EVENTS_RXPTRUPD_A::NOT_GENERATED) + } + #[doc = "Event generated"] + #[inline(always)] + pub fn generated(self) -> &'a mut W { + self.variant(EVENTS_RXPTRUPD_A::GENERATED) + } +} +impl R { + #[doc = "Bit 0 - The RXD.PTR register has been copied to internal double-buffers. When the I2S module is started and RX is enabled, this event will be generated for every RXTXD.MAXCNT words that are received on the SDIN pin."] + #[inline(always)] + pub fn events_rxptrupd(&self) -> EVENTS_RXPTRUPD_R { + EVENTS_RXPTRUPD_R::new((self.bits & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - The RXD.PTR register has been copied to internal double-buffers. When the I2S module is started and RX is enabled, this event will be generated for every RXTXD.MAXCNT words that are received on the SDIN pin."] + #[inline(always)] + pub fn events_rxptrupd(&mut self) -> EVENTS_RXPTRUPD_W<0> { + EVENTS_RXPTRUPD_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "The RXD.PTR register has been copied to internal double-buffers. When the I2S module is started and RX is enabled, this event will be generated for every RXTXD.MAXCNT words that are received on the SDIN pin.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [events_rxptrupd](index.html) module"] +pub struct EVENTS_RXPTRUPD_SPEC; +impl crate::RegisterSpec for EVENTS_RXPTRUPD_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [events_rxptrupd::R](R) reader structure"] +impl crate::Readable for EVENTS_RXPTRUPD_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [events_rxptrupd::W](W) writer structure"] +impl crate::Writable for EVENTS_RXPTRUPD_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EVENTS_RXPTRUPD to value 0"] +impl crate::Resettable for EVENTS_RXPTRUPD_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/i2s_ns/events_stopped.rs b/pacs/nrf9120-pac/src/i2s_ns/events_stopped.rs new file mode 100644 index 00000000..9f5e7038 --- /dev/null +++ b/pacs/nrf9120-pac/src/i2s_ns/events_stopped.rs @@ -0,0 +1,127 @@ +#[doc = "Register `EVENTS_STOPPED` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVENTS_STOPPED` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `EVENTS_STOPPED` reader - I2S transfer stopped."] +pub type EVENTS_STOPPED_R = crate::BitReader; +#[doc = "I2S transfer stopped.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum EVENTS_STOPPED_A { + #[doc = "0: Event not generated"] + NOT_GENERATED = 0, + #[doc = "1: Event generated"] + GENERATED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: EVENTS_STOPPED_A) -> Self { + variant as u8 != 0 + } +} +impl EVENTS_STOPPED_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EVENTS_STOPPED_A { + match self.bits { + false => EVENTS_STOPPED_A::NOT_GENERATED, + true => EVENTS_STOPPED_A::GENERATED, + } + } + #[doc = "Checks if the value of the field is `NOT_GENERATED`"] + #[inline(always)] + pub fn is_not_generated(&self) -> bool { + *self == EVENTS_STOPPED_A::NOT_GENERATED + } + #[doc = "Checks if the value of the field is `GENERATED`"] + #[inline(always)] + pub fn is_generated(&self) -> bool { + *self == EVENTS_STOPPED_A::GENERATED + } +} +#[doc = "Field `EVENTS_STOPPED` writer - I2S transfer stopped."] +pub type EVENTS_STOPPED_W<'a, const O: u8> = + crate::BitWriter<'a, u32, EVENTS_STOPPED_SPEC, EVENTS_STOPPED_A, O>; +impl<'a, const O: u8> EVENTS_STOPPED_W<'a, O> { + #[doc = "Event not generated"] + #[inline(always)] + pub fn not_generated(self) -> &'a mut W { + self.variant(EVENTS_STOPPED_A::NOT_GENERATED) + } + #[doc = "Event generated"] + #[inline(always)] + pub fn generated(self) -> &'a mut W { + self.variant(EVENTS_STOPPED_A::GENERATED) + } +} +impl R { + #[doc = "Bit 0 - I2S transfer stopped."] + #[inline(always)] + pub fn events_stopped(&self) -> EVENTS_STOPPED_R { + EVENTS_STOPPED_R::new((self.bits & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - I2S transfer stopped."] + #[inline(always)] + pub fn events_stopped(&mut self) -> EVENTS_STOPPED_W<0> { + EVENTS_STOPPED_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "I2S transfer stopped.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [events_stopped](index.html) module"] +pub struct EVENTS_STOPPED_SPEC; +impl crate::RegisterSpec for EVENTS_STOPPED_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [events_stopped::R](R) reader structure"] +impl crate::Readable for EVENTS_STOPPED_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [events_stopped::W](W) writer structure"] +impl crate::Writable for EVENTS_STOPPED_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EVENTS_STOPPED to value 0"] +impl crate::Resettable for EVENTS_STOPPED_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/i2s_ns/events_txptrupd.rs b/pacs/nrf9120-pac/src/i2s_ns/events_txptrupd.rs new file mode 100644 index 00000000..05197d4e --- /dev/null +++ b/pacs/nrf9120-pac/src/i2s_ns/events_txptrupd.rs @@ -0,0 +1,127 @@ +#[doc = "Register `EVENTS_TXPTRUPD` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVENTS_TXPTRUPD` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `EVENTS_TXPTRUPD` reader - The TDX.PTR register has been copied to internal double-buffers. When the I2S module is started and TX is enabled, this event will be generated for every RXTXD.MAXCNT words that are sent on the SDOUT pin."] +pub type EVENTS_TXPTRUPD_R = crate::BitReader; +#[doc = "The TDX.PTR register has been copied to internal double-buffers. When the I2S module is started and TX is enabled, this event will be generated for every RXTXD.MAXCNT words that are sent on the SDOUT pin.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum EVENTS_TXPTRUPD_A { + #[doc = "0: Event not generated"] + NOT_GENERATED = 0, + #[doc = "1: Event generated"] + GENERATED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: EVENTS_TXPTRUPD_A) -> Self { + variant as u8 != 0 + } +} +impl EVENTS_TXPTRUPD_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EVENTS_TXPTRUPD_A { + match self.bits { + false => EVENTS_TXPTRUPD_A::NOT_GENERATED, + true => EVENTS_TXPTRUPD_A::GENERATED, + } + } + #[doc = "Checks if the value of the field is `NOT_GENERATED`"] + #[inline(always)] + pub fn is_not_generated(&self) -> bool { + *self == EVENTS_TXPTRUPD_A::NOT_GENERATED + } + #[doc = "Checks if the value of the field is `GENERATED`"] + #[inline(always)] + pub fn is_generated(&self) -> bool { + *self == EVENTS_TXPTRUPD_A::GENERATED + } +} +#[doc = "Field `EVENTS_TXPTRUPD` writer - The TDX.PTR register has been copied to internal double-buffers. When the I2S module is started and TX is enabled, this event will be generated for every RXTXD.MAXCNT words that are sent on the SDOUT pin."] +pub type EVENTS_TXPTRUPD_W<'a, const O: u8> = + crate::BitWriter<'a, u32, EVENTS_TXPTRUPD_SPEC, EVENTS_TXPTRUPD_A, O>; +impl<'a, const O: u8> EVENTS_TXPTRUPD_W<'a, O> { + #[doc = "Event not generated"] + #[inline(always)] + pub fn not_generated(self) -> &'a mut W { + self.variant(EVENTS_TXPTRUPD_A::NOT_GENERATED) + } + #[doc = "Event generated"] + #[inline(always)] + pub fn generated(self) -> &'a mut W { + self.variant(EVENTS_TXPTRUPD_A::GENERATED) + } +} +impl R { + #[doc = "Bit 0 - The TDX.PTR register has been copied to internal double-buffers. When the I2S module is started and TX is enabled, this event will be generated for every RXTXD.MAXCNT words that are sent on the SDOUT pin."] + #[inline(always)] + pub fn events_txptrupd(&self) -> EVENTS_TXPTRUPD_R { + EVENTS_TXPTRUPD_R::new((self.bits & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - The TDX.PTR register has been copied to internal double-buffers. When the I2S module is started and TX is enabled, this event will be generated for every RXTXD.MAXCNT words that are sent on the SDOUT pin."] + #[inline(always)] + pub fn events_txptrupd(&mut self) -> EVENTS_TXPTRUPD_W<0> { + EVENTS_TXPTRUPD_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "The TDX.PTR register has been copied to internal double-buffers. When the I2S module is started and TX is enabled, this event will be generated for every RXTXD.MAXCNT words that are sent on the SDOUT pin.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [events_txptrupd](index.html) module"] +pub struct EVENTS_TXPTRUPD_SPEC; +impl crate::RegisterSpec for EVENTS_TXPTRUPD_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [events_txptrupd::R](R) reader structure"] +impl crate::Readable for EVENTS_TXPTRUPD_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [events_txptrupd::W](W) writer structure"] +impl crate::Writable for EVENTS_TXPTRUPD_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EVENTS_TXPTRUPD to value 0"] +impl crate::Resettable for EVENTS_TXPTRUPD_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/i2s_ns/inten.rs b/pacs/nrf9120-pac/src/i2s_ns/inten.rs new file mode 100644 index 00000000..ba92a6ea --- /dev/null +++ b/pacs/nrf9120-pac/src/i2s_ns/inten.rs @@ -0,0 +1,246 @@ +#[doc = "Register `INTEN` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTEN` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `RXPTRUPD` reader - Enable or disable interrupt for event RXPTRUPD"] +pub type RXPTRUPD_R = crate::BitReader; +#[doc = "Enable or disable interrupt for event RXPTRUPD\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RXPTRUPD_A { + #[doc = "0: Disable"] + DISABLED = 0, + #[doc = "1: Enable"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RXPTRUPD_A) -> Self { + variant as u8 != 0 + } +} +impl RXPTRUPD_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RXPTRUPD_A { + match self.bits { + false => RXPTRUPD_A::DISABLED, + true => RXPTRUPD_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == RXPTRUPD_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == RXPTRUPD_A::ENABLED + } +} +#[doc = "Field `RXPTRUPD` writer - Enable or disable interrupt for event RXPTRUPD"] +pub type RXPTRUPD_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTEN_SPEC, RXPTRUPD_A, O>; +impl<'a, const O: u8> RXPTRUPD_W<'a, O> { + #[doc = "Disable"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(RXPTRUPD_A::DISABLED) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(RXPTRUPD_A::ENABLED) + } +} +#[doc = "Field `STOPPED` reader - Enable or disable interrupt for event STOPPED"] +pub type STOPPED_R = crate::BitReader; +#[doc = "Enable or disable interrupt for event STOPPED\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum STOPPED_A { + #[doc = "0: Disable"] + DISABLED = 0, + #[doc = "1: Enable"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: STOPPED_A) -> Self { + variant as u8 != 0 + } +} +impl STOPPED_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> STOPPED_A { + match self.bits { + false => STOPPED_A::DISABLED, + true => STOPPED_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == STOPPED_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == STOPPED_A::ENABLED + } +} +#[doc = "Field `STOPPED` writer - Enable or disable interrupt for event STOPPED"] +pub type STOPPED_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTEN_SPEC, STOPPED_A, O>; +impl<'a, const O: u8> STOPPED_W<'a, O> { + #[doc = "Disable"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(STOPPED_A::DISABLED) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(STOPPED_A::ENABLED) + } +} +#[doc = "Field `TXPTRUPD` reader - Enable or disable interrupt for event TXPTRUPD"] +pub type TXPTRUPD_R = crate::BitReader; +#[doc = "Enable or disable interrupt for event TXPTRUPD\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum TXPTRUPD_A { + #[doc = "0: Disable"] + DISABLED = 0, + #[doc = "1: Enable"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TXPTRUPD_A) -> Self { + variant as u8 != 0 + } +} +impl TXPTRUPD_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> TXPTRUPD_A { + match self.bits { + false => TXPTRUPD_A::DISABLED, + true => TXPTRUPD_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == TXPTRUPD_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == TXPTRUPD_A::ENABLED + } +} +#[doc = "Field `TXPTRUPD` writer - Enable or disable interrupt for event TXPTRUPD"] +pub type TXPTRUPD_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTEN_SPEC, TXPTRUPD_A, O>; +impl<'a, const O: u8> TXPTRUPD_W<'a, O> { + #[doc = "Disable"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(TXPTRUPD_A::DISABLED) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(TXPTRUPD_A::ENABLED) + } +} +impl R { + #[doc = "Bit 1 - Enable or disable interrupt for event RXPTRUPD"] + #[inline(always)] + pub fn rxptrupd(&self) -> RXPTRUPD_R { + RXPTRUPD_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Enable or disable interrupt for event STOPPED"] + #[inline(always)] + pub fn stopped(&self) -> STOPPED_R { + STOPPED_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 5 - Enable or disable interrupt for event TXPTRUPD"] + #[inline(always)] + pub fn txptrupd(&self) -> TXPTRUPD_R { + TXPTRUPD_R::new(((self.bits >> 5) & 1) != 0) + } +} +impl W { + #[doc = "Bit 1 - Enable or disable interrupt for event RXPTRUPD"] + #[inline(always)] + pub fn rxptrupd(&mut self) -> RXPTRUPD_W<1> { + RXPTRUPD_W::new(self) + } + #[doc = "Bit 2 - Enable or disable interrupt for event STOPPED"] + #[inline(always)] + pub fn stopped(&mut self) -> STOPPED_W<2> { + STOPPED_W::new(self) + } + #[doc = "Bit 5 - Enable or disable interrupt for event TXPTRUPD"] + #[inline(always)] + pub fn txptrupd(&mut self) -> TXPTRUPD_W<5> { + TXPTRUPD_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Enable or disable interrupt\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [inten](index.html) module"] +pub struct INTEN_SPEC; +impl crate::RegisterSpec for INTEN_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [inten::R](R) reader structure"] +impl crate::Readable for INTEN_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [inten::W](W) writer structure"] +impl crate::Writable for INTEN_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTEN to value 0"] +impl crate::Resettable for INTEN_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/i2s_ns/intenclr.rs b/pacs/nrf9120-pac/src/i2s_ns/intenclr.rs new file mode 100644 index 00000000..c5d4dc2f --- /dev/null +++ b/pacs/nrf9120-pac/src/i2s_ns/intenclr.rs @@ -0,0 +1,267 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `RXPTRUPD` reader - Write '1' to disable interrupt for event RXPTRUPD"] +pub type RXPTRUPD_R = crate::BitReader; +#[doc = "Write '1' to disable interrupt for event RXPTRUPD\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RXPTRUPD_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RXPTRUPD_A) -> Self { + variant as u8 != 0 + } +} +impl RXPTRUPD_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RXPTRUPD_A { + match self.bits { + false => RXPTRUPD_A::DISABLED, + true => RXPTRUPD_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == RXPTRUPD_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == RXPTRUPD_A::ENABLED + } +} +#[doc = "Write '1' to disable interrupt for event RXPTRUPD\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RXPTRUPD_AW { + #[doc = "1: Disable"] + CLEAR = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RXPTRUPD_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RXPTRUPD` writer - Write '1' to disable interrupt for event RXPTRUPD"] +pub type RXPTRUPD_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENCLR_SPEC, RXPTRUPD_AW, O>; +impl<'a, const O: u8> RXPTRUPD_W<'a, O> { + #[doc = "Disable"] + #[inline(always)] + pub fn clear(self) -> &'a mut W { + self.variant(RXPTRUPD_AW::CLEAR) + } +} +#[doc = "Field `STOPPED` reader - Write '1' to disable interrupt for event STOPPED"] +pub type STOPPED_R = crate::BitReader; +#[doc = "Write '1' to disable interrupt for event STOPPED\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum STOPPED_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: STOPPED_A) -> Self { + variant as u8 != 0 + } +} +impl STOPPED_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> STOPPED_A { + match self.bits { + false => STOPPED_A::DISABLED, + true => STOPPED_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == STOPPED_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == STOPPED_A::ENABLED + } +} +#[doc = "Write '1' to disable interrupt for event STOPPED\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum STOPPED_AW { + #[doc = "1: Disable"] + CLEAR = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: STOPPED_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `STOPPED` writer - Write '1' to disable interrupt for event STOPPED"] +pub type STOPPED_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENCLR_SPEC, STOPPED_AW, O>; +impl<'a, const O: u8> STOPPED_W<'a, O> { + #[doc = "Disable"] + #[inline(always)] + pub fn clear(self) -> &'a mut W { + self.variant(STOPPED_AW::CLEAR) + } +} +#[doc = "Field `TXPTRUPD` reader - Write '1' to disable interrupt for event TXPTRUPD"] +pub type TXPTRUPD_R = crate::BitReader; +#[doc = "Write '1' to disable interrupt for event TXPTRUPD\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum TXPTRUPD_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TXPTRUPD_A) -> Self { + variant as u8 != 0 + } +} +impl TXPTRUPD_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> TXPTRUPD_A { + match self.bits { + false => TXPTRUPD_A::DISABLED, + true => TXPTRUPD_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == TXPTRUPD_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == TXPTRUPD_A::ENABLED + } +} +#[doc = "Write '1' to disable interrupt for event TXPTRUPD\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum TXPTRUPD_AW { + #[doc = "1: Disable"] + CLEAR = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TXPTRUPD_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TXPTRUPD` writer - Write '1' to disable interrupt for event TXPTRUPD"] +pub type TXPTRUPD_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENCLR_SPEC, TXPTRUPD_AW, O>; +impl<'a, const O: u8> TXPTRUPD_W<'a, O> { + #[doc = "Disable"] + #[inline(always)] + pub fn clear(self) -> &'a mut W { + self.variant(TXPTRUPD_AW::CLEAR) + } +} +impl R { + #[doc = "Bit 1 - Write '1' to disable interrupt for event RXPTRUPD"] + #[inline(always)] + pub fn rxptrupd(&self) -> RXPTRUPD_R { + RXPTRUPD_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Write '1' to disable interrupt for event STOPPED"] + #[inline(always)] + pub fn stopped(&self) -> STOPPED_R { + STOPPED_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 5 - Write '1' to disable interrupt for event TXPTRUPD"] + #[inline(always)] + pub fn txptrupd(&self) -> TXPTRUPD_R { + TXPTRUPD_R::new(((self.bits >> 5) & 1) != 0) + } +} +impl W { + #[doc = "Bit 1 - Write '1' to disable interrupt for event RXPTRUPD"] + #[inline(always)] + pub fn rxptrupd(&mut self) -> RXPTRUPD_W<1> { + RXPTRUPD_W::new(self) + } + #[doc = "Bit 2 - Write '1' to disable interrupt for event STOPPED"] + #[inline(always)] + pub fn stopped(&mut self) -> STOPPED_W<2> { + STOPPED_W::new(self) + } + #[doc = "Bit 5 - Write '1' to disable interrupt for event TXPTRUPD"] + #[inline(always)] + pub fn txptrupd(&mut self) -> TXPTRUPD_W<5> { + TXPTRUPD_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Disable interrupt\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/i2s_ns/intenset.rs b/pacs/nrf9120-pac/src/i2s_ns/intenset.rs new file mode 100644 index 00000000..376d082a --- /dev/null +++ b/pacs/nrf9120-pac/src/i2s_ns/intenset.rs @@ -0,0 +1,267 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `RXPTRUPD` reader - Write '1' to enable interrupt for event RXPTRUPD"] +pub type RXPTRUPD_R = crate::BitReader; +#[doc = "Write '1' to enable interrupt for event RXPTRUPD\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RXPTRUPD_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RXPTRUPD_A) -> Self { + variant as u8 != 0 + } +} +impl RXPTRUPD_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RXPTRUPD_A { + match self.bits { + false => RXPTRUPD_A::DISABLED, + true => RXPTRUPD_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == RXPTRUPD_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == RXPTRUPD_A::ENABLED + } +} +#[doc = "Write '1' to enable interrupt for event RXPTRUPD\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RXPTRUPD_AW { + #[doc = "1: Enable"] + SET = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RXPTRUPD_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RXPTRUPD` writer - Write '1' to enable interrupt for event RXPTRUPD"] +pub type RXPTRUPD_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENSET_SPEC, RXPTRUPD_AW, O>; +impl<'a, const O: u8> RXPTRUPD_W<'a, O> { + #[doc = "Enable"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(RXPTRUPD_AW::SET) + } +} +#[doc = "Field `STOPPED` reader - Write '1' to enable interrupt for event STOPPED"] +pub type STOPPED_R = crate::BitReader; +#[doc = "Write '1' to enable interrupt for event STOPPED\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum STOPPED_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: STOPPED_A) -> Self { + variant as u8 != 0 + } +} +impl STOPPED_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> STOPPED_A { + match self.bits { + false => STOPPED_A::DISABLED, + true => STOPPED_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == STOPPED_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == STOPPED_A::ENABLED + } +} +#[doc = "Write '1' to enable interrupt for event STOPPED\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum STOPPED_AW { + #[doc = "1: Enable"] + SET = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: STOPPED_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `STOPPED` writer - Write '1' to enable interrupt for event STOPPED"] +pub type STOPPED_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENSET_SPEC, STOPPED_AW, O>; +impl<'a, const O: u8> STOPPED_W<'a, O> { + #[doc = "Enable"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(STOPPED_AW::SET) + } +} +#[doc = "Field `TXPTRUPD` reader - Write '1' to enable interrupt for event TXPTRUPD"] +pub type TXPTRUPD_R = crate::BitReader; +#[doc = "Write '1' to enable interrupt for event TXPTRUPD\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum TXPTRUPD_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TXPTRUPD_A) -> Self { + variant as u8 != 0 + } +} +impl TXPTRUPD_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> TXPTRUPD_A { + match self.bits { + false => TXPTRUPD_A::DISABLED, + true => TXPTRUPD_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == TXPTRUPD_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == TXPTRUPD_A::ENABLED + } +} +#[doc = "Write '1' to enable interrupt for event TXPTRUPD\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum TXPTRUPD_AW { + #[doc = "1: Enable"] + SET = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TXPTRUPD_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TXPTRUPD` writer - Write '1' to enable interrupt for event TXPTRUPD"] +pub type TXPTRUPD_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENSET_SPEC, TXPTRUPD_AW, O>; +impl<'a, const O: u8> TXPTRUPD_W<'a, O> { + #[doc = "Enable"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(TXPTRUPD_AW::SET) + } +} +impl R { + #[doc = "Bit 1 - Write '1' to enable interrupt for event RXPTRUPD"] + #[inline(always)] + pub fn rxptrupd(&self) -> RXPTRUPD_R { + RXPTRUPD_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Write '1' to enable interrupt for event STOPPED"] + #[inline(always)] + pub fn stopped(&self) -> STOPPED_R { + STOPPED_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 5 - Write '1' to enable interrupt for event TXPTRUPD"] + #[inline(always)] + pub fn txptrupd(&self) -> TXPTRUPD_R { + TXPTRUPD_R::new(((self.bits >> 5) & 1) != 0) + } +} +impl W { + #[doc = "Bit 1 - Write '1' to enable interrupt for event RXPTRUPD"] + #[inline(always)] + pub fn rxptrupd(&mut self) -> RXPTRUPD_W<1> { + RXPTRUPD_W::new(self) + } + #[doc = "Bit 2 - Write '1' to enable interrupt for event STOPPED"] + #[inline(always)] + pub fn stopped(&mut self) -> STOPPED_W<2> { + STOPPED_W::new(self) + } + #[doc = "Bit 5 - Write '1' to enable interrupt for event TXPTRUPD"] + #[inline(always)] + pub fn txptrupd(&mut self) -> TXPTRUPD_W<5> { + TXPTRUPD_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Enable interrupt\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/i2s_ns/psel.rs b/pacs/nrf9120-pac/src/i2s_ns/psel.rs new file mode 100644 index 00000000..b36fccfa --- /dev/null +++ b/pacs/nrf9120-pac/src/i2s_ns/psel.rs @@ -0,0 +1,34 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct PSEL { + #[doc = "0x00 - Pin select for MCK signal."] + pub mck: MCK, + #[doc = "0x04 - Pin select for SCK signal."] + pub sck: SCK, + #[doc = "0x08 - Pin select for LRCK signal."] + pub lrck: LRCK, + #[doc = "0x0c - Pin select for SDIN signal."] + pub sdin: SDIN, + #[doc = "0x10 - Pin select for SDOUT signal."] + pub sdout: SDOUT, +} +#[doc = "MCK (rw) register accessor: an alias for `Reg`"] +pub type MCK = crate::Reg; +#[doc = "Pin select for MCK signal."] +pub mod mck; +#[doc = "SCK (rw) register accessor: an alias for `Reg`"] +pub type SCK = crate::Reg; +#[doc = "Pin select for SCK signal."] +pub mod sck; +#[doc = "LRCK (rw) register accessor: an alias for `Reg`"] +pub type LRCK = crate::Reg; +#[doc = "Pin select for LRCK signal."] +pub mod lrck; +#[doc = "SDIN (rw) register accessor: an alias for `Reg`"] +pub type SDIN = crate::Reg; +#[doc = "Pin select for SDIN signal."] +pub mod sdin; +#[doc = "SDOUT (rw) register accessor: an alias for `Reg`"] +pub type SDOUT = crate::Reg; +#[doc = "Pin select for SDOUT signal."] +pub mod sdout; diff --git a/pacs/nrf9120-pac/src/i2s_ns/psel/lrck.rs b/pacs/nrf9120-pac/src/i2s_ns/psel/lrck.rs new file mode 100644 index 00000000..90c719d1 --- /dev/null +++ b/pacs/nrf9120-pac/src/i2s_ns/psel/lrck.rs @@ -0,0 +1,140 @@ +#[doc = "Register `LRCK` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `LRCK` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PIN` reader - Pin number"] +pub type PIN_R = crate::FieldReader; +#[doc = "Field `PIN` writer - Pin number"] +pub type PIN_W<'a, const O: u8> = crate::FieldWriter<'a, u32, LRCK_SPEC, u8, u8, 5, O>; +#[doc = "Field `CONNECT` reader - Connection"] +pub type CONNECT_R = crate::BitReader; +#[doc = "Connection\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CONNECT_A { + #[doc = "1: Disconnect"] + DISCONNECTED = 1, + #[doc = "0: Connect"] + CONNECTED = 0, +} +impl From for bool { + #[inline(always)] + fn from(variant: CONNECT_A) -> Self { + variant as u8 != 0 + } +} +impl CONNECT_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CONNECT_A { + match self.bits { + true => CONNECT_A::DISCONNECTED, + false => CONNECT_A::CONNECTED, + } + } + #[doc = "Checks if the value of the field is `DISCONNECTED`"] + #[inline(always)] + pub fn is_disconnected(&self) -> bool { + *self == CONNECT_A::DISCONNECTED + } + #[doc = "Checks if the value of the field is `CONNECTED`"] + #[inline(always)] + pub fn is_connected(&self) -> bool { + *self == CONNECT_A::CONNECTED + } +} +#[doc = "Field `CONNECT` writer - Connection"] +pub type CONNECT_W<'a, const O: u8> = crate::BitWriter<'a, u32, LRCK_SPEC, CONNECT_A, O>; +impl<'a, const O: u8> CONNECT_W<'a, O> { + #[doc = "Disconnect"] + #[inline(always)] + pub fn disconnected(self) -> &'a mut W { + self.variant(CONNECT_A::DISCONNECTED) + } + #[doc = "Connect"] + #[inline(always)] + pub fn connected(self) -> &'a mut W { + self.variant(CONNECT_A::CONNECTED) + } +} +impl R { + #[doc = "Bits 0:4 - Pin number"] + #[inline(always)] + pub fn pin(&self) -> PIN_R { + PIN_R::new((self.bits & 0x1f) as u8) + } + #[doc = "Bit 31 - Connection"] + #[inline(always)] + pub fn connect(&self) -> CONNECT_R { + CONNECT_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:4 - Pin number"] + #[inline(always)] + pub fn pin(&mut self) -> PIN_W<0> { + PIN_W::new(self) + } + #[doc = "Bit 31 - Connection"] + #[inline(always)] + pub fn connect(&mut self) -> CONNECT_W<31> { + CONNECT_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Pin select for LRCK signal.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [lrck](index.html) module"] +pub struct LRCK_SPEC; +impl crate::RegisterSpec for LRCK_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [lrck::R](R) reader structure"] +impl crate::Readable for LRCK_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [lrck::W](W) writer structure"] +impl crate::Writable for LRCK_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets LRCK to value 0xffff_ffff"] +impl crate::Resettable for LRCK_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0xffff_ffff + } +} diff --git a/pacs/nrf9120-pac/src/i2s_ns/psel/mck.rs b/pacs/nrf9120-pac/src/i2s_ns/psel/mck.rs new file mode 100644 index 00000000..18030c79 --- /dev/null +++ b/pacs/nrf9120-pac/src/i2s_ns/psel/mck.rs @@ -0,0 +1,140 @@ +#[doc = "Register `MCK` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `MCK` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PIN` reader - Pin number"] +pub type PIN_R = crate::FieldReader; +#[doc = "Field `PIN` writer - Pin number"] +pub type PIN_W<'a, const O: u8> = crate::FieldWriter<'a, u32, MCK_SPEC, u8, u8, 5, O>; +#[doc = "Field `CONNECT` reader - Connection"] +pub type CONNECT_R = crate::BitReader; +#[doc = "Connection\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CONNECT_A { + #[doc = "1: Disconnect"] + DISCONNECTED = 1, + #[doc = "0: Connect"] + CONNECTED = 0, +} +impl From for bool { + #[inline(always)] + fn from(variant: CONNECT_A) -> Self { + variant as u8 != 0 + } +} +impl CONNECT_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CONNECT_A { + match self.bits { + true => CONNECT_A::DISCONNECTED, + false => CONNECT_A::CONNECTED, + } + } + #[doc = "Checks if the value of the field is `DISCONNECTED`"] + #[inline(always)] + pub fn is_disconnected(&self) -> bool { + *self == CONNECT_A::DISCONNECTED + } + #[doc = "Checks if the value of the field is `CONNECTED`"] + #[inline(always)] + pub fn is_connected(&self) -> bool { + *self == CONNECT_A::CONNECTED + } +} +#[doc = "Field `CONNECT` writer - Connection"] +pub type CONNECT_W<'a, const O: u8> = crate::BitWriter<'a, u32, MCK_SPEC, CONNECT_A, O>; +impl<'a, const O: u8> CONNECT_W<'a, O> { + #[doc = "Disconnect"] + #[inline(always)] + pub fn disconnected(self) -> &'a mut W { + self.variant(CONNECT_A::DISCONNECTED) + } + #[doc = "Connect"] + #[inline(always)] + pub fn connected(self) -> &'a mut W { + self.variant(CONNECT_A::CONNECTED) + } +} +impl R { + #[doc = "Bits 0:4 - Pin number"] + #[inline(always)] + pub fn pin(&self) -> PIN_R { + PIN_R::new((self.bits & 0x1f) as u8) + } + #[doc = "Bit 31 - Connection"] + #[inline(always)] + pub fn connect(&self) -> CONNECT_R { + CONNECT_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:4 - Pin number"] + #[inline(always)] + pub fn pin(&mut self) -> PIN_W<0> { + PIN_W::new(self) + } + #[doc = "Bit 31 - Connection"] + #[inline(always)] + pub fn connect(&mut self) -> CONNECT_W<31> { + CONNECT_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Pin select for MCK signal.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [mck](index.html) module"] +pub struct MCK_SPEC; +impl crate::RegisterSpec for MCK_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [mck::R](R) reader structure"] +impl crate::Readable for MCK_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [mck::W](W) writer structure"] +impl crate::Writable for MCK_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets MCK to value 0xffff_ffff"] +impl crate::Resettable for MCK_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0xffff_ffff + } +} diff --git a/pacs/nrf9120-pac/src/i2s_ns/psel/sck.rs b/pacs/nrf9120-pac/src/i2s_ns/psel/sck.rs new file mode 100644 index 00000000..f3b39ebd --- /dev/null +++ b/pacs/nrf9120-pac/src/i2s_ns/psel/sck.rs @@ -0,0 +1,140 @@ +#[doc = "Register `SCK` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SCK` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PIN` reader - Pin number"] +pub type PIN_R = crate::FieldReader; +#[doc = "Field `PIN` writer - Pin number"] +pub type PIN_W<'a, const O: u8> = crate::FieldWriter<'a, u32, SCK_SPEC, u8, u8, 5, O>; +#[doc = "Field `CONNECT` reader - Connection"] +pub type CONNECT_R = crate::BitReader; +#[doc = "Connection\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CONNECT_A { + #[doc = "1: Disconnect"] + DISCONNECTED = 1, + #[doc = "0: Connect"] + CONNECTED = 0, +} +impl From for bool { + #[inline(always)] + fn from(variant: CONNECT_A) -> Self { + variant as u8 != 0 + } +} +impl CONNECT_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CONNECT_A { + match self.bits { + true => CONNECT_A::DISCONNECTED, + false => CONNECT_A::CONNECTED, + } + } + #[doc = "Checks if the value of the field is `DISCONNECTED`"] + #[inline(always)] + pub fn is_disconnected(&self) -> bool { + *self == CONNECT_A::DISCONNECTED + } + #[doc = "Checks if the value of the field is `CONNECTED`"] + #[inline(always)] + pub fn is_connected(&self) -> bool { + *self == CONNECT_A::CONNECTED + } +} +#[doc = "Field `CONNECT` writer - Connection"] +pub type CONNECT_W<'a, const O: u8> = crate::BitWriter<'a, u32, SCK_SPEC, CONNECT_A, O>; +impl<'a, const O: u8> CONNECT_W<'a, O> { + #[doc = "Disconnect"] + #[inline(always)] + pub fn disconnected(self) -> &'a mut W { + self.variant(CONNECT_A::DISCONNECTED) + } + #[doc = "Connect"] + #[inline(always)] + pub fn connected(self) -> &'a mut W { + self.variant(CONNECT_A::CONNECTED) + } +} +impl R { + #[doc = "Bits 0:4 - Pin number"] + #[inline(always)] + pub fn pin(&self) -> PIN_R { + PIN_R::new((self.bits & 0x1f) as u8) + } + #[doc = "Bit 31 - Connection"] + #[inline(always)] + pub fn connect(&self) -> CONNECT_R { + CONNECT_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:4 - Pin number"] + #[inline(always)] + pub fn pin(&mut self) -> PIN_W<0> { + PIN_W::new(self) + } + #[doc = "Bit 31 - Connection"] + #[inline(always)] + pub fn connect(&mut self) -> CONNECT_W<31> { + CONNECT_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Pin select for SCK signal.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sck](index.html) module"] +pub struct SCK_SPEC; +impl crate::RegisterSpec for SCK_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [sck::R](R) reader structure"] +impl crate::Readable for SCK_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [sck::W](W) writer structure"] +impl crate::Writable for SCK_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SCK to value 0xffff_ffff"] +impl crate::Resettable for SCK_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0xffff_ffff + } +} diff --git a/pacs/nrf9120-pac/src/i2s_ns/psel/sdin.rs b/pacs/nrf9120-pac/src/i2s_ns/psel/sdin.rs new file mode 100644 index 00000000..b06d558b --- /dev/null +++ b/pacs/nrf9120-pac/src/i2s_ns/psel/sdin.rs @@ -0,0 +1,140 @@ +#[doc = "Register `SDIN` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SDIN` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PIN` reader - Pin number"] +pub type PIN_R = crate::FieldReader; +#[doc = "Field `PIN` writer - Pin number"] +pub type PIN_W<'a, const O: u8> = crate::FieldWriter<'a, u32, SDIN_SPEC, u8, u8, 5, O>; +#[doc = "Field `CONNECT` reader - Connection"] +pub type CONNECT_R = crate::BitReader; +#[doc = "Connection\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CONNECT_A { + #[doc = "1: Disconnect"] + DISCONNECTED = 1, + #[doc = "0: Connect"] + CONNECTED = 0, +} +impl From for bool { + #[inline(always)] + fn from(variant: CONNECT_A) -> Self { + variant as u8 != 0 + } +} +impl CONNECT_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CONNECT_A { + match self.bits { + true => CONNECT_A::DISCONNECTED, + false => CONNECT_A::CONNECTED, + } + } + #[doc = "Checks if the value of the field is `DISCONNECTED`"] + #[inline(always)] + pub fn is_disconnected(&self) -> bool { + *self == CONNECT_A::DISCONNECTED + } + #[doc = "Checks if the value of the field is `CONNECTED`"] + #[inline(always)] + pub fn is_connected(&self) -> bool { + *self == CONNECT_A::CONNECTED + } +} +#[doc = "Field `CONNECT` writer - Connection"] +pub type CONNECT_W<'a, const O: u8> = crate::BitWriter<'a, u32, SDIN_SPEC, CONNECT_A, O>; +impl<'a, const O: u8> CONNECT_W<'a, O> { + #[doc = "Disconnect"] + #[inline(always)] + pub fn disconnected(self) -> &'a mut W { + self.variant(CONNECT_A::DISCONNECTED) + } + #[doc = "Connect"] + #[inline(always)] + pub fn connected(self) -> &'a mut W { + self.variant(CONNECT_A::CONNECTED) + } +} +impl R { + #[doc = "Bits 0:4 - Pin number"] + #[inline(always)] + pub fn pin(&self) -> PIN_R { + PIN_R::new((self.bits & 0x1f) as u8) + } + #[doc = "Bit 31 - Connection"] + #[inline(always)] + pub fn connect(&self) -> CONNECT_R { + CONNECT_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:4 - Pin number"] + #[inline(always)] + pub fn pin(&mut self) -> PIN_W<0> { + PIN_W::new(self) + } + #[doc = "Bit 31 - Connection"] + #[inline(always)] + pub fn connect(&mut self) -> CONNECT_W<31> { + CONNECT_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Pin select for SDIN signal.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sdin](index.html) module"] +pub struct SDIN_SPEC; +impl crate::RegisterSpec for SDIN_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [sdin::R](R) reader structure"] +impl crate::Readable for SDIN_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [sdin::W](W) writer structure"] +impl crate::Writable for SDIN_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SDIN to value 0xffff_ffff"] +impl crate::Resettable for SDIN_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0xffff_ffff + } +} diff --git a/pacs/nrf9120-pac/src/i2s_ns/psel/sdout.rs b/pacs/nrf9120-pac/src/i2s_ns/psel/sdout.rs new file mode 100644 index 00000000..9ffa858a --- /dev/null +++ b/pacs/nrf9120-pac/src/i2s_ns/psel/sdout.rs @@ -0,0 +1,140 @@ +#[doc = "Register `SDOUT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SDOUT` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PIN` reader - Pin number"] +pub type PIN_R = crate::FieldReader; +#[doc = "Field `PIN` writer - Pin number"] +pub type PIN_W<'a, const O: u8> = crate::FieldWriter<'a, u32, SDOUT_SPEC, u8, u8, 5, O>; +#[doc = "Field `CONNECT` reader - Connection"] +pub type CONNECT_R = crate::BitReader; +#[doc = "Connection\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CONNECT_A { + #[doc = "1: Disconnect"] + DISCONNECTED = 1, + #[doc = "0: Connect"] + CONNECTED = 0, +} +impl From for bool { + #[inline(always)] + fn from(variant: CONNECT_A) -> Self { + variant as u8 != 0 + } +} +impl CONNECT_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CONNECT_A { + match self.bits { + true => CONNECT_A::DISCONNECTED, + false => CONNECT_A::CONNECTED, + } + } + #[doc = "Checks if the value of the field is `DISCONNECTED`"] + #[inline(always)] + pub fn is_disconnected(&self) -> bool { + *self == CONNECT_A::DISCONNECTED + } + #[doc = "Checks if the value of the field is `CONNECTED`"] + #[inline(always)] + pub fn is_connected(&self) -> bool { + *self == CONNECT_A::CONNECTED + } +} +#[doc = "Field `CONNECT` writer - Connection"] +pub type CONNECT_W<'a, const O: u8> = crate::BitWriter<'a, u32, SDOUT_SPEC, CONNECT_A, O>; +impl<'a, const O: u8> CONNECT_W<'a, O> { + #[doc = "Disconnect"] + #[inline(always)] + pub fn disconnected(self) -> &'a mut W { + self.variant(CONNECT_A::DISCONNECTED) + } + #[doc = "Connect"] + #[inline(always)] + pub fn connected(self) -> &'a mut W { + self.variant(CONNECT_A::CONNECTED) + } +} +impl R { + #[doc = "Bits 0:4 - Pin number"] + #[inline(always)] + pub fn pin(&self) -> PIN_R { + PIN_R::new((self.bits & 0x1f) as u8) + } + #[doc = "Bit 31 - Connection"] + #[inline(always)] + pub fn connect(&self) -> CONNECT_R { + CONNECT_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:4 - Pin number"] + #[inline(always)] + pub fn pin(&mut self) -> PIN_W<0> { + PIN_W::new(self) + } + #[doc = "Bit 31 - Connection"] + #[inline(always)] + pub fn connect(&mut self) -> CONNECT_W<31> { + CONNECT_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Pin select for SDOUT signal.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sdout](index.html) module"] +pub struct SDOUT_SPEC; +impl crate::RegisterSpec for SDOUT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [sdout::R](R) reader structure"] +impl crate::Readable for SDOUT_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [sdout::W](W) writer structure"] +impl crate::Writable for SDOUT_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SDOUT to value 0xffff_ffff"] +impl crate::Resettable for SDOUT_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0xffff_ffff + } +} diff --git a/pacs/nrf9120-pac/src/i2s_ns/publish_rxptrupd.rs b/pacs/nrf9120-pac/src/i2s_ns/publish_rxptrupd.rs new file mode 100644 index 00000000..d6cd5db3 --- /dev/null +++ b/pacs/nrf9120-pac/src/i2s_ns/publish_rxptrupd.rs @@ -0,0 +1,141 @@ +#[doc = "Register `PUBLISH_RXPTRUPD` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PUBLISH_RXPTRUPD` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CHIDX` reader - DPPI channel that event RXPTRUPD will publish to"] +pub type CHIDX_R = crate::FieldReader; +#[doc = "Field `CHIDX` writer - DPPI channel that event RXPTRUPD will publish to"] +pub type CHIDX_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, PUBLISH_RXPTRUPD_SPEC, u8, u8, 8, O>; +#[doc = "Field `EN` reader - "] +pub type EN_R = crate::BitReader; +#[doc = "\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum EN_A { + #[doc = "0: Disable publishing"] + DISABLED = 0, + #[doc = "1: Enable publishing"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: EN_A) -> Self { + variant as u8 != 0 + } +} +impl EN_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EN_A { + match self.bits { + false => EN_A::DISABLED, + true => EN_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == EN_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == EN_A::ENABLED + } +} +#[doc = "Field `EN` writer - "] +pub type EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, PUBLISH_RXPTRUPD_SPEC, EN_A, O>; +impl<'a, const O: u8> EN_W<'a, O> { + #[doc = "Disable publishing"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(EN_A::DISABLED) + } + #[doc = "Enable publishing"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(EN_A::ENABLED) + } +} +impl R { + #[doc = "Bits 0:7 - DPPI channel that event RXPTRUPD will publish to"] + #[inline(always)] + pub fn chidx(&self) -> CHIDX_R { + CHIDX_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&self) -> EN_R { + EN_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:7 - DPPI channel that event RXPTRUPD will publish to"] + #[inline(always)] + pub fn chidx(&mut self) -> CHIDX_W<0> { + CHIDX_W::new(self) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&mut self) -> EN_W<31> { + EN_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Publish configuration for event RXPTRUPD\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [publish_rxptrupd](index.html) module"] +pub struct PUBLISH_RXPTRUPD_SPEC; +impl crate::RegisterSpec for PUBLISH_RXPTRUPD_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [publish_rxptrupd::R](R) reader structure"] +impl crate::Readable for PUBLISH_RXPTRUPD_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [publish_rxptrupd::W](W) writer structure"] +impl crate::Writable for PUBLISH_RXPTRUPD_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PUBLISH_RXPTRUPD to value 0"] +impl crate::Resettable for PUBLISH_RXPTRUPD_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/i2s_ns/publish_stopped.rs b/pacs/nrf9120-pac/src/i2s_ns/publish_stopped.rs new file mode 100644 index 00000000..247f50bf --- /dev/null +++ b/pacs/nrf9120-pac/src/i2s_ns/publish_stopped.rs @@ -0,0 +1,140 @@ +#[doc = "Register `PUBLISH_STOPPED` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PUBLISH_STOPPED` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CHIDX` reader - DPPI channel that event STOPPED will publish to"] +pub type CHIDX_R = crate::FieldReader; +#[doc = "Field `CHIDX` writer - DPPI channel that event STOPPED will publish to"] +pub type CHIDX_W<'a, const O: u8> = crate::FieldWriter<'a, u32, PUBLISH_STOPPED_SPEC, u8, u8, 8, O>; +#[doc = "Field `EN` reader - "] +pub type EN_R = crate::BitReader; +#[doc = "\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum EN_A { + #[doc = "0: Disable publishing"] + DISABLED = 0, + #[doc = "1: Enable publishing"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: EN_A) -> Self { + variant as u8 != 0 + } +} +impl EN_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EN_A { + match self.bits { + false => EN_A::DISABLED, + true => EN_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == EN_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == EN_A::ENABLED + } +} +#[doc = "Field `EN` writer - "] +pub type EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, PUBLISH_STOPPED_SPEC, EN_A, O>; +impl<'a, const O: u8> EN_W<'a, O> { + #[doc = "Disable publishing"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(EN_A::DISABLED) + } + #[doc = "Enable publishing"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(EN_A::ENABLED) + } +} +impl R { + #[doc = "Bits 0:7 - DPPI channel that event STOPPED will publish to"] + #[inline(always)] + pub fn chidx(&self) -> CHIDX_R { + CHIDX_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&self) -> EN_R { + EN_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:7 - DPPI channel that event STOPPED will publish to"] + #[inline(always)] + pub fn chidx(&mut self) -> CHIDX_W<0> { + CHIDX_W::new(self) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&mut self) -> EN_W<31> { + EN_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Publish configuration for event STOPPED\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [publish_stopped](index.html) module"] +pub struct PUBLISH_STOPPED_SPEC; +impl crate::RegisterSpec for PUBLISH_STOPPED_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [publish_stopped::R](R) reader structure"] +impl crate::Readable for PUBLISH_STOPPED_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [publish_stopped::W](W) writer structure"] +impl crate::Writable for PUBLISH_STOPPED_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PUBLISH_STOPPED to value 0"] +impl crate::Resettable for PUBLISH_STOPPED_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/i2s_ns/publish_txptrupd.rs b/pacs/nrf9120-pac/src/i2s_ns/publish_txptrupd.rs new file mode 100644 index 00000000..85427f3d --- /dev/null +++ b/pacs/nrf9120-pac/src/i2s_ns/publish_txptrupd.rs @@ -0,0 +1,141 @@ +#[doc = "Register `PUBLISH_TXPTRUPD` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PUBLISH_TXPTRUPD` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CHIDX` reader - DPPI channel that event TXPTRUPD will publish to"] +pub type CHIDX_R = crate::FieldReader; +#[doc = "Field `CHIDX` writer - DPPI channel that event TXPTRUPD will publish to"] +pub type CHIDX_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, PUBLISH_TXPTRUPD_SPEC, u8, u8, 8, O>; +#[doc = "Field `EN` reader - "] +pub type EN_R = crate::BitReader; +#[doc = "\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum EN_A { + #[doc = "0: Disable publishing"] + DISABLED = 0, + #[doc = "1: Enable publishing"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: EN_A) -> Self { + variant as u8 != 0 + } +} +impl EN_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EN_A { + match self.bits { + false => EN_A::DISABLED, + true => EN_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == EN_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == EN_A::ENABLED + } +} +#[doc = "Field `EN` writer - "] +pub type EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, PUBLISH_TXPTRUPD_SPEC, EN_A, O>; +impl<'a, const O: u8> EN_W<'a, O> { + #[doc = "Disable publishing"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(EN_A::DISABLED) + } + #[doc = "Enable publishing"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(EN_A::ENABLED) + } +} +impl R { + #[doc = "Bits 0:7 - DPPI channel that event TXPTRUPD will publish to"] + #[inline(always)] + pub fn chidx(&self) -> CHIDX_R { + CHIDX_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&self) -> EN_R { + EN_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:7 - DPPI channel that event TXPTRUPD will publish to"] + #[inline(always)] + pub fn chidx(&mut self) -> CHIDX_W<0> { + CHIDX_W::new(self) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&mut self) -> EN_W<31> { + EN_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Publish configuration for event TXPTRUPD\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [publish_txptrupd](index.html) module"] +pub struct PUBLISH_TXPTRUPD_SPEC; +impl crate::RegisterSpec for PUBLISH_TXPTRUPD_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [publish_txptrupd::R](R) reader structure"] +impl crate::Readable for PUBLISH_TXPTRUPD_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [publish_txptrupd::W](W) writer structure"] +impl crate::Writable for PUBLISH_TXPTRUPD_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PUBLISH_TXPTRUPD to value 0"] +impl crate::Resettable for PUBLISH_TXPTRUPD_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/i2s_ns/rxd.rs b/pacs/nrf9120-pac/src/i2s_ns/rxd.rs new file mode 100644 index 00000000..56ceed6c --- /dev/null +++ b/pacs/nrf9120-pac/src/i2s_ns/rxd.rs @@ -0,0 +1,10 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RXD { + #[doc = "0x00 - Receive buffer RAM start address."] + pub ptr: PTR, +} +#[doc = "PTR (rw) register accessor: an alias for `Reg`"] +pub type PTR = crate::Reg; +#[doc = "Receive buffer RAM start address."] +pub mod ptr; diff --git a/pacs/nrf9120-pac/src/i2s_ns/rxd/ptr.rs b/pacs/nrf9120-pac/src/i2s_ns/rxd/ptr.rs new file mode 100644 index 00000000..25257eda --- /dev/null +++ b/pacs/nrf9120-pac/src/i2s_ns/rxd/ptr.rs @@ -0,0 +1,80 @@ +#[doc = "Register `PTR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PTR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PTR` reader - Receive buffer Data RAM start address. When receiving, words containing samples will be written to this address. This address is a word aligned Data RAM address."] +pub type PTR_R = crate::FieldReader; +#[doc = "Field `PTR` writer - Receive buffer Data RAM start address. When receiving, words containing samples will be written to this address. This address is a word aligned Data RAM address."] +pub type PTR_W<'a, const O: u8> = crate::FieldWriter<'a, u32, PTR_SPEC, u32, u32, 32, O>; +impl R { + #[doc = "Bits 0:31 - Receive buffer Data RAM start address. When receiving, words containing samples will be written to this address. This address is a word aligned Data RAM address."] + #[inline(always)] + pub fn ptr(&self) -> PTR_R { + PTR_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Receive buffer Data RAM start address. When receiving, words containing samples will be written to this address. This address is a word aligned Data RAM address."] + #[inline(always)] + pub fn ptr(&mut self) -> PTR_W<0> { + PTR_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Receive buffer RAM start address.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ptr](index.html) module"] +pub struct PTR_SPEC; +impl crate::RegisterSpec for PTR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ptr::R](R) reader structure"] +impl crate::Readable for PTR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ptr::W](W) writer structure"] +impl crate::Writable for PTR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PTR to value 0"] +impl crate::Resettable for PTR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/i2s_ns/rxtxd.rs b/pacs/nrf9120-pac/src/i2s_ns/rxtxd.rs new file mode 100644 index 00000000..8f4bd2b7 --- /dev/null +++ b/pacs/nrf9120-pac/src/i2s_ns/rxtxd.rs @@ -0,0 +1,10 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RXTXD { + #[doc = "0x00 - Size of RXD and TXD buffers."] + pub maxcnt: MAXCNT, +} +#[doc = "MAXCNT (rw) register accessor: an alias for `Reg`"] +pub type MAXCNT = crate::Reg; +#[doc = "Size of RXD and TXD buffers."] +pub mod maxcnt; diff --git a/pacs/nrf9120-pac/src/i2s_ns/rxtxd/maxcnt.rs b/pacs/nrf9120-pac/src/i2s_ns/rxtxd/maxcnt.rs new file mode 100644 index 00000000..83f3ba5f --- /dev/null +++ b/pacs/nrf9120-pac/src/i2s_ns/rxtxd/maxcnt.rs @@ -0,0 +1,80 @@ +#[doc = "Register `MAXCNT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `MAXCNT` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `MAXCNT` reader - Size of RXD and TXD buffers in number of 32 bit words."] +pub type MAXCNT_R = crate::FieldReader; +#[doc = "Field `MAXCNT` writer - Size of RXD and TXD buffers in number of 32 bit words."] +pub type MAXCNT_W<'a, const O: u8> = crate::FieldWriter<'a, u32, MAXCNT_SPEC, u16, u16, 14, O>; +impl R { + #[doc = "Bits 0:13 - Size of RXD and TXD buffers in number of 32 bit words."] + #[inline(always)] + pub fn maxcnt(&self) -> MAXCNT_R { + MAXCNT_R::new((self.bits & 0x3fff) as u16) + } +} +impl W { + #[doc = "Bits 0:13 - Size of RXD and TXD buffers in number of 32 bit words."] + #[inline(always)] + pub fn maxcnt(&mut self) -> MAXCNT_W<0> { + MAXCNT_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Size of RXD and TXD buffers.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [maxcnt](index.html) module"] +pub struct MAXCNT_SPEC; +impl crate::RegisterSpec for MAXCNT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [maxcnt::R](R) reader structure"] +impl crate::Readable for MAXCNT_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [maxcnt::W](W) writer structure"] +impl crate::Writable for MAXCNT_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets MAXCNT to value 0"] +impl crate::Resettable for MAXCNT_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/i2s_ns/subscribe_start.rs b/pacs/nrf9120-pac/src/i2s_ns/subscribe_start.rs new file mode 100644 index 00000000..fb9deced --- /dev/null +++ b/pacs/nrf9120-pac/src/i2s_ns/subscribe_start.rs @@ -0,0 +1,140 @@ +#[doc = "Register `SUBSCRIBE_START` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SUBSCRIBE_START` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CHIDX` reader - DPPI channel that task START will subscribe to"] +pub type CHIDX_R = crate::FieldReader; +#[doc = "Field `CHIDX` writer - DPPI channel that task START will subscribe to"] +pub type CHIDX_W<'a, const O: u8> = crate::FieldWriter<'a, u32, SUBSCRIBE_START_SPEC, u8, u8, 8, O>; +#[doc = "Field `EN` reader - "] +pub type EN_R = crate::BitReader; +#[doc = "\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum EN_A { + #[doc = "0: Disable subscription"] + DISABLED = 0, + #[doc = "1: Enable subscription"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: EN_A) -> Self { + variant as u8 != 0 + } +} +impl EN_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EN_A { + match self.bits { + false => EN_A::DISABLED, + true => EN_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == EN_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == EN_A::ENABLED + } +} +#[doc = "Field `EN` writer - "] +pub type EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, SUBSCRIBE_START_SPEC, EN_A, O>; +impl<'a, const O: u8> EN_W<'a, O> { + #[doc = "Disable subscription"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(EN_A::DISABLED) + } + #[doc = "Enable subscription"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(EN_A::ENABLED) + } +} +impl R { + #[doc = "Bits 0:7 - DPPI channel that task START will subscribe to"] + #[inline(always)] + pub fn chidx(&self) -> CHIDX_R { + CHIDX_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&self) -> EN_R { + EN_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:7 - DPPI channel that task START will subscribe to"] + #[inline(always)] + pub fn chidx(&mut self) -> CHIDX_W<0> { + CHIDX_W::new(self) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&mut self) -> EN_W<31> { + EN_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Subscribe configuration for task START\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [subscribe_start](index.html) module"] +pub struct SUBSCRIBE_START_SPEC; +impl crate::RegisterSpec for SUBSCRIBE_START_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [subscribe_start::R](R) reader structure"] +impl crate::Readable for SUBSCRIBE_START_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [subscribe_start::W](W) writer structure"] +impl crate::Writable for SUBSCRIBE_START_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SUBSCRIBE_START to value 0"] +impl crate::Resettable for SUBSCRIBE_START_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/i2s_ns/subscribe_stop.rs b/pacs/nrf9120-pac/src/i2s_ns/subscribe_stop.rs new file mode 100644 index 00000000..2fe3af58 --- /dev/null +++ b/pacs/nrf9120-pac/src/i2s_ns/subscribe_stop.rs @@ -0,0 +1,140 @@ +#[doc = "Register `SUBSCRIBE_STOP` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SUBSCRIBE_STOP` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CHIDX` reader - DPPI channel that task STOP will subscribe to"] +pub type CHIDX_R = crate::FieldReader; +#[doc = "Field `CHIDX` writer - DPPI channel that task STOP will subscribe to"] +pub type CHIDX_W<'a, const O: u8> = crate::FieldWriter<'a, u32, SUBSCRIBE_STOP_SPEC, u8, u8, 8, O>; +#[doc = "Field `EN` reader - "] +pub type EN_R = crate::BitReader; +#[doc = "\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum EN_A { + #[doc = "0: Disable subscription"] + DISABLED = 0, + #[doc = "1: Enable subscription"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: EN_A) -> Self { + variant as u8 != 0 + } +} +impl EN_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EN_A { + match self.bits { + false => EN_A::DISABLED, + true => EN_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == EN_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == EN_A::ENABLED + } +} +#[doc = "Field `EN` writer - "] +pub type EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, SUBSCRIBE_STOP_SPEC, EN_A, O>; +impl<'a, const O: u8> EN_W<'a, O> { + #[doc = "Disable subscription"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(EN_A::DISABLED) + } + #[doc = "Enable subscription"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(EN_A::ENABLED) + } +} +impl R { + #[doc = "Bits 0:7 - DPPI channel that task STOP will subscribe to"] + #[inline(always)] + pub fn chidx(&self) -> CHIDX_R { + CHIDX_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&self) -> EN_R { + EN_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:7 - DPPI channel that task STOP will subscribe to"] + #[inline(always)] + pub fn chidx(&mut self) -> CHIDX_W<0> { + CHIDX_W::new(self) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&mut self) -> EN_W<31> { + EN_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Subscribe configuration for task STOP\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [subscribe_stop](index.html) module"] +pub struct SUBSCRIBE_STOP_SPEC; +impl crate::RegisterSpec for SUBSCRIBE_STOP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [subscribe_stop::R](R) reader structure"] +impl crate::Readable for SUBSCRIBE_STOP_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [subscribe_stop::W](W) writer structure"] +impl crate::Writable for SUBSCRIBE_STOP_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SUBSCRIBE_STOP to value 0"] +impl crate::Resettable for SUBSCRIBE_STOP_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/i2s_ns/tasks_start.rs b/pacs/nrf9120-pac/src/i2s_ns/tasks_start.rs new file mode 100644 index 00000000..db7a263b --- /dev/null +++ b/pacs/nrf9120-pac/src/i2s_ns/tasks_start.rs @@ -0,0 +1,72 @@ +#[doc = "Register `TASKS_START` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Starts continuous I2S transfer. Also starts MCK generator when this is enabled.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum TASKS_START_AW { + #[doc = "1: Trigger task"] + TRIGGER = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TASKS_START_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TASKS_START` writer - Starts continuous I2S transfer. Also starts MCK generator when this is enabled."] +pub type TASKS_START_W<'a, const O: u8> = + crate::BitWriter<'a, u32, TASKS_START_SPEC, TASKS_START_AW, O>; +impl<'a, const O: u8> TASKS_START_W<'a, O> { + #[doc = "Trigger task"] + #[inline(always)] + pub fn trigger(self) -> &'a mut W { + self.variant(TASKS_START_AW::TRIGGER) + } +} +impl W { + #[doc = "Bit 0 - Starts continuous I2S transfer. Also starts MCK generator when this is enabled."] + #[inline(always)] + pub fn tasks_start(&mut self) -> TASKS_START_W<0> { + TASKS_START_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Starts continuous I2S transfer. Also starts MCK generator when this is enabled.\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tasks_start](index.html) module"] +pub struct TASKS_START_SPEC; +impl crate::RegisterSpec for TASKS_START_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [tasks_start::W](W) writer structure"] +impl crate::Writable for TASKS_START_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets TASKS_START to value 0"] +impl crate::Resettable for TASKS_START_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/i2s_ns/tasks_stop.rs b/pacs/nrf9120-pac/src/i2s_ns/tasks_stop.rs new file mode 100644 index 00000000..c6019f6f --- /dev/null +++ b/pacs/nrf9120-pac/src/i2s_ns/tasks_stop.rs @@ -0,0 +1,72 @@ +#[doc = "Register `TASKS_STOP` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Stops I2S transfer. Also stops MCK generator. Triggering this task will cause the STOPPED event to be generated.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum TASKS_STOP_AW { + #[doc = "1: Trigger task"] + TRIGGER = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TASKS_STOP_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TASKS_STOP` writer - Stops I2S transfer. Also stops MCK generator. Triggering this task will cause the STOPPED event to be generated."] +pub type TASKS_STOP_W<'a, const O: u8> = + crate::BitWriter<'a, u32, TASKS_STOP_SPEC, TASKS_STOP_AW, O>; +impl<'a, const O: u8> TASKS_STOP_W<'a, O> { + #[doc = "Trigger task"] + #[inline(always)] + pub fn trigger(self) -> &'a mut W { + self.variant(TASKS_STOP_AW::TRIGGER) + } +} +impl W { + #[doc = "Bit 0 - Stops I2S transfer. Also stops MCK generator. Triggering this task will cause the STOPPED event to be generated."] + #[inline(always)] + pub fn tasks_stop(&mut self) -> TASKS_STOP_W<0> { + TASKS_STOP_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Stops I2S transfer. Also stops MCK generator. Triggering this task will cause the STOPPED event to be generated.\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tasks_stop](index.html) module"] +pub struct TASKS_STOP_SPEC; +impl crate::RegisterSpec for TASKS_STOP_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [tasks_stop::W](W) writer structure"] +impl crate::Writable for TASKS_STOP_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets TASKS_STOP to value 0"] +impl crate::Resettable for TASKS_STOP_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/i2s_ns/txd.rs b/pacs/nrf9120-pac/src/i2s_ns/txd.rs new file mode 100644 index 00000000..9abfe8c6 --- /dev/null +++ b/pacs/nrf9120-pac/src/i2s_ns/txd.rs @@ -0,0 +1,10 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct TXD { + #[doc = "0x00 - Transmit buffer RAM start address."] + pub ptr: PTR, +} +#[doc = "PTR (rw) register accessor: an alias for `Reg`"] +pub type PTR = crate::Reg; +#[doc = "Transmit buffer RAM start address."] +pub mod ptr; diff --git a/pacs/nrf9120-pac/src/i2s_ns/txd/ptr.rs b/pacs/nrf9120-pac/src/i2s_ns/txd/ptr.rs new file mode 100644 index 00000000..98480d75 --- /dev/null +++ b/pacs/nrf9120-pac/src/i2s_ns/txd/ptr.rs @@ -0,0 +1,80 @@ +#[doc = "Register `PTR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PTR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PTR` reader - Transmit buffer Data RAM start address. When transmitting, words containing samples will be fetched from this address. This address is a word aligned Data RAM address."] +pub type PTR_R = crate::FieldReader; +#[doc = "Field `PTR` writer - Transmit buffer Data RAM start address. When transmitting, words containing samples will be fetched from this address. This address is a word aligned Data RAM address."] +pub type PTR_W<'a, const O: u8> = crate::FieldWriter<'a, u32, PTR_SPEC, u32, u32, 32, O>; +impl R { + #[doc = "Bits 0:31 - Transmit buffer Data RAM start address. When transmitting, words containing samples will be fetched from this address. This address is a word aligned Data RAM address."] + #[inline(always)] + pub fn ptr(&self) -> PTR_R { + PTR_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Transmit buffer Data RAM start address. When transmitting, words containing samples will be fetched from this address. This address is a word aligned Data RAM address."] + #[inline(always)] + pub fn ptr(&mut self) -> PTR_W<0> { + PTR_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Transmit buffer RAM start address.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ptr](index.html) module"] +pub struct PTR_SPEC; +impl crate::RegisterSpec for PTR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ptr::R](R) reader structure"] +impl crate::Readable for PTR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ptr::W](W) writer structure"] +impl crate::Writable for PTR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PTR to value 0"] +impl crate::Resettable for PTR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/ipc_ns.rs b/pacs/nrf9120-pac/src/ipc_ns.rs new file mode 100644 index 00000000..7eb12d26 --- /dev/null +++ b/pacs/nrf9120-pac/src/ipc_ns.rs @@ -0,0 +1,77 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00..0x20 - Description collection: Trigger events on IPC channel enabled in SEND_CNF\\[n\\]"] + pub tasks_send: [TASKS_SEND; 8], + _reserved1: [u8; 0x60], + #[doc = "0x80..0xa0 - Description collection: Subscribe configuration for task SEND\\[n\\]"] + pub subscribe_send: [SUBSCRIBE_SEND; 8], + _reserved2: [u8; 0x60], + #[doc = "0x100..0x120 - Description collection: Event received on one or more of the enabled IPC channels in RECEIVE_CNF\\[n\\]"] + pub events_receive: [EVENTS_RECEIVE; 8], + _reserved3: [u8; 0x60], + #[doc = "0x180..0x1a0 - Description collection: Publish configuration for event RECEIVE\\[n\\]"] + pub publish_receive: [PUBLISH_RECEIVE; 8], + _reserved4: [u8; 0x0160], + #[doc = "0x300 - Enable or disable interrupt"] + pub inten: INTEN, + #[doc = "0x304 - Enable interrupt"] + pub intenset: INTENSET, + #[doc = "0x308 - Disable interrupt"] + pub intenclr: INTENCLR, + #[doc = "0x30c - Pending interrupts"] + pub intpend: INTPEND, + _reserved8: [u8; 0x0200], + #[doc = "0x510..0x530 - Description collection: Send event configuration for TASKS_SEND\\[n\\]"] + pub send_cnf: [SEND_CNF; 8], + _reserved9: [u8; 0x60], + #[doc = "0x590..0x5b0 - Description collection: Receive event configuration for EVENTS_RECEIVE\\[n\\]"] + pub receive_cnf: [RECEIVE_CNF; 8], + _reserved10: [u8; 0x60], + #[doc = "0x610..0x620 - Description collection: General purpose memory"] + pub gpmem: [GPMEM; 4], +} +#[doc = "TASKS_SEND (w) register accessor: an alias for `Reg`"] +pub type TASKS_SEND = crate::Reg; +#[doc = "Description collection: Trigger events on IPC channel enabled in SEND_CNF\\[n\\]"] +pub mod tasks_send; +#[doc = "SUBSCRIBE_SEND (rw) register accessor: an alias for `Reg`"] +pub type SUBSCRIBE_SEND = crate::Reg; +#[doc = "Description collection: Subscribe configuration for task SEND\\[n\\]"] +pub mod subscribe_send; +#[doc = "EVENTS_RECEIVE (rw) register accessor: an alias for `Reg`"] +pub type EVENTS_RECEIVE = crate::Reg; +#[doc = "Description collection: Event received on one or more of the enabled IPC channels in RECEIVE_CNF\\[n\\]"] +pub mod events_receive; +#[doc = "PUBLISH_RECEIVE (rw) register accessor: an alias for `Reg`"] +pub type PUBLISH_RECEIVE = crate::Reg; +#[doc = "Description collection: Publish configuration for event RECEIVE\\[n\\]"] +pub mod publish_receive; +#[doc = "INTEN (rw) register accessor: an alias for `Reg`"] +pub type INTEN = crate::Reg; +#[doc = "Enable or disable interrupt"] +pub mod inten; +#[doc = "INTENSET (rw) register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "Enable interrupt"] +pub mod intenset; +#[doc = "INTENCLR (rw) register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "Disable interrupt"] +pub mod intenclr; +#[doc = "INTPEND (r) register accessor: an alias for `Reg`"] +pub type INTPEND = crate::Reg; +#[doc = "Pending interrupts"] +pub mod intpend; +#[doc = "SEND_CNF (rw) register accessor: an alias for `Reg`"] +pub type SEND_CNF = crate::Reg; +#[doc = "Description collection: Send event configuration for TASKS_SEND\\[n\\]"] +pub mod send_cnf; +#[doc = "RECEIVE_CNF (rw) register accessor: an alias for `Reg`"] +pub type RECEIVE_CNF = crate::Reg; +#[doc = "Description collection: Receive event configuration for EVENTS_RECEIVE\\[n\\]"] +pub mod receive_cnf; +#[doc = "GPMEM (rw) register accessor: an alias for `Reg`"] +pub type GPMEM = crate::Reg; +#[doc = "Description collection: General purpose memory"] +pub mod gpmem; diff --git a/pacs/nrf9120-pac/src/ipc_ns/events_receive.rs b/pacs/nrf9120-pac/src/ipc_ns/events_receive.rs new file mode 100644 index 00000000..37a5c88d --- /dev/null +++ b/pacs/nrf9120-pac/src/ipc_ns/events_receive.rs @@ -0,0 +1,128 @@ +#[doc = "Register `EVENTS_RECEIVE[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVENTS_RECEIVE[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `EVENTS_RECEIVE` reader - Event received on one or more of the enabled IPC channels in RECEIVE_CNF\\[n\\]"] +pub type EVENTS_RECEIVE_R = crate::BitReader; +#[doc = "Event received on one or more of the enabled IPC channels in RECEIVE_CNF\\[n\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum EVENTS_RECEIVE_A { + #[doc = "0: Event not generated"] + NOT_GENERATED = 0, + #[doc = "1: Event generated"] + GENERATED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: EVENTS_RECEIVE_A) -> Self { + variant as u8 != 0 + } +} +impl EVENTS_RECEIVE_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EVENTS_RECEIVE_A { + match self.bits { + false => EVENTS_RECEIVE_A::NOT_GENERATED, + true => EVENTS_RECEIVE_A::GENERATED, + } + } + #[doc = "Checks if the value of the field is `NOT_GENERATED`"] + #[inline(always)] + pub fn is_not_generated(&self) -> bool { + *self == EVENTS_RECEIVE_A::NOT_GENERATED + } + #[doc = "Checks if the value of the field is `GENERATED`"] + #[inline(always)] + pub fn is_generated(&self) -> bool { + *self == EVENTS_RECEIVE_A::GENERATED + } +} +#[doc = "Field `EVENTS_RECEIVE` writer - Event received on one or more of the enabled IPC channels in RECEIVE_CNF\\[n\\]"] +pub type EVENTS_RECEIVE_W<'a, const O: u8> = + crate::BitWriter<'a, u32, EVENTS_RECEIVE_SPEC, EVENTS_RECEIVE_A, O>; +impl<'a, const O: u8> EVENTS_RECEIVE_W<'a, O> { + #[doc = "Event not generated"] + #[inline(always)] + pub fn not_generated(self) -> &'a mut W { + self.variant(EVENTS_RECEIVE_A::NOT_GENERATED) + } + #[doc = "Event generated"] + #[inline(always)] + pub fn generated(self) -> &'a mut W { + self.variant(EVENTS_RECEIVE_A::GENERATED) + } +} +impl R { + #[doc = "Bit 0 - Event received on one or more of the enabled IPC channels in RECEIVE_CNF\\[n\\]"] + #[inline(always)] + pub fn events_receive(&self) -> EVENTS_RECEIVE_R { + EVENTS_RECEIVE_R::new((self.bits & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Event received on one or more of the enabled IPC channels in RECEIVE_CNF\\[n\\]"] + #[inline(always)] + pub fn events_receive(&mut self) -> EVENTS_RECEIVE_W<0> { + EVENTS_RECEIVE_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Description collection: Event received on one or more of the enabled IPC channels in RECEIVE_CNF\\[n\\]\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [events_receive](index.html) module"] +pub struct EVENTS_RECEIVE_SPEC; +impl crate::RegisterSpec for EVENTS_RECEIVE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [events_receive::R](R) reader structure"] +impl crate::Readable for EVENTS_RECEIVE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [events_receive::W](W) writer structure"] +impl crate::Writable for EVENTS_RECEIVE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EVENTS_RECEIVE[%s] +to value 0"] +impl crate::Resettable for EVENTS_RECEIVE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/ipc_ns/gpmem.rs b/pacs/nrf9120-pac/src/ipc_ns/gpmem.rs new file mode 100644 index 00000000..3af11b69 --- /dev/null +++ b/pacs/nrf9120-pac/src/ipc_ns/gpmem.rs @@ -0,0 +1,81 @@ +#[doc = "Register `GPMEM[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GPMEM[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `GPMEM` reader - General purpose memory"] +pub type GPMEM_R = crate::FieldReader; +#[doc = "Field `GPMEM` writer - General purpose memory"] +pub type GPMEM_W<'a, const O: u8> = crate::FieldWriter<'a, u32, GPMEM_SPEC, u32, u32, 32, O>; +impl R { + #[doc = "Bits 0:31 - General purpose memory"] + #[inline(always)] + pub fn gpmem(&self) -> GPMEM_R { + GPMEM_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - General purpose memory"] + #[inline(always)] + pub fn gpmem(&mut self) -> GPMEM_W<0> { + GPMEM_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Description collection: General purpose memory\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gpmem](index.html) module"] +pub struct GPMEM_SPEC; +impl crate::RegisterSpec for GPMEM_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gpmem::R](R) reader structure"] +impl crate::Readable for GPMEM_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gpmem::W](W) writer structure"] +impl crate::Writable for GPMEM_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets GPMEM[%s] +to value 0"] +impl crate::Resettable for GPMEM_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/ipc_ns/inten.rs b/pacs/nrf9120-pac/src/ipc_ns/inten.rs new file mode 100644 index 00000000..77ae07d8 --- /dev/null +++ b/pacs/nrf9120-pac/src/ipc_ns/inten.rs @@ -0,0 +1,546 @@ +#[doc = "Register `INTEN` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTEN` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `RECEIVE0` reader - Enable or disable interrupt for event RECEIVE\\[0\\]"] +pub type RECEIVE0_R = crate::BitReader; +#[doc = "Enable or disable interrupt for event RECEIVE\\[0\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RECEIVE0_A { + #[doc = "0: Disable"] + DISABLED = 0, + #[doc = "1: Enable"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RECEIVE0_A) -> Self { + variant as u8 != 0 + } +} +impl RECEIVE0_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RECEIVE0_A { + match self.bits { + false => RECEIVE0_A::DISABLED, + true => RECEIVE0_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == RECEIVE0_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == RECEIVE0_A::ENABLED + } +} +#[doc = "Field `RECEIVE0` writer - Enable or disable interrupt for event RECEIVE\\[0\\]"] +pub type RECEIVE0_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTEN_SPEC, RECEIVE0_A, O>; +impl<'a, const O: u8> RECEIVE0_W<'a, O> { + #[doc = "Disable"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(RECEIVE0_A::DISABLED) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(RECEIVE0_A::ENABLED) + } +} +#[doc = "Field `RECEIVE1` reader - Enable or disable interrupt for event RECEIVE\\[1\\]"] +pub type RECEIVE1_R = crate::BitReader; +#[doc = "Enable or disable interrupt for event RECEIVE\\[1\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RECEIVE1_A { + #[doc = "0: Disable"] + DISABLED = 0, + #[doc = "1: Enable"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RECEIVE1_A) -> Self { + variant as u8 != 0 + } +} +impl RECEIVE1_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RECEIVE1_A { + match self.bits { + false => RECEIVE1_A::DISABLED, + true => RECEIVE1_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == RECEIVE1_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == RECEIVE1_A::ENABLED + } +} +#[doc = "Field `RECEIVE1` writer - Enable or disable interrupt for event RECEIVE\\[1\\]"] +pub type RECEIVE1_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTEN_SPEC, RECEIVE1_A, O>; +impl<'a, const O: u8> RECEIVE1_W<'a, O> { + #[doc = "Disable"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(RECEIVE1_A::DISABLED) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(RECEIVE1_A::ENABLED) + } +} +#[doc = "Field `RECEIVE2` reader - Enable or disable interrupt for event RECEIVE\\[2\\]"] +pub type RECEIVE2_R = crate::BitReader; +#[doc = "Enable or disable interrupt for event RECEIVE\\[2\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RECEIVE2_A { + #[doc = "0: Disable"] + DISABLED = 0, + #[doc = "1: Enable"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RECEIVE2_A) -> Self { + variant as u8 != 0 + } +} +impl RECEIVE2_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RECEIVE2_A { + match self.bits { + false => RECEIVE2_A::DISABLED, + true => RECEIVE2_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == RECEIVE2_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == RECEIVE2_A::ENABLED + } +} +#[doc = "Field `RECEIVE2` writer - Enable or disable interrupt for event RECEIVE\\[2\\]"] +pub type RECEIVE2_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTEN_SPEC, RECEIVE2_A, O>; +impl<'a, const O: u8> RECEIVE2_W<'a, O> { + #[doc = "Disable"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(RECEIVE2_A::DISABLED) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(RECEIVE2_A::ENABLED) + } +} +#[doc = "Field `RECEIVE3` reader - Enable or disable interrupt for event RECEIVE\\[3\\]"] +pub type RECEIVE3_R = crate::BitReader; +#[doc = "Enable or disable interrupt for event RECEIVE\\[3\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RECEIVE3_A { + #[doc = "0: Disable"] + DISABLED = 0, + #[doc = "1: Enable"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RECEIVE3_A) -> Self { + variant as u8 != 0 + } +} +impl RECEIVE3_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RECEIVE3_A { + match self.bits { + false => RECEIVE3_A::DISABLED, + true => RECEIVE3_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == RECEIVE3_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == RECEIVE3_A::ENABLED + } +} +#[doc = "Field `RECEIVE3` writer - Enable or disable interrupt for event RECEIVE\\[3\\]"] +pub type RECEIVE3_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTEN_SPEC, RECEIVE3_A, O>; +impl<'a, const O: u8> RECEIVE3_W<'a, O> { + #[doc = "Disable"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(RECEIVE3_A::DISABLED) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(RECEIVE3_A::ENABLED) + } +} +#[doc = "Field `RECEIVE4` reader - Enable or disable interrupt for event RECEIVE\\[4\\]"] +pub type RECEIVE4_R = crate::BitReader; +#[doc = "Enable or disable interrupt for event RECEIVE\\[4\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RECEIVE4_A { + #[doc = "0: Disable"] + DISABLED = 0, + #[doc = "1: Enable"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RECEIVE4_A) -> Self { + variant as u8 != 0 + } +} +impl RECEIVE4_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RECEIVE4_A { + match self.bits { + false => RECEIVE4_A::DISABLED, + true => RECEIVE4_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == RECEIVE4_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == RECEIVE4_A::ENABLED + } +} +#[doc = "Field `RECEIVE4` writer - Enable or disable interrupt for event RECEIVE\\[4\\]"] +pub type RECEIVE4_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTEN_SPEC, RECEIVE4_A, O>; +impl<'a, const O: u8> RECEIVE4_W<'a, O> { + #[doc = "Disable"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(RECEIVE4_A::DISABLED) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(RECEIVE4_A::ENABLED) + } +} +#[doc = "Field `RECEIVE5` reader - Enable or disable interrupt for event RECEIVE\\[5\\]"] +pub type RECEIVE5_R = crate::BitReader; +#[doc = "Enable or disable interrupt for event RECEIVE\\[5\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RECEIVE5_A { + #[doc = "0: Disable"] + DISABLED = 0, + #[doc = "1: Enable"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RECEIVE5_A) -> Self { + variant as u8 != 0 + } +} +impl RECEIVE5_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RECEIVE5_A { + match self.bits { + false => RECEIVE5_A::DISABLED, + true => RECEIVE5_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == RECEIVE5_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == RECEIVE5_A::ENABLED + } +} +#[doc = "Field `RECEIVE5` writer - Enable or disable interrupt for event RECEIVE\\[5\\]"] +pub type RECEIVE5_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTEN_SPEC, RECEIVE5_A, O>; +impl<'a, const O: u8> RECEIVE5_W<'a, O> { + #[doc = "Disable"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(RECEIVE5_A::DISABLED) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(RECEIVE5_A::ENABLED) + } +} +#[doc = "Field `RECEIVE6` reader - Enable or disable interrupt for event RECEIVE\\[6\\]"] +pub type RECEIVE6_R = crate::BitReader; +#[doc = "Enable or disable interrupt for event RECEIVE\\[6\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RECEIVE6_A { + #[doc = "0: Disable"] + DISABLED = 0, + #[doc = "1: Enable"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RECEIVE6_A) -> Self { + variant as u8 != 0 + } +} +impl RECEIVE6_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RECEIVE6_A { + match self.bits { + false => RECEIVE6_A::DISABLED, + true => RECEIVE6_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == RECEIVE6_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == RECEIVE6_A::ENABLED + } +} +#[doc = "Field `RECEIVE6` writer - Enable or disable interrupt for event RECEIVE\\[6\\]"] +pub type RECEIVE6_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTEN_SPEC, RECEIVE6_A, O>; +impl<'a, const O: u8> RECEIVE6_W<'a, O> { + #[doc = "Disable"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(RECEIVE6_A::DISABLED) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(RECEIVE6_A::ENABLED) + } +} +#[doc = "Field `RECEIVE7` reader - Enable or disable interrupt for event RECEIVE\\[7\\]"] +pub type RECEIVE7_R = crate::BitReader; +#[doc = "Enable or disable interrupt for event RECEIVE\\[7\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RECEIVE7_A { + #[doc = "0: Disable"] + DISABLED = 0, + #[doc = "1: Enable"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RECEIVE7_A) -> Self { + variant as u8 != 0 + } +} +impl RECEIVE7_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RECEIVE7_A { + match self.bits { + false => RECEIVE7_A::DISABLED, + true => RECEIVE7_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == RECEIVE7_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == RECEIVE7_A::ENABLED + } +} +#[doc = "Field `RECEIVE7` writer - Enable or disable interrupt for event RECEIVE\\[7\\]"] +pub type RECEIVE7_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTEN_SPEC, RECEIVE7_A, O>; +impl<'a, const O: u8> RECEIVE7_W<'a, O> { + #[doc = "Disable"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(RECEIVE7_A::DISABLED) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(RECEIVE7_A::ENABLED) + } +} +impl R { + #[doc = "Bit 0 - Enable or disable interrupt for event RECEIVE\\[0\\]"] + #[inline(always)] + pub fn receive0(&self) -> RECEIVE0_R { + RECEIVE0_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Enable or disable interrupt for event RECEIVE\\[1\\]"] + #[inline(always)] + pub fn receive1(&self) -> RECEIVE1_R { + RECEIVE1_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Enable or disable interrupt for event RECEIVE\\[2\\]"] + #[inline(always)] + pub fn receive2(&self) -> RECEIVE2_R { + RECEIVE2_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Enable or disable interrupt for event RECEIVE\\[3\\]"] + #[inline(always)] + pub fn receive3(&self) -> RECEIVE3_R { + RECEIVE3_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Enable or disable interrupt for event RECEIVE\\[4\\]"] + #[inline(always)] + pub fn receive4(&self) -> RECEIVE4_R { + RECEIVE4_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Enable or disable interrupt for event RECEIVE\\[5\\]"] + #[inline(always)] + pub fn receive5(&self) -> RECEIVE5_R { + RECEIVE5_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Enable or disable interrupt for event RECEIVE\\[6\\]"] + #[inline(always)] + pub fn receive6(&self) -> RECEIVE6_R { + RECEIVE6_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Enable or disable interrupt for event RECEIVE\\[7\\]"] + #[inline(always)] + pub fn receive7(&self) -> RECEIVE7_R { + RECEIVE7_R::new(((self.bits >> 7) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Enable or disable interrupt for event RECEIVE\\[0\\]"] + #[inline(always)] + pub fn receive0(&mut self) -> RECEIVE0_W<0> { + RECEIVE0_W::new(self) + } + #[doc = "Bit 1 - Enable or disable interrupt for event RECEIVE\\[1\\]"] + #[inline(always)] + pub fn receive1(&mut self) -> RECEIVE1_W<1> { + RECEIVE1_W::new(self) + } + #[doc = "Bit 2 - Enable or disable interrupt for event RECEIVE\\[2\\]"] + #[inline(always)] + pub fn receive2(&mut self) -> RECEIVE2_W<2> { + RECEIVE2_W::new(self) + } + #[doc = "Bit 3 - Enable or disable interrupt for event RECEIVE\\[3\\]"] + #[inline(always)] + pub fn receive3(&mut self) -> RECEIVE3_W<3> { + RECEIVE3_W::new(self) + } + #[doc = "Bit 4 - Enable or disable interrupt for event RECEIVE\\[4\\]"] + #[inline(always)] + pub fn receive4(&mut self) -> RECEIVE4_W<4> { + RECEIVE4_W::new(self) + } + #[doc = "Bit 5 - Enable or disable interrupt for event RECEIVE\\[5\\]"] + #[inline(always)] + pub fn receive5(&mut self) -> RECEIVE5_W<5> { + RECEIVE5_W::new(self) + } + #[doc = "Bit 6 - Enable or disable interrupt for event RECEIVE\\[6\\]"] + #[inline(always)] + pub fn receive6(&mut self) -> RECEIVE6_W<6> { + RECEIVE6_W::new(self) + } + #[doc = "Bit 7 - Enable or disable interrupt for event RECEIVE\\[7\\]"] + #[inline(always)] + pub fn receive7(&mut self) -> RECEIVE7_W<7> { + RECEIVE7_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Enable or disable interrupt\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [inten](index.html) module"] +pub struct INTEN_SPEC; +impl crate::RegisterSpec for INTEN_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [inten::R](R) reader structure"] +impl crate::Readable for INTEN_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [inten::W](W) writer structure"] +impl crate::Writable for INTEN_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTEN to value 0"] +impl crate::Resettable for INTEN_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/ipc_ns/intenclr.rs b/pacs/nrf9120-pac/src/ipc_ns/intenclr.rs new file mode 100644 index 00000000..87e05583 --- /dev/null +++ b/pacs/nrf9120-pac/src/ipc_ns/intenclr.rs @@ -0,0 +1,602 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `RECEIVE0` reader - Write '1' to disable interrupt for event RECEIVE\\[0\\]"] +pub type RECEIVE0_R = crate::BitReader; +#[doc = "Write '1' to disable interrupt for event RECEIVE\\[0\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RECEIVE0_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RECEIVE0_A) -> Self { + variant as u8 != 0 + } +} +impl RECEIVE0_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RECEIVE0_A { + match self.bits { + false => RECEIVE0_A::DISABLED, + true => RECEIVE0_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == RECEIVE0_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == RECEIVE0_A::ENABLED + } +} +#[doc = "Write '1' to disable interrupt for event RECEIVE\\[0\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RECEIVE0_AW { + #[doc = "1: Disable"] + CLEAR = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RECEIVE0_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RECEIVE0` writer - Write '1' to disable interrupt for event RECEIVE\\[0\\]"] +pub type RECEIVE0_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENCLR_SPEC, RECEIVE0_AW, O>; +impl<'a, const O: u8> RECEIVE0_W<'a, O> { + #[doc = "Disable"] + #[inline(always)] + pub fn clear(self) -> &'a mut W { + self.variant(RECEIVE0_AW::CLEAR) + } +} +#[doc = "Field `RECEIVE1` reader - Write '1' to disable interrupt for event RECEIVE\\[1\\]"] +pub type RECEIVE1_R = crate::BitReader; +#[doc = "Write '1' to disable interrupt for event RECEIVE\\[1\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RECEIVE1_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RECEIVE1_A) -> Self { + variant as u8 != 0 + } +} +impl RECEIVE1_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RECEIVE1_A { + match self.bits { + false => RECEIVE1_A::DISABLED, + true => RECEIVE1_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == RECEIVE1_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == RECEIVE1_A::ENABLED + } +} +#[doc = "Write '1' to disable interrupt for event RECEIVE\\[1\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RECEIVE1_AW { + #[doc = "1: Disable"] + CLEAR = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RECEIVE1_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RECEIVE1` writer - Write '1' to disable interrupt for event RECEIVE\\[1\\]"] +pub type RECEIVE1_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENCLR_SPEC, RECEIVE1_AW, O>; +impl<'a, const O: u8> RECEIVE1_W<'a, O> { + #[doc = "Disable"] + #[inline(always)] + pub fn clear(self) -> &'a mut W { + self.variant(RECEIVE1_AW::CLEAR) + } +} +#[doc = "Field `RECEIVE2` reader - Write '1' to disable interrupt for event RECEIVE\\[2\\]"] +pub type RECEIVE2_R = crate::BitReader; +#[doc = "Write '1' to disable interrupt for event RECEIVE\\[2\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RECEIVE2_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RECEIVE2_A) -> Self { + variant as u8 != 0 + } +} +impl RECEIVE2_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RECEIVE2_A { + match self.bits { + false => RECEIVE2_A::DISABLED, + true => RECEIVE2_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == RECEIVE2_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == RECEIVE2_A::ENABLED + } +} +#[doc = "Write '1' to disable interrupt for event RECEIVE\\[2\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RECEIVE2_AW { + #[doc = "1: Disable"] + CLEAR = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RECEIVE2_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RECEIVE2` writer - Write '1' to disable interrupt for event RECEIVE\\[2\\]"] +pub type RECEIVE2_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENCLR_SPEC, RECEIVE2_AW, O>; +impl<'a, const O: u8> RECEIVE2_W<'a, O> { + #[doc = "Disable"] + #[inline(always)] + pub fn clear(self) -> &'a mut W { + self.variant(RECEIVE2_AW::CLEAR) + } +} +#[doc = "Field `RECEIVE3` reader - Write '1' to disable interrupt for event RECEIVE\\[3\\]"] +pub type RECEIVE3_R = crate::BitReader; +#[doc = "Write '1' to disable interrupt for event RECEIVE\\[3\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RECEIVE3_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RECEIVE3_A) -> Self { + variant as u8 != 0 + } +} +impl RECEIVE3_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RECEIVE3_A { + match self.bits { + false => RECEIVE3_A::DISABLED, + true => RECEIVE3_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == RECEIVE3_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == RECEIVE3_A::ENABLED + } +} +#[doc = "Write '1' to disable interrupt for event RECEIVE\\[3\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RECEIVE3_AW { + #[doc = "1: Disable"] + CLEAR = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RECEIVE3_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RECEIVE3` writer - Write '1' to disable interrupt for event RECEIVE\\[3\\]"] +pub type RECEIVE3_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENCLR_SPEC, RECEIVE3_AW, O>; +impl<'a, const O: u8> RECEIVE3_W<'a, O> { + #[doc = "Disable"] + #[inline(always)] + pub fn clear(self) -> &'a mut W { + self.variant(RECEIVE3_AW::CLEAR) + } +} +#[doc = "Field `RECEIVE4` reader - Write '1' to disable interrupt for event RECEIVE\\[4\\]"] +pub type RECEIVE4_R = crate::BitReader; +#[doc = "Write '1' to disable interrupt for event RECEIVE\\[4\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RECEIVE4_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RECEIVE4_A) -> Self { + variant as u8 != 0 + } +} +impl RECEIVE4_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RECEIVE4_A { + match self.bits { + false => RECEIVE4_A::DISABLED, + true => RECEIVE4_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == RECEIVE4_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == RECEIVE4_A::ENABLED + } +} +#[doc = "Write '1' to disable interrupt for event RECEIVE\\[4\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RECEIVE4_AW { + #[doc = "1: Disable"] + CLEAR = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RECEIVE4_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RECEIVE4` writer - Write '1' to disable interrupt for event RECEIVE\\[4\\]"] +pub type RECEIVE4_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENCLR_SPEC, RECEIVE4_AW, O>; +impl<'a, const O: u8> RECEIVE4_W<'a, O> { + #[doc = "Disable"] + #[inline(always)] + pub fn clear(self) -> &'a mut W { + self.variant(RECEIVE4_AW::CLEAR) + } +} +#[doc = "Field `RECEIVE5` reader - Write '1' to disable interrupt for event RECEIVE\\[5\\]"] +pub type RECEIVE5_R = crate::BitReader; +#[doc = "Write '1' to disable interrupt for event RECEIVE\\[5\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RECEIVE5_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RECEIVE5_A) -> Self { + variant as u8 != 0 + } +} +impl RECEIVE5_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RECEIVE5_A { + match self.bits { + false => RECEIVE5_A::DISABLED, + true => RECEIVE5_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == RECEIVE5_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == RECEIVE5_A::ENABLED + } +} +#[doc = "Write '1' to disable interrupt for event RECEIVE\\[5\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RECEIVE5_AW { + #[doc = "1: Disable"] + CLEAR = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RECEIVE5_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RECEIVE5` writer - Write '1' to disable interrupt for event RECEIVE\\[5\\]"] +pub type RECEIVE5_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENCLR_SPEC, RECEIVE5_AW, O>; +impl<'a, const O: u8> RECEIVE5_W<'a, O> { + #[doc = "Disable"] + #[inline(always)] + pub fn clear(self) -> &'a mut W { + self.variant(RECEIVE5_AW::CLEAR) + } +} +#[doc = "Field `RECEIVE6` reader - Write '1' to disable interrupt for event RECEIVE\\[6\\]"] +pub type RECEIVE6_R = crate::BitReader; +#[doc = "Write '1' to disable interrupt for event RECEIVE\\[6\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RECEIVE6_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RECEIVE6_A) -> Self { + variant as u8 != 0 + } +} +impl RECEIVE6_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RECEIVE6_A { + match self.bits { + false => RECEIVE6_A::DISABLED, + true => RECEIVE6_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == RECEIVE6_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == RECEIVE6_A::ENABLED + } +} +#[doc = "Write '1' to disable interrupt for event RECEIVE\\[6\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RECEIVE6_AW { + #[doc = "1: Disable"] + CLEAR = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RECEIVE6_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RECEIVE6` writer - Write '1' to disable interrupt for event RECEIVE\\[6\\]"] +pub type RECEIVE6_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENCLR_SPEC, RECEIVE6_AW, O>; +impl<'a, const O: u8> RECEIVE6_W<'a, O> { + #[doc = "Disable"] + #[inline(always)] + pub fn clear(self) -> &'a mut W { + self.variant(RECEIVE6_AW::CLEAR) + } +} +#[doc = "Field `RECEIVE7` reader - Write '1' to disable interrupt for event RECEIVE\\[7\\]"] +pub type RECEIVE7_R = crate::BitReader; +#[doc = "Write '1' to disable interrupt for event RECEIVE\\[7\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RECEIVE7_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RECEIVE7_A) -> Self { + variant as u8 != 0 + } +} +impl RECEIVE7_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RECEIVE7_A { + match self.bits { + false => RECEIVE7_A::DISABLED, + true => RECEIVE7_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == RECEIVE7_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == RECEIVE7_A::ENABLED + } +} +#[doc = "Write '1' to disable interrupt for event RECEIVE\\[7\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RECEIVE7_AW { + #[doc = "1: Disable"] + CLEAR = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RECEIVE7_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RECEIVE7` writer - Write '1' to disable interrupt for event RECEIVE\\[7\\]"] +pub type RECEIVE7_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENCLR_SPEC, RECEIVE7_AW, O>; +impl<'a, const O: u8> RECEIVE7_W<'a, O> { + #[doc = "Disable"] + #[inline(always)] + pub fn clear(self) -> &'a mut W { + self.variant(RECEIVE7_AW::CLEAR) + } +} +impl R { + #[doc = "Bit 0 - Write '1' to disable interrupt for event RECEIVE\\[0\\]"] + #[inline(always)] + pub fn receive0(&self) -> RECEIVE0_R { + RECEIVE0_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Write '1' to disable interrupt for event RECEIVE\\[1\\]"] + #[inline(always)] + pub fn receive1(&self) -> RECEIVE1_R { + RECEIVE1_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Write '1' to disable interrupt for event RECEIVE\\[2\\]"] + #[inline(always)] + pub fn receive2(&self) -> RECEIVE2_R { + RECEIVE2_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Write '1' to disable interrupt for event RECEIVE\\[3\\]"] + #[inline(always)] + pub fn receive3(&self) -> RECEIVE3_R { + RECEIVE3_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Write '1' to disable interrupt for event RECEIVE\\[4\\]"] + #[inline(always)] + pub fn receive4(&self) -> RECEIVE4_R { + RECEIVE4_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Write '1' to disable interrupt for event RECEIVE\\[5\\]"] + #[inline(always)] + pub fn receive5(&self) -> RECEIVE5_R { + RECEIVE5_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Write '1' to disable interrupt for event RECEIVE\\[6\\]"] + #[inline(always)] + pub fn receive6(&self) -> RECEIVE6_R { + RECEIVE6_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Write '1' to disable interrupt for event RECEIVE\\[7\\]"] + #[inline(always)] + pub fn receive7(&self) -> RECEIVE7_R { + RECEIVE7_R::new(((self.bits >> 7) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Write '1' to disable interrupt for event RECEIVE\\[0\\]"] + #[inline(always)] + pub fn receive0(&mut self) -> RECEIVE0_W<0> { + RECEIVE0_W::new(self) + } + #[doc = "Bit 1 - Write '1' to disable interrupt for event RECEIVE\\[1\\]"] + #[inline(always)] + pub fn receive1(&mut self) -> RECEIVE1_W<1> { + RECEIVE1_W::new(self) + } + #[doc = "Bit 2 - Write '1' to disable interrupt for event RECEIVE\\[2\\]"] + #[inline(always)] + pub fn receive2(&mut self) -> RECEIVE2_W<2> { + RECEIVE2_W::new(self) + } + #[doc = "Bit 3 - Write '1' to disable interrupt for event RECEIVE\\[3\\]"] + #[inline(always)] + pub fn receive3(&mut self) -> RECEIVE3_W<3> { + RECEIVE3_W::new(self) + } + #[doc = "Bit 4 - Write '1' to disable interrupt for event RECEIVE\\[4\\]"] + #[inline(always)] + pub fn receive4(&mut self) -> RECEIVE4_W<4> { + RECEIVE4_W::new(self) + } + #[doc = "Bit 5 - Write '1' to disable interrupt for event RECEIVE\\[5\\]"] + #[inline(always)] + pub fn receive5(&mut self) -> RECEIVE5_W<5> { + RECEIVE5_W::new(self) + } + #[doc = "Bit 6 - Write '1' to disable interrupt for event RECEIVE\\[6\\]"] + #[inline(always)] + pub fn receive6(&mut self) -> RECEIVE6_W<6> { + RECEIVE6_W::new(self) + } + #[doc = "Bit 7 - Write '1' to disable interrupt for event RECEIVE\\[7\\]"] + #[inline(always)] + pub fn receive7(&mut self) -> RECEIVE7_W<7> { + RECEIVE7_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Disable interrupt\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/ipc_ns/intenset.rs b/pacs/nrf9120-pac/src/ipc_ns/intenset.rs new file mode 100644 index 00000000..33285a19 --- /dev/null +++ b/pacs/nrf9120-pac/src/ipc_ns/intenset.rs @@ -0,0 +1,602 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `RECEIVE0` reader - Write '1' to enable interrupt for event RECEIVE\\[0\\]"] +pub type RECEIVE0_R = crate::BitReader; +#[doc = "Write '1' to enable interrupt for event RECEIVE\\[0\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RECEIVE0_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RECEIVE0_A) -> Self { + variant as u8 != 0 + } +} +impl RECEIVE0_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RECEIVE0_A { + match self.bits { + false => RECEIVE0_A::DISABLED, + true => RECEIVE0_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == RECEIVE0_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == RECEIVE0_A::ENABLED + } +} +#[doc = "Write '1' to enable interrupt for event RECEIVE\\[0\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RECEIVE0_AW { + #[doc = "1: Enable"] + SET = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RECEIVE0_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RECEIVE0` writer - Write '1' to enable interrupt for event RECEIVE\\[0\\]"] +pub type RECEIVE0_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENSET_SPEC, RECEIVE0_AW, O>; +impl<'a, const O: u8> RECEIVE0_W<'a, O> { + #[doc = "Enable"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(RECEIVE0_AW::SET) + } +} +#[doc = "Field `RECEIVE1` reader - Write '1' to enable interrupt for event RECEIVE\\[1\\]"] +pub type RECEIVE1_R = crate::BitReader; +#[doc = "Write '1' to enable interrupt for event RECEIVE\\[1\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RECEIVE1_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RECEIVE1_A) -> Self { + variant as u8 != 0 + } +} +impl RECEIVE1_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RECEIVE1_A { + match self.bits { + false => RECEIVE1_A::DISABLED, + true => RECEIVE1_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == RECEIVE1_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == RECEIVE1_A::ENABLED + } +} +#[doc = "Write '1' to enable interrupt for event RECEIVE\\[1\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RECEIVE1_AW { + #[doc = "1: Enable"] + SET = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RECEIVE1_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RECEIVE1` writer - Write '1' to enable interrupt for event RECEIVE\\[1\\]"] +pub type RECEIVE1_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENSET_SPEC, RECEIVE1_AW, O>; +impl<'a, const O: u8> RECEIVE1_W<'a, O> { + #[doc = "Enable"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(RECEIVE1_AW::SET) + } +} +#[doc = "Field `RECEIVE2` reader - Write '1' to enable interrupt for event RECEIVE\\[2\\]"] +pub type RECEIVE2_R = crate::BitReader; +#[doc = "Write '1' to enable interrupt for event RECEIVE\\[2\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RECEIVE2_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RECEIVE2_A) -> Self { + variant as u8 != 0 + } +} +impl RECEIVE2_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RECEIVE2_A { + match self.bits { + false => RECEIVE2_A::DISABLED, + true => RECEIVE2_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == RECEIVE2_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == RECEIVE2_A::ENABLED + } +} +#[doc = "Write '1' to enable interrupt for event RECEIVE\\[2\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RECEIVE2_AW { + #[doc = "1: Enable"] + SET = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RECEIVE2_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RECEIVE2` writer - Write '1' to enable interrupt for event RECEIVE\\[2\\]"] +pub type RECEIVE2_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENSET_SPEC, RECEIVE2_AW, O>; +impl<'a, const O: u8> RECEIVE2_W<'a, O> { + #[doc = "Enable"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(RECEIVE2_AW::SET) + } +} +#[doc = "Field `RECEIVE3` reader - Write '1' to enable interrupt for event RECEIVE\\[3\\]"] +pub type RECEIVE3_R = crate::BitReader; +#[doc = "Write '1' to enable interrupt for event RECEIVE\\[3\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RECEIVE3_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RECEIVE3_A) -> Self { + variant as u8 != 0 + } +} +impl RECEIVE3_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RECEIVE3_A { + match self.bits { + false => RECEIVE3_A::DISABLED, + true => RECEIVE3_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == RECEIVE3_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == RECEIVE3_A::ENABLED + } +} +#[doc = "Write '1' to enable interrupt for event RECEIVE\\[3\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RECEIVE3_AW { + #[doc = "1: Enable"] + SET = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RECEIVE3_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RECEIVE3` writer - Write '1' to enable interrupt for event RECEIVE\\[3\\]"] +pub type RECEIVE3_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENSET_SPEC, RECEIVE3_AW, O>; +impl<'a, const O: u8> RECEIVE3_W<'a, O> { + #[doc = "Enable"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(RECEIVE3_AW::SET) + } +} +#[doc = "Field `RECEIVE4` reader - Write '1' to enable interrupt for event RECEIVE\\[4\\]"] +pub type RECEIVE4_R = crate::BitReader; +#[doc = "Write '1' to enable interrupt for event RECEIVE\\[4\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RECEIVE4_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RECEIVE4_A) -> Self { + variant as u8 != 0 + } +} +impl RECEIVE4_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RECEIVE4_A { + match self.bits { + false => RECEIVE4_A::DISABLED, + true => RECEIVE4_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == RECEIVE4_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == RECEIVE4_A::ENABLED + } +} +#[doc = "Write '1' to enable interrupt for event RECEIVE\\[4\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RECEIVE4_AW { + #[doc = "1: Enable"] + SET = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RECEIVE4_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RECEIVE4` writer - Write '1' to enable interrupt for event RECEIVE\\[4\\]"] +pub type RECEIVE4_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENSET_SPEC, RECEIVE4_AW, O>; +impl<'a, const O: u8> RECEIVE4_W<'a, O> { + #[doc = "Enable"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(RECEIVE4_AW::SET) + } +} +#[doc = "Field `RECEIVE5` reader - Write '1' to enable interrupt for event RECEIVE\\[5\\]"] +pub type RECEIVE5_R = crate::BitReader; +#[doc = "Write '1' to enable interrupt for event RECEIVE\\[5\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RECEIVE5_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RECEIVE5_A) -> Self { + variant as u8 != 0 + } +} +impl RECEIVE5_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RECEIVE5_A { + match self.bits { + false => RECEIVE5_A::DISABLED, + true => RECEIVE5_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == RECEIVE5_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == RECEIVE5_A::ENABLED + } +} +#[doc = "Write '1' to enable interrupt for event RECEIVE\\[5\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RECEIVE5_AW { + #[doc = "1: Enable"] + SET = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RECEIVE5_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RECEIVE5` writer - Write '1' to enable interrupt for event RECEIVE\\[5\\]"] +pub type RECEIVE5_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENSET_SPEC, RECEIVE5_AW, O>; +impl<'a, const O: u8> RECEIVE5_W<'a, O> { + #[doc = "Enable"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(RECEIVE5_AW::SET) + } +} +#[doc = "Field `RECEIVE6` reader - Write '1' to enable interrupt for event RECEIVE\\[6\\]"] +pub type RECEIVE6_R = crate::BitReader; +#[doc = "Write '1' to enable interrupt for event RECEIVE\\[6\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RECEIVE6_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RECEIVE6_A) -> Self { + variant as u8 != 0 + } +} +impl RECEIVE6_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RECEIVE6_A { + match self.bits { + false => RECEIVE6_A::DISABLED, + true => RECEIVE6_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == RECEIVE6_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == RECEIVE6_A::ENABLED + } +} +#[doc = "Write '1' to enable interrupt for event RECEIVE\\[6\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RECEIVE6_AW { + #[doc = "1: Enable"] + SET = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RECEIVE6_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RECEIVE6` writer - Write '1' to enable interrupt for event RECEIVE\\[6\\]"] +pub type RECEIVE6_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENSET_SPEC, RECEIVE6_AW, O>; +impl<'a, const O: u8> RECEIVE6_W<'a, O> { + #[doc = "Enable"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(RECEIVE6_AW::SET) + } +} +#[doc = "Field `RECEIVE7` reader - Write '1' to enable interrupt for event RECEIVE\\[7\\]"] +pub type RECEIVE7_R = crate::BitReader; +#[doc = "Write '1' to enable interrupt for event RECEIVE\\[7\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RECEIVE7_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RECEIVE7_A) -> Self { + variant as u8 != 0 + } +} +impl RECEIVE7_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RECEIVE7_A { + match self.bits { + false => RECEIVE7_A::DISABLED, + true => RECEIVE7_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == RECEIVE7_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == RECEIVE7_A::ENABLED + } +} +#[doc = "Write '1' to enable interrupt for event RECEIVE\\[7\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RECEIVE7_AW { + #[doc = "1: Enable"] + SET = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RECEIVE7_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RECEIVE7` writer - Write '1' to enable interrupt for event RECEIVE\\[7\\]"] +pub type RECEIVE7_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENSET_SPEC, RECEIVE7_AW, O>; +impl<'a, const O: u8> RECEIVE7_W<'a, O> { + #[doc = "Enable"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(RECEIVE7_AW::SET) + } +} +impl R { + #[doc = "Bit 0 - Write '1' to enable interrupt for event RECEIVE\\[0\\]"] + #[inline(always)] + pub fn receive0(&self) -> RECEIVE0_R { + RECEIVE0_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Write '1' to enable interrupt for event RECEIVE\\[1\\]"] + #[inline(always)] + pub fn receive1(&self) -> RECEIVE1_R { + RECEIVE1_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Write '1' to enable interrupt for event RECEIVE\\[2\\]"] + #[inline(always)] + pub fn receive2(&self) -> RECEIVE2_R { + RECEIVE2_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Write '1' to enable interrupt for event RECEIVE\\[3\\]"] + #[inline(always)] + pub fn receive3(&self) -> RECEIVE3_R { + RECEIVE3_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Write '1' to enable interrupt for event RECEIVE\\[4\\]"] + #[inline(always)] + pub fn receive4(&self) -> RECEIVE4_R { + RECEIVE4_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Write '1' to enable interrupt for event RECEIVE\\[5\\]"] + #[inline(always)] + pub fn receive5(&self) -> RECEIVE5_R { + RECEIVE5_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Write '1' to enable interrupt for event RECEIVE\\[6\\]"] + #[inline(always)] + pub fn receive6(&self) -> RECEIVE6_R { + RECEIVE6_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Write '1' to enable interrupt for event RECEIVE\\[7\\]"] + #[inline(always)] + pub fn receive7(&self) -> RECEIVE7_R { + RECEIVE7_R::new(((self.bits >> 7) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Write '1' to enable interrupt for event RECEIVE\\[0\\]"] + #[inline(always)] + pub fn receive0(&mut self) -> RECEIVE0_W<0> { + RECEIVE0_W::new(self) + } + #[doc = "Bit 1 - Write '1' to enable interrupt for event RECEIVE\\[1\\]"] + #[inline(always)] + pub fn receive1(&mut self) -> RECEIVE1_W<1> { + RECEIVE1_W::new(self) + } + #[doc = "Bit 2 - Write '1' to enable interrupt for event RECEIVE\\[2\\]"] + #[inline(always)] + pub fn receive2(&mut self) -> RECEIVE2_W<2> { + RECEIVE2_W::new(self) + } + #[doc = "Bit 3 - Write '1' to enable interrupt for event RECEIVE\\[3\\]"] + #[inline(always)] + pub fn receive3(&mut self) -> RECEIVE3_W<3> { + RECEIVE3_W::new(self) + } + #[doc = "Bit 4 - Write '1' to enable interrupt for event RECEIVE\\[4\\]"] + #[inline(always)] + pub fn receive4(&mut self) -> RECEIVE4_W<4> { + RECEIVE4_W::new(self) + } + #[doc = "Bit 5 - Write '1' to enable interrupt for event RECEIVE\\[5\\]"] + #[inline(always)] + pub fn receive5(&mut self) -> RECEIVE5_W<5> { + RECEIVE5_W::new(self) + } + #[doc = "Bit 6 - Write '1' to enable interrupt for event RECEIVE\\[6\\]"] + #[inline(always)] + pub fn receive6(&mut self) -> RECEIVE6_W<6> { + RECEIVE6_W::new(self) + } + #[doc = "Bit 7 - Write '1' to enable interrupt for event RECEIVE\\[7\\]"] + #[inline(always)] + pub fn receive7(&mut self) -> RECEIVE7_W<7> { + RECEIVE7_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Enable interrupt\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/ipc_ns/intpend.rs b/pacs/nrf9120-pac/src/ipc_ns/intpend.rs new file mode 100644 index 00000000..0ea035ed --- /dev/null +++ b/pacs/nrf9120-pac/src/ipc_ns/intpend.rs @@ -0,0 +1,361 @@ +#[doc = "Register `INTPEND` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `RECEIVE0` reader - Read pending status of interrupt for event RECEIVE\\[0\\]"] +pub type RECEIVE0_R = crate::BitReader; +#[doc = "Read pending status of interrupt for event RECEIVE\\[0\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RECEIVE0_A { + #[doc = "0: Read: Not pending"] + NOT_PENDING = 0, + #[doc = "1: Read: Pending"] + PENDING = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RECEIVE0_A) -> Self { + variant as u8 != 0 + } +} +impl RECEIVE0_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RECEIVE0_A { + match self.bits { + false => RECEIVE0_A::NOT_PENDING, + true => RECEIVE0_A::PENDING, + } + } + #[doc = "Checks if the value of the field is `NOT_PENDING`"] + #[inline(always)] + pub fn is_not_pending(&self) -> bool { + *self == RECEIVE0_A::NOT_PENDING + } + #[doc = "Checks if the value of the field is `PENDING`"] + #[inline(always)] + pub fn is_pending(&self) -> bool { + *self == RECEIVE0_A::PENDING + } +} +#[doc = "Field `RECEIVE1` reader - Read pending status of interrupt for event RECEIVE\\[1\\]"] +pub type RECEIVE1_R = crate::BitReader; +#[doc = "Read pending status of interrupt for event RECEIVE\\[1\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RECEIVE1_A { + #[doc = "0: Read: Not pending"] + NOT_PENDING = 0, + #[doc = "1: Read: Pending"] + PENDING = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RECEIVE1_A) -> Self { + variant as u8 != 0 + } +} +impl RECEIVE1_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RECEIVE1_A { + match self.bits { + false => RECEIVE1_A::NOT_PENDING, + true => RECEIVE1_A::PENDING, + } + } + #[doc = "Checks if the value of the field is `NOT_PENDING`"] + #[inline(always)] + pub fn is_not_pending(&self) -> bool { + *self == RECEIVE1_A::NOT_PENDING + } + #[doc = "Checks if the value of the field is `PENDING`"] + #[inline(always)] + pub fn is_pending(&self) -> bool { + *self == RECEIVE1_A::PENDING + } +} +#[doc = "Field `RECEIVE2` reader - Read pending status of interrupt for event RECEIVE\\[2\\]"] +pub type RECEIVE2_R = crate::BitReader; +#[doc = "Read pending status of interrupt for event RECEIVE\\[2\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RECEIVE2_A { + #[doc = "0: Read: Not pending"] + NOT_PENDING = 0, + #[doc = "1: Read: Pending"] + PENDING = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RECEIVE2_A) -> Self { + variant as u8 != 0 + } +} +impl RECEIVE2_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RECEIVE2_A { + match self.bits { + false => RECEIVE2_A::NOT_PENDING, + true => RECEIVE2_A::PENDING, + } + } + #[doc = "Checks if the value of the field is `NOT_PENDING`"] + #[inline(always)] + pub fn is_not_pending(&self) -> bool { + *self == RECEIVE2_A::NOT_PENDING + } + #[doc = "Checks if the value of the field is `PENDING`"] + #[inline(always)] + pub fn is_pending(&self) -> bool { + *self == RECEIVE2_A::PENDING + } +} +#[doc = "Field `RECEIVE3` reader - Read pending status of interrupt for event RECEIVE\\[3\\]"] +pub type RECEIVE3_R = crate::BitReader; +#[doc = "Read pending status of interrupt for event RECEIVE\\[3\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RECEIVE3_A { + #[doc = "0: Read: Not pending"] + NOT_PENDING = 0, + #[doc = "1: Read: Pending"] + PENDING = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RECEIVE3_A) -> Self { + variant as u8 != 0 + } +} +impl RECEIVE3_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RECEIVE3_A { + match self.bits { + false => RECEIVE3_A::NOT_PENDING, + true => RECEIVE3_A::PENDING, + } + } + #[doc = "Checks if the value of the field is `NOT_PENDING`"] + #[inline(always)] + pub fn is_not_pending(&self) -> bool { + *self == RECEIVE3_A::NOT_PENDING + } + #[doc = "Checks if the value of the field is `PENDING`"] + #[inline(always)] + pub fn is_pending(&self) -> bool { + *self == RECEIVE3_A::PENDING + } +} +#[doc = "Field `RECEIVE4` reader - Read pending status of interrupt for event RECEIVE\\[4\\]"] +pub type RECEIVE4_R = crate::BitReader; +#[doc = "Read pending status of interrupt for event RECEIVE\\[4\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RECEIVE4_A { + #[doc = "0: Read: Not pending"] + NOT_PENDING = 0, + #[doc = "1: Read: Pending"] + PENDING = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RECEIVE4_A) -> Self { + variant as u8 != 0 + } +} +impl RECEIVE4_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RECEIVE4_A { + match self.bits { + false => RECEIVE4_A::NOT_PENDING, + true => RECEIVE4_A::PENDING, + } + } + #[doc = "Checks if the value of the field is `NOT_PENDING`"] + #[inline(always)] + pub fn is_not_pending(&self) -> bool { + *self == RECEIVE4_A::NOT_PENDING + } + #[doc = "Checks if the value of the field is `PENDING`"] + #[inline(always)] + pub fn is_pending(&self) -> bool { + *self == RECEIVE4_A::PENDING + } +} +#[doc = "Field `RECEIVE5` reader - Read pending status of interrupt for event RECEIVE\\[5\\]"] +pub type RECEIVE5_R = crate::BitReader; +#[doc = "Read pending status of interrupt for event RECEIVE\\[5\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RECEIVE5_A { + #[doc = "0: Read: Not pending"] + NOT_PENDING = 0, + #[doc = "1: Read: Pending"] + PENDING = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RECEIVE5_A) -> Self { + variant as u8 != 0 + } +} +impl RECEIVE5_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RECEIVE5_A { + match self.bits { + false => RECEIVE5_A::NOT_PENDING, + true => RECEIVE5_A::PENDING, + } + } + #[doc = "Checks if the value of the field is `NOT_PENDING`"] + #[inline(always)] + pub fn is_not_pending(&self) -> bool { + *self == RECEIVE5_A::NOT_PENDING + } + #[doc = "Checks if the value of the field is `PENDING`"] + #[inline(always)] + pub fn is_pending(&self) -> bool { + *self == RECEIVE5_A::PENDING + } +} +#[doc = "Field `RECEIVE6` reader - Read pending status of interrupt for event RECEIVE\\[6\\]"] +pub type RECEIVE6_R = crate::BitReader; +#[doc = "Read pending status of interrupt for event RECEIVE\\[6\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RECEIVE6_A { + #[doc = "0: Read: Not pending"] + NOT_PENDING = 0, + #[doc = "1: Read: Pending"] + PENDING = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RECEIVE6_A) -> Self { + variant as u8 != 0 + } +} +impl RECEIVE6_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RECEIVE6_A { + match self.bits { + false => RECEIVE6_A::NOT_PENDING, + true => RECEIVE6_A::PENDING, + } + } + #[doc = "Checks if the value of the field is `NOT_PENDING`"] + #[inline(always)] + pub fn is_not_pending(&self) -> bool { + *self == RECEIVE6_A::NOT_PENDING + } + #[doc = "Checks if the value of the field is `PENDING`"] + #[inline(always)] + pub fn is_pending(&self) -> bool { + *self == RECEIVE6_A::PENDING + } +} +#[doc = "Field `RECEIVE7` reader - Read pending status of interrupt for event RECEIVE\\[7\\]"] +pub type RECEIVE7_R = crate::BitReader; +#[doc = "Read pending status of interrupt for event RECEIVE\\[7\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RECEIVE7_A { + #[doc = "0: Read: Not pending"] + NOT_PENDING = 0, + #[doc = "1: Read: Pending"] + PENDING = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RECEIVE7_A) -> Self { + variant as u8 != 0 + } +} +impl RECEIVE7_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RECEIVE7_A { + match self.bits { + false => RECEIVE7_A::NOT_PENDING, + true => RECEIVE7_A::PENDING, + } + } + #[doc = "Checks if the value of the field is `NOT_PENDING`"] + #[inline(always)] + pub fn is_not_pending(&self) -> bool { + *self == RECEIVE7_A::NOT_PENDING + } + #[doc = "Checks if the value of the field is `PENDING`"] + #[inline(always)] + pub fn is_pending(&self) -> bool { + *self == RECEIVE7_A::PENDING + } +} +impl R { + #[doc = "Bit 0 - Read pending status of interrupt for event RECEIVE\\[0\\]"] + #[inline(always)] + pub fn receive0(&self) -> RECEIVE0_R { + RECEIVE0_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Read pending status of interrupt for event RECEIVE\\[1\\]"] + #[inline(always)] + pub fn receive1(&self) -> RECEIVE1_R { + RECEIVE1_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Read pending status of interrupt for event RECEIVE\\[2\\]"] + #[inline(always)] + pub fn receive2(&self) -> RECEIVE2_R { + RECEIVE2_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Read pending status of interrupt for event RECEIVE\\[3\\]"] + #[inline(always)] + pub fn receive3(&self) -> RECEIVE3_R { + RECEIVE3_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Read pending status of interrupt for event RECEIVE\\[4\\]"] + #[inline(always)] + pub fn receive4(&self) -> RECEIVE4_R { + RECEIVE4_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Read pending status of interrupt for event RECEIVE\\[5\\]"] + #[inline(always)] + pub fn receive5(&self) -> RECEIVE5_R { + RECEIVE5_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Read pending status of interrupt for event RECEIVE\\[6\\]"] + #[inline(always)] + pub fn receive6(&self) -> RECEIVE6_R { + RECEIVE6_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Read pending status of interrupt for event RECEIVE\\[7\\]"] + #[inline(always)] + pub fn receive7(&self) -> RECEIVE7_R { + RECEIVE7_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[doc = "Pending interrupts\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intpend](index.html) module"] +pub struct INTPEND_SPEC; +impl crate::RegisterSpec for INTPEND_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intpend::R](R) reader structure"] +impl crate::Readable for INTPEND_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets INTPEND to value 0"] +impl crate::Resettable for INTPEND_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/ipc_ns/publish_receive.rs b/pacs/nrf9120-pac/src/ipc_ns/publish_receive.rs new file mode 100644 index 00000000..42b5471a --- /dev/null +++ b/pacs/nrf9120-pac/src/ipc_ns/publish_receive.rs @@ -0,0 +1,145 @@ +#[doc = "Register `PUBLISH_RECEIVE[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PUBLISH_RECEIVE[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CHIDX` reader - DPPI channel that event RECEIVE\\[n\\] +will publish to"] +pub type CHIDX_R = crate::FieldReader; +#[doc = "Field `CHIDX` writer - DPPI channel that event RECEIVE\\[n\\] +will publish to"] +pub type CHIDX_W<'a, const O: u8> = crate::FieldWriter<'a, u32, PUBLISH_RECEIVE_SPEC, u8, u8, 8, O>; +#[doc = "Field `EN` reader - "] +pub type EN_R = crate::BitReader; +#[doc = "\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum EN_A { + #[doc = "0: Disable publishing"] + DISABLED = 0, + #[doc = "1: Enable publishing"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: EN_A) -> Self { + variant as u8 != 0 + } +} +impl EN_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EN_A { + match self.bits { + false => EN_A::DISABLED, + true => EN_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == EN_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == EN_A::ENABLED + } +} +#[doc = "Field `EN` writer - "] +pub type EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, PUBLISH_RECEIVE_SPEC, EN_A, O>; +impl<'a, const O: u8> EN_W<'a, O> { + #[doc = "Disable publishing"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(EN_A::DISABLED) + } + #[doc = "Enable publishing"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(EN_A::ENABLED) + } +} +impl R { + #[doc = "Bits 0:7 - DPPI channel that event RECEIVE\\[n\\] +will publish to"] + #[inline(always)] + pub fn chidx(&self) -> CHIDX_R { + CHIDX_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&self) -> EN_R { + EN_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:7 - DPPI channel that event RECEIVE\\[n\\] +will publish to"] + #[inline(always)] + pub fn chidx(&mut self) -> CHIDX_W<0> { + CHIDX_W::new(self) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&mut self) -> EN_W<31> { + EN_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Description collection: Publish configuration for event RECEIVE\\[n\\]\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [publish_receive](index.html) module"] +pub struct PUBLISH_RECEIVE_SPEC; +impl crate::RegisterSpec for PUBLISH_RECEIVE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [publish_receive::R](R) reader structure"] +impl crate::Readable for PUBLISH_RECEIVE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [publish_receive::W](W) writer structure"] +impl crate::Writable for PUBLISH_RECEIVE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PUBLISH_RECEIVE[%s] +to value 0"] +impl crate::Resettable for PUBLISH_RECEIVE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/ipc_ns/receive_cnf.rs b/pacs/nrf9120-pac/src/ipc_ns/receive_cnf.rs new file mode 100644 index 00000000..91925b88 --- /dev/null +++ b/pacs/nrf9120-pac/src/ipc_ns/receive_cnf.rs @@ -0,0 +1,547 @@ +#[doc = "Register `RECEIVE_CNF[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `RECEIVE_CNF[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CHEN0` reader - Enable subscription to IPC channel 0"] +pub type CHEN0_R = crate::BitReader; +#[doc = "Enable subscription to IPC channel 0\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CHEN0_A { + #[doc = "0: Disable events"] + DISABLE = 0, + #[doc = "1: Enable events"] + ENABLE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CHEN0_A) -> Self { + variant as u8 != 0 + } +} +impl CHEN0_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CHEN0_A { + match self.bits { + false => CHEN0_A::DISABLE, + true => CHEN0_A::ENABLE, + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == CHEN0_A::DISABLE + } + #[doc = "Checks if the value of the field is `ENABLE`"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == CHEN0_A::ENABLE + } +} +#[doc = "Field `CHEN0` writer - Enable subscription to IPC channel 0"] +pub type CHEN0_W<'a, const O: u8> = crate::BitWriter<'a, u32, RECEIVE_CNF_SPEC, CHEN0_A, O>; +impl<'a, const O: u8> CHEN0_W<'a, O> { + #[doc = "Disable events"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(CHEN0_A::DISABLE) + } + #[doc = "Enable events"] + #[inline(always)] + pub fn enable(self) -> &'a mut W { + self.variant(CHEN0_A::ENABLE) + } +} +#[doc = "Field `CHEN1` reader - Enable subscription to IPC channel 1"] +pub type CHEN1_R = crate::BitReader; +#[doc = "Enable subscription to IPC channel 1\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CHEN1_A { + #[doc = "0: Disable events"] + DISABLE = 0, + #[doc = "1: Enable events"] + ENABLE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CHEN1_A) -> Self { + variant as u8 != 0 + } +} +impl CHEN1_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CHEN1_A { + match self.bits { + false => CHEN1_A::DISABLE, + true => CHEN1_A::ENABLE, + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == CHEN1_A::DISABLE + } + #[doc = "Checks if the value of the field is `ENABLE`"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == CHEN1_A::ENABLE + } +} +#[doc = "Field `CHEN1` writer - Enable subscription to IPC channel 1"] +pub type CHEN1_W<'a, const O: u8> = crate::BitWriter<'a, u32, RECEIVE_CNF_SPEC, CHEN1_A, O>; +impl<'a, const O: u8> CHEN1_W<'a, O> { + #[doc = "Disable events"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(CHEN1_A::DISABLE) + } + #[doc = "Enable events"] + #[inline(always)] + pub fn enable(self) -> &'a mut W { + self.variant(CHEN1_A::ENABLE) + } +} +#[doc = "Field `CHEN2` reader - Enable subscription to IPC channel 2"] +pub type CHEN2_R = crate::BitReader; +#[doc = "Enable subscription to IPC channel 2\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CHEN2_A { + #[doc = "0: Disable events"] + DISABLE = 0, + #[doc = "1: Enable events"] + ENABLE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CHEN2_A) -> Self { + variant as u8 != 0 + } +} +impl CHEN2_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CHEN2_A { + match self.bits { + false => CHEN2_A::DISABLE, + true => CHEN2_A::ENABLE, + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == CHEN2_A::DISABLE + } + #[doc = "Checks if the value of the field is `ENABLE`"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == CHEN2_A::ENABLE + } +} +#[doc = "Field `CHEN2` writer - Enable subscription to IPC channel 2"] +pub type CHEN2_W<'a, const O: u8> = crate::BitWriter<'a, u32, RECEIVE_CNF_SPEC, CHEN2_A, O>; +impl<'a, const O: u8> CHEN2_W<'a, O> { + #[doc = "Disable events"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(CHEN2_A::DISABLE) + } + #[doc = "Enable events"] + #[inline(always)] + pub fn enable(self) -> &'a mut W { + self.variant(CHEN2_A::ENABLE) + } +} +#[doc = "Field `CHEN3` reader - Enable subscription to IPC channel 3"] +pub type CHEN3_R = crate::BitReader; +#[doc = "Enable subscription to IPC channel 3\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CHEN3_A { + #[doc = "0: Disable events"] + DISABLE = 0, + #[doc = "1: Enable events"] + ENABLE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CHEN3_A) -> Self { + variant as u8 != 0 + } +} +impl CHEN3_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CHEN3_A { + match self.bits { + false => CHEN3_A::DISABLE, + true => CHEN3_A::ENABLE, + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == CHEN3_A::DISABLE + } + #[doc = "Checks if the value of the field is `ENABLE`"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == CHEN3_A::ENABLE + } +} +#[doc = "Field `CHEN3` writer - Enable subscription to IPC channel 3"] +pub type CHEN3_W<'a, const O: u8> = crate::BitWriter<'a, u32, RECEIVE_CNF_SPEC, CHEN3_A, O>; +impl<'a, const O: u8> CHEN3_W<'a, O> { + #[doc = "Disable events"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(CHEN3_A::DISABLE) + } + #[doc = "Enable events"] + #[inline(always)] + pub fn enable(self) -> &'a mut W { + self.variant(CHEN3_A::ENABLE) + } +} +#[doc = "Field `CHEN4` reader - Enable subscription to IPC channel 4"] +pub type CHEN4_R = crate::BitReader; +#[doc = "Enable subscription to IPC channel 4\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CHEN4_A { + #[doc = "0: Disable events"] + DISABLE = 0, + #[doc = "1: Enable events"] + ENABLE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CHEN4_A) -> Self { + variant as u8 != 0 + } +} +impl CHEN4_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CHEN4_A { + match self.bits { + false => CHEN4_A::DISABLE, + true => CHEN4_A::ENABLE, + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == CHEN4_A::DISABLE + } + #[doc = "Checks if the value of the field is `ENABLE`"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == CHEN4_A::ENABLE + } +} +#[doc = "Field `CHEN4` writer - Enable subscription to IPC channel 4"] +pub type CHEN4_W<'a, const O: u8> = crate::BitWriter<'a, u32, RECEIVE_CNF_SPEC, CHEN4_A, O>; +impl<'a, const O: u8> CHEN4_W<'a, O> { + #[doc = "Disable events"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(CHEN4_A::DISABLE) + } + #[doc = "Enable events"] + #[inline(always)] + pub fn enable(self) -> &'a mut W { + self.variant(CHEN4_A::ENABLE) + } +} +#[doc = "Field `CHEN5` reader - Enable subscription to IPC channel 5"] +pub type CHEN5_R = crate::BitReader; +#[doc = "Enable subscription to IPC channel 5\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CHEN5_A { + #[doc = "0: Disable events"] + DISABLE = 0, + #[doc = "1: Enable events"] + ENABLE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CHEN5_A) -> Self { + variant as u8 != 0 + } +} +impl CHEN5_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CHEN5_A { + match self.bits { + false => CHEN5_A::DISABLE, + true => CHEN5_A::ENABLE, + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == CHEN5_A::DISABLE + } + #[doc = "Checks if the value of the field is `ENABLE`"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == CHEN5_A::ENABLE + } +} +#[doc = "Field `CHEN5` writer - Enable subscription to IPC channel 5"] +pub type CHEN5_W<'a, const O: u8> = crate::BitWriter<'a, u32, RECEIVE_CNF_SPEC, CHEN5_A, O>; +impl<'a, const O: u8> CHEN5_W<'a, O> { + #[doc = "Disable events"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(CHEN5_A::DISABLE) + } + #[doc = "Enable events"] + #[inline(always)] + pub fn enable(self) -> &'a mut W { + self.variant(CHEN5_A::ENABLE) + } +} +#[doc = "Field `CHEN6` reader - Enable subscription to IPC channel 6"] +pub type CHEN6_R = crate::BitReader; +#[doc = "Enable subscription to IPC channel 6\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CHEN6_A { + #[doc = "0: Disable events"] + DISABLE = 0, + #[doc = "1: Enable events"] + ENABLE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CHEN6_A) -> Self { + variant as u8 != 0 + } +} +impl CHEN6_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CHEN6_A { + match self.bits { + false => CHEN6_A::DISABLE, + true => CHEN6_A::ENABLE, + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == CHEN6_A::DISABLE + } + #[doc = "Checks if the value of the field is `ENABLE`"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == CHEN6_A::ENABLE + } +} +#[doc = "Field `CHEN6` writer - Enable subscription to IPC channel 6"] +pub type CHEN6_W<'a, const O: u8> = crate::BitWriter<'a, u32, RECEIVE_CNF_SPEC, CHEN6_A, O>; +impl<'a, const O: u8> CHEN6_W<'a, O> { + #[doc = "Disable events"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(CHEN6_A::DISABLE) + } + #[doc = "Enable events"] + #[inline(always)] + pub fn enable(self) -> &'a mut W { + self.variant(CHEN6_A::ENABLE) + } +} +#[doc = "Field `CHEN7` reader - Enable subscription to IPC channel 7"] +pub type CHEN7_R = crate::BitReader; +#[doc = "Enable subscription to IPC channel 7\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CHEN7_A { + #[doc = "0: Disable events"] + DISABLE = 0, + #[doc = "1: Enable events"] + ENABLE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CHEN7_A) -> Self { + variant as u8 != 0 + } +} +impl CHEN7_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CHEN7_A { + match self.bits { + false => CHEN7_A::DISABLE, + true => CHEN7_A::ENABLE, + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == CHEN7_A::DISABLE + } + #[doc = "Checks if the value of the field is `ENABLE`"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == CHEN7_A::ENABLE + } +} +#[doc = "Field `CHEN7` writer - Enable subscription to IPC channel 7"] +pub type CHEN7_W<'a, const O: u8> = crate::BitWriter<'a, u32, RECEIVE_CNF_SPEC, CHEN7_A, O>; +impl<'a, const O: u8> CHEN7_W<'a, O> { + #[doc = "Disable events"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(CHEN7_A::DISABLE) + } + #[doc = "Enable events"] + #[inline(always)] + pub fn enable(self) -> &'a mut W { + self.variant(CHEN7_A::ENABLE) + } +} +impl R { + #[doc = "Bit 0 - Enable subscription to IPC channel 0"] + #[inline(always)] + pub fn chen0(&self) -> CHEN0_R { + CHEN0_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Enable subscription to IPC channel 1"] + #[inline(always)] + pub fn chen1(&self) -> CHEN1_R { + CHEN1_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Enable subscription to IPC channel 2"] + #[inline(always)] + pub fn chen2(&self) -> CHEN2_R { + CHEN2_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Enable subscription to IPC channel 3"] + #[inline(always)] + pub fn chen3(&self) -> CHEN3_R { + CHEN3_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Enable subscription to IPC channel 4"] + #[inline(always)] + pub fn chen4(&self) -> CHEN4_R { + CHEN4_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Enable subscription to IPC channel 5"] + #[inline(always)] + pub fn chen5(&self) -> CHEN5_R { + CHEN5_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Enable subscription to IPC channel 6"] + #[inline(always)] + pub fn chen6(&self) -> CHEN6_R { + CHEN6_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Enable subscription to IPC channel 7"] + #[inline(always)] + pub fn chen7(&self) -> CHEN7_R { + CHEN7_R::new(((self.bits >> 7) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Enable subscription to IPC channel 0"] + #[inline(always)] + pub fn chen0(&mut self) -> CHEN0_W<0> { + CHEN0_W::new(self) + } + #[doc = "Bit 1 - Enable subscription to IPC channel 1"] + #[inline(always)] + pub fn chen1(&mut self) -> CHEN1_W<1> { + CHEN1_W::new(self) + } + #[doc = "Bit 2 - Enable subscription to IPC channel 2"] + #[inline(always)] + pub fn chen2(&mut self) -> CHEN2_W<2> { + CHEN2_W::new(self) + } + #[doc = "Bit 3 - Enable subscription to IPC channel 3"] + #[inline(always)] + pub fn chen3(&mut self) -> CHEN3_W<3> { + CHEN3_W::new(self) + } + #[doc = "Bit 4 - Enable subscription to IPC channel 4"] + #[inline(always)] + pub fn chen4(&mut self) -> CHEN4_W<4> { + CHEN4_W::new(self) + } + #[doc = "Bit 5 - Enable subscription to IPC channel 5"] + #[inline(always)] + pub fn chen5(&mut self) -> CHEN5_W<5> { + CHEN5_W::new(self) + } + #[doc = "Bit 6 - Enable subscription to IPC channel 6"] + #[inline(always)] + pub fn chen6(&mut self) -> CHEN6_W<6> { + CHEN6_W::new(self) + } + #[doc = "Bit 7 - Enable subscription to IPC channel 7"] + #[inline(always)] + pub fn chen7(&mut self) -> CHEN7_W<7> { + CHEN7_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Description collection: Receive event configuration for EVENTS_RECEIVE\\[n\\]\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [receive_cnf](index.html) module"] +pub struct RECEIVE_CNF_SPEC; +impl crate::RegisterSpec for RECEIVE_CNF_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [receive_cnf::R](R) reader structure"] +impl crate::Readable for RECEIVE_CNF_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [receive_cnf::W](W) writer structure"] +impl crate::Writable for RECEIVE_CNF_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets RECEIVE_CNF[%s] +to value 0"] +impl crate::Resettable for RECEIVE_CNF_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/ipc_ns/send_cnf.rs b/pacs/nrf9120-pac/src/ipc_ns/send_cnf.rs new file mode 100644 index 00000000..0db295fa --- /dev/null +++ b/pacs/nrf9120-pac/src/ipc_ns/send_cnf.rs @@ -0,0 +1,547 @@ +#[doc = "Register `SEND_CNF[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SEND_CNF[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CHEN0` reader - Enable broadcasting on IPC channel 0"] +pub type CHEN0_R = crate::BitReader; +#[doc = "Enable broadcasting on IPC channel 0\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CHEN0_A { + #[doc = "0: Disable broadcast"] + DISABLE = 0, + #[doc = "1: Enable broadcast"] + ENABLE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CHEN0_A) -> Self { + variant as u8 != 0 + } +} +impl CHEN0_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CHEN0_A { + match self.bits { + false => CHEN0_A::DISABLE, + true => CHEN0_A::ENABLE, + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == CHEN0_A::DISABLE + } + #[doc = "Checks if the value of the field is `ENABLE`"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == CHEN0_A::ENABLE + } +} +#[doc = "Field `CHEN0` writer - Enable broadcasting on IPC channel 0"] +pub type CHEN0_W<'a, const O: u8> = crate::BitWriter<'a, u32, SEND_CNF_SPEC, CHEN0_A, O>; +impl<'a, const O: u8> CHEN0_W<'a, O> { + #[doc = "Disable broadcast"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(CHEN0_A::DISABLE) + } + #[doc = "Enable broadcast"] + #[inline(always)] + pub fn enable(self) -> &'a mut W { + self.variant(CHEN0_A::ENABLE) + } +} +#[doc = "Field `CHEN1` reader - Enable broadcasting on IPC channel 1"] +pub type CHEN1_R = crate::BitReader; +#[doc = "Enable broadcasting on IPC channel 1\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CHEN1_A { + #[doc = "0: Disable broadcast"] + DISABLE = 0, + #[doc = "1: Enable broadcast"] + ENABLE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CHEN1_A) -> Self { + variant as u8 != 0 + } +} +impl CHEN1_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CHEN1_A { + match self.bits { + false => CHEN1_A::DISABLE, + true => CHEN1_A::ENABLE, + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == CHEN1_A::DISABLE + } + #[doc = "Checks if the value of the field is `ENABLE`"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == CHEN1_A::ENABLE + } +} +#[doc = "Field `CHEN1` writer - Enable broadcasting on IPC channel 1"] +pub type CHEN1_W<'a, const O: u8> = crate::BitWriter<'a, u32, SEND_CNF_SPEC, CHEN1_A, O>; +impl<'a, const O: u8> CHEN1_W<'a, O> { + #[doc = "Disable broadcast"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(CHEN1_A::DISABLE) + } + #[doc = "Enable broadcast"] + #[inline(always)] + pub fn enable(self) -> &'a mut W { + self.variant(CHEN1_A::ENABLE) + } +} +#[doc = "Field `CHEN2` reader - Enable broadcasting on IPC channel 2"] +pub type CHEN2_R = crate::BitReader; +#[doc = "Enable broadcasting on IPC channel 2\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CHEN2_A { + #[doc = "0: Disable broadcast"] + DISABLE = 0, + #[doc = "1: Enable broadcast"] + ENABLE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CHEN2_A) -> Self { + variant as u8 != 0 + } +} +impl CHEN2_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CHEN2_A { + match self.bits { + false => CHEN2_A::DISABLE, + true => CHEN2_A::ENABLE, + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == CHEN2_A::DISABLE + } + #[doc = "Checks if the value of the field is `ENABLE`"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == CHEN2_A::ENABLE + } +} +#[doc = "Field `CHEN2` writer - Enable broadcasting on IPC channel 2"] +pub type CHEN2_W<'a, const O: u8> = crate::BitWriter<'a, u32, SEND_CNF_SPEC, CHEN2_A, O>; +impl<'a, const O: u8> CHEN2_W<'a, O> { + #[doc = "Disable broadcast"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(CHEN2_A::DISABLE) + } + #[doc = "Enable broadcast"] + #[inline(always)] + pub fn enable(self) -> &'a mut W { + self.variant(CHEN2_A::ENABLE) + } +} +#[doc = "Field `CHEN3` reader - Enable broadcasting on IPC channel 3"] +pub type CHEN3_R = crate::BitReader; +#[doc = "Enable broadcasting on IPC channel 3\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CHEN3_A { + #[doc = "0: Disable broadcast"] + DISABLE = 0, + #[doc = "1: Enable broadcast"] + ENABLE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CHEN3_A) -> Self { + variant as u8 != 0 + } +} +impl CHEN3_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CHEN3_A { + match self.bits { + false => CHEN3_A::DISABLE, + true => CHEN3_A::ENABLE, + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == CHEN3_A::DISABLE + } + #[doc = "Checks if the value of the field is `ENABLE`"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == CHEN3_A::ENABLE + } +} +#[doc = "Field `CHEN3` writer - Enable broadcasting on IPC channel 3"] +pub type CHEN3_W<'a, const O: u8> = crate::BitWriter<'a, u32, SEND_CNF_SPEC, CHEN3_A, O>; +impl<'a, const O: u8> CHEN3_W<'a, O> { + #[doc = "Disable broadcast"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(CHEN3_A::DISABLE) + } + #[doc = "Enable broadcast"] + #[inline(always)] + pub fn enable(self) -> &'a mut W { + self.variant(CHEN3_A::ENABLE) + } +} +#[doc = "Field `CHEN4` reader - Enable broadcasting on IPC channel 4"] +pub type CHEN4_R = crate::BitReader; +#[doc = "Enable broadcasting on IPC channel 4\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CHEN4_A { + #[doc = "0: Disable broadcast"] + DISABLE = 0, + #[doc = "1: Enable broadcast"] + ENABLE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CHEN4_A) -> Self { + variant as u8 != 0 + } +} +impl CHEN4_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CHEN4_A { + match self.bits { + false => CHEN4_A::DISABLE, + true => CHEN4_A::ENABLE, + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == CHEN4_A::DISABLE + } + #[doc = "Checks if the value of the field is `ENABLE`"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == CHEN4_A::ENABLE + } +} +#[doc = "Field `CHEN4` writer - Enable broadcasting on IPC channel 4"] +pub type CHEN4_W<'a, const O: u8> = crate::BitWriter<'a, u32, SEND_CNF_SPEC, CHEN4_A, O>; +impl<'a, const O: u8> CHEN4_W<'a, O> { + #[doc = "Disable broadcast"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(CHEN4_A::DISABLE) + } + #[doc = "Enable broadcast"] + #[inline(always)] + pub fn enable(self) -> &'a mut W { + self.variant(CHEN4_A::ENABLE) + } +} +#[doc = "Field `CHEN5` reader - Enable broadcasting on IPC channel 5"] +pub type CHEN5_R = crate::BitReader; +#[doc = "Enable broadcasting on IPC channel 5\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CHEN5_A { + #[doc = "0: Disable broadcast"] + DISABLE = 0, + #[doc = "1: Enable broadcast"] + ENABLE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CHEN5_A) -> Self { + variant as u8 != 0 + } +} +impl CHEN5_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CHEN5_A { + match self.bits { + false => CHEN5_A::DISABLE, + true => CHEN5_A::ENABLE, + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == CHEN5_A::DISABLE + } + #[doc = "Checks if the value of the field is `ENABLE`"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == CHEN5_A::ENABLE + } +} +#[doc = "Field `CHEN5` writer - Enable broadcasting on IPC channel 5"] +pub type CHEN5_W<'a, const O: u8> = crate::BitWriter<'a, u32, SEND_CNF_SPEC, CHEN5_A, O>; +impl<'a, const O: u8> CHEN5_W<'a, O> { + #[doc = "Disable broadcast"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(CHEN5_A::DISABLE) + } + #[doc = "Enable broadcast"] + #[inline(always)] + pub fn enable(self) -> &'a mut W { + self.variant(CHEN5_A::ENABLE) + } +} +#[doc = "Field `CHEN6` reader - Enable broadcasting on IPC channel 6"] +pub type CHEN6_R = crate::BitReader; +#[doc = "Enable broadcasting on IPC channel 6\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CHEN6_A { + #[doc = "0: Disable broadcast"] + DISABLE = 0, + #[doc = "1: Enable broadcast"] + ENABLE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CHEN6_A) -> Self { + variant as u8 != 0 + } +} +impl CHEN6_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CHEN6_A { + match self.bits { + false => CHEN6_A::DISABLE, + true => CHEN6_A::ENABLE, + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == CHEN6_A::DISABLE + } + #[doc = "Checks if the value of the field is `ENABLE`"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == CHEN6_A::ENABLE + } +} +#[doc = "Field `CHEN6` writer - Enable broadcasting on IPC channel 6"] +pub type CHEN6_W<'a, const O: u8> = crate::BitWriter<'a, u32, SEND_CNF_SPEC, CHEN6_A, O>; +impl<'a, const O: u8> CHEN6_W<'a, O> { + #[doc = "Disable broadcast"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(CHEN6_A::DISABLE) + } + #[doc = "Enable broadcast"] + #[inline(always)] + pub fn enable(self) -> &'a mut W { + self.variant(CHEN6_A::ENABLE) + } +} +#[doc = "Field `CHEN7` reader - Enable broadcasting on IPC channel 7"] +pub type CHEN7_R = crate::BitReader; +#[doc = "Enable broadcasting on IPC channel 7\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CHEN7_A { + #[doc = "0: Disable broadcast"] + DISABLE = 0, + #[doc = "1: Enable broadcast"] + ENABLE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CHEN7_A) -> Self { + variant as u8 != 0 + } +} +impl CHEN7_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CHEN7_A { + match self.bits { + false => CHEN7_A::DISABLE, + true => CHEN7_A::ENABLE, + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == CHEN7_A::DISABLE + } + #[doc = "Checks if the value of the field is `ENABLE`"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == CHEN7_A::ENABLE + } +} +#[doc = "Field `CHEN7` writer - Enable broadcasting on IPC channel 7"] +pub type CHEN7_W<'a, const O: u8> = crate::BitWriter<'a, u32, SEND_CNF_SPEC, CHEN7_A, O>; +impl<'a, const O: u8> CHEN7_W<'a, O> { + #[doc = "Disable broadcast"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(CHEN7_A::DISABLE) + } + #[doc = "Enable broadcast"] + #[inline(always)] + pub fn enable(self) -> &'a mut W { + self.variant(CHEN7_A::ENABLE) + } +} +impl R { + #[doc = "Bit 0 - Enable broadcasting on IPC channel 0"] + #[inline(always)] + pub fn chen0(&self) -> CHEN0_R { + CHEN0_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Enable broadcasting on IPC channel 1"] + #[inline(always)] + pub fn chen1(&self) -> CHEN1_R { + CHEN1_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Enable broadcasting on IPC channel 2"] + #[inline(always)] + pub fn chen2(&self) -> CHEN2_R { + CHEN2_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Enable broadcasting on IPC channel 3"] + #[inline(always)] + pub fn chen3(&self) -> CHEN3_R { + CHEN3_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Enable broadcasting on IPC channel 4"] + #[inline(always)] + pub fn chen4(&self) -> CHEN4_R { + CHEN4_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Enable broadcasting on IPC channel 5"] + #[inline(always)] + pub fn chen5(&self) -> CHEN5_R { + CHEN5_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Enable broadcasting on IPC channel 6"] + #[inline(always)] + pub fn chen6(&self) -> CHEN6_R { + CHEN6_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Enable broadcasting on IPC channel 7"] + #[inline(always)] + pub fn chen7(&self) -> CHEN7_R { + CHEN7_R::new(((self.bits >> 7) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Enable broadcasting on IPC channel 0"] + #[inline(always)] + pub fn chen0(&mut self) -> CHEN0_W<0> { + CHEN0_W::new(self) + } + #[doc = "Bit 1 - Enable broadcasting on IPC channel 1"] + #[inline(always)] + pub fn chen1(&mut self) -> CHEN1_W<1> { + CHEN1_W::new(self) + } + #[doc = "Bit 2 - Enable broadcasting on IPC channel 2"] + #[inline(always)] + pub fn chen2(&mut self) -> CHEN2_W<2> { + CHEN2_W::new(self) + } + #[doc = "Bit 3 - Enable broadcasting on IPC channel 3"] + #[inline(always)] + pub fn chen3(&mut self) -> CHEN3_W<3> { + CHEN3_W::new(self) + } + #[doc = "Bit 4 - Enable broadcasting on IPC channel 4"] + #[inline(always)] + pub fn chen4(&mut self) -> CHEN4_W<4> { + CHEN4_W::new(self) + } + #[doc = "Bit 5 - Enable broadcasting on IPC channel 5"] + #[inline(always)] + pub fn chen5(&mut self) -> CHEN5_W<5> { + CHEN5_W::new(self) + } + #[doc = "Bit 6 - Enable broadcasting on IPC channel 6"] + #[inline(always)] + pub fn chen6(&mut self) -> CHEN6_W<6> { + CHEN6_W::new(self) + } + #[doc = "Bit 7 - Enable broadcasting on IPC channel 7"] + #[inline(always)] + pub fn chen7(&mut self) -> CHEN7_W<7> { + CHEN7_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Description collection: Send event configuration for TASKS_SEND\\[n\\]\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [send_cnf](index.html) module"] +pub struct SEND_CNF_SPEC; +impl crate::RegisterSpec for SEND_CNF_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [send_cnf::R](R) reader structure"] +impl crate::Readable for SEND_CNF_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [send_cnf::W](W) writer structure"] +impl crate::Writable for SEND_CNF_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SEND_CNF[%s] +to value 0"] +impl crate::Resettable for SEND_CNF_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/ipc_ns/subscribe_send.rs b/pacs/nrf9120-pac/src/ipc_ns/subscribe_send.rs new file mode 100644 index 00000000..a8279ae0 --- /dev/null +++ b/pacs/nrf9120-pac/src/ipc_ns/subscribe_send.rs @@ -0,0 +1,145 @@ +#[doc = "Register `SUBSCRIBE_SEND[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SUBSCRIBE_SEND[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CHIDX` reader - DPPI channel that task SEND\\[n\\] +will subscribe to"] +pub type CHIDX_R = crate::FieldReader; +#[doc = "Field `CHIDX` writer - DPPI channel that task SEND\\[n\\] +will subscribe to"] +pub type CHIDX_W<'a, const O: u8> = crate::FieldWriter<'a, u32, SUBSCRIBE_SEND_SPEC, u8, u8, 8, O>; +#[doc = "Field `EN` reader - "] +pub type EN_R = crate::BitReader; +#[doc = "\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum EN_A { + #[doc = "0: Disable subscription"] + DISABLED = 0, + #[doc = "1: Enable subscription"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: EN_A) -> Self { + variant as u8 != 0 + } +} +impl EN_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EN_A { + match self.bits { + false => EN_A::DISABLED, + true => EN_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == EN_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == EN_A::ENABLED + } +} +#[doc = "Field `EN` writer - "] +pub type EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, SUBSCRIBE_SEND_SPEC, EN_A, O>; +impl<'a, const O: u8> EN_W<'a, O> { + #[doc = "Disable subscription"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(EN_A::DISABLED) + } + #[doc = "Enable subscription"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(EN_A::ENABLED) + } +} +impl R { + #[doc = "Bits 0:7 - DPPI channel that task SEND\\[n\\] +will subscribe to"] + #[inline(always)] + pub fn chidx(&self) -> CHIDX_R { + CHIDX_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&self) -> EN_R { + EN_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:7 - DPPI channel that task SEND\\[n\\] +will subscribe to"] + #[inline(always)] + pub fn chidx(&mut self) -> CHIDX_W<0> { + CHIDX_W::new(self) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&mut self) -> EN_W<31> { + EN_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Description collection: Subscribe configuration for task SEND\\[n\\]\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [subscribe_send](index.html) module"] +pub struct SUBSCRIBE_SEND_SPEC; +impl crate::RegisterSpec for SUBSCRIBE_SEND_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [subscribe_send::R](R) reader structure"] +impl crate::Readable for SUBSCRIBE_SEND_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [subscribe_send::W](W) writer structure"] +impl crate::Writable for SUBSCRIBE_SEND_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SUBSCRIBE_SEND[%s] +to value 0"] +impl crate::Resettable for SUBSCRIBE_SEND_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/ipc_ns/tasks_send.rs b/pacs/nrf9120-pac/src/ipc_ns/tasks_send.rs new file mode 100644 index 00000000..1bafcb37 --- /dev/null +++ b/pacs/nrf9120-pac/src/ipc_ns/tasks_send.rs @@ -0,0 +1,73 @@ +#[doc = "Register `TASKS_SEND[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Trigger events on IPC channel enabled in SEND_CNF\\[n\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum TASKS_SEND_AW { + #[doc = "1: Trigger task"] + TRIGGER = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TASKS_SEND_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TASKS_SEND` writer - Trigger events on IPC channel enabled in SEND_CNF\\[n\\]"] +pub type TASKS_SEND_W<'a, const O: u8> = + crate::BitWriter<'a, u32, TASKS_SEND_SPEC, TASKS_SEND_AW, O>; +impl<'a, const O: u8> TASKS_SEND_W<'a, O> { + #[doc = "Trigger task"] + #[inline(always)] + pub fn trigger(self) -> &'a mut W { + self.variant(TASKS_SEND_AW::TRIGGER) + } +} +impl W { + #[doc = "Bit 0 - Trigger events on IPC channel enabled in SEND_CNF\\[n\\]"] + #[inline(always)] + pub fn tasks_send(&mut self) -> TASKS_SEND_W<0> { + TASKS_SEND_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Description collection: Trigger events on IPC channel enabled in SEND_CNF\\[n\\]\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tasks_send](index.html) module"] +pub struct TASKS_SEND_SPEC; +impl crate::RegisterSpec for TASKS_SEND_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [tasks_send::W](W) writer structure"] +impl crate::Writable for TASKS_SEND_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets TASKS_SEND[%s] +to value 0"] +impl crate::Resettable for TASKS_SEND_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/kmu_ns.rs b/pacs/nrf9120-pac/src/kmu_ns.rs new file mode 100644 index 00000000..78632a66 --- /dev/null +++ b/pacs/nrf9120-pac/src/kmu_ns.rs @@ -0,0 +1,68 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Push a key slot over secure APB"] + pub tasks_push_keyslot: TASKS_PUSH_KEYSLOT, + _reserved1: [u8; 0xfc], + #[doc = "0x100 - Key slot successfully pushed over secure APB"] + pub events_keyslot_pushed: EVENTS_KEYSLOT_PUSHED, + #[doc = "0x104 - Key slot has been revoked and cannot be tasked for selection"] + pub events_keyslot_revoked: EVENTS_KEYSLOT_REVOKED, + #[doc = "0x108 - No key slot selected, no destination address defined, or error during push operation"] + pub events_keyslot_error: EVENTS_KEYSLOT_ERROR, + _reserved4: [u8; 0x01f4], + #[doc = "0x300 - Enable or disable interrupt"] + pub inten: INTEN, + #[doc = "0x304 - Enable interrupt"] + pub intenset: INTENSET, + #[doc = "0x308 - Disable interrupt"] + pub intenclr: INTENCLR, + #[doc = "0x30c - Pending interrupts"] + pub intpend: INTPEND, + _reserved8: [u8; 0xfc], + #[doc = "0x40c - Status bits for KMU operation"] + pub status: STATUS, + _reserved9: [u8; 0xf0], + #[doc = "0x500 - Select key slot to be read over AHB or pushed over secure APB when TASKS_PUSH_KEYSLOT is started"] + pub selectkeyslot: SELECTKEYSLOT, +} +#[doc = "TASKS_PUSH_KEYSLOT (w) register accessor: an alias for `Reg`"] +pub type TASKS_PUSH_KEYSLOT = crate::Reg; +#[doc = "Push a key slot over secure APB"] +pub mod tasks_push_keyslot; +#[doc = "EVENTS_KEYSLOT_PUSHED (rw) register accessor: an alias for `Reg`"] +pub type EVENTS_KEYSLOT_PUSHED = crate::Reg; +#[doc = "Key slot successfully pushed over secure APB"] +pub mod events_keyslot_pushed; +#[doc = "EVENTS_KEYSLOT_REVOKED (rw) register accessor: an alias for `Reg`"] +pub type EVENTS_KEYSLOT_REVOKED = crate::Reg; +#[doc = "Key slot has been revoked and cannot be tasked for selection"] +pub mod events_keyslot_revoked; +#[doc = "EVENTS_KEYSLOT_ERROR (rw) register accessor: an alias for `Reg`"] +pub type EVENTS_KEYSLOT_ERROR = crate::Reg; +#[doc = "No key slot selected, no destination address defined, or error during push operation"] +pub mod events_keyslot_error; +#[doc = "INTEN (rw) register accessor: an alias for `Reg`"] +pub type INTEN = crate::Reg; +#[doc = "Enable or disable interrupt"] +pub mod inten; +#[doc = "INTENSET (rw) register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "Enable interrupt"] +pub mod intenset; +#[doc = "INTENCLR (rw) register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "Disable interrupt"] +pub mod intenclr; +#[doc = "INTPEND (r) register accessor: an alias for `Reg`"] +pub type INTPEND = crate::Reg; +#[doc = "Pending interrupts"] +pub mod intpend; +#[doc = "STATUS (r) register accessor: an alias for `Reg`"] +pub type STATUS = crate::Reg; +#[doc = "Status bits for KMU operation"] +pub mod status; +#[doc = "SELECTKEYSLOT (rw) register accessor: an alias for `Reg`"] +pub type SELECTKEYSLOT = crate::Reg; +#[doc = "Select key slot to be read over AHB or pushed over secure APB when TASKS_PUSH_KEYSLOT is started"] +pub mod selectkeyslot; diff --git a/pacs/nrf9120-pac/src/kmu_ns/events_keyslot_error.rs b/pacs/nrf9120-pac/src/kmu_ns/events_keyslot_error.rs new file mode 100644 index 00000000..1481ee64 --- /dev/null +++ b/pacs/nrf9120-pac/src/kmu_ns/events_keyslot_error.rs @@ -0,0 +1,127 @@ +#[doc = "Register `EVENTS_KEYSLOT_ERROR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVENTS_KEYSLOT_ERROR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `EVENTS_KEYSLOT_ERROR` reader - No key slot selected, no destination address defined, or error during push operation"] +pub type EVENTS_KEYSLOT_ERROR_R = crate::BitReader; +#[doc = "No key slot selected, no destination address defined, or error during push operation\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum EVENTS_KEYSLOT_ERROR_A { + #[doc = "0: Event not generated"] + NOT_GENERATED = 0, + #[doc = "1: Event generated"] + GENERATED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: EVENTS_KEYSLOT_ERROR_A) -> Self { + variant as u8 != 0 + } +} +impl EVENTS_KEYSLOT_ERROR_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EVENTS_KEYSLOT_ERROR_A { + match self.bits { + false => EVENTS_KEYSLOT_ERROR_A::NOT_GENERATED, + true => EVENTS_KEYSLOT_ERROR_A::GENERATED, + } + } + #[doc = "Checks if the value of the field is `NOT_GENERATED`"] + #[inline(always)] + pub fn is_not_generated(&self) -> bool { + *self == EVENTS_KEYSLOT_ERROR_A::NOT_GENERATED + } + #[doc = "Checks if the value of the field is `GENERATED`"] + #[inline(always)] + pub fn is_generated(&self) -> bool { + *self == EVENTS_KEYSLOT_ERROR_A::GENERATED + } +} +#[doc = "Field `EVENTS_KEYSLOT_ERROR` writer - No key slot selected, no destination address defined, or error during push operation"] +pub type EVENTS_KEYSLOT_ERROR_W<'a, const O: u8> = + crate::BitWriter<'a, u32, EVENTS_KEYSLOT_ERROR_SPEC, EVENTS_KEYSLOT_ERROR_A, O>; +impl<'a, const O: u8> EVENTS_KEYSLOT_ERROR_W<'a, O> { + #[doc = "Event not generated"] + #[inline(always)] + pub fn not_generated(self) -> &'a mut W { + self.variant(EVENTS_KEYSLOT_ERROR_A::NOT_GENERATED) + } + #[doc = "Event generated"] + #[inline(always)] + pub fn generated(self) -> &'a mut W { + self.variant(EVENTS_KEYSLOT_ERROR_A::GENERATED) + } +} +impl R { + #[doc = "Bit 0 - No key slot selected, no destination address defined, or error during push operation"] + #[inline(always)] + pub fn events_keyslot_error(&self) -> EVENTS_KEYSLOT_ERROR_R { + EVENTS_KEYSLOT_ERROR_R::new((self.bits & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - No key slot selected, no destination address defined, or error during push operation"] + #[inline(always)] + pub fn events_keyslot_error(&mut self) -> EVENTS_KEYSLOT_ERROR_W<0> { + EVENTS_KEYSLOT_ERROR_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "No key slot selected, no destination address defined, or error during push operation\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [events_keyslot_error](index.html) module"] +pub struct EVENTS_KEYSLOT_ERROR_SPEC; +impl crate::RegisterSpec for EVENTS_KEYSLOT_ERROR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [events_keyslot_error::R](R) reader structure"] +impl crate::Readable for EVENTS_KEYSLOT_ERROR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [events_keyslot_error::W](W) writer structure"] +impl crate::Writable for EVENTS_KEYSLOT_ERROR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EVENTS_KEYSLOT_ERROR to value 0"] +impl crate::Resettable for EVENTS_KEYSLOT_ERROR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/kmu_ns/events_keyslot_pushed.rs b/pacs/nrf9120-pac/src/kmu_ns/events_keyslot_pushed.rs new file mode 100644 index 00000000..c2a404c4 --- /dev/null +++ b/pacs/nrf9120-pac/src/kmu_ns/events_keyslot_pushed.rs @@ -0,0 +1,127 @@ +#[doc = "Register `EVENTS_KEYSLOT_PUSHED` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVENTS_KEYSLOT_PUSHED` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `EVENTS_KEYSLOT_PUSHED` reader - Key slot successfully pushed over secure APB"] +pub type EVENTS_KEYSLOT_PUSHED_R = crate::BitReader; +#[doc = "Key slot successfully pushed over secure APB\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum EVENTS_KEYSLOT_PUSHED_A { + #[doc = "0: Event not generated"] + NOT_GENERATED = 0, + #[doc = "1: Event generated"] + GENERATED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: EVENTS_KEYSLOT_PUSHED_A) -> Self { + variant as u8 != 0 + } +} +impl EVENTS_KEYSLOT_PUSHED_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EVENTS_KEYSLOT_PUSHED_A { + match self.bits { + false => EVENTS_KEYSLOT_PUSHED_A::NOT_GENERATED, + true => EVENTS_KEYSLOT_PUSHED_A::GENERATED, + } + } + #[doc = "Checks if the value of the field is `NOT_GENERATED`"] + #[inline(always)] + pub fn is_not_generated(&self) -> bool { + *self == EVENTS_KEYSLOT_PUSHED_A::NOT_GENERATED + } + #[doc = "Checks if the value of the field is `GENERATED`"] + #[inline(always)] + pub fn is_generated(&self) -> bool { + *self == EVENTS_KEYSLOT_PUSHED_A::GENERATED + } +} +#[doc = "Field `EVENTS_KEYSLOT_PUSHED` writer - Key slot successfully pushed over secure APB"] +pub type EVENTS_KEYSLOT_PUSHED_W<'a, const O: u8> = + crate::BitWriter<'a, u32, EVENTS_KEYSLOT_PUSHED_SPEC, EVENTS_KEYSLOT_PUSHED_A, O>; +impl<'a, const O: u8> EVENTS_KEYSLOT_PUSHED_W<'a, O> { + #[doc = "Event not generated"] + #[inline(always)] + pub fn not_generated(self) -> &'a mut W { + self.variant(EVENTS_KEYSLOT_PUSHED_A::NOT_GENERATED) + } + #[doc = "Event generated"] + #[inline(always)] + pub fn generated(self) -> &'a mut W { + self.variant(EVENTS_KEYSLOT_PUSHED_A::GENERATED) + } +} +impl R { + #[doc = "Bit 0 - Key slot successfully pushed over secure APB"] + #[inline(always)] + pub fn events_keyslot_pushed(&self) -> EVENTS_KEYSLOT_PUSHED_R { + EVENTS_KEYSLOT_PUSHED_R::new((self.bits & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Key slot successfully pushed over secure APB"] + #[inline(always)] + pub fn events_keyslot_pushed(&mut self) -> EVENTS_KEYSLOT_PUSHED_W<0> { + EVENTS_KEYSLOT_PUSHED_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Key slot successfully pushed over secure APB\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [events_keyslot_pushed](index.html) module"] +pub struct EVENTS_KEYSLOT_PUSHED_SPEC; +impl crate::RegisterSpec for EVENTS_KEYSLOT_PUSHED_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [events_keyslot_pushed::R](R) reader structure"] +impl crate::Readable for EVENTS_KEYSLOT_PUSHED_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [events_keyslot_pushed::W](W) writer structure"] +impl crate::Writable for EVENTS_KEYSLOT_PUSHED_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EVENTS_KEYSLOT_PUSHED to value 0"] +impl crate::Resettable for EVENTS_KEYSLOT_PUSHED_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/kmu_ns/events_keyslot_revoked.rs b/pacs/nrf9120-pac/src/kmu_ns/events_keyslot_revoked.rs new file mode 100644 index 00000000..af6a4897 --- /dev/null +++ b/pacs/nrf9120-pac/src/kmu_ns/events_keyslot_revoked.rs @@ -0,0 +1,127 @@ +#[doc = "Register `EVENTS_KEYSLOT_REVOKED` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVENTS_KEYSLOT_REVOKED` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `EVENTS_KEYSLOT_REVOKED` reader - Key slot has been revoked and cannot be tasked for selection"] +pub type EVENTS_KEYSLOT_REVOKED_R = crate::BitReader; +#[doc = "Key slot has been revoked and cannot be tasked for selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum EVENTS_KEYSLOT_REVOKED_A { + #[doc = "0: Event not generated"] + NOT_GENERATED = 0, + #[doc = "1: Event generated"] + GENERATED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: EVENTS_KEYSLOT_REVOKED_A) -> Self { + variant as u8 != 0 + } +} +impl EVENTS_KEYSLOT_REVOKED_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EVENTS_KEYSLOT_REVOKED_A { + match self.bits { + false => EVENTS_KEYSLOT_REVOKED_A::NOT_GENERATED, + true => EVENTS_KEYSLOT_REVOKED_A::GENERATED, + } + } + #[doc = "Checks if the value of the field is `NOT_GENERATED`"] + #[inline(always)] + pub fn is_not_generated(&self) -> bool { + *self == EVENTS_KEYSLOT_REVOKED_A::NOT_GENERATED + } + #[doc = "Checks if the value of the field is `GENERATED`"] + #[inline(always)] + pub fn is_generated(&self) -> bool { + *self == EVENTS_KEYSLOT_REVOKED_A::GENERATED + } +} +#[doc = "Field `EVENTS_KEYSLOT_REVOKED` writer - Key slot has been revoked and cannot be tasked for selection"] +pub type EVENTS_KEYSLOT_REVOKED_W<'a, const O: u8> = + crate::BitWriter<'a, u32, EVENTS_KEYSLOT_REVOKED_SPEC, EVENTS_KEYSLOT_REVOKED_A, O>; +impl<'a, const O: u8> EVENTS_KEYSLOT_REVOKED_W<'a, O> { + #[doc = "Event not generated"] + #[inline(always)] + pub fn not_generated(self) -> &'a mut W { + self.variant(EVENTS_KEYSLOT_REVOKED_A::NOT_GENERATED) + } + #[doc = "Event generated"] + #[inline(always)] + pub fn generated(self) -> &'a mut W { + self.variant(EVENTS_KEYSLOT_REVOKED_A::GENERATED) + } +} +impl R { + #[doc = "Bit 0 - Key slot has been revoked and cannot be tasked for selection"] + #[inline(always)] + pub fn events_keyslot_revoked(&self) -> EVENTS_KEYSLOT_REVOKED_R { + EVENTS_KEYSLOT_REVOKED_R::new((self.bits & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Key slot has been revoked and cannot be tasked for selection"] + #[inline(always)] + pub fn events_keyslot_revoked(&mut self) -> EVENTS_KEYSLOT_REVOKED_W<0> { + EVENTS_KEYSLOT_REVOKED_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Key slot has been revoked and cannot be tasked for selection\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [events_keyslot_revoked](index.html) module"] +pub struct EVENTS_KEYSLOT_REVOKED_SPEC; +impl crate::RegisterSpec for EVENTS_KEYSLOT_REVOKED_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [events_keyslot_revoked::R](R) reader structure"] +impl crate::Readable for EVENTS_KEYSLOT_REVOKED_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [events_keyslot_revoked::W](W) writer structure"] +impl crate::Writable for EVENTS_KEYSLOT_REVOKED_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EVENTS_KEYSLOT_REVOKED to value 0"] +impl crate::Resettable for EVENTS_KEYSLOT_REVOKED_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/kmu_ns/inten.rs b/pacs/nrf9120-pac/src/kmu_ns/inten.rs new file mode 100644 index 00000000..cc0913b8 --- /dev/null +++ b/pacs/nrf9120-pac/src/kmu_ns/inten.rs @@ -0,0 +1,249 @@ +#[doc = "Register `INTEN` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTEN` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `KEYSLOT_PUSHED` reader - Enable or disable interrupt for event KEYSLOT_PUSHED"] +pub type KEYSLOT_PUSHED_R = crate::BitReader; +#[doc = "Enable or disable interrupt for event KEYSLOT_PUSHED\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum KEYSLOT_PUSHED_A { + #[doc = "0: Disable"] + DISABLED = 0, + #[doc = "1: Enable"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: KEYSLOT_PUSHED_A) -> Self { + variant as u8 != 0 + } +} +impl KEYSLOT_PUSHED_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> KEYSLOT_PUSHED_A { + match self.bits { + false => KEYSLOT_PUSHED_A::DISABLED, + true => KEYSLOT_PUSHED_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == KEYSLOT_PUSHED_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == KEYSLOT_PUSHED_A::ENABLED + } +} +#[doc = "Field `KEYSLOT_PUSHED` writer - Enable or disable interrupt for event KEYSLOT_PUSHED"] +pub type KEYSLOT_PUSHED_W<'a, const O: u8> = + crate::BitWriter<'a, u32, INTEN_SPEC, KEYSLOT_PUSHED_A, O>; +impl<'a, const O: u8> KEYSLOT_PUSHED_W<'a, O> { + #[doc = "Disable"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(KEYSLOT_PUSHED_A::DISABLED) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(KEYSLOT_PUSHED_A::ENABLED) + } +} +#[doc = "Field `KEYSLOT_REVOKED` reader - Enable or disable interrupt for event KEYSLOT_REVOKED"] +pub type KEYSLOT_REVOKED_R = crate::BitReader; +#[doc = "Enable or disable interrupt for event KEYSLOT_REVOKED\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum KEYSLOT_REVOKED_A { + #[doc = "0: Disable"] + DISABLED = 0, + #[doc = "1: Enable"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: KEYSLOT_REVOKED_A) -> Self { + variant as u8 != 0 + } +} +impl KEYSLOT_REVOKED_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> KEYSLOT_REVOKED_A { + match self.bits { + false => KEYSLOT_REVOKED_A::DISABLED, + true => KEYSLOT_REVOKED_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == KEYSLOT_REVOKED_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == KEYSLOT_REVOKED_A::ENABLED + } +} +#[doc = "Field `KEYSLOT_REVOKED` writer - Enable or disable interrupt for event KEYSLOT_REVOKED"] +pub type KEYSLOT_REVOKED_W<'a, const O: u8> = + crate::BitWriter<'a, u32, INTEN_SPEC, KEYSLOT_REVOKED_A, O>; +impl<'a, const O: u8> KEYSLOT_REVOKED_W<'a, O> { + #[doc = "Disable"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(KEYSLOT_REVOKED_A::DISABLED) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(KEYSLOT_REVOKED_A::ENABLED) + } +} +#[doc = "Field `KEYSLOT_ERROR` reader - Enable or disable interrupt for event KEYSLOT_ERROR"] +pub type KEYSLOT_ERROR_R = crate::BitReader; +#[doc = "Enable or disable interrupt for event KEYSLOT_ERROR\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum KEYSLOT_ERROR_A { + #[doc = "0: Disable"] + DISABLED = 0, + #[doc = "1: Enable"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: KEYSLOT_ERROR_A) -> Self { + variant as u8 != 0 + } +} +impl KEYSLOT_ERROR_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> KEYSLOT_ERROR_A { + match self.bits { + false => KEYSLOT_ERROR_A::DISABLED, + true => KEYSLOT_ERROR_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == KEYSLOT_ERROR_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == KEYSLOT_ERROR_A::ENABLED + } +} +#[doc = "Field `KEYSLOT_ERROR` writer - Enable or disable interrupt for event KEYSLOT_ERROR"] +pub type KEYSLOT_ERROR_W<'a, const O: u8> = + crate::BitWriter<'a, u32, INTEN_SPEC, KEYSLOT_ERROR_A, O>; +impl<'a, const O: u8> KEYSLOT_ERROR_W<'a, O> { + #[doc = "Disable"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(KEYSLOT_ERROR_A::DISABLED) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(KEYSLOT_ERROR_A::ENABLED) + } +} +impl R { + #[doc = "Bit 0 - Enable or disable interrupt for event KEYSLOT_PUSHED"] + #[inline(always)] + pub fn keyslot_pushed(&self) -> KEYSLOT_PUSHED_R { + KEYSLOT_PUSHED_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Enable or disable interrupt for event KEYSLOT_REVOKED"] + #[inline(always)] + pub fn keyslot_revoked(&self) -> KEYSLOT_REVOKED_R { + KEYSLOT_REVOKED_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Enable or disable interrupt for event KEYSLOT_ERROR"] + #[inline(always)] + pub fn keyslot_error(&self) -> KEYSLOT_ERROR_R { + KEYSLOT_ERROR_R::new(((self.bits >> 2) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Enable or disable interrupt for event KEYSLOT_PUSHED"] + #[inline(always)] + pub fn keyslot_pushed(&mut self) -> KEYSLOT_PUSHED_W<0> { + KEYSLOT_PUSHED_W::new(self) + } + #[doc = "Bit 1 - Enable or disable interrupt for event KEYSLOT_REVOKED"] + #[inline(always)] + pub fn keyslot_revoked(&mut self) -> KEYSLOT_REVOKED_W<1> { + KEYSLOT_REVOKED_W::new(self) + } + #[doc = "Bit 2 - Enable or disable interrupt for event KEYSLOT_ERROR"] + #[inline(always)] + pub fn keyslot_error(&mut self) -> KEYSLOT_ERROR_W<2> { + KEYSLOT_ERROR_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Enable or disable interrupt\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [inten](index.html) module"] +pub struct INTEN_SPEC; +impl crate::RegisterSpec for INTEN_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [inten::R](R) reader structure"] +impl crate::Readable for INTEN_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [inten::W](W) writer structure"] +impl crate::Writable for INTEN_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTEN to value 0"] +impl crate::Resettable for INTEN_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/kmu_ns/intenclr.rs b/pacs/nrf9120-pac/src/kmu_ns/intenclr.rs new file mode 100644 index 00000000..b63536a8 --- /dev/null +++ b/pacs/nrf9120-pac/src/kmu_ns/intenclr.rs @@ -0,0 +1,270 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `KEYSLOT_PUSHED` reader - Write '1' to disable interrupt for event KEYSLOT_PUSHED"] +pub type KEYSLOT_PUSHED_R = crate::BitReader; +#[doc = "Write '1' to disable interrupt for event KEYSLOT_PUSHED\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum KEYSLOT_PUSHED_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: KEYSLOT_PUSHED_A) -> Self { + variant as u8 != 0 + } +} +impl KEYSLOT_PUSHED_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> KEYSLOT_PUSHED_A { + match self.bits { + false => KEYSLOT_PUSHED_A::DISABLED, + true => KEYSLOT_PUSHED_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == KEYSLOT_PUSHED_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == KEYSLOT_PUSHED_A::ENABLED + } +} +#[doc = "Write '1' to disable interrupt for event KEYSLOT_PUSHED\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum KEYSLOT_PUSHED_AW { + #[doc = "1: Disable"] + CLEAR = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: KEYSLOT_PUSHED_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `KEYSLOT_PUSHED` writer - Write '1' to disable interrupt for event KEYSLOT_PUSHED"] +pub type KEYSLOT_PUSHED_W<'a, const O: u8> = + crate::BitWriter<'a, u32, INTENCLR_SPEC, KEYSLOT_PUSHED_AW, O>; +impl<'a, const O: u8> KEYSLOT_PUSHED_W<'a, O> { + #[doc = "Disable"] + #[inline(always)] + pub fn clear(self) -> &'a mut W { + self.variant(KEYSLOT_PUSHED_AW::CLEAR) + } +} +#[doc = "Field `KEYSLOT_REVOKED` reader - Write '1' to disable interrupt for event KEYSLOT_REVOKED"] +pub type KEYSLOT_REVOKED_R = crate::BitReader; +#[doc = "Write '1' to disable interrupt for event KEYSLOT_REVOKED\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum KEYSLOT_REVOKED_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: KEYSLOT_REVOKED_A) -> Self { + variant as u8 != 0 + } +} +impl KEYSLOT_REVOKED_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> KEYSLOT_REVOKED_A { + match self.bits { + false => KEYSLOT_REVOKED_A::DISABLED, + true => KEYSLOT_REVOKED_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == KEYSLOT_REVOKED_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == KEYSLOT_REVOKED_A::ENABLED + } +} +#[doc = "Write '1' to disable interrupt for event KEYSLOT_REVOKED\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum KEYSLOT_REVOKED_AW { + #[doc = "1: Disable"] + CLEAR = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: KEYSLOT_REVOKED_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `KEYSLOT_REVOKED` writer - Write '1' to disable interrupt for event KEYSLOT_REVOKED"] +pub type KEYSLOT_REVOKED_W<'a, const O: u8> = + crate::BitWriter<'a, u32, INTENCLR_SPEC, KEYSLOT_REVOKED_AW, O>; +impl<'a, const O: u8> KEYSLOT_REVOKED_W<'a, O> { + #[doc = "Disable"] + #[inline(always)] + pub fn clear(self) -> &'a mut W { + self.variant(KEYSLOT_REVOKED_AW::CLEAR) + } +} +#[doc = "Field `KEYSLOT_ERROR` reader - Write '1' to disable interrupt for event KEYSLOT_ERROR"] +pub type KEYSLOT_ERROR_R = crate::BitReader; +#[doc = "Write '1' to disable interrupt for event KEYSLOT_ERROR\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum KEYSLOT_ERROR_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: KEYSLOT_ERROR_A) -> Self { + variant as u8 != 0 + } +} +impl KEYSLOT_ERROR_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> KEYSLOT_ERROR_A { + match self.bits { + false => KEYSLOT_ERROR_A::DISABLED, + true => KEYSLOT_ERROR_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == KEYSLOT_ERROR_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == KEYSLOT_ERROR_A::ENABLED + } +} +#[doc = "Write '1' to disable interrupt for event KEYSLOT_ERROR\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum KEYSLOT_ERROR_AW { + #[doc = "1: Disable"] + CLEAR = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: KEYSLOT_ERROR_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `KEYSLOT_ERROR` writer - Write '1' to disable interrupt for event KEYSLOT_ERROR"] +pub type KEYSLOT_ERROR_W<'a, const O: u8> = + crate::BitWriter<'a, u32, INTENCLR_SPEC, KEYSLOT_ERROR_AW, O>; +impl<'a, const O: u8> KEYSLOT_ERROR_W<'a, O> { + #[doc = "Disable"] + #[inline(always)] + pub fn clear(self) -> &'a mut W { + self.variant(KEYSLOT_ERROR_AW::CLEAR) + } +} +impl R { + #[doc = "Bit 0 - Write '1' to disable interrupt for event KEYSLOT_PUSHED"] + #[inline(always)] + pub fn keyslot_pushed(&self) -> KEYSLOT_PUSHED_R { + KEYSLOT_PUSHED_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Write '1' to disable interrupt for event KEYSLOT_REVOKED"] + #[inline(always)] + pub fn keyslot_revoked(&self) -> KEYSLOT_REVOKED_R { + KEYSLOT_REVOKED_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Write '1' to disable interrupt for event KEYSLOT_ERROR"] + #[inline(always)] + pub fn keyslot_error(&self) -> KEYSLOT_ERROR_R { + KEYSLOT_ERROR_R::new(((self.bits >> 2) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Write '1' to disable interrupt for event KEYSLOT_PUSHED"] + #[inline(always)] + pub fn keyslot_pushed(&mut self) -> KEYSLOT_PUSHED_W<0> { + KEYSLOT_PUSHED_W::new(self) + } + #[doc = "Bit 1 - Write '1' to disable interrupt for event KEYSLOT_REVOKED"] + #[inline(always)] + pub fn keyslot_revoked(&mut self) -> KEYSLOT_REVOKED_W<1> { + KEYSLOT_REVOKED_W::new(self) + } + #[doc = "Bit 2 - Write '1' to disable interrupt for event KEYSLOT_ERROR"] + #[inline(always)] + pub fn keyslot_error(&mut self) -> KEYSLOT_ERROR_W<2> { + KEYSLOT_ERROR_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Disable interrupt\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/kmu_ns/intenset.rs b/pacs/nrf9120-pac/src/kmu_ns/intenset.rs new file mode 100644 index 00000000..aa0ff911 --- /dev/null +++ b/pacs/nrf9120-pac/src/kmu_ns/intenset.rs @@ -0,0 +1,270 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `KEYSLOT_PUSHED` reader - Write '1' to enable interrupt for event KEYSLOT_PUSHED"] +pub type KEYSLOT_PUSHED_R = crate::BitReader; +#[doc = "Write '1' to enable interrupt for event KEYSLOT_PUSHED\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum KEYSLOT_PUSHED_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: KEYSLOT_PUSHED_A) -> Self { + variant as u8 != 0 + } +} +impl KEYSLOT_PUSHED_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> KEYSLOT_PUSHED_A { + match self.bits { + false => KEYSLOT_PUSHED_A::DISABLED, + true => KEYSLOT_PUSHED_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == KEYSLOT_PUSHED_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == KEYSLOT_PUSHED_A::ENABLED + } +} +#[doc = "Write '1' to enable interrupt for event KEYSLOT_PUSHED\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum KEYSLOT_PUSHED_AW { + #[doc = "1: Enable"] + SET = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: KEYSLOT_PUSHED_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `KEYSLOT_PUSHED` writer - Write '1' to enable interrupt for event KEYSLOT_PUSHED"] +pub type KEYSLOT_PUSHED_W<'a, const O: u8> = + crate::BitWriter<'a, u32, INTENSET_SPEC, KEYSLOT_PUSHED_AW, O>; +impl<'a, const O: u8> KEYSLOT_PUSHED_W<'a, O> { + #[doc = "Enable"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(KEYSLOT_PUSHED_AW::SET) + } +} +#[doc = "Field `KEYSLOT_REVOKED` reader - Write '1' to enable interrupt for event KEYSLOT_REVOKED"] +pub type KEYSLOT_REVOKED_R = crate::BitReader; +#[doc = "Write '1' to enable interrupt for event KEYSLOT_REVOKED\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum KEYSLOT_REVOKED_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: KEYSLOT_REVOKED_A) -> Self { + variant as u8 != 0 + } +} +impl KEYSLOT_REVOKED_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> KEYSLOT_REVOKED_A { + match self.bits { + false => KEYSLOT_REVOKED_A::DISABLED, + true => KEYSLOT_REVOKED_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == KEYSLOT_REVOKED_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == KEYSLOT_REVOKED_A::ENABLED + } +} +#[doc = "Write '1' to enable interrupt for event KEYSLOT_REVOKED\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum KEYSLOT_REVOKED_AW { + #[doc = "1: Enable"] + SET = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: KEYSLOT_REVOKED_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `KEYSLOT_REVOKED` writer - Write '1' to enable interrupt for event KEYSLOT_REVOKED"] +pub type KEYSLOT_REVOKED_W<'a, const O: u8> = + crate::BitWriter<'a, u32, INTENSET_SPEC, KEYSLOT_REVOKED_AW, O>; +impl<'a, const O: u8> KEYSLOT_REVOKED_W<'a, O> { + #[doc = "Enable"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(KEYSLOT_REVOKED_AW::SET) + } +} +#[doc = "Field `KEYSLOT_ERROR` reader - Write '1' to enable interrupt for event KEYSLOT_ERROR"] +pub type KEYSLOT_ERROR_R = crate::BitReader; +#[doc = "Write '1' to enable interrupt for event KEYSLOT_ERROR\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum KEYSLOT_ERROR_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: KEYSLOT_ERROR_A) -> Self { + variant as u8 != 0 + } +} +impl KEYSLOT_ERROR_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> KEYSLOT_ERROR_A { + match self.bits { + false => KEYSLOT_ERROR_A::DISABLED, + true => KEYSLOT_ERROR_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == KEYSLOT_ERROR_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == KEYSLOT_ERROR_A::ENABLED + } +} +#[doc = "Write '1' to enable interrupt for event KEYSLOT_ERROR\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum KEYSLOT_ERROR_AW { + #[doc = "1: Enable"] + SET = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: KEYSLOT_ERROR_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `KEYSLOT_ERROR` writer - Write '1' to enable interrupt for event KEYSLOT_ERROR"] +pub type KEYSLOT_ERROR_W<'a, const O: u8> = + crate::BitWriter<'a, u32, INTENSET_SPEC, KEYSLOT_ERROR_AW, O>; +impl<'a, const O: u8> KEYSLOT_ERROR_W<'a, O> { + #[doc = "Enable"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(KEYSLOT_ERROR_AW::SET) + } +} +impl R { + #[doc = "Bit 0 - Write '1' to enable interrupt for event KEYSLOT_PUSHED"] + #[inline(always)] + pub fn keyslot_pushed(&self) -> KEYSLOT_PUSHED_R { + KEYSLOT_PUSHED_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Write '1' to enable interrupt for event KEYSLOT_REVOKED"] + #[inline(always)] + pub fn keyslot_revoked(&self) -> KEYSLOT_REVOKED_R { + KEYSLOT_REVOKED_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Write '1' to enable interrupt for event KEYSLOT_ERROR"] + #[inline(always)] + pub fn keyslot_error(&self) -> KEYSLOT_ERROR_R { + KEYSLOT_ERROR_R::new(((self.bits >> 2) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Write '1' to enable interrupt for event KEYSLOT_PUSHED"] + #[inline(always)] + pub fn keyslot_pushed(&mut self) -> KEYSLOT_PUSHED_W<0> { + KEYSLOT_PUSHED_W::new(self) + } + #[doc = "Bit 1 - Write '1' to enable interrupt for event KEYSLOT_REVOKED"] + #[inline(always)] + pub fn keyslot_revoked(&mut self) -> KEYSLOT_REVOKED_W<1> { + KEYSLOT_REVOKED_W::new(self) + } + #[doc = "Bit 2 - Write '1' to enable interrupt for event KEYSLOT_ERROR"] + #[inline(always)] + pub fn keyslot_error(&mut self) -> KEYSLOT_ERROR_W<2> { + KEYSLOT_ERROR_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Enable interrupt\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/kmu_ns/intpend.rs b/pacs/nrf9120-pac/src/kmu_ns/intpend.rs new file mode 100644 index 00000000..2aa8aa0a --- /dev/null +++ b/pacs/nrf9120-pac/src/kmu_ns/intpend.rs @@ -0,0 +1,156 @@ +#[doc = "Register `INTPEND` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `KEYSLOT_PUSHED` reader - Read pending status of interrupt for event KEYSLOT_PUSHED"] +pub type KEYSLOT_PUSHED_R = crate::BitReader; +#[doc = "Read pending status of interrupt for event KEYSLOT_PUSHED\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum KEYSLOT_PUSHED_A { + #[doc = "0: Read: Not pending"] + NOT_PENDING = 0, + #[doc = "1: Read: Pending"] + PENDING = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: KEYSLOT_PUSHED_A) -> Self { + variant as u8 != 0 + } +} +impl KEYSLOT_PUSHED_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> KEYSLOT_PUSHED_A { + match self.bits { + false => KEYSLOT_PUSHED_A::NOT_PENDING, + true => KEYSLOT_PUSHED_A::PENDING, + } + } + #[doc = "Checks if the value of the field is `NOT_PENDING`"] + #[inline(always)] + pub fn is_not_pending(&self) -> bool { + *self == KEYSLOT_PUSHED_A::NOT_PENDING + } + #[doc = "Checks if the value of the field is `PENDING`"] + #[inline(always)] + pub fn is_pending(&self) -> bool { + *self == KEYSLOT_PUSHED_A::PENDING + } +} +#[doc = "Field `KEYSLOT_REVOKED` reader - Read pending status of interrupt for event KEYSLOT_REVOKED"] +pub type KEYSLOT_REVOKED_R = crate::BitReader; +#[doc = "Read pending status of interrupt for event KEYSLOT_REVOKED\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum KEYSLOT_REVOKED_A { + #[doc = "0: Read: Not pending"] + NOT_PENDING = 0, + #[doc = "1: Read: Pending"] + PENDING = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: KEYSLOT_REVOKED_A) -> Self { + variant as u8 != 0 + } +} +impl KEYSLOT_REVOKED_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> KEYSLOT_REVOKED_A { + match self.bits { + false => KEYSLOT_REVOKED_A::NOT_PENDING, + true => KEYSLOT_REVOKED_A::PENDING, + } + } + #[doc = "Checks if the value of the field is `NOT_PENDING`"] + #[inline(always)] + pub fn is_not_pending(&self) -> bool { + *self == KEYSLOT_REVOKED_A::NOT_PENDING + } + #[doc = "Checks if the value of the field is `PENDING`"] + #[inline(always)] + pub fn is_pending(&self) -> bool { + *self == KEYSLOT_REVOKED_A::PENDING + } +} +#[doc = "Field `KEYSLOT_ERROR` reader - Read pending status of interrupt for event KEYSLOT_ERROR"] +pub type KEYSLOT_ERROR_R = crate::BitReader; +#[doc = "Read pending status of interrupt for event KEYSLOT_ERROR\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum KEYSLOT_ERROR_A { + #[doc = "0: Read: Not pending"] + NOT_PENDING = 0, + #[doc = "1: Read: Pending"] + PENDING = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: KEYSLOT_ERROR_A) -> Self { + variant as u8 != 0 + } +} +impl KEYSLOT_ERROR_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> KEYSLOT_ERROR_A { + match self.bits { + false => KEYSLOT_ERROR_A::NOT_PENDING, + true => KEYSLOT_ERROR_A::PENDING, + } + } + #[doc = "Checks if the value of the field is `NOT_PENDING`"] + #[inline(always)] + pub fn is_not_pending(&self) -> bool { + *self == KEYSLOT_ERROR_A::NOT_PENDING + } + #[doc = "Checks if the value of the field is `PENDING`"] + #[inline(always)] + pub fn is_pending(&self) -> bool { + *self == KEYSLOT_ERROR_A::PENDING + } +} +impl R { + #[doc = "Bit 0 - Read pending status of interrupt for event KEYSLOT_PUSHED"] + #[inline(always)] + pub fn keyslot_pushed(&self) -> KEYSLOT_PUSHED_R { + KEYSLOT_PUSHED_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Read pending status of interrupt for event KEYSLOT_REVOKED"] + #[inline(always)] + pub fn keyslot_revoked(&self) -> KEYSLOT_REVOKED_R { + KEYSLOT_REVOKED_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Read pending status of interrupt for event KEYSLOT_ERROR"] + #[inline(always)] + pub fn keyslot_error(&self) -> KEYSLOT_ERROR_R { + KEYSLOT_ERROR_R::new(((self.bits >> 2) & 1) != 0) + } +} +#[doc = "Pending interrupts\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intpend](index.html) module"] +pub struct INTPEND_SPEC; +impl crate::RegisterSpec for INTPEND_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intpend::R](R) reader structure"] +impl crate::Readable for INTPEND_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets INTPEND to value 0"] +impl crate::Resettable for INTPEND_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/kmu_ns/selectkeyslot.rs b/pacs/nrf9120-pac/src/kmu_ns/selectkeyslot.rs new file mode 100644 index 00000000..413f8506 --- /dev/null +++ b/pacs/nrf9120-pac/src/kmu_ns/selectkeyslot.rs @@ -0,0 +1,88 @@ +#[doc = "Register `SELECTKEYSLOT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SELECTKEYSLOT` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ID` reader - Select key slot ID to be read over AHB, or pushed over secure APB, when TASKS_PUSH_KEYSLOT is started. NOTE: ID=0 is not a valid key slot ID. The 0 ID should be used when the KMU is idle or not in use. NOTE: Index N in UICR->KEYSLOT.KEY\\[N\\] +and UICR->KEYSLOT.CONFIG\\[N\\] +corresponds to KMU key slot ID=N+1."] +pub type ID_R = crate::FieldReader; +#[doc = "Field `ID` writer - Select key slot ID to be read over AHB, or pushed over secure APB, when TASKS_PUSH_KEYSLOT is started. NOTE: ID=0 is not a valid key slot ID. The 0 ID should be used when the KMU is idle or not in use. NOTE: Index N in UICR->KEYSLOT.KEY\\[N\\] +and UICR->KEYSLOT.CONFIG\\[N\\] +corresponds to KMU key slot ID=N+1."] +pub type ID_W<'a, const O: u8> = crate::FieldWriter<'a, u32, SELECTKEYSLOT_SPEC, u8, u8, 8, O>; +impl R { + #[doc = "Bits 0:7 - Select key slot ID to be read over AHB, or pushed over secure APB, when TASKS_PUSH_KEYSLOT is started. NOTE: ID=0 is not a valid key slot ID. The 0 ID should be used when the KMU is idle or not in use. NOTE: Index N in UICR->KEYSLOT.KEY\\[N\\] +and UICR->KEYSLOT.CONFIG\\[N\\] +corresponds to KMU key slot ID=N+1."] + #[inline(always)] + pub fn id(&self) -> ID_R { + ID_R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Select key slot ID to be read over AHB, or pushed over secure APB, when TASKS_PUSH_KEYSLOT is started. NOTE: ID=0 is not a valid key slot ID. The 0 ID should be used when the KMU is idle or not in use. NOTE: Index N in UICR->KEYSLOT.KEY\\[N\\] +and UICR->KEYSLOT.CONFIG\\[N\\] +corresponds to KMU key slot ID=N+1."] + #[inline(always)] + pub fn id(&mut self) -> ID_W<0> { + ID_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Select key slot to be read over AHB or pushed over secure APB when TASKS_PUSH_KEYSLOT is started\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [selectkeyslot](index.html) module"] +pub struct SELECTKEYSLOT_SPEC; +impl crate::RegisterSpec for SELECTKEYSLOT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [selectkeyslot::R](R) reader structure"] +impl crate::Readable for SELECTKEYSLOT_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [selectkeyslot::W](W) writer structure"] +impl crate::Writable for SELECTKEYSLOT_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SELECTKEYSLOT to value 0"] +impl crate::Resettable for SELECTKEYSLOT_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/kmu_ns/status.rs b/pacs/nrf9120-pac/src/kmu_ns/status.rs new file mode 100644 index 00000000..f049efea --- /dev/null +++ b/pacs/nrf9120-pac/src/kmu_ns/status.rs @@ -0,0 +1,115 @@ +#[doc = "Register `STATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SELECTED` reader - Key slot ID successfully selected by the KMU"] +pub type SELECTED_R = crate::BitReader; +#[doc = "Key slot ID successfully selected by the KMU\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum SELECTED_A { + #[doc = "0: No key slot ID selected by KMU"] + DISABLED = 0, + #[doc = "1: Key slot ID successfully selected by KMU"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: SELECTED_A) -> Self { + variant as u8 != 0 + } +} +impl SELECTED_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> SELECTED_A { + match self.bits { + false => SELECTED_A::DISABLED, + true => SELECTED_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == SELECTED_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == SELECTED_A::ENABLED + } +} +#[doc = "Field `BLOCKED` reader - Violation status"] +pub type BLOCKED_R = crate::BitReader; +#[doc = "Violation status\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum BLOCKED_A { + #[doc = "0: No access violation detected"] + DISABLED = 0, + #[doc = "1: Access violation detected and blocked"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: BLOCKED_A) -> Self { + variant as u8 != 0 + } +} +impl BLOCKED_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> BLOCKED_A { + match self.bits { + false => BLOCKED_A::DISABLED, + true => BLOCKED_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == BLOCKED_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == BLOCKED_A::ENABLED + } +} +impl R { + #[doc = "Bit 0 - Key slot ID successfully selected by the KMU"] + #[inline(always)] + pub fn selected(&self) -> SELECTED_R { + SELECTED_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Violation status"] + #[inline(always)] + pub fn blocked(&self) -> BLOCKED_R { + BLOCKED_R::new(((self.bits >> 1) & 1) != 0) + } +} +#[doc = "Status bits for KMU operation\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [status::R](R) reader structure"] +impl crate::Readable for STATUS_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets STATUS to value 0"] +impl crate::Resettable for STATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/kmu_ns/tasks_push_keyslot.rs b/pacs/nrf9120-pac/src/kmu_ns/tasks_push_keyslot.rs new file mode 100644 index 00000000..3df6e1a2 --- /dev/null +++ b/pacs/nrf9120-pac/src/kmu_ns/tasks_push_keyslot.rs @@ -0,0 +1,72 @@ +#[doc = "Register `TASKS_PUSH_KEYSLOT` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Push a key slot over secure APB\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum TASKS_PUSH_KEYSLOT_AW { + #[doc = "1: Trigger task"] + TRIGGER = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TASKS_PUSH_KEYSLOT_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TASKS_PUSH_KEYSLOT` writer - Push a key slot over secure APB"] +pub type TASKS_PUSH_KEYSLOT_W<'a, const O: u8> = + crate::BitWriter<'a, u32, TASKS_PUSH_KEYSLOT_SPEC, TASKS_PUSH_KEYSLOT_AW, O>; +impl<'a, const O: u8> TASKS_PUSH_KEYSLOT_W<'a, O> { + #[doc = "Trigger task"] + #[inline(always)] + pub fn trigger(self) -> &'a mut W { + self.variant(TASKS_PUSH_KEYSLOT_AW::TRIGGER) + } +} +impl W { + #[doc = "Bit 0 - Push a key slot over secure APB"] + #[inline(always)] + pub fn tasks_push_keyslot(&mut self) -> TASKS_PUSH_KEYSLOT_W<0> { + TASKS_PUSH_KEYSLOT_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Push a key slot over secure APB\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tasks_push_keyslot](index.html) module"] +pub struct TASKS_PUSH_KEYSLOT_SPEC; +impl crate::RegisterSpec for TASKS_PUSH_KEYSLOT_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [tasks_push_keyslot::W](W) writer structure"] +impl crate::Writable for TASKS_PUSH_KEYSLOT_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets TASKS_PUSH_KEYSLOT to value 0"] +impl crate::Resettable for TASKS_PUSH_KEYSLOT_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/lib.rs b/pacs/nrf9120-pac/src/lib.rs new file mode 100644 index 00000000..13952fda --- /dev/null +++ b/pacs/nrf9120-pac/src/lib.rs @@ -0,0 +1,3817 @@ +#![doc = "Peripheral access API for NRF9120 microcontrollers (generated using svd2rust v0.25.1 ( ))\n\nYou can find an overview of the generated API [here].\n\nAPI features to be included in the [next] +svd2rust release can be generated by cloning the svd2rust [repository], checking out the above commit, and running `cargo doc --open`.\n\n[here]: https://docs.rs/svd2rust/0.25.1/svd2rust/#peripheral-api\n[next]: https://github.com/rust-embedded/svd2rust/blob/master/CHANGELOG.md#unreleased\n[repository]: https://github.com/rust-embedded/svd2rust"] +#![deny(dead_code)] +#![deny(improper_ctypes)] +#![deny(missing_docs)] +#![deny(no_mangle_generic_items)] +#![deny(non_shorthand_field_patterns)] +#![deny(overflowing_literals)] +#![deny(path_statements)] +#![deny(patterns_in_fns_without_body)] +#![deny(unconditional_recursion)] +#![deny(unused_allocation)] +#![deny(unused_comparisons)] +#![deny(unused_parens)] +#![deny(while_true)] +#![allow(non_camel_case_types)] +#![allow(non_snake_case)] +#![no_std] +use core::marker::PhantomData; +use core::ops::Deref; +#[doc = r"Number available in the NVIC for configuring priority"] +pub const NVIC_PRIO_BITS: u8 = 3; +#[cfg(feature = "rt")] +pub use self::Interrupt as interrupt; +pub use cortex_m::peripheral::Peripherals as CorePeripherals; +pub use cortex_m::peripheral::{CBP, CPUID, DCB, DWT, FPB, FPU, ITM, MPU, NVIC, SCB, SYST, TPIU}; +#[cfg(feature = "rt")] +pub use cortex_m_rt::interrupt; +#[allow(unused_imports)] +use generic::*; +#[doc = r"Common register and bit access and modify traits"] +pub mod generic; +#[cfg(feature = "rt")] +extern "C" { + fn SPU(); + fn CLOCK_POWER(); + fn SPIM0_SPIS0_TWIM0_TWIS0_UARTE0(); + fn SPIM1_SPIS1_TWIM1_TWIS1_UARTE1(); + fn SPIM2_SPIS2_TWIM2_TWIS2_UARTE2(); + fn SPIM3_SPIS3_TWIM3_TWIS3_UARTE3(); + fn GPIOTE0(); + fn SAADC(); + fn TIMER0(); + fn TIMER1(); + fn TIMER2(); + fn RTC0(); + fn RTC1(); + fn WDT(); + fn EGU0(); + fn EGU1(); + fn EGU2(); + fn EGU3(); + fn EGU4(); + fn EGU5(); + fn PWM0(); + fn PWM1(); + fn PWM2(); + fn PWM3(); + fn PDM(); + fn I2S(); + fn IPC(); + fn FPU(); + fn GPIOTE1(); + fn KMU(); + fn CRYPTOCELL(); +} +#[doc(hidden)] +pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, +} +#[cfg(feature = "rt")] +#[doc(hidden)] +#[link_section = ".vector_table.interrupts"] +#[no_mangle] +pub static __INTERRUPTS: [Vector; 65] = [ + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SPU }, + Vector { _reserved: 0 }, + Vector { + _handler: CLOCK_POWER, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: SPIM0_SPIS0_TWIM0_TWIS0_UARTE0, + }, + Vector { + _handler: SPIM1_SPIS1_TWIM1_TWIS1_UARTE1, + }, + Vector { + _handler: SPIM2_SPIS2_TWIM2_TWIS2_UARTE2, + }, + Vector { + _handler: SPIM3_SPIS3_TWIM3_TWIS3_UARTE3, + }, + Vector { _reserved: 0 }, + Vector { _handler: GPIOTE0 }, + Vector { _handler: SAADC }, + Vector { _handler: TIMER0 }, + Vector { _handler: TIMER1 }, + Vector { _handler: TIMER2 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RTC0 }, + Vector { _handler: RTC1 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: WDT }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: EGU0 }, + Vector { _handler: EGU1 }, + Vector { _handler: EGU2 }, + Vector { _handler: EGU3 }, + Vector { _handler: EGU4 }, + Vector { _handler: EGU5 }, + Vector { _handler: PWM0 }, + Vector { _handler: PWM1 }, + Vector { _handler: PWM2 }, + Vector { _handler: PWM3 }, + Vector { _reserved: 0 }, + Vector { _handler: PDM }, + Vector { _reserved: 0 }, + Vector { _handler: I2S }, + Vector { _reserved: 0 }, + Vector { _handler: IPC }, + Vector { _reserved: 0 }, + Vector { _handler: FPU }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: GPIOTE1 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: KMU }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: CRYPTOCELL, + }, +]; +#[doc = r"Enumeration of all the interrupts."] +#[derive(Copy, Clone, Debug, PartialEq, Eq)] +#[repr(u16)] +pub enum Interrupt { + #[doc = "3 - SPU"] + SPU = 3, + #[doc = "5 - CLOCK_POWER"] + CLOCK_POWER = 5, + #[doc = "8 - SPIM0_SPIS0_TWIM0_TWIS0_UARTE0"] + SPIM0_SPIS0_TWIM0_TWIS0_UARTE0 = 8, + #[doc = "9 - SPIM1_SPIS1_TWIM1_TWIS1_UARTE1"] + SPIM1_SPIS1_TWIM1_TWIS1_UARTE1 = 9, + #[doc = "10 - SPIM2_SPIS2_TWIM2_TWIS2_UARTE2"] + SPIM2_SPIS2_TWIM2_TWIS2_UARTE2 = 10, + #[doc = "11 - SPIM3_SPIS3_TWIM3_TWIS3_UARTE3"] + SPIM3_SPIS3_TWIM3_TWIS3_UARTE3 = 11, + #[doc = "13 - GPIOTE0"] + GPIOTE0 = 13, + #[doc = "14 - SAADC"] + SAADC = 14, + #[doc = "15 - TIMER0"] + TIMER0 = 15, + #[doc = "16 - TIMER1"] + TIMER1 = 16, + #[doc = "17 - TIMER2"] + TIMER2 = 17, + #[doc = "20 - RTC0"] + RTC0 = 20, + #[doc = "21 - RTC1"] + RTC1 = 21, + #[doc = "24 - WDT"] + WDT = 24, + #[doc = "27 - EGU0"] + EGU0 = 27, + #[doc = "28 - EGU1"] + EGU1 = 28, + #[doc = "29 - EGU2"] + EGU2 = 29, + #[doc = "30 - EGU3"] + EGU3 = 30, + #[doc = "31 - EGU4"] + EGU4 = 31, + #[doc = "32 - EGU5"] + EGU5 = 32, + #[doc = "33 - PWM0"] + PWM0 = 33, + #[doc = "34 - PWM1"] + PWM1 = 34, + #[doc = "35 - PWM2"] + PWM2 = 35, + #[doc = "36 - PWM3"] + PWM3 = 36, + #[doc = "38 - PDM"] + PDM = 38, + #[doc = "40 - I2S"] + I2S = 40, + #[doc = "42 - IPC"] + IPC = 42, + #[doc = "44 - FPU"] + FPU = 44, + #[doc = "49 - GPIOTE1"] + GPIOTE1 = 49, + #[doc = "57 - KMU"] + KMU = 57, + #[doc = "64 - CRYPTOCELL"] + CRYPTOCELL = 64, +} +unsafe impl cortex_m::interrupt::InterruptNumber for Interrupt { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } +} +#[doc = "Factory Information Configuration Registers"] +pub struct FICR_S { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for FICR_S {} +impl FICR_S { + #[doc = r"Pointer to the register block"] + pub const PTR: *const ficr_s::RegisterBlock = 0x00ff_0000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const ficr_s::RegisterBlock { + Self::PTR + } +} +impl Deref for FICR_S { + type Target = ficr_s::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for FICR_S { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FICR_S").finish() + } +} +#[doc = "Factory Information Configuration Registers"] +pub mod ficr_s; +#[doc = "User information configuration registers User information configuration registers"] +pub struct UICR_S { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for UICR_S {} +impl UICR_S { + #[doc = r"Pointer to the register block"] + pub const PTR: *const uicr_s::RegisterBlock = 0x00ff_8000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const uicr_s::RegisterBlock { + Self::PTR + } +} +impl Deref for UICR_S { + type Target = uicr_s::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for UICR_S { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("UICR_S").finish() + } +} +#[doc = "User information configuration registers User information configuration registers"] +pub mod uicr_s; +#[doc = "Trace and debug control"] +pub struct TAD_S { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for TAD_S {} +impl TAD_S { + #[doc = r"Pointer to the register block"] + pub const PTR: *const tad_s::RegisterBlock = 0xe008_0000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const tad_s::RegisterBlock { + Self::PTR + } +} +impl Deref for TAD_S { + type Target = tad_s::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for TAD_S { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TAD_S").finish() + } +} +#[doc = "Trace and debug control"] +pub mod tad_s; +#[doc = "System protection unit"] +pub struct SPU_S { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for SPU_S {} +impl SPU_S { + #[doc = r"Pointer to the register block"] + pub const PTR: *const spu_s::RegisterBlock = 0x5000_3000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const spu_s::RegisterBlock { + Self::PTR + } +} +impl Deref for SPU_S { + type Target = spu_s::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for SPU_S { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SPU_S").finish() + } +} +#[doc = "System protection unit"] +pub mod spu_s; +#[doc = "Voltage regulators control 0"] +pub struct REGULATORS_NS { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for REGULATORS_NS {} +impl REGULATORS_NS { + #[doc = r"Pointer to the register block"] + pub const PTR: *const regulators_ns::RegisterBlock = 0x4000_4000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const regulators_ns::RegisterBlock { + Self::PTR + } +} +impl Deref for REGULATORS_NS { + type Target = regulators_ns::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for REGULATORS_NS { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("REGULATORS_NS").finish() + } +} +#[doc = "Voltage regulators control 0"] +pub mod regulators_ns; +#[doc = "Voltage regulators control 1"] +pub struct REGULATORS_S { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for REGULATORS_S {} +impl REGULATORS_S { + #[doc = r"Pointer to the register block"] + pub const PTR: *const regulators_ns::RegisterBlock = 0x5000_4000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const regulators_ns::RegisterBlock { + Self::PTR + } +} +impl Deref for REGULATORS_S { + type Target = regulators_ns::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for REGULATORS_S { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("REGULATORS_S").finish() + } +} +#[doc = "Voltage regulators control 1"] +pub use regulators_ns as regulators_s; +#[doc = "Clock management 0"] +pub struct CLOCK_NS { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for CLOCK_NS {} +impl CLOCK_NS { + #[doc = r"Pointer to the register block"] + pub const PTR: *const clock_ns::RegisterBlock = 0x4000_5000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const clock_ns::RegisterBlock { + Self::PTR + } +} +impl Deref for CLOCK_NS { + type Target = clock_ns::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for CLOCK_NS { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CLOCK_NS").finish() + } +} +#[doc = "Clock management 0"] +pub mod clock_ns; +#[doc = "Power control 0"] +pub struct POWER_NS { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for POWER_NS {} +impl POWER_NS { + #[doc = r"Pointer to the register block"] + pub const PTR: *const power_ns::RegisterBlock = 0x4000_5000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const power_ns::RegisterBlock { + Self::PTR + } +} +impl Deref for POWER_NS { + type Target = power_ns::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for POWER_NS { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("POWER_NS").finish() + } +} +#[doc = "Power control 0"] +pub mod power_ns; +#[doc = "Clock management 1"] +pub struct CLOCK_S { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for CLOCK_S {} +impl CLOCK_S { + #[doc = r"Pointer to the register block"] + pub const PTR: *const clock_ns::RegisterBlock = 0x5000_5000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const clock_ns::RegisterBlock { + Self::PTR + } +} +impl Deref for CLOCK_S { + type Target = clock_ns::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for CLOCK_S { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CLOCK_S").finish() + } +} +#[doc = "Clock management 1"] +pub use clock_ns as clock_s; +#[doc = "Power control 1"] +pub struct POWER_S { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for POWER_S {} +impl POWER_S { + #[doc = r"Pointer to the register block"] + pub const PTR: *const power_ns::RegisterBlock = 0x5000_5000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const power_ns::RegisterBlock { + Self::PTR + } +} +impl Deref for POWER_S { + type Target = power_ns::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for POWER_S { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("POWER_S").finish() + } +} +#[doc = "Power control 1"] +pub use power_ns as power_s; +#[doc = "Control access port"] +pub struct CTRL_AP_PERI_S { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for CTRL_AP_PERI_S {} +impl CTRL_AP_PERI_S { + #[doc = r"Pointer to the register block"] + pub const PTR: *const ctrl_ap_peri_s::RegisterBlock = 0x5000_6000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const ctrl_ap_peri_s::RegisterBlock { + Self::PTR + } +} +impl Deref for CTRL_AP_PERI_S { + type Target = ctrl_ap_peri_s::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for CTRL_AP_PERI_S { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CTRL_AP_PERI_S").finish() + } +} +#[doc = "Control access port"] +pub mod ctrl_ap_peri_s; +#[doc = "Serial Peripheral Interface Master with EasyDMA 0"] +pub struct SPIM0_NS { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for SPIM0_NS {} +impl SPIM0_NS { + #[doc = r"Pointer to the register block"] + pub const PTR: *const spim0_ns::RegisterBlock = 0x4000_8000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const spim0_ns::RegisterBlock { + Self::PTR + } +} +impl Deref for SPIM0_NS { + type Target = spim0_ns::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for SPIM0_NS { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SPIM0_NS").finish() + } +} +#[doc = "Serial Peripheral Interface Master with EasyDMA 0"] +pub mod spim0_ns; +#[doc = "SPI Slave 0"] +pub struct SPIS0_NS { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for SPIS0_NS {} +impl SPIS0_NS { + #[doc = r"Pointer to the register block"] + pub const PTR: *const spis0_ns::RegisterBlock = 0x4000_8000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const spis0_ns::RegisterBlock { + Self::PTR + } +} +impl Deref for SPIS0_NS { + type Target = spis0_ns::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for SPIS0_NS { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SPIS0_NS").finish() + } +} +#[doc = "SPI Slave 0"] +pub mod spis0_ns; +#[doc = "I2C compatible Two-Wire Master Interface with EasyDMA 0"] +pub struct TWIM0_NS { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for TWIM0_NS {} +impl TWIM0_NS { + #[doc = r"Pointer to the register block"] + pub const PTR: *const twim0_ns::RegisterBlock = 0x4000_8000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const twim0_ns::RegisterBlock { + Self::PTR + } +} +impl Deref for TWIM0_NS { + type Target = twim0_ns::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for TWIM0_NS { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TWIM0_NS").finish() + } +} +#[doc = "I2C compatible Two-Wire Master Interface with EasyDMA 0"] +pub mod twim0_ns; +#[doc = "I2C compatible Two-Wire Slave Interface with EasyDMA 0"] +pub struct TWIS0_NS { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for TWIS0_NS {} +impl TWIS0_NS { + #[doc = r"Pointer to the register block"] + pub const PTR: *const twis0_ns::RegisterBlock = 0x4000_8000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const twis0_ns::RegisterBlock { + Self::PTR + } +} +impl Deref for TWIS0_NS { + type Target = twis0_ns::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for TWIS0_NS { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TWIS0_NS").finish() + } +} +#[doc = "I2C compatible Two-Wire Slave Interface with EasyDMA 0"] +pub mod twis0_ns; +#[doc = "UART with EasyDMA 0"] +pub struct UARTE0_NS { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for UARTE0_NS {} +impl UARTE0_NS { + #[doc = r"Pointer to the register block"] + pub const PTR: *const uarte0_ns::RegisterBlock = 0x4000_8000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const uarte0_ns::RegisterBlock { + Self::PTR + } +} +impl Deref for UARTE0_NS { + type Target = uarte0_ns::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for UARTE0_NS { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("UARTE0_NS").finish() + } +} +#[doc = "UART with EasyDMA 0"] +pub mod uarte0_ns; +#[doc = "Serial Peripheral Interface Master with EasyDMA 1"] +pub struct SPIM0_S { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for SPIM0_S {} +impl SPIM0_S { + #[doc = r"Pointer to the register block"] + pub const PTR: *const spim0_ns::RegisterBlock = 0x5000_8000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const spim0_ns::RegisterBlock { + Self::PTR + } +} +impl Deref for SPIM0_S { + type Target = spim0_ns::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for SPIM0_S { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SPIM0_S").finish() + } +} +#[doc = "Serial Peripheral Interface Master with EasyDMA 1"] +pub use spim0_ns as spim0_s; +#[doc = "SPI Slave 1"] +pub struct SPIS0_S { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for SPIS0_S {} +impl SPIS0_S { + #[doc = r"Pointer to the register block"] + pub const PTR: *const spis0_ns::RegisterBlock = 0x5000_8000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const spis0_ns::RegisterBlock { + Self::PTR + } +} +impl Deref for SPIS0_S { + type Target = spis0_ns::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for SPIS0_S { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SPIS0_S").finish() + } +} +#[doc = "SPI Slave 1"] +pub use spis0_ns as spis0_s; +#[doc = "I2C compatible Two-Wire Master Interface with EasyDMA 1"] +pub struct TWIM0_S { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for TWIM0_S {} +impl TWIM0_S { + #[doc = r"Pointer to the register block"] + pub const PTR: *const twim0_ns::RegisterBlock = 0x5000_8000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const twim0_ns::RegisterBlock { + Self::PTR + } +} +impl Deref for TWIM0_S { + type Target = twim0_ns::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for TWIM0_S { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TWIM0_S").finish() + } +} +#[doc = "I2C compatible Two-Wire Master Interface with EasyDMA 1"] +pub use twim0_ns as twim0_s; +#[doc = "I2C compatible Two-Wire Slave Interface with EasyDMA 1"] +pub struct TWIS0_S { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for TWIS0_S {} +impl TWIS0_S { + #[doc = r"Pointer to the register block"] + pub const PTR: *const twis0_ns::RegisterBlock = 0x5000_8000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const twis0_ns::RegisterBlock { + Self::PTR + } +} +impl Deref for TWIS0_S { + type Target = twis0_ns::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for TWIS0_S { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TWIS0_S").finish() + } +} +#[doc = "I2C compatible Two-Wire Slave Interface with EasyDMA 1"] +pub use twis0_ns as twis0_s; +#[doc = "UART with EasyDMA 1"] +pub struct UARTE0_S { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for UARTE0_S {} +impl UARTE0_S { + #[doc = r"Pointer to the register block"] + pub const PTR: *const uarte0_ns::RegisterBlock = 0x5000_8000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const uarte0_ns::RegisterBlock { + Self::PTR + } +} +impl Deref for UARTE0_S { + type Target = uarte0_ns::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for UARTE0_S { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("UARTE0_S").finish() + } +} +#[doc = "UART with EasyDMA 1"] +pub use uarte0_ns as uarte0_s; +#[doc = "Serial Peripheral Interface Master with EasyDMA 2"] +pub struct SPIM1_NS { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for SPIM1_NS {} +impl SPIM1_NS { + #[doc = r"Pointer to the register block"] + pub const PTR: *const spim0_ns::RegisterBlock = 0x4000_9000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const spim0_ns::RegisterBlock { + Self::PTR + } +} +impl Deref for SPIM1_NS { + type Target = spim0_ns::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for SPIM1_NS { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SPIM1_NS").finish() + } +} +#[doc = "Serial Peripheral Interface Master with EasyDMA 2"] +pub use spim0_ns as spim1_ns; +#[doc = "SPI Slave 2"] +pub struct SPIS1_NS { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for SPIS1_NS {} +impl SPIS1_NS { + #[doc = r"Pointer to the register block"] + pub const PTR: *const spis0_ns::RegisterBlock = 0x4000_9000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const spis0_ns::RegisterBlock { + Self::PTR + } +} +impl Deref for SPIS1_NS { + type Target = spis0_ns::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for SPIS1_NS { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SPIS1_NS").finish() + } +} +#[doc = "SPI Slave 2"] +pub use spis0_ns as spis1_ns; +#[doc = "I2C compatible Two-Wire Master Interface with EasyDMA 2"] +pub struct TWIM1_NS { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for TWIM1_NS {} +impl TWIM1_NS { + #[doc = r"Pointer to the register block"] + pub const PTR: *const twim0_ns::RegisterBlock = 0x4000_9000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const twim0_ns::RegisterBlock { + Self::PTR + } +} +impl Deref for TWIM1_NS { + type Target = twim0_ns::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for TWIM1_NS { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TWIM1_NS").finish() + } +} +#[doc = "I2C compatible Two-Wire Master Interface with EasyDMA 2"] +pub use twim0_ns as twim1_ns; +#[doc = "I2C compatible Two-Wire Slave Interface with EasyDMA 2"] +pub struct TWIS1_NS { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for TWIS1_NS {} +impl TWIS1_NS { + #[doc = r"Pointer to the register block"] + pub const PTR: *const twis0_ns::RegisterBlock = 0x4000_9000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const twis0_ns::RegisterBlock { + Self::PTR + } +} +impl Deref for TWIS1_NS { + type Target = twis0_ns::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for TWIS1_NS { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TWIS1_NS").finish() + } +} +#[doc = "I2C compatible Two-Wire Slave Interface with EasyDMA 2"] +pub use twis0_ns as twis1_ns; +#[doc = "UART with EasyDMA 2"] +pub struct UARTE1_NS { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for UARTE1_NS {} +impl UARTE1_NS { + #[doc = r"Pointer to the register block"] + pub const PTR: *const uarte0_ns::RegisterBlock = 0x4000_9000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const uarte0_ns::RegisterBlock { + Self::PTR + } +} +impl Deref for UARTE1_NS { + type Target = uarte0_ns::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for UARTE1_NS { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("UARTE1_NS").finish() + } +} +#[doc = "UART with EasyDMA 2"] +pub use uarte0_ns as uarte1_ns; +#[doc = "Serial Peripheral Interface Master with EasyDMA 3"] +pub struct SPIM1_S { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for SPIM1_S {} +impl SPIM1_S { + #[doc = r"Pointer to the register block"] + pub const PTR: *const spim0_ns::RegisterBlock = 0x5000_9000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const spim0_ns::RegisterBlock { + Self::PTR + } +} +impl Deref for SPIM1_S { + type Target = spim0_ns::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for SPIM1_S { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SPIM1_S").finish() + } +} +#[doc = "Serial Peripheral Interface Master with EasyDMA 3"] +pub use spim0_ns as spim1_s; +#[doc = "SPI Slave 3"] +pub struct SPIS1_S { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for SPIS1_S {} +impl SPIS1_S { + #[doc = r"Pointer to the register block"] + pub const PTR: *const spis0_ns::RegisterBlock = 0x5000_9000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const spis0_ns::RegisterBlock { + Self::PTR + } +} +impl Deref for SPIS1_S { + type Target = spis0_ns::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for SPIS1_S { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SPIS1_S").finish() + } +} +#[doc = "SPI Slave 3"] +pub use spis0_ns as spis1_s; +#[doc = "I2C compatible Two-Wire Master Interface with EasyDMA 3"] +pub struct TWIM1_S { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for TWIM1_S {} +impl TWIM1_S { + #[doc = r"Pointer to the register block"] + pub const PTR: *const twim0_ns::RegisterBlock = 0x5000_9000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const twim0_ns::RegisterBlock { + Self::PTR + } +} +impl Deref for TWIM1_S { + type Target = twim0_ns::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for TWIM1_S { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TWIM1_S").finish() + } +} +#[doc = "I2C compatible Two-Wire Master Interface with EasyDMA 3"] +pub use twim0_ns as twim1_s; +#[doc = "I2C compatible Two-Wire Slave Interface with EasyDMA 3"] +pub struct TWIS1_S { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for TWIS1_S {} +impl TWIS1_S { + #[doc = r"Pointer to the register block"] + pub const PTR: *const twis0_ns::RegisterBlock = 0x5000_9000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const twis0_ns::RegisterBlock { + Self::PTR + } +} +impl Deref for TWIS1_S { + type Target = twis0_ns::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for TWIS1_S { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TWIS1_S").finish() + } +} +#[doc = "I2C compatible Two-Wire Slave Interface with EasyDMA 3"] +pub use twis0_ns as twis1_s; +#[doc = "UART with EasyDMA 3"] +pub struct UARTE1_S { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for UARTE1_S {} +impl UARTE1_S { + #[doc = r"Pointer to the register block"] + pub const PTR: *const uarte0_ns::RegisterBlock = 0x5000_9000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const uarte0_ns::RegisterBlock { + Self::PTR + } +} +impl Deref for UARTE1_S { + type Target = uarte0_ns::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for UARTE1_S { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("UARTE1_S").finish() + } +} +#[doc = "UART with EasyDMA 3"] +pub use uarte0_ns as uarte1_s; +#[doc = "Serial Peripheral Interface Master with EasyDMA 4"] +pub struct SPIM2_NS { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for SPIM2_NS {} +impl SPIM2_NS { + #[doc = r"Pointer to the register block"] + pub const PTR: *const spim0_ns::RegisterBlock = 0x4000_a000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const spim0_ns::RegisterBlock { + Self::PTR + } +} +impl Deref for SPIM2_NS { + type Target = spim0_ns::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for SPIM2_NS { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SPIM2_NS").finish() + } +} +#[doc = "Serial Peripheral Interface Master with EasyDMA 4"] +pub use spim0_ns as spim2_ns; +#[doc = "SPI Slave 4"] +pub struct SPIS2_NS { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for SPIS2_NS {} +impl SPIS2_NS { + #[doc = r"Pointer to the register block"] + pub const PTR: *const spis0_ns::RegisterBlock = 0x4000_a000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const spis0_ns::RegisterBlock { + Self::PTR + } +} +impl Deref for SPIS2_NS { + type Target = spis0_ns::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for SPIS2_NS { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SPIS2_NS").finish() + } +} +#[doc = "SPI Slave 4"] +pub use spis0_ns as spis2_ns; +#[doc = "I2C compatible Two-Wire Master Interface with EasyDMA 4"] +pub struct TWIM2_NS { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for TWIM2_NS {} +impl TWIM2_NS { + #[doc = r"Pointer to the register block"] + pub const PTR: *const twim0_ns::RegisterBlock = 0x4000_a000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const twim0_ns::RegisterBlock { + Self::PTR + } +} +impl Deref for TWIM2_NS { + type Target = twim0_ns::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for TWIM2_NS { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TWIM2_NS").finish() + } +} +#[doc = "I2C compatible Two-Wire Master Interface with EasyDMA 4"] +pub use twim0_ns as twim2_ns; +#[doc = "I2C compatible Two-Wire Slave Interface with EasyDMA 4"] +pub struct TWIS2_NS { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for TWIS2_NS {} +impl TWIS2_NS { + #[doc = r"Pointer to the register block"] + pub const PTR: *const twis0_ns::RegisterBlock = 0x4000_a000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const twis0_ns::RegisterBlock { + Self::PTR + } +} +impl Deref for TWIS2_NS { + type Target = twis0_ns::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for TWIS2_NS { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TWIS2_NS").finish() + } +} +#[doc = "I2C compatible Two-Wire Slave Interface with EasyDMA 4"] +pub use twis0_ns as twis2_ns; +#[doc = "UART with EasyDMA 4"] +pub struct UARTE2_NS { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for UARTE2_NS {} +impl UARTE2_NS { + #[doc = r"Pointer to the register block"] + pub const PTR: *const uarte0_ns::RegisterBlock = 0x4000_a000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const uarte0_ns::RegisterBlock { + Self::PTR + } +} +impl Deref for UARTE2_NS { + type Target = uarte0_ns::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for UARTE2_NS { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("UARTE2_NS").finish() + } +} +#[doc = "UART with EasyDMA 4"] +pub use uarte0_ns as uarte2_ns; +#[doc = "Serial Peripheral Interface Master with EasyDMA 5"] +pub struct SPIM2_S { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for SPIM2_S {} +impl SPIM2_S { + #[doc = r"Pointer to the register block"] + pub const PTR: *const spim0_ns::RegisterBlock = 0x5000_a000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const spim0_ns::RegisterBlock { + Self::PTR + } +} +impl Deref for SPIM2_S { + type Target = spim0_ns::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for SPIM2_S { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SPIM2_S").finish() + } +} +#[doc = "Serial Peripheral Interface Master with EasyDMA 5"] +pub use spim0_ns as spim2_s; +#[doc = "SPI Slave 5"] +pub struct SPIS2_S { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for SPIS2_S {} +impl SPIS2_S { + #[doc = r"Pointer to the register block"] + pub const PTR: *const spis0_ns::RegisterBlock = 0x5000_a000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const spis0_ns::RegisterBlock { + Self::PTR + } +} +impl Deref for SPIS2_S { + type Target = spis0_ns::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for SPIS2_S { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SPIS2_S").finish() + } +} +#[doc = "SPI Slave 5"] +pub use spis0_ns as spis2_s; +#[doc = "I2C compatible Two-Wire Master Interface with EasyDMA 5"] +pub struct TWIM2_S { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for TWIM2_S {} +impl TWIM2_S { + #[doc = r"Pointer to the register block"] + pub const PTR: *const twim0_ns::RegisterBlock = 0x5000_a000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const twim0_ns::RegisterBlock { + Self::PTR + } +} +impl Deref for TWIM2_S { + type Target = twim0_ns::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for TWIM2_S { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TWIM2_S").finish() + } +} +#[doc = "I2C compatible Two-Wire Master Interface with EasyDMA 5"] +pub use twim0_ns as twim2_s; +#[doc = "I2C compatible Two-Wire Slave Interface with EasyDMA 5"] +pub struct TWIS2_S { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for TWIS2_S {} +impl TWIS2_S { + #[doc = r"Pointer to the register block"] + pub const PTR: *const twis0_ns::RegisterBlock = 0x5000_a000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const twis0_ns::RegisterBlock { + Self::PTR + } +} +impl Deref for TWIS2_S { + type Target = twis0_ns::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for TWIS2_S { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TWIS2_S").finish() + } +} +#[doc = "I2C compatible Two-Wire Slave Interface with EasyDMA 5"] +pub use twis0_ns as twis2_s; +#[doc = "UART with EasyDMA 5"] +pub struct UARTE2_S { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for UARTE2_S {} +impl UARTE2_S { + #[doc = r"Pointer to the register block"] + pub const PTR: *const uarte0_ns::RegisterBlock = 0x5000_a000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const uarte0_ns::RegisterBlock { + Self::PTR + } +} +impl Deref for UARTE2_S { + type Target = uarte0_ns::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for UARTE2_S { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("UARTE2_S").finish() + } +} +#[doc = "UART with EasyDMA 5"] +pub use uarte0_ns as uarte2_s; +#[doc = "Serial Peripheral Interface Master with EasyDMA 6"] +pub struct SPIM3_NS { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for SPIM3_NS {} +impl SPIM3_NS { + #[doc = r"Pointer to the register block"] + pub const PTR: *const spim0_ns::RegisterBlock = 0x4000_b000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const spim0_ns::RegisterBlock { + Self::PTR + } +} +impl Deref for SPIM3_NS { + type Target = spim0_ns::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for SPIM3_NS { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SPIM3_NS").finish() + } +} +#[doc = "Serial Peripheral Interface Master with EasyDMA 6"] +pub use spim0_ns as spim3_ns; +#[doc = "SPI Slave 6"] +pub struct SPIS3_NS { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for SPIS3_NS {} +impl SPIS3_NS { + #[doc = r"Pointer to the register block"] + pub const PTR: *const spis0_ns::RegisterBlock = 0x4000_b000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const spis0_ns::RegisterBlock { + Self::PTR + } +} +impl Deref for SPIS3_NS { + type Target = spis0_ns::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for SPIS3_NS { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SPIS3_NS").finish() + } +} +#[doc = "SPI Slave 6"] +pub use spis0_ns as spis3_ns; +#[doc = "I2C compatible Two-Wire Master Interface with EasyDMA 6"] +pub struct TWIM3_NS { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for TWIM3_NS {} +impl TWIM3_NS { + #[doc = r"Pointer to the register block"] + pub const PTR: *const twim0_ns::RegisterBlock = 0x4000_b000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const twim0_ns::RegisterBlock { + Self::PTR + } +} +impl Deref for TWIM3_NS { + type Target = twim0_ns::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for TWIM3_NS { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TWIM3_NS").finish() + } +} +#[doc = "I2C compatible Two-Wire Master Interface with EasyDMA 6"] +pub use twim0_ns as twim3_ns; +#[doc = "I2C compatible Two-Wire Slave Interface with EasyDMA 6"] +pub struct TWIS3_NS { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for TWIS3_NS {} +impl TWIS3_NS { + #[doc = r"Pointer to the register block"] + pub const PTR: *const twis0_ns::RegisterBlock = 0x4000_b000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const twis0_ns::RegisterBlock { + Self::PTR + } +} +impl Deref for TWIS3_NS { + type Target = twis0_ns::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for TWIS3_NS { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TWIS3_NS").finish() + } +} +#[doc = "I2C compatible Two-Wire Slave Interface with EasyDMA 6"] +pub use twis0_ns as twis3_ns; +#[doc = "UART with EasyDMA 6"] +pub struct UARTE3_NS { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for UARTE3_NS {} +impl UARTE3_NS { + #[doc = r"Pointer to the register block"] + pub const PTR: *const uarte0_ns::RegisterBlock = 0x4000_b000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const uarte0_ns::RegisterBlock { + Self::PTR + } +} +impl Deref for UARTE3_NS { + type Target = uarte0_ns::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for UARTE3_NS { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("UARTE3_NS").finish() + } +} +#[doc = "UART with EasyDMA 6"] +pub use uarte0_ns as uarte3_ns; +#[doc = "Serial Peripheral Interface Master with EasyDMA 7"] +pub struct SPIM3_S { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for SPIM3_S {} +impl SPIM3_S { + #[doc = r"Pointer to the register block"] + pub const PTR: *const spim0_ns::RegisterBlock = 0x5000_b000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const spim0_ns::RegisterBlock { + Self::PTR + } +} +impl Deref for SPIM3_S { + type Target = spim0_ns::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for SPIM3_S { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SPIM3_S").finish() + } +} +#[doc = "Serial Peripheral Interface Master with EasyDMA 7"] +pub use spim0_ns as spim3_s; +#[doc = "SPI Slave 7"] +pub struct SPIS3_S { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for SPIS3_S {} +impl SPIS3_S { + #[doc = r"Pointer to the register block"] + pub const PTR: *const spis0_ns::RegisterBlock = 0x5000_b000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const spis0_ns::RegisterBlock { + Self::PTR + } +} +impl Deref for SPIS3_S { + type Target = spis0_ns::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for SPIS3_S { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SPIS3_S").finish() + } +} +#[doc = "SPI Slave 7"] +pub use spis0_ns as spis3_s; +#[doc = "I2C compatible Two-Wire Master Interface with EasyDMA 7"] +pub struct TWIM3_S { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for TWIM3_S {} +impl TWIM3_S { + #[doc = r"Pointer to the register block"] + pub const PTR: *const twim0_ns::RegisterBlock = 0x5000_b000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const twim0_ns::RegisterBlock { + Self::PTR + } +} +impl Deref for TWIM3_S { + type Target = twim0_ns::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for TWIM3_S { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TWIM3_S").finish() + } +} +#[doc = "I2C compatible Two-Wire Master Interface with EasyDMA 7"] +pub use twim0_ns as twim3_s; +#[doc = "I2C compatible Two-Wire Slave Interface with EasyDMA 7"] +pub struct TWIS3_S { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for TWIS3_S {} +impl TWIS3_S { + #[doc = r"Pointer to the register block"] + pub const PTR: *const twis0_ns::RegisterBlock = 0x5000_b000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const twis0_ns::RegisterBlock { + Self::PTR + } +} +impl Deref for TWIS3_S { + type Target = twis0_ns::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for TWIS3_S { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TWIS3_S").finish() + } +} +#[doc = "I2C compatible Two-Wire Slave Interface with EasyDMA 7"] +pub use twis0_ns as twis3_s; +#[doc = "UART with EasyDMA 7"] +pub struct UARTE3_S { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for UARTE3_S {} +impl UARTE3_S { + #[doc = r"Pointer to the register block"] + pub const PTR: *const uarte0_ns::RegisterBlock = 0x5000_b000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const uarte0_ns::RegisterBlock { + Self::PTR + } +} +impl Deref for UARTE3_S { + type Target = uarte0_ns::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for UARTE3_S { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("UARTE3_S").finish() + } +} +#[doc = "UART with EasyDMA 7"] +pub use uarte0_ns as uarte3_s; +#[doc = "GPIO Tasks and Events 0"] +pub struct GPIOTE0_S { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for GPIOTE0_S {} +impl GPIOTE0_S { + #[doc = r"Pointer to the register block"] + pub const PTR: *const gpiote0_s::RegisterBlock = 0x5000_d000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const gpiote0_s::RegisterBlock { + Self::PTR + } +} +impl Deref for GPIOTE0_S { + type Target = gpiote0_s::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for GPIOTE0_S { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GPIOTE0_S").finish() + } +} +#[doc = "GPIO Tasks and Events 0"] +pub mod gpiote0_s; +#[doc = "Analog to Digital Converter 0"] +pub struct SAADC_NS { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for SAADC_NS {} +impl SAADC_NS { + #[doc = r"Pointer to the register block"] + pub const PTR: *const saadc_ns::RegisterBlock = 0x4000_e000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const saadc_ns::RegisterBlock { + Self::PTR + } +} +impl Deref for SAADC_NS { + type Target = saadc_ns::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for SAADC_NS { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SAADC_NS").finish() + } +} +#[doc = "Analog to Digital Converter 0"] +pub mod saadc_ns; +#[doc = "Analog to Digital Converter 1"] +pub struct SAADC_S { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for SAADC_S {} +impl SAADC_S { + #[doc = r"Pointer to the register block"] + pub const PTR: *const saadc_ns::RegisterBlock = 0x5000_e000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const saadc_ns::RegisterBlock { + Self::PTR + } +} +impl Deref for SAADC_S { + type Target = saadc_ns::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for SAADC_S { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SAADC_S").finish() + } +} +#[doc = "Analog to Digital Converter 1"] +pub use saadc_ns as saadc_s; +#[doc = "Timer/Counter 0"] +pub struct TIMER0_NS { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for TIMER0_NS {} +impl TIMER0_NS { + #[doc = r"Pointer to the register block"] + pub const PTR: *const timer0_ns::RegisterBlock = 0x4000_f000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const timer0_ns::RegisterBlock { + Self::PTR + } +} +impl Deref for TIMER0_NS { + type Target = timer0_ns::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for TIMER0_NS { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TIMER0_NS").finish() + } +} +#[doc = "Timer/Counter 0"] +pub mod timer0_ns; +#[doc = "Timer/Counter 1"] +pub struct TIMER0_S { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for TIMER0_S {} +impl TIMER0_S { + #[doc = r"Pointer to the register block"] + pub const PTR: *const timer0_ns::RegisterBlock = 0x5000_f000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const timer0_ns::RegisterBlock { + Self::PTR + } +} +impl Deref for TIMER0_S { + type Target = timer0_ns::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for TIMER0_S { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TIMER0_S").finish() + } +} +#[doc = "Timer/Counter 1"] +pub use timer0_ns as timer0_s; +#[doc = "Timer/Counter 2"] +pub struct TIMER1_NS { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for TIMER1_NS {} +impl TIMER1_NS { + #[doc = r"Pointer to the register block"] + pub const PTR: *const timer0_ns::RegisterBlock = 0x4001_0000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const timer0_ns::RegisterBlock { + Self::PTR + } +} +impl Deref for TIMER1_NS { + type Target = timer0_ns::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for TIMER1_NS { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TIMER1_NS").finish() + } +} +#[doc = "Timer/Counter 2"] +pub use timer0_ns as timer1_ns; +#[doc = "Timer/Counter 3"] +pub struct TIMER1_S { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for TIMER1_S {} +impl TIMER1_S { + #[doc = r"Pointer to the register block"] + pub const PTR: *const timer0_ns::RegisterBlock = 0x5001_0000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const timer0_ns::RegisterBlock { + Self::PTR + } +} +impl Deref for TIMER1_S { + type Target = timer0_ns::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for TIMER1_S { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TIMER1_S").finish() + } +} +#[doc = "Timer/Counter 3"] +pub use timer0_ns as timer1_s; +#[doc = "Timer/Counter 4"] +pub struct TIMER2_NS { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for TIMER2_NS {} +impl TIMER2_NS { + #[doc = r"Pointer to the register block"] + pub const PTR: *const timer0_ns::RegisterBlock = 0x4001_1000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const timer0_ns::RegisterBlock { + Self::PTR + } +} +impl Deref for TIMER2_NS { + type Target = timer0_ns::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for TIMER2_NS { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TIMER2_NS").finish() + } +} +#[doc = "Timer/Counter 4"] +pub use timer0_ns as timer2_ns; +#[doc = "Timer/Counter 5"] +pub struct TIMER2_S { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for TIMER2_S {} +impl TIMER2_S { + #[doc = r"Pointer to the register block"] + pub const PTR: *const timer0_ns::RegisterBlock = 0x5001_1000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const timer0_ns::RegisterBlock { + Self::PTR + } +} +impl Deref for TIMER2_S { + type Target = timer0_ns::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for TIMER2_S { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TIMER2_S").finish() + } +} +#[doc = "Timer/Counter 5"] +pub use timer0_ns as timer2_s; +#[doc = "Real-time counter 0"] +pub struct RTC0_NS { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for RTC0_NS {} +impl RTC0_NS { + #[doc = r"Pointer to the register block"] + pub const PTR: *const rtc0_ns::RegisterBlock = 0x4001_4000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const rtc0_ns::RegisterBlock { + Self::PTR + } +} +impl Deref for RTC0_NS { + type Target = rtc0_ns::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for RTC0_NS { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RTC0_NS").finish() + } +} +#[doc = "Real-time counter 0"] +pub mod rtc0_ns; +#[doc = "Real-time counter 1"] +pub struct RTC0_S { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for RTC0_S {} +impl RTC0_S { + #[doc = r"Pointer to the register block"] + pub const PTR: *const rtc0_ns::RegisterBlock = 0x5001_4000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const rtc0_ns::RegisterBlock { + Self::PTR + } +} +impl Deref for RTC0_S { + type Target = rtc0_ns::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for RTC0_S { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RTC0_S").finish() + } +} +#[doc = "Real-time counter 1"] +pub use rtc0_ns as rtc0_s; +#[doc = "Real-time counter 2"] +pub struct RTC1_NS { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for RTC1_NS {} +impl RTC1_NS { + #[doc = r"Pointer to the register block"] + pub const PTR: *const rtc0_ns::RegisterBlock = 0x4001_5000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const rtc0_ns::RegisterBlock { + Self::PTR + } +} +impl Deref for RTC1_NS { + type Target = rtc0_ns::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for RTC1_NS { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RTC1_NS").finish() + } +} +#[doc = "Real-time counter 2"] +pub use rtc0_ns as rtc1_ns; +#[doc = "Real-time counter 3"] +pub struct RTC1_S { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for RTC1_S {} +impl RTC1_S { + #[doc = r"Pointer to the register block"] + pub const PTR: *const rtc0_ns::RegisterBlock = 0x5001_5000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const rtc0_ns::RegisterBlock { + Self::PTR + } +} +impl Deref for RTC1_S { + type Target = rtc0_ns::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for RTC1_S { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RTC1_S").finish() + } +} +#[doc = "Real-time counter 3"] +pub use rtc0_ns as rtc1_s; +#[doc = "Distributed programmable peripheral interconnect controller 0"] +pub struct DPPIC_NS { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for DPPIC_NS {} +impl DPPIC_NS { + #[doc = r"Pointer to the register block"] + pub const PTR: *const dppic_ns::RegisterBlock = 0x4001_7000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const dppic_ns::RegisterBlock { + Self::PTR + } +} +impl Deref for DPPIC_NS { + type Target = dppic_ns::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for DPPIC_NS { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DPPIC_NS").finish() + } +} +#[doc = "Distributed programmable peripheral interconnect controller 0"] +pub mod dppic_ns; +#[doc = "Distributed programmable peripheral interconnect controller 1"] +pub struct DPPIC_S { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for DPPIC_S {} +impl DPPIC_S { + #[doc = r"Pointer to the register block"] + pub const PTR: *const dppic_ns::RegisterBlock = 0x5001_7000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const dppic_ns::RegisterBlock { + Self::PTR + } +} +impl Deref for DPPIC_S { + type Target = dppic_ns::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for DPPIC_S { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DPPIC_S").finish() + } +} +#[doc = "Distributed programmable peripheral interconnect controller 1"] +pub use dppic_ns as dppic_s; +#[doc = "Watchdog Timer 0"] +pub struct WDT_NS { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for WDT_NS {} +impl WDT_NS { + #[doc = r"Pointer to the register block"] + pub const PTR: *const wdt_ns::RegisterBlock = 0x4001_8000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const wdt_ns::RegisterBlock { + Self::PTR + } +} +impl Deref for WDT_NS { + type Target = wdt_ns::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for WDT_NS { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("WDT_NS").finish() + } +} +#[doc = "Watchdog Timer 0"] +pub mod wdt_ns; +#[doc = "Watchdog Timer 1"] +pub struct WDT_S { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for WDT_S {} +impl WDT_S { + #[doc = r"Pointer to the register block"] + pub const PTR: *const wdt_ns::RegisterBlock = 0x5001_8000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const wdt_ns::RegisterBlock { + Self::PTR + } +} +impl Deref for WDT_S { + type Target = wdt_ns::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for WDT_S { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("WDT_S").finish() + } +} +#[doc = "Watchdog Timer 1"] +pub use wdt_ns as wdt_s; +#[doc = "Event generator unit 0"] +pub struct EGU0_NS { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for EGU0_NS {} +impl EGU0_NS { + #[doc = r"Pointer to the register block"] + pub const PTR: *const egu0_ns::RegisterBlock = 0x4001_b000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const egu0_ns::RegisterBlock { + Self::PTR + } +} +impl Deref for EGU0_NS { + type Target = egu0_ns::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for EGU0_NS { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("EGU0_NS").finish() + } +} +#[doc = "Event generator unit 0"] +pub mod egu0_ns; +#[doc = "Event generator unit 1"] +pub struct EGU0_S { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for EGU0_S {} +impl EGU0_S { + #[doc = r"Pointer to the register block"] + pub const PTR: *const egu0_ns::RegisterBlock = 0x5001_b000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const egu0_ns::RegisterBlock { + Self::PTR + } +} +impl Deref for EGU0_S { + type Target = egu0_ns::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for EGU0_S { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("EGU0_S").finish() + } +} +#[doc = "Event generator unit 1"] +pub use egu0_ns as egu0_s; +#[doc = "Event generator unit 2"] +pub struct EGU1_NS { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for EGU1_NS {} +impl EGU1_NS { + #[doc = r"Pointer to the register block"] + pub const PTR: *const egu0_ns::RegisterBlock = 0x4001_c000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const egu0_ns::RegisterBlock { + Self::PTR + } +} +impl Deref for EGU1_NS { + type Target = egu0_ns::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for EGU1_NS { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("EGU1_NS").finish() + } +} +#[doc = "Event generator unit 2"] +pub use egu0_ns as egu1_ns; +#[doc = "Event generator unit 3"] +pub struct EGU1_S { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for EGU1_S {} +impl EGU1_S { + #[doc = r"Pointer to the register block"] + pub const PTR: *const egu0_ns::RegisterBlock = 0x5001_c000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const egu0_ns::RegisterBlock { + Self::PTR + } +} +impl Deref for EGU1_S { + type Target = egu0_ns::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for EGU1_S { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("EGU1_S").finish() + } +} +#[doc = "Event generator unit 3"] +pub use egu0_ns as egu1_s; +#[doc = "Event generator unit 4"] +pub struct EGU2_NS { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for EGU2_NS {} +impl EGU2_NS { + #[doc = r"Pointer to the register block"] + pub const PTR: *const egu0_ns::RegisterBlock = 0x4001_d000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const egu0_ns::RegisterBlock { + Self::PTR + } +} +impl Deref for EGU2_NS { + type Target = egu0_ns::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for EGU2_NS { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("EGU2_NS").finish() + } +} +#[doc = "Event generator unit 4"] +pub use egu0_ns as egu2_ns; +#[doc = "Event generator unit 5"] +pub struct EGU2_S { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for EGU2_S {} +impl EGU2_S { + #[doc = r"Pointer to the register block"] + pub const PTR: *const egu0_ns::RegisterBlock = 0x5001_d000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const egu0_ns::RegisterBlock { + Self::PTR + } +} +impl Deref for EGU2_S { + type Target = egu0_ns::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for EGU2_S { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("EGU2_S").finish() + } +} +#[doc = "Event generator unit 5"] +pub use egu0_ns as egu2_s; +#[doc = "Event generator unit 6"] +pub struct EGU3_NS { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for EGU3_NS {} +impl EGU3_NS { + #[doc = r"Pointer to the register block"] + pub const PTR: *const egu0_ns::RegisterBlock = 0x4001_e000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const egu0_ns::RegisterBlock { + Self::PTR + } +} +impl Deref for EGU3_NS { + type Target = egu0_ns::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for EGU3_NS { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("EGU3_NS").finish() + } +} +#[doc = "Event generator unit 6"] +pub use egu0_ns as egu3_ns; +#[doc = "Event generator unit 7"] +pub struct EGU3_S { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for EGU3_S {} +impl EGU3_S { + #[doc = r"Pointer to the register block"] + pub const PTR: *const egu0_ns::RegisterBlock = 0x5001_e000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const egu0_ns::RegisterBlock { + Self::PTR + } +} +impl Deref for EGU3_S { + type Target = egu0_ns::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for EGU3_S { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("EGU3_S").finish() + } +} +#[doc = "Event generator unit 7"] +pub use egu0_ns as egu3_s; +#[doc = "Event generator unit 8"] +pub struct EGU4_NS { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for EGU4_NS {} +impl EGU4_NS { + #[doc = r"Pointer to the register block"] + pub const PTR: *const egu0_ns::RegisterBlock = 0x4001_f000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const egu0_ns::RegisterBlock { + Self::PTR + } +} +impl Deref for EGU4_NS { + type Target = egu0_ns::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for EGU4_NS { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("EGU4_NS").finish() + } +} +#[doc = "Event generator unit 8"] +pub use egu0_ns as egu4_ns; +#[doc = "Event generator unit 9"] +pub struct EGU4_S { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for EGU4_S {} +impl EGU4_S { + #[doc = r"Pointer to the register block"] + pub const PTR: *const egu0_ns::RegisterBlock = 0x5001_f000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const egu0_ns::RegisterBlock { + Self::PTR + } +} +impl Deref for EGU4_S { + type Target = egu0_ns::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for EGU4_S { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("EGU4_S").finish() + } +} +#[doc = "Event generator unit 9"] +pub use egu0_ns as egu4_s; +#[doc = "Event generator unit 10"] +pub struct EGU5_NS { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for EGU5_NS {} +impl EGU5_NS { + #[doc = r"Pointer to the register block"] + pub const PTR: *const egu0_ns::RegisterBlock = 0x4002_0000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const egu0_ns::RegisterBlock { + Self::PTR + } +} +impl Deref for EGU5_NS { + type Target = egu0_ns::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for EGU5_NS { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("EGU5_NS").finish() + } +} +#[doc = "Event generator unit 10"] +pub use egu0_ns as egu5_ns; +#[doc = "Event generator unit 11"] +pub struct EGU5_S { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for EGU5_S {} +impl EGU5_S { + #[doc = r"Pointer to the register block"] + pub const PTR: *const egu0_ns::RegisterBlock = 0x5002_0000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const egu0_ns::RegisterBlock { + Self::PTR + } +} +impl Deref for EGU5_S { + type Target = egu0_ns::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for EGU5_S { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("EGU5_S").finish() + } +} +#[doc = "Event generator unit 11"] +pub use egu0_ns as egu5_s; +#[doc = "Pulse width modulation unit 0"] +pub struct PWM0_NS { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for PWM0_NS {} +impl PWM0_NS { + #[doc = r"Pointer to the register block"] + pub const PTR: *const pwm0_ns::RegisterBlock = 0x4002_1000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const pwm0_ns::RegisterBlock { + Self::PTR + } +} +impl Deref for PWM0_NS { + type Target = pwm0_ns::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for PWM0_NS { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PWM0_NS").finish() + } +} +#[doc = "Pulse width modulation unit 0"] +pub mod pwm0_ns; +#[doc = "Pulse width modulation unit 1"] +pub struct PWM0_S { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for PWM0_S {} +impl PWM0_S { + #[doc = r"Pointer to the register block"] + pub const PTR: *const pwm0_ns::RegisterBlock = 0x5002_1000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const pwm0_ns::RegisterBlock { + Self::PTR + } +} +impl Deref for PWM0_S { + type Target = pwm0_ns::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for PWM0_S { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PWM0_S").finish() + } +} +#[doc = "Pulse width modulation unit 1"] +pub use pwm0_ns as pwm0_s; +#[doc = "Pulse width modulation unit 2"] +pub struct PWM1_NS { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for PWM1_NS {} +impl PWM1_NS { + #[doc = r"Pointer to the register block"] + pub const PTR: *const pwm0_ns::RegisterBlock = 0x4002_2000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const pwm0_ns::RegisterBlock { + Self::PTR + } +} +impl Deref for PWM1_NS { + type Target = pwm0_ns::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for PWM1_NS { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PWM1_NS").finish() + } +} +#[doc = "Pulse width modulation unit 2"] +pub use pwm0_ns as pwm1_ns; +#[doc = "Pulse width modulation unit 3"] +pub struct PWM1_S { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for PWM1_S {} +impl PWM1_S { + #[doc = r"Pointer to the register block"] + pub const PTR: *const pwm0_ns::RegisterBlock = 0x5002_2000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const pwm0_ns::RegisterBlock { + Self::PTR + } +} +impl Deref for PWM1_S { + type Target = pwm0_ns::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for PWM1_S { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PWM1_S").finish() + } +} +#[doc = "Pulse width modulation unit 3"] +pub use pwm0_ns as pwm1_s; +#[doc = "Pulse width modulation unit 4"] +pub struct PWM2_NS { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for PWM2_NS {} +impl PWM2_NS { + #[doc = r"Pointer to the register block"] + pub const PTR: *const pwm0_ns::RegisterBlock = 0x4002_3000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const pwm0_ns::RegisterBlock { + Self::PTR + } +} +impl Deref for PWM2_NS { + type Target = pwm0_ns::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for PWM2_NS { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PWM2_NS").finish() + } +} +#[doc = "Pulse width modulation unit 4"] +pub use pwm0_ns as pwm2_ns; +#[doc = "Pulse width modulation unit 5"] +pub struct PWM2_S { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for PWM2_S {} +impl PWM2_S { + #[doc = r"Pointer to the register block"] + pub const PTR: *const pwm0_ns::RegisterBlock = 0x5002_3000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const pwm0_ns::RegisterBlock { + Self::PTR + } +} +impl Deref for PWM2_S { + type Target = pwm0_ns::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for PWM2_S { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PWM2_S").finish() + } +} +#[doc = "Pulse width modulation unit 5"] +pub use pwm0_ns as pwm2_s; +#[doc = "Pulse width modulation unit 6"] +pub struct PWM3_NS { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for PWM3_NS {} +impl PWM3_NS { + #[doc = r"Pointer to the register block"] + pub const PTR: *const pwm0_ns::RegisterBlock = 0x4002_4000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const pwm0_ns::RegisterBlock { + Self::PTR + } +} +impl Deref for PWM3_NS { + type Target = pwm0_ns::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for PWM3_NS { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PWM3_NS").finish() + } +} +#[doc = "Pulse width modulation unit 6"] +pub use pwm0_ns as pwm3_ns; +#[doc = "Pulse width modulation unit 7"] +pub struct PWM3_S { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for PWM3_S {} +impl PWM3_S { + #[doc = r"Pointer to the register block"] + pub const PTR: *const pwm0_ns::RegisterBlock = 0x5002_4000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const pwm0_ns::RegisterBlock { + Self::PTR + } +} +impl Deref for PWM3_S { + type Target = pwm0_ns::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for PWM3_S { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PWM3_S").finish() + } +} +#[doc = "Pulse width modulation unit 7"] +pub use pwm0_ns as pwm3_s; +#[doc = "Pulse Density Modulation (Digital Microphone) Interface 0"] +pub struct PDM_NS { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for PDM_NS {} +impl PDM_NS { + #[doc = r"Pointer to the register block"] + pub const PTR: *const pdm_ns::RegisterBlock = 0x4002_6000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const pdm_ns::RegisterBlock { + Self::PTR + } +} +impl Deref for PDM_NS { + type Target = pdm_ns::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for PDM_NS { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PDM_NS").finish() + } +} +#[doc = "Pulse Density Modulation (Digital Microphone) Interface 0"] +pub mod pdm_ns; +#[doc = "Pulse Density Modulation (Digital Microphone) Interface 1"] +pub struct PDM_S { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for PDM_S {} +impl PDM_S { + #[doc = r"Pointer to the register block"] + pub const PTR: *const pdm_ns::RegisterBlock = 0x5002_6000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const pdm_ns::RegisterBlock { + Self::PTR + } +} +impl Deref for PDM_S { + type Target = pdm_ns::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for PDM_S { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PDM_S").finish() + } +} +#[doc = "Pulse Density Modulation (Digital Microphone) Interface 1"] +pub use pdm_ns as pdm_s; +#[doc = "Inter-IC Sound 0"] +pub struct I2S_NS { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for I2S_NS {} +impl I2S_NS { + #[doc = r"Pointer to the register block"] + pub const PTR: *const i2s_ns::RegisterBlock = 0x4002_8000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const i2s_ns::RegisterBlock { + Self::PTR + } +} +impl Deref for I2S_NS { + type Target = i2s_ns::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for I2S_NS { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("I2S_NS").finish() + } +} +#[doc = "Inter-IC Sound 0"] +pub mod i2s_ns; +#[doc = "Inter-IC Sound 1"] +pub struct I2S_S { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for I2S_S {} +impl I2S_S { + #[doc = r"Pointer to the register block"] + pub const PTR: *const i2s_ns::RegisterBlock = 0x5002_8000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const i2s_ns::RegisterBlock { + Self::PTR + } +} +impl Deref for I2S_S { + type Target = i2s_ns::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for I2S_S { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("I2S_S").finish() + } +} +#[doc = "Inter-IC Sound 1"] +pub use i2s_ns as i2s_s; +#[doc = "Interprocessor communication 0"] +pub struct IPC_NS { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for IPC_NS {} +impl IPC_NS { + #[doc = r"Pointer to the register block"] + pub const PTR: *const ipc_ns::RegisterBlock = 0x4002_a000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const ipc_ns::RegisterBlock { + Self::PTR + } +} +impl Deref for IPC_NS { + type Target = ipc_ns::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for IPC_NS { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("IPC_NS").finish() + } +} +#[doc = "Interprocessor communication 0"] +pub mod ipc_ns; +#[doc = "Interprocessor communication 1"] +pub struct IPC_S { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for IPC_S {} +impl IPC_S { + #[doc = r"Pointer to the register block"] + pub const PTR: *const ipc_ns::RegisterBlock = 0x5002_a000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const ipc_ns::RegisterBlock { + Self::PTR + } +} +impl Deref for IPC_S { + type Target = ipc_ns::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for IPC_S { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("IPC_S").finish() + } +} +#[doc = "Interprocessor communication 1"] +pub use ipc_ns as ipc_s; +#[doc = "FPU"] +pub struct FPU_NS { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for FPU_NS {} +impl FPU_NS { + #[doc = r"Pointer to the register block"] + pub const PTR: *const fpu_ns::RegisterBlock = 0x4002_c000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const fpu_ns::RegisterBlock { + Self::PTR + } +} +impl Deref for FPU_NS { + type Target = fpu_ns::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for FPU_NS { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FPU_NS").finish() + } +} +#[doc = "FPU"] +pub mod fpu_ns; +#[doc = "GPIO Tasks and Events 1"] +pub struct GPIOTE1_NS { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for GPIOTE1_NS {} +impl GPIOTE1_NS { + #[doc = r"Pointer to the register block"] + pub const PTR: *const gpiote0_s::RegisterBlock = 0x4003_1000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const gpiote0_s::RegisterBlock { + Self::PTR + } +} +impl Deref for GPIOTE1_NS { + type Target = gpiote0_s::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for GPIOTE1_NS { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GPIOTE1_NS").finish() + } +} +#[doc = "GPIO Tasks and Events 1"] +pub use gpiote0_s as gpiote1_ns; +#[doc = "Access Port Protection 0"] +pub struct APPROTECT_NS { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for APPROTECT_NS {} +impl APPROTECT_NS { + #[doc = r"Pointer to the register block"] + pub const PTR: *const approtect_ns::RegisterBlock = 0x4003_9000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const approtect_ns::RegisterBlock { + Self::PTR + } +} +impl Deref for APPROTECT_NS { + type Target = approtect_ns::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for APPROTECT_NS { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("APPROTECT_NS").finish() + } +} +#[doc = "Access Port Protection 0"] +pub mod approtect_ns; +#[doc = "Key management unit 0"] +pub struct KMU_NS { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for KMU_NS {} +impl KMU_NS { + #[doc = r"Pointer to the register block"] + pub const PTR: *const kmu_ns::RegisterBlock = 0x4003_9000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const kmu_ns::RegisterBlock { + Self::PTR + } +} +impl Deref for KMU_NS { + type Target = kmu_ns::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for KMU_NS { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("KMU_NS").finish() + } +} +#[doc = "Key management unit 0"] +pub mod kmu_ns; +#[doc = "Non-volatile memory controller 0"] +pub struct NVMC_NS { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for NVMC_NS {} +impl NVMC_NS { + #[doc = r"Pointer to the register block"] + pub const PTR: *const nvmc_ns::RegisterBlock = 0x4003_9000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const nvmc_ns::RegisterBlock { + Self::PTR + } +} +impl Deref for NVMC_NS { + type Target = nvmc_ns::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for NVMC_NS { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("NVMC_NS").finish() + } +} +#[doc = "Non-volatile memory controller 0"] +pub mod nvmc_ns; +#[doc = "Access Port Protection 1"] +pub struct APPROTECT_S { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for APPROTECT_S {} +impl APPROTECT_S { + #[doc = r"Pointer to the register block"] + pub const PTR: *const approtect_ns::RegisterBlock = 0x5003_9000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const approtect_ns::RegisterBlock { + Self::PTR + } +} +impl Deref for APPROTECT_S { + type Target = approtect_ns::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for APPROTECT_S { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("APPROTECT_S").finish() + } +} +#[doc = "Access Port Protection 1"] +pub use approtect_ns as approtect_s; +#[doc = "Key management unit 1"] +pub struct KMU_S { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for KMU_S {} +impl KMU_S { + #[doc = r"Pointer to the register block"] + pub const PTR: *const kmu_ns::RegisterBlock = 0x5003_9000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const kmu_ns::RegisterBlock { + Self::PTR + } +} +impl Deref for KMU_S { + type Target = kmu_ns::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for KMU_S { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("KMU_S").finish() + } +} +#[doc = "Key management unit 1"] +pub use kmu_ns as kmu_s; +#[doc = "Non-volatile memory controller 1"] +pub struct NVMC_S { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for NVMC_S {} +impl NVMC_S { + #[doc = r"Pointer to the register block"] + pub const PTR: *const nvmc_ns::RegisterBlock = 0x5003_9000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const nvmc_ns::RegisterBlock { + Self::PTR + } +} +impl Deref for NVMC_S { + type Target = nvmc_ns::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for NVMC_S { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("NVMC_S").finish() + } +} +#[doc = "Non-volatile memory controller 1"] +pub use nvmc_ns as nvmc_s; +#[doc = "Volatile Memory controller 0"] +pub struct VMC_NS { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for VMC_NS {} +impl VMC_NS { + #[doc = r"Pointer to the register block"] + pub const PTR: *const vmc_ns::RegisterBlock = 0x4003_a000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const vmc_ns::RegisterBlock { + Self::PTR + } +} +impl Deref for VMC_NS { + type Target = vmc_ns::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for VMC_NS { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("VMC_NS").finish() + } +} +#[doc = "Volatile Memory controller 0"] +pub mod vmc_ns; +#[doc = "Volatile Memory controller 1"] +pub struct VMC_S { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for VMC_S {} +impl VMC_S { + #[doc = r"Pointer to the register block"] + pub const PTR: *const vmc_ns::RegisterBlock = 0x5003_a000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const vmc_ns::RegisterBlock { + Self::PTR + } +} +impl Deref for VMC_S { + type Target = vmc_ns::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for VMC_S { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("VMC_S").finish() + } +} +#[doc = "Volatile Memory controller 1"] +pub use vmc_ns as vmc_s; +#[doc = "CRYPTOCELL HOST_RGF interface"] +pub struct CC_HOST_RGF_S { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for CC_HOST_RGF_S {} +impl CC_HOST_RGF_S { + #[doc = r"Pointer to the register block"] + pub const PTR: *const cc_host_rgf_s::RegisterBlock = 0x5084_0000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const cc_host_rgf_s::RegisterBlock { + Self::PTR + } +} +impl Deref for CC_HOST_RGF_S { + type Target = cc_host_rgf_s::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for CC_HOST_RGF_S { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CC_HOST_RGF_S").finish() + } +} +#[doc = "CRYPTOCELL HOST_RGF interface"] +pub mod cc_host_rgf_s; +#[doc = "ARM TrustZone CryptoCell register interface"] +pub struct CRYPTOCELL_S { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for CRYPTOCELL_S {} +impl CRYPTOCELL_S { + #[doc = r"Pointer to the register block"] + pub const PTR: *const cryptocell_s::RegisterBlock = 0x5084_0000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const cryptocell_s::RegisterBlock { + Self::PTR + } +} +impl Deref for CRYPTOCELL_S { + type Target = cryptocell_s::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for CRYPTOCELL_S { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CRYPTOCELL_S").finish() + } +} +#[doc = "ARM TrustZone CryptoCell register interface"] +pub mod cryptocell_s; +#[doc = "GPIO Port 0"] +pub struct P0_NS { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for P0_NS {} +impl P0_NS { + #[doc = r"Pointer to the register block"] + pub const PTR: *const p0_ns::RegisterBlock = 0x4084_2500 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const p0_ns::RegisterBlock { + Self::PTR + } +} +impl Deref for P0_NS { + type Target = p0_ns::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for P0_NS { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("P0_NS").finish() + } +} +#[doc = "GPIO Port 0"] +pub mod p0_ns; +#[doc = "GPIO Port 1"] +pub struct P0_S { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for P0_S {} +impl P0_S { + #[doc = r"Pointer to the register block"] + pub const PTR: *const p0_ns::RegisterBlock = 0x5084_2500 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const p0_ns::RegisterBlock { + Self::PTR + } +} +impl Deref for P0_S { + type Target = p0_ns::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for P0_S { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("P0_S").finish() + } +} +#[doc = "GPIO Port 1"] +pub use p0_ns as p0_s; +#[no_mangle] +static mut DEVICE_PERIPHERALS: bool = false; +#[doc = r"All the peripherals"] +#[allow(non_snake_case)] +pub struct Peripherals { + #[doc = "FICR_S"] + pub FICR_S: FICR_S, + #[doc = "UICR_S"] + pub UICR_S: UICR_S, + #[doc = "TAD_S"] + pub TAD_S: TAD_S, + #[doc = "SPU_S"] + pub SPU_S: SPU_S, + #[doc = "REGULATORS_NS"] + pub REGULATORS_NS: REGULATORS_NS, + #[doc = "REGULATORS_S"] + pub REGULATORS_S: REGULATORS_S, + #[doc = "CLOCK_NS"] + pub CLOCK_NS: CLOCK_NS, + #[doc = "POWER_NS"] + pub POWER_NS: POWER_NS, + #[doc = "CLOCK_S"] + pub CLOCK_S: CLOCK_S, + #[doc = "POWER_S"] + pub POWER_S: POWER_S, + #[doc = "CTRL_AP_PERI_S"] + pub CTRL_AP_PERI_S: CTRL_AP_PERI_S, + #[doc = "SPIM0_NS"] + pub SPIM0_NS: SPIM0_NS, + #[doc = "SPIS0_NS"] + pub SPIS0_NS: SPIS0_NS, + #[doc = "TWIM0_NS"] + pub TWIM0_NS: TWIM0_NS, + #[doc = "TWIS0_NS"] + pub TWIS0_NS: TWIS0_NS, + #[doc = "UARTE0_NS"] + pub UARTE0_NS: UARTE0_NS, + #[doc = "SPIM0_S"] + pub SPIM0_S: SPIM0_S, + #[doc = "SPIS0_S"] + pub SPIS0_S: SPIS0_S, + #[doc = "TWIM0_S"] + pub TWIM0_S: TWIM0_S, + #[doc = "TWIS0_S"] + pub TWIS0_S: TWIS0_S, + #[doc = "UARTE0_S"] + pub UARTE0_S: UARTE0_S, + #[doc = "SPIM1_NS"] + pub SPIM1_NS: SPIM1_NS, + #[doc = "SPIS1_NS"] + pub SPIS1_NS: SPIS1_NS, + #[doc = "TWIM1_NS"] + pub TWIM1_NS: TWIM1_NS, + #[doc = "TWIS1_NS"] + pub TWIS1_NS: TWIS1_NS, + #[doc = "UARTE1_NS"] + pub UARTE1_NS: UARTE1_NS, + #[doc = "SPIM1_S"] + pub SPIM1_S: SPIM1_S, + #[doc = "SPIS1_S"] + pub SPIS1_S: SPIS1_S, + #[doc = "TWIM1_S"] + pub TWIM1_S: TWIM1_S, + #[doc = "TWIS1_S"] + pub TWIS1_S: TWIS1_S, + #[doc = "UARTE1_S"] + pub UARTE1_S: UARTE1_S, + #[doc = "SPIM2_NS"] + pub SPIM2_NS: SPIM2_NS, + #[doc = "SPIS2_NS"] + pub SPIS2_NS: SPIS2_NS, + #[doc = "TWIM2_NS"] + pub TWIM2_NS: TWIM2_NS, + #[doc = "TWIS2_NS"] + pub TWIS2_NS: TWIS2_NS, + #[doc = "UARTE2_NS"] + pub UARTE2_NS: UARTE2_NS, + #[doc = "SPIM2_S"] + pub SPIM2_S: SPIM2_S, + #[doc = "SPIS2_S"] + pub SPIS2_S: SPIS2_S, + #[doc = "TWIM2_S"] + pub TWIM2_S: TWIM2_S, + #[doc = "TWIS2_S"] + pub TWIS2_S: TWIS2_S, + #[doc = "UARTE2_S"] + pub UARTE2_S: UARTE2_S, + #[doc = "SPIM3_NS"] + pub SPIM3_NS: SPIM3_NS, + #[doc = "SPIS3_NS"] + pub SPIS3_NS: SPIS3_NS, + #[doc = "TWIM3_NS"] + pub TWIM3_NS: TWIM3_NS, + #[doc = "TWIS3_NS"] + pub TWIS3_NS: TWIS3_NS, + #[doc = "UARTE3_NS"] + pub UARTE3_NS: UARTE3_NS, + #[doc = "SPIM3_S"] + pub SPIM3_S: SPIM3_S, + #[doc = "SPIS3_S"] + pub SPIS3_S: SPIS3_S, + #[doc = "TWIM3_S"] + pub TWIM3_S: TWIM3_S, + #[doc = "TWIS3_S"] + pub TWIS3_S: TWIS3_S, + #[doc = "UARTE3_S"] + pub UARTE3_S: UARTE3_S, + #[doc = "GPIOTE0_S"] + pub GPIOTE0_S: GPIOTE0_S, + #[doc = "SAADC_NS"] + pub SAADC_NS: SAADC_NS, + #[doc = "SAADC_S"] + pub SAADC_S: SAADC_S, + #[doc = "TIMER0_NS"] + pub TIMER0_NS: TIMER0_NS, + #[doc = "TIMER0_S"] + pub TIMER0_S: TIMER0_S, + #[doc = "TIMER1_NS"] + pub TIMER1_NS: TIMER1_NS, + #[doc = "TIMER1_S"] + pub TIMER1_S: TIMER1_S, + #[doc = "TIMER2_NS"] + pub TIMER2_NS: TIMER2_NS, + #[doc = "TIMER2_S"] + pub TIMER2_S: TIMER2_S, + #[doc = "RTC0_NS"] + pub RTC0_NS: RTC0_NS, + #[doc = "RTC0_S"] + pub RTC0_S: RTC0_S, + #[doc = "RTC1_NS"] + pub RTC1_NS: RTC1_NS, + #[doc = "RTC1_S"] + pub RTC1_S: RTC1_S, + #[doc = "DPPIC_NS"] + pub DPPIC_NS: DPPIC_NS, + #[doc = "DPPIC_S"] + pub DPPIC_S: DPPIC_S, + #[doc = "WDT_NS"] + pub WDT_NS: WDT_NS, + #[doc = "WDT_S"] + pub WDT_S: WDT_S, + #[doc = "EGU0_NS"] + pub EGU0_NS: EGU0_NS, + #[doc = "EGU0_S"] + pub EGU0_S: EGU0_S, + #[doc = "EGU1_NS"] + pub EGU1_NS: EGU1_NS, + #[doc = "EGU1_S"] + pub EGU1_S: EGU1_S, + #[doc = "EGU2_NS"] + pub EGU2_NS: EGU2_NS, + #[doc = "EGU2_S"] + pub EGU2_S: EGU2_S, + #[doc = "EGU3_NS"] + pub EGU3_NS: EGU3_NS, + #[doc = "EGU3_S"] + pub EGU3_S: EGU3_S, + #[doc = "EGU4_NS"] + pub EGU4_NS: EGU4_NS, + #[doc = "EGU4_S"] + pub EGU4_S: EGU4_S, + #[doc = "EGU5_NS"] + pub EGU5_NS: EGU5_NS, + #[doc = "EGU5_S"] + pub EGU5_S: EGU5_S, + #[doc = "PWM0_NS"] + pub PWM0_NS: PWM0_NS, + #[doc = "PWM0_S"] + pub PWM0_S: PWM0_S, + #[doc = "PWM1_NS"] + pub PWM1_NS: PWM1_NS, + #[doc = "PWM1_S"] + pub PWM1_S: PWM1_S, + #[doc = "PWM2_NS"] + pub PWM2_NS: PWM2_NS, + #[doc = "PWM2_S"] + pub PWM2_S: PWM2_S, + #[doc = "PWM3_NS"] + pub PWM3_NS: PWM3_NS, + #[doc = "PWM3_S"] + pub PWM3_S: PWM3_S, + #[doc = "PDM_NS"] + pub PDM_NS: PDM_NS, + #[doc = "PDM_S"] + pub PDM_S: PDM_S, + #[doc = "I2S_NS"] + pub I2S_NS: I2S_NS, + #[doc = "I2S_S"] + pub I2S_S: I2S_S, + #[doc = "IPC_NS"] + pub IPC_NS: IPC_NS, + #[doc = "IPC_S"] + pub IPC_S: IPC_S, + #[doc = "FPU_NS"] + pub FPU_NS: FPU_NS, + #[doc = "GPIOTE1_NS"] + pub GPIOTE1_NS: GPIOTE1_NS, + #[doc = "APPROTECT_NS"] + pub APPROTECT_NS: APPROTECT_NS, + #[doc = "KMU_NS"] + pub KMU_NS: KMU_NS, + #[doc = "NVMC_NS"] + pub NVMC_NS: NVMC_NS, + #[doc = "APPROTECT_S"] + pub APPROTECT_S: APPROTECT_S, + #[doc = "KMU_S"] + pub KMU_S: KMU_S, + #[doc = "NVMC_S"] + pub NVMC_S: NVMC_S, + #[doc = "VMC_NS"] + pub VMC_NS: VMC_NS, + #[doc = "VMC_S"] + pub VMC_S: VMC_S, + #[doc = "CC_HOST_RGF_S"] + pub CC_HOST_RGF_S: CC_HOST_RGF_S, + #[doc = "CRYPTOCELL_S"] + pub CRYPTOCELL_S: CRYPTOCELL_S, + #[doc = "P0_NS"] + pub P0_NS: P0_NS, + #[doc = "P0_S"] + pub P0_S: P0_S, +} +impl Peripherals { + #[doc = r"Returns all the peripherals *once*"] + #[inline] + pub fn take() -> Option { + cortex_m::interrupt::free(|_| { + if unsafe { DEVICE_PERIPHERALS } { + None + } else { + Some(unsafe { Peripherals::steal() }) + } + }) + } + #[doc = r"Unchecked version of `Peripherals::take`"] + #[inline] + pub unsafe fn steal() -> Self { + DEVICE_PERIPHERALS = true; + Peripherals { + FICR_S: FICR_S { + _marker: PhantomData, + }, + UICR_S: UICR_S { + _marker: PhantomData, + }, + TAD_S: TAD_S { + _marker: PhantomData, + }, + SPU_S: SPU_S { + _marker: PhantomData, + }, + REGULATORS_NS: REGULATORS_NS { + _marker: PhantomData, + }, + REGULATORS_S: REGULATORS_S { + _marker: PhantomData, + }, + CLOCK_NS: CLOCK_NS { + _marker: PhantomData, + }, + POWER_NS: POWER_NS { + _marker: PhantomData, + }, + CLOCK_S: CLOCK_S { + _marker: PhantomData, + }, + POWER_S: POWER_S { + _marker: PhantomData, + }, + CTRL_AP_PERI_S: CTRL_AP_PERI_S { + _marker: PhantomData, + }, + SPIM0_NS: SPIM0_NS { + _marker: PhantomData, + }, + SPIS0_NS: SPIS0_NS { + _marker: PhantomData, + }, + TWIM0_NS: TWIM0_NS { + _marker: PhantomData, + }, + TWIS0_NS: TWIS0_NS { + _marker: PhantomData, + }, + UARTE0_NS: UARTE0_NS { + _marker: PhantomData, + }, + SPIM0_S: SPIM0_S { + _marker: PhantomData, + }, + SPIS0_S: SPIS0_S { + _marker: PhantomData, + }, + TWIM0_S: TWIM0_S { + _marker: PhantomData, + }, + TWIS0_S: TWIS0_S { + _marker: PhantomData, + }, + UARTE0_S: UARTE0_S { + _marker: PhantomData, + }, + SPIM1_NS: SPIM1_NS { + _marker: PhantomData, + }, + SPIS1_NS: SPIS1_NS { + _marker: PhantomData, + }, + TWIM1_NS: TWIM1_NS { + _marker: PhantomData, + }, + TWIS1_NS: TWIS1_NS { + _marker: PhantomData, + }, + UARTE1_NS: UARTE1_NS { + _marker: PhantomData, + }, + SPIM1_S: SPIM1_S { + _marker: PhantomData, + }, + SPIS1_S: SPIS1_S { + _marker: PhantomData, + }, + TWIM1_S: TWIM1_S { + _marker: PhantomData, + }, + TWIS1_S: TWIS1_S { + _marker: PhantomData, + }, + UARTE1_S: UARTE1_S { + _marker: PhantomData, + }, + SPIM2_NS: SPIM2_NS { + _marker: PhantomData, + }, + SPIS2_NS: SPIS2_NS { + _marker: PhantomData, + }, + TWIM2_NS: TWIM2_NS { + _marker: PhantomData, + }, + TWIS2_NS: TWIS2_NS { + _marker: PhantomData, + }, + UARTE2_NS: UARTE2_NS { + _marker: PhantomData, + }, + SPIM2_S: SPIM2_S { + _marker: PhantomData, + }, + SPIS2_S: SPIS2_S { + _marker: PhantomData, + }, + TWIM2_S: TWIM2_S { + _marker: PhantomData, + }, + TWIS2_S: TWIS2_S { + _marker: PhantomData, + }, + UARTE2_S: UARTE2_S { + _marker: PhantomData, + }, + SPIM3_NS: SPIM3_NS { + _marker: PhantomData, + }, + SPIS3_NS: SPIS3_NS { + _marker: PhantomData, + }, + TWIM3_NS: TWIM3_NS { + _marker: PhantomData, + }, + TWIS3_NS: TWIS3_NS { + _marker: PhantomData, + }, + UARTE3_NS: UARTE3_NS { + _marker: PhantomData, + }, + SPIM3_S: SPIM3_S { + _marker: PhantomData, + }, + SPIS3_S: SPIS3_S { + _marker: PhantomData, + }, + TWIM3_S: TWIM3_S { + _marker: PhantomData, + }, + TWIS3_S: TWIS3_S { + _marker: PhantomData, + }, + UARTE3_S: UARTE3_S { + _marker: PhantomData, + }, + GPIOTE0_S: GPIOTE0_S { + _marker: PhantomData, + }, + SAADC_NS: SAADC_NS { + _marker: PhantomData, + }, + SAADC_S: SAADC_S { + _marker: PhantomData, + }, + TIMER0_NS: TIMER0_NS { + _marker: PhantomData, + }, + TIMER0_S: TIMER0_S { + _marker: PhantomData, + }, + TIMER1_NS: TIMER1_NS { + _marker: PhantomData, + }, + TIMER1_S: TIMER1_S { + _marker: PhantomData, + }, + TIMER2_NS: TIMER2_NS { + _marker: PhantomData, + }, + TIMER2_S: TIMER2_S { + _marker: PhantomData, + }, + RTC0_NS: RTC0_NS { + _marker: PhantomData, + }, + RTC0_S: RTC0_S { + _marker: PhantomData, + }, + RTC1_NS: RTC1_NS { + _marker: PhantomData, + }, + RTC1_S: RTC1_S { + _marker: PhantomData, + }, + DPPIC_NS: DPPIC_NS { + _marker: PhantomData, + }, + DPPIC_S: DPPIC_S { + _marker: PhantomData, + }, + WDT_NS: WDT_NS { + _marker: PhantomData, + }, + WDT_S: WDT_S { + _marker: PhantomData, + }, + EGU0_NS: EGU0_NS { + _marker: PhantomData, + }, + EGU0_S: EGU0_S { + _marker: PhantomData, + }, + EGU1_NS: EGU1_NS { + _marker: PhantomData, + }, + EGU1_S: EGU1_S { + _marker: PhantomData, + }, + EGU2_NS: EGU2_NS { + _marker: PhantomData, + }, + EGU2_S: EGU2_S { + _marker: PhantomData, + }, + EGU3_NS: EGU3_NS { + _marker: PhantomData, + }, + EGU3_S: EGU3_S { + _marker: PhantomData, + }, + EGU4_NS: EGU4_NS { + _marker: PhantomData, + }, + EGU4_S: EGU4_S { + _marker: PhantomData, + }, + EGU5_NS: EGU5_NS { + _marker: PhantomData, + }, + EGU5_S: EGU5_S { + _marker: PhantomData, + }, + PWM0_NS: PWM0_NS { + _marker: PhantomData, + }, + PWM0_S: PWM0_S { + _marker: PhantomData, + }, + PWM1_NS: PWM1_NS { + _marker: PhantomData, + }, + PWM1_S: PWM1_S { + _marker: PhantomData, + }, + PWM2_NS: PWM2_NS { + _marker: PhantomData, + }, + PWM2_S: PWM2_S { + _marker: PhantomData, + }, + PWM3_NS: PWM3_NS { + _marker: PhantomData, + }, + PWM3_S: PWM3_S { + _marker: PhantomData, + }, + PDM_NS: PDM_NS { + _marker: PhantomData, + }, + PDM_S: PDM_S { + _marker: PhantomData, + }, + I2S_NS: I2S_NS { + _marker: PhantomData, + }, + I2S_S: I2S_S { + _marker: PhantomData, + }, + IPC_NS: IPC_NS { + _marker: PhantomData, + }, + IPC_S: IPC_S { + _marker: PhantomData, + }, + FPU_NS: FPU_NS { + _marker: PhantomData, + }, + GPIOTE1_NS: GPIOTE1_NS { + _marker: PhantomData, + }, + APPROTECT_NS: APPROTECT_NS { + _marker: PhantomData, + }, + KMU_NS: KMU_NS { + _marker: PhantomData, + }, + NVMC_NS: NVMC_NS { + _marker: PhantomData, + }, + APPROTECT_S: APPROTECT_S { + _marker: PhantomData, + }, + KMU_S: KMU_S { + _marker: PhantomData, + }, + NVMC_S: NVMC_S { + _marker: PhantomData, + }, + VMC_NS: VMC_NS { + _marker: PhantomData, + }, + VMC_S: VMC_S { + _marker: PhantomData, + }, + CC_HOST_RGF_S: CC_HOST_RGF_S { + _marker: PhantomData, + }, + CRYPTOCELL_S: CRYPTOCELL_S { + _marker: PhantomData, + }, + P0_NS: P0_NS { + _marker: PhantomData, + }, + P0_S: P0_S { + _marker: PhantomData, + }, + } + } +} diff --git a/pacs/nrf9120-pac/src/nvmc_ns.rs b/pacs/nrf9120-pac/src/nvmc_ns.rs new file mode 100644 index 00000000..a4730aff --- /dev/null +++ b/pacs/nrf9120-pac/src/nvmc_ns.rs @@ -0,0 +1,72 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + _reserved0: [u8; 0x0400], + #[doc = "0x400 - Ready flag"] + pub ready: READY, + _reserved1: [u8; 0x04], + #[doc = "0x408 - Ready flag"] + pub readynext: READYNEXT, + _reserved2: [u8; 0xf8], + #[doc = "0x504 - Configuration register"] + pub config: CONFIG, + _reserved3: [u8; 0x04], + #[doc = "0x50c - Register for erasing all non-volatile user memory"] + pub eraseall: ERASEALL, + _reserved4: [u8; 0x0c], + #[doc = "0x51c - Register for partial erase configuration"] + pub erasepagepartialcfg: ERASEPAGEPARTIALCFG, + _reserved5: [u8; 0x20], + #[doc = "0x540 - I-code cache configuration register"] + pub icachecnf: ICACHECNF, + _reserved6: [u8; 0x04], + #[doc = "0x548 - I-code cache hit counter"] + pub ihit: IHIT, + #[doc = "0x54c - I-code cache miss counter"] + pub imiss: IMISS, + _reserved8: [u8; 0x34], + #[doc = "0x584 - Unspecified"] + pub configns: CONFIGNS, + #[doc = "0x588 - Non-secure APPROTECT enable register"] + pub writeuicrns: WRITEUICRNS, +} +#[doc = "READY (r) register accessor: an alias for `Reg`"] +pub type READY = crate::Reg; +#[doc = "Ready flag"] +pub mod ready; +#[doc = "READYNEXT (r) register accessor: an alias for `Reg`"] +pub type READYNEXT = crate::Reg; +#[doc = "Ready flag"] +pub mod readynext; +#[doc = "CONFIG (rw) register accessor: an alias for `Reg`"] +pub type CONFIG = crate::Reg; +#[doc = "Configuration register"] +pub mod config; +#[doc = "ERASEALL (w) register accessor: an alias for `Reg`"] +pub type ERASEALL = crate::Reg; +#[doc = "Register for erasing all non-volatile user memory"] +pub mod eraseall; +#[doc = "ERASEPAGEPARTIALCFG (rw) register accessor: an alias for `Reg`"] +pub type ERASEPAGEPARTIALCFG = crate::Reg; +#[doc = "Register for partial erase configuration"] +pub mod erasepagepartialcfg; +#[doc = "ICACHECNF (rw) register accessor: an alias for `Reg`"] +pub type ICACHECNF = crate::Reg; +#[doc = "I-code cache configuration register"] +pub mod icachecnf; +#[doc = "IHIT (rw) register accessor: an alias for `Reg`"] +pub type IHIT = crate::Reg; +#[doc = "I-code cache hit counter"] +pub mod ihit; +#[doc = "IMISS (rw) register accessor: an alias for `Reg`"] +pub type IMISS = crate::Reg; +#[doc = "I-code cache miss counter"] +pub mod imiss; +#[doc = "CONFIGNS (rw) register accessor: an alias for `Reg`"] +pub type CONFIGNS = crate::Reg; +#[doc = "Unspecified"] +pub mod configns; +#[doc = "WRITEUICRNS (w) register accessor: an alias for `Reg`"] +pub type WRITEUICRNS = crate::Reg; +#[doc = "Non-secure APPROTECT enable register"] +pub mod writeuicrns; diff --git a/pacs/nrf9120-pac/src/nvmc_ns/config.rs b/pacs/nrf9120-pac/src/nvmc_ns/config.rs new file mode 100644 index 00000000..a5dcf543 --- /dev/null +++ b/pacs/nrf9120-pac/src/nvmc_ns/config.rs @@ -0,0 +1,154 @@ +#[doc = "Register `CONFIG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CONFIG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `WEN` reader - Program memory access mode. It is strongly recommended to only activate erase and write modes when they are actively used. Enabling write or erase will invalidate the cache and keep it invalidated."] +pub type WEN_R = crate::FieldReader; +#[doc = "Program memory access mode. It is strongly recommended to only activate erase and write modes when they are actively used. Enabling write or erase will invalidate the cache and keep it invalidated.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum WEN_A { + #[doc = "0: Read only access"] + REN = 0, + #[doc = "1: Write enabled"] + WEN = 1, + #[doc = "2: Erase enabled"] + EEN = 2, + #[doc = "4: Partial erase enabled"] + PEEN = 4, +} +impl From for u8 { + #[inline(always)] + fn from(variant: WEN_A) -> Self { + variant as _ + } +} +impl WEN_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(WEN_A::REN), + 1 => Some(WEN_A::WEN), + 2 => Some(WEN_A::EEN), + 4 => Some(WEN_A::PEEN), + _ => None, + } + } + #[doc = "Checks if the value of the field is `REN`"] + #[inline(always)] + pub fn is_ren(&self) -> bool { + *self == WEN_A::REN + } + #[doc = "Checks if the value of the field is `WEN`"] + #[inline(always)] + pub fn is_wen(&self) -> bool { + *self == WEN_A::WEN + } + #[doc = "Checks if the value of the field is `EEN`"] + #[inline(always)] + pub fn is_een(&self) -> bool { + *self == WEN_A::EEN + } + #[doc = "Checks if the value of the field is `PEEN`"] + #[inline(always)] + pub fn is_peen(&self) -> bool { + *self == WEN_A::PEEN + } +} +#[doc = "Field `WEN` writer - Program memory access mode. It is strongly recommended to only activate erase and write modes when they are actively used. Enabling write or erase will invalidate the cache and keep it invalidated."] +pub type WEN_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CONFIG_SPEC, u8, WEN_A, 3, O>; +impl<'a, const O: u8> WEN_W<'a, O> { + #[doc = "Read only access"] + #[inline(always)] + pub fn ren(self) -> &'a mut W { + self.variant(WEN_A::REN) + } + #[doc = "Write enabled"] + #[inline(always)] + pub fn wen(self) -> &'a mut W { + self.variant(WEN_A::WEN) + } + #[doc = "Erase enabled"] + #[inline(always)] + pub fn een(self) -> &'a mut W { + self.variant(WEN_A::EEN) + } + #[doc = "Partial erase enabled"] + #[inline(always)] + pub fn peen(self) -> &'a mut W { + self.variant(WEN_A::PEEN) + } +} +impl R { + #[doc = "Bits 0:2 - Program memory access mode. It is strongly recommended to only activate erase and write modes when they are actively used. Enabling write or erase will invalidate the cache and keep it invalidated."] + #[inline(always)] + pub fn wen(&self) -> WEN_R { + WEN_R::new((self.bits & 7) as u8) + } +} +impl W { + #[doc = "Bits 0:2 - Program memory access mode. It is strongly recommended to only activate erase and write modes when they are actively used. Enabling write or erase will invalidate the cache and keep it invalidated."] + #[inline(always)] + pub fn wen(&mut self) -> WEN_W<0> { + WEN_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Configuration register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [config](index.html) module"] +pub struct CONFIG_SPEC; +impl crate::RegisterSpec for CONFIG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [config::R](R) reader structure"] +impl crate::Readable for CONFIG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [config::W](W) writer structure"] +impl crate::Writable for CONFIG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CONFIG to value 0"] +impl crate::Resettable for CONFIG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/nvmc_ns/configns.rs b/pacs/nrf9120-pac/src/nvmc_ns/configns.rs new file mode 100644 index 00000000..38148f5e --- /dev/null +++ b/pacs/nrf9120-pac/src/nvmc_ns/configns.rs @@ -0,0 +1,141 @@ +#[doc = "Register `CONFIGNS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CONFIGNS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `WEN` reader - Program memory access mode. It is strongly recommended to only activate erase and write modes when they are actively used. Enabling write or erase will invalidate the cache and keep it invalidated."] +pub type WEN_R = crate::FieldReader; +#[doc = "Program memory access mode. It is strongly recommended to only activate erase and write modes when they are actively used. Enabling write or erase will invalidate the cache and keep it invalidated.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum WEN_A { + #[doc = "0: Read only access"] + REN = 0, + #[doc = "1: Write enabled"] + WEN = 1, + #[doc = "2: Erase enabled"] + EEN = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: WEN_A) -> Self { + variant as _ + } +} +impl WEN_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(WEN_A::REN), + 1 => Some(WEN_A::WEN), + 2 => Some(WEN_A::EEN), + _ => None, + } + } + #[doc = "Checks if the value of the field is `REN`"] + #[inline(always)] + pub fn is_ren(&self) -> bool { + *self == WEN_A::REN + } + #[doc = "Checks if the value of the field is `WEN`"] + #[inline(always)] + pub fn is_wen(&self) -> bool { + *self == WEN_A::WEN + } + #[doc = "Checks if the value of the field is `EEN`"] + #[inline(always)] + pub fn is_een(&self) -> bool { + *self == WEN_A::EEN + } +} +#[doc = "Field `WEN` writer - Program memory access mode. It is strongly recommended to only activate erase and write modes when they are actively used. Enabling write or erase will invalidate the cache and keep it invalidated."] +pub type WEN_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CONFIGNS_SPEC, u8, WEN_A, 2, O>; +impl<'a, const O: u8> WEN_W<'a, O> { + #[doc = "Read only access"] + #[inline(always)] + pub fn ren(self) -> &'a mut W { + self.variant(WEN_A::REN) + } + #[doc = "Write enabled"] + #[inline(always)] + pub fn wen(self) -> &'a mut W { + self.variant(WEN_A::WEN) + } + #[doc = "Erase enabled"] + #[inline(always)] + pub fn een(self) -> &'a mut W { + self.variant(WEN_A::EEN) + } +} +impl R { + #[doc = "Bits 0:1 - Program memory access mode. It is strongly recommended to only activate erase and write modes when they are actively used. Enabling write or erase will invalidate the cache and keep it invalidated."] + #[inline(always)] + pub fn wen(&self) -> WEN_R { + WEN_R::new((self.bits & 3) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Program memory access mode. It is strongly recommended to only activate erase and write modes when they are actively used. Enabling write or erase will invalidate the cache and keep it invalidated."] + #[inline(always)] + pub fn wen(&mut self) -> WEN_W<0> { + WEN_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Unspecified\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [configns](index.html) module"] +pub struct CONFIGNS_SPEC; +impl crate::RegisterSpec for CONFIGNS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [configns::R](R) reader structure"] +impl crate::Readable for CONFIGNS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [configns::W](W) writer structure"] +impl crate::Writable for CONFIGNS_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CONFIGNS to value 0"] +impl crate::Resettable for CONFIGNS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/nvmc_ns/eraseall.rs b/pacs/nrf9120-pac/src/nvmc_ns/eraseall.rs new file mode 100644 index 00000000..42430da1 --- /dev/null +++ b/pacs/nrf9120-pac/src/nvmc_ns/eraseall.rs @@ -0,0 +1,78 @@ +#[doc = "Register `ERASEALL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Erase all non-volatile memory including UICR registers. Note that erasing must be enabled by setting CONFIG.WEN = Een before the non-volatile memory can be erased.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum ERASEALL_AW { + #[doc = "0: No operation"] + NO_OPERATION = 0, + #[doc = "1: Start chip erase"] + ERASE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: ERASEALL_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ERASEALL` writer - Erase all non-volatile memory including UICR registers. Note that erasing must be enabled by setting CONFIG.WEN = Een before the non-volatile memory can be erased."] +pub type ERASEALL_W<'a, const O: u8> = crate::BitWriter<'a, u32, ERASEALL_SPEC, ERASEALL_AW, O>; +impl<'a, const O: u8> ERASEALL_W<'a, O> { + #[doc = "No operation"] + #[inline(always)] + pub fn no_operation(self) -> &'a mut W { + self.variant(ERASEALL_AW::NO_OPERATION) + } + #[doc = "Start chip erase"] + #[inline(always)] + pub fn erase(self) -> &'a mut W { + self.variant(ERASEALL_AW::ERASE) + } +} +impl W { + #[doc = "Bit 0 - Erase all non-volatile memory including UICR registers. Note that erasing must be enabled by setting CONFIG.WEN = Een before the non-volatile memory can be erased."] + #[inline(always)] + pub fn eraseall(&mut self) -> ERASEALL_W<0> { + ERASEALL_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Register for erasing all non-volatile user memory\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [eraseall](index.html) module"] +pub struct ERASEALL_SPEC; +impl crate::RegisterSpec for ERASEALL_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [eraseall::W](W) writer structure"] +impl crate::Writable for ERASEALL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets ERASEALL to value 0"] +impl crate::Resettable for ERASEALL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/nvmc_ns/erasepagepartialcfg.rs b/pacs/nrf9120-pac/src/nvmc_ns/erasepagepartialcfg.rs new file mode 100644 index 00000000..825d2ddc --- /dev/null +++ b/pacs/nrf9120-pac/src/nvmc_ns/erasepagepartialcfg.rs @@ -0,0 +1,81 @@ +#[doc = "Register `ERASEPAGEPARTIALCFG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `ERASEPAGEPARTIALCFG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DURATION` reader - Duration of the partial erase in milliseconds"] +pub type DURATION_R = crate::FieldReader; +#[doc = "Field `DURATION` writer - Duration of the partial erase in milliseconds"] +pub type DURATION_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, ERASEPAGEPARTIALCFG_SPEC, u8, u8, 7, O>; +impl R { + #[doc = "Bits 0:6 - Duration of the partial erase in milliseconds"] + #[inline(always)] + pub fn duration(&self) -> DURATION_R { + DURATION_R::new((self.bits & 0x7f) as u8) + } +} +impl W { + #[doc = "Bits 0:6 - Duration of the partial erase in milliseconds"] + #[inline(always)] + pub fn duration(&mut self) -> DURATION_W<0> { + DURATION_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Register for partial erase configuration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [erasepagepartialcfg](index.html) module"] +pub struct ERASEPAGEPARTIALCFG_SPEC; +impl crate::RegisterSpec for ERASEPAGEPARTIALCFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [erasepagepartialcfg::R](R) reader structure"] +impl crate::Readable for ERASEPAGEPARTIALCFG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [erasepagepartialcfg::W](W) writer structure"] +impl crate::Writable for ERASEPAGEPARTIALCFG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets ERASEPAGEPARTIALCFG to value 0x0a"] +impl crate::Resettable for ERASEPAGEPARTIALCFG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x0a + } +} diff --git a/pacs/nrf9120-pac/src/nvmc_ns/icachecnf.rs b/pacs/nrf9120-pac/src/nvmc_ns/icachecnf.rs new file mode 100644 index 00000000..bf5763ea --- /dev/null +++ b/pacs/nrf9120-pac/src/nvmc_ns/icachecnf.rs @@ -0,0 +1,187 @@ +#[doc = "Register `ICACHECNF` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `ICACHECNF` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CACHEEN` reader - Cache enable"] +pub type CACHEEN_R = crate::BitReader; +#[doc = "Cache enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CACHEEN_A { + #[doc = "0: Disable cache. Invalidates all cache entries."] + DISABLED = 0, + #[doc = "1: Enable cache"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CACHEEN_A) -> Self { + variant as u8 != 0 + } +} +impl CACHEEN_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CACHEEN_A { + match self.bits { + false => CACHEEN_A::DISABLED, + true => CACHEEN_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == CACHEEN_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == CACHEEN_A::ENABLED + } +} +#[doc = "Field `CACHEEN` writer - Cache enable"] +pub type CACHEEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, ICACHECNF_SPEC, CACHEEN_A, O>; +impl<'a, const O: u8> CACHEEN_W<'a, O> { + #[doc = "Disable cache. Invalidates all cache entries."] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(CACHEEN_A::DISABLED) + } + #[doc = "Enable cache"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(CACHEEN_A::ENABLED) + } +} +#[doc = "Field `CACHEPROFEN` reader - Cache profiling enable"] +pub type CACHEPROFEN_R = crate::BitReader; +#[doc = "Cache profiling enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CACHEPROFEN_A { + #[doc = "0: Disable cache profiling"] + DISABLED = 0, + #[doc = "1: Enable cache profiling"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CACHEPROFEN_A) -> Self { + variant as u8 != 0 + } +} +impl CACHEPROFEN_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CACHEPROFEN_A { + match self.bits { + false => CACHEPROFEN_A::DISABLED, + true => CACHEPROFEN_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == CACHEPROFEN_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == CACHEPROFEN_A::ENABLED + } +} +#[doc = "Field `CACHEPROFEN` writer - Cache profiling enable"] +pub type CACHEPROFEN_W<'a, const O: u8> = + crate::BitWriter<'a, u32, ICACHECNF_SPEC, CACHEPROFEN_A, O>; +impl<'a, const O: u8> CACHEPROFEN_W<'a, O> { + #[doc = "Disable cache profiling"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(CACHEPROFEN_A::DISABLED) + } + #[doc = "Enable cache profiling"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(CACHEPROFEN_A::ENABLED) + } +} +impl R { + #[doc = "Bit 0 - Cache enable"] + #[inline(always)] + pub fn cacheen(&self) -> CACHEEN_R { + CACHEEN_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 8 - Cache profiling enable"] + #[inline(always)] + pub fn cacheprofen(&self) -> CACHEPROFEN_R { + CACHEPROFEN_R::new(((self.bits >> 8) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Cache enable"] + #[inline(always)] + pub fn cacheen(&mut self) -> CACHEEN_W<0> { + CACHEEN_W::new(self) + } + #[doc = "Bit 8 - Cache profiling enable"] + #[inline(always)] + pub fn cacheprofen(&mut self) -> CACHEPROFEN_W<8> { + CACHEPROFEN_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "I-code cache configuration register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [icachecnf](index.html) module"] +pub struct ICACHECNF_SPEC; +impl crate::RegisterSpec for ICACHECNF_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [icachecnf::R](R) reader structure"] +impl crate::Readable for ICACHECNF_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [icachecnf::W](W) writer structure"] +impl crate::Writable for ICACHECNF_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets ICACHECNF to value 0"] +impl crate::Resettable for ICACHECNF_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/nvmc_ns/ihit.rs b/pacs/nrf9120-pac/src/nvmc_ns/ihit.rs new file mode 100644 index 00000000..9d655155 --- /dev/null +++ b/pacs/nrf9120-pac/src/nvmc_ns/ihit.rs @@ -0,0 +1,80 @@ +#[doc = "Register `IHIT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `IHIT` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `HITS` reader - Number of cache hits Write zero to clear"] +pub type HITS_R = crate::FieldReader; +#[doc = "Field `HITS` writer - Number of cache hits Write zero to clear"] +pub type HITS_W<'a, const O: u8> = crate::FieldWriter<'a, u32, IHIT_SPEC, u32, u32, 32, O>; +impl R { + #[doc = "Bits 0:31 - Number of cache hits Write zero to clear"] + #[inline(always)] + pub fn hits(&self) -> HITS_R { + HITS_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Number of cache hits Write zero to clear"] + #[inline(always)] + pub fn hits(&mut self) -> HITS_W<0> { + HITS_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "I-code cache hit counter\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ihit](index.html) module"] +pub struct IHIT_SPEC; +impl crate::RegisterSpec for IHIT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ihit::R](R) reader structure"] +impl crate::Readable for IHIT_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ihit::W](W) writer structure"] +impl crate::Writable for IHIT_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets IHIT to value 0"] +impl crate::Resettable for IHIT_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/nvmc_ns/imiss.rs b/pacs/nrf9120-pac/src/nvmc_ns/imiss.rs new file mode 100644 index 00000000..4bf4ccb2 --- /dev/null +++ b/pacs/nrf9120-pac/src/nvmc_ns/imiss.rs @@ -0,0 +1,80 @@ +#[doc = "Register `IMISS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `IMISS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `MISSES` reader - Number of cache misses Write zero to clear"] +pub type MISSES_R = crate::FieldReader; +#[doc = "Field `MISSES` writer - Number of cache misses Write zero to clear"] +pub type MISSES_W<'a, const O: u8> = crate::FieldWriter<'a, u32, IMISS_SPEC, u32, u32, 32, O>; +impl R { + #[doc = "Bits 0:31 - Number of cache misses Write zero to clear"] + #[inline(always)] + pub fn misses(&self) -> MISSES_R { + MISSES_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Number of cache misses Write zero to clear"] + #[inline(always)] + pub fn misses(&mut self) -> MISSES_W<0> { + MISSES_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "I-code cache miss counter\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [imiss](index.html) module"] +pub struct IMISS_SPEC; +impl crate::RegisterSpec for IMISS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [imiss::R](R) reader structure"] +impl crate::Readable for IMISS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [imiss::W](W) writer structure"] +impl crate::Writable for IMISS_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets IMISS to value 0"] +impl crate::Resettable for IMISS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/nvmc_ns/ready.rs b/pacs/nrf9120-pac/src/nvmc_ns/ready.rs new file mode 100644 index 00000000..a1c16794 --- /dev/null +++ b/pacs/nrf9120-pac/src/nvmc_ns/ready.rs @@ -0,0 +1,74 @@ +#[doc = "Register `READY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `READY` reader - NVMC is ready or busy"] +pub type READY_R = crate::BitReader; +#[doc = "NVMC is ready or busy\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum READY_A { + #[doc = "0: NVMC is busy (on-going write or erase operation)"] + BUSY = 0, + #[doc = "1: NVMC is ready"] + READY = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: READY_A) -> Self { + variant as u8 != 0 + } +} +impl READY_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> READY_A { + match self.bits { + false => READY_A::BUSY, + true => READY_A::READY, + } + } + #[doc = "Checks if the value of the field is `BUSY`"] + #[inline(always)] + pub fn is_busy(&self) -> bool { + *self == READY_A::BUSY + } + #[doc = "Checks if the value of the field is `READY`"] + #[inline(always)] + pub fn is_ready(&self) -> bool { + *self == READY_A::READY + } +} +impl R { + #[doc = "Bit 0 - NVMC is ready or busy"] + #[inline(always)] + pub fn ready(&self) -> READY_R { + READY_R::new((self.bits & 1) != 0) + } +} +#[doc = "Ready flag\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ready](index.html) module"] +pub struct READY_SPEC; +impl crate::RegisterSpec for READY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ready::R](R) reader structure"] +impl crate::Readable for READY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets READY to value 0x01"] +impl crate::Resettable for READY_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x01 + } +} diff --git a/pacs/nrf9120-pac/src/nvmc_ns/readynext.rs b/pacs/nrf9120-pac/src/nvmc_ns/readynext.rs new file mode 100644 index 00000000..9d5d48f2 --- /dev/null +++ b/pacs/nrf9120-pac/src/nvmc_ns/readynext.rs @@ -0,0 +1,74 @@ +#[doc = "Register `READYNEXT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `READYNEXT` reader - NVMC can accept a new write operation"] +pub type READYNEXT_R = crate::BitReader; +#[doc = "NVMC can accept a new write operation\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum READYNEXT_A { + #[doc = "0: NVMC cannot accept any write operation"] + BUSY = 0, + #[doc = "1: NVMC is ready"] + READY = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: READYNEXT_A) -> Self { + variant as u8 != 0 + } +} +impl READYNEXT_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> READYNEXT_A { + match self.bits { + false => READYNEXT_A::BUSY, + true => READYNEXT_A::READY, + } + } + #[doc = "Checks if the value of the field is `BUSY`"] + #[inline(always)] + pub fn is_busy(&self) -> bool { + *self == READYNEXT_A::BUSY + } + #[doc = "Checks if the value of the field is `READY`"] + #[inline(always)] + pub fn is_ready(&self) -> bool { + *self == READYNEXT_A::READY + } +} +impl R { + #[doc = "Bit 0 - NVMC can accept a new write operation"] + #[inline(always)] + pub fn readynext(&self) -> READYNEXT_R { + READYNEXT_R::new((self.bits & 1) != 0) + } +} +#[doc = "Ready flag\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [readynext](index.html) module"] +pub struct READYNEXT_SPEC; +impl crate::RegisterSpec for READYNEXT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [readynext::R](R) reader structure"] +impl crate::Readable for READYNEXT_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets READYNEXT to value 0x01"] +impl crate::Resettable for READYNEXT_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x01 + } +} diff --git a/pacs/nrf9120-pac/src/nvmc_ns/writeuicrns.rs b/pacs/nrf9120-pac/src/nvmc_ns/writeuicrns.rs new file mode 100644 index 00000000..e9b84509 --- /dev/null +++ b/pacs/nrf9120-pac/src/nvmc_ns/writeuicrns.rs @@ -0,0 +1,98 @@ +#[doc = "Register `WRITEUICRNS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Allow non-secure code to set APPROTECT\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum SET_AW { + #[doc = "1: Set value"] + SET = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: SET_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SET` writer - Allow non-secure code to set APPROTECT"] +pub type SET_W<'a, const O: u8> = crate::BitWriter<'a, u32, WRITEUICRNS_SPEC, SET_AW, O>; +impl<'a, const O: u8> SET_W<'a, O> { + #[doc = "Set value"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(SET_AW::SET) + } +} +#[doc = "Key to write in order to validate the write operation\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u32)] +pub enum KEY_AW { + #[doc = "184280487: Key value"] + KEYVALID = 184280487, +} +impl From for u32 { + #[inline(always)] + fn from(variant: KEY_AW) -> Self { + variant as _ + } +} +#[doc = "Field `KEY` writer - Key to write in order to validate the write operation"] +pub type KEY_W<'a, const O: u8> = crate::FieldWriter<'a, u32, WRITEUICRNS_SPEC, u32, KEY_AW, 28, O>; +impl<'a, const O: u8> KEY_W<'a, O> { + #[doc = "Key value"] + #[inline(always)] + pub fn keyvalid(self) -> &'a mut W { + self.variant(KEY_AW::KEYVALID) + } +} +impl W { + #[doc = "Bit 0 - Allow non-secure code to set APPROTECT"] + #[inline(always)] + pub fn set(&mut self) -> SET_W<0> { + SET_W::new(self) + } + #[doc = "Bits 4:31 - Key to write in order to validate the write operation"] + #[inline(always)] + pub fn key(&mut self) -> KEY_W<4> { + KEY_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Non-secure APPROTECT enable register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [writeuicrns](index.html) module"] +pub struct WRITEUICRNS_SPEC; +impl crate::RegisterSpec for WRITEUICRNS_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [writeuicrns::W](W) writer structure"] +impl crate::Writable for WRITEUICRNS_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets WRITEUICRNS to value 0"] +impl crate::Resettable for WRITEUICRNS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/p0_ns.rs b/pacs/nrf9120-pac/src/p0_ns.rs new file mode 100644 index 00000000..5235db42 --- /dev/null +++ b/pacs/nrf9120-pac/src/p0_ns.rs @@ -0,0 +1,72 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + _reserved0: [u8; 0x04], + #[doc = "0x04 - Write GPIO port"] + pub out: OUT, + #[doc = "0x08 - Set individual bits in GPIO port"] + pub outset: OUTSET, + #[doc = "0x0c - Clear individual bits in GPIO port"] + pub outclr: OUTCLR, + #[doc = "0x10 - Read GPIO port"] + pub in_: IN, + #[doc = "0x14 - Direction of GPIO pins"] + pub dir: DIR, + #[doc = "0x18 - DIR set register"] + pub dirset: DIRSET, + #[doc = "0x1c - DIR clear register"] + pub dirclr: DIRCLR, + #[doc = "0x20 - Latch register indicating what GPIO pins that have met the criteria set in the PIN_CNF\\[n\\].SENSE registers"] + pub latch: LATCH, + #[doc = "0x24 - Select between default DETECT signal behavior and LDETECT mode (For non-secure pin only)"] + pub detectmode: DETECTMODE, + #[doc = "0x28 - Select between default DETECT signal behavior and LDETECT mode (For secure pin only)"] + pub detectmode_sec: DETECTMODE_SEC, + _reserved10: [u8; 0x01d4], + #[doc = "0x200..0x280 - Description collection: Configuration of GPIO pins"] + pub pin_cnf: [PIN_CNF; 32], +} +#[doc = "OUT (rw) register accessor: an alias for `Reg`"] +pub type OUT = crate::Reg; +#[doc = "Write GPIO port"] +pub mod out; +#[doc = "OUTSET (rw) register accessor: an alias for `Reg`"] +pub type OUTSET = crate::Reg; +#[doc = "Set individual bits in GPIO port"] +pub mod outset; +#[doc = "OUTCLR (rw) register accessor: an alias for `Reg`"] +pub type OUTCLR = crate::Reg; +#[doc = "Clear individual bits in GPIO port"] +pub mod outclr; +#[doc = "IN (r) register accessor: an alias for `Reg`"] +pub type IN = crate::Reg; +#[doc = "Read GPIO port"] +pub mod in_; +#[doc = "DIR (rw) register accessor: an alias for `Reg`"] +pub type DIR = crate::Reg; +#[doc = "Direction of GPIO pins"] +pub mod dir; +#[doc = "DIRSET (rw) register accessor: an alias for `Reg`"] +pub type DIRSET = crate::Reg; +#[doc = "DIR set register"] +pub mod dirset; +#[doc = "DIRCLR (rw) register accessor: an alias for `Reg`"] +pub type DIRCLR = crate::Reg; +#[doc = "DIR clear register"] +pub mod dirclr; +#[doc = "LATCH (rw) register accessor: an alias for `Reg`"] +pub type LATCH = crate::Reg; +#[doc = "Latch register indicating what GPIO pins that have met the criteria set in the PIN_CNF\\[n\\].SENSE registers"] +pub mod latch; +#[doc = "DETECTMODE (rw) register accessor: an alias for `Reg`"] +pub type DETECTMODE = crate::Reg; +#[doc = "Select between default DETECT signal behavior and LDETECT mode (For non-secure pin only)"] +pub mod detectmode; +#[doc = "DETECTMODE_SEC (rw) register accessor: an alias for `Reg`"] +pub type DETECTMODE_SEC = crate::Reg; +#[doc = "Select between default DETECT signal behavior and LDETECT mode (For secure pin only)"] +pub mod detectmode_sec; +#[doc = "PIN_CNF (rw) register accessor: an alias for `Reg`"] +pub type PIN_CNF = crate::Reg; +#[doc = "Description collection: Configuration of GPIO pins"] +pub mod pin_cnf; diff --git a/pacs/nrf9120-pac/src/p0_ns/detectmode.rs b/pacs/nrf9120-pac/src/p0_ns/detectmode.rs new file mode 100644 index 00000000..d469e83b --- /dev/null +++ b/pacs/nrf9120-pac/src/p0_ns/detectmode.rs @@ -0,0 +1,127 @@ +#[doc = "Register `DETECTMODE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DETECTMODE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DETECTMODE` reader - Select between default DETECT signal behavior and LDETECT mode"] +pub type DETECTMODE_R = crate::BitReader; +#[doc = "Select between default DETECT signal behavior and LDETECT mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum DETECTMODE_A { + #[doc = "0: DETECT directly connected to PIN DETECT signals"] + DEFAULT = 0, + #[doc = "1: Use the latched LDETECT behavior"] + LDETECT = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: DETECTMODE_A) -> Self { + variant as u8 != 0 + } +} +impl DETECTMODE_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> DETECTMODE_A { + match self.bits { + false => DETECTMODE_A::DEFAULT, + true => DETECTMODE_A::LDETECT, + } + } + #[doc = "Checks if the value of the field is `DEFAULT`"] + #[inline(always)] + pub fn is_default(&self) -> bool { + *self == DETECTMODE_A::DEFAULT + } + #[doc = "Checks if the value of the field is `LDETECT`"] + #[inline(always)] + pub fn is_ldetect(&self) -> bool { + *self == DETECTMODE_A::LDETECT + } +} +#[doc = "Field `DETECTMODE` writer - Select between default DETECT signal behavior and LDETECT mode"] +pub type DETECTMODE_W<'a, const O: u8> = + crate::BitWriter<'a, u32, DETECTMODE_SPEC, DETECTMODE_A, O>; +impl<'a, const O: u8> DETECTMODE_W<'a, O> { + #[doc = "DETECT directly connected to PIN DETECT signals"] + #[inline(always)] + pub fn default(self) -> &'a mut W { + self.variant(DETECTMODE_A::DEFAULT) + } + #[doc = "Use the latched LDETECT behavior"] + #[inline(always)] + pub fn ldetect(self) -> &'a mut W { + self.variant(DETECTMODE_A::LDETECT) + } +} +impl R { + #[doc = "Bit 0 - Select between default DETECT signal behavior and LDETECT mode"] + #[inline(always)] + pub fn detectmode(&self) -> DETECTMODE_R { + DETECTMODE_R::new((self.bits & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Select between default DETECT signal behavior and LDETECT mode"] + #[inline(always)] + pub fn detectmode(&mut self) -> DETECTMODE_W<0> { + DETECTMODE_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Select between default DETECT signal behavior and LDETECT mode (For non-secure pin only)\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [detectmode](index.html) module"] +pub struct DETECTMODE_SPEC; +impl crate::RegisterSpec for DETECTMODE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [detectmode::R](R) reader structure"] +impl crate::Readable for DETECTMODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [detectmode::W](W) writer structure"] +impl crate::Writable for DETECTMODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DETECTMODE to value 0"] +impl crate::Resettable for DETECTMODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/p0_ns/detectmode_sec.rs b/pacs/nrf9120-pac/src/p0_ns/detectmode_sec.rs new file mode 100644 index 00000000..930689ae --- /dev/null +++ b/pacs/nrf9120-pac/src/p0_ns/detectmode_sec.rs @@ -0,0 +1,127 @@ +#[doc = "Register `DETECTMODE_SEC` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DETECTMODE_SEC` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DETECTMODE` reader - Select between default DETECT signal behavior and LDETECT mode"] +pub type DETECTMODE_R = crate::BitReader; +#[doc = "Select between default DETECT signal behavior and LDETECT mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum DETECTMODE_A { + #[doc = "0: DETECT directly connected to PIN DETECT signals"] + DEFAULT = 0, + #[doc = "1: Use the latched LDETECT behavior"] + LDETECT = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: DETECTMODE_A) -> Self { + variant as u8 != 0 + } +} +impl DETECTMODE_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> DETECTMODE_A { + match self.bits { + false => DETECTMODE_A::DEFAULT, + true => DETECTMODE_A::LDETECT, + } + } + #[doc = "Checks if the value of the field is `DEFAULT`"] + #[inline(always)] + pub fn is_default(&self) -> bool { + *self == DETECTMODE_A::DEFAULT + } + #[doc = "Checks if the value of the field is `LDETECT`"] + #[inline(always)] + pub fn is_ldetect(&self) -> bool { + *self == DETECTMODE_A::LDETECT + } +} +#[doc = "Field `DETECTMODE` writer - Select between default DETECT signal behavior and LDETECT mode"] +pub type DETECTMODE_W<'a, const O: u8> = + crate::BitWriter<'a, u32, DETECTMODE_SEC_SPEC, DETECTMODE_A, O>; +impl<'a, const O: u8> DETECTMODE_W<'a, O> { + #[doc = "DETECT directly connected to PIN DETECT signals"] + #[inline(always)] + pub fn default(self) -> &'a mut W { + self.variant(DETECTMODE_A::DEFAULT) + } + #[doc = "Use the latched LDETECT behavior"] + #[inline(always)] + pub fn ldetect(self) -> &'a mut W { + self.variant(DETECTMODE_A::LDETECT) + } +} +impl R { + #[doc = "Bit 0 - Select between default DETECT signal behavior and LDETECT mode"] + #[inline(always)] + pub fn detectmode(&self) -> DETECTMODE_R { + DETECTMODE_R::new((self.bits & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Select between default DETECT signal behavior and LDETECT mode"] + #[inline(always)] + pub fn detectmode(&mut self) -> DETECTMODE_W<0> { + DETECTMODE_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Select between default DETECT signal behavior and LDETECT mode (For secure pin only)\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [detectmode_sec](index.html) module"] +pub struct DETECTMODE_SEC_SPEC; +impl crate::RegisterSpec for DETECTMODE_SEC_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [detectmode_sec::R](R) reader structure"] +impl crate::Readable for DETECTMODE_SEC_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [detectmode_sec::W](W) writer structure"] +impl crate::Writable for DETECTMODE_SEC_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DETECTMODE_SEC to value 0"] +impl crate::Resettable for DETECTMODE_SEC_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/p0_ns/dir.rs b/pacs/nrf9120-pac/src/p0_ns/dir.rs new file mode 100644 index 00000000..1efb6d02 --- /dev/null +++ b/pacs/nrf9120-pac/src/p0_ns/dir.rs @@ -0,0 +1,1986 @@ +#[doc = "Register `DIR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DIR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PIN0` reader - Pin 0"] +pub type PIN0_R = crate::BitReader; +#[doc = "Pin 0\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN0_A { + #[doc = "0: Pin set as input"] + INPUT = 0, + #[doc = "1: Pin set as output"] + OUTPUT = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN0_A) -> Self { + variant as u8 != 0 + } +} +impl PIN0_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN0_A { + match self.bits { + false => PIN0_A::INPUT, + true => PIN0_A::OUTPUT, + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == PIN0_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == PIN0_A::OUTPUT + } +} +#[doc = "Field `PIN0` writer - Pin 0"] +pub type PIN0_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIR_SPEC, PIN0_A, O>; +impl<'a, const O: u8> PIN0_W<'a, O> { + #[doc = "Pin set as input"] + #[inline(always)] + pub fn input(self) -> &'a mut W { + self.variant(PIN0_A::INPUT) + } + #[doc = "Pin set as output"] + #[inline(always)] + pub fn output(self) -> &'a mut W { + self.variant(PIN0_A::OUTPUT) + } +} +#[doc = "Field `PIN1` reader - Pin 1"] +pub type PIN1_R = crate::BitReader; +#[doc = "Pin 1\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN1_A { + #[doc = "0: Pin set as input"] + INPUT = 0, + #[doc = "1: Pin set as output"] + OUTPUT = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN1_A) -> Self { + variant as u8 != 0 + } +} +impl PIN1_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN1_A { + match self.bits { + false => PIN1_A::INPUT, + true => PIN1_A::OUTPUT, + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == PIN1_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == PIN1_A::OUTPUT + } +} +#[doc = "Field `PIN1` writer - Pin 1"] +pub type PIN1_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIR_SPEC, PIN1_A, O>; +impl<'a, const O: u8> PIN1_W<'a, O> { + #[doc = "Pin set as input"] + #[inline(always)] + pub fn input(self) -> &'a mut W { + self.variant(PIN1_A::INPUT) + } + #[doc = "Pin set as output"] + #[inline(always)] + pub fn output(self) -> &'a mut W { + self.variant(PIN1_A::OUTPUT) + } +} +#[doc = "Field `PIN2` reader - Pin 2"] +pub type PIN2_R = crate::BitReader; +#[doc = "Pin 2\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN2_A { + #[doc = "0: Pin set as input"] + INPUT = 0, + #[doc = "1: Pin set as output"] + OUTPUT = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN2_A) -> Self { + variant as u8 != 0 + } +} +impl PIN2_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN2_A { + match self.bits { + false => PIN2_A::INPUT, + true => PIN2_A::OUTPUT, + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == PIN2_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == PIN2_A::OUTPUT + } +} +#[doc = "Field `PIN2` writer - Pin 2"] +pub type PIN2_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIR_SPEC, PIN2_A, O>; +impl<'a, const O: u8> PIN2_W<'a, O> { + #[doc = "Pin set as input"] + #[inline(always)] + pub fn input(self) -> &'a mut W { + self.variant(PIN2_A::INPUT) + } + #[doc = "Pin set as output"] + #[inline(always)] + pub fn output(self) -> &'a mut W { + self.variant(PIN2_A::OUTPUT) + } +} +#[doc = "Field `PIN3` reader - Pin 3"] +pub type PIN3_R = crate::BitReader; +#[doc = "Pin 3\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN3_A { + #[doc = "0: Pin set as input"] + INPUT = 0, + #[doc = "1: Pin set as output"] + OUTPUT = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN3_A) -> Self { + variant as u8 != 0 + } +} +impl PIN3_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN3_A { + match self.bits { + false => PIN3_A::INPUT, + true => PIN3_A::OUTPUT, + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == PIN3_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == PIN3_A::OUTPUT + } +} +#[doc = "Field `PIN3` writer - Pin 3"] +pub type PIN3_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIR_SPEC, PIN3_A, O>; +impl<'a, const O: u8> PIN3_W<'a, O> { + #[doc = "Pin set as input"] + #[inline(always)] + pub fn input(self) -> &'a mut W { + self.variant(PIN3_A::INPUT) + } + #[doc = "Pin set as output"] + #[inline(always)] + pub fn output(self) -> &'a mut W { + self.variant(PIN3_A::OUTPUT) + } +} +#[doc = "Field `PIN4` reader - Pin 4"] +pub type PIN4_R = crate::BitReader; +#[doc = "Pin 4\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN4_A { + #[doc = "0: Pin set as input"] + INPUT = 0, + #[doc = "1: Pin set as output"] + OUTPUT = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN4_A) -> Self { + variant as u8 != 0 + } +} +impl PIN4_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN4_A { + match self.bits { + false => PIN4_A::INPUT, + true => PIN4_A::OUTPUT, + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == PIN4_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == PIN4_A::OUTPUT + } +} +#[doc = "Field `PIN4` writer - Pin 4"] +pub type PIN4_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIR_SPEC, PIN4_A, O>; +impl<'a, const O: u8> PIN4_W<'a, O> { + #[doc = "Pin set as input"] + #[inline(always)] + pub fn input(self) -> &'a mut W { + self.variant(PIN4_A::INPUT) + } + #[doc = "Pin set as output"] + #[inline(always)] + pub fn output(self) -> &'a mut W { + self.variant(PIN4_A::OUTPUT) + } +} +#[doc = "Field `PIN5` reader - Pin 5"] +pub type PIN5_R = crate::BitReader; +#[doc = "Pin 5\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN5_A { + #[doc = "0: Pin set as input"] + INPUT = 0, + #[doc = "1: Pin set as output"] + OUTPUT = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN5_A) -> Self { + variant as u8 != 0 + } +} +impl PIN5_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN5_A { + match self.bits { + false => PIN5_A::INPUT, + true => PIN5_A::OUTPUT, + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == PIN5_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == PIN5_A::OUTPUT + } +} +#[doc = "Field `PIN5` writer - Pin 5"] +pub type PIN5_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIR_SPEC, PIN5_A, O>; +impl<'a, const O: u8> PIN5_W<'a, O> { + #[doc = "Pin set as input"] + #[inline(always)] + pub fn input(self) -> &'a mut W { + self.variant(PIN5_A::INPUT) + } + #[doc = "Pin set as output"] + #[inline(always)] + pub fn output(self) -> &'a mut W { + self.variant(PIN5_A::OUTPUT) + } +} +#[doc = "Field `PIN6` reader - Pin 6"] +pub type PIN6_R = crate::BitReader; +#[doc = "Pin 6\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN6_A { + #[doc = "0: Pin set as input"] + INPUT = 0, + #[doc = "1: Pin set as output"] + OUTPUT = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN6_A) -> Self { + variant as u8 != 0 + } +} +impl PIN6_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN6_A { + match self.bits { + false => PIN6_A::INPUT, + true => PIN6_A::OUTPUT, + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == PIN6_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == PIN6_A::OUTPUT + } +} +#[doc = "Field `PIN6` writer - Pin 6"] +pub type PIN6_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIR_SPEC, PIN6_A, O>; +impl<'a, const O: u8> PIN6_W<'a, O> { + #[doc = "Pin set as input"] + #[inline(always)] + pub fn input(self) -> &'a mut W { + self.variant(PIN6_A::INPUT) + } + #[doc = "Pin set as output"] + #[inline(always)] + pub fn output(self) -> &'a mut W { + self.variant(PIN6_A::OUTPUT) + } +} +#[doc = "Field `PIN7` reader - Pin 7"] +pub type PIN7_R = crate::BitReader; +#[doc = "Pin 7\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN7_A { + #[doc = "0: Pin set as input"] + INPUT = 0, + #[doc = "1: Pin set as output"] + OUTPUT = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN7_A) -> Self { + variant as u8 != 0 + } +} +impl PIN7_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN7_A { + match self.bits { + false => PIN7_A::INPUT, + true => PIN7_A::OUTPUT, + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == PIN7_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == PIN7_A::OUTPUT + } +} +#[doc = "Field `PIN7` writer - Pin 7"] +pub type PIN7_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIR_SPEC, PIN7_A, O>; +impl<'a, const O: u8> PIN7_W<'a, O> { + #[doc = "Pin set as input"] + #[inline(always)] + pub fn input(self) -> &'a mut W { + self.variant(PIN7_A::INPUT) + } + #[doc = "Pin set as output"] + #[inline(always)] + pub fn output(self) -> &'a mut W { + self.variant(PIN7_A::OUTPUT) + } +} +#[doc = "Field `PIN8` reader - Pin 8"] +pub type PIN8_R = crate::BitReader; +#[doc = "Pin 8\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN8_A { + #[doc = "0: Pin set as input"] + INPUT = 0, + #[doc = "1: Pin set as output"] + OUTPUT = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN8_A) -> Self { + variant as u8 != 0 + } +} +impl PIN8_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN8_A { + match self.bits { + false => PIN8_A::INPUT, + true => PIN8_A::OUTPUT, + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == PIN8_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == PIN8_A::OUTPUT + } +} +#[doc = "Field `PIN8` writer - Pin 8"] +pub type PIN8_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIR_SPEC, PIN8_A, O>; +impl<'a, const O: u8> PIN8_W<'a, O> { + #[doc = "Pin set as input"] + #[inline(always)] + pub fn input(self) -> &'a mut W { + self.variant(PIN8_A::INPUT) + } + #[doc = "Pin set as output"] + #[inline(always)] + pub fn output(self) -> &'a mut W { + self.variant(PIN8_A::OUTPUT) + } +} +#[doc = "Field `PIN9` reader - Pin 9"] +pub type PIN9_R = crate::BitReader; +#[doc = "Pin 9\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN9_A { + #[doc = "0: Pin set as input"] + INPUT = 0, + #[doc = "1: Pin set as output"] + OUTPUT = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN9_A) -> Self { + variant as u8 != 0 + } +} +impl PIN9_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN9_A { + match self.bits { + false => PIN9_A::INPUT, + true => PIN9_A::OUTPUT, + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == PIN9_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == PIN9_A::OUTPUT + } +} +#[doc = "Field `PIN9` writer - Pin 9"] +pub type PIN9_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIR_SPEC, PIN9_A, O>; +impl<'a, const O: u8> PIN9_W<'a, O> { + #[doc = "Pin set as input"] + #[inline(always)] + pub fn input(self) -> &'a mut W { + self.variant(PIN9_A::INPUT) + } + #[doc = "Pin set as output"] + #[inline(always)] + pub fn output(self) -> &'a mut W { + self.variant(PIN9_A::OUTPUT) + } +} +#[doc = "Field `PIN10` reader - Pin 10"] +pub type PIN10_R = crate::BitReader; +#[doc = "Pin 10\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN10_A { + #[doc = "0: Pin set as input"] + INPUT = 0, + #[doc = "1: Pin set as output"] + OUTPUT = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN10_A) -> Self { + variant as u8 != 0 + } +} +impl PIN10_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN10_A { + match self.bits { + false => PIN10_A::INPUT, + true => PIN10_A::OUTPUT, + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == PIN10_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == PIN10_A::OUTPUT + } +} +#[doc = "Field `PIN10` writer - Pin 10"] +pub type PIN10_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIR_SPEC, PIN10_A, O>; +impl<'a, const O: u8> PIN10_W<'a, O> { + #[doc = "Pin set as input"] + #[inline(always)] + pub fn input(self) -> &'a mut W { + self.variant(PIN10_A::INPUT) + } + #[doc = "Pin set as output"] + #[inline(always)] + pub fn output(self) -> &'a mut W { + self.variant(PIN10_A::OUTPUT) + } +} +#[doc = "Field `PIN11` reader - Pin 11"] +pub type PIN11_R = crate::BitReader; +#[doc = "Pin 11\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN11_A { + #[doc = "0: Pin set as input"] + INPUT = 0, + #[doc = "1: Pin set as output"] + OUTPUT = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN11_A) -> Self { + variant as u8 != 0 + } +} +impl PIN11_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN11_A { + match self.bits { + false => PIN11_A::INPUT, + true => PIN11_A::OUTPUT, + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == PIN11_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == PIN11_A::OUTPUT + } +} +#[doc = "Field `PIN11` writer - Pin 11"] +pub type PIN11_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIR_SPEC, PIN11_A, O>; +impl<'a, const O: u8> PIN11_W<'a, O> { + #[doc = "Pin set as input"] + #[inline(always)] + pub fn input(self) -> &'a mut W { + self.variant(PIN11_A::INPUT) + } + #[doc = "Pin set as output"] + #[inline(always)] + pub fn output(self) -> &'a mut W { + self.variant(PIN11_A::OUTPUT) + } +} +#[doc = "Field `PIN12` reader - Pin 12"] +pub type PIN12_R = crate::BitReader; +#[doc = "Pin 12\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN12_A { + #[doc = "0: Pin set as input"] + INPUT = 0, + #[doc = "1: Pin set as output"] + OUTPUT = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN12_A) -> Self { + variant as u8 != 0 + } +} +impl PIN12_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN12_A { + match self.bits { + false => PIN12_A::INPUT, + true => PIN12_A::OUTPUT, + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == PIN12_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == PIN12_A::OUTPUT + } +} +#[doc = "Field `PIN12` writer - Pin 12"] +pub type PIN12_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIR_SPEC, PIN12_A, O>; +impl<'a, const O: u8> PIN12_W<'a, O> { + #[doc = "Pin set as input"] + #[inline(always)] + pub fn input(self) -> &'a mut W { + self.variant(PIN12_A::INPUT) + } + #[doc = "Pin set as output"] + #[inline(always)] + pub fn output(self) -> &'a mut W { + self.variant(PIN12_A::OUTPUT) + } +} +#[doc = "Field `PIN13` reader - Pin 13"] +pub type PIN13_R = crate::BitReader; +#[doc = "Pin 13\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN13_A { + #[doc = "0: Pin set as input"] + INPUT = 0, + #[doc = "1: Pin set as output"] + OUTPUT = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN13_A) -> Self { + variant as u8 != 0 + } +} +impl PIN13_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN13_A { + match self.bits { + false => PIN13_A::INPUT, + true => PIN13_A::OUTPUT, + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == PIN13_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == PIN13_A::OUTPUT + } +} +#[doc = "Field `PIN13` writer - Pin 13"] +pub type PIN13_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIR_SPEC, PIN13_A, O>; +impl<'a, const O: u8> PIN13_W<'a, O> { + #[doc = "Pin set as input"] + #[inline(always)] + pub fn input(self) -> &'a mut W { + self.variant(PIN13_A::INPUT) + } + #[doc = "Pin set as output"] + #[inline(always)] + pub fn output(self) -> &'a mut W { + self.variant(PIN13_A::OUTPUT) + } +} +#[doc = "Field `PIN14` reader - Pin 14"] +pub type PIN14_R = crate::BitReader; +#[doc = "Pin 14\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN14_A { + #[doc = "0: Pin set as input"] + INPUT = 0, + #[doc = "1: Pin set as output"] + OUTPUT = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN14_A) -> Self { + variant as u8 != 0 + } +} +impl PIN14_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN14_A { + match self.bits { + false => PIN14_A::INPUT, + true => PIN14_A::OUTPUT, + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == PIN14_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == PIN14_A::OUTPUT + } +} +#[doc = "Field `PIN14` writer - Pin 14"] +pub type PIN14_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIR_SPEC, PIN14_A, O>; +impl<'a, const O: u8> PIN14_W<'a, O> { + #[doc = "Pin set as input"] + #[inline(always)] + pub fn input(self) -> &'a mut W { + self.variant(PIN14_A::INPUT) + } + #[doc = "Pin set as output"] + #[inline(always)] + pub fn output(self) -> &'a mut W { + self.variant(PIN14_A::OUTPUT) + } +} +#[doc = "Field `PIN15` reader - Pin 15"] +pub type PIN15_R = crate::BitReader; +#[doc = "Pin 15\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN15_A { + #[doc = "0: Pin set as input"] + INPUT = 0, + #[doc = "1: Pin set as output"] + OUTPUT = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN15_A) -> Self { + variant as u8 != 0 + } +} +impl PIN15_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN15_A { + match self.bits { + false => PIN15_A::INPUT, + true => PIN15_A::OUTPUT, + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == PIN15_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == PIN15_A::OUTPUT + } +} +#[doc = "Field `PIN15` writer - Pin 15"] +pub type PIN15_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIR_SPEC, PIN15_A, O>; +impl<'a, const O: u8> PIN15_W<'a, O> { + #[doc = "Pin set as input"] + #[inline(always)] + pub fn input(self) -> &'a mut W { + self.variant(PIN15_A::INPUT) + } + #[doc = "Pin set as output"] + #[inline(always)] + pub fn output(self) -> &'a mut W { + self.variant(PIN15_A::OUTPUT) + } +} +#[doc = "Field `PIN16` reader - Pin 16"] +pub type PIN16_R = crate::BitReader; +#[doc = "Pin 16\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN16_A { + #[doc = "0: Pin set as input"] + INPUT = 0, + #[doc = "1: Pin set as output"] + OUTPUT = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN16_A) -> Self { + variant as u8 != 0 + } +} +impl PIN16_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN16_A { + match self.bits { + false => PIN16_A::INPUT, + true => PIN16_A::OUTPUT, + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == PIN16_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == PIN16_A::OUTPUT + } +} +#[doc = "Field `PIN16` writer - Pin 16"] +pub type PIN16_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIR_SPEC, PIN16_A, O>; +impl<'a, const O: u8> PIN16_W<'a, O> { + #[doc = "Pin set as input"] + #[inline(always)] + pub fn input(self) -> &'a mut W { + self.variant(PIN16_A::INPUT) + } + #[doc = "Pin set as output"] + #[inline(always)] + pub fn output(self) -> &'a mut W { + self.variant(PIN16_A::OUTPUT) + } +} +#[doc = "Field `PIN17` reader - Pin 17"] +pub type PIN17_R = crate::BitReader; +#[doc = "Pin 17\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN17_A { + #[doc = "0: Pin set as input"] + INPUT = 0, + #[doc = "1: Pin set as output"] + OUTPUT = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN17_A) -> Self { + variant as u8 != 0 + } +} +impl PIN17_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN17_A { + match self.bits { + false => PIN17_A::INPUT, + true => PIN17_A::OUTPUT, + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == PIN17_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == PIN17_A::OUTPUT + } +} +#[doc = "Field `PIN17` writer - Pin 17"] +pub type PIN17_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIR_SPEC, PIN17_A, O>; +impl<'a, const O: u8> PIN17_W<'a, O> { + #[doc = "Pin set as input"] + #[inline(always)] + pub fn input(self) -> &'a mut W { + self.variant(PIN17_A::INPUT) + } + #[doc = "Pin set as output"] + #[inline(always)] + pub fn output(self) -> &'a mut W { + self.variant(PIN17_A::OUTPUT) + } +} +#[doc = "Field `PIN18` reader - Pin 18"] +pub type PIN18_R = crate::BitReader; +#[doc = "Pin 18\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN18_A { + #[doc = "0: Pin set as input"] + INPUT = 0, + #[doc = "1: Pin set as output"] + OUTPUT = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN18_A) -> Self { + variant as u8 != 0 + } +} +impl PIN18_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN18_A { + match self.bits { + false => PIN18_A::INPUT, + true => PIN18_A::OUTPUT, + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == PIN18_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == PIN18_A::OUTPUT + } +} +#[doc = "Field `PIN18` writer - Pin 18"] +pub type PIN18_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIR_SPEC, PIN18_A, O>; +impl<'a, const O: u8> PIN18_W<'a, O> { + #[doc = "Pin set as input"] + #[inline(always)] + pub fn input(self) -> &'a mut W { + self.variant(PIN18_A::INPUT) + } + #[doc = "Pin set as output"] + #[inline(always)] + pub fn output(self) -> &'a mut W { + self.variant(PIN18_A::OUTPUT) + } +} +#[doc = "Field `PIN19` reader - Pin 19"] +pub type PIN19_R = crate::BitReader; +#[doc = "Pin 19\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN19_A { + #[doc = "0: Pin set as input"] + INPUT = 0, + #[doc = "1: Pin set as output"] + OUTPUT = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN19_A) -> Self { + variant as u8 != 0 + } +} +impl PIN19_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN19_A { + match self.bits { + false => PIN19_A::INPUT, + true => PIN19_A::OUTPUT, + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == PIN19_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == PIN19_A::OUTPUT + } +} +#[doc = "Field `PIN19` writer - Pin 19"] +pub type PIN19_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIR_SPEC, PIN19_A, O>; +impl<'a, const O: u8> PIN19_W<'a, O> { + #[doc = "Pin set as input"] + #[inline(always)] + pub fn input(self) -> &'a mut W { + self.variant(PIN19_A::INPUT) + } + #[doc = "Pin set as output"] + #[inline(always)] + pub fn output(self) -> &'a mut W { + self.variant(PIN19_A::OUTPUT) + } +} +#[doc = "Field `PIN20` reader - Pin 20"] +pub type PIN20_R = crate::BitReader; +#[doc = "Pin 20\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN20_A { + #[doc = "0: Pin set as input"] + INPUT = 0, + #[doc = "1: Pin set as output"] + OUTPUT = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN20_A) -> Self { + variant as u8 != 0 + } +} +impl PIN20_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN20_A { + match self.bits { + false => PIN20_A::INPUT, + true => PIN20_A::OUTPUT, + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == PIN20_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == PIN20_A::OUTPUT + } +} +#[doc = "Field `PIN20` writer - Pin 20"] +pub type PIN20_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIR_SPEC, PIN20_A, O>; +impl<'a, const O: u8> PIN20_W<'a, O> { + #[doc = "Pin set as input"] + #[inline(always)] + pub fn input(self) -> &'a mut W { + self.variant(PIN20_A::INPUT) + } + #[doc = "Pin set as output"] + #[inline(always)] + pub fn output(self) -> &'a mut W { + self.variant(PIN20_A::OUTPUT) + } +} +#[doc = "Field `PIN21` reader - Pin 21"] +pub type PIN21_R = crate::BitReader; +#[doc = "Pin 21\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN21_A { + #[doc = "0: Pin set as input"] + INPUT = 0, + #[doc = "1: Pin set as output"] + OUTPUT = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN21_A) -> Self { + variant as u8 != 0 + } +} +impl PIN21_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN21_A { + match self.bits { + false => PIN21_A::INPUT, + true => PIN21_A::OUTPUT, + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == PIN21_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == PIN21_A::OUTPUT + } +} +#[doc = "Field `PIN21` writer - Pin 21"] +pub type PIN21_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIR_SPEC, PIN21_A, O>; +impl<'a, const O: u8> PIN21_W<'a, O> { + #[doc = "Pin set as input"] + #[inline(always)] + pub fn input(self) -> &'a mut W { + self.variant(PIN21_A::INPUT) + } + #[doc = "Pin set as output"] + #[inline(always)] + pub fn output(self) -> &'a mut W { + self.variant(PIN21_A::OUTPUT) + } +} +#[doc = "Field `PIN22` reader - Pin 22"] +pub type PIN22_R = crate::BitReader; +#[doc = "Pin 22\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN22_A { + #[doc = "0: Pin set as input"] + INPUT = 0, + #[doc = "1: Pin set as output"] + OUTPUT = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN22_A) -> Self { + variant as u8 != 0 + } +} +impl PIN22_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN22_A { + match self.bits { + false => PIN22_A::INPUT, + true => PIN22_A::OUTPUT, + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == PIN22_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == PIN22_A::OUTPUT + } +} +#[doc = "Field `PIN22` writer - Pin 22"] +pub type PIN22_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIR_SPEC, PIN22_A, O>; +impl<'a, const O: u8> PIN22_W<'a, O> { + #[doc = "Pin set as input"] + #[inline(always)] + pub fn input(self) -> &'a mut W { + self.variant(PIN22_A::INPUT) + } + #[doc = "Pin set as output"] + #[inline(always)] + pub fn output(self) -> &'a mut W { + self.variant(PIN22_A::OUTPUT) + } +} +#[doc = "Field `PIN23` reader - Pin 23"] +pub type PIN23_R = crate::BitReader; +#[doc = "Pin 23\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN23_A { + #[doc = "0: Pin set as input"] + INPUT = 0, + #[doc = "1: Pin set as output"] + OUTPUT = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN23_A) -> Self { + variant as u8 != 0 + } +} +impl PIN23_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN23_A { + match self.bits { + false => PIN23_A::INPUT, + true => PIN23_A::OUTPUT, + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == PIN23_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == PIN23_A::OUTPUT + } +} +#[doc = "Field `PIN23` writer - Pin 23"] +pub type PIN23_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIR_SPEC, PIN23_A, O>; +impl<'a, const O: u8> PIN23_W<'a, O> { + #[doc = "Pin set as input"] + #[inline(always)] + pub fn input(self) -> &'a mut W { + self.variant(PIN23_A::INPUT) + } + #[doc = "Pin set as output"] + #[inline(always)] + pub fn output(self) -> &'a mut W { + self.variant(PIN23_A::OUTPUT) + } +} +#[doc = "Field `PIN24` reader - Pin 24"] +pub type PIN24_R = crate::BitReader; +#[doc = "Pin 24\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN24_A { + #[doc = "0: Pin set as input"] + INPUT = 0, + #[doc = "1: Pin set as output"] + OUTPUT = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN24_A) -> Self { + variant as u8 != 0 + } +} +impl PIN24_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN24_A { + match self.bits { + false => PIN24_A::INPUT, + true => PIN24_A::OUTPUT, + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == PIN24_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == PIN24_A::OUTPUT + } +} +#[doc = "Field `PIN24` writer - Pin 24"] +pub type PIN24_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIR_SPEC, PIN24_A, O>; +impl<'a, const O: u8> PIN24_W<'a, O> { + #[doc = "Pin set as input"] + #[inline(always)] + pub fn input(self) -> &'a mut W { + self.variant(PIN24_A::INPUT) + } + #[doc = "Pin set as output"] + #[inline(always)] + pub fn output(self) -> &'a mut W { + self.variant(PIN24_A::OUTPUT) + } +} +#[doc = "Field `PIN25` reader - Pin 25"] +pub type PIN25_R = crate::BitReader; +#[doc = "Pin 25\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN25_A { + #[doc = "0: Pin set as input"] + INPUT = 0, + #[doc = "1: Pin set as output"] + OUTPUT = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN25_A) -> Self { + variant as u8 != 0 + } +} +impl PIN25_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN25_A { + match self.bits { + false => PIN25_A::INPUT, + true => PIN25_A::OUTPUT, + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == PIN25_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == PIN25_A::OUTPUT + } +} +#[doc = "Field `PIN25` writer - Pin 25"] +pub type PIN25_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIR_SPEC, PIN25_A, O>; +impl<'a, const O: u8> PIN25_W<'a, O> { + #[doc = "Pin set as input"] + #[inline(always)] + pub fn input(self) -> &'a mut W { + self.variant(PIN25_A::INPUT) + } + #[doc = "Pin set as output"] + #[inline(always)] + pub fn output(self) -> &'a mut W { + self.variant(PIN25_A::OUTPUT) + } +} +#[doc = "Field `PIN26` reader - Pin 26"] +pub type PIN26_R = crate::BitReader; +#[doc = "Pin 26\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN26_A { + #[doc = "0: Pin set as input"] + INPUT = 0, + #[doc = "1: Pin set as output"] + OUTPUT = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN26_A) -> Self { + variant as u8 != 0 + } +} +impl PIN26_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN26_A { + match self.bits { + false => PIN26_A::INPUT, + true => PIN26_A::OUTPUT, + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == PIN26_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == PIN26_A::OUTPUT + } +} +#[doc = "Field `PIN26` writer - Pin 26"] +pub type PIN26_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIR_SPEC, PIN26_A, O>; +impl<'a, const O: u8> PIN26_W<'a, O> { + #[doc = "Pin set as input"] + #[inline(always)] + pub fn input(self) -> &'a mut W { + self.variant(PIN26_A::INPUT) + } + #[doc = "Pin set as output"] + #[inline(always)] + pub fn output(self) -> &'a mut W { + self.variant(PIN26_A::OUTPUT) + } +} +#[doc = "Field `PIN27` reader - Pin 27"] +pub type PIN27_R = crate::BitReader; +#[doc = "Pin 27\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN27_A { + #[doc = "0: Pin set as input"] + INPUT = 0, + #[doc = "1: Pin set as output"] + OUTPUT = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN27_A) -> Self { + variant as u8 != 0 + } +} +impl PIN27_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN27_A { + match self.bits { + false => PIN27_A::INPUT, + true => PIN27_A::OUTPUT, + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == PIN27_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == PIN27_A::OUTPUT + } +} +#[doc = "Field `PIN27` writer - Pin 27"] +pub type PIN27_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIR_SPEC, PIN27_A, O>; +impl<'a, const O: u8> PIN27_W<'a, O> { + #[doc = "Pin set as input"] + #[inline(always)] + pub fn input(self) -> &'a mut W { + self.variant(PIN27_A::INPUT) + } + #[doc = "Pin set as output"] + #[inline(always)] + pub fn output(self) -> &'a mut W { + self.variant(PIN27_A::OUTPUT) + } +} +#[doc = "Field `PIN28` reader - Pin 28"] +pub type PIN28_R = crate::BitReader; +#[doc = "Pin 28\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN28_A { + #[doc = "0: Pin set as input"] + INPUT = 0, + #[doc = "1: Pin set as output"] + OUTPUT = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN28_A) -> Self { + variant as u8 != 0 + } +} +impl PIN28_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN28_A { + match self.bits { + false => PIN28_A::INPUT, + true => PIN28_A::OUTPUT, + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == PIN28_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == PIN28_A::OUTPUT + } +} +#[doc = "Field `PIN28` writer - Pin 28"] +pub type PIN28_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIR_SPEC, PIN28_A, O>; +impl<'a, const O: u8> PIN28_W<'a, O> { + #[doc = "Pin set as input"] + #[inline(always)] + pub fn input(self) -> &'a mut W { + self.variant(PIN28_A::INPUT) + } + #[doc = "Pin set as output"] + #[inline(always)] + pub fn output(self) -> &'a mut W { + self.variant(PIN28_A::OUTPUT) + } +} +#[doc = "Field `PIN29` reader - Pin 29"] +pub type PIN29_R = crate::BitReader; +#[doc = "Pin 29\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN29_A { + #[doc = "0: Pin set as input"] + INPUT = 0, + #[doc = "1: Pin set as output"] + OUTPUT = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN29_A) -> Self { + variant as u8 != 0 + } +} +impl PIN29_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN29_A { + match self.bits { + false => PIN29_A::INPUT, + true => PIN29_A::OUTPUT, + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == PIN29_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == PIN29_A::OUTPUT + } +} +#[doc = "Field `PIN29` writer - Pin 29"] +pub type PIN29_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIR_SPEC, PIN29_A, O>; +impl<'a, const O: u8> PIN29_W<'a, O> { + #[doc = "Pin set as input"] + #[inline(always)] + pub fn input(self) -> &'a mut W { + self.variant(PIN29_A::INPUT) + } + #[doc = "Pin set as output"] + #[inline(always)] + pub fn output(self) -> &'a mut W { + self.variant(PIN29_A::OUTPUT) + } +} +#[doc = "Field `PIN30` reader - Pin 30"] +pub type PIN30_R = crate::BitReader; +#[doc = "Pin 30\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN30_A { + #[doc = "0: Pin set as input"] + INPUT = 0, + #[doc = "1: Pin set as output"] + OUTPUT = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN30_A) -> Self { + variant as u8 != 0 + } +} +impl PIN30_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN30_A { + match self.bits { + false => PIN30_A::INPUT, + true => PIN30_A::OUTPUT, + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == PIN30_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == PIN30_A::OUTPUT + } +} +#[doc = "Field `PIN30` writer - Pin 30"] +pub type PIN30_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIR_SPEC, PIN30_A, O>; +impl<'a, const O: u8> PIN30_W<'a, O> { + #[doc = "Pin set as input"] + #[inline(always)] + pub fn input(self) -> &'a mut W { + self.variant(PIN30_A::INPUT) + } + #[doc = "Pin set as output"] + #[inline(always)] + pub fn output(self) -> &'a mut W { + self.variant(PIN30_A::OUTPUT) + } +} +#[doc = "Field `PIN31` reader - Pin 31"] +pub type PIN31_R = crate::BitReader; +#[doc = "Pin 31\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN31_A { + #[doc = "0: Pin set as input"] + INPUT = 0, + #[doc = "1: Pin set as output"] + OUTPUT = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN31_A) -> Self { + variant as u8 != 0 + } +} +impl PIN31_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN31_A { + match self.bits { + false => PIN31_A::INPUT, + true => PIN31_A::OUTPUT, + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == PIN31_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == PIN31_A::OUTPUT + } +} +#[doc = "Field `PIN31` writer - Pin 31"] +pub type PIN31_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIR_SPEC, PIN31_A, O>; +impl<'a, const O: u8> PIN31_W<'a, O> { + #[doc = "Pin set as input"] + #[inline(always)] + pub fn input(self) -> &'a mut W { + self.variant(PIN31_A::INPUT) + } + #[doc = "Pin set as output"] + #[inline(always)] + pub fn output(self) -> &'a mut W { + self.variant(PIN31_A::OUTPUT) + } +} +impl R { + #[doc = "Bit 0 - Pin 0"] + #[inline(always)] + pub fn pin0(&self) -> PIN0_R { + PIN0_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Pin 1"] + #[inline(always)] + pub fn pin1(&self) -> PIN1_R { + PIN1_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Pin 2"] + #[inline(always)] + pub fn pin2(&self) -> PIN2_R { + PIN2_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Pin 3"] + #[inline(always)] + pub fn pin3(&self) -> PIN3_R { + PIN3_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Pin 4"] + #[inline(always)] + pub fn pin4(&self) -> PIN4_R { + PIN4_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Pin 5"] + #[inline(always)] + pub fn pin5(&self) -> PIN5_R { + PIN5_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Pin 6"] + #[inline(always)] + pub fn pin6(&self) -> PIN6_R { + PIN6_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Pin 7"] + #[inline(always)] + pub fn pin7(&self) -> PIN7_R { + PIN7_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Pin 8"] + #[inline(always)] + pub fn pin8(&self) -> PIN8_R { + PIN8_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Pin 9"] + #[inline(always)] + pub fn pin9(&self) -> PIN9_R { + PIN9_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Pin 10"] + #[inline(always)] + pub fn pin10(&self) -> PIN10_R { + PIN10_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Pin 11"] + #[inline(always)] + pub fn pin11(&self) -> PIN11_R { + PIN11_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Pin 12"] + #[inline(always)] + pub fn pin12(&self) -> PIN12_R { + PIN12_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Pin 13"] + #[inline(always)] + pub fn pin13(&self) -> PIN13_R { + PIN13_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Pin 14"] + #[inline(always)] + pub fn pin14(&self) -> PIN14_R { + PIN14_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Pin 15"] + #[inline(always)] + pub fn pin15(&self) -> PIN15_R { + PIN15_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - Pin 16"] + #[inline(always)] + pub fn pin16(&self) -> PIN16_R { + PIN16_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Pin 17"] + #[inline(always)] + pub fn pin17(&self) -> PIN17_R { + PIN17_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Pin 18"] + #[inline(always)] + pub fn pin18(&self) -> PIN18_R { + PIN18_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Pin 19"] + #[inline(always)] + pub fn pin19(&self) -> PIN19_R { + PIN19_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Pin 20"] + #[inline(always)] + pub fn pin20(&self) -> PIN20_R { + PIN20_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Pin 21"] + #[inline(always)] + pub fn pin21(&self) -> PIN21_R { + PIN21_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Pin 22"] + #[inline(always)] + pub fn pin22(&self) -> PIN22_R { + PIN22_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - Pin 23"] + #[inline(always)] + pub fn pin23(&self) -> PIN23_R { + PIN23_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - Pin 24"] + #[inline(always)] + pub fn pin24(&self) -> PIN24_R { + PIN24_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - Pin 25"] + #[inline(always)] + pub fn pin25(&self) -> PIN25_R { + PIN25_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - Pin 26"] + #[inline(always)] + pub fn pin26(&self) -> PIN26_R { + PIN26_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - Pin 27"] + #[inline(always)] + pub fn pin27(&self) -> PIN27_R { + PIN27_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - Pin 28"] + #[inline(always)] + pub fn pin28(&self) -> PIN28_R { + PIN28_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - Pin 29"] + #[inline(always)] + pub fn pin29(&self) -> PIN29_R { + PIN29_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Pin 30"] + #[inline(always)] + pub fn pin30(&self) -> PIN30_R { + PIN30_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Pin 31"] + #[inline(always)] + pub fn pin31(&self) -> PIN31_R { + PIN31_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Pin 0"] + #[inline(always)] + pub fn pin0(&mut self) -> PIN0_W<0> { + PIN0_W::new(self) + } + #[doc = "Bit 1 - Pin 1"] + #[inline(always)] + pub fn pin1(&mut self) -> PIN1_W<1> { + PIN1_W::new(self) + } + #[doc = "Bit 2 - Pin 2"] + #[inline(always)] + pub fn pin2(&mut self) -> PIN2_W<2> { + PIN2_W::new(self) + } + #[doc = "Bit 3 - Pin 3"] + #[inline(always)] + pub fn pin3(&mut self) -> PIN3_W<3> { + PIN3_W::new(self) + } + #[doc = "Bit 4 - Pin 4"] + #[inline(always)] + pub fn pin4(&mut self) -> PIN4_W<4> { + PIN4_W::new(self) + } + #[doc = "Bit 5 - Pin 5"] + #[inline(always)] + pub fn pin5(&mut self) -> PIN5_W<5> { + PIN5_W::new(self) + } + #[doc = "Bit 6 - Pin 6"] + #[inline(always)] + pub fn pin6(&mut self) -> PIN6_W<6> { + PIN6_W::new(self) + } + #[doc = "Bit 7 - Pin 7"] + #[inline(always)] + pub fn pin7(&mut self) -> PIN7_W<7> { + PIN7_W::new(self) + } + #[doc = "Bit 8 - Pin 8"] + #[inline(always)] + pub fn pin8(&mut self) -> PIN8_W<8> { + PIN8_W::new(self) + } + #[doc = "Bit 9 - Pin 9"] + #[inline(always)] + pub fn pin9(&mut self) -> PIN9_W<9> { + PIN9_W::new(self) + } + #[doc = "Bit 10 - Pin 10"] + #[inline(always)] + pub fn pin10(&mut self) -> PIN10_W<10> { + PIN10_W::new(self) + } + #[doc = "Bit 11 - Pin 11"] + #[inline(always)] + pub fn pin11(&mut self) -> PIN11_W<11> { + PIN11_W::new(self) + } + #[doc = "Bit 12 - Pin 12"] + #[inline(always)] + pub fn pin12(&mut self) -> PIN12_W<12> { + PIN12_W::new(self) + } + #[doc = "Bit 13 - Pin 13"] + #[inline(always)] + pub fn pin13(&mut self) -> PIN13_W<13> { + PIN13_W::new(self) + } + #[doc = "Bit 14 - Pin 14"] + #[inline(always)] + pub fn pin14(&mut self) -> PIN14_W<14> { + PIN14_W::new(self) + } + #[doc = "Bit 15 - Pin 15"] + #[inline(always)] + pub fn pin15(&mut self) -> PIN15_W<15> { + PIN15_W::new(self) + } + #[doc = "Bit 16 - Pin 16"] + #[inline(always)] + pub fn pin16(&mut self) -> PIN16_W<16> { + PIN16_W::new(self) + } + #[doc = "Bit 17 - Pin 17"] + #[inline(always)] + pub fn pin17(&mut self) -> PIN17_W<17> { + PIN17_W::new(self) + } + #[doc = "Bit 18 - Pin 18"] + #[inline(always)] + pub fn pin18(&mut self) -> PIN18_W<18> { + PIN18_W::new(self) + } + #[doc = "Bit 19 - Pin 19"] + #[inline(always)] + pub fn pin19(&mut self) -> PIN19_W<19> { + PIN19_W::new(self) + } + #[doc = "Bit 20 - Pin 20"] + #[inline(always)] + pub fn pin20(&mut self) -> PIN20_W<20> { + PIN20_W::new(self) + } + #[doc = "Bit 21 - Pin 21"] + #[inline(always)] + pub fn pin21(&mut self) -> PIN21_W<21> { + PIN21_W::new(self) + } + #[doc = "Bit 22 - Pin 22"] + #[inline(always)] + pub fn pin22(&mut self) -> PIN22_W<22> { + PIN22_W::new(self) + } + #[doc = "Bit 23 - Pin 23"] + #[inline(always)] + pub fn pin23(&mut self) -> PIN23_W<23> { + PIN23_W::new(self) + } + #[doc = "Bit 24 - Pin 24"] + #[inline(always)] + pub fn pin24(&mut self) -> PIN24_W<24> { + PIN24_W::new(self) + } + #[doc = "Bit 25 - Pin 25"] + #[inline(always)] + pub fn pin25(&mut self) -> PIN25_W<25> { + PIN25_W::new(self) + } + #[doc = "Bit 26 - Pin 26"] + #[inline(always)] + pub fn pin26(&mut self) -> PIN26_W<26> { + PIN26_W::new(self) + } + #[doc = "Bit 27 - Pin 27"] + #[inline(always)] + pub fn pin27(&mut self) -> PIN27_W<27> { + PIN27_W::new(self) + } + #[doc = "Bit 28 - Pin 28"] + #[inline(always)] + pub fn pin28(&mut self) -> PIN28_W<28> { + PIN28_W::new(self) + } + #[doc = "Bit 29 - Pin 29"] + #[inline(always)] + pub fn pin29(&mut self) -> PIN29_W<29> { + PIN29_W::new(self) + } + #[doc = "Bit 30 - Pin 30"] + #[inline(always)] + pub fn pin30(&mut self) -> PIN30_W<30> { + PIN30_W::new(self) + } + #[doc = "Bit 31 - Pin 31"] + #[inline(always)] + pub fn pin31(&mut self) -> PIN31_W<31> { + PIN31_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Direction of GPIO pins\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dir](index.html) module"] +pub struct DIR_SPEC; +impl crate::RegisterSpec for DIR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dir::R](R) reader structure"] +impl crate::Readable for DIR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dir::W](W) writer structure"] +impl crate::Writable for DIR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DIR to value 0"] +impl crate::Resettable for DIR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/p0_ns/dirclr.rs b/pacs/nrf9120-pac/src/p0_ns/dirclr.rs new file mode 100644 index 00000000..9dcf634a --- /dev/null +++ b/pacs/nrf9120-pac/src/p0_ns/dirclr.rs @@ -0,0 +1,2210 @@ +#[doc = "Register `DIRCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DIRCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PIN0` reader - Set as input pin 0"] +pub type PIN0_R = crate::BitReader; +#[doc = "Set as input pin 0\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN0_A { + #[doc = "0: Read: pin set as input"] + INPUT = 0, + #[doc = "1: Read: pin set as output"] + OUTPUT = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN0_A) -> Self { + variant as u8 != 0 + } +} +impl PIN0_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN0_A { + match self.bits { + false => PIN0_A::INPUT, + true => PIN0_A::OUTPUT, + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == PIN0_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == PIN0_A::OUTPUT + } +} +#[doc = "Set as input pin 0\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN0_AW { + #[doc = "1: Write: writing a '1' sets pin to input; writing a '0' has no effect"] + CLEAR = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN0_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PIN0` writer - Set as input pin 0"] +pub type PIN0_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DIRCLR_SPEC, PIN0_AW, O>; +impl<'a, const O: u8> PIN0_W<'a, O> { + #[doc = "Write: writing a '1' sets pin to input; writing a '0' has no effect"] + #[inline(always)] + pub fn clear(self) -> &'a mut W { + self.variant(PIN0_AW::CLEAR) + } +} +#[doc = "Field `PIN1` reader - Set as input pin 1"] +pub type PIN1_R = crate::BitReader; +#[doc = "Set as input pin 1\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN1_A { + #[doc = "0: Read: pin set as input"] + INPUT = 0, + #[doc = "1: Read: pin set as output"] + OUTPUT = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN1_A) -> Self { + variant as u8 != 0 + } +} +impl PIN1_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN1_A { + match self.bits { + false => PIN1_A::INPUT, + true => PIN1_A::OUTPUT, + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == PIN1_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == PIN1_A::OUTPUT + } +} +#[doc = "Set as input pin 1\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN1_AW { + #[doc = "1: Write: writing a '1' sets pin to input; writing a '0' has no effect"] + CLEAR = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN1_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PIN1` writer - Set as input pin 1"] +pub type PIN1_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DIRCLR_SPEC, PIN1_AW, O>; +impl<'a, const O: u8> PIN1_W<'a, O> { + #[doc = "Write: writing a '1' sets pin to input; writing a '0' has no effect"] + #[inline(always)] + pub fn clear(self) -> &'a mut W { + self.variant(PIN1_AW::CLEAR) + } +} +#[doc = "Field `PIN2` reader - Set as input pin 2"] +pub type PIN2_R = crate::BitReader; +#[doc = "Set as input pin 2\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN2_A { + #[doc = "0: Read: pin set as input"] + INPUT = 0, + #[doc = "1: Read: pin set as output"] + OUTPUT = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN2_A) -> Self { + variant as u8 != 0 + } +} +impl PIN2_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN2_A { + match self.bits { + false => PIN2_A::INPUT, + true => PIN2_A::OUTPUT, + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == PIN2_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == PIN2_A::OUTPUT + } +} +#[doc = "Set as input pin 2\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN2_AW { + #[doc = "1: Write: writing a '1' sets pin to input; writing a '0' has no effect"] + CLEAR = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN2_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PIN2` writer - Set as input pin 2"] +pub type PIN2_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DIRCLR_SPEC, PIN2_AW, O>; +impl<'a, const O: u8> PIN2_W<'a, O> { + #[doc = "Write: writing a '1' sets pin to input; writing a '0' has no effect"] + #[inline(always)] + pub fn clear(self) -> &'a mut W { + self.variant(PIN2_AW::CLEAR) + } +} +#[doc = "Field `PIN3` reader - Set as input pin 3"] +pub type PIN3_R = crate::BitReader; +#[doc = "Set as input pin 3\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN3_A { + #[doc = "0: Read: pin set as input"] + INPUT = 0, + #[doc = "1: Read: pin set as output"] + OUTPUT = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN3_A) -> Self { + variant as u8 != 0 + } +} +impl PIN3_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN3_A { + match self.bits { + false => PIN3_A::INPUT, + true => PIN3_A::OUTPUT, + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == PIN3_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == PIN3_A::OUTPUT + } +} +#[doc = "Set as input pin 3\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN3_AW { + #[doc = "1: Write: writing a '1' sets pin to input; writing a '0' has no effect"] + CLEAR = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN3_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PIN3` writer - Set as input pin 3"] +pub type PIN3_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DIRCLR_SPEC, PIN3_AW, O>; +impl<'a, const O: u8> PIN3_W<'a, O> { + #[doc = "Write: writing a '1' sets pin to input; writing a '0' has no effect"] + #[inline(always)] + pub fn clear(self) -> &'a mut W { + self.variant(PIN3_AW::CLEAR) + } +} +#[doc = "Field `PIN4` reader - Set as input pin 4"] +pub type PIN4_R = crate::BitReader; +#[doc = "Set as input pin 4\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN4_A { + #[doc = "0: Read: pin set as input"] + INPUT = 0, + #[doc = "1: Read: pin set as output"] + OUTPUT = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN4_A) -> Self { + variant as u8 != 0 + } +} +impl PIN4_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN4_A { + match self.bits { + false => PIN4_A::INPUT, + true => PIN4_A::OUTPUT, + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == PIN4_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == PIN4_A::OUTPUT + } +} +#[doc = "Set as input pin 4\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN4_AW { + #[doc = "1: Write: writing a '1' sets pin to input; writing a '0' has no effect"] + CLEAR = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN4_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PIN4` writer - Set as input pin 4"] +pub type PIN4_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DIRCLR_SPEC, PIN4_AW, O>; +impl<'a, const O: u8> PIN4_W<'a, O> { + #[doc = "Write: writing a '1' sets pin to input; writing a '0' has no effect"] + #[inline(always)] + pub fn clear(self) -> &'a mut W { + self.variant(PIN4_AW::CLEAR) + } +} +#[doc = "Field `PIN5` reader - Set as input pin 5"] +pub type PIN5_R = crate::BitReader; +#[doc = "Set as input pin 5\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN5_A { + #[doc = "0: Read: pin set as input"] + INPUT = 0, + #[doc = "1: Read: pin set as output"] + OUTPUT = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN5_A) -> Self { + variant as u8 != 0 + } +} +impl PIN5_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN5_A { + match self.bits { + false => PIN5_A::INPUT, + true => PIN5_A::OUTPUT, + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == PIN5_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == PIN5_A::OUTPUT + } +} +#[doc = "Set as input pin 5\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN5_AW { + #[doc = "1: Write: writing a '1' sets pin to input; writing a '0' has no effect"] + CLEAR = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN5_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PIN5` writer - Set as input pin 5"] +pub type PIN5_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DIRCLR_SPEC, PIN5_AW, O>; +impl<'a, const O: u8> PIN5_W<'a, O> { + #[doc = "Write: writing a '1' sets pin to input; writing a '0' has no effect"] + #[inline(always)] + pub fn clear(self) -> &'a mut W { + self.variant(PIN5_AW::CLEAR) + } +} +#[doc = "Field `PIN6` reader - Set as input pin 6"] +pub type PIN6_R = crate::BitReader; +#[doc = "Set as input pin 6\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN6_A { + #[doc = "0: Read: pin set as input"] + INPUT = 0, + #[doc = "1: Read: pin set as output"] + OUTPUT = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN6_A) -> Self { + variant as u8 != 0 + } +} +impl PIN6_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN6_A { + match self.bits { + false => PIN6_A::INPUT, + true => PIN6_A::OUTPUT, + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == PIN6_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == PIN6_A::OUTPUT + } +} +#[doc = "Set as input pin 6\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN6_AW { + #[doc = "1: Write: writing a '1' sets pin to input; writing a '0' has no effect"] + CLEAR = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN6_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PIN6` writer - Set as input pin 6"] +pub type PIN6_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DIRCLR_SPEC, PIN6_AW, O>; +impl<'a, const O: u8> PIN6_W<'a, O> { + #[doc = "Write: writing a '1' sets pin to input; writing a '0' has no effect"] + #[inline(always)] + pub fn clear(self) -> &'a mut W { + self.variant(PIN6_AW::CLEAR) + } +} +#[doc = "Field `PIN7` reader - Set as input pin 7"] +pub type PIN7_R = crate::BitReader; +#[doc = "Set as input pin 7\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN7_A { + #[doc = "0: Read: pin set as input"] + INPUT = 0, + #[doc = "1: Read: pin set as output"] + OUTPUT = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN7_A) -> Self { + variant as u8 != 0 + } +} +impl PIN7_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN7_A { + match self.bits { + false => PIN7_A::INPUT, + true => PIN7_A::OUTPUT, + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == PIN7_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == PIN7_A::OUTPUT + } +} +#[doc = "Set as input pin 7\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN7_AW { + #[doc = "1: Write: writing a '1' sets pin to input; writing a '0' has no effect"] + CLEAR = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN7_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PIN7` writer - Set as input pin 7"] +pub type PIN7_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DIRCLR_SPEC, PIN7_AW, O>; +impl<'a, const O: u8> PIN7_W<'a, O> { + #[doc = "Write: writing a '1' sets pin to input; writing a '0' has no effect"] + #[inline(always)] + pub fn clear(self) -> &'a mut W { + self.variant(PIN7_AW::CLEAR) + } +} +#[doc = "Field `PIN8` reader - Set as input pin 8"] +pub type PIN8_R = crate::BitReader; +#[doc = "Set as input pin 8\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN8_A { + #[doc = "0: Read: pin set as input"] + INPUT = 0, + #[doc = "1: Read: pin set as output"] + OUTPUT = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN8_A) -> Self { + variant as u8 != 0 + } +} +impl PIN8_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN8_A { + match self.bits { + false => PIN8_A::INPUT, + true => PIN8_A::OUTPUT, + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == PIN8_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == PIN8_A::OUTPUT + } +} +#[doc = "Set as input pin 8\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN8_AW { + #[doc = "1: Write: writing a '1' sets pin to input; writing a '0' has no effect"] + CLEAR = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN8_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PIN8` writer - Set as input pin 8"] +pub type PIN8_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DIRCLR_SPEC, PIN8_AW, O>; +impl<'a, const O: u8> PIN8_W<'a, O> { + #[doc = "Write: writing a '1' sets pin to input; writing a '0' has no effect"] + #[inline(always)] + pub fn clear(self) -> &'a mut W { + self.variant(PIN8_AW::CLEAR) + } +} +#[doc = "Field `PIN9` reader - Set as input pin 9"] +pub type PIN9_R = crate::BitReader; +#[doc = "Set as input pin 9\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN9_A { + #[doc = "0: Read: pin set as input"] + INPUT = 0, + #[doc = "1: Read: pin set as output"] + OUTPUT = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN9_A) -> Self { + variant as u8 != 0 + } +} +impl PIN9_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN9_A { + match self.bits { + false => PIN9_A::INPUT, + true => PIN9_A::OUTPUT, + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == PIN9_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == PIN9_A::OUTPUT + } +} +#[doc = "Set as input pin 9\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN9_AW { + #[doc = "1: Write: writing a '1' sets pin to input; writing a '0' has no effect"] + CLEAR = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN9_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PIN9` writer - Set as input pin 9"] +pub type PIN9_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DIRCLR_SPEC, PIN9_AW, O>; +impl<'a, const O: u8> PIN9_W<'a, O> { + #[doc = "Write: writing a '1' sets pin to input; writing a '0' has no effect"] + #[inline(always)] + pub fn clear(self) -> &'a mut W { + self.variant(PIN9_AW::CLEAR) + } +} +#[doc = "Field `PIN10` reader - Set as input pin 10"] +pub type PIN10_R = crate::BitReader; +#[doc = "Set as input pin 10\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN10_A { + #[doc = "0: Read: pin set as input"] + INPUT = 0, + #[doc = "1: Read: pin set as output"] + OUTPUT = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN10_A) -> Self { + variant as u8 != 0 + } +} +impl PIN10_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN10_A { + match self.bits { + false => PIN10_A::INPUT, + true => PIN10_A::OUTPUT, + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == PIN10_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == PIN10_A::OUTPUT + } +} +#[doc = "Set as input pin 10\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN10_AW { + #[doc = "1: Write: writing a '1' sets pin to input; writing a '0' has no effect"] + CLEAR = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN10_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PIN10` writer - Set as input pin 10"] +pub type PIN10_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DIRCLR_SPEC, PIN10_AW, O>; +impl<'a, const O: u8> PIN10_W<'a, O> { + #[doc = "Write: writing a '1' sets pin to input; writing a '0' has no effect"] + #[inline(always)] + pub fn clear(self) -> &'a mut W { + self.variant(PIN10_AW::CLEAR) + } +} +#[doc = "Field `PIN11` reader - Set as input pin 11"] +pub type PIN11_R = crate::BitReader; +#[doc = "Set as input pin 11\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN11_A { + #[doc = "0: Read: pin set as input"] + INPUT = 0, + #[doc = "1: Read: pin set as output"] + OUTPUT = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN11_A) -> Self { + variant as u8 != 0 + } +} +impl PIN11_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN11_A { + match self.bits { + false => PIN11_A::INPUT, + true => PIN11_A::OUTPUT, + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == PIN11_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == PIN11_A::OUTPUT + } +} +#[doc = "Set as input pin 11\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN11_AW { + #[doc = "1: Write: writing a '1' sets pin to input; writing a '0' has no effect"] + CLEAR = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN11_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PIN11` writer - Set as input pin 11"] +pub type PIN11_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DIRCLR_SPEC, PIN11_AW, O>; +impl<'a, const O: u8> PIN11_W<'a, O> { + #[doc = "Write: writing a '1' sets pin to input; writing a '0' has no effect"] + #[inline(always)] + pub fn clear(self) -> &'a mut W { + self.variant(PIN11_AW::CLEAR) + } +} +#[doc = "Field `PIN12` reader - Set as input pin 12"] +pub type PIN12_R = crate::BitReader; +#[doc = "Set as input pin 12\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN12_A { + #[doc = "0: Read: pin set as input"] + INPUT = 0, + #[doc = "1: Read: pin set as output"] + OUTPUT = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN12_A) -> Self { + variant as u8 != 0 + } +} +impl PIN12_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN12_A { + match self.bits { + false => PIN12_A::INPUT, + true => PIN12_A::OUTPUT, + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == PIN12_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == PIN12_A::OUTPUT + } +} +#[doc = "Set as input pin 12\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN12_AW { + #[doc = "1: Write: writing a '1' sets pin to input; writing a '0' has no effect"] + CLEAR = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN12_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PIN12` writer - Set as input pin 12"] +pub type PIN12_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DIRCLR_SPEC, PIN12_AW, O>; +impl<'a, const O: u8> PIN12_W<'a, O> { + #[doc = "Write: writing a '1' sets pin to input; writing a '0' has no effect"] + #[inline(always)] + pub fn clear(self) -> &'a mut W { + self.variant(PIN12_AW::CLEAR) + } +} +#[doc = "Field `PIN13` reader - Set as input pin 13"] +pub type PIN13_R = crate::BitReader; +#[doc = "Set as input pin 13\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN13_A { + #[doc = "0: Read: pin set as input"] + INPUT = 0, + #[doc = "1: Read: pin set as output"] + OUTPUT = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN13_A) -> Self { + variant as u8 != 0 + } +} +impl PIN13_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN13_A { + match self.bits { + false => PIN13_A::INPUT, + true => PIN13_A::OUTPUT, + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == PIN13_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == PIN13_A::OUTPUT + } +} +#[doc = "Set as input pin 13\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN13_AW { + #[doc = "1: Write: writing a '1' sets pin to input; writing a '0' has no effect"] + CLEAR = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN13_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PIN13` writer - Set as input pin 13"] +pub type PIN13_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DIRCLR_SPEC, PIN13_AW, O>; +impl<'a, const O: u8> PIN13_W<'a, O> { + #[doc = "Write: writing a '1' sets pin to input; writing a '0' has no effect"] + #[inline(always)] + pub fn clear(self) -> &'a mut W { + self.variant(PIN13_AW::CLEAR) + } +} +#[doc = "Field `PIN14` reader - Set as input pin 14"] +pub type PIN14_R = crate::BitReader; +#[doc = "Set as input pin 14\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN14_A { + #[doc = "0: Read: pin set as input"] + INPUT = 0, + #[doc = "1: Read: pin set as output"] + OUTPUT = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN14_A) -> Self { + variant as u8 != 0 + } +} +impl PIN14_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN14_A { + match self.bits { + false => PIN14_A::INPUT, + true => PIN14_A::OUTPUT, + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == PIN14_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == PIN14_A::OUTPUT + } +} +#[doc = "Set as input pin 14\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN14_AW { + #[doc = "1: Write: writing a '1' sets pin to input; writing a '0' has no effect"] + CLEAR = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN14_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PIN14` writer - Set as input pin 14"] +pub type PIN14_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DIRCLR_SPEC, PIN14_AW, O>; +impl<'a, const O: u8> PIN14_W<'a, O> { + #[doc = "Write: writing a '1' sets pin to input; writing a '0' has no effect"] + #[inline(always)] + pub fn clear(self) -> &'a mut W { + self.variant(PIN14_AW::CLEAR) + } +} +#[doc = "Field `PIN15` reader - Set as input pin 15"] +pub type PIN15_R = crate::BitReader; +#[doc = "Set as input pin 15\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN15_A { + #[doc = "0: Read: pin set as input"] + INPUT = 0, + #[doc = "1: Read: pin set as output"] + OUTPUT = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN15_A) -> Self { + variant as u8 != 0 + } +} +impl PIN15_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN15_A { + match self.bits { + false => PIN15_A::INPUT, + true => PIN15_A::OUTPUT, + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == PIN15_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == PIN15_A::OUTPUT + } +} +#[doc = "Set as input pin 15\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN15_AW { + #[doc = "1: Write: writing a '1' sets pin to input; writing a '0' has no effect"] + CLEAR = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN15_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PIN15` writer - Set as input pin 15"] +pub type PIN15_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DIRCLR_SPEC, PIN15_AW, O>; +impl<'a, const O: u8> PIN15_W<'a, O> { + #[doc = "Write: writing a '1' sets pin to input; writing a '0' has no effect"] + #[inline(always)] + pub fn clear(self) -> &'a mut W { + self.variant(PIN15_AW::CLEAR) + } +} +#[doc = "Field `PIN16` reader - Set as input pin 16"] +pub type PIN16_R = crate::BitReader; +#[doc = "Set as input pin 16\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN16_A { + #[doc = "0: Read: pin set as input"] + INPUT = 0, + #[doc = "1: Read: pin set as output"] + OUTPUT = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN16_A) -> Self { + variant as u8 != 0 + } +} +impl PIN16_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN16_A { + match self.bits { + false => PIN16_A::INPUT, + true => PIN16_A::OUTPUT, + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == PIN16_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == PIN16_A::OUTPUT + } +} +#[doc = "Set as input pin 16\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN16_AW { + #[doc = "1: Write: writing a '1' sets pin to input; writing a '0' has no effect"] + CLEAR = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN16_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PIN16` writer - Set as input pin 16"] +pub type PIN16_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DIRCLR_SPEC, PIN16_AW, O>; +impl<'a, const O: u8> PIN16_W<'a, O> { + #[doc = "Write: writing a '1' sets pin to input; writing a '0' has no effect"] + #[inline(always)] + pub fn clear(self) -> &'a mut W { + self.variant(PIN16_AW::CLEAR) + } +} +#[doc = "Field `PIN17` reader - Set as input pin 17"] +pub type PIN17_R = crate::BitReader; +#[doc = "Set as input pin 17\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN17_A { + #[doc = "0: Read: pin set as input"] + INPUT = 0, + #[doc = "1: Read: pin set as output"] + OUTPUT = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN17_A) -> Self { + variant as u8 != 0 + } +} +impl PIN17_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN17_A { + match self.bits { + false => PIN17_A::INPUT, + true => PIN17_A::OUTPUT, + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == PIN17_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == PIN17_A::OUTPUT + } +} +#[doc = "Set as input pin 17\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN17_AW { + #[doc = "1: Write: writing a '1' sets pin to input; writing a '0' has no effect"] + CLEAR = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN17_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PIN17` writer - Set as input pin 17"] +pub type PIN17_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DIRCLR_SPEC, PIN17_AW, O>; +impl<'a, const O: u8> PIN17_W<'a, O> { + #[doc = "Write: writing a '1' sets pin to input; writing a '0' has no effect"] + #[inline(always)] + pub fn clear(self) -> &'a mut W { + self.variant(PIN17_AW::CLEAR) + } +} +#[doc = "Field `PIN18` reader - Set as input pin 18"] +pub type PIN18_R = crate::BitReader; +#[doc = "Set as input pin 18\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN18_A { + #[doc = "0: Read: pin set as input"] + INPUT = 0, + #[doc = "1: Read: pin set as output"] + OUTPUT = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN18_A) -> Self { + variant as u8 != 0 + } +} +impl PIN18_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN18_A { + match self.bits { + false => PIN18_A::INPUT, + true => PIN18_A::OUTPUT, + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == PIN18_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == PIN18_A::OUTPUT + } +} +#[doc = "Set as input pin 18\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN18_AW { + #[doc = "1: Write: writing a '1' sets pin to input; writing a '0' has no effect"] + CLEAR = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN18_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PIN18` writer - Set as input pin 18"] +pub type PIN18_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DIRCLR_SPEC, PIN18_AW, O>; +impl<'a, const O: u8> PIN18_W<'a, O> { + #[doc = "Write: writing a '1' sets pin to input; writing a '0' has no effect"] + #[inline(always)] + pub fn clear(self) -> &'a mut W { + self.variant(PIN18_AW::CLEAR) + } +} +#[doc = "Field `PIN19` reader - Set as input pin 19"] +pub type PIN19_R = crate::BitReader; +#[doc = "Set as input pin 19\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN19_A { + #[doc = "0: Read: pin set as input"] + INPUT = 0, + #[doc = "1: Read: pin set as output"] + OUTPUT = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN19_A) -> Self { + variant as u8 != 0 + } +} +impl PIN19_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN19_A { + match self.bits { + false => PIN19_A::INPUT, + true => PIN19_A::OUTPUT, + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == PIN19_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == PIN19_A::OUTPUT + } +} +#[doc = "Set as input pin 19\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN19_AW { + #[doc = "1: Write: writing a '1' sets pin to input; writing a '0' has no effect"] + CLEAR = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN19_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PIN19` writer - Set as input pin 19"] +pub type PIN19_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DIRCLR_SPEC, PIN19_AW, O>; +impl<'a, const O: u8> PIN19_W<'a, O> { + #[doc = "Write: writing a '1' sets pin to input; writing a '0' has no effect"] + #[inline(always)] + pub fn clear(self) -> &'a mut W { + self.variant(PIN19_AW::CLEAR) + } +} +#[doc = "Field `PIN20` reader - Set as input pin 20"] +pub type PIN20_R = crate::BitReader; +#[doc = "Set as input pin 20\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN20_A { + #[doc = "0: Read: pin set as input"] + INPUT = 0, + #[doc = "1: Read: pin set as output"] + OUTPUT = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN20_A) -> Self { + variant as u8 != 0 + } +} +impl PIN20_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN20_A { + match self.bits { + false => PIN20_A::INPUT, + true => PIN20_A::OUTPUT, + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == PIN20_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == PIN20_A::OUTPUT + } +} +#[doc = "Set as input pin 20\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN20_AW { + #[doc = "1: Write: writing a '1' sets pin to input; writing a '0' has no effect"] + CLEAR = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN20_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PIN20` writer - Set as input pin 20"] +pub type PIN20_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DIRCLR_SPEC, PIN20_AW, O>; +impl<'a, const O: u8> PIN20_W<'a, O> { + #[doc = "Write: writing a '1' sets pin to input; writing a '0' has no effect"] + #[inline(always)] + pub fn clear(self) -> &'a mut W { + self.variant(PIN20_AW::CLEAR) + } +} +#[doc = "Field `PIN21` reader - Set as input pin 21"] +pub type PIN21_R = crate::BitReader; +#[doc = "Set as input pin 21\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN21_A { + #[doc = "0: Read: pin set as input"] + INPUT = 0, + #[doc = "1: Read: pin set as output"] + OUTPUT = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN21_A) -> Self { + variant as u8 != 0 + } +} +impl PIN21_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN21_A { + match self.bits { + false => PIN21_A::INPUT, + true => PIN21_A::OUTPUT, + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == PIN21_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == PIN21_A::OUTPUT + } +} +#[doc = "Set as input pin 21\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN21_AW { + #[doc = "1: Write: writing a '1' sets pin to input; writing a '0' has no effect"] + CLEAR = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN21_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PIN21` writer - Set as input pin 21"] +pub type PIN21_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DIRCLR_SPEC, PIN21_AW, O>; +impl<'a, const O: u8> PIN21_W<'a, O> { + #[doc = "Write: writing a '1' sets pin to input; writing a '0' has no effect"] + #[inline(always)] + pub fn clear(self) -> &'a mut W { + self.variant(PIN21_AW::CLEAR) + } +} +#[doc = "Field `PIN22` reader - Set as input pin 22"] +pub type PIN22_R = crate::BitReader; +#[doc = "Set as input pin 22\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN22_A { + #[doc = "0: Read: pin set as input"] + INPUT = 0, + #[doc = "1: Read: pin set as output"] + OUTPUT = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN22_A) -> Self { + variant as u8 != 0 + } +} +impl PIN22_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN22_A { + match self.bits { + false => PIN22_A::INPUT, + true => PIN22_A::OUTPUT, + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == PIN22_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == PIN22_A::OUTPUT + } +} +#[doc = "Set as input pin 22\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN22_AW { + #[doc = "1: Write: writing a '1' sets pin to input; writing a '0' has no effect"] + CLEAR = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN22_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PIN22` writer - Set as input pin 22"] +pub type PIN22_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DIRCLR_SPEC, PIN22_AW, O>; +impl<'a, const O: u8> PIN22_W<'a, O> { + #[doc = "Write: writing a '1' sets pin to input; writing a '0' has no effect"] + #[inline(always)] + pub fn clear(self) -> &'a mut W { + self.variant(PIN22_AW::CLEAR) + } +} +#[doc = "Field `PIN23` reader - Set as input pin 23"] +pub type PIN23_R = crate::BitReader; +#[doc = "Set as input pin 23\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN23_A { + #[doc = "0: Read: pin set as input"] + INPUT = 0, + #[doc = "1: Read: pin set as output"] + OUTPUT = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN23_A) -> Self { + variant as u8 != 0 + } +} +impl PIN23_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN23_A { + match self.bits { + false => PIN23_A::INPUT, + true => PIN23_A::OUTPUT, + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == PIN23_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == PIN23_A::OUTPUT + } +} +#[doc = "Set as input pin 23\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN23_AW { + #[doc = "1: Write: writing a '1' sets pin to input; writing a '0' has no effect"] + CLEAR = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN23_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PIN23` writer - Set as input pin 23"] +pub type PIN23_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DIRCLR_SPEC, PIN23_AW, O>; +impl<'a, const O: u8> PIN23_W<'a, O> { + #[doc = "Write: writing a '1' sets pin to input; writing a '0' has no effect"] + #[inline(always)] + pub fn clear(self) -> &'a mut W { + self.variant(PIN23_AW::CLEAR) + } +} +#[doc = "Field `PIN24` reader - Set as input pin 24"] +pub type PIN24_R = crate::BitReader; +#[doc = "Set as input pin 24\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN24_A { + #[doc = "0: Read: pin set as input"] + INPUT = 0, + #[doc = "1: Read: pin set as output"] + OUTPUT = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN24_A) -> Self { + variant as u8 != 0 + } +} +impl PIN24_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN24_A { + match self.bits { + false => PIN24_A::INPUT, + true => PIN24_A::OUTPUT, + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == PIN24_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == PIN24_A::OUTPUT + } +} +#[doc = "Set as input pin 24\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN24_AW { + #[doc = "1: Write: writing a '1' sets pin to input; writing a '0' has no effect"] + CLEAR = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN24_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PIN24` writer - Set as input pin 24"] +pub type PIN24_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DIRCLR_SPEC, PIN24_AW, O>; +impl<'a, const O: u8> PIN24_W<'a, O> { + #[doc = "Write: writing a '1' sets pin to input; writing a '0' has no effect"] + #[inline(always)] + pub fn clear(self) -> &'a mut W { + self.variant(PIN24_AW::CLEAR) + } +} +#[doc = "Field `PIN25` reader - Set as input pin 25"] +pub type PIN25_R = crate::BitReader; +#[doc = "Set as input pin 25\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN25_A { + #[doc = "0: Read: pin set as input"] + INPUT = 0, + #[doc = "1: Read: pin set as output"] + OUTPUT = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN25_A) -> Self { + variant as u8 != 0 + } +} +impl PIN25_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN25_A { + match self.bits { + false => PIN25_A::INPUT, + true => PIN25_A::OUTPUT, + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == PIN25_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == PIN25_A::OUTPUT + } +} +#[doc = "Set as input pin 25\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN25_AW { + #[doc = "1: Write: writing a '1' sets pin to input; writing a '0' has no effect"] + CLEAR = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN25_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PIN25` writer - Set as input pin 25"] +pub type PIN25_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DIRCLR_SPEC, PIN25_AW, O>; +impl<'a, const O: u8> PIN25_W<'a, O> { + #[doc = "Write: writing a '1' sets pin to input; writing a '0' has no effect"] + #[inline(always)] + pub fn clear(self) -> &'a mut W { + self.variant(PIN25_AW::CLEAR) + } +} +#[doc = "Field `PIN26` reader - Set as input pin 26"] +pub type PIN26_R = crate::BitReader; +#[doc = "Set as input pin 26\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN26_A { + #[doc = "0: Read: pin set as input"] + INPUT = 0, + #[doc = "1: Read: pin set as output"] + OUTPUT = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN26_A) -> Self { + variant as u8 != 0 + } +} +impl PIN26_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN26_A { + match self.bits { + false => PIN26_A::INPUT, + true => PIN26_A::OUTPUT, + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == PIN26_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == PIN26_A::OUTPUT + } +} +#[doc = "Set as input pin 26\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN26_AW { + #[doc = "1: Write: writing a '1' sets pin to input; writing a '0' has no effect"] + CLEAR = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN26_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PIN26` writer - Set as input pin 26"] +pub type PIN26_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DIRCLR_SPEC, PIN26_AW, O>; +impl<'a, const O: u8> PIN26_W<'a, O> { + #[doc = "Write: writing a '1' sets pin to input; writing a '0' has no effect"] + #[inline(always)] + pub fn clear(self) -> &'a mut W { + self.variant(PIN26_AW::CLEAR) + } +} +#[doc = "Field `PIN27` reader - Set as input pin 27"] +pub type PIN27_R = crate::BitReader; +#[doc = "Set as input pin 27\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN27_A { + #[doc = "0: Read: pin set as input"] + INPUT = 0, + #[doc = "1: Read: pin set as output"] + OUTPUT = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN27_A) -> Self { + variant as u8 != 0 + } +} +impl PIN27_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN27_A { + match self.bits { + false => PIN27_A::INPUT, + true => PIN27_A::OUTPUT, + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == PIN27_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == PIN27_A::OUTPUT + } +} +#[doc = "Set as input pin 27\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN27_AW { + #[doc = "1: Write: writing a '1' sets pin to input; writing a '0' has no effect"] + CLEAR = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN27_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PIN27` writer - Set as input pin 27"] +pub type PIN27_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DIRCLR_SPEC, PIN27_AW, O>; +impl<'a, const O: u8> PIN27_W<'a, O> { + #[doc = "Write: writing a '1' sets pin to input; writing a '0' has no effect"] + #[inline(always)] + pub fn clear(self) -> &'a mut W { + self.variant(PIN27_AW::CLEAR) + } +} +#[doc = "Field `PIN28` reader - Set as input pin 28"] +pub type PIN28_R = crate::BitReader; +#[doc = "Set as input pin 28\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN28_A { + #[doc = "0: Read: pin set as input"] + INPUT = 0, + #[doc = "1: Read: pin set as output"] + OUTPUT = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN28_A) -> Self { + variant as u8 != 0 + } +} +impl PIN28_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN28_A { + match self.bits { + false => PIN28_A::INPUT, + true => PIN28_A::OUTPUT, + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == PIN28_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == PIN28_A::OUTPUT + } +} +#[doc = "Set as input pin 28\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN28_AW { + #[doc = "1: Write: writing a '1' sets pin to input; writing a '0' has no effect"] + CLEAR = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN28_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PIN28` writer - Set as input pin 28"] +pub type PIN28_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DIRCLR_SPEC, PIN28_AW, O>; +impl<'a, const O: u8> PIN28_W<'a, O> { + #[doc = "Write: writing a '1' sets pin to input; writing a '0' has no effect"] + #[inline(always)] + pub fn clear(self) -> &'a mut W { + self.variant(PIN28_AW::CLEAR) + } +} +#[doc = "Field `PIN29` reader - Set as input pin 29"] +pub type PIN29_R = crate::BitReader; +#[doc = "Set as input pin 29\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN29_A { + #[doc = "0: Read: pin set as input"] + INPUT = 0, + #[doc = "1: Read: pin set as output"] + OUTPUT = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN29_A) -> Self { + variant as u8 != 0 + } +} +impl PIN29_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN29_A { + match self.bits { + false => PIN29_A::INPUT, + true => PIN29_A::OUTPUT, + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == PIN29_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == PIN29_A::OUTPUT + } +} +#[doc = "Set as input pin 29\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN29_AW { + #[doc = "1: Write: writing a '1' sets pin to input; writing a '0' has no effect"] + CLEAR = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN29_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PIN29` writer - Set as input pin 29"] +pub type PIN29_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DIRCLR_SPEC, PIN29_AW, O>; +impl<'a, const O: u8> PIN29_W<'a, O> { + #[doc = "Write: writing a '1' sets pin to input; writing a '0' has no effect"] + #[inline(always)] + pub fn clear(self) -> &'a mut W { + self.variant(PIN29_AW::CLEAR) + } +} +#[doc = "Field `PIN30` reader - Set as input pin 30"] +pub type PIN30_R = crate::BitReader; +#[doc = "Set as input pin 30\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN30_A { + #[doc = "0: Read: pin set as input"] + INPUT = 0, + #[doc = "1: Read: pin set as output"] + OUTPUT = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN30_A) -> Self { + variant as u8 != 0 + } +} +impl PIN30_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN30_A { + match self.bits { + false => PIN30_A::INPUT, + true => PIN30_A::OUTPUT, + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == PIN30_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == PIN30_A::OUTPUT + } +} +#[doc = "Set as input pin 30\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN30_AW { + #[doc = "1: Write: writing a '1' sets pin to input; writing a '0' has no effect"] + CLEAR = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN30_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PIN30` writer - Set as input pin 30"] +pub type PIN30_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DIRCLR_SPEC, PIN30_AW, O>; +impl<'a, const O: u8> PIN30_W<'a, O> { + #[doc = "Write: writing a '1' sets pin to input; writing a '0' has no effect"] + #[inline(always)] + pub fn clear(self) -> &'a mut W { + self.variant(PIN30_AW::CLEAR) + } +} +#[doc = "Field `PIN31` reader - Set as input pin 31"] +pub type PIN31_R = crate::BitReader; +#[doc = "Set as input pin 31\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN31_A { + #[doc = "0: Read: pin set as input"] + INPUT = 0, + #[doc = "1: Read: pin set as output"] + OUTPUT = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN31_A) -> Self { + variant as u8 != 0 + } +} +impl PIN31_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN31_A { + match self.bits { + false => PIN31_A::INPUT, + true => PIN31_A::OUTPUT, + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == PIN31_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == PIN31_A::OUTPUT + } +} +#[doc = "Set as input pin 31\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN31_AW { + #[doc = "1: Write: writing a '1' sets pin to input; writing a '0' has no effect"] + CLEAR = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN31_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PIN31` writer - Set as input pin 31"] +pub type PIN31_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DIRCLR_SPEC, PIN31_AW, O>; +impl<'a, const O: u8> PIN31_W<'a, O> { + #[doc = "Write: writing a '1' sets pin to input; writing a '0' has no effect"] + #[inline(always)] + pub fn clear(self) -> &'a mut W { + self.variant(PIN31_AW::CLEAR) + } +} +impl R { + #[doc = "Bit 0 - Set as input pin 0"] + #[inline(always)] + pub fn pin0(&self) -> PIN0_R { + PIN0_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Set as input pin 1"] + #[inline(always)] + pub fn pin1(&self) -> PIN1_R { + PIN1_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Set as input pin 2"] + #[inline(always)] + pub fn pin2(&self) -> PIN2_R { + PIN2_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Set as input pin 3"] + #[inline(always)] + pub fn pin3(&self) -> PIN3_R { + PIN3_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Set as input pin 4"] + #[inline(always)] + pub fn pin4(&self) -> PIN4_R { + PIN4_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Set as input pin 5"] + #[inline(always)] + pub fn pin5(&self) -> PIN5_R { + PIN5_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Set as input pin 6"] + #[inline(always)] + pub fn pin6(&self) -> PIN6_R { + PIN6_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Set as input pin 7"] + #[inline(always)] + pub fn pin7(&self) -> PIN7_R { + PIN7_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Set as input pin 8"] + #[inline(always)] + pub fn pin8(&self) -> PIN8_R { + PIN8_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Set as input pin 9"] + #[inline(always)] + pub fn pin9(&self) -> PIN9_R { + PIN9_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Set as input pin 10"] + #[inline(always)] + pub fn pin10(&self) -> PIN10_R { + PIN10_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Set as input pin 11"] + #[inline(always)] + pub fn pin11(&self) -> PIN11_R { + PIN11_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Set as input pin 12"] + #[inline(always)] + pub fn pin12(&self) -> PIN12_R { + PIN12_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Set as input pin 13"] + #[inline(always)] + pub fn pin13(&self) -> PIN13_R { + PIN13_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Set as input pin 14"] + #[inline(always)] + pub fn pin14(&self) -> PIN14_R { + PIN14_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Set as input pin 15"] + #[inline(always)] + pub fn pin15(&self) -> PIN15_R { + PIN15_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - Set as input pin 16"] + #[inline(always)] + pub fn pin16(&self) -> PIN16_R { + PIN16_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Set as input pin 17"] + #[inline(always)] + pub fn pin17(&self) -> PIN17_R { + PIN17_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Set as input pin 18"] + #[inline(always)] + pub fn pin18(&self) -> PIN18_R { + PIN18_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Set as input pin 19"] + #[inline(always)] + pub fn pin19(&self) -> PIN19_R { + PIN19_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Set as input pin 20"] + #[inline(always)] + pub fn pin20(&self) -> PIN20_R { + PIN20_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Set as input pin 21"] + #[inline(always)] + pub fn pin21(&self) -> PIN21_R { + PIN21_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Set as input pin 22"] + #[inline(always)] + pub fn pin22(&self) -> PIN22_R { + PIN22_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - Set as input pin 23"] + #[inline(always)] + pub fn pin23(&self) -> PIN23_R { + PIN23_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - Set as input pin 24"] + #[inline(always)] + pub fn pin24(&self) -> PIN24_R { + PIN24_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - Set as input pin 25"] + #[inline(always)] + pub fn pin25(&self) -> PIN25_R { + PIN25_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - Set as input pin 26"] + #[inline(always)] + pub fn pin26(&self) -> PIN26_R { + PIN26_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - Set as input pin 27"] + #[inline(always)] + pub fn pin27(&self) -> PIN27_R { + PIN27_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - Set as input pin 28"] + #[inline(always)] + pub fn pin28(&self) -> PIN28_R { + PIN28_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - Set as input pin 29"] + #[inline(always)] + pub fn pin29(&self) -> PIN29_R { + PIN29_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Set as input pin 30"] + #[inline(always)] + pub fn pin30(&self) -> PIN30_R { + PIN30_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Set as input pin 31"] + #[inline(always)] + pub fn pin31(&self) -> PIN31_R { + PIN31_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Set as input pin 0"] + #[inline(always)] + pub fn pin0(&mut self) -> PIN0_W<0> { + PIN0_W::new(self) + } + #[doc = "Bit 1 - Set as input pin 1"] + #[inline(always)] + pub fn pin1(&mut self) -> PIN1_W<1> { + PIN1_W::new(self) + } + #[doc = "Bit 2 - Set as input pin 2"] + #[inline(always)] + pub fn pin2(&mut self) -> PIN2_W<2> { + PIN2_W::new(self) + } + #[doc = "Bit 3 - Set as input pin 3"] + #[inline(always)] + pub fn pin3(&mut self) -> PIN3_W<3> { + PIN3_W::new(self) + } + #[doc = "Bit 4 - Set as input pin 4"] + #[inline(always)] + pub fn pin4(&mut self) -> PIN4_W<4> { + PIN4_W::new(self) + } + #[doc = "Bit 5 - Set as input pin 5"] + #[inline(always)] + pub fn pin5(&mut self) -> PIN5_W<5> { + PIN5_W::new(self) + } + #[doc = "Bit 6 - Set as input pin 6"] + #[inline(always)] + pub fn pin6(&mut self) -> PIN6_W<6> { + PIN6_W::new(self) + } + #[doc = "Bit 7 - Set as input pin 7"] + #[inline(always)] + pub fn pin7(&mut self) -> PIN7_W<7> { + PIN7_W::new(self) + } + #[doc = "Bit 8 - Set as input pin 8"] + #[inline(always)] + pub fn pin8(&mut self) -> PIN8_W<8> { + PIN8_W::new(self) + } + #[doc = "Bit 9 - Set as input pin 9"] + #[inline(always)] + pub fn pin9(&mut self) -> PIN9_W<9> { + PIN9_W::new(self) + } + #[doc = "Bit 10 - Set as input pin 10"] + #[inline(always)] + pub fn pin10(&mut self) -> PIN10_W<10> { + PIN10_W::new(self) + } + #[doc = "Bit 11 - Set as input pin 11"] + #[inline(always)] + pub fn pin11(&mut self) -> PIN11_W<11> { + PIN11_W::new(self) + } + #[doc = "Bit 12 - Set as input pin 12"] + #[inline(always)] + pub fn pin12(&mut self) -> PIN12_W<12> { + PIN12_W::new(self) + } + #[doc = "Bit 13 - Set as input pin 13"] + #[inline(always)] + pub fn pin13(&mut self) -> PIN13_W<13> { + PIN13_W::new(self) + } + #[doc = "Bit 14 - Set as input pin 14"] + #[inline(always)] + pub fn pin14(&mut self) -> PIN14_W<14> { + PIN14_W::new(self) + } + #[doc = "Bit 15 - Set as input pin 15"] + #[inline(always)] + pub fn pin15(&mut self) -> PIN15_W<15> { + PIN15_W::new(self) + } + #[doc = "Bit 16 - Set as input pin 16"] + #[inline(always)] + pub fn pin16(&mut self) -> PIN16_W<16> { + PIN16_W::new(self) + } + #[doc = "Bit 17 - Set as input pin 17"] + #[inline(always)] + pub fn pin17(&mut self) -> PIN17_W<17> { + PIN17_W::new(self) + } + #[doc = "Bit 18 - Set as input pin 18"] + #[inline(always)] + pub fn pin18(&mut self) -> PIN18_W<18> { + PIN18_W::new(self) + } + #[doc = "Bit 19 - Set as input pin 19"] + #[inline(always)] + pub fn pin19(&mut self) -> PIN19_W<19> { + PIN19_W::new(self) + } + #[doc = "Bit 20 - Set as input pin 20"] + #[inline(always)] + pub fn pin20(&mut self) -> PIN20_W<20> { + PIN20_W::new(self) + } + #[doc = "Bit 21 - Set as input pin 21"] + #[inline(always)] + pub fn pin21(&mut self) -> PIN21_W<21> { + PIN21_W::new(self) + } + #[doc = "Bit 22 - Set as input pin 22"] + #[inline(always)] + pub fn pin22(&mut self) -> PIN22_W<22> { + PIN22_W::new(self) + } + #[doc = "Bit 23 - Set as input pin 23"] + #[inline(always)] + pub fn pin23(&mut self) -> PIN23_W<23> { + PIN23_W::new(self) + } + #[doc = "Bit 24 - Set as input pin 24"] + #[inline(always)] + pub fn pin24(&mut self) -> PIN24_W<24> { + PIN24_W::new(self) + } + #[doc = "Bit 25 - Set as input pin 25"] + #[inline(always)] + pub fn pin25(&mut self) -> PIN25_W<25> { + PIN25_W::new(self) + } + #[doc = "Bit 26 - Set as input pin 26"] + #[inline(always)] + pub fn pin26(&mut self) -> PIN26_W<26> { + PIN26_W::new(self) + } + #[doc = "Bit 27 - Set as input pin 27"] + #[inline(always)] + pub fn pin27(&mut self) -> PIN27_W<27> { + PIN27_W::new(self) + } + #[doc = "Bit 28 - Set as input pin 28"] + #[inline(always)] + pub fn pin28(&mut self) -> PIN28_W<28> { + PIN28_W::new(self) + } + #[doc = "Bit 29 - Set as input pin 29"] + #[inline(always)] + pub fn pin29(&mut self) -> PIN29_W<29> { + PIN29_W::new(self) + } + #[doc = "Bit 30 - Set as input pin 30"] + #[inline(always)] + pub fn pin30(&mut self) -> PIN30_W<30> { + PIN30_W::new(self) + } + #[doc = "Bit 31 - Set as input pin 31"] + #[inline(always)] + pub fn pin31(&mut self) -> PIN31_W<31> { + PIN31_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "DIR clear register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dirclr](index.html) module"] +pub struct DIRCLR_SPEC; +impl crate::RegisterSpec for DIRCLR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dirclr::R](R) reader structure"] +impl crate::Readable for DIRCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dirclr::W](W) writer structure"] +impl crate::Writable for DIRCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DIRCLR to value 0"] +impl crate::Resettable for DIRCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/p0_ns/dirset.rs b/pacs/nrf9120-pac/src/p0_ns/dirset.rs new file mode 100644 index 00000000..f0fd06b3 --- /dev/null +++ b/pacs/nrf9120-pac/src/p0_ns/dirset.rs @@ -0,0 +1,2210 @@ +#[doc = "Register `DIRSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DIRSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PIN0` reader - Set as output pin 0"] +pub type PIN0_R = crate::BitReader; +#[doc = "Set as output pin 0\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN0_A { + #[doc = "0: Read: pin set as input"] + INPUT = 0, + #[doc = "1: Read: pin set as output"] + OUTPUT = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN0_A) -> Self { + variant as u8 != 0 + } +} +impl PIN0_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN0_A { + match self.bits { + false => PIN0_A::INPUT, + true => PIN0_A::OUTPUT, + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == PIN0_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == PIN0_A::OUTPUT + } +} +#[doc = "Set as output pin 0\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN0_AW { + #[doc = "1: Write: writing a '1' sets pin to output; writing a '0' has no effect"] + SET = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN0_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PIN0` writer - Set as output pin 0"] +pub type PIN0_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, DIRSET_SPEC, PIN0_AW, O>; +impl<'a, const O: u8> PIN0_W<'a, O> { + #[doc = "Write: writing a '1' sets pin to output; writing a '0' has no effect"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(PIN0_AW::SET) + } +} +#[doc = "Field `PIN1` reader - Set as output pin 1"] +pub type PIN1_R = crate::BitReader; +#[doc = "Set as output pin 1\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN1_A { + #[doc = "0: Read: pin set as input"] + INPUT = 0, + #[doc = "1: Read: pin set as output"] + OUTPUT = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN1_A) -> Self { + variant as u8 != 0 + } +} +impl PIN1_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN1_A { + match self.bits { + false => PIN1_A::INPUT, + true => PIN1_A::OUTPUT, + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == PIN1_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == PIN1_A::OUTPUT + } +} +#[doc = "Set as output pin 1\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN1_AW { + #[doc = "1: Write: writing a '1' sets pin to output; writing a '0' has no effect"] + SET = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN1_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PIN1` writer - Set as output pin 1"] +pub type PIN1_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, DIRSET_SPEC, PIN1_AW, O>; +impl<'a, const O: u8> PIN1_W<'a, O> { + #[doc = "Write: writing a '1' sets pin to output; writing a '0' has no effect"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(PIN1_AW::SET) + } +} +#[doc = "Field `PIN2` reader - Set as output pin 2"] +pub type PIN2_R = crate::BitReader; +#[doc = "Set as output pin 2\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN2_A { + #[doc = "0: Read: pin set as input"] + INPUT = 0, + #[doc = "1: Read: pin set as output"] + OUTPUT = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN2_A) -> Self { + variant as u8 != 0 + } +} +impl PIN2_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN2_A { + match self.bits { + false => PIN2_A::INPUT, + true => PIN2_A::OUTPUT, + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == PIN2_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == PIN2_A::OUTPUT + } +} +#[doc = "Set as output pin 2\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN2_AW { + #[doc = "1: Write: writing a '1' sets pin to output; writing a '0' has no effect"] + SET = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN2_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PIN2` writer - Set as output pin 2"] +pub type PIN2_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, DIRSET_SPEC, PIN2_AW, O>; +impl<'a, const O: u8> PIN2_W<'a, O> { + #[doc = "Write: writing a '1' sets pin to output; writing a '0' has no effect"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(PIN2_AW::SET) + } +} +#[doc = "Field `PIN3` reader - Set as output pin 3"] +pub type PIN3_R = crate::BitReader; +#[doc = "Set as output pin 3\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN3_A { + #[doc = "0: Read: pin set as input"] + INPUT = 0, + #[doc = "1: Read: pin set as output"] + OUTPUT = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN3_A) -> Self { + variant as u8 != 0 + } +} +impl PIN3_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN3_A { + match self.bits { + false => PIN3_A::INPUT, + true => PIN3_A::OUTPUT, + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == PIN3_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == PIN3_A::OUTPUT + } +} +#[doc = "Set as output pin 3\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN3_AW { + #[doc = "1: Write: writing a '1' sets pin to output; writing a '0' has no effect"] + SET = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN3_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PIN3` writer - Set as output pin 3"] +pub type PIN3_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, DIRSET_SPEC, PIN3_AW, O>; +impl<'a, const O: u8> PIN3_W<'a, O> { + #[doc = "Write: writing a '1' sets pin to output; writing a '0' has no effect"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(PIN3_AW::SET) + } +} +#[doc = "Field `PIN4` reader - Set as output pin 4"] +pub type PIN4_R = crate::BitReader; +#[doc = "Set as output pin 4\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN4_A { + #[doc = "0: Read: pin set as input"] + INPUT = 0, + #[doc = "1: Read: pin set as output"] + OUTPUT = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN4_A) -> Self { + variant as u8 != 0 + } +} +impl PIN4_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN4_A { + match self.bits { + false => PIN4_A::INPUT, + true => PIN4_A::OUTPUT, + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == PIN4_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == PIN4_A::OUTPUT + } +} +#[doc = "Set as output pin 4\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN4_AW { + #[doc = "1: Write: writing a '1' sets pin to output; writing a '0' has no effect"] + SET = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN4_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PIN4` writer - Set as output pin 4"] +pub type PIN4_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, DIRSET_SPEC, PIN4_AW, O>; +impl<'a, const O: u8> PIN4_W<'a, O> { + #[doc = "Write: writing a '1' sets pin to output; writing a '0' has no effect"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(PIN4_AW::SET) + } +} +#[doc = "Field `PIN5` reader - Set as output pin 5"] +pub type PIN5_R = crate::BitReader; +#[doc = "Set as output pin 5\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN5_A { + #[doc = "0: Read: pin set as input"] + INPUT = 0, + #[doc = "1: Read: pin set as output"] + OUTPUT = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN5_A) -> Self { + variant as u8 != 0 + } +} +impl PIN5_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN5_A { + match self.bits { + false => PIN5_A::INPUT, + true => PIN5_A::OUTPUT, + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == PIN5_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == PIN5_A::OUTPUT + } +} +#[doc = "Set as output pin 5\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN5_AW { + #[doc = "1: Write: writing a '1' sets pin to output; writing a '0' has no effect"] + SET = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN5_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PIN5` writer - Set as output pin 5"] +pub type PIN5_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, DIRSET_SPEC, PIN5_AW, O>; +impl<'a, const O: u8> PIN5_W<'a, O> { + #[doc = "Write: writing a '1' sets pin to output; writing a '0' has no effect"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(PIN5_AW::SET) + } +} +#[doc = "Field `PIN6` reader - Set as output pin 6"] +pub type PIN6_R = crate::BitReader; +#[doc = "Set as output pin 6\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN6_A { + #[doc = "0: Read: pin set as input"] + INPUT = 0, + #[doc = "1: Read: pin set as output"] + OUTPUT = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN6_A) -> Self { + variant as u8 != 0 + } +} +impl PIN6_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN6_A { + match self.bits { + false => PIN6_A::INPUT, + true => PIN6_A::OUTPUT, + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == PIN6_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == PIN6_A::OUTPUT + } +} +#[doc = "Set as output pin 6\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN6_AW { + #[doc = "1: Write: writing a '1' sets pin to output; writing a '0' has no effect"] + SET = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN6_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PIN6` writer - Set as output pin 6"] +pub type PIN6_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, DIRSET_SPEC, PIN6_AW, O>; +impl<'a, const O: u8> PIN6_W<'a, O> { + #[doc = "Write: writing a '1' sets pin to output; writing a '0' has no effect"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(PIN6_AW::SET) + } +} +#[doc = "Field `PIN7` reader - Set as output pin 7"] +pub type PIN7_R = crate::BitReader; +#[doc = "Set as output pin 7\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN7_A { + #[doc = "0: Read: pin set as input"] + INPUT = 0, + #[doc = "1: Read: pin set as output"] + OUTPUT = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN7_A) -> Self { + variant as u8 != 0 + } +} +impl PIN7_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN7_A { + match self.bits { + false => PIN7_A::INPUT, + true => PIN7_A::OUTPUT, + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == PIN7_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == PIN7_A::OUTPUT + } +} +#[doc = "Set as output pin 7\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN7_AW { + #[doc = "1: Write: writing a '1' sets pin to output; writing a '0' has no effect"] + SET = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN7_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PIN7` writer - Set as output pin 7"] +pub type PIN7_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, DIRSET_SPEC, PIN7_AW, O>; +impl<'a, const O: u8> PIN7_W<'a, O> { + #[doc = "Write: writing a '1' sets pin to output; writing a '0' has no effect"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(PIN7_AW::SET) + } +} +#[doc = "Field `PIN8` reader - Set as output pin 8"] +pub type PIN8_R = crate::BitReader; +#[doc = "Set as output pin 8\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN8_A { + #[doc = "0: Read: pin set as input"] + INPUT = 0, + #[doc = "1: Read: pin set as output"] + OUTPUT = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN8_A) -> Self { + variant as u8 != 0 + } +} +impl PIN8_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN8_A { + match self.bits { + false => PIN8_A::INPUT, + true => PIN8_A::OUTPUT, + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == PIN8_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == PIN8_A::OUTPUT + } +} +#[doc = "Set as output pin 8\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN8_AW { + #[doc = "1: Write: writing a '1' sets pin to output; writing a '0' has no effect"] + SET = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN8_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PIN8` writer - Set as output pin 8"] +pub type PIN8_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, DIRSET_SPEC, PIN8_AW, O>; +impl<'a, const O: u8> PIN8_W<'a, O> { + #[doc = "Write: writing a '1' sets pin to output; writing a '0' has no effect"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(PIN8_AW::SET) + } +} +#[doc = "Field `PIN9` reader - Set as output pin 9"] +pub type PIN9_R = crate::BitReader; +#[doc = "Set as output pin 9\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN9_A { + #[doc = "0: Read: pin set as input"] + INPUT = 0, + #[doc = "1: Read: pin set as output"] + OUTPUT = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN9_A) -> Self { + variant as u8 != 0 + } +} +impl PIN9_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN9_A { + match self.bits { + false => PIN9_A::INPUT, + true => PIN9_A::OUTPUT, + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == PIN9_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == PIN9_A::OUTPUT + } +} +#[doc = "Set as output pin 9\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN9_AW { + #[doc = "1: Write: writing a '1' sets pin to output; writing a '0' has no effect"] + SET = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN9_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PIN9` writer - Set as output pin 9"] +pub type PIN9_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, DIRSET_SPEC, PIN9_AW, O>; +impl<'a, const O: u8> PIN9_W<'a, O> { + #[doc = "Write: writing a '1' sets pin to output; writing a '0' has no effect"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(PIN9_AW::SET) + } +} +#[doc = "Field `PIN10` reader - Set as output pin 10"] +pub type PIN10_R = crate::BitReader; +#[doc = "Set as output pin 10\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN10_A { + #[doc = "0: Read: pin set as input"] + INPUT = 0, + #[doc = "1: Read: pin set as output"] + OUTPUT = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN10_A) -> Self { + variant as u8 != 0 + } +} +impl PIN10_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN10_A { + match self.bits { + false => PIN10_A::INPUT, + true => PIN10_A::OUTPUT, + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == PIN10_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == PIN10_A::OUTPUT + } +} +#[doc = "Set as output pin 10\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN10_AW { + #[doc = "1: Write: writing a '1' sets pin to output; writing a '0' has no effect"] + SET = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN10_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PIN10` writer - Set as output pin 10"] +pub type PIN10_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, DIRSET_SPEC, PIN10_AW, O>; +impl<'a, const O: u8> PIN10_W<'a, O> { + #[doc = "Write: writing a '1' sets pin to output; writing a '0' has no effect"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(PIN10_AW::SET) + } +} +#[doc = "Field `PIN11` reader - Set as output pin 11"] +pub type PIN11_R = crate::BitReader; +#[doc = "Set as output pin 11\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN11_A { + #[doc = "0: Read: pin set as input"] + INPUT = 0, + #[doc = "1: Read: pin set as output"] + OUTPUT = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN11_A) -> Self { + variant as u8 != 0 + } +} +impl PIN11_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN11_A { + match self.bits { + false => PIN11_A::INPUT, + true => PIN11_A::OUTPUT, + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == PIN11_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == PIN11_A::OUTPUT + } +} +#[doc = "Set as output pin 11\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN11_AW { + #[doc = "1: Write: writing a '1' sets pin to output; writing a '0' has no effect"] + SET = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN11_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PIN11` writer - Set as output pin 11"] +pub type PIN11_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, DIRSET_SPEC, PIN11_AW, O>; +impl<'a, const O: u8> PIN11_W<'a, O> { + #[doc = "Write: writing a '1' sets pin to output; writing a '0' has no effect"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(PIN11_AW::SET) + } +} +#[doc = "Field `PIN12` reader - Set as output pin 12"] +pub type PIN12_R = crate::BitReader; +#[doc = "Set as output pin 12\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN12_A { + #[doc = "0: Read: pin set as input"] + INPUT = 0, + #[doc = "1: Read: pin set as output"] + OUTPUT = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN12_A) -> Self { + variant as u8 != 0 + } +} +impl PIN12_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN12_A { + match self.bits { + false => PIN12_A::INPUT, + true => PIN12_A::OUTPUT, + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == PIN12_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == PIN12_A::OUTPUT + } +} +#[doc = "Set as output pin 12\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN12_AW { + #[doc = "1: Write: writing a '1' sets pin to output; writing a '0' has no effect"] + SET = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN12_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PIN12` writer - Set as output pin 12"] +pub type PIN12_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, DIRSET_SPEC, PIN12_AW, O>; +impl<'a, const O: u8> PIN12_W<'a, O> { + #[doc = "Write: writing a '1' sets pin to output; writing a '0' has no effect"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(PIN12_AW::SET) + } +} +#[doc = "Field `PIN13` reader - Set as output pin 13"] +pub type PIN13_R = crate::BitReader; +#[doc = "Set as output pin 13\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN13_A { + #[doc = "0: Read: pin set as input"] + INPUT = 0, + #[doc = "1: Read: pin set as output"] + OUTPUT = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN13_A) -> Self { + variant as u8 != 0 + } +} +impl PIN13_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN13_A { + match self.bits { + false => PIN13_A::INPUT, + true => PIN13_A::OUTPUT, + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == PIN13_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == PIN13_A::OUTPUT + } +} +#[doc = "Set as output pin 13\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN13_AW { + #[doc = "1: Write: writing a '1' sets pin to output; writing a '0' has no effect"] + SET = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN13_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PIN13` writer - Set as output pin 13"] +pub type PIN13_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, DIRSET_SPEC, PIN13_AW, O>; +impl<'a, const O: u8> PIN13_W<'a, O> { + #[doc = "Write: writing a '1' sets pin to output; writing a '0' has no effect"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(PIN13_AW::SET) + } +} +#[doc = "Field `PIN14` reader - Set as output pin 14"] +pub type PIN14_R = crate::BitReader; +#[doc = "Set as output pin 14\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN14_A { + #[doc = "0: Read: pin set as input"] + INPUT = 0, + #[doc = "1: Read: pin set as output"] + OUTPUT = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN14_A) -> Self { + variant as u8 != 0 + } +} +impl PIN14_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN14_A { + match self.bits { + false => PIN14_A::INPUT, + true => PIN14_A::OUTPUT, + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == PIN14_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == PIN14_A::OUTPUT + } +} +#[doc = "Set as output pin 14\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN14_AW { + #[doc = "1: Write: writing a '1' sets pin to output; writing a '0' has no effect"] + SET = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN14_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PIN14` writer - Set as output pin 14"] +pub type PIN14_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, DIRSET_SPEC, PIN14_AW, O>; +impl<'a, const O: u8> PIN14_W<'a, O> { + #[doc = "Write: writing a '1' sets pin to output; writing a '0' has no effect"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(PIN14_AW::SET) + } +} +#[doc = "Field `PIN15` reader - Set as output pin 15"] +pub type PIN15_R = crate::BitReader; +#[doc = "Set as output pin 15\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN15_A { + #[doc = "0: Read: pin set as input"] + INPUT = 0, + #[doc = "1: Read: pin set as output"] + OUTPUT = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN15_A) -> Self { + variant as u8 != 0 + } +} +impl PIN15_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN15_A { + match self.bits { + false => PIN15_A::INPUT, + true => PIN15_A::OUTPUT, + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == PIN15_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == PIN15_A::OUTPUT + } +} +#[doc = "Set as output pin 15\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN15_AW { + #[doc = "1: Write: writing a '1' sets pin to output; writing a '0' has no effect"] + SET = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN15_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PIN15` writer - Set as output pin 15"] +pub type PIN15_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, DIRSET_SPEC, PIN15_AW, O>; +impl<'a, const O: u8> PIN15_W<'a, O> { + #[doc = "Write: writing a '1' sets pin to output; writing a '0' has no effect"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(PIN15_AW::SET) + } +} +#[doc = "Field `PIN16` reader - Set as output pin 16"] +pub type PIN16_R = crate::BitReader; +#[doc = "Set as output pin 16\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN16_A { + #[doc = "0: Read: pin set as input"] + INPUT = 0, + #[doc = "1: Read: pin set as output"] + OUTPUT = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN16_A) -> Self { + variant as u8 != 0 + } +} +impl PIN16_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN16_A { + match self.bits { + false => PIN16_A::INPUT, + true => PIN16_A::OUTPUT, + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == PIN16_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == PIN16_A::OUTPUT + } +} +#[doc = "Set as output pin 16\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN16_AW { + #[doc = "1: Write: writing a '1' sets pin to output; writing a '0' has no effect"] + SET = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN16_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PIN16` writer - Set as output pin 16"] +pub type PIN16_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, DIRSET_SPEC, PIN16_AW, O>; +impl<'a, const O: u8> PIN16_W<'a, O> { + #[doc = "Write: writing a '1' sets pin to output; writing a '0' has no effect"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(PIN16_AW::SET) + } +} +#[doc = "Field `PIN17` reader - Set as output pin 17"] +pub type PIN17_R = crate::BitReader; +#[doc = "Set as output pin 17\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN17_A { + #[doc = "0: Read: pin set as input"] + INPUT = 0, + #[doc = "1: Read: pin set as output"] + OUTPUT = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN17_A) -> Self { + variant as u8 != 0 + } +} +impl PIN17_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN17_A { + match self.bits { + false => PIN17_A::INPUT, + true => PIN17_A::OUTPUT, + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == PIN17_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == PIN17_A::OUTPUT + } +} +#[doc = "Set as output pin 17\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN17_AW { + #[doc = "1: Write: writing a '1' sets pin to output; writing a '0' has no effect"] + SET = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN17_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PIN17` writer - Set as output pin 17"] +pub type PIN17_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, DIRSET_SPEC, PIN17_AW, O>; +impl<'a, const O: u8> PIN17_W<'a, O> { + #[doc = "Write: writing a '1' sets pin to output; writing a '0' has no effect"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(PIN17_AW::SET) + } +} +#[doc = "Field `PIN18` reader - Set as output pin 18"] +pub type PIN18_R = crate::BitReader; +#[doc = "Set as output pin 18\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN18_A { + #[doc = "0: Read: pin set as input"] + INPUT = 0, + #[doc = "1: Read: pin set as output"] + OUTPUT = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN18_A) -> Self { + variant as u8 != 0 + } +} +impl PIN18_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN18_A { + match self.bits { + false => PIN18_A::INPUT, + true => PIN18_A::OUTPUT, + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == PIN18_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == PIN18_A::OUTPUT + } +} +#[doc = "Set as output pin 18\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN18_AW { + #[doc = "1: Write: writing a '1' sets pin to output; writing a '0' has no effect"] + SET = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN18_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PIN18` writer - Set as output pin 18"] +pub type PIN18_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, DIRSET_SPEC, PIN18_AW, O>; +impl<'a, const O: u8> PIN18_W<'a, O> { + #[doc = "Write: writing a '1' sets pin to output; writing a '0' has no effect"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(PIN18_AW::SET) + } +} +#[doc = "Field `PIN19` reader - Set as output pin 19"] +pub type PIN19_R = crate::BitReader; +#[doc = "Set as output pin 19\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN19_A { + #[doc = "0: Read: pin set as input"] + INPUT = 0, + #[doc = "1: Read: pin set as output"] + OUTPUT = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN19_A) -> Self { + variant as u8 != 0 + } +} +impl PIN19_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN19_A { + match self.bits { + false => PIN19_A::INPUT, + true => PIN19_A::OUTPUT, + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == PIN19_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == PIN19_A::OUTPUT + } +} +#[doc = "Set as output pin 19\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN19_AW { + #[doc = "1: Write: writing a '1' sets pin to output; writing a '0' has no effect"] + SET = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN19_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PIN19` writer - Set as output pin 19"] +pub type PIN19_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, DIRSET_SPEC, PIN19_AW, O>; +impl<'a, const O: u8> PIN19_W<'a, O> { + #[doc = "Write: writing a '1' sets pin to output; writing a '0' has no effect"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(PIN19_AW::SET) + } +} +#[doc = "Field `PIN20` reader - Set as output pin 20"] +pub type PIN20_R = crate::BitReader; +#[doc = "Set as output pin 20\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN20_A { + #[doc = "0: Read: pin set as input"] + INPUT = 0, + #[doc = "1: Read: pin set as output"] + OUTPUT = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN20_A) -> Self { + variant as u8 != 0 + } +} +impl PIN20_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN20_A { + match self.bits { + false => PIN20_A::INPUT, + true => PIN20_A::OUTPUT, + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == PIN20_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == PIN20_A::OUTPUT + } +} +#[doc = "Set as output pin 20\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN20_AW { + #[doc = "1: Write: writing a '1' sets pin to output; writing a '0' has no effect"] + SET = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN20_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PIN20` writer - Set as output pin 20"] +pub type PIN20_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, DIRSET_SPEC, PIN20_AW, O>; +impl<'a, const O: u8> PIN20_W<'a, O> { + #[doc = "Write: writing a '1' sets pin to output; writing a '0' has no effect"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(PIN20_AW::SET) + } +} +#[doc = "Field `PIN21` reader - Set as output pin 21"] +pub type PIN21_R = crate::BitReader; +#[doc = "Set as output pin 21\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN21_A { + #[doc = "0: Read: pin set as input"] + INPUT = 0, + #[doc = "1: Read: pin set as output"] + OUTPUT = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN21_A) -> Self { + variant as u8 != 0 + } +} +impl PIN21_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN21_A { + match self.bits { + false => PIN21_A::INPUT, + true => PIN21_A::OUTPUT, + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == PIN21_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == PIN21_A::OUTPUT + } +} +#[doc = "Set as output pin 21\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN21_AW { + #[doc = "1: Write: writing a '1' sets pin to output; writing a '0' has no effect"] + SET = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN21_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PIN21` writer - Set as output pin 21"] +pub type PIN21_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, DIRSET_SPEC, PIN21_AW, O>; +impl<'a, const O: u8> PIN21_W<'a, O> { + #[doc = "Write: writing a '1' sets pin to output; writing a '0' has no effect"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(PIN21_AW::SET) + } +} +#[doc = "Field `PIN22` reader - Set as output pin 22"] +pub type PIN22_R = crate::BitReader; +#[doc = "Set as output pin 22\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN22_A { + #[doc = "0: Read: pin set as input"] + INPUT = 0, + #[doc = "1: Read: pin set as output"] + OUTPUT = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN22_A) -> Self { + variant as u8 != 0 + } +} +impl PIN22_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN22_A { + match self.bits { + false => PIN22_A::INPUT, + true => PIN22_A::OUTPUT, + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == PIN22_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == PIN22_A::OUTPUT + } +} +#[doc = "Set as output pin 22\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN22_AW { + #[doc = "1: Write: writing a '1' sets pin to output; writing a '0' has no effect"] + SET = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN22_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PIN22` writer - Set as output pin 22"] +pub type PIN22_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, DIRSET_SPEC, PIN22_AW, O>; +impl<'a, const O: u8> PIN22_W<'a, O> { + #[doc = "Write: writing a '1' sets pin to output; writing a '0' has no effect"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(PIN22_AW::SET) + } +} +#[doc = "Field `PIN23` reader - Set as output pin 23"] +pub type PIN23_R = crate::BitReader; +#[doc = "Set as output pin 23\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN23_A { + #[doc = "0: Read: pin set as input"] + INPUT = 0, + #[doc = "1: Read: pin set as output"] + OUTPUT = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN23_A) -> Self { + variant as u8 != 0 + } +} +impl PIN23_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN23_A { + match self.bits { + false => PIN23_A::INPUT, + true => PIN23_A::OUTPUT, + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == PIN23_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == PIN23_A::OUTPUT + } +} +#[doc = "Set as output pin 23\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN23_AW { + #[doc = "1: Write: writing a '1' sets pin to output; writing a '0' has no effect"] + SET = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN23_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PIN23` writer - Set as output pin 23"] +pub type PIN23_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, DIRSET_SPEC, PIN23_AW, O>; +impl<'a, const O: u8> PIN23_W<'a, O> { + #[doc = "Write: writing a '1' sets pin to output; writing a '0' has no effect"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(PIN23_AW::SET) + } +} +#[doc = "Field `PIN24` reader - Set as output pin 24"] +pub type PIN24_R = crate::BitReader; +#[doc = "Set as output pin 24\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN24_A { + #[doc = "0: Read: pin set as input"] + INPUT = 0, + #[doc = "1: Read: pin set as output"] + OUTPUT = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN24_A) -> Self { + variant as u8 != 0 + } +} +impl PIN24_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN24_A { + match self.bits { + false => PIN24_A::INPUT, + true => PIN24_A::OUTPUT, + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == PIN24_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == PIN24_A::OUTPUT + } +} +#[doc = "Set as output pin 24\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN24_AW { + #[doc = "1: Write: writing a '1' sets pin to output; writing a '0' has no effect"] + SET = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN24_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PIN24` writer - Set as output pin 24"] +pub type PIN24_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, DIRSET_SPEC, PIN24_AW, O>; +impl<'a, const O: u8> PIN24_W<'a, O> { + #[doc = "Write: writing a '1' sets pin to output; writing a '0' has no effect"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(PIN24_AW::SET) + } +} +#[doc = "Field `PIN25` reader - Set as output pin 25"] +pub type PIN25_R = crate::BitReader; +#[doc = "Set as output pin 25\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN25_A { + #[doc = "0: Read: pin set as input"] + INPUT = 0, + #[doc = "1: Read: pin set as output"] + OUTPUT = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN25_A) -> Self { + variant as u8 != 0 + } +} +impl PIN25_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN25_A { + match self.bits { + false => PIN25_A::INPUT, + true => PIN25_A::OUTPUT, + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == PIN25_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == PIN25_A::OUTPUT + } +} +#[doc = "Set as output pin 25\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN25_AW { + #[doc = "1: Write: writing a '1' sets pin to output; writing a '0' has no effect"] + SET = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN25_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PIN25` writer - Set as output pin 25"] +pub type PIN25_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, DIRSET_SPEC, PIN25_AW, O>; +impl<'a, const O: u8> PIN25_W<'a, O> { + #[doc = "Write: writing a '1' sets pin to output; writing a '0' has no effect"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(PIN25_AW::SET) + } +} +#[doc = "Field `PIN26` reader - Set as output pin 26"] +pub type PIN26_R = crate::BitReader; +#[doc = "Set as output pin 26\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN26_A { + #[doc = "0: Read: pin set as input"] + INPUT = 0, + #[doc = "1: Read: pin set as output"] + OUTPUT = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN26_A) -> Self { + variant as u8 != 0 + } +} +impl PIN26_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN26_A { + match self.bits { + false => PIN26_A::INPUT, + true => PIN26_A::OUTPUT, + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == PIN26_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == PIN26_A::OUTPUT + } +} +#[doc = "Set as output pin 26\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN26_AW { + #[doc = "1: Write: writing a '1' sets pin to output; writing a '0' has no effect"] + SET = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN26_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PIN26` writer - Set as output pin 26"] +pub type PIN26_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, DIRSET_SPEC, PIN26_AW, O>; +impl<'a, const O: u8> PIN26_W<'a, O> { + #[doc = "Write: writing a '1' sets pin to output; writing a '0' has no effect"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(PIN26_AW::SET) + } +} +#[doc = "Field `PIN27` reader - Set as output pin 27"] +pub type PIN27_R = crate::BitReader; +#[doc = "Set as output pin 27\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN27_A { + #[doc = "0: Read: pin set as input"] + INPUT = 0, + #[doc = "1: Read: pin set as output"] + OUTPUT = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN27_A) -> Self { + variant as u8 != 0 + } +} +impl PIN27_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN27_A { + match self.bits { + false => PIN27_A::INPUT, + true => PIN27_A::OUTPUT, + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == PIN27_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == PIN27_A::OUTPUT + } +} +#[doc = "Set as output pin 27\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN27_AW { + #[doc = "1: Write: writing a '1' sets pin to output; writing a '0' has no effect"] + SET = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN27_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PIN27` writer - Set as output pin 27"] +pub type PIN27_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, DIRSET_SPEC, PIN27_AW, O>; +impl<'a, const O: u8> PIN27_W<'a, O> { + #[doc = "Write: writing a '1' sets pin to output; writing a '0' has no effect"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(PIN27_AW::SET) + } +} +#[doc = "Field `PIN28` reader - Set as output pin 28"] +pub type PIN28_R = crate::BitReader; +#[doc = "Set as output pin 28\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN28_A { + #[doc = "0: Read: pin set as input"] + INPUT = 0, + #[doc = "1: Read: pin set as output"] + OUTPUT = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN28_A) -> Self { + variant as u8 != 0 + } +} +impl PIN28_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN28_A { + match self.bits { + false => PIN28_A::INPUT, + true => PIN28_A::OUTPUT, + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == PIN28_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == PIN28_A::OUTPUT + } +} +#[doc = "Set as output pin 28\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN28_AW { + #[doc = "1: Write: writing a '1' sets pin to output; writing a '0' has no effect"] + SET = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN28_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PIN28` writer - Set as output pin 28"] +pub type PIN28_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, DIRSET_SPEC, PIN28_AW, O>; +impl<'a, const O: u8> PIN28_W<'a, O> { + #[doc = "Write: writing a '1' sets pin to output; writing a '0' has no effect"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(PIN28_AW::SET) + } +} +#[doc = "Field `PIN29` reader - Set as output pin 29"] +pub type PIN29_R = crate::BitReader; +#[doc = "Set as output pin 29\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN29_A { + #[doc = "0: Read: pin set as input"] + INPUT = 0, + #[doc = "1: Read: pin set as output"] + OUTPUT = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN29_A) -> Self { + variant as u8 != 0 + } +} +impl PIN29_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN29_A { + match self.bits { + false => PIN29_A::INPUT, + true => PIN29_A::OUTPUT, + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == PIN29_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == PIN29_A::OUTPUT + } +} +#[doc = "Set as output pin 29\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN29_AW { + #[doc = "1: Write: writing a '1' sets pin to output; writing a '0' has no effect"] + SET = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN29_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PIN29` writer - Set as output pin 29"] +pub type PIN29_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, DIRSET_SPEC, PIN29_AW, O>; +impl<'a, const O: u8> PIN29_W<'a, O> { + #[doc = "Write: writing a '1' sets pin to output; writing a '0' has no effect"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(PIN29_AW::SET) + } +} +#[doc = "Field `PIN30` reader - Set as output pin 30"] +pub type PIN30_R = crate::BitReader; +#[doc = "Set as output pin 30\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN30_A { + #[doc = "0: Read: pin set as input"] + INPUT = 0, + #[doc = "1: Read: pin set as output"] + OUTPUT = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN30_A) -> Self { + variant as u8 != 0 + } +} +impl PIN30_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN30_A { + match self.bits { + false => PIN30_A::INPUT, + true => PIN30_A::OUTPUT, + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == PIN30_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == PIN30_A::OUTPUT + } +} +#[doc = "Set as output pin 30\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN30_AW { + #[doc = "1: Write: writing a '1' sets pin to output; writing a '0' has no effect"] + SET = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN30_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PIN30` writer - Set as output pin 30"] +pub type PIN30_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, DIRSET_SPEC, PIN30_AW, O>; +impl<'a, const O: u8> PIN30_W<'a, O> { + #[doc = "Write: writing a '1' sets pin to output; writing a '0' has no effect"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(PIN30_AW::SET) + } +} +#[doc = "Field `PIN31` reader - Set as output pin 31"] +pub type PIN31_R = crate::BitReader; +#[doc = "Set as output pin 31\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN31_A { + #[doc = "0: Read: pin set as input"] + INPUT = 0, + #[doc = "1: Read: pin set as output"] + OUTPUT = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN31_A) -> Self { + variant as u8 != 0 + } +} +impl PIN31_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN31_A { + match self.bits { + false => PIN31_A::INPUT, + true => PIN31_A::OUTPUT, + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == PIN31_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == PIN31_A::OUTPUT + } +} +#[doc = "Set as output pin 31\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN31_AW { + #[doc = "1: Write: writing a '1' sets pin to output; writing a '0' has no effect"] + SET = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN31_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PIN31` writer - Set as output pin 31"] +pub type PIN31_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, DIRSET_SPEC, PIN31_AW, O>; +impl<'a, const O: u8> PIN31_W<'a, O> { + #[doc = "Write: writing a '1' sets pin to output; writing a '0' has no effect"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(PIN31_AW::SET) + } +} +impl R { + #[doc = "Bit 0 - Set as output pin 0"] + #[inline(always)] + pub fn pin0(&self) -> PIN0_R { + PIN0_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Set as output pin 1"] + #[inline(always)] + pub fn pin1(&self) -> PIN1_R { + PIN1_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Set as output pin 2"] + #[inline(always)] + pub fn pin2(&self) -> PIN2_R { + PIN2_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Set as output pin 3"] + #[inline(always)] + pub fn pin3(&self) -> PIN3_R { + PIN3_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Set as output pin 4"] + #[inline(always)] + pub fn pin4(&self) -> PIN4_R { + PIN4_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Set as output pin 5"] + #[inline(always)] + pub fn pin5(&self) -> PIN5_R { + PIN5_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Set as output pin 6"] + #[inline(always)] + pub fn pin6(&self) -> PIN6_R { + PIN6_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Set as output pin 7"] + #[inline(always)] + pub fn pin7(&self) -> PIN7_R { + PIN7_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Set as output pin 8"] + #[inline(always)] + pub fn pin8(&self) -> PIN8_R { + PIN8_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Set as output pin 9"] + #[inline(always)] + pub fn pin9(&self) -> PIN9_R { + PIN9_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Set as output pin 10"] + #[inline(always)] + pub fn pin10(&self) -> PIN10_R { + PIN10_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Set as output pin 11"] + #[inline(always)] + pub fn pin11(&self) -> PIN11_R { + PIN11_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Set as output pin 12"] + #[inline(always)] + pub fn pin12(&self) -> PIN12_R { + PIN12_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Set as output pin 13"] + #[inline(always)] + pub fn pin13(&self) -> PIN13_R { + PIN13_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Set as output pin 14"] + #[inline(always)] + pub fn pin14(&self) -> PIN14_R { + PIN14_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Set as output pin 15"] + #[inline(always)] + pub fn pin15(&self) -> PIN15_R { + PIN15_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - Set as output pin 16"] + #[inline(always)] + pub fn pin16(&self) -> PIN16_R { + PIN16_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Set as output pin 17"] + #[inline(always)] + pub fn pin17(&self) -> PIN17_R { + PIN17_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Set as output pin 18"] + #[inline(always)] + pub fn pin18(&self) -> PIN18_R { + PIN18_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Set as output pin 19"] + #[inline(always)] + pub fn pin19(&self) -> PIN19_R { + PIN19_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Set as output pin 20"] + #[inline(always)] + pub fn pin20(&self) -> PIN20_R { + PIN20_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Set as output pin 21"] + #[inline(always)] + pub fn pin21(&self) -> PIN21_R { + PIN21_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Set as output pin 22"] + #[inline(always)] + pub fn pin22(&self) -> PIN22_R { + PIN22_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - Set as output pin 23"] + #[inline(always)] + pub fn pin23(&self) -> PIN23_R { + PIN23_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - Set as output pin 24"] + #[inline(always)] + pub fn pin24(&self) -> PIN24_R { + PIN24_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - Set as output pin 25"] + #[inline(always)] + pub fn pin25(&self) -> PIN25_R { + PIN25_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - Set as output pin 26"] + #[inline(always)] + pub fn pin26(&self) -> PIN26_R { + PIN26_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - Set as output pin 27"] + #[inline(always)] + pub fn pin27(&self) -> PIN27_R { + PIN27_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - Set as output pin 28"] + #[inline(always)] + pub fn pin28(&self) -> PIN28_R { + PIN28_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - Set as output pin 29"] + #[inline(always)] + pub fn pin29(&self) -> PIN29_R { + PIN29_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Set as output pin 30"] + #[inline(always)] + pub fn pin30(&self) -> PIN30_R { + PIN30_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Set as output pin 31"] + #[inline(always)] + pub fn pin31(&self) -> PIN31_R { + PIN31_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Set as output pin 0"] + #[inline(always)] + pub fn pin0(&mut self) -> PIN0_W<0> { + PIN0_W::new(self) + } + #[doc = "Bit 1 - Set as output pin 1"] + #[inline(always)] + pub fn pin1(&mut self) -> PIN1_W<1> { + PIN1_W::new(self) + } + #[doc = "Bit 2 - Set as output pin 2"] + #[inline(always)] + pub fn pin2(&mut self) -> PIN2_W<2> { + PIN2_W::new(self) + } + #[doc = "Bit 3 - Set as output pin 3"] + #[inline(always)] + pub fn pin3(&mut self) -> PIN3_W<3> { + PIN3_W::new(self) + } + #[doc = "Bit 4 - Set as output pin 4"] + #[inline(always)] + pub fn pin4(&mut self) -> PIN4_W<4> { + PIN4_W::new(self) + } + #[doc = "Bit 5 - Set as output pin 5"] + #[inline(always)] + pub fn pin5(&mut self) -> PIN5_W<5> { + PIN5_W::new(self) + } + #[doc = "Bit 6 - Set as output pin 6"] + #[inline(always)] + pub fn pin6(&mut self) -> PIN6_W<6> { + PIN6_W::new(self) + } + #[doc = "Bit 7 - Set as output pin 7"] + #[inline(always)] + pub fn pin7(&mut self) -> PIN7_W<7> { + PIN7_W::new(self) + } + #[doc = "Bit 8 - Set as output pin 8"] + #[inline(always)] + pub fn pin8(&mut self) -> PIN8_W<8> { + PIN8_W::new(self) + } + #[doc = "Bit 9 - Set as output pin 9"] + #[inline(always)] + pub fn pin9(&mut self) -> PIN9_W<9> { + PIN9_W::new(self) + } + #[doc = "Bit 10 - Set as output pin 10"] + #[inline(always)] + pub fn pin10(&mut self) -> PIN10_W<10> { + PIN10_W::new(self) + } + #[doc = "Bit 11 - Set as output pin 11"] + #[inline(always)] + pub fn pin11(&mut self) -> PIN11_W<11> { + PIN11_W::new(self) + } + #[doc = "Bit 12 - Set as output pin 12"] + #[inline(always)] + pub fn pin12(&mut self) -> PIN12_W<12> { + PIN12_W::new(self) + } + #[doc = "Bit 13 - Set as output pin 13"] + #[inline(always)] + pub fn pin13(&mut self) -> PIN13_W<13> { + PIN13_W::new(self) + } + #[doc = "Bit 14 - Set as output pin 14"] + #[inline(always)] + pub fn pin14(&mut self) -> PIN14_W<14> { + PIN14_W::new(self) + } + #[doc = "Bit 15 - Set as output pin 15"] + #[inline(always)] + pub fn pin15(&mut self) -> PIN15_W<15> { + PIN15_W::new(self) + } + #[doc = "Bit 16 - Set as output pin 16"] + #[inline(always)] + pub fn pin16(&mut self) -> PIN16_W<16> { + PIN16_W::new(self) + } + #[doc = "Bit 17 - Set as output pin 17"] + #[inline(always)] + pub fn pin17(&mut self) -> PIN17_W<17> { + PIN17_W::new(self) + } + #[doc = "Bit 18 - Set as output pin 18"] + #[inline(always)] + pub fn pin18(&mut self) -> PIN18_W<18> { + PIN18_W::new(self) + } + #[doc = "Bit 19 - Set as output pin 19"] + #[inline(always)] + pub fn pin19(&mut self) -> PIN19_W<19> { + PIN19_W::new(self) + } + #[doc = "Bit 20 - Set as output pin 20"] + #[inline(always)] + pub fn pin20(&mut self) -> PIN20_W<20> { + PIN20_W::new(self) + } + #[doc = "Bit 21 - Set as output pin 21"] + #[inline(always)] + pub fn pin21(&mut self) -> PIN21_W<21> { + PIN21_W::new(self) + } + #[doc = "Bit 22 - Set as output pin 22"] + #[inline(always)] + pub fn pin22(&mut self) -> PIN22_W<22> { + PIN22_W::new(self) + } + #[doc = "Bit 23 - Set as output pin 23"] + #[inline(always)] + pub fn pin23(&mut self) -> PIN23_W<23> { + PIN23_W::new(self) + } + #[doc = "Bit 24 - Set as output pin 24"] + #[inline(always)] + pub fn pin24(&mut self) -> PIN24_W<24> { + PIN24_W::new(self) + } + #[doc = "Bit 25 - Set as output pin 25"] + #[inline(always)] + pub fn pin25(&mut self) -> PIN25_W<25> { + PIN25_W::new(self) + } + #[doc = "Bit 26 - Set as output pin 26"] + #[inline(always)] + pub fn pin26(&mut self) -> PIN26_W<26> { + PIN26_W::new(self) + } + #[doc = "Bit 27 - Set as output pin 27"] + #[inline(always)] + pub fn pin27(&mut self) -> PIN27_W<27> { + PIN27_W::new(self) + } + #[doc = "Bit 28 - Set as output pin 28"] + #[inline(always)] + pub fn pin28(&mut self) -> PIN28_W<28> { + PIN28_W::new(self) + } + #[doc = "Bit 29 - Set as output pin 29"] + #[inline(always)] + pub fn pin29(&mut self) -> PIN29_W<29> { + PIN29_W::new(self) + } + #[doc = "Bit 30 - Set as output pin 30"] + #[inline(always)] + pub fn pin30(&mut self) -> PIN30_W<30> { + PIN30_W::new(self) + } + #[doc = "Bit 31 - Set as output pin 31"] + #[inline(always)] + pub fn pin31(&mut self) -> PIN31_W<31> { + PIN31_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "DIR set register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dirset](index.html) module"] +pub struct DIRSET_SPEC; +impl crate::RegisterSpec for DIRSET_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dirset::R](R) reader structure"] +impl crate::Readable for DIRSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dirset::W](W) writer structure"] +impl crate::Writable for DIRSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DIRSET to value 0"] +impl crate::Resettable for DIRSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/p0_ns/in_.rs b/pacs/nrf9120-pac/src/p0_ns/in_.rs new file mode 100644 index 00000000..9a7971d5 --- /dev/null +++ b/pacs/nrf9120-pac/src/p0_ns/in_.rs @@ -0,0 +1,1345 @@ +#[doc = "Register `IN` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `PIN0` reader - Pin 0"] +pub type PIN0_R = crate::BitReader; +#[doc = "Pin 0\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN0_A { + #[doc = "0: Pin input is low"] + LOW = 0, + #[doc = "1: Pin input is high"] + HIGH = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN0_A) -> Self { + variant as u8 != 0 + } +} +impl PIN0_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN0_A { + match self.bits { + false => PIN0_A::LOW, + true => PIN0_A::HIGH, + } + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + *self == PIN0_A::LOW + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + *self == PIN0_A::HIGH + } +} +#[doc = "Field `PIN1` reader - Pin 1"] +pub type PIN1_R = crate::BitReader; +#[doc = "Pin 1\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN1_A { + #[doc = "0: Pin input is low"] + LOW = 0, + #[doc = "1: Pin input is high"] + HIGH = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN1_A) -> Self { + variant as u8 != 0 + } +} +impl PIN1_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN1_A { + match self.bits { + false => PIN1_A::LOW, + true => PIN1_A::HIGH, + } + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + *self == PIN1_A::LOW + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + *self == PIN1_A::HIGH + } +} +#[doc = "Field `PIN2` reader - Pin 2"] +pub type PIN2_R = crate::BitReader; +#[doc = "Pin 2\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN2_A { + #[doc = "0: Pin input is low"] + LOW = 0, + #[doc = "1: Pin input is high"] + HIGH = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN2_A) -> Self { + variant as u8 != 0 + } +} +impl PIN2_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN2_A { + match self.bits { + false => PIN2_A::LOW, + true => PIN2_A::HIGH, + } + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + *self == PIN2_A::LOW + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + *self == PIN2_A::HIGH + } +} +#[doc = "Field `PIN3` reader - Pin 3"] +pub type PIN3_R = crate::BitReader; +#[doc = "Pin 3\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN3_A { + #[doc = "0: Pin input is low"] + LOW = 0, + #[doc = "1: Pin input is high"] + HIGH = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN3_A) -> Self { + variant as u8 != 0 + } +} +impl PIN3_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN3_A { + match self.bits { + false => PIN3_A::LOW, + true => PIN3_A::HIGH, + } + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + *self == PIN3_A::LOW + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + *self == PIN3_A::HIGH + } +} +#[doc = "Field `PIN4` reader - Pin 4"] +pub type PIN4_R = crate::BitReader; +#[doc = "Pin 4\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN4_A { + #[doc = "0: Pin input is low"] + LOW = 0, + #[doc = "1: Pin input is high"] + HIGH = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN4_A) -> Self { + variant as u8 != 0 + } +} +impl PIN4_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN4_A { + match self.bits { + false => PIN4_A::LOW, + true => PIN4_A::HIGH, + } + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + *self == PIN4_A::LOW + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + *self == PIN4_A::HIGH + } +} +#[doc = "Field `PIN5` reader - Pin 5"] +pub type PIN5_R = crate::BitReader; +#[doc = "Pin 5\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN5_A { + #[doc = "0: Pin input is low"] + LOW = 0, + #[doc = "1: Pin input is high"] + HIGH = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN5_A) -> Self { + variant as u8 != 0 + } +} +impl PIN5_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN5_A { + match self.bits { + false => PIN5_A::LOW, + true => PIN5_A::HIGH, + } + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + *self == PIN5_A::LOW + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + *self == PIN5_A::HIGH + } +} +#[doc = "Field `PIN6` reader - Pin 6"] +pub type PIN6_R = crate::BitReader; +#[doc = "Pin 6\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN6_A { + #[doc = "0: Pin input is low"] + LOW = 0, + #[doc = "1: Pin input is high"] + HIGH = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN6_A) -> Self { + variant as u8 != 0 + } +} +impl PIN6_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN6_A { + match self.bits { + false => PIN6_A::LOW, + true => PIN6_A::HIGH, + } + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + *self == PIN6_A::LOW + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + *self == PIN6_A::HIGH + } +} +#[doc = "Field `PIN7` reader - Pin 7"] +pub type PIN7_R = crate::BitReader; +#[doc = "Pin 7\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN7_A { + #[doc = "0: Pin input is low"] + LOW = 0, + #[doc = "1: Pin input is high"] + HIGH = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN7_A) -> Self { + variant as u8 != 0 + } +} +impl PIN7_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN7_A { + match self.bits { + false => PIN7_A::LOW, + true => PIN7_A::HIGH, + } + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + *self == PIN7_A::LOW + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + *self == PIN7_A::HIGH + } +} +#[doc = "Field `PIN8` reader - Pin 8"] +pub type PIN8_R = crate::BitReader; +#[doc = "Pin 8\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN8_A { + #[doc = "0: Pin input is low"] + LOW = 0, + #[doc = "1: Pin input is high"] + HIGH = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN8_A) -> Self { + variant as u8 != 0 + } +} +impl PIN8_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN8_A { + match self.bits { + false => PIN8_A::LOW, + true => PIN8_A::HIGH, + } + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + *self == PIN8_A::LOW + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + *self == PIN8_A::HIGH + } +} +#[doc = "Field `PIN9` reader - Pin 9"] +pub type PIN9_R = crate::BitReader; +#[doc = "Pin 9\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN9_A { + #[doc = "0: Pin input is low"] + LOW = 0, + #[doc = "1: Pin input is high"] + HIGH = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN9_A) -> Self { + variant as u8 != 0 + } +} +impl PIN9_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN9_A { + match self.bits { + false => PIN9_A::LOW, + true => PIN9_A::HIGH, + } + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + *self == PIN9_A::LOW + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + *self == PIN9_A::HIGH + } +} +#[doc = "Field `PIN10` reader - Pin 10"] +pub type PIN10_R = crate::BitReader; +#[doc = "Pin 10\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN10_A { + #[doc = "0: Pin input is low"] + LOW = 0, + #[doc = "1: Pin input is high"] + HIGH = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN10_A) -> Self { + variant as u8 != 0 + } +} +impl PIN10_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN10_A { + match self.bits { + false => PIN10_A::LOW, + true => PIN10_A::HIGH, + } + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + *self == PIN10_A::LOW + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + *self == PIN10_A::HIGH + } +} +#[doc = "Field `PIN11` reader - Pin 11"] +pub type PIN11_R = crate::BitReader; +#[doc = "Pin 11\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN11_A { + #[doc = "0: Pin input is low"] + LOW = 0, + #[doc = "1: Pin input is high"] + HIGH = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN11_A) -> Self { + variant as u8 != 0 + } +} +impl PIN11_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN11_A { + match self.bits { + false => PIN11_A::LOW, + true => PIN11_A::HIGH, + } + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + *self == PIN11_A::LOW + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + *self == PIN11_A::HIGH + } +} +#[doc = "Field `PIN12` reader - Pin 12"] +pub type PIN12_R = crate::BitReader; +#[doc = "Pin 12\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN12_A { + #[doc = "0: Pin input is low"] + LOW = 0, + #[doc = "1: Pin input is high"] + HIGH = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN12_A) -> Self { + variant as u8 != 0 + } +} +impl PIN12_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN12_A { + match self.bits { + false => PIN12_A::LOW, + true => PIN12_A::HIGH, + } + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + *self == PIN12_A::LOW + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + *self == PIN12_A::HIGH + } +} +#[doc = "Field `PIN13` reader - Pin 13"] +pub type PIN13_R = crate::BitReader; +#[doc = "Pin 13\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN13_A { + #[doc = "0: Pin input is low"] + LOW = 0, + #[doc = "1: Pin input is high"] + HIGH = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN13_A) -> Self { + variant as u8 != 0 + } +} +impl PIN13_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN13_A { + match self.bits { + false => PIN13_A::LOW, + true => PIN13_A::HIGH, + } + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + *self == PIN13_A::LOW + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + *self == PIN13_A::HIGH + } +} +#[doc = "Field `PIN14` reader - Pin 14"] +pub type PIN14_R = crate::BitReader; +#[doc = "Pin 14\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN14_A { + #[doc = "0: Pin input is low"] + LOW = 0, + #[doc = "1: Pin input is high"] + HIGH = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN14_A) -> Self { + variant as u8 != 0 + } +} +impl PIN14_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN14_A { + match self.bits { + false => PIN14_A::LOW, + true => PIN14_A::HIGH, + } + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + *self == PIN14_A::LOW + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + *self == PIN14_A::HIGH + } +} +#[doc = "Field `PIN15` reader - Pin 15"] +pub type PIN15_R = crate::BitReader; +#[doc = "Pin 15\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN15_A { + #[doc = "0: Pin input is low"] + LOW = 0, + #[doc = "1: Pin input is high"] + HIGH = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN15_A) -> Self { + variant as u8 != 0 + } +} +impl PIN15_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN15_A { + match self.bits { + false => PIN15_A::LOW, + true => PIN15_A::HIGH, + } + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + *self == PIN15_A::LOW + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + *self == PIN15_A::HIGH + } +} +#[doc = "Field `PIN16` reader - Pin 16"] +pub type PIN16_R = crate::BitReader; +#[doc = "Pin 16\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN16_A { + #[doc = "0: Pin input is low"] + LOW = 0, + #[doc = "1: Pin input is high"] + HIGH = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN16_A) -> Self { + variant as u8 != 0 + } +} +impl PIN16_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN16_A { + match self.bits { + false => PIN16_A::LOW, + true => PIN16_A::HIGH, + } + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + *self == PIN16_A::LOW + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + *self == PIN16_A::HIGH + } +} +#[doc = "Field `PIN17` reader - Pin 17"] +pub type PIN17_R = crate::BitReader; +#[doc = "Pin 17\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN17_A { + #[doc = "0: Pin input is low"] + LOW = 0, + #[doc = "1: Pin input is high"] + HIGH = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN17_A) -> Self { + variant as u8 != 0 + } +} +impl PIN17_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN17_A { + match self.bits { + false => PIN17_A::LOW, + true => PIN17_A::HIGH, + } + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + *self == PIN17_A::LOW + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + *self == PIN17_A::HIGH + } +} +#[doc = "Field `PIN18` reader - Pin 18"] +pub type PIN18_R = crate::BitReader; +#[doc = "Pin 18\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN18_A { + #[doc = "0: Pin input is low"] + LOW = 0, + #[doc = "1: Pin input is high"] + HIGH = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN18_A) -> Self { + variant as u8 != 0 + } +} +impl PIN18_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN18_A { + match self.bits { + false => PIN18_A::LOW, + true => PIN18_A::HIGH, + } + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + *self == PIN18_A::LOW + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + *self == PIN18_A::HIGH + } +} +#[doc = "Field `PIN19` reader - Pin 19"] +pub type PIN19_R = crate::BitReader; +#[doc = "Pin 19\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN19_A { + #[doc = "0: Pin input is low"] + LOW = 0, + #[doc = "1: Pin input is high"] + HIGH = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN19_A) -> Self { + variant as u8 != 0 + } +} +impl PIN19_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN19_A { + match self.bits { + false => PIN19_A::LOW, + true => PIN19_A::HIGH, + } + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + *self == PIN19_A::LOW + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + *self == PIN19_A::HIGH + } +} +#[doc = "Field `PIN20` reader - Pin 20"] +pub type PIN20_R = crate::BitReader; +#[doc = "Pin 20\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN20_A { + #[doc = "0: Pin input is low"] + LOW = 0, + #[doc = "1: Pin input is high"] + HIGH = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN20_A) -> Self { + variant as u8 != 0 + } +} +impl PIN20_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN20_A { + match self.bits { + false => PIN20_A::LOW, + true => PIN20_A::HIGH, + } + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + *self == PIN20_A::LOW + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + *self == PIN20_A::HIGH + } +} +#[doc = "Field `PIN21` reader - Pin 21"] +pub type PIN21_R = crate::BitReader; +#[doc = "Pin 21\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN21_A { + #[doc = "0: Pin input is low"] + LOW = 0, + #[doc = "1: Pin input is high"] + HIGH = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN21_A) -> Self { + variant as u8 != 0 + } +} +impl PIN21_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN21_A { + match self.bits { + false => PIN21_A::LOW, + true => PIN21_A::HIGH, + } + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + *self == PIN21_A::LOW + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + *self == PIN21_A::HIGH + } +} +#[doc = "Field `PIN22` reader - Pin 22"] +pub type PIN22_R = crate::BitReader; +#[doc = "Pin 22\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN22_A { + #[doc = "0: Pin input is low"] + LOW = 0, + #[doc = "1: Pin input is high"] + HIGH = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN22_A) -> Self { + variant as u8 != 0 + } +} +impl PIN22_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN22_A { + match self.bits { + false => PIN22_A::LOW, + true => PIN22_A::HIGH, + } + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + *self == PIN22_A::LOW + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + *self == PIN22_A::HIGH + } +} +#[doc = "Field `PIN23` reader - Pin 23"] +pub type PIN23_R = crate::BitReader; +#[doc = "Pin 23\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN23_A { + #[doc = "0: Pin input is low"] + LOW = 0, + #[doc = "1: Pin input is high"] + HIGH = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN23_A) -> Self { + variant as u8 != 0 + } +} +impl PIN23_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN23_A { + match self.bits { + false => PIN23_A::LOW, + true => PIN23_A::HIGH, + } + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + *self == PIN23_A::LOW + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + *self == PIN23_A::HIGH + } +} +#[doc = "Field `PIN24` reader - Pin 24"] +pub type PIN24_R = crate::BitReader; +#[doc = "Pin 24\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN24_A { + #[doc = "0: Pin input is low"] + LOW = 0, + #[doc = "1: Pin input is high"] + HIGH = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN24_A) -> Self { + variant as u8 != 0 + } +} +impl PIN24_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN24_A { + match self.bits { + false => PIN24_A::LOW, + true => PIN24_A::HIGH, + } + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + *self == PIN24_A::LOW + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + *self == PIN24_A::HIGH + } +} +#[doc = "Field `PIN25` reader - Pin 25"] +pub type PIN25_R = crate::BitReader; +#[doc = "Pin 25\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN25_A { + #[doc = "0: Pin input is low"] + LOW = 0, + #[doc = "1: Pin input is high"] + HIGH = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN25_A) -> Self { + variant as u8 != 0 + } +} +impl PIN25_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN25_A { + match self.bits { + false => PIN25_A::LOW, + true => PIN25_A::HIGH, + } + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + *self == PIN25_A::LOW + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + *self == PIN25_A::HIGH + } +} +#[doc = "Field `PIN26` reader - Pin 26"] +pub type PIN26_R = crate::BitReader; +#[doc = "Pin 26\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN26_A { + #[doc = "0: Pin input is low"] + LOW = 0, + #[doc = "1: Pin input is high"] + HIGH = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN26_A) -> Self { + variant as u8 != 0 + } +} +impl PIN26_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN26_A { + match self.bits { + false => PIN26_A::LOW, + true => PIN26_A::HIGH, + } + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + *self == PIN26_A::LOW + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + *self == PIN26_A::HIGH + } +} +#[doc = "Field `PIN27` reader - Pin 27"] +pub type PIN27_R = crate::BitReader; +#[doc = "Pin 27\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN27_A { + #[doc = "0: Pin input is low"] + LOW = 0, + #[doc = "1: Pin input is high"] + HIGH = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN27_A) -> Self { + variant as u8 != 0 + } +} +impl PIN27_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN27_A { + match self.bits { + false => PIN27_A::LOW, + true => PIN27_A::HIGH, + } + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + *self == PIN27_A::LOW + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + *self == PIN27_A::HIGH + } +} +#[doc = "Field `PIN28` reader - Pin 28"] +pub type PIN28_R = crate::BitReader; +#[doc = "Pin 28\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN28_A { + #[doc = "0: Pin input is low"] + LOW = 0, + #[doc = "1: Pin input is high"] + HIGH = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN28_A) -> Self { + variant as u8 != 0 + } +} +impl PIN28_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN28_A { + match self.bits { + false => PIN28_A::LOW, + true => PIN28_A::HIGH, + } + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + *self == PIN28_A::LOW + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + *self == PIN28_A::HIGH + } +} +#[doc = "Field `PIN29` reader - Pin 29"] +pub type PIN29_R = crate::BitReader; +#[doc = "Pin 29\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN29_A { + #[doc = "0: Pin input is low"] + LOW = 0, + #[doc = "1: Pin input is high"] + HIGH = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN29_A) -> Self { + variant as u8 != 0 + } +} +impl PIN29_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN29_A { + match self.bits { + false => PIN29_A::LOW, + true => PIN29_A::HIGH, + } + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + *self == PIN29_A::LOW + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + *self == PIN29_A::HIGH + } +} +#[doc = "Field `PIN30` reader - Pin 30"] +pub type PIN30_R = crate::BitReader; +#[doc = "Pin 30\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN30_A { + #[doc = "0: Pin input is low"] + LOW = 0, + #[doc = "1: Pin input is high"] + HIGH = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN30_A) -> Self { + variant as u8 != 0 + } +} +impl PIN30_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN30_A { + match self.bits { + false => PIN30_A::LOW, + true => PIN30_A::HIGH, + } + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + *self == PIN30_A::LOW + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + *self == PIN30_A::HIGH + } +} +#[doc = "Field `PIN31` reader - Pin 31"] +pub type PIN31_R = crate::BitReader; +#[doc = "Pin 31\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN31_A { + #[doc = "0: Pin input is low"] + LOW = 0, + #[doc = "1: Pin input is high"] + HIGH = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN31_A) -> Self { + variant as u8 != 0 + } +} +impl PIN31_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN31_A { + match self.bits { + false => PIN31_A::LOW, + true => PIN31_A::HIGH, + } + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + *self == PIN31_A::LOW + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + *self == PIN31_A::HIGH + } +} +impl R { + #[doc = "Bit 0 - Pin 0"] + #[inline(always)] + pub fn pin0(&self) -> PIN0_R { + PIN0_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Pin 1"] + #[inline(always)] + pub fn pin1(&self) -> PIN1_R { + PIN1_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Pin 2"] + #[inline(always)] + pub fn pin2(&self) -> PIN2_R { + PIN2_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Pin 3"] + #[inline(always)] + pub fn pin3(&self) -> PIN3_R { + PIN3_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Pin 4"] + #[inline(always)] + pub fn pin4(&self) -> PIN4_R { + PIN4_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Pin 5"] + #[inline(always)] + pub fn pin5(&self) -> PIN5_R { + PIN5_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Pin 6"] + #[inline(always)] + pub fn pin6(&self) -> PIN6_R { + PIN6_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Pin 7"] + #[inline(always)] + pub fn pin7(&self) -> PIN7_R { + PIN7_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Pin 8"] + #[inline(always)] + pub fn pin8(&self) -> PIN8_R { + PIN8_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Pin 9"] + #[inline(always)] + pub fn pin9(&self) -> PIN9_R { + PIN9_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Pin 10"] + #[inline(always)] + pub fn pin10(&self) -> PIN10_R { + PIN10_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Pin 11"] + #[inline(always)] + pub fn pin11(&self) -> PIN11_R { + PIN11_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Pin 12"] + #[inline(always)] + pub fn pin12(&self) -> PIN12_R { + PIN12_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Pin 13"] + #[inline(always)] + pub fn pin13(&self) -> PIN13_R { + PIN13_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Pin 14"] + #[inline(always)] + pub fn pin14(&self) -> PIN14_R { + PIN14_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Pin 15"] + #[inline(always)] + pub fn pin15(&self) -> PIN15_R { + PIN15_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - Pin 16"] + #[inline(always)] + pub fn pin16(&self) -> PIN16_R { + PIN16_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Pin 17"] + #[inline(always)] + pub fn pin17(&self) -> PIN17_R { + PIN17_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Pin 18"] + #[inline(always)] + pub fn pin18(&self) -> PIN18_R { + PIN18_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Pin 19"] + #[inline(always)] + pub fn pin19(&self) -> PIN19_R { + PIN19_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Pin 20"] + #[inline(always)] + pub fn pin20(&self) -> PIN20_R { + PIN20_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Pin 21"] + #[inline(always)] + pub fn pin21(&self) -> PIN21_R { + PIN21_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Pin 22"] + #[inline(always)] + pub fn pin22(&self) -> PIN22_R { + PIN22_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - Pin 23"] + #[inline(always)] + pub fn pin23(&self) -> PIN23_R { + PIN23_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - Pin 24"] + #[inline(always)] + pub fn pin24(&self) -> PIN24_R { + PIN24_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - Pin 25"] + #[inline(always)] + pub fn pin25(&self) -> PIN25_R { + PIN25_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - Pin 26"] + #[inline(always)] + pub fn pin26(&self) -> PIN26_R { + PIN26_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - Pin 27"] + #[inline(always)] + pub fn pin27(&self) -> PIN27_R { + PIN27_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - Pin 28"] + #[inline(always)] + pub fn pin28(&self) -> PIN28_R { + PIN28_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - Pin 29"] + #[inline(always)] + pub fn pin29(&self) -> PIN29_R { + PIN29_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Pin 30"] + #[inline(always)] + pub fn pin30(&self) -> PIN30_R { + PIN30_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Pin 31"] + #[inline(always)] + pub fn pin31(&self) -> PIN31_R { + PIN31_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[doc = "Read GPIO port\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [in_](index.html) module"] +pub struct IN_SPEC; +impl crate::RegisterSpec for IN_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [in_::R](R) reader structure"] +impl crate::Readable for IN_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets IN to value 0"] +impl crate::Resettable for IN_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/p0_ns/latch.rs b/pacs/nrf9120-pac/src/p0_ns/latch.rs new file mode 100644 index 00000000..bf23c0b5 --- /dev/null +++ b/pacs/nrf9120-pac/src/p0_ns/latch.rs @@ -0,0 +1,2146 @@ +#[doc = "Register `LATCH` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `LATCH` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PIN0` reader - Status on whether PIN\\[0\\] +has met criteria set in PIN_CNF\\[0\\].SENSE register. Write '1' to clear."] +pub type PIN0_R = crate::BitReader; +#[doc = "Status on whether PIN\\[0\\] +has met criteria set in PIN_CNF\\[0\\].SENSE register. Write '1' to clear.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN0_A { + #[doc = "0: Criteria has not been met"] + NOT_LATCHED = 0, + #[doc = "1: Criteria has been met"] + LATCHED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN0_A) -> Self { + variant as u8 != 0 + } +} +impl PIN0_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN0_A { + match self.bits { + false => PIN0_A::NOT_LATCHED, + true => PIN0_A::LATCHED, + } + } + #[doc = "Checks if the value of the field is `NOT_LATCHED`"] + #[inline(always)] + pub fn is_not_latched(&self) -> bool { + *self == PIN0_A::NOT_LATCHED + } + #[doc = "Checks if the value of the field is `LATCHED`"] + #[inline(always)] + pub fn is_latched(&self) -> bool { + *self == PIN0_A::LATCHED + } +} +#[doc = "Field `PIN0` writer - Status on whether PIN\\[0\\] +has met criteria set in PIN_CNF\\[0\\].SENSE register. Write '1' to clear."] +pub type PIN0_W<'a, const O: u8> = crate::BitWriter<'a, u32, LATCH_SPEC, PIN0_A, O>; +impl<'a, const O: u8> PIN0_W<'a, O> { + #[doc = "Criteria has not been met"] + #[inline(always)] + pub fn not_latched(self) -> &'a mut W { + self.variant(PIN0_A::NOT_LATCHED) + } + #[doc = "Criteria has been met"] + #[inline(always)] + pub fn latched(self) -> &'a mut W { + self.variant(PIN0_A::LATCHED) + } +} +#[doc = "Field `PIN1` reader - Status on whether PIN\\[1\\] +has met criteria set in PIN_CNF\\[1\\].SENSE register. Write '1' to clear."] +pub type PIN1_R = crate::BitReader; +#[doc = "Status on whether PIN\\[1\\] +has met criteria set in PIN_CNF\\[1\\].SENSE register. Write '1' to clear.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN1_A { + #[doc = "0: Criteria has not been met"] + NOT_LATCHED = 0, + #[doc = "1: Criteria has been met"] + LATCHED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN1_A) -> Self { + variant as u8 != 0 + } +} +impl PIN1_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN1_A { + match self.bits { + false => PIN1_A::NOT_LATCHED, + true => PIN1_A::LATCHED, + } + } + #[doc = "Checks if the value of the field is `NOT_LATCHED`"] + #[inline(always)] + pub fn is_not_latched(&self) -> bool { + *self == PIN1_A::NOT_LATCHED + } + #[doc = "Checks if the value of the field is `LATCHED`"] + #[inline(always)] + pub fn is_latched(&self) -> bool { + *self == PIN1_A::LATCHED + } +} +#[doc = "Field `PIN1` writer - Status on whether PIN\\[1\\] +has met criteria set in PIN_CNF\\[1\\].SENSE register. Write '1' to clear."] +pub type PIN1_W<'a, const O: u8> = crate::BitWriter<'a, u32, LATCH_SPEC, PIN1_A, O>; +impl<'a, const O: u8> PIN1_W<'a, O> { + #[doc = "Criteria has not been met"] + #[inline(always)] + pub fn not_latched(self) -> &'a mut W { + self.variant(PIN1_A::NOT_LATCHED) + } + #[doc = "Criteria has been met"] + #[inline(always)] + pub fn latched(self) -> &'a mut W { + self.variant(PIN1_A::LATCHED) + } +} +#[doc = "Field `PIN2` reader - Status on whether PIN\\[2\\] +has met criteria set in PIN_CNF\\[2\\].SENSE register. Write '1' to clear."] +pub type PIN2_R = crate::BitReader; +#[doc = "Status on whether PIN\\[2\\] +has met criteria set in PIN_CNF\\[2\\].SENSE register. Write '1' to clear.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN2_A { + #[doc = "0: Criteria has not been met"] + NOT_LATCHED = 0, + #[doc = "1: Criteria has been met"] + LATCHED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN2_A) -> Self { + variant as u8 != 0 + } +} +impl PIN2_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN2_A { + match self.bits { + false => PIN2_A::NOT_LATCHED, + true => PIN2_A::LATCHED, + } + } + #[doc = "Checks if the value of the field is `NOT_LATCHED`"] + #[inline(always)] + pub fn is_not_latched(&self) -> bool { + *self == PIN2_A::NOT_LATCHED + } + #[doc = "Checks if the value of the field is `LATCHED`"] + #[inline(always)] + pub fn is_latched(&self) -> bool { + *self == PIN2_A::LATCHED + } +} +#[doc = "Field `PIN2` writer - Status on whether PIN\\[2\\] +has met criteria set in PIN_CNF\\[2\\].SENSE register. Write '1' to clear."] +pub type PIN2_W<'a, const O: u8> = crate::BitWriter<'a, u32, LATCH_SPEC, PIN2_A, O>; +impl<'a, const O: u8> PIN2_W<'a, O> { + #[doc = "Criteria has not been met"] + #[inline(always)] + pub fn not_latched(self) -> &'a mut W { + self.variant(PIN2_A::NOT_LATCHED) + } + #[doc = "Criteria has been met"] + #[inline(always)] + pub fn latched(self) -> &'a mut W { + self.variant(PIN2_A::LATCHED) + } +} +#[doc = "Field `PIN3` reader - Status on whether PIN\\[3\\] +has met criteria set in PIN_CNF\\[3\\].SENSE register. Write '1' to clear."] +pub type PIN3_R = crate::BitReader; +#[doc = "Status on whether PIN\\[3\\] +has met criteria set in PIN_CNF\\[3\\].SENSE register. Write '1' to clear.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN3_A { + #[doc = "0: Criteria has not been met"] + NOT_LATCHED = 0, + #[doc = "1: Criteria has been met"] + LATCHED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN3_A) -> Self { + variant as u8 != 0 + } +} +impl PIN3_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN3_A { + match self.bits { + false => PIN3_A::NOT_LATCHED, + true => PIN3_A::LATCHED, + } + } + #[doc = "Checks if the value of the field is `NOT_LATCHED`"] + #[inline(always)] + pub fn is_not_latched(&self) -> bool { + *self == PIN3_A::NOT_LATCHED + } + #[doc = "Checks if the value of the field is `LATCHED`"] + #[inline(always)] + pub fn is_latched(&self) -> bool { + *self == PIN3_A::LATCHED + } +} +#[doc = "Field `PIN3` writer - Status on whether PIN\\[3\\] +has met criteria set in PIN_CNF\\[3\\].SENSE register. Write '1' to clear."] +pub type PIN3_W<'a, const O: u8> = crate::BitWriter<'a, u32, LATCH_SPEC, PIN3_A, O>; +impl<'a, const O: u8> PIN3_W<'a, O> { + #[doc = "Criteria has not been met"] + #[inline(always)] + pub fn not_latched(self) -> &'a mut W { + self.variant(PIN3_A::NOT_LATCHED) + } + #[doc = "Criteria has been met"] + #[inline(always)] + pub fn latched(self) -> &'a mut W { + self.variant(PIN3_A::LATCHED) + } +} +#[doc = "Field `PIN4` reader - Status on whether PIN\\[4\\] +has met criteria set in PIN_CNF\\[4\\].SENSE register. Write '1' to clear."] +pub type PIN4_R = crate::BitReader; +#[doc = "Status on whether PIN\\[4\\] +has met criteria set in PIN_CNF\\[4\\].SENSE register. Write '1' to clear.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN4_A { + #[doc = "0: Criteria has not been met"] + NOT_LATCHED = 0, + #[doc = "1: Criteria has been met"] + LATCHED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN4_A) -> Self { + variant as u8 != 0 + } +} +impl PIN4_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN4_A { + match self.bits { + false => PIN4_A::NOT_LATCHED, + true => PIN4_A::LATCHED, + } + } + #[doc = "Checks if the value of the field is `NOT_LATCHED`"] + #[inline(always)] + pub fn is_not_latched(&self) -> bool { + *self == PIN4_A::NOT_LATCHED + } + #[doc = "Checks if the value of the field is `LATCHED`"] + #[inline(always)] + pub fn is_latched(&self) -> bool { + *self == PIN4_A::LATCHED + } +} +#[doc = "Field `PIN4` writer - Status on whether PIN\\[4\\] +has met criteria set in PIN_CNF\\[4\\].SENSE register. Write '1' to clear."] +pub type PIN4_W<'a, const O: u8> = crate::BitWriter<'a, u32, LATCH_SPEC, PIN4_A, O>; +impl<'a, const O: u8> PIN4_W<'a, O> { + #[doc = "Criteria has not been met"] + #[inline(always)] + pub fn not_latched(self) -> &'a mut W { + self.variant(PIN4_A::NOT_LATCHED) + } + #[doc = "Criteria has been met"] + #[inline(always)] + pub fn latched(self) -> &'a mut W { + self.variant(PIN4_A::LATCHED) + } +} +#[doc = "Field `PIN5` reader - Status on whether PIN\\[5\\] +has met criteria set in PIN_CNF\\[5\\].SENSE register. Write '1' to clear."] +pub type PIN5_R = crate::BitReader; +#[doc = "Status on whether PIN\\[5\\] +has met criteria set in PIN_CNF\\[5\\].SENSE register. Write '1' to clear.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN5_A { + #[doc = "0: Criteria has not been met"] + NOT_LATCHED = 0, + #[doc = "1: Criteria has been met"] + LATCHED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN5_A) -> Self { + variant as u8 != 0 + } +} +impl PIN5_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN5_A { + match self.bits { + false => PIN5_A::NOT_LATCHED, + true => PIN5_A::LATCHED, + } + } + #[doc = "Checks if the value of the field is `NOT_LATCHED`"] + #[inline(always)] + pub fn is_not_latched(&self) -> bool { + *self == PIN5_A::NOT_LATCHED + } + #[doc = "Checks if the value of the field is `LATCHED`"] + #[inline(always)] + pub fn is_latched(&self) -> bool { + *self == PIN5_A::LATCHED + } +} +#[doc = "Field `PIN5` writer - Status on whether PIN\\[5\\] +has met criteria set in PIN_CNF\\[5\\].SENSE register. Write '1' to clear."] +pub type PIN5_W<'a, const O: u8> = crate::BitWriter<'a, u32, LATCH_SPEC, PIN5_A, O>; +impl<'a, const O: u8> PIN5_W<'a, O> { + #[doc = "Criteria has not been met"] + #[inline(always)] + pub fn not_latched(self) -> &'a mut W { + self.variant(PIN5_A::NOT_LATCHED) + } + #[doc = "Criteria has been met"] + #[inline(always)] + pub fn latched(self) -> &'a mut W { + self.variant(PIN5_A::LATCHED) + } +} +#[doc = "Field `PIN6` reader - Status on whether PIN\\[6\\] +has met criteria set in PIN_CNF\\[6\\].SENSE register. Write '1' to clear."] +pub type PIN6_R = crate::BitReader; +#[doc = "Status on whether PIN\\[6\\] +has met criteria set in PIN_CNF\\[6\\].SENSE register. Write '1' to clear.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN6_A { + #[doc = "0: Criteria has not been met"] + NOT_LATCHED = 0, + #[doc = "1: Criteria has been met"] + LATCHED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN6_A) -> Self { + variant as u8 != 0 + } +} +impl PIN6_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN6_A { + match self.bits { + false => PIN6_A::NOT_LATCHED, + true => PIN6_A::LATCHED, + } + } + #[doc = "Checks if the value of the field is `NOT_LATCHED`"] + #[inline(always)] + pub fn is_not_latched(&self) -> bool { + *self == PIN6_A::NOT_LATCHED + } + #[doc = "Checks if the value of the field is `LATCHED`"] + #[inline(always)] + pub fn is_latched(&self) -> bool { + *self == PIN6_A::LATCHED + } +} +#[doc = "Field `PIN6` writer - Status on whether PIN\\[6\\] +has met criteria set in PIN_CNF\\[6\\].SENSE register. Write '1' to clear."] +pub type PIN6_W<'a, const O: u8> = crate::BitWriter<'a, u32, LATCH_SPEC, PIN6_A, O>; +impl<'a, const O: u8> PIN6_W<'a, O> { + #[doc = "Criteria has not been met"] + #[inline(always)] + pub fn not_latched(self) -> &'a mut W { + self.variant(PIN6_A::NOT_LATCHED) + } + #[doc = "Criteria has been met"] + #[inline(always)] + pub fn latched(self) -> &'a mut W { + self.variant(PIN6_A::LATCHED) + } +} +#[doc = "Field `PIN7` reader - Status on whether PIN\\[7\\] +has met criteria set in PIN_CNF\\[7\\].SENSE register. Write '1' to clear."] +pub type PIN7_R = crate::BitReader; +#[doc = "Status on whether PIN\\[7\\] +has met criteria set in PIN_CNF\\[7\\].SENSE register. Write '1' to clear.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN7_A { + #[doc = "0: Criteria has not been met"] + NOT_LATCHED = 0, + #[doc = "1: Criteria has been met"] + LATCHED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN7_A) -> Self { + variant as u8 != 0 + } +} +impl PIN7_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN7_A { + match self.bits { + false => PIN7_A::NOT_LATCHED, + true => PIN7_A::LATCHED, + } + } + #[doc = "Checks if the value of the field is `NOT_LATCHED`"] + #[inline(always)] + pub fn is_not_latched(&self) -> bool { + *self == PIN7_A::NOT_LATCHED + } + #[doc = "Checks if the value of the field is `LATCHED`"] + #[inline(always)] + pub fn is_latched(&self) -> bool { + *self == PIN7_A::LATCHED + } +} +#[doc = "Field `PIN7` writer - Status on whether PIN\\[7\\] +has met criteria set in PIN_CNF\\[7\\].SENSE register. Write '1' to clear."] +pub type PIN7_W<'a, const O: u8> = crate::BitWriter<'a, u32, LATCH_SPEC, PIN7_A, O>; +impl<'a, const O: u8> PIN7_W<'a, O> { + #[doc = "Criteria has not been met"] + #[inline(always)] + pub fn not_latched(self) -> &'a mut W { + self.variant(PIN7_A::NOT_LATCHED) + } + #[doc = "Criteria has been met"] + #[inline(always)] + pub fn latched(self) -> &'a mut W { + self.variant(PIN7_A::LATCHED) + } +} +#[doc = "Field `PIN8` reader - Status on whether PIN\\[8\\] +has met criteria set in PIN_CNF\\[8\\].SENSE register. Write '1' to clear."] +pub type PIN8_R = crate::BitReader; +#[doc = "Status on whether PIN\\[8\\] +has met criteria set in PIN_CNF\\[8\\].SENSE register. Write '1' to clear.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN8_A { + #[doc = "0: Criteria has not been met"] + NOT_LATCHED = 0, + #[doc = "1: Criteria has been met"] + LATCHED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN8_A) -> Self { + variant as u8 != 0 + } +} +impl PIN8_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN8_A { + match self.bits { + false => PIN8_A::NOT_LATCHED, + true => PIN8_A::LATCHED, + } + } + #[doc = "Checks if the value of the field is `NOT_LATCHED`"] + #[inline(always)] + pub fn is_not_latched(&self) -> bool { + *self == PIN8_A::NOT_LATCHED + } + #[doc = "Checks if the value of the field is `LATCHED`"] + #[inline(always)] + pub fn is_latched(&self) -> bool { + *self == PIN8_A::LATCHED + } +} +#[doc = "Field `PIN8` writer - Status on whether PIN\\[8\\] +has met criteria set in PIN_CNF\\[8\\].SENSE register. Write '1' to clear."] +pub type PIN8_W<'a, const O: u8> = crate::BitWriter<'a, u32, LATCH_SPEC, PIN8_A, O>; +impl<'a, const O: u8> PIN8_W<'a, O> { + #[doc = "Criteria has not been met"] + #[inline(always)] + pub fn not_latched(self) -> &'a mut W { + self.variant(PIN8_A::NOT_LATCHED) + } + #[doc = "Criteria has been met"] + #[inline(always)] + pub fn latched(self) -> &'a mut W { + self.variant(PIN8_A::LATCHED) + } +} +#[doc = "Field `PIN9` reader - Status on whether PIN\\[9\\] +has met criteria set in PIN_CNF\\[9\\].SENSE register. Write '1' to clear."] +pub type PIN9_R = crate::BitReader; +#[doc = "Status on whether PIN\\[9\\] +has met criteria set in PIN_CNF\\[9\\].SENSE register. Write '1' to clear.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN9_A { + #[doc = "0: Criteria has not been met"] + NOT_LATCHED = 0, + #[doc = "1: Criteria has been met"] + LATCHED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN9_A) -> Self { + variant as u8 != 0 + } +} +impl PIN9_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN9_A { + match self.bits { + false => PIN9_A::NOT_LATCHED, + true => PIN9_A::LATCHED, + } + } + #[doc = "Checks if the value of the field is `NOT_LATCHED`"] + #[inline(always)] + pub fn is_not_latched(&self) -> bool { + *self == PIN9_A::NOT_LATCHED + } + #[doc = "Checks if the value of the field is `LATCHED`"] + #[inline(always)] + pub fn is_latched(&self) -> bool { + *self == PIN9_A::LATCHED + } +} +#[doc = "Field `PIN9` writer - Status on whether PIN\\[9\\] +has met criteria set in PIN_CNF\\[9\\].SENSE register. Write '1' to clear."] +pub type PIN9_W<'a, const O: u8> = crate::BitWriter<'a, u32, LATCH_SPEC, PIN9_A, O>; +impl<'a, const O: u8> PIN9_W<'a, O> { + #[doc = "Criteria has not been met"] + #[inline(always)] + pub fn not_latched(self) -> &'a mut W { + self.variant(PIN9_A::NOT_LATCHED) + } + #[doc = "Criteria has been met"] + #[inline(always)] + pub fn latched(self) -> &'a mut W { + self.variant(PIN9_A::LATCHED) + } +} +#[doc = "Field `PIN10` reader - Status on whether PIN\\[10\\] +has met criteria set in PIN_CNF\\[10\\].SENSE register. Write '1' to clear."] +pub type PIN10_R = crate::BitReader; +#[doc = "Status on whether PIN\\[10\\] +has met criteria set in PIN_CNF\\[10\\].SENSE register. Write '1' to clear.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN10_A { + #[doc = "0: Criteria has not been met"] + NOT_LATCHED = 0, + #[doc = "1: Criteria has been met"] + LATCHED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN10_A) -> Self { + variant as u8 != 0 + } +} +impl PIN10_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN10_A { + match self.bits { + false => PIN10_A::NOT_LATCHED, + true => PIN10_A::LATCHED, + } + } + #[doc = "Checks if the value of the field is `NOT_LATCHED`"] + #[inline(always)] + pub fn is_not_latched(&self) -> bool { + *self == PIN10_A::NOT_LATCHED + } + #[doc = "Checks if the value of the field is `LATCHED`"] + #[inline(always)] + pub fn is_latched(&self) -> bool { + *self == PIN10_A::LATCHED + } +} +#[doc = "Field `PIN10` writer - Status on whether PIN\\[10\\] +has met criteria set in PIN_CNF\\[10\\].SENSE register. Write '1' to clear."] +pub type PIN10_W<'a, const O: u8> = crate::BitWriter<'a, u32, LATCH_SPEC, PIN10_A, O>; +impl<'a, const O: u8> PIN10_W<'a, O> { + #[doc = "Criteria has not been met"] + #[inline(always)] + pub fn not_latched(self) -> &'a mut W { + self.variant(PIN10_A::NOT_LATCHED) + } + #[doc = "Criteria has been met"] + #[inline(always)] + pub fn latched(self) -> &'a mut W { + self.variant(PIN10_A::LATCHED) + } +} +#[doc = "Field `PIN11` reader - Status on whether PIN\\[11\\] +has met criteria set in PIN_CNF\\[11\\].SENSE register. Write '1' to clear."] +pub type PIN11_R = crate::BitReader; +#[doc = "Status on whether PIN\\[11\\] +has met criteria set in PIN_CNF\\[11\\].SENSE register. Write '1' to clear.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN11_A { + #[doc = "0: Criteria has not been met"] + NOT_LATCHED = 0, + #[doc = "1: Criteria has been met"] + LATCHED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN11_A) -> Self { + variant as u8 != 0 + } +} +impl PIN11_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN11_A { + match self.bits { + false => PIN11_A::NOT_LATCHED, + true => PIN11_A::LATCHED, + } + } + #[doc = "Checks if the value of the field is `NOT_LATCHED`"] + #[inline(always)] + pub fn is_not_latched(&self) -> bool { + *self == PIN11_A::NOT_LATCHED + } + #[doc = "Checks if the value of the field is `LATCHED`"] + #[inline(always)] + pub fn is_latched(&self) -> bool { + *self == PIN11_A::LATCHED + } +} +#[doc = "Field `PIN11` writer - Status on whether PIN\\[11\\] +has met criteria set in PIN_CNF\\[11\\].SENSE register. Write '1' to clear."] +pub type PIN11_W<'a, const O: u8> = crate::BitWriter<'a, u32, LATCH_SPEC, PIN11_A, O>; +impl<'a, const O: u8> PIN11_W<'a, O> { + #[doc = "Criteria has not been met"] + #[inline(always)] + pub fn not_latched(self) -> &'a mut W { + self.variant(PIN11_A::NOT_LATCHED) + } + #[doc = "Criteria has been met"] + #[inline(always)] + pub fn latched(self) -> &'a mut W { + self.variant(PIN11_A::LATCHED) + } +} +#[doc = "Field `PIN12` reader - Status on whether PIN\\[12\\] +has met criteria set in PIN_CNF\\[12\\].SENSE register. Write '1' to clear."] +pub type PIN12_R = crate::BitReader; +#[doc = "Status on whether PIN\\[12\\] +has met criteria set in PIN_CNF\\[12\\].SENSE register. Write '1' to clear.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN12_A { + #[doc = "0: Criteria has not been met"] + NOT_LATCHED = 0, + #[doc = "1: Criteria has been met"] + LATCHED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN12_A) -> Self { + variant as u8 != 0 + } +} +impl PIN12_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN12_A { + match self.bits { + false => PIN12_A::NOT_LATCHED, + true => PIN12_A::LATCHED, + } + } + #[doc = "Checks if the value of the field is `NOT_LATCHED`"] + #[inline(always)] + pub fn is_not_latched(&self) -> bool { + *self == PIN12_A::NOT_LATCHED + } + #[doc = "Checks if the value of the field is `LATCHED`"] + #[inline(always)] + pub fn is_latched(&self) -> bool { + *self == PIN12_A::LATCHED + } +} +#[doc = "Field `PIN12` writer - Status on whether PIN\\[12\\] +has met criteria set in PIN_CNF\\[12\\].SENSE register. Write '1' to clear."] +pub type PIN12_W<'a, const O: u8> = crate::BitWriter<'a, u32, LATCH_SPEC, PIN12_A, O>; +impl<'a, const O: u8> PIN12_W<'a, O> { + #[doc = "Criteria has not been met"] + #[inline(always)] + pub fn not_latched(self) -> &'a mut W { + self.variant(PIN12_A::NOT_LATCHED) + } + #[doc = "Criteria has been met"] + #[inline(always)] + pub fn latched(self) -> &'a mut W { + self.variant(PIN12_A::LATCHED) + } +} +#[doc = "Field `PIN13` reader - Status on whether PIN\\[13\\] +has met criteria set in PIN_CNF\\[13\\].SENSE register. Write '1' to clear."] +pub type PIN13_R = crate::BitReader; +#[doc = "Status on whether PIN\\[13\\] +has met criteria set in PIN_CNF\\[13\\].SENSE register. Write '1' to clear.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN13_A { + #[doc = "0: Criteria has not been met"] + NOT_LATCHED = 0, + #[doc = "1: Criteria has been met"] + LATCHED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN13_A) -> Self { + variant as u8 != 0 + } +} +impl PIN13_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN13_A { + match self.bits { + false => PIN13_A::NOT_LATCHED, + true => PIN13_A::LATCHED, + } + } + #[doc = "Checks if the value of the field is `NOT_LATCHED`"] + #[inline(always)] + pub fn is_not_latched(&self) -> bool { + *self == PIN13_A::NOT_LATCHED + } + #[doc = "Checks if the value of the field is `LATCHED`"] + #[inline(always)] + pub fn is_latched(&self) -> bool { + *self == PIN13_A::LATCHED + } +} +#[doc = "Field `PIN13` writer - Status on whether PIN\\[13\\] +has met criteria set in PIN_CNF\\[13\\].SENSE register. Write '1' to clear."] +pub type PIN13_W<'a, const O: u8> = crate::BitWriter<'a, u32, LATCH_SPEC, PIN13_A, O>; +impl<'a, const O: u8> PIN13_W<'a, O> { + #[doc = "Criteria has not been met"] + #[inline(always)] + pub fn not_latched(self) -> &'a mut W { + self.variant(PIN13_A::NOT_LATCHED) + } + #[doc = "Criteria has been met"] + #[inline(always)] + pub fn latched(self) -> &'a mut W { + self.variant(PIN13_A::LATCHED) + } +} +#[doc = "Field `PIN14` reader - Status on whether PIN\\[14\\] +has met criteria set in PIN_CNF\\[14\\].SENSE register. Write '1' to clear."] +pub type PIN14_R = crate::BitReader; +#[doc = "Status on whether PIN\\[14\\] +has met criteria set in PIN_CNF\\[14\\].SENSE register. Write '1' to clear.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN14_A { + #[doc = "0: Criteria has not been met"] + NOT_LATCHED = 0, + #[doc = "1: Criteria has been met"] + LATCHED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN14_A) -> Self { + variant as u8 != 0 + } +} +impl PIN14_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN14_A { + match self.bits { + false => PIN14_A::NOT_LATCHED, + true => PIN14_A::LATCHED, + } + } + #[doc = "Checks if the value of the field is `NOT_LATCHED`"] + #[inline(always)] + pub fn is_not_latched(&self) -> bool { + *self == PIN14_A::NOT_LATCHED + } + #[doc = "Checks if the value of the field is `LATCHED`"] + #[inline(always)] + pub fn is_latched(&self) -> bool { + *self == PIN14_A::LATCHED + } +} +#[doc = "Field `PIN14` writer - Status on whether PIN\\[14\\] +has met criteria set in PIN_CNF\\[14\\].SENSE register. Write '1' to clear."] +pub type PIN14_W<'a, const O: u8> = crate::BitWriter<'a, u32, LATCH_SPEC, PIN14_A, O>; +impl<'a, const O: u8> PIN14_W<'a, O> { + #[doc = "Criteria has not been met"] + #[inline(always)] + pub fn not_latched(self) -> &'a mut W { + self.variant(PIN14_A::NOT_LATCHED) + } + #[doc = "Criteria has been met"] + #[inline(always)] + pub fn latched(self) -> &'a mut W { + self.variant(PIN14_A::LATCHED) + } +} +#[doc = "Field `PIN15` reader - Status on whether PIN\\[15\\] +has met criteria set in PIN_CNF\\[15\\].SENSE register. Write '1' to clear."] +pub type PIN15_R = crate::BitReader; +#[doc = "Status on whether PIN\\[15\\] +has met criteria set in PIN_CNF\\[15\\].SENSE register. Write '1' to clear.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN15_A { + #[doc = "0: Criteria has not been met"] + NOT_LATCHED = 0, + #[doc = "1: Criteria has been met"] + LATCHED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN15_A) -> Self { + variant as u8 != 0 + } +} +impl PIN15_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN15_A { + match self.bits { + false => PIN15_A::NOT_LATCHED, + true => PIN15_A::LATCHED, + } + } + #[doc = "Checks if the value of the field is `NOT_LATCHED`"] + #[inline(always)] + pub fn is_not_latched(&self) -> bool { + *self == PIN15_A::NOT_LATCHED + } + #[doc = "Checks if the value of the field is `LATCHED`"] + #[inline(always)] + pub fn is_latched(&self) -> bool { + *self == PIN15_A::LATCHED + } +} +#[doc = "Field `PIN15` writer - Status on whether PIN\\[15\\] +has met criteria set in PIN_CNF\\[15\\].SENSE register. Write '1' to clear."] +pub type PIN15_W<'a, const O: u8> = crate::BitWriter<'a, u32, LATCH_SPEC, PIN15_A, O>; +impl<'a, const O: u8> PIN15_W<'a, O> { + #[doc = "Criteria has not been met"] + #[inline(always)] + pub fn not_latched(self) -> &'a mut W { + self.variant(PIN15_A::NOT_LATCHED) + } + #[doc = "Criteria has been met"] + #[inline(always)] + pub fn latched(self) -> &'a mut W { + self.variant(PIN15_A::LATCHED) + } +} +#[doc = "Field `PIN16` reader - Status on whether PIN\\[16\\] +has met criteria set in PIN_CNF\\[16\\].SENSE register. Write '1' to clear."] +pub type PIN16_R = crate::BitReader; +#[doc = "Status on whether PIN\\[16\\] +has met criteria set in PIN_CNF\\[16\\].SENSE register. Write '1' to clear.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN16_A { + #[doc = "0: Criteria has not been met"] + NOT_LATCHED = 0, + #[doc = "1: Criteria has been met"] + LATCHED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN16_A) -> Self { + variant as u8 != 0 + } +} +impl PIN16_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN16_A { + match self.bits { + false => PIN16_A::NOT_LATCHED, + true => PIN16_A::LATCHED, + } + } + #[doc = "Checks if the value of the field is `NOT_LATCHED`"] + #[inline(always)] + pub fn is_not_latched(&self) -> bool { + *self == PIN16_A::NOT_LATCHED + } + #[doc = "Checks if the value of the field is `LATCHED`"] + #[inline(always)] + pub fn is_latched(&self) -> bool { + *self == PIN16_A::LATCHED + } +} +#[doc = "Field `PIN16` writer - Status on whether PIN\\[16\\] +has met criteria set in PIN_CNF\\[16\\].SENSE register. Write '1' to clear."] +pub type PIN16_W<'a, const O: u8> = crate::BitWriter<'a, u32, LATCH_SPEC, PIN16_A, O>; +impl<'a, const O: u8> PIN16_W<'a, O> { + #[doc = "Criteria has not been met"] + #[inline(always)] + pub fn not_latched(self) -> &'a mut W { + self.variant(PIN16_A::NOT_LATCHED) + } + #[doc = "Criteria has been met"] + #[inline(always)] + pub fn latched(self) -> &'a mut W { + self.variant(PIN16_A::LATCHED) + } +} +#[doc = "Field `PIN17` reader - Status on whether PIN\\[17\\] +has met criteria set in PIN_CNF\\[17\\].SENSE register. Write '1' to clear."] +pub type PIN17_R = crate::BitReader; +#[doc = "Status on whether PIN\\[17\\] +has met criteria set in PIN_CNF\\[17\\].SENSE register. Write '1' to clear.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN17_A { + #[doc = "0: Criteria has not been met"] + NOT_LATCHED = 0, + #[doc = "1: Criteria has been met"] + LATCHED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN17_A) -> Self { + variant as u8 != 0 + } +} +impl PIN17_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN17_A { + match self.bits { + false => PIN17_A::NOT_LATCHED, + true => PIN17_A::LATCHED, + } + } + #[doc = "Checks if the value of the field is `NOT_LATCHED`"] + #[inline(always)] + pub fn is_not_latched(&self) -> bool { + *self == PIN17_A::NOT_LATCHED + } + #[doc = "Checks if the value of the field is `LATCHED`"] + #[inline(always)] + pub fn is_latched(&self) -> bool { + *self == PIN17_A::LATCHED + } +} +#[doc = "Field `PIN17` writer - Status on whether PIN\\[17\\] +has met criteria set in PIN_CNF\\[17\\].SENSE register. Write '1' to clear."] +pub type PIN17_W<'a, const O: u8> = crate::BitWriter<'a, u32, LATCH_SPEC, PIN17_A, O>; +impl<'a, const O: u8> PIN17_W<'a, O> { + #[doc = "Criteria has not been met"] + #[inline(always)] + pub fn not_latched(self) -> &'a mut W { + self.variant(PIN17_A::NOT_LATCHED) + } + #[doc = "Criteria has been met"] + #[inline(always)] + pub fn latched(self) -> &'a mut W { + self.variant(PIN17_A::LATCHED) + } +} +#[doc = "Field `PIN18` reader - Status on whether PIN\\[18\\] +has met criteria set in PIN_CNF\\[18\\].SENSE register. Write '1' to clear."] +pub type PIN18_R = crate::BitReader; +#[doc = "Status on whether PIN\\[18\\] +has met criteria set in PIN_CNF\\[18\\].SENSE register. Write '1' to clear.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN18_A { + #[doc = "0: Criteria has not been met"] + NOT_LATCHED = 0, + #[doc = "1: Criteria has been met"] + LATCHED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN18_A) -> Self { + variant as u8 != 0 + } +} +impl PIN18_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN18_A { + match self.bits { + false => PIN18_A::NOT_LATCHED, + true => PIN18_A::LATCHED, + } + } + #[doc = "Checks if the value of the field is `NOT_LATCHED`"] + #[inline(always)] + pub fn is_not_latched(&self) -> bool { + *self == PIN18_A::NOT_LATCHED + } + #[doc = "Checks if the value of the field is `LATCHED`"] + #[inline(always)] + pub fn is_latched(&self) -> bool { + *self == PIN18_A::LATCHED + } +} +#[doc = "Field `PIN18` writer - Status on whether PIN\\[18\\] +has met criteria set in PIN_CNF\\[18\\].SENSE register. Write '1' to clear."] +pub type PIN18_W<'a, const O: u8> = crate::BitWriter<'a, u32, LATCH_SPEC, PIN18_A, O>; +impl<'a, const O: u8> PIN18_W<'a, O> { + #[doc = "Criteria has not been met"] + #[inline(always)] + pub fn not_latched(self) -> &'a mut W { + self.variant(PIN18_A::NOT_LATCHED) + } + #[doc = "Criteria has been met"] + #[inline(always)] + pub fn latched(self) -> &'a mut W { + self.variant(PIN18_A::LATCHED) + } +} +#[doc = "Field `PIN19` reader - Status on whether PIN\\[19\\] +has met criteria set in PIN_CNF\\[19\\].SENSE register. Write '1' to clear."] +pub type PIN19_R = crate::BitReader; +#[doc = "Status on whether PIN\\[19\\] +has met criteria set in PIN_CNF\\[19\\].SENSE register. Write '1' to clear.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN19_A { + #[doc = "0: Criteria has not been met"] + NOT_LATCHED = 0, + #[doc = "1: Criteria has been met"] + LATCHED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN19_A) -> Self { + variant as u8 != 0 + } +} +impl PIN19_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN19_A { + match self.bits { + false => PIN19_A::NOT_LATCHED, + true => PIN19_A::LATCHED, + } + } + #[doc = "Checks if the value of the field is `NOT_LATCHED`"] + #[inline(always)] + pub fn is_not_latched(&self) -> bool { + *self == PIN19_A::NOT_LATCHED + } + #[doc = "Checks if the value of the field is `LATCHED`"] + #[inline(always)] + pub fn is_latched(&self) -> bool { + *self == PIN19_A::LATCHED + } +} +#[doc = "Field `PIN19` writer - Status on whether PIN\\[19\\] +has met criteria set in PIN_CNF\\[19\\].SENSE register. Write '1' to clear."] +pub type PIN19_W<'a, const O: u8> = crate::BitWriter<'a, u32, LATCH_SPEC, PIN19_A, O>; +impl<'a, const O: u8> PIN19_W<'a, O> { + #[doc = "Criteria has not been met"] + #[inline(always)] + pub fn not_latched(self) -> &'a mut W { + self.variant(PIN19_A::NOT_LATCHED) + } + #[doc = "Criteria has been met"] + #[inline(always)] + pub fn latched(self) -> &'a mut W { + self.variant(PIN19_A::LATCHED) + } +} +#[doc = "Field `PIN20` reader - Status on whether PIN\\[20\\] +has met criteria set in PIN_CNF\\[20\\].SENSE register. Write '1' to clear."] +pub type PIN20_R = crate::BitReader; +#[doc = "Status on whether PIN\\[20\\] +has met criteria set in PIN_CNF\\[20\\].SENSE register. Write '1' to clear.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN20_A { + #[doc = "0: Criteria has not been met"] + NOT_LATCHED = 0, + #[doc = "1: Criteria has been met"] + LATCHED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN20_A) -> Self { + variant as u8 != 0 + } +} +impl PIN20_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN20_A { + match self.bits { + false => PIN20_A::NOT_LATCHED, + true => PIN20_A::LATCHED, + } + } + #[doc = "Checks if the value of the field is `NOT_LATCHED`"] + #[inline(always)] + pub fn is_not_latched(&self) -> bool { + *self == PIN20_A::NOT_LATCHED + } + #[doc = "Checks if the value of the field is `LATCHED`"] + #[inline(always)] + pub fn is_latched(&self) -> bool { + *self == PIN20_A::LATCHED + } +} +#[doc = "Field `PIN20` writer - Status on whether PIN\\[20\\] +has met criteria set in PIN_CNF\\[20\\].SENSE register. Write '1' to clear."] +pub type PIN20_W<'a, const O: u8> = crate::BitWriter<'a, u32, LATCH_SPEC, PIN20_A, O>; +impl<'a, const O: u8> PIN20_W<'a, O> { + #[doc = "Criteria has not been met"] + #[inline(always)] + pub fn not_latched(self) -> &'a mut W { + self.variant(PIN20_A::NOT_LATCHED) + } + #[doc = "Criteria has been met"] + #[inline(always)] + pub fn latched(self) -> &'a mut W { + self.variant(PIN20_A::LATCHED) + } +} +#[doc = "Field `PIN21` reader - Status on whether PIN\\[21\\] +has met criteria set in PIN_CNF\\[21\\].SENSE register. Write '1' to clear."] +pub type PIN21_R = crate::BitReader; +#[doc = "Status on whether PIN\\[21\\] +has met criteria set in PIN_CNF\\[21\\].SENSE register. Write '1' to clear.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN21_A { + #[doc = "0: Criteria has not been met"] + NOT_LATCHED = 0, + #[doc = "1: Criteria has been met"] + LATCHED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN21_A) -> Self { + variant as u8 != 0 + } +} +impl PIN21_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN21_A { + match self.bits { + false => PIN21_A::NOT_LATCHED, + true => PIN21_A::LATCHED, + } + } + #[doc = "Checks if the value of the field is `NOT_LATCHED`"] + #[inline(always)] + pub fn is_not_latched(&self) -> bool { + *self == PIN21_A::NOT_LATCHED + } + #[doc = "Checks if the value of the field is `LATCHED`"] + #[inline(always)] + pub fn is_latched(&self) -> bool { + *self == PIN21_A::LATCHED + } +} +#[doc = "Field `PIN21` writer - Status on whether PIN\\[21\\] +has met criteria set in PIN_CNF\\[21\\].SENSE register. Write '1' to clear."] +pub type PIN21_W<'a, const O: u8> = crate::BitWriter<'a, u32, LATCH_SPEC, PIN21_A, O>; +impl<'a, const O: u8> PIN21_W<'a, O> { + #[doc = "Criteria has not been met"] + #[inline(always)] + pub fn not_latched(self) -> &'a mut W { + self.variant(PIN21_A::NOT_LATCHED) + } + #[doc = "Criteria has been met"] + #[inline(always)] + pub fn latched(self) -> &'a mut W { + self.variant(PIN21_A::LATCHED) + } +} +#[doc = "Field `PIN22` reader - Status on whether PIN\\[22\\] +has met criteria set in PIN_CNF\\[22\\].SENSE register. Write '1' to clear."] +pub type PIN22_R = crate::BitReader; +#[doc = "Status on whether PIN\\[22\\] +has met criteria set in PIN_CNF\\[22\\].SENSE register. Write '1' to clear.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN22_A { + #[doc = "0: Criteria has not been met"] + NOT_LATCHED = 0, + #[doc = "1: Criteria has been met"] + LATCHED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN22_A) -> Self { + variant as u8 != 0 + } +} +impl PIN22_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN22_A { + match self.bits { + false => PIN22_A::NOT_LATCHED, + true => PIN22_A::LATCHED, + } + } + #[doc = "Checks if the value of the field is `NOT_LATCHED`"] + #[inline(always)] + pub fn is_not_latched(&self) -> bool { + *self == PIN22_A::NOT_LATCHED + } + #[doc = "Checks if the value of the field is `LATCHED`"] + #[inline(always)] + pub fn is_latched(&self) -> bool { + *self == PIN22_A::LATCHED + } +} +#[doc = "Field `PIN22` writer - Status on whether PIN\\[22\\] +has met criteria set in PIN_CNF\\[22\\].SENSE register. Write '1' to clear."] +pub type PIN22_W<'a, const O: u8> = crate::BitWriter<'a, u32, LATCH_SPEC, PIN22_A, O>; +impl<'a, const O: u8> PIN22_W<'a, O> { + #[doc = "Criteria has not been met"] + #[inline(always)] + pub fn not_latched(self) -> &'a mut W { + self.variant(PIN22_A::NOT_LATCHED) + } + #[doc = "Criteria has been met"] + #[inline(always)] + pub fn latched(self) -> &'a mut W { + self.variant(PIN22_A::LATCHED) + } +} +#[doc = "Field `PIN23` reader - Status on whether PIN\\[23\\] +has met criteria set in PIN_CNF\\[23\\].SENSE register. Write '1' to clear."] +pub type PIN23_R = crate::BitReader; +#[doc = "Status on whether PIN\\[23\\] +has met criteria set in PIN_CNF\\[23\\].SENSE register. Write '1' to clear.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN23_A { + #[doc = "0: Criteria has not been met"] + NOT_LATCHED = 0, + #[doc = "1: Criteria has been met"] + LATCHED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN23_A) -> Self { + variant as u8 != 0 + } +} +impl PIN23_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN23_A { + match self.bits { + false => PIN23_A::NOT_LATCHED, + true => PIN23_A::LATCHED, + } + } + #[doc = "Checks if the value of the field is `NOT_LATCHED`"] + #[inline(always)] + pub fn is_not_latched(&self) -> bool { + *self == PIN23_A::NOT_LATCHED + } + #[doc = "Checks if the value of the field is `LATCHED`"] + #[inline(always)] + pub fn is_latched(&self) -> bool { + *self == PIN23_A::LATCHED + } +} +#[doc = "Field `PIN23` writer - Status on whether PIN\\[23\\] +has met criteria set in PIN_CNF\\[23\\].SENSE register. Write '1' to clear."] +pub type PIN23_W<'a, const O: u8> = crate::BitWriter<'a, u32, LATCH_SPEC, PIN23_A, O>; +impl<'a, const O: u8> PIN23_W<'a, O> { + #[doc = "Criteria has not been met"] + #[inline(always)] + pub fn not_latched(self) -> &'a mut W { + self.variant(PIN23_A::NOT_LATCHED) + } + #[doc = "Criteria has been met"] + #[inline(always)] + pub fn latched(self) -> &'a mut W { + self.variant(PIN23_A::LATCHED) + } +} +#[doc = "Field `PIN24` reader - Status on whether PIN\\[24\\] +has met criteria set in PIN_CNF\\[24\\].SENSE register. Write '1' to clear."] +pub type PIN24_R = crate::BitReader; +#[doc = "Status on whether PIN\\[24\\] +has met criteria set in PIN_CNF\\[24\\].SENSE register. Write '1' to clear.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN24_A { + #[doc = "0: Criteria has not been met"] + NOT_LATCHED = 0, + #[doc = "1: Criteria has been met"] + LATCHED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN24_A) -> Self { + variant as u8 != 0 + } +} +impl PIN24_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN24_A { + match self.bits { + false => PIN24_A::NOT_LATCHED, + true => PIN24_A::LATCHED, + } + } + #[doc = "Checks if the value of the field is `NOT_LATCHED`"] + #[inline(always)] + pub fn is_not_latched(&self) -> bool { + *self == PIN24_A::NOT_LATCHED + } + #[doc = "Checks if the value of the field is `LATCHED`"] + #[inline(always)] + pub fn is_latched(&self) -> bool { + *self == PIN24_A::LATCHED + } +} +#[doc = "Field `PIN24` writer - Status on whether PIN\\[24\\] +has met criteria set in PIN_CNF\\[24\\].SENSE register. Write '1' to clear."] +pub type PIN24_W<'a, const O: u8> = crate::BitWriter<'a, u32, LATCH_SPEC, PIN24_A, O>; +impl<'a, const O: u8> PIN24_W<'a, O> { + #[doc = "Criteria has not been met"] + #[inline(always)] + pub fn not_latched(self) -> &'a mut W { + self.variant(PIN24_A::NOT_LATCHED) + } + #[doc = "Criteria has been met"] + #[inline(always)] + pub fn latched(self) -> &'a mut W { + self.variant(PIN24_A::LATCHED) + } +} +#[doc = "Field `PIN25` reader - Status on whether PIN\\[25\\] +has met criteria set in PIN_CNF\\[25\\].SENSE register. Write '1' to clear."] +pub type PIN25_R = crate::BitReader; +#[doc = "Status on whether PIN\\[25\\] +has met criteria set in PIN_CNF\\[25\\].SENSE register. Write '1' to clear.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN25_A { + #[doc = "0: Criteria has not been met"] + NOT_LATCHED = 0, + #[doc = "1: Criteria has been met"] + LATCHED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN25_A) -> Self { + variant as u8 != 0 + } +} +impl PIN25_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN25_A { + match self.bits { + false => PIN25_A::NOT_LATCHED, + true => PIN25_A::LATCHED, + } + } + #[doc = "Checks if the value of the field is `NOT_LATCHED`"] + #[inline(always)] + pub fn is_not_latched(&self) -> bool { + *self == PIN25_A::NOT_LATCHED + } + #[doc = "Checks if the value of the field is `LATCHED`"] + #[inline(always)] + pub fn is_latched(&self) -> bool { + *self == PIN25_A::LATCHED + } +} +#[doc = "Field `PIN25` writer - Status on whether PIN\\[25\\] +has met criteria set in PIN_CNF\\[25\\].SENSE register. Write '1' to clear."] +pub type PIN25_W<'a, const O: u8> = crate::BitWriter<'a, u32, LATCH_SPEC, PIN25_A, O>; +impl<'a, const O: u8> PIN25_W<'a, O> { + #[doc = "Criteria has not been met"] + #[inline(always)] + pub fn not_latched(self) -> &'a mut W { + self.variant(PIN25_A::NOT_LATCHED) + } + #[doc = "Criteria has been met"] + #[inline(always)] + pub fn latched(self) -> &'a mut W { + self.variant(PIN25_A::LATCHED) + } +} +#[doc = "Field `PIN26` reader - Status on whether PIN\\[26\\] +has met criteria set in PIN_CNF\\[26\\].SENSE register. Write '1' to clear."] +pub type PIN26_R = crate::BitReader; +#[doc = "Status on whether PIN\\[26\\] +has met criteria set in PIN_CNF\\[26\\].SENSE register. Write '1' to clear.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN26_A { + #[doc = "0: Criteria has not been met"] + NOT_LATCHED = 0, + #[doc = "1: Criteria has been met"] + LATCHED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN26_A) -> Self { + variant as u8 != 0 + } +} +impl PIN26_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN26_A { + match self.bits { + false => PIN26_A::NOT_LATCHED, + true => PIN26_A::LATCHED, + } + } + #[doc = "Checks if the value of the field is `NOT_LATCHED`"] + #[inline(always)] + pub fn is_not_latched(&self) -> bool { + *self == PIN26_A::NOT_LATCHED + } + #[doc = "Checks if the value of the field is `LATCHED`"] + #[inline(always)] + pub fn is_latched(&self) -> bool { + *self == PIN26_A::LATCHED + } +} +#[doc = "Field `PIN26` writer - Status on whether PIN\\[26\\] +has met criteria set in PIN_CNF\\[26\\].SENSE register. Write '1' to clear."] +pub type PIN26_W<'a, const O: u8> = crate::BitWriter<'a, u32, LATCH_SPEC, PIN26_A, O>; +impl<'a, const O: u8> PIN26_W<'a, O> { + #[doc = "Criteria has not been met"] + #[inline(always)] + pub fn not_latched(self) -> &'a mut W { + self.variant(PIN26_A::NOT_LATCHED) + } + #[doc = "Criteria has been met"] + #[inline(always)] + pub fn latched(self) -> &'a mut W { + self.variant(PIN26_A::LATCHED) + } +} +#[doc = "Field `PIN27` reader - Status on whether PIN\\[27\\] +has met criteria set in PIN_CNF\\[27\\].SENSE register. Write '1' to clear."] +pub type PIN27_R = crate::BitReader; +#[doc = "Status on whether PIN\\[27\\] +has met criteria set in PIN_CNF\\[27\\].SENSE register. Write '1' to clear.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN27_A { + #[doc = "0: Criteria has not been met"] + NOT_LATCHED = 0, + #[doc = "1: Criteria has been met"] + LATCHED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN27_A) -> Self { + variant as u8 != 0 + } +} +impl PIN27_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN27_A { + match self.bits { + false => PIN27_A::NOT_LATCHED, + true => PIN27_A::LATCHED, + } + } + #[doc = "Checks if the value of the field is `NOT_LATCHED`"] + #[inline(always)] + pub fn is_not_latched(&self) -> bool { + *self == PIN27_A::NOT_LATCHED + } + #[doc = "Checks if the value of the field is `LATCHED`"] + #[inline(always)] + pub fn is_latched(&self) -> bool { + *self == PIN27_A::LATCHED + } +} +#[doc = "Field `PIN27` writer - Status on whether PIN\\[27\\] +has met criteria set in PIN_CNF\\[27\\].SENSE register. Write '1' to clear."] +pub type PIN27_W<'a, const O: u8> = crate::BitWriter<'a, u32, LATCH_SPEC, PIN27_A, O>; +impl<'a, const O: u8> PIN27_W<'a, O> { + #[doc = "Criteria has not been met"] + #[inline(always)] + pub fn not_latched(self) -> &'a mut W { + self.variant(PIN27_A::NOT_LATCHED) + } + #[doc = "Criteria has been met"] + #[inline(always)] + pub fn latched(self) -> &'a mut W { + self.variant(PIN27_A::LATCHED) + } +} +#[doc = "Field `PIN28` reader - Status on whether PIN\\[28\\] +has met criteria set in PIN_CNF\\[28\\].SENSE register. Write '1' to clear."] +pub type PIN28_R = crate::BitReader; +#[doc = "Status on whether PIN\\[28\\] +has met criteria set in PIN_CNF\\[28\\].SENSE register. Write '1' to clear.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN28_A { + #[doc = "0: Criteria has not been met"] + NOT_LATCHED = 0, + #[doc = "1: Criteria has been met"] + LATCHED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN28_A) -> Self { + variant as u8 != 0 + } +} +impl PIN28_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN28_A { + match self.bits { + false => PIN28_A::NOT_LATCHED, + true => PIN28_A::LATCHED, + } + } + #[doc = "Checks if the value of the field is `NOT_LATCHED`"] + #[inline(always)] + pub fn is_not_latched(&self) -> bool { + *self == PIN28_A::NOT_LATCHED + } + #[doc = "Checks if the value of the field is `LATCHED`"] + #[inline(always)] + pub fn is_latched(&self) -> bool { + *self == PIN28_A::LATCHED + } +} +#[doc = "Field `PIN28` writer - Status on whether PIN\\[28\\] +has met criteria set in PIN_CNF\\[28\\].SENSE register. Write '1' to clear."] +pub type PIN28_W<'a, const O: u8> = crate::BitWriter<'a, u32, LATCH_SPEC, PIN28_A, O>; +impl<'a, const O: u8> PIN28_W<'a, O> { + #[doc = "Criteria has not been met"] + #[inline(always)] + pub fn not_latched(self) -> &'a mut W { + self.variant(PIN28_A::NOT_LATCHED) + } + #[doc = "Criteria has been met"] + #[inline(always)] + pub fn latched(self) -> &'a mut W { + self.variant(PIN28_A::LATCHED) + } +} +#[doc = "Field `PIN29` reader - Status on whether PIN\\[29\\] +has met criteria set in PIN_CNF\\[29\\].SENSE register. Write '1' to clear."] +pub type PIN29_R = crate::BitReader; +#[doc = "Status on whether PIN\\[29\\] +has met criteria set in PIN_CNF\\[29\\].SENSE register. Write '1' to clear.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN29_A { + #[doc = "0: Criteria has not been met"] + NOT_LATCHED = 0, + #[doc = "1: Criteria has been met"] + LATCHED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN29_A) -> Self { + variant as u8 != 0 + } +} +impl PIN29_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN29_A { + match self.bits { + false => PIN29_A::NOT_LATCHED, + true => PIN29_A::LATCHED, + } + } + #[doc = "Checks if the value of the field is `NOT_LATCHED`"] + #[inline(always)] + pub fn is_not_latched(&self) -> bool { + *self == PIN29_A::NOT_LATCHED + } + #[doc = "Checks if the value of the field is `LATCHED`"] + #[inline(always)] + pub fn is_latched(&self) -> bool { + *self == PIN29_A::LATCHED + } +} +#[doc = "Field `PIN29` writer - Status on whether PIN\\[29\\] +has met criteria set in PIN_CNF\\[29\\].SENSE register. Write '1' to clear."] +pub type PIN29_W<'a, const O: u8> = crate::BitWriter<'a, u32, LATCH_SPEC, PIN29_A, O>; +impl<'a, const O: u8> PIN29_W<'a, O> { + #[doc = "Criteria has not been met"] + #[inline(always)] + pub fn not_latched(self) -> &'a mut W { + self.variant(PIN29_A::NOT_LATCHED) + } + #[doc = "Criteria has been met"] + #[inline(always)] + pub fn latched(self) -> &'a mut W { + self.variant(PIN29_A::LATCHED) + } +} +#[doc = "Field `PIN30` reader - Status on whether PIN\\[30\\] +has met criteria set in PIN_CNF\\[30\\].SENSE register. Write '1' to clear."] +pub type PIN30_R = crate::BitReader; +#[doc = "Status on whether PIN\\[30\\] +has met criteria set in PIN_CNF\\[30\\].SENSE register. Write '1' to clear.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN30_A { + #[doc = "0: Criteria has not been met"] + NOT_LATCHED = 0, + #[doc = "1: Criteria has been met"] + LATCHED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN30_A) -> Self { + variant as u8 != 0 + } +} +impl PIN30_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN30_A { + match self.bits { + false => PIN30_A::NOT_LATCHED, + true => PIN30_A::LATCHED, + } + } + #[doc = "Checks if the value of the field is `NOT_LATCHED`"] + #[inline(always)] + pub fn is_not_latched(&self) -> bool { + *self == PIN30_A::NOT_LATCHED + } + #[doc = "Checks if the value of the field is `LATCHED`"] + #[inline(always)] + pub fn is_latched(&self) -> bool { + *self == PIN30_A::LATCHED + } +} +#[doc = "Field `PIN30` writer - Status on whether PIN\\[30\\] +has met criteria set in PIN_CNF\\[30\\].SENSE register. Write '1' to clear."] +pub type PIN30_W<'a, const O: u8> = crate::BitWriter<'a, u32, LATCH_SPEC, PIN30_A, O>; +impl<'a, const O: u8> PIN30_W<'a, O> { + #[doc = "Criteria has not been met"] + #[inline(always)] + pub fn not_latched(self) -> &'a mut W { + self.variant(PIN30_A::NOT_LATCHED) + } + #[doc = "Criteria has been met"] + #[inline(always)] + pub fn latched(self) -> &'a mut W { + self.variant(PIN30_A::LATCHED) + } +} +#[doc = "Field `PIN31` reader - Status on whether PIN\\[31\\] +has met criteria set in PIN_CNF\\[31\\].SENSE register. Write '1' to clear."] +pub type PIN31_R = crate::BitReader; +#[doc = "Status on whether PIN\\[31\\] +has met criteria set in PIN_CNF\\[31\\].SENSE register. Write '1' to clear.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN31_A { + #[doc = "0: Criteria has not been met"] + NOT_LATCHED = 0, + #[doc = "1: Criteria has been met"] + LATCHED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN31_A) -> Self { + variant as u8 != 0 + } +} +impl PIN31_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN31_A { + match self.bits { + false => PIN31_A::NOT_LATCHED, + true => PIN31_A::LATCHED, + } + } + #[doc = "Checks if the value of the field is `NOT_LATCHED`"] + #[inline(always)] + pub fn is_not_latched(&self) -> bool { + *self == PIN31_A::NOT_LATCHED + } + #[doc = "Checks if the value of the field is `LATCHED`"] + #[inline(always)] + pub fn is_latched(&self) -> bool { + *self == PIN31_A::LATCHED + } +} +#[doc = "Field `PIN31` writer - Status on whether PIN\\[31\\] +has met criteria set in PIN_CNF\\[31\\].SENSE register. Write '1' to clear."] +pub type PIN31_W<'a, const O: u8> = crate::BitWriter<'a, u32, LATCH_SPEC, PIN31_A, O>; +impl<'a, const O: u8> PIN31_W<'a, O> { + #[doc = "Criteria has not been met"] + #[inline(always)] + pub fn not_latched(self) -> &'a mut W { + self.variant(PIN31_A::NOT_LATCHED) + } + #[doc = "Criteria has been met"] + #[inline(always)] + pub fn latched(self) -> &'a mut W { + self.variant(PIN31_A::LATCHED) + } +} +impl R { + #[doc = "Bit 0 - Status on whether PIN\\[0\\] +has met criteria set in PIN_CNF\\[0\\].SENSE register. Write '1' to clear."] + #[inline(always)] + pub fn pin0(&self) -> PIN0_R { + PIN0_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Status on whether PIN\\[1\\] +has met criteria set in PIN_CNF\\[1\\].SENSE register. Write '1' to clear."] + #[inline(always)] + pub fn pin1(&self) -> PIN1_R { + PIN1_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Status on whether PIN\\[2\\] +has met criteria set in PIN_CNF\\[2\\].SENSE register. Write '1' to clear."] + #[inline(always)] + pub fn pin2(&self) -> PIN2_R { + PIN2_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Status on whether PIN\\[3\\] +has met criteria set in PIN_CNF\\[3\\].SENSE register. Write '1' to clear."] + #[inline(always)] + pub fn pin3(&self) -> PIN3_R { + PIN3_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Status on whether PIN\\[4\\] +has met criteria set in PIN_CNF\\[4\\].SENSE register. Write '1' to clear."] + #[inline(always)] + pub fn pin4(&self) -> PIN4_R { + PIN4_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Status on whether PIN\\[5\\] +has met criteria set in PIN_CNF\\[5\\].SENSE register. Write '1' to clear."] + #[inline(always)] + pub fn pin5(&self) -> PIN5_R { + PIN5_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Status on whether PIN\\[6\\] +has met criteria set in PIN_CNF\\[6\\].SENSE register. Write '1' to clear."] + #[inline(always)] + pub fn pin6(&self) -> PIN6_R { + PIN6_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Status on whether PIN\\[7\\] +has met criteria set in PIN_CNF\\[7\\].SENSE register. Write '1' to clear."] + #[inline(always)] + pub fn pin7(&self) -> PIN7_R { + PIN7_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Status on whether PIN\\[8\\] +has met criteria set in PIN_CNF\\[8\\].SENSE register. Write '1' to clear."] + #[inline(always)] + pub fn pin8(&self) -> PIN8_R { + PIN8_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Status on whether PIN\\[9\\] +has met criteria set in PIN_CNF\\[9\\].SENSE register. Write '1' to clear."] + #[inline(always)] + pub fn pin9(&self) -> PIN9_R { + PIN9_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Status on whether PIN\\[10\\] +has met criteria set in PIN_CNF\\[10\\].SENSE register. Write '1' to clear."] + #[inline(always)] + pub fn pin10(&self) -> PIN10_R { + PIN10_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Status on whether PIN\\[11\\] +has met criteria set in PIN_CNF\\[11\\].SENSE register. Write '1' to clear."] + #[inline(always)] + pub fn pin11(&self) -> PIN11_R { + PIN11_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Status on whether PIN\\[12\\] +has met criteria set in PIN_CNF\\[12\\].SENSE register. Write '1' to clear."] + #[inline(always)] + pub fn pin12(&self) -> PIN12_R { + PIN12_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Status on whether PIN\\[13\\] +has met criteria set in PIN_CNF\\[13\\].SENSE register. Write '1' to clear."] + #[inline(always)] + pub fn pin13(&self) -> PIN13_R { + PIN13_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Status on whether PIN\\[14\\] +has met criteria set in PIN_CNF\\[14\\].SENSE register. Write '1' to clear."] + #[inline(always)] + pub fn pin14(&self) -> PIN14_R { + PIN14_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Status on whether PIN\\[15\\] +has met criteria set in PIN_CNF\\[15\\].SENSE register. Write '1' to clear."] + #[inline(always)] + pub fn pin15(&self) -> PIN15_R { + PIN15_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - Status on whether PIN\\[16\\] +has met criteria set in PIN_CNF\\[16\\].SENSE register. Write '1' to clear."] + #[inline(always)] + pub fn pin16(&self) -> PIN16_R { + PIN16_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Status on whether PIN\\[17\\] +has met criteria set in PIN_CNF\\[17\\].SENSE register. Write '1' to clear."] + #[inline(always)] + pub fn pin17(&self) -> PIN17_R { + PIN17_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Status on whether PIN\\[18\\] +has met criteria set in PIN_CNF\\[18\\].SENSE register. Write '1' to clear."] + #[inline(always)] + pub fn pin18(&self) -> PIN18_R { + PIN18_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Status on whether PIN\\[19\\] +has met criteria set in PIN_CNF\\[19\\].SENSE register. Write '1' to clear."] + #[inline(always)] + pub fn pin19(&self) -> PIN19_R { + PIN19_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Status on whether PIN\\[20\\] +has met criteria set in PIN_CNF\\[20\\].SENSE register. Write '1' to clear."] + #[inline(always)] + pub fn pin20(&self) -> PIN20_R { + PIN20_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Status on whether PIN\\[21\\] +has met criteria set in PIN_CNF\\[21\\].SENSE register. Write '1' to clear."] + #[inline(always)] + pub fn pin21(&self) -> PIN21_R { + PIN21_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Status on whether PIN\\[22\\] +has met criteria set in PIN_CNF\\[22\\].SENSE register. Write '1' to clear."] + #[inline(always)] + pub fn pin22(&self) -> PIN22_R { + PIN22_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - Status on whether PIN\\[23\\] +has met criteria set in PIN_CNF\\[23\\].SENSE register. Write '1' to clear."] + #[inline(always)] + pub fn pin23(&self) -> PIN23_R { + PIN23_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - Status on whether PIN\\[24\\] +has met criteria set in PIN_CNF\\[24\\].SENSE register. Write '1' to clear."] + #[inline(always)] + pub fn pin24(&self) -> PIN24_R { + PIN24_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - Status on whether PIN\\[25\\] +has met criteria set in PIN_CNF\\[25\\].SENSE register. Write '1' to clear."] + #[inline(always)] + pub fn pin25(&self) -> PIN25_R { + PIN25_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - Status on whether PIN\\[26\\] +has met criteria set in PIN_CNF\\[26\\].SENSE register. Write '1' to clear."] + #[inline(always)] + pub fn pin26(&self) -> PIN26_R { + PIN26_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - Status on whether PIN\\[27\\] +has met criteria set in PIN_CNF\\[27\\].SENSE register. Write '1' to clear."] + #[inline(always)] + pub fn pin27(&self) -> PIN27_R { + PIN27_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - Status on whether PIN\\[28\\] +has met criteria set in PIN_CNF\\[28\\].SENSE register. Write '1' to clear."] + #[inline(always)] + pub fn pin28(&self) -> PIN28_R { + PIN28_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - Status on whether PIN\\[29\\] +has met criteria set in PIN_CNF\\[29\\].SENSE register. Write '1' to clear."] + #[inline(always)] + pub fn pin29(&self) -> PIN29_R { + PIN29_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Status on whether PIN\\[30\\] +has met criteria set in PIN_CNF\\[30\\].SENSE register. Write '1' to clear."] + #[inline(always)] + pub fn pin30(&self) -> PIN30_R { + PIN30_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Status on whether PIN\\[31\\] +has met criteria set in PIN_CNF\\[31\\].SENSE register. Write '1' to clear."] + #[inline(always)] + pub fn pin31(&self) -> PIN31_R { + PIN31_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Status on whether PIN\\[0\\] +has met criteria set in PIN_CNF\\[0\\].SENSE register. Write '1' to clear."] + #[inline(always)] + pub fn pin0(&mut self) -> PIN0_W<0> { + PIN0_W::new(self) + } + #[doc = "Bit 1 - Status on whether PIN\\[1\\] +has met criteria set in PIN_CNF\\[1\\].SENSE register. Write '1' to clear."] + #[inline(always)] + pub fn pin1(&mut self) -> PIN1_W<1> { + PIN1_W::new(self) + } + #[doc = "Bit 2 - Status on whether PIN\\[2\\] +has met criteria set in PIN_CNF\\[2\\].SENSE register. Write '1' to clear."] + #[inline(always)] + pub fn pin2(&mut self) -> PIN2_W<2> { + PIN2_W::new(self) + } + #[doc = "Bit 3 - Status on whether PIN\\[3\\] +has met criteria set in PIN_CNF\\[3\\].SENSE register. Write '1' to clear."] + #[inline(always)] + pub fn pin3(&mut self) -> PIN3_W<3> { + PIN3_W::new(self) + } + #[doc = "Bit 4 - Status on whether PIN\\[4\\] +has met criteria set in PIN_CNF\\[4\\].SENSE register. Write '1' to clear."] + #[inline(always)] + pub fn pin4(&mut self) -> PIN4_W<4> { + PIN4_W::new(self) + } + #[doc = "Bit 5 - Status on whether PIN\\[5\\] +has met criteria set in PIN_CNF\\[5\\].SENSE register. Write '1' to clear."] + #[inline(always)] + pub fn pin5(&mut self) -> PIN5_W<5> { + PIN5_W::new(self) + } + #[doc = "Bit 6 - Status on whether PIN\\[6\\] +has met criteria set in PIN_CNF\\[6\\].SENSE register. Write '1' to clear."] + #[inline(always)] + pub fn pin6(&mut self) -> PIN6_W<6> { + PIN6_W::new(self) + } + #[doc = "Bit 7 - Status on whether PIN\\[7\\] +has met criteria set in PIN_CNF\\[7\\].SENSE register. Write '1' to clear."] + #[inline(always)] + pub fn pin7(&mut self) -> PIN7_W<7> { + PIN7_W::new(self) + } + #[doc = "Bit 8 - Status on whether PIN\\[8\\] +has met criteria set in PIN_CNF\\[8\\].SENSE register. Write '1' to clear."] + #[inline(always)] + pub fn pin8(&mut self) -> PIN8_W<8> { + PIN8_W::new(self) + } + #[doc = "Bit 9 - Status on whether PIN\\[9\\] +has met criteria set in PIN_CNF\\[9\\].SENSE register. Write '1' to clear."] + #[inline(always)] + pub fn pin9(&mut self) -> PIN9_W<9> { + PIN9_W::new(self) + } + #[doc = "Bit 10 - Status on whether PIN\\[10\\] +has met criteria set in PIN_CNF\\[10\\].SENSE register. Write '1' to clear."] + #[inline(always)] + pub fn pin10(&mut self) -> PIN10_W<10> { + PIN10_W::new(self) + } + #[doc = "Bit 11 - Status on whether PIN\\[11\\] +has met criteria set in PIN_CNF\\[11\\].SENSE register. Write '1' to clear."] + #[inline(always)] + pub fn pin11(&mut self) -> PIN11_W<11> { + PIN11_W::new(self) + } + #[doc = "Bit 12 - Status on whether PIN\\[12\\] +has met criteria set in PIN_CNF\\[12\\].SENSE register. Write '1' to clear."] + #[inline(always)] + pub fn pin12(&mut self) -> PIN12_W<12> { + PIN12_W::new(self) + } + #[doc = "Bit 13 - Status on whether PIN\\[13\\] +has met criteria set in PIN_CNF\\[13\\].SENSE register. Write '1' to clear."] + #[inline(always)] + pub fn pin13(&mut self) -> PIN13_W<13> { + PIN13_W::new(self) + } + #[doc = "Bit 14 - Status on whether PIN\\[14\\] +has met criteria set in PIN_CNF\\[14\\].SENSE register. Write '1' to clear."] + #[inline(always)] + pub fn pin14(&mut self) -> PIN14_W<14> { + PIN14_W::new(self) + } + #[doc = "Bit 15 - Status on whether PIN\\[15\\] +has met criteria set in PIN_CNF\\[15\\].SENSE register. Write '1' to clear."] + #[inline(always)] + pub fn pin15(&mut self) -> PIN15_W<15> { + PIN15_W::new(self) + } + #[doc = "Bit 16 - Status on whether PIN\\[16\\] +has met criteria set in PIN_CNF\\[16\\].SENSE register. Write '1' to clear."] + #[inline(always)] + pub fn pin16(&mut self) -> PIN16_W<16> { + PIN16_W::new(self) + } + #[doc = "Bit 17 - Status on whether PIN\\[17\\] +has met criteria set in PIN_CNF\\[17\\].SENSE register. Write '1' to clear."] + #[inline(always)] + pub fn pin17(&mut self) -> PIN17_W<17> { + PIN17_W::new(self) + } + #[doc = "Bit 18 - Status on whether PIN\\[18\\] +has met criteria set in PIN_CNF\\[18\\].SENSE register. Write '1' to clear."] + #[inline(always)] + pub fn pin18(&mut self) -> PIN18_W<18> { + PIN18_W::new(self) + } + #[doc = "Bit 19 - Status on whether PIN\\[19\\] +has met criteria set in PIN_CNF\\[19\\].SENSE register. Write '1' to clear."] + #[inline(always)] + pub fn pin19(&mut self) -> PIN19_W<19> { + PIN19_W::new(self) + } + #[doc = "Bit 20 - Status on whether PIN\\[20\\] +has met criteria set in PIN_CNF\\[20\\].SENSE register. Write '1' to clear."] + #[inline(always)] + pub fn pin20(&mut self) -> PIN20_W<20> { + PIN20_W::new(self) + } + #[doc = "Bit 21 - Status on whether PIN\\[21\\] +has met criteria set in PIN_CNF\\[21\\].SENSE register. Write '1' to clear."] + #[inline(always)] + pub fn pin21(&mut self) -> PIN21_W<21> { + PIN21_W::new(self) + } + #[doc = "Bit 22 - Status on whether PIN\\[22\\] +has met criteria set in PIN_CNF\\[22\\].SENSE register. Write '1' to clear."] + #[inline(always)] + pub fn pin22(&mut self) -> PIN22_W<22> { + PIN22_W::new(self) + } + #[doc = "Bit 23 - Status on whether PIN\\[23\\] +has met criteria set in PIN_CNF\\[23\\].SENSE register. Write '1' to clear."] + #[inline(always)] + pub fn pin23(&mut self) -> PIN23_W<23> { + PIN23_W::new(self) + } + #[doc = "Bit 24 - Status on whether PIN\\[24\\] +has met criteria set in PIN_CNF\\[24\\].SENSE register. Write '1' to clear."] + #[inline(always)] + pub fn pin24(&mut self) -> PIN24_W<24> { + PIN24_W::new(self) + } + #[doc = "Bit 25 - Status on whether PIN\\[25\\] +has met criteria set in PIN_CNF\\[25\\].SENSE register. Write '1' to clear."] + #[inline(always)] + pub fn pin25(&mut self) -> PIN25_W<25> { + PIN25_W::new(self) + } + #[doc = "Bit 26 - Status on whether PIN\\[26\\] +has met criteria set in PIN_CNF\\[26\\].SENSE register. Write '1' to clear."] + #[inline(always)] + pub fn pin26(&mut self) -> PIN26_W<26> { + PIN26_W::new(self) + } + #[doc = "Bit 27 - Status on whether PIN\\[27\\] +has met criteria set in PIN_CNF\\[27\\].SENSE register. Write '1' to clear."] + #[inline(always)] + pub fn pin27(&mut self) -> PIN27_W<27> { + PIN27_W::new(self) + } + #[doc = "Bit 28 - Status on whether PIN\\[28\\] +has met criteria set in PIN_CNF\\[28\\].SENSE register. Write '1' to clear."] + #[inline(always)] + pub fn pin28(&mut self) -> PIN28_W<28> { + PIN28_W::new(self) + } + #[doc = "Bit 29 - Status on whether PIN\\[29\\] +has met criteria set in PIN_CNF\\[29\\].SENSE register. Write '1' to clear."] + #[inline(always)] + pub fn pin29(&mut self) -> PIN29_W<29> { + PIN29_W::new(self) + } + #[doc = "Bit 30 - Status on whether PIN\\[30\\] +has met criteria set in PIN_CNF\\[30\\].SENSE register. Write '1' to clear."] + #[inline(always)] + pub fn pin30(&mut self) -> PIN30_W<30> { + PIN30_W::new(self) + } + #[doc = "Bit 31 - Status on whether PIN\\[31\\] +has met criteria set in PIN_CNF\\[31\\].SENSE register. Write '1' to clear."] + #[inline(always)] + pub fn pin31(&mut self) -> PIN31_W<31> { + PIN31_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Latch register indicating what GPIO pins that have met the criteria set in the PIN_CNF\\[n\\].SENSE registers\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [latch](index.html) module"] +pub struct LATCH_SPEC; +impl crate::RegisterSpec for LATCH_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [latch::R](R) reader structure"] +impl crate::Readable for LATCH_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [latch::W](W) writer structure"] +impl crate::Writable for LATCH_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets LATCH to value 0"] +impl crate::Resettable for LATCH_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/p0_ns/out.rs b/pacs/nrf9120-pac/src/p0_ns/out.rs new file mode 100644 index 00000000..ba461f24 --- /dev/null +++ b/pacs/nrf9120-pac/src/p0_ns/out.rs @@ -0,0 +1,1986 @@ +#[doc = "Register `OUT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `OUT` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PIN0` reader - Pin 0"] +pub type PIN0_R = crate::BitReader; +#[doc = "Pin 0\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN0_A { + #[doc = "0: Pin driver is low"] + LOW = 0, + #[doc = "1: Pin driver is high"] + HIGH = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN0_A) -> Self { + variant as u8 != 0 + } +} +impl PIN0_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN0_A { + match self.bits { + false => PIN0_A::LOW, + true => PIN0_A::HIGH, + } + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + *self == PIN0_A::LOW + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + *self == PIN0_A::HIGH + } +} +#[doc = "Field `PIN0` writer - Pin 0"] +pub type PIN0_W<'a, const O: u8> = crate::BitWriter<'a, u32, OUT_SPEC, PIN0_A, O>; +impl<'a, const O: u8> PIN0_W<'a, O> { + #[doc = "Pin driver is low"] + #[inline(always)] + pub fn low(self) -> &'a mut W { + self.variant(PIN0_A::LOW) + } + #[doc = "Pin driver is high"] + #[inline(always)] + pub fn high(self) -> &'a mut W { + self.variant(PIN0_A::HIGH) + } +} +#[doc = "Field `PIN1` reader - Pin 1"] +pub type PIN1_R = crate::BitReader; +#[doc = "Pin 1\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN1_A { + #[doc = "0: Pin driver is low"] + LOW = 0, + #[doc = "1: Pin driver is high"] + HIGH = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN1_A) -> Self { + variant as u8 != 0 + } +} +impl PIN1_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN1_A { + match self.bits { + false => PIN1_A::LOW, + true => PIN1_A::HIGH, + } + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + *self == PIN1_A::LOW + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + *self == PIN1_A::HIGH + } +} +#[doc = "Field `PIN1` writer - Pin 1"] +pub type PIN1_W<'a, const O: u8> = crate::BitWriter<'a, u32, OUT_SPEC, PIN1_A, O>; +impl<'a, const O: u8> PIN1_W<'a, O> { + #[doc = "Pin driver is low"] + #[inline(always)] + pub fn low(self) -> &'a mut W { + self.variant(PIN1_A::LOW) + } + #[doc = "Pin driver is high"] + #[inline(always)] + pub fn high(self) -> &'a mut W { + self.variant(PIN1_A::HIGH) + } +} +#[doc = "Field `PIN2` reader - Pin 2"] +pub type PIN2_R = crate::BitReader; +#[doc = "Pin 2\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN2_A { + #[doc = "0: Pin driver is low"] + LOW = 0, + #[doc = "1: Pin driver is high"] + HIGH = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN2_A) -> Self { + variant as u8 != 0 + } +} +impl PIN2_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN2_A { + match self.bits { + false => PIN2_A::LOW, + true => PIN2_A::HIGH, + } + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + *self == PIN2_A::LOW + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + *self == PIN2_A::HIGH + } +} +#[doc = "Field `PIN2` writer - Pin 2"] +pub type PIN2_W<'a, const O: u8> = crate::BitWriter<'a, u32, OUT_SPEC, PIN2_A, O>; +impl<'a, const O: u8> PIN2_W<'a, O> { + #[doc = "Pin driver is low"] + #[inline(always)] + pub fn low(self) -> &'a mut W { + self.variant(PIN2_A::LOW) + } + #[doc = "Pin driver is high"] + #[inline(always)] + pub fn high(self) -> &'a mut W { + self.variant(PIN2_A::HIGH) + } +} +#[doc = "Field `PIN3` reader - Pin 3"] +pub type PIN3_R = crate::BitReader; +#[doc = "Pin 3\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN3_A { + #[doc = "0: Pin driver is low"] + LOW = 0, + #[doc = "1: Pin driver is high"] + HIGH = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN3_A) -> Self { + variant as u8 != 0 + } +} +impl PIN3_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN3_A { + match self.bits { + false => PIN3_A::LOW, + true => PIN3_A::HIGH, + } + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + *self == PIN3_A::LOW + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + *self == PIN3_A::HIGH + } +} +#[doc = "Field `PIN3` writer - Pin 3"] +pub type PIN3_W<'a, const O: u8> = crate::BitWriter<'a, u32, OUT_SPEC, PIN3_A, O>; +impl<'a, const O: u8> PIN3_W<'a, O> { + #[doc = "Pin driver is low"] + #[inline(always)] + pub fn low(self) -> &'a mut W { + self.variant(PIN3_A::LOW) + } + #[doc = "Pin driver is high"] + #[inline(always)] + pub fn high(self) -> &'a mut W { + self.variant(PIN3_A::HIGH) + } +} +#[doc = "Field `PIN4` reader - Pin 4"] +pub type PIN4_R = crate::BitReader; +#[doc = "Pin 4\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN4_A { + #[doc = "0: Pin driver is low"] + LOW = 0, + #[doc = "1: Pin driver is high"] + HIGH = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN4_A) -> Self { + variant as u8 != 0 + } +} +impl PIN4_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN4_A { + match self.bits { + false => PIN4_A::LOW, + true => PIN4_A::HIGH, + } + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + *self == PIN4_A::LOW + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + *self == PIN4_A::HIGH + } +} +#[doc = "Field `PIN4` writer - Pin 4"] +pub type PIN4_W<'a, const O: u8> = crate::BitWriter<'a, u32, OUT_SPEC, PIN4_A, O>; +impl<'a, const O: u8> PIN4_W<'a, O> { + #[doc = "Pin driver is low"] + #[inline(always)] + pub fn low(self) -> &'a mut W { + self.variant(PIN4_A::LOW) + } + #[doc = "Pin driver is high"] + #[inline(always)] + pub fn high(self) -> &'a mut W { + self.variant(PIN4_A::HIGH) + } +} +#[doc = "Field `PIN5` reader - Pin 5"] +pub type PIN5_R = crate::BitReader; +#[doc = "Pin 5\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN5_A { + #[doc = "0: Pin driver is low"] + LOW = 0, + #[doc = "1: Pin driver is high"] + HIGH = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN5_A) -> Self { + variant as u8 != 0 + } +} +impl PIN5_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN5_A { + match self.bits { + false => PIN5_A::LOW, + true => PIN5_A::HIGH, + } + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + *self == PIN5_A::LOW + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + *self == PIN5_A::HIGH + } +} +#[doc = "Field `PIN5` writer - Pin 5"] +pub type PIN5_W<'a, const O: u8> = crate::BitWriter<'a, u32, OUT_SPEC, PIN5_A, O>; +impl<'a, const O: u8> PIN5_W<'a, O> { + #[doc = "Pin driver is low"] + #[inline(always)] + pub fn low(self) -> &'a mut W { + self.variant(PIN5_A::LOW) + } + #[doc = "Pin driver is high"] + #[inline(always)] + pub fn high(self) -> &'a mut W { + self.variant(PIN5_A::HIGH) + } +} +#[doc = "Field `PIN6` reader - Pin 6"] +pub type PIN6_R = crate::BitReader; +#[doc = "Pin 6\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN6_A { + #[doc = "0: Pin driver is low"] + LOW = 0, + #[doc = "1: Pin driver is high"] + HIGH = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN6_A) -> Self { + variant as u8 != 0 + } +} +impl PIN6_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN6_A { + match self.bits { + false => PIN6_A::LOW, + true => PIN6_A::HIGH, + } + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + *self == PIN6_A::LOW + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + *self == PIN6_A::HIGH + } +} +#[doc = "Field `PIN6` writer - Pin 6"] +pub type PIN6_W<'a, const O: u8> = crate::BitWriter<'a, u32, OUT_SPEC, PIN6_A, O>; +impl<'a, const O: u8> PIN6_W<'a, O> { + #[doc = "Pin driver is low"] + #[inline(always)] + pub fn low(self) -> &'a mut W { + self.variant(PIN6_A::LOW) + } + #[doc = "Pin driver is high"] + #[inline(always)] + pub fn high(self) -> &'a mut W { + self.variant(PIN6_A::HIGH) + } +} +#[doc = "Field `PIN7` reader - Pin 7"] +pub type PIN7_R = crate::BitReader; +#[doc = "Pin 7\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN7_A { + #[doc = "0: Pin driver is low"] + LOW = 0, + #[doc = "1: Pin driver is high"] + HIGH = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN7_A) -> Self { + variant as u8 != 0 + } +} +impl PIN7_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN7_A { + match self.bits { + false => PIN7_A::LOW, + true => PIN7_A::HIGH, + } + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + *self == PIN7_A::LOW + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + *self == PIN7_A::HIGH + } +} +#[doc = "Field `PIN7` writer - Pin 7"] +pub type PIN7_W<'a, const O: u8> = crate::BitWriter<'a, u32, OUT_SPEC, PIN7_A, O>; +impl<'a, const O: u8> PIN7_W<'a, O> { + #[doc = "Pin driver is low"] + #[inline(always)] + pub fn low(self) -> &'a mut W { + self.variant(PIN7_A::LOW) + } + #[doc = "Pin driver is high"] + #[inline(always)] + pub fn high(self) -> &'a mut W { + self.variant(PIN7_A::HIGH) + } +} +#[doc = "Field `PIN8` reader - Pin 8"] +pub type PIN8_R = crate::BitReader; +#[doc = "Pin 8\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN8_A { + #[doc = "0: Pin driver is low"] + LOW = 0, + #[doc = "1: Pin driver is high"] + HIGH = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN8_A) -> Self { + variant as u8 != 0 + } +} +impl PIN8_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN8_A { + match self.bits { + false => PIN8_A::LOW, + true => PIN8_A::HIGH, + } + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + *self == PIN8_A::LOW + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + *self == PIN8_A::HIGH + } +} +#[doc = "Field `PIN8` writer - Pin 8"] +pub type PIN8_W<'a, const O: u8> = crate::BitWriter<'a, u32, OUT_SPEC, PIN8_A, O>; +impl<'a, const O: u8> PIN8_W<'a, O> { + #[doc = "Pin driver is low"] + #[inline(always)] + pub fn low(self) -> &'a mut W { + self.variant(PIN8_A::LOW) + } + #[doc = "Pin driver is high"] + #[inline(always)] + pub fn high(self) -> &'a mut W { + self.variant(PIN8_A::HIGH) + } +} +#[doc = "Field `PIN9` reader - Pin 9"] +pub type PIN9_R = crate::BitReader; +#[doc = "Pin 9\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN9_A { + #[doc = "0: Pin driver is low"] + LOW = 0, + #[doc = "1: Pin driver is high"] + HIGH = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN9_A) -> Self { + variant as u8 != 0 + } +} +impl PIN9_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN9_A { + match self.bits { + false => PIN9_A::LOW, + true => PIN9_A::HIGH, + } + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + *self == PIN9_A::LOW + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + *self == PIN9_A::HIGH + } +} +#[doc = "Field `PIN9` writer - Pin 9"] +pub type PIN9_W<'a, const O: u8> = crate::BitWriter<'a, u32, OUT_SPEC, PIN9_A, O>; +impl<'a, const O: u8> PIN9_W<'a, O> { + #[doc = "Pin driver is low"] + #[inline(always)] + pub fn low(self) -> &'a mut W { + self.variant(PIN9_A::LOW) + } + #[doc = "Pin driver is high"] + #[inline(always)] + pub fn high(self) -> &'a mut W { + self.variant(PIN9_A::HIGH) + } +} +#[doc = "Field `PIN10` reader - Pin 10"] +pub type PIN10_R = crate::BitReader; +#[doc = "Pin 10\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN10_A { + #[doc = "0: Pin driver is low"] + LOW = 0, + #[doc = "1: Pin driver is high"] + HIGH = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN10_A) -> Self { + variant as u8 != 0 + } +} +impl PIN10_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN10_A { + match self.bits { + false => PIN10_A::LOW, + true => PIN10_A::HIGH, + } + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + *self == PIN10_A::LOW + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + *self == PIN10_A::HIGH + } +} +#[doc = "Field `PIN10` writer - Pin 10"] +pub type PIN10_W<'a, const O: u8> = crate::BitWriter<'a, u32, OUT_SPEC, PIN10_A, O>; +impl<'a, const O: u8> PIN10_W<'a, O> { + #[doc = "Pin driver is low"] + #[inline(always)] + pub fn low(self) -> &'a mut W { + self.variant(PIN10_A::LOW) + } + #[doc = "Pin driver is high"] + #[inline(always)] + pub fn high(self) -> &'a mut W { + self.variant(PIN10_A::HIGH) + } +} +#[doc = "Field `PIN11` reader - Pin 11"] +pub type PIN11_R = crate::BitReader; +#[doc = "Pin 11\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN11_A { + #[doc = "0: Pin driver is low"] + LOW = 0, + #[doc = "1: Pin driver is high"] + HIGH = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN11_A) -> Self { + variant as u8 != 0 + } +} +impl PIN11_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN11_A { + match self.bits { + false => PIN11_A::LOW, + true => PIN11_A::HIGH, + } + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + *self == PIN11_A::LOW + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + *self == PIN11_A::HIGH + } +} +#[doc = "Field `PIN11` writer - Pin 11"] +pub type PIN11_W<'a, const O: u8> = crate::BitWriter<'a, u32, OUT_SPEC, PIN11_A, O>; +impl<'a, const O: u8> PIN11_W<'a, O> { + #[doc = "Pin driver is low"] + #[inline(always)] + pub fn low(self) -> &'a mut W { + self.variant(PIN11_A::LOW) + } + #[doc = "Pin driver is high"] + #[inline(always)] + pub fn high(self) -> &'a mut W { + self.variant(PIN11_A::HIGH) + } +} +#[doc = "Field `PIN12` reader - Pin 12"] +pub type PIN12_R = crate::BitReader; +#[doc = "Pin 12\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN12_A { + #[doc = "0: Pin driver is low"] + LOW = 0, + #[doc = "1: Pin driver is high"] + HIGH = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN12_A) -> Self { + variant as u8 != 0 + } +} +impl PIN12_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN12_A { + match self.bits { + false => PIN12_A::LOW, + true => PIN12_A::HIGH, + } + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + *self == PIN12_A::LOW + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + *self == PIN12_A::HIGH + } +} +#[doc = "Field `PIN12` writer - Pin 12"] +pub type PIN12_W<'a, const O: u8> = crate::BitWriter<'a, u32, OUT_SPEC, PIN12_A, O>; +impl<'a, const O: u8> PIN12_W<'a, O> { + #[doc = "Pin driver is low"] + #[inline(always)] + pub fn low(self) -> &'a mut W { + self.variant(PIN12_A::LOW) + } + #[doc = "Pin driver is high"] + #[inline(always)] + pub fn high(self) -> &'a mut W { + self.variant(PIN12_A::HIGH) + } +} +#[doc = "Field `PIN13` reader - Pin 13"] +pub type PIN13_R = crate::BitReader; +#[doc = "Pin 13\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN13_A { + #[doc = "0: Pin driver is low"] + LOW = 0, + #[doc = "1: Pin driver is high"] + HIGH = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN13_A) -> Self { + variant as u8 != 0 + } +} +impl PIN13_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN13_A { + match self.bits { + false => PIN13_A::LOW, + true => PIN13_A::HIGH, + } + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + *self == PIN13_A::LOW + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + *self == PIN13_A::HIGH + } +} +#[doc = "Field `PIN13` writer - Pin 13"] +pub type PIN13_W<'a, const O: u8> = crate::BitWriter<'a, u32, OUT_SPEC, PIN13_A, O>; +impl<'a, const O: u8> PIN13_W<'a, O> { + #[doc = "Pin driver is low"] + #[inline(always)] + pub fn low(self) -> &'a mut W { + self.variant(PIN13_A::LOW) + } + #[doc = "Pin driver is high"] + #[inline(always)] + pub fn high(self) -> &'a mut W { + self.variant(PIN13_A::HIGH) + } +} +#[doc = "Field `PIN14` reader - Pin 14"] +pub type PIN14_R = crate::BitReader; +#[doc = "Pin 14\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN14_A { + #[doc = "0: Pin driver is low"] + LOW = 0, + #[doc = "1: Pin driver is high"] + HIGH = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN14_A) -> Self { + variant as u8 != 0 + } +} +impl PIN14_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN14_A { + match self.bits { + false => PIN14_A::LOW, + true => PIN14_A::HIGH, + } + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + *self == PIN14_A::LOW + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + *self == PIN14_A::HIGH + } +} +#[doc = "Field `PIN14` writer - Pin 14"] +pub type PIN14_W<'a, const O: u8> = crate::BitWriter<'a, u32, OUT_SPEC, PIN14_A, O>; +impl<'a, const O: u8> PIN14_W<'a, O> { + #[doc = "Pin driver is low"] + #[inline(always)] + pub fn low(self) -> &'a mut W { + self.variant(PIN14_A::LOW) + } + #[doc = "Pin driver is high"] + #[inline(always)] + pub fn high(self) -> &'a mut W { + self.variant(PIN14_A::HIGH) + } +} +#[doc = "Field `PIN15` reader - Pin 15"] +pub type PIN15_R = crate::BitReader; +#[doc = "Pin 15\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN15_A { + #[doc = "0: Pin driver is low"] + LOW = 0, + #[doc = "1: Pin driver is high"] + HIGH = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN15_A) -> Self { + variant as u8 != 0 + } +} +impl PIN15_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN15_A { + match self.bits { + false => PIN15_A::LOW, + true => PIN15_A::HIGH, + } + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + *self == PIN15_A::LOW + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + *self == PIN15_A::HIGH + } +} +#[doc = "Field `PIN15` writer - Pin 15"] +pub type PIN15_W<'a, const O: u8> = crate::BitWriter<'a, u32, OUT_SPEC, PIN15_A, O>; +impl<'a, const O: u8> PIN15_W<'a, O> { + #[doc = "Pin driver is low"] + #[inline(always)] + pub fn low(self) -> &'a mut W { + self.variant(PIN15_A::LOW) + } + #[doc = "Pin driver is high"] + #[inline(always)] + pub fn high(self) -> &'a mut W { + self.variant(PIN15_A::HIGH) + } +} +#[doc = "Field `PIN16` reader - Pin 16"] +pub type PIN16_R = crate::BitReader; +#[doc = "Pin 16\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN16_A { + #[doc = "0: Pin driver is low"] + LOW = 0, + #[doc = "1: Pin driver is high"] + HIGH = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN16_A) -> Self { + variant as u8 != 0 + } +} +impl PIN16_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN16_A { + match self.bits { + false => PIN16_A::LOW, + true => PIN16_A::HIGH, + } + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + *self == PIN16_A::LOW + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + *self == PIN16_A::HIGH + } +} +#[doc = "Field `PIN16` writer - Pin 16"] +pub type PIN16_W<'a, const O: u8> = crate::BitWriter<'a, u32, OUT_SPEC, PIN16_A, O>; +impl<'a, const O: u8> PIN16_W<'a, O> { + #[doc = "Pin driver is low"] + #[inline(always)] + pub fn low(self) -> &'a mut W { + self.variant(PIN16_A::LOW) + } + #[doc = "Pin driver is high"] + #[inline(always)] + pub fn high(self) -> &'a mut W { + self.variant(PIN16_A::HIGH) + } +} +#[doc = "Field `PIN17` reader - Pin 17"] +pub type PIN17_R = crate::BitReader; +#[doc = "Pin 17\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN17_A { + #[doc = "0: Pin driver is low"] + LOW = 0, + #[doc = "1: Pin driver is high"] + HIGH = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN17_A) -> Self { + variant as u8 != 0 + } +} +impl PIN17_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN17_A { + match self.bits { + false => PIN17_A::LOW, + true => PIN17_A::HIGH, + } + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + *self == PIN17_A::LOW + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + *self == PIN17_A::HIGH + } +} +#[doc = "Field `PIN17` writer - Pin 17"] +pub type PIN17_W<'a, const O: u8> = crate::BitWriter<'a, u32, OUT_SPEC, PIN17_A, O>; +impl<'a, const O: u8> PIN17_W<'a, O> { + #[doc = "Pin driver is low"] + #[inline(always)] + pub fn low(self) -> &'a mut W { + self.variant(PIN17_A::LOW) + } + #[doc = "Pin driver is high"] + #[inline(always)] + pub fn high(self) -> &'a mut W { + self.variant(PIN17_A::HIGH) + } +} +#[doc = "Field `PIN18` reader - Pin 18"] +pub type PIN18_R = crate::BitReader; +#[doc = "Pin 18\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN18_A { + #[doc = "0: Pin driver is low"] + LOW = 0, + #[doc = "1: Pin driver is high"] + HIGH = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN18_A) -> Self { + variant as u8 != 0 + } +} +impl PIN18_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN18_A { + match self.bits { + false => PIN18_A::LOW, + true => PIN18_A::HIGH, + } + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + *self == PIN18_A::LOW + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + *self == PIN18_A::HIGH + } +} +#[doc = "Field `PIN18` writer - Pin 18"] +pub type PIN18_W<'a, const O: u8> = crate::BitWriter<'a, u32, OUT_SPEC, PIN18_A, O>; +impl<'a, const O: u8> PIN18_W<'a, O> { + #[doc = "Pin driver is low"] + #[inline(always)] + pub fn low(self) -> &'a mut W { + self.variant(PIN18_A::LOW) + } + #[doc = "Pin driver is high"] + #[inline(always)] + pub fn high(self) -> &'a mut W { + self.variant(PIN18_A::HIGH) + } +} +#[doc = "Field `PIN19` reader - Pin 19"] +pub type PIN19_R = crate::BitReader; +#[doc = "Pin 19\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN19_A { + #[doc = "0: Pin driver is low"] + LOW = 0, + #[doc = "1: Pin driver is high"] + HIGH = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN19_A) -> Self { + variant as u8 != 0 + } +} +impl PIN19_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN19_A { + match self.bits { + false => PIN19_A::LOW, + true => PIN19_A::HIGH, + } + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + *self == PIN19_A::LOW + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + *self == PIN19_A::HIGH + } +} +#[doc = "Field `PIN19` writer - Pin 19"] +pub type PIN19_W<'a, const O: u8> = crate::BitWriter<'a, u32, OUT_SPEC, PIN19_A, O>; +impl<'a, const O: u8> PIN19_W<'a, O> { + #[doc = "Pin driver is low"] + #[inline(always)] + pub fn low(self) -> &'a mut W { + self.variant(PIN19_A::LOW) + } + #[doc = "Pin driver is high"] + #[inline(always)] + pub fn high(self) -> &'a mut W { + self.variant(PIN19_A::HIGH) + } +} +#[doc = "Field `PIN20` reader - Pin 20"] +pub type PIN20_R = crate::BitReader; +#[doc = "Pin 20\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN20_A { + #[doc = "0: Pin driver is low"] + LOW = 0, + #[doc = "1: Pin driver is high"] + HIGH = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN20_A) -> Self { + variant as u8 != 0 + } +} +impl PIN20_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN20_A { + match self.bits { + false => PIN20_A::LOW, + true => PIN20_A::HIGH, + } + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + *self == PIN20_A::LOW + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + *self == PIN20_A::HIGH + } +} +#[doc = "Field `PIN20` writer - Pin 20"] +pub type PIN20_W<'a, const O: u8> = crate::BitWriter<'a, u32, OUT_SPEC, PIN20_A, O>; +impl<'a, const O: u8> PIN20_W<'a, O> { + #[doc = "Pin driver is low"] + #[inline(always)] + pub fn low(self) -> &'a mut W { + self.variant(PIN20_A::LOW) + } + #[doc = "Pin driver is high"] + #[inline(always)] + pub fn high(self) -> &'a mut W { + self.variant(PIN20_A::HIGH) + } +} +#[doc = "Field `PIN21` reader - Pin 21"] +pub type PIN21_R = crate::BitReader; +#[doc = "Pin 21\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN21_A { + #[doc = "0: Pin driver is low"] + LOW = 0, + #[doc = "1: Pin driver is high"] + HIGH = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN21_A) -> Self { + variant as u8 != 0 + } +} +impl PIN21_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN21_A { + match self.bits { + false => PIN21_A::LOW, + true => PIN21_A::HIGH, + } + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + *self == PIN21_A::LOW + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + *self == PIN21_A::HIGH + } +} +#[doc = "Field `PIN21` writer - Pin 21"] +pub type PIN21_W<'a, const O: u8> = crate::BitWriter<'a, u32, OUT_SPEC, PIN21_A, O>; +impl<'a, const O: u8> PIN21_W<'a, O> { + #[doc = "Pin driver is low"] + #[inline(always)] + pub fn low(self) -> &'a mut W { + self.variant(PIN21_A::LOW) + } + #[doc = "Pin driver is high"] + #[inline(always)] + pub fn high(self) -> &'a mut W { + self.variant(PIN21_A::HIGH) + } +} +#[doc = "Field `PIN22` reader - Pin 22"] +pub type PIN22_R = crate::BitReader; +#[doc = "Pin 22\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN22_A { + #[doc = "0: Pin driver is low"] + LOW = 0, + #[doc = "1: Pin driver is high"] + HIGH = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN22_A) -> Self { + variant as u8 != 0 + } +} +impl PIN22_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN22_A { + match self.bits { + false => PIN22_A::LOW, + true => PIN22_A::HIGH, + } + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + *self == PIN22_A::LOW + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + *self == PIN22_A::HIGH + } +} +#[doc = "Field `PIN22` writer - Pin 22"] +pub type PIN22_W<'a, const O: u8> = crate::BitWriter<'a, u32, OUT_SPEC, PIN22_A, O>; +impl<'a, const O: u8> PIN22_W<'a, O> { + #[doc = "Pin driver is low"] + #[inline(always)] + pub fn low(self) -> &'a mut W { + self.variant(PIN22_A::LOW) + } + #[doc = "Pin driver is high"] + #[inline(always)] + pub fn high(self) -> &'a mut W { + self.variant(PIN22_A::HIGH) + } +} +#[doc = "Field `PIN23` reader - Pin 23"] +pub type PIN23_R = crate::BitReader; +#[doc = "Pin 23\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN23_A { + #[doc = "0: Pin driver is low"] + LOW = 0, + #[doc = "1: Pin driver is high"] + HIGH = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN23_A) -> Self { + variant as u8 != 0 + } +} +impl PIN23_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN23_A { + match self.bits { + false => PIN23_A::LOW, + true => PIN23_A::HIGH, + } + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + *self == PIN23_A::LOW + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + *self == PIN23_A::HIGH + } +} +#[doc = "Field `PIN23` writer - Pin 23"] +pub type PIN23_W<'a, const O: u8> = crate::BitWriter<'a, u32, OUT_SPEC, PIN23_A, O>; +impl<'a, const O: u8> PIN23_W<'a, O> { + #[doc = "Pin driver is low"] + #[inline(always)] + pub fn low(self) -> &'a mut W { + self.variant(PIN23_A::LOW) + } + #[doc = "Pin driver is high"] + #[inline(always)] + pub fn high(self) -> &'a mut W { + self.variant(PIN23_A::HIGH) + } +} +#[doc = "Field `PIN24` reader - Pin 24"] +pub type PIN24_R = crate::BitReader; +#[doc = "Pin 24\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN24_A { + #[doc = "0: Pin driver is low"] + LOW = 0, + #[doc = "1: Pin driver is high"] + HIGH = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN24_A) -> Self { + variant as u8 != 0 + } +} +impl PIN24_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN24_A { + match self.bits { + false => PIN24_A::LOW, + true => PIN24_A::HIGH, + } + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + *self == PIN24_A::LOW + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + *self == PIN24_A::HIGH + } +} +#[doc = "Field `PIN24` writer - Pin 24"] +pub type PIN24_W<'a, const O: u8> = crate::BitWriter<'a, u32, OUT_SPEC, PIN24_A, O>; +impl<'a, const O: u8> PIN24_W<'a, O> { + #[doc = "Pin driver is low"] + #[inline(always)] + pub fn low(self) -> &'a mut W { + self.variant(PIN24_A::LOW) + } + #[doc = "Pin driver is high"] + #[inline(always)] + pub fn high(self) -> &'a mut W { + self.variant(PIN24_A::HIGH) + } +} +#[doc = "Field `PIN25` reader - Pin 25"] +pub type PIN25_R = crate::BitReader; +#[doc = "Pin 25\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN25_A { + #[doc = "0: Pin driver is low"] + LOW = 0, + #[doc = "1: Pin driver is high"] + HIGH = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN25_A) -> Self { + variant as u8 != 0 + } +} +impl PIN25_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN25_A { + match self.bits { + false => PIN25_A::LOW, + true => PIN25_A::HIGH, + } + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + *self == PIN25_A::LOW + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + *self == PIN25_A::HIGH + } +} +#[doc = "Field `PIN25` writer - Pin 25"] +pub type PIN25_W<'a, const O: u8> = crate::BitWriter<'a, u32, OUT_SPEC, PIN25_A, O>; +impl<'a, const O: u8> PIN25_W<'a, O> { + #[doc = "Pin driver is low"] + #[inline(always)] + pub fn low(self) -> &'a mut W { + self.variant(PIN25_A::LOW) + } + #[doc = "Pin driver is high"] + #[inline(always)] + pub fn high(self) -> &'a mut W { + self.variant(PIN25_A::HIGH) + } +} +#[doc = "Field `PIN26` reader - Pin 26"] +pub type PIN26_R = crate::BitReader; +#[doc = "Pin 26\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN26_A { + #[doc = "0: Pin driver is low"] + LOW = 0, + #[doc = "1: Pin driver is high"] + HIGH = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN26_A) -> Self { + variant as u8 != 0 + } +} +impl PIN26_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN26_A { + match self.bits { + false => PIN26_A::LOW, + true => PIN26_A::HIGH, + } + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + *self == PIN26_A::LOW + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + *self == PIN26_A::HIGH + } +} +#[doc = "Field `PIN26` writer - Pin 26"] +pub type PIN26_W<'a, const O: u8> = crate::BitWriter<'a, u32, OUT_SPEC, PIN26_A, O>; +impl<'a, const O: u8> PIN26_W<'a, O> { + #[doc = "Pin driver is low"] + #[inline(always)] + pub fn low(self) -> &'a mut W { + self.variant(PIN26_A::LOW) + } + #[doc = "Pin driver is high"] + #[inline(always)] + pub fn high(self) -> &'a mut W { + self.variant(PIN26_A::HIGH) + } +} +#[doc = "Field `PIN27` reader - Pin 27"] +pub type PIN27_R = crate::BitReader; +#[doc = "Pin 27\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN27_A { + #[doc = "0: Pin driver is low"] + LOW = 0, + #[doc = "1: Pin driver is high"] + HIGH = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN27_A) -> Self { + variant as u8 != 0 + } +} +impl PIN27_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN27_A { + match self.bits { + false => PIN27_A::LOW, + true => PIN27_A::HIGH, + } + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + *self == PIN27_A::LOW + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + *self == PIN27_A::HIGH + } +} +#[doc = "Field `PIN27` writer - Pin 27"] +pub type PIN27_W<'a, const O: u8> = crate::BitWriter<'a, u32, OUT_SPEC, PIN27_A, O>; +impl<'a, const O: u8> PIN27_W<'a, O> { + #[doc = "Pin driver is low"] + #[inline(always)] + pub fn low(self) -> &'a mut W { + self.variant(PIN27_A::LOW) + } + #[doc = "Pin driver is high"] + #[inline(always)] + pub fn high(self) -> &'a mut W { + self.variant(PIN27_A::HIGH) + } +} +#[doc = "Field `PIN28` reader - Pin 28"] +pub type PIN28_R = crate::BitReader; +#[doc = "Pin 28\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN28_A { + #[doc = "0: Pin driver is low"] + LOW = 0, + #[doc = "1: Pin driver is high"] + HIGH = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN28_A) -> Self { + variant as u8 != 0 + } +} +impl PIN28_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN28_A { + match self.bits { + false => PIN28_A::LOW, + true => PIN28_A::HIGH, + } + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + *self == PIN28_A::LOW + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + *self == PIN28_A::HIGH + } +} +#[doc = "Field `PIN28` writer - Pin 28"] +pub type PIN28_W<'a, const O: u8> = crate::BitWriter<'a, u32, OUT_SPEC, PIN28_A, O>; +impl<'a, const O: u8> PIN28_W<'a, O> { + #[doc = "Pin driver is low"] + #[inline(always)] + pub fn low(self) -> &'a mut W { + self.variant(PIN28_A::LOW) + } + #[doc = "Pin driver is high"] + #[inline(always)] + pub fn high(self) -> &'a mut W { + self.variant(PIN28_A::HIGH) + } +} +#[doc = "Field `PIN29` reader - Pin 29"] +pub type PIN29_R = crate::BitReader; +#[doc = "Pin 29\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN29_A { + #[doc = "0: Pin driver is low"] + LOW = 0, + #[doc = "1: Pin driver is high"] + HIGH = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN29_A) -> Self { + variant as u8 != 0 + } +} +impl PIN29_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN29_A { + match self.bits { + false => PIN29_A::LOW, + true => PIN29_A::HIGH, + } + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + *self == PIN29_A::LOW + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + *self == PIN29_A::HIGH + } +} +#[doc = "Field `PIN29` writer - Pin 29"] +pub type PIN29_W<'a, const O: u8> = crate::BitWriter<'a, u32, OUT_SPEC, PIN29_A, O>; +impl<'a, const O: u8> PIN29_W<'a, O> { + #[doc = "Pin driver is low"] + #[inline(always)] + pub fn low(self) -> &'a mut W { + self.variant(PIN29_A::LOW) + } + #[doc = "Pin driver is high"] + #[inline(always)] + pub fn high(self) -> &'a mut W { + self.variant(PIN29_A::HIGH) + } +} +#[doc = "Field `PIN30` reader - Pin 30"] +pub type PIN30_R = crate::BitReader; +#[doc = "Pin 30\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN30_A { + #[doc = "0: Pin driver is low"] + LOW = 0, + #[doc = "1: Pin driver is high"] + HIGH = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN30_A) -> Self { + variant as u8 != 0 + } +} +impl PIN30_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN30_A { + match self.bits { + false => PIN30_A::LOW, + true => PIN30_A::HIGH, + } + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + *self == PIN30_A::LOW + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + *self == PIN30_A::HIGH + } +} +#[doc = "Field `PIN30` writer - Pin 30"] +pub type PIN30_W<'a, const O: u8> = crate::BitWriter<'a, u32, OUT_SPEC, PIN30_A, O>; +impl<'a, const O: u8> PIN30_W<'a, O> { + #[doc = "Pin driver is low"] + #[inline(always)] + pub fn low(self) -> &'a mut W { + self.variant(PIN30_A::LOW) + } + #[doc = "Pin driver is high"] + #[inline(always)] + pub fn high(self) -> &'a mut W { + self.variant(PIN30_A::HIGH) + } +} +#[doc = "Field `PIN31` reader - Pin 31"] +pub type PIN31_R = crate::BitReader; +#[doc = "Pin 31\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN31_A { + #[doc = "0: Pin driver is low"] + LOW = 0, + #[doc = "1: Pin driver is high"] + HIGH = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN31_A) -> Self { + variant as u8 != 0 + } +} +impl PIN31_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN31_A { + match self.bits { + false => PIN31_A::LOW, + true => PIN31_A::HIGH, + } + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + *self == PIN31_A::LOW + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + *self == PIN31_A::HIGH + } +} +#[doc = "Field `PIN31` writer - Pin 31"] +pub type PIN31_W<'a, const O: u8> = crate::BitWriter<'a, u32, OUT_SPEC, PIN31_A, O>; +impl<'a, const O: u8> PIN31_W<'a, O> { + #[doc = "Pin driver is low"] + #[inline(always)] + pub fn low(self) -> &'a mut W { + self.variant(PIN31_A::LOW) + } + #[doc = "Pin driver is high"] + #[inline(always)] + pub fn high(self) -> &'a mut W { + self.variant(PIN31_A::HIGH) + } +} +impl R { + #[doc = "Bit 0 - Pin 0"] + #[inline(always)] + pub fn pin0(&self) -> PIN0_R { + PIN0_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Pin 1"] + #[inline(always)] + pub fn pin1(&self) -> PIN1_R { + PIN1_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Pin 2"] + #[inline(always)] + pub fn pin2(&self) -> PIN2_R { + PIN2_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Pin 3"] + #[inline(always)] + pub fn pin3(&self) -> PIN3_R { + PIN3_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Pin 4"] + #[inline(always)] + pub fn pin4(&self) -> PIN4_R { + PIN4_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Pin 5"] + #[inline(always)] + pub fn pin5(&self) -> PIN5_R { + PIN5_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Pin 6"] + #[inline(always)] + pub fn pin6(&self) -> PIN6_R { + PIN6_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Pin 7"] + #[inline(always)] + pub fn pin7(&self) -> PIN7_R { + PIN7_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Pin 8"] + #[inline(always)] + pub fn pin8(&self) -> PIN8_R { + PIN8_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Pin 9"] + #[inline(always)] + pub fn pin9(&self) -> PIN9_R { + PIN9_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Pin 10"] + #[inline(always)] + pub fn pin10(&self) -> PIN10_R { + PIN10_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Pin 11"] + #[inline(always)] + pub fn pin11(&self) -> PIN11_R { + PIN11_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Pin 12"] + #[inline(always)] + pub fn pin12(&self) -> PIN12_R { + PIN12_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Pin 13"] + #[inline(always)] + pub fn pin13(&self) -> PIN13_R { + PIN13_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Pin 14"] + #[inline(always)] + pub fn pin14(&self) -> PIN14_R { + PIN14_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Pin 15"] + #[inline(always)] + pub fn pin15(&self) -> PIN15_R { + PIN15_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - Pin 16"] + #[inline(always)] + pub fn pin16(&self) -> PIN16_R { + PIN16_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Pin 17"] + #[inline(always)] + pub fn pin17(&self) -> PIN17_R { + PIN17_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Pin 18"] + #[inline(always)] + pub fn pin18(&self) -> PIN18_R { + PIN18_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Pin 19"] + #[inline(always)] + pub fn pin19(&self) -> PIN19_R { + PIN19_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Pin 20"] + #[inline(always)] + pub fn pin20(&self) -> PIN20_R { + PIN20_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Pin 21"] + #[inline(always)] + pub fn pin21(&self) -> PIN21_R { + PIN21_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Pin 22"] + #[inline(always)] + pub fn pin22(&self) -> PIN22_R { + PIN22_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - Pin 23"] + #[inline(always)] + pub fn pin23(&self) -> PIN23_R { + PIN23_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - Pin 24"] + #[inline(always)] + pub fn pin24(&self) -> PIN24_R { + PIN24_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - Pin 25"] + #[inline(always)] + pub fn pin25(&self) -> PIN25_R { + PIN25_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - Pin 26"] + #[inline(always)] + pub fn pin26(&self) -> PIN26_R { + PIN26_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - Pin 27"] + #[inline(always)] + pub fn pin27(&self) -> PIN27_R { + PIN27_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - Pin 28"] + #[inline(always)] + pub fn pin28(&self) -> PIN28_R { + PIN28_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - Pin 29"] + #[inline(always)] + pub fn pin29(&self) -> PIN29_R { + PIN29_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Pin 30"] + #[inline(always)] + pub fn pin30(&self) -> PIN30_R { + PIN30_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Pin 31"] + #[inline(always)] + pub fn pin31(&self) -> PIN31_R { + PIN31_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Pin 0"] + #[inline(always)] + pub fn pin0(&mut self) -> PIN0_W<0> { + PIN0_W::new(self) + } + #[doc = "Bit 1 - Pin 1"] + #[inline(always)] + pub fn pin1(&mut self) -> PIN1_W<1> { + PIN1_W::new(self) + } + #[doc = "Bit 2 - Pin 2"] + #[inline(always)] + pub fn pin2(&mut self) -> PIN2_W<2> { + PIN2_W::new(self) + } + #[doc = "Bit 3 - Pin 3"] + #[inline(always)] + pub fn pin3(&mut self) -> PIN3_W<3> { + PIN3_W::new(self) + } + #[doc = "Bit 4 - Pin 4"] + #[inline(always)] + pub fn pin4(&mut self) -> PIN4_W<4> { + PIN4_W::new(self) + } + #[doc = "Bit 5 - Pin 5"] + #[inline(always)] + pub fn pin5(&mut self) -> PIN5_W<5> { + PIN5_W::new(self) + } + #[doc = "Bit 6 - Pin 6"] + #[inline(always)] + pub fn pin6(&mut self) -> PIN6_W<6> { + PIN6_W::new(self) + } + #[doc = "Bit 7 - Pin 7"] + #[inline(always)] + pub fn pin7(&mut self) -> PIN7_W<7> { + PIN7_W::new(self) + } + #[doc = "Bit 8 - Pin 8"] + #[inline(always)] + pub fn pin8(&mut self) -> PIN8_W<8> { + PIN8_W::new(self) + } + #[doc = "Bit 9 - Pin 9"] + #[inline(always)] + pub fn pin9(&mut self) -> PIN9_W<9> { + PIN9_W::new(self) + } + #[doc = "Bit 10 - Pin 10"] + #[inline(always)] + pub fn pin10(&mut self) -> PIN10_W<10> { + PIN10_W::new(self) + } + #[doc = "Bit 11 - Pin 11"] + #[inline(always)] + pub fn pin11(&mut self) -> PIN11_W<11> { + PIN11_W::new(self) + } + #[doc = "Bit 12 - Pin 12"] + #[inline(always)] + pub fn pin12(&mut self) -> PIN12_W<12> { + PIN12_W::new(self) + } + #[doc = "Bit 13 - Pin 13"] + #[inline(always)] + pub fn pin13(&mut self) -> PIN13_W<13> { + PIN13_W::new(self) + } + #[doc = "Bit 14 - Pin 14"] + #[inline(always)] + pub fn pin14(&mut self) -> PIN14_W<14> { + PIN14_W::new(self) + } + #[doc = "Bit 15 - Pin 15"] + #[inline(always)] + pub fn pin15(&mut self) -> PIN15_W<15> { + PIN15_W::new(self) + } + #[doc = "Bit 16 - Pin 16"] + #[inline(always)] + pub fn pin16(&mut self) -> PIN16_W<16> { + PIN16_W::new(self) + } + #[doc = "Bit 17 - Pin 17"] + #[inline(always)] + pub fn pin17(&mut self) -> PIN17_W<17> { + PIN17_W::new(self) + } + #[doc = "Bit 18 - Pin 18"] + #[inline(always)] + pub fn pin18(&mut self) -> PIN18_W<18> { + PIN18_W::new(self) + } + #[doc = "Bit 19 - Pin 19"] + #[inline(always)] + pub fn pin19(&mut self) -> PIN19_W<19> { + PIN19_W::new(self) + } + #[doc = "Bit 20 - Pin 20"] + #[inline(always)] + pub fn pin20(&mut self) -> PIN20_W<20> { + PIN20_W::new(self) + } + #[doc = "Bit 21 - Pin 21"] + #[inline(always)] + pub fn pin21(&mut self) -> PIN21_W<21> { + PIN21_W::new(self) + } + #[doc = "Bit 22 - Pin 22"] + #[inline(always)] + pub fn pin22(&mut self) -> PIN22_W<22> { + PIN22_W::new(self) + } + #[doc = "Bit 23 - Pin 23"] + #[inline(always)] + pub fn pin23(&mut self) -> PIN23_W<23> { + PIN23_W::new(self) + } + #[doc = "Bit 24 - Pin 24"] + #[inline(always)] + pub fn pin24(&mut self) -> PIN24_W<24> { + PIN24_W::new(self) + } + #[doc = "Bit 25 - Pin 25"] + #[inline(always)] + pub fn pin25(&mut self) -> PIN25_W<25> { + PIN25_W::new(self) + } + #[doc = "Bit 26 - Pin 26"] + #[inline(always)] + pub fn pin26(&mut self) -> PIN26_W<26> { + PIN26_W::new(self) + } + #[doc = "Bit 27 - Pin 27"] + #[inline(always)] + pub fn pin27(&mut self) -> PIN27_W<27> { + PIN27_W::new(self) + } + #[doc = "Bit 28 - Pin 28"] + #[inline(always)] + pub fn pin28(&mut self) -> PIN28_W<28> { + PIN28_W::new(self) + } + #[doc = "Bit 29 - Pin 29"] + #[inline(always)] + pub fn pin29(&mut self) -> PIN29_W<29> { + PIN29_W::new(self) + } + #[doc = "Bit 30 - Pin 30"] + #[inline(always)] + pub fn pin30(&mut self) -> PIN30_W<30> { + PIN30_W::new(self) + } + #[doc = "Bit 31 - Pin 31"] + #[inline(always)] + pub fn pin31(&mut self) -> PIN31_W<31> { + PIN31_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Write GPIO port\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [out](index.html) module"] +pub struct OUT_SPEC; +impl crate::RegisterSpec for OUT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [out::R](R) reader structure"] +impl crate::Readable for OUT_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [out::W](W) writer structure"] +impl crate::Writable for OUT_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets OUT to value 0"] +impl crate::Resettable for OUT_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/p0_ns/outclr.rs b/pacs/nrf9120-pac/src/p0_ns/outclr.rs new file mode 100644 index 00000000..ed51ecdc --- /dev/null +++ b/pacs/nrf9120-pac/src/p0_ns/outclr.rs @@ -0,0 +1,2210 @@ +#[doc = "Register `OUTCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `OUTCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PIN0` reader - Pin 0"] +pub type PIN0_R = crate::BitReader; +#[doc = "Pin 0\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN0_A { + #[doc = "0: Read: pin driver is low"] + LOW = 0, + #[doc = "1: Read: pin driver is high"] + HIGH = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN0_A) -> Self { + variant as u8 != 0 + } +} +impl PIN0_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN0_A { + match self.bits { + false => PIN0_A::LOW, + true => PIN0_A::HIGH, + } + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + *self == PIN0_A::LOW + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + *self == PIN0_A::HIGH + } +} +#[doc = "Pin 0\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN0_AW { + #[doc = "1: Write: writing a '1' sets the pin low; writing a '0' has no effect"] + CLEAR = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN0_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PIN0` writer - Pin 0"] +pub type PIN0_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, OUTCLR_SPEC, PIN0_AW, O>; +impl<'a, const O: u8> PIN0_W<'a, O> { + #[doc = "Write: writing a '1' sets the pin low; writing a '0' has no effect"] + #[inline(always)] + pub fn clear(self) -> &'a mut W { + self.variant(PIN0_AW::CLEAR) + } +} +#[doc = "Field `PIN1` reader - Pin 1"] +pub type PIN1_R = crate::BitReader; +#[doc = "Pin 1\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN1_A { + #[doc = "0: Read: pin driver is low"] + LOW = 0, + #[doc = "1: Read: pin driver is high"] + HIGH = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN1_A) -> Self { + variant as u8 != 0 + } +} +impl PIN1_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN1_A { + match self.bits { + false => PIN1_A::LOW, + true => PIN1_A::HIGH, + } + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + *self == PIN1_A::LOW + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + *self == PIN1_A::HIGH + } +} +#[doc = "Pin 1\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN1_AW { + #[doc = "1: Write: writing a '1' sets the pin low; writing a '0' has no effect"] + CLEAR = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN1_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PIN1` writer - Pin 1"] +pub type PIN1_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, OUTCLR_SPEC, PIN1_AW, O>; +impl<'a, const O: u8> PIN1_W<'a, O> { + #[doc = "Write: writing a '1' sets the pin low; writing a '0' has no effect"] + #[inline(always)] + pub fn clear(self) -> &'a mut W { + self.variant(PIN1_AW::CLEAR) + } +} +#[doc = "Field `PIN2` reader - Pin 2"] +pub type PIN2_R = crate::BitReader; +#[doc = "Pin 2\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN2_A { + #[doc = "0: Read: pin driver is low"] + LOW = 0, + #[doc = "1: Read: pin driver is high"] + HIGH = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN2_A) -> Self { + variant as u8 != 0 + } +} +impl PIN2_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN2_A { + match self.bits { + false => PIN2_A::LOW, + true => PIN2_A::HIGH, + } + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + *self == PIN2_A::LOW + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + *self == PIN2_A::HIGH + } +} +#[doc = "Pin 2\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN2_AW { + #[doc = "1: Write: writing a '1' sets the pin low; writing a '0' has no effect"] + CLEAR = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN2_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PIN2` writer - Pin 2"] +pub type PIN2_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, OUTCLR_SPEC, PIN2_AW, O>; +impl<'a, const O: u8> PIN2_W<'a, O> { + #[doc = "Write: writing a '1' sets the pin low; writing a '0' has no effect"] + #[inline(always)] + pub fn clear(self) -> &'a mut W { + self.variant(PIN2_AW::CLEAR) + } +} +#[doc = "Field `PIN3` reader - Pin 3"] +pub type PIN3_R = crate::BitReader; +#[doc = "Pin 3\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN3_A { + #[doc = "0: Read: pin driver is low"] + LOW = 0, + #[doc = "1: Read: pin driver is high"] + HIGH = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN3_A) -> Self { + variant as u8 != 0 + } +} +impl PIN3_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN3_A { + match self.bits { + false => PIN3_A::LOW, + true => PIN3_A::HIGH, + } + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + *self == PIN3_A::LOW + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + *self == PIN3_A::HIGH + } +} +#[doc = "Pin 3\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN3_AW { + #[doc = "1: Write: writing a '1' sets the pin low; writing a '0' has no effect"] + CLEAR = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN3_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PIN3` writer - Pin 3"] +pub type PIN3_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, OUTCLR_SPEC, PIN3_AW, O>; +impl<'a, const O: u8> PIN3_W<'a, O> { + #[doc = "Write: writing a '1' sets the pin low; writing a '0' has no effect"] + #[inline(always)] + pub fn clear(self) -> &'a mut W { + self.variant(PIN3_AW::CLEAR) + } +} +#[doc = "Field `PIN4` reader - Pin 4"] +pub type PIN4_R = crate::BitReader; +#[doc = "Pin 4\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN4_A { + #[doc = "0: Read: pin driver is low"] + LOW = 0, + #[doc = "1: Read: pin driver is high"] + HIGH = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN4_A) -> Self { + variant as u8 != 0 + } +} +impl PIN4_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN4_A { + match self.bits { + false => PIN4_A::LOW, + true => PIN4_A::HIGH, + } + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + *self == PIN4_A::LOW + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + *self == PIN4_A::HIGH + } +} +#[doc = "Pin 4\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN4_AW { + #[doc = "1: Write: writing a '1' sets the pin low; writing a '0' has no effect"] + CLEAR = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN4_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PIN4` writer - Pin 4"] +pub type PIN4_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, OUTCLR_SPEC, PIN4_AW, O>; +impl<'a, const O: u8> PIN4_W<'a, O> { + #[doc = "Write: writing a '1' sets the pin low; writing a '0' has no effect"] + #[inline(always)] + pub fn clear(self) -> &'a mut W { + self.variant(PIN4_AW::CLEAR) + } +} +#[doc = "Field `PIN5` reader - Pin 5"] +pub type PIN5_R = crate::BitReader; +#[doc = "Pin 5\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN5_A { + #[doc = "0: Read: pin driver is low"] + LOW = 0, + #[doc = "1: Read: pin driver is high"] + HIGH = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN5_A) -> Self { + variant as u8 != 0 + } +} +impl PIN5_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN5_A { + match self.bits { + false => PIN5_A::LOW, + true => PIN5_A::HIGH, + } + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + *self == PIN5_A::LOW + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + *self == PIN5_A::HIGH + } +} +#[doc = "Pin 5\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN5_AW { + #[doc = "1: Write: writing a '1' sets the pin low; writing a '0' has no effect"] + CLEAR = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN5_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PIN5` writer - Pin 5"] +pub type PIN5_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, OUTCLR_SPEC, PIN5_AW, O>; +impl<'a, const O: u8> PIN5_W<'a, O> { + #[doc = "Write: writing a '1' sets the pin low; writing a '0' has no effect"] + #[inline(always)] + pub fn clear(self) -> &'a mut W { + self.variant(PIN5_AW::CLEAR) + } +} +#[doc = "Field `PIN6` reader - Pin 6"] +pub type PIN6_R = crate::BitReader; +#[doc = "Pin 6\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN6_A { + #[doc = "0: Read: pin driver is low"] + LOW = 0, + #[doc = "1: Read: pin driver is high"] + HIGH = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN6_A) -> Self { + variant as u8 != 0 + } +} +impl PIN6_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN6_A { + match self.bits { + false => PIN6_A::LOW, + true => PIN6_A::HIGH, + } + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + *self == PIN6_A::LOW + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + *self == PIN6_A::HIGH + } +} +#[doc = "Pin 6\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN6_AW { + #[doc = "1: Write: writing a '1' sets the pin low; writing a '0' has no effect"] + CLEAR = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN6_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PIN6` writer - Pin 6"] +pub type PIN6_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, OUTCLR_SPEC, PIN6_AW, O>; +impl<'a, const O: u8> PIN6_W<'a, O> { + #[doc = "Write: writing a '1' sets the pin low; writing a '0' has no effect"] + #[inline(always)] + pub fn clear(self) -> &'a mut W { + self.variant(PIN6_AW::CLEAR) + } +} +#[doc = "Field `PIN7` reader - Pin 7"] +pub type PIN7_R = crate::BitReader; +#[doc = "Pin 7\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN7_A { + #[doc = "0: Read: pin driver is low"] + LOW = 0, + #[doc = "1: Read: pin driver is high"] + HIGH = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN7_A) -> Self { + variant as u8 != 0 + } +} +impl PIN7_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN7_A { + match self.bits { + false => PIN7_A::LOW, + true => PIN7_A::HIGH, + } + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + *self == PIN7_A::LOW + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + *self == PIN7_A::HIGH + } +} +#[doc = "Pin 7\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN7_AW { + #[doc = "1: Write: writing a '1' sets the pin low; writing a '0' has no effect"] + CLEAR = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN7_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PIN7` writer - Pin 7"] +pub type PIN7_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, OUTCLR_SPEC, PIN7_AW, O>; +impl<'a, const O: u8> PIN7_W<'a, O> { + #[doc = "Write: writing a '1' sets the pin low; writing a '0' has no effect"] + #[inline(always)] + pub fn clear(self) -> &'a mut W { + self.variant(PIN7_AW::CLEAR) + } +} +#[doc = "Field `PIN8` reader - Pin 8"] +pub type PIN8_R = crate::BitReader; +#[doc = "Pin 8\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN8_A { + #[doc = "0: Read: pin driver is low"] + LOW = 0, + #[doc = "1: Read: pin driver is high"] + HIGH = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN8_A) -> Self { + variant as u8 != 0 + } +} +impl PIN8_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN8_A { + match self.bits { + false => PIN8_A::LOW, + true => PIN8_A::HIGH, + } + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + *self == PIN8_A::LOW + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + *self == PIN8_A::HIGH + } +} +#[doc = "Pin 8\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN8_AW { + #[doc = "1: Write: writing a '1' sets the pin low; writing a '0' has no effect"] + CLEAR = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN8_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PIN8` writer - Pin 8"] +pub type PIN8_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, OUTCLR_SPEC, PIN8_AW, O>; +impl<'a, const O: u8> PIN8_W<'a, O> { + #[doc = "Write: writing a '1' sets the pin low; writing a '0' has no effect"] + #[inline(always)] + pub fn clear(self) -> &'a mut W { + self.variant(PIN8_AW::CLEAR) + } +} +#[doc = "Field `PIN9` reader - Pin 9"] +pub type PIN9_R = crate::BitReader; +#[doc = "Pin 9\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN9_A { + #[doc = "0: Read: pin driver is low"] + LOW = 0, + #[doc = "1: Read: pin driver is high"] + HIGH = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN9_A) -> Self { + variant as u8 != 0 + } +} +impl PIN9_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN9_A { + match self.bits { + false => PIN9_A::LOW, + true => PIN9_A::HIGH, + } + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + *self == PIN9_A::LOW + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + *self == PIN9_A::HIGH + } +} +#[doc = "Pin 9\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN9_AW { + #[doc = "1: Write: writing a '1' sets the pin low; writing a '0' has no effect"] + CLEAR = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN9_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PIN9` writer - Pin 9"] +pub type PIN9_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, OUTCLR_SPEC, PIN9_AW, O>; +impl<'a, const O: u8> PIN9_W<'a, O> { + #[doc = "Write: writing a '1' sets the pin low; writing a '0' has no effect"] + #[inline(always)] + pub fn clear(self) -> &'a mut W { + self.variant(PIN9_AW::CLEAR) + } +} +#[doc = "Field `PIN10` reader - Pin 10"] +pub type PIN10_R = crate::BitReader; +#[doc = "Pin 10\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN10_A { + #[doc = "0: Read: pin driver is low"] + LOW = 0, + #[doc = "1: Read: pin driver is high"] + HIGH = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN10_A) -> Self { + variant as u8 != 0 + } +} +impl PIN10_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN10_A { + match self.bits { + false => PIN10_A::LOW, + true => PIN10_A::HIGH, + } + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + *self == PIN10_A::LOW + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + *self == PIN10_A::HIGH + } +} +#[doc = "Pin 10\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN10_AW { + #[doc = "1: Write: writing a '1' sets the pin low; writing a '0' has no effect"] + CLEAR = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN10_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PIN10` writer - Pin 10"] +pub type PIN10_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, OUTCLR_SPEC, PIN10_AW, O>; +impl<'a, const O: u8> PIN10_W<'a, O> { + #[doc = "Write: writing a '1' sets the pin low; writing a '0' has no effect"] + #[inline(always)] + pub fn clear(self) -> &'a mut W { + self.variant(PIN10_AW::CLEAR) + } +} +#[doc = "Field `PIN11` reader - Pin 11"] +pub type PIN11_R = crate::BitReader; +#[doc = "Pin 11\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN11_A { + #[doc = "0: Read: pin driver is low"] + LOW = 0, + #[doc = "1: Read: pin driver is high"] + HIGH = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN11_A) -> Self { + variant as u8 != 0 + } +} +impl PIN11_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN11_A { + match self.bits { + false => PIN11_A::LOW, + true => PIN11_A::HIGH, + } + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + *self == PIN11_A::LOW + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + *self == PIN11_A::HIGH + } +} +#[doc = "Pin 11\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN11_AW { + #[doc = "1: Write: writing a '1' sets the pin low; writing a '0' has no effect"] + CLEAR = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN11_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PIN11` writer - Pin 11"] +pub type PIN11_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, OUTCLR_SPEC, PIN11_AW, O>; +impl<'a, const O: u8> PIN11_W<'a, O> { + #[doc = "Write: writing a '1' sets the pin low; writing a '0' has no effect"] + #[inline(always)] + pub fn clear(self) -> &'a mut W { + self.variant(PIN11_AW::CLEAR) + } +} +#[doc = "Field `PIN12` reader - Pin 12"] +pub type PIN12_R = crate::BitReader; +#[doc = "Pin 12\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN12_A { + #[doc = "0: Read: pin driver is low"] + LOW = 0, + #[doc = "1: Read: pin driver is high"] + HIGH = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN12_A) -> Self { + variant as u8 != 0 + } +} +impl PIN12_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN12_A { + match self.bits { + false => PIN12_A::LOW, + true => PIN12_A::HIGH, + } + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + *self == PIN12_A::LOW + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + *self == PIN12_A::HIGH + } +} +#[doc = "Pin 12\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN12_AW { + #[doc = "1: Write: writing a '1' sets the pin low; writing a '0' has no effect"] + CLEAR = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN12_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PIN12` writer - Pin 12"] +pub type PIN12_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, OUTCLR_SPEC, PIN12_AW, O>; +impl<'a, const O: u8> PIN12_W<'a, O> { + #[doc = "Write: writing a '1' sets the pin low; writing a '0' has no effect"] + #[inline(always)] + pub fn clear(self) -> &'a mut W { + self.variant(PIN12_AW::CLEAR) + } +} +#[doc = "Field `PIN13` reader - Pin 13"] +pub type PIN13_R = crate::BitReader; +#[doc = "Pin 13\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN13_A { + #[doc = "0: Read: pin driver is low"] + LOW = 0, + #[doc = "1: Read: pin driver is high"] + HIGH = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN13_A) -> Self { + variant as u8 != 0 + } +} +impl PIN13_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN13_A { + match self.bits { + false => PIN13_A::LOW, + true => PIN13_A::HIGH, + } + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + *self == PIN13_A::LOW + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + *self == PIN13_A::HIGH + } +} +#[doc = "Pin 13\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN13_AW { + #[doc = "1: Write: writing a '1' sets the pin low; writing a '0' has no effect"] + CLEAR = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN13_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PIN13` writer - Pin 13"] +pub type PIN13_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, OUTCLR_SPEC, PIN13_AW, O>; +impl<'a, const O: u8> PIN13_W<'a, O> { + #[doc = "Write: writing a '1' sets the pin low; writing a '0' has no effect"] + #[inline(always)] + pub fn clear(self) -> &'a mut W { + self.variant(PIN13_AW::CLEAR) + } +} +#[doc = "Field `PIN14` reader - Pin 14"] +pub type PIN14_R = crate::BitReader; +#[doc = "Pin 14\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN14_A { + #[doc = "0: Read: pin driver is low"] + LOW = 0, + #[doc = "1: Read: pin driver is high"] + HIGH = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN14_A) -> Self { + variant as u8 != 0 + } +} +impl PIN14_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN14_A { + match self.bits { + false => PIN14_A::LOW, + true => PIN14_A::HIGH, + } + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + *self == PIN14_A::LOW + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + *self == PIN14_A::HIGH + } +} +#[doc = "Pin 14\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN14_AW { + #[doc = "1: Write: writing a '1' sets the pin low; writing a '0' has no effect"] + CLEAR = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN14_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PIN14` writer - Pin 14"] +pub type PIN14_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, OUTCLR_SPEC, PIN14_AW, O>; +impl<'a, const O: u8> PIN14_W<'a, O> { + #[doc = "Write: writing a '1' sets the pin low; writing a '0' has no effect"] + #[inline(always)] + pub fn clear(self) -> &'a mut W { + self.variant(PIN14_AW::CLEAR) + } +} +#[doc = "Field `PIN15` reader - Pin 15"] +pub type PIN15_R = crate::BitReader; +#[doc = "Pin 15\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN15_A { + #[doc = "0: Read: pin driver is low"] + LOW = 0, + #[doc = "1: Read: pin driver is high"] + HIGH = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN15_A) -> Self { + variant as u8 != 0 + } +} +impl PIN15_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN15_A { + match self.bits { + false => PIN15_A::LOW, + true => PIN15_A::HIGH, + } + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + *self == PIN15_A::LOW + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + *self == PIN15_A::HIGH + } +} +#[doc = "Pin 15\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN15_AW { + #[doc = "1: Write: writing a '1' sets the pin low; writing a '0' has no effect"] + CLEAR = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN15_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PIN15` writer - Pin 15"] +pub type PIN15_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, OUTCLR_SPEC, PIN15_AW, O>; +impl<'a, const O: u8> PIN15_W<'a, O> { + #[doc = "Write: writing a '1' sets the pin low; writing a '0' has no effect"] + #[inline(always)] + pub fn clear(self) -> &'a mut W { + self.variant(PIN15_AW::CLEAR) + } +} +#[doc = "Field `PIN16` reader - Pin 16"] +pub type PIN16_R = crate::BitReader; +#[doc = "Pin 16\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN16_A { + #[doc = "0: Read: pin driver is low"] + LOW = 0, + #[doc = "1: Read: pin driver is high"] + HIGH = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN16_A) -> Self { + variant as u8 != 0 + } +} +impl PIN16_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN16_A { + match self.bits { + false => PIN16_A::LOW, + true => PIN16_A::HIGH, + } + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + *self == PIN16_A::LOW + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + *self == PIN16_A::HIGH + } +} +#[doc = "Pin 16\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN16_AW { + #[doc = "1: Write: writing a '1' sets the pin low; writing a '0' has no effect"] + CLEAR = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN16_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PIN16` writer - Pin 16"] +pub type PIN16_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, OUTCLR_SPEC, PIN16_AW, O>; +impl<'a, const O: u8> PIN16_W<'a, O> { + #[doc = "Write: writing a '1' sets the pin low; writing a '0' has no effect"] + #[inline(always)] + pub fn clear(self) -> &'a mut W { + self.variant(PIN16_AW::CLEAR) + } +} +#[doc = "Field `PIN17` reader - Pin 17"] +pub type PIN17_R = crate::BitReader; +#[doc = "Pin 17\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN17_A { + #[doc = "0: Read: pin driver is low"] + LOW = 0, + #[doc = "1: Read: pin driver is high"] + HIGH = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN17_A) -> Self { + variant as u8 != 0 + } +} +impl PIN17_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN17_A { + match self.bits { + false => PIN17_A::LOW, + true => PIN17_A::HIGH, + } + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + *self == PIN17_A::LOW + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + *self == PIN17_A::HIGH + } +} +#[doc = "Pin 17\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN17_AW { + #[doc = "1: Write: writing a '1' sets the pin low; writing a '0' has no effect"] + CLEAR = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN17_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PIN17` writer - Pin 17"] +pub type PIN17_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, OUTCLR_SPEC, PIN17_AW, O>; +impl<'a, const O: u8> PIN17_W<'a, O> { + #[doc = "Write: writing a '1' sets the pin low; writing a '0' has no effect"] + #[inline(always)] + pub fn clear(self) -> &'a mut W { + self.variant(PIN17_AW::CLEAR) + } +} +#[doc = "Field `PIN18` reader - Pin 18"] +pub type PIN18_R = crate::BitReader; +#[doc = "Pin 18\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN18_A { + #[doc = "0: Read: pin driver is low"] + LOW = 0, + #[doc = "1: Read: pin driver is high"] + HIGH = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN18_A) -> Self { + variant as u8 != 0 + } +} +impl PIN18_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN18_A { + match self.bits { + false => PIN18_A::LOW, + true => PIN18_A::HIGH, + } + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + *self == PIN18_A::LOW + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + *self == PIN18_A::HIGH + } +} +#[doc = "Pin 18\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN18_AW { + #[doc = "1: Write: writing a '1' sets the pin low; writing a '0' has no effect"] + CLEAR = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN18_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PIN18` writer - Pin 18"] +pub type PIN18_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, OUTCLR_SPEC, PIN18_AW, O>; +impl<'a, const O: u8> PIN18_W<'a, O> { + #[doc = "Write: writing a '1' sets the pin low; writing a '0' has no effect"] + #[inline(always)] + pub fn clear(self) -> &'a mut W { + self.variant(PIN18_AW::CLEAR) + } +} +#[doc = "Field `PIN19` reader - Pin 19"] +pub type PIN19_R = crate::BitReader; +#[doc = "Pin 19\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN19_A { + #[doc = "0: Read: pin driver is low"] + LOW = 0, + #[doc = "1: Read: pin driver is high"] + HIGH = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN19_A) -> Self { + variant as u8 != 0 + } +} +impl PIN19_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN19_A { + match self.bits { + false => PIN19_A::LOW, + true => PIN19_A::HIGH, + } + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + *self == PIN19_A::LOW + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + *self == PIN19_A::HIGH + } +} +#[doc = "Pin 19\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN19_AW { + #[doc = "1: Write: writing a '1' sets the pin low; writing a '0' has no effect"] + CLEAR = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN19_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PIN19` writer - Pin 19"] +pub type PIN19_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, OUTCLR_SPEC, PIN19_AW, O>; +impl<'a, const O: u8> PIN19_W<'a, O> { + #[doc = "Write: writing a '1' sets the pin low; writing a '0' has no effect"] + #[inline(always)] + pub fn clear(self) -> &'a mut W { + self.variant(PIN19_AW::CLEAR) + } +} +#[doc = "Field `PIN20` reader - Pin 20"] +pub type PIN20_R = crate::BitReader; +#[doc = "Pin 20\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN20_A { + #[doc = "0: Read: pin driver is low"] + LOW = 0, + #[doc = "1: Read: pin driver is high"] + HIGH = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN20_A) -> Self { + variant as u8 != 0 + } +} +impl PIN20_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN20_A { + match self.bits { + false => PIN20_A::LOW, + true => PIN20_A::HIGH, + } + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + *self == PIN20_A::LOW + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + *self == PIN20_A::HIGH + } +} +#[doc = "Pin 20\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN20_AW { + #[doc = "1: Write: writing a '1' sets the pin low; writing a '0' has no effect"] + CLEAR = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN20_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PIN20` writer - Pin 20"] +pub type PIN20_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, OUTCLR_SPEC, PIN20_AW, O>; +impl<'a, const O: u8> PIN20_W<'a, O> { + #[doc = "Write: writing a '1' sets the pin low; writing a '0' has no effect"] + #[inline(always)] + pub fn clear(self) -> &'a mut W { + self.variant(PIN20_AW::CLEAR) + } +} +#[doc = "Field `PIN21` reader - Pin 21"] +pub type PIN21_R = crate::BitReader; +#[doc = "Pin 21\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN21_A { + #[doc = "0: Read: pin driver is low"] + LOW = 0, + #[doc = "1: Read: pin driver is high"] + HIGH = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN21_A) -> Self { + variant as u8 != 0 + } +} +impl PIN21_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN21_A { + match self.bits { + false => PIN21_A::LOW, + true => PIN21_A::HIGH, + } + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + *self == PIN21_A::LOW + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + *self == PIN21_A::HIGH + } +} +#[doc = "Pin 21\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN21_AW { + #[doc = "1: Write: writing a '1' sets the pin low; writing a '0' has no effect"] + CLEAR = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN21_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PIN21` writer - Pin 21"] +pub type PIN21_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, OUTCLR_SPEC, PIN21_AW, O>; +impl<'a, const O: u8> PIN21_W<'a, O> { + #[doc = "Write: writing a '1' sets the pin low; writing a '0' has no effect"] + #[inline(always)] + pub fn clear(self) -> &'a mut W { + self.variant(PIN21_AW::CLEAR) + } +} +#[doc = "Field `PIN22` reader - Pin 22"] +pub type PIN22_R = crate::BitReader; +#[doc = "Pin 22\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN22_A { + #[doc = "0: Read: pin driver is low"] + LOW = 0, + #[doc = "1: Read: pin driver is high"] + HIGH = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN22_A) -> Self { + variant as u8 != 0 + } +} +impl PIN22_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN22_A { + match self.bits { + false => PIN22_A::LOW, + true => PIN22_A::HIGH, + } + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + *self == PIN22_A::LOW + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + *self == PIN22_A::HIGH + } +} +#[doc = "Pin 22\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN22_AW { + #[doc = "1: Write: writing a '1' sets the pin low; writing a '0' has no effect"] + CLEAR = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN22_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PIN22` writer - Pin 22"] +pub type PIN22_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, OUTCLR_SPEC, PIN22_AW, O>; +impl<'a, const O: u8> PIN22_W<'a, O> { + #[doc = "Write: writing a '1' sets the pin low; writing a '0' has no effect"] + #[inline(always)] + pub fn clear(self) -> &'a mut W { + self.variant(PIN22_AW::CLEAR) + } +} +#[doc = "Field `PIN23` reader - Pin 23"] +pub type PIN23_R = crate::BitReader; +#[doc = "Pin 23\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN23_A { + #[doc = "0: Read: pin driver is low"] + LOW = 0, + #[doc = "1: Read: pin driver is high"] + HIGH = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN23_A) -> Self { + variant as u8 != 0 + } +} +impl PIN23_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN23_A { + match self.bits { + false => PIN23_A::LOW, + true => PIN23_A::HIGH, + } + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + *self == PIN23_A::LOW + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + *self == PIN23_A::HIGH + } +} +#[doc = "Pin 23\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN23_AW { + #[doc = "1: Write: writing a '1' sets the pin low; writing a '0' has no effect"] + CLEAR = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN23_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PIN23` writer - Pin 23"] +pub type PIN23_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, OUTCLR_SPEC, PIN23_AW, O>; +impl<'a, const O: u8> PIN23_W<'a, O> { + #[doc = "Write: writing a '1' sets the pin low; writing a '0' has no effect"] + #[inline(always)] + pub fn clear(self) -> &'a mut W { + self.variant(PIN23_AW::CLEAR) + } +} +#[doc = "Field `PIN24` reader - Pin 24"] +pub type PIN24_R = crate::BitReader; +#[doc = "Pin 24\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN24_A { + #[doc = "0: Read: pin driver is low"] + LOW = 0, + #[doc = "1: Read: pin driver is high"] + HIGH = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN24_A) -> Self { + variant as u8 != 0 + } +} +impl PIN24_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN24_A { + match self.bits { + false => PIN24_A::LOW, + true => PIN24_A::HIGH, + } + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + *self == PIN24_A::LOW + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + *self == PIN24_A::HIGH + } +} +#[doc = "Pin 24\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN24_AW { + #[doc = "1: Write: writing a '1' sets the pin low; writing a '0' has no effect"] + CLEAR = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN24_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PIN24` writer - Pin 24"] +pub type PIN24_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, OUTCLR_SPEC, PIN24_AW, O>; +impl<'a, const O: u8> PIN24_W<'a, O> { + #[doc = "Write: writing a '1' sets the pin low; writing a '0' has no effect"] + #[inline(always)] + pub fn clear(self) -> &'a mut W { + self.variant(PIN24_AW::CLEAR) + } +} +#[doc = "Field `PIN25` reader - Pin 25"] +pub type PIN25_R = crate::BitReader; +#[doc = "Pin 25\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN25_A { + #[doc = "0: Read: pin driver is low"] + LOW = 0, + #[doc = "1: Read: pin driver is high"] + HIGH = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN25_A) -> Self { + variant as u8 != 0 + } +} +impl PIN25_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN25_A { + match self.bits { + false => PIN25_A::LOW, + true => PIN25_A::HIGH, + } + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + *self == PIN25_A::LOW + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + *self == PIN25_A::HIGH + } +} +#[doc = "Pin 25\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN25_AW { + #[doc = "1: Write: writing a '1' sets the pin low; writing a '0' has no effect"] + CLEAR = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN25_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PIN25` writer - Pin 25"] +pub type PIN25_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, OUTCLR_SPEC, PIN25_AW, O>; +impl<'a, const O: u8> PIN25_W<'a, O> { + #[doc = "Write: writing a '1' sets the pin low; writing a '0' has no effect"] + #[inline(always)] + pub fn clear(self) -> &'a mut W { + self.variant(PIN25_AW::CLEAR) + } +} +#[doc = "Field `PIN26` reader - Pin 26"] +pub type PIN26_R = crate::BitReader; +#[doc = "Pin 26\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN26_A { + #[doc = "0: Read: pin driver is low"] + LOW = 0, + #[doc = "1: Read: pin driver is high"] + HIGH = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN26_A) -> Self { + variant as u8 != 0 + } +} +impl PIN26_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN26_A { + match self.bits { + false => PIN26_A::LOW, + true => PIN26_A::HIGH, + } + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + *self == PIN26_A::LOW + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + *self == PIN26_A::HIGH + } +} +#[doc = "Pin 26\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN26_AW { + #[doc = "1: Write: writing a '1' sets the pin low; writing a '0' has no effect"] + CLEAR = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN26_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PIN26` writer - Pin 26"] +pub type PIN26_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, OUTCLR_SPEC, PIN26_AW, O>; +impl<'a, const O: u8> PIN26_W<'a, O> { + #[doc = "Write: writing a '1' sets the pin low; writing a '0' has no effect"] + #[inline(always)] + pub fn clear(self) -> &'a mut W { + self.variant(PIN26_AW::CLEAR) + } +} +#[doc = "Field `PIN27` reader - Pin 27"] +pub type PIN27_R = crate::BitReader; +#[doc = "Pin 27\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN27_A { + #[doc = "0: Read: pin driver is low"] + LOW = 0, + #[doc = "1: Read: pin driver is high"] + HIGH = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN27_A) -> Self { + variant as u8 != 0 + } +} +impl PIN27_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN27_A { + match self.bits { + false => PIN27_A::LOW, + true => PIN27_A::HIGH, + } + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + *self == PIN27_A::LOW + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + *self == PIN27_A::HIGH + } +} +#[doc = "Pin 27\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN27_AW { + #[doc = "1: Write: writing a '1' sets the pin low; writing a '0' has no effect"] + CLEAR = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN27_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PIN27` writer - Pin 27"] +pub type PIN27_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, OUTCLR_SPEC, PIN27_AW, O>; +impl<'a, const O: u8> PIN27_W<'a, O> { + #[doc = "Write: writing a '1' sets the pin low; writing a '0' has no effect"] + #[inline(always)] + pub fn clear(self) -> &'a mut W { + self.variant(PIN27_AW::CLEAR) + } +} +#[doc = "Field `PIN28` reader - Pin 28"] +pub type PIN28_R = crate::BitReader; +#[doc = "Pin 28\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN28_A { + #[doc = "0: Read: pin driver is low"] + LOW = 0, + #[doc = "1: Read: pin driver is high"] + HIGH = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN28_A) -> Self { + variant as u8 != 0 + } +} +impl PIN28_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN28_A { + match self.bits { + false => PIN28_A::LOW, + true => PIN28_A::HIGH, + } + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + *self == PIN28_A::LOW + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + *self == PIN28_A::HIGH + } +} +#[doc = "Pin 28\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN28_AW { + #[doc = "1: Write: writing a '1' sets the pin low; writing a '0' has no effect"] + CLEAR = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN28_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PIN28` writer - Pin 28"] +pub type PIN28_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, OUTCLR_SPEC, PIN28_AW, O>; +impl<'a, const O: u8> PIN28_W<'a, O> { + #[doc = "Write: writing a '1' sets the pin low; writing a '0' has no effect"] + #[inline(always)] + pub fn clear(self) -> &'a mut W { + self.variant(PIN28_AW::CLEAR) + } +} +#[doc = "Field `PIN29` reader - Pin 29"] +pub type PIN29_R = crate::BitReader; +#[doc = "Pin 29\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN29_A { + #[doc = "0: Read: pin driver is low"] + LOW = 0, + #[doc = "1: Read: pin driver is high"] + HIGH = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN29_A) -> Self { + variant as u8 != 0 + } +} +impl PIN29_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN29_A { + match self.bits { + false => PIN29_A::LOW, + true => PIN29_A::HIGH, + } + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + *self == PIN29_A::LOW + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + *self == PIN29_A::HIGH + } +} +#[doc = "Pin 29\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN29_AW { + #[doc = "1: Write: writing a '1' sets the pin low; writing a '0' has no effect"] + CLEAR = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN29_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PIN29` writer - Pin 29"] +pub type PIN29_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, OUTCLR_SPEC, PIN29_AW, O>; +impl<'a, const O: u8> PIN29_W<'a, O> { + #[doc = "Write: writing a '1' sets the pin low; writing a '0' has no effect"] + #[inline(always)] + pub fn clear(self) -> &'a mut W { + self.variant(PIN29_AW::CLEAR) + } +} +#[doc = "Field `PIN30` reader - Pin 30"] +pub type PIN30_R = crate::BitReader; +#[doc = "Pin 30\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN30_A { + #[doc = "0: Read: pin driver is low"] + LOW = 0, + #[doc = "1: Read: pin driver is high"] + HIGH = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN30_A) -> Self { + variant as u8 != 0 + } +} +impl PIN30_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN30_A { + match self.bits { + false => PIN30_A::LOW, + true => PIN30_A::HIGH, + } + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + *self == PIN30_A::LOW + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + *self == PIN30_A::HIGH + } +} +#[doc = "Pin 30\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN30_AW { + #[doc = "1: Write: writing a '1' sets the pin low; writing a '0' has no effect"] + CLEAR = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN30_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PIN30` writer - Pin 30"] +pub type PIN30_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, OUTCLR_SPEC, PIN30_AW, O>; +impl<'a, const O: u8> PIN30_W<'a, O> { + #[doc = "Write: writing a '1' sets the pin low; writing a '0' has no effect"] + #[inline(always)] + pub fn clear(self) -> &'a mut W { + self.variant(PIN30_AW::CLEAR) + } +} +#[doc = "Field `PIN31` reader - Pin 31"] +pub type PIN31_R = crate::BitReader; +#[doc = "Pin 31\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN31_A { + #[doc = "0: Read: pin driver is low"] + LOW = 0, + #[doc = "1: Read: pin driver is high"] + HIGH = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN31_A) -> Self { + variant as u8 != 0 + } +} +impl PIN31_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN31_A { + match self.bits { + false => PIN31_A::LOW, + true => PIN31_A::HIGH, + } + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + *self == PIN31_A::LOW + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + *self == PIN31_A::HIGH + } +} +#[doc = "Pin 31\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN31_AW { + #[doc = "1: Write: writing a '1' sets the pin low; writing a '0' has no effect"] + CLEAR = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN31_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PIN31` writer - Pin 31"] +pub type PIN31_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, OUTCLR_SPEC, PIN31_AW, O>; +impl<'a, const O: u8> PIN31_W<'a, O> { + #[doc = "Write: writing a '1' sets the pin low; writing a '0' has no effect"] + #[inline(always)] + pub fn clear(self) -> &'a mut W { + self.variant(PIN31_AW::CLEAR) + } +} +impl R { + #[doc = "Bit 0 - Pin 0"] + #[inline(always)] + pub fn pin0(&self) -> PIN0_R { + PIN0_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Pin 1"] + #[inline(always)] + pub fn pin1(&self) -> PIN1_R { + PIN1_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Pin 2"] + #[inline(always)] + pub fn pin2(&self) -> PIN2_R { + PIN2_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Pin 3"] + #[inline(always)] + pub fn pin3(&self) -> PIN3_R { + PIN3_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Pin 4"] + #[inline(always)] + pub fn pin4(&self) -> PIN4_R { + PIN4_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Pin 5"] + #[inline(always)] + pub fn pin5(&self) -> PIN5_R { + PIN5_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Pin 6"] + #[inline(always)] + pub fn pin6(&self) -> PIN6_R { + PIN6_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Pin 7"] + #[inline(always)] + pub fn pin7(&self) -> PIN7_R { + PIN7_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Pin 8"] + #[inline(always)] + pub fn pin8(&self) -> PIN8_R { + PIN8_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Pin 9"] + #[inline(always)] + pub fn pin9(&self) -> PIN9_R { + PIN9_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Pin 10"] + #[inline(always)] + pub fn pin10(&self) -> PIN10_R { + PIN10_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Pin 11"] + #[inline(always)] + pub fn pin11(&self) -> PIN11_R { + PIN11_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Pin 12"] + #[inline(always)] + pub fn pin12(&self) -> PIN12_R { + PIN12_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Pin 13"] + #[inline(always)] + pub fn pin13(&self) -> PIN13_R { + PIN13_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Pin 14"] + #[inline(always)] + pub fn pin14(&self) -> PIN14_R { + PIN14_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Pin 15"] + #[inline(always)] + pub fn pin15(&self) -> PIN15_R { + PIN15_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - Pin 16"] + #[inline(always)] + pub fn pin16(&self) -> PIN16_R { + PIN16_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Pin 17"] + #[inline(always)] + pub fn pin17(&self) -> PIN17_R { + PIN17_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Pin 18"] + #[inline(always)] + pub fn pin18(&self) -> PIN18_R { + PIN18_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Pin 19"] + #[inline(always)] + pub fn pin19(&self) -> PIN19_R { + PIN19_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Pin 20"] + #[inline(always)] + pub fn pin20(&self) -> PIN20_R { + PIN20_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Pin 21"] + #[inline(always)] + pub fn pin21(&self) -> PIN21_R { + PIN21_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Pin 22"] + #[inline(always)] + pub fn pin22(&self) -> PIN22_R { + PIN22_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - Pin 23"] + #[inline(always)] + pub fn pin23(&self) -> PIN23_R { + PIN23_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - Pin 24"] + #[inline(always)] + pub fn pin24(&self) -> PIN24_R { + PIN24_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - Pin 25"] + #[inline(always)] + pub fn pin25(&self) -> PIN25_R { + PIN25_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - Pin 26"] + #[inline(always)] + pub fn pin26(&self) -> PIN26_R { + PIN26_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - Pin 27"] + #[inline(always)] + pub fn pin27(&self) -> PIN27_R { + PIN27_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - Pin 28"] + #[inline(always)] + pub fn pin28(&self) -> PIN28_R { + PIN28_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - Pin 29"] + #[inline(always)] + pub fn pin29(&self) -> PIN29_R { + PIN29_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Pin 30"] + #[inline(always)] + pub fn pin30(&self) -> PIN30_R { + PIN30_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Pin 31"] + #[inline(always)] + pub fn pin31(&self) -> PIN31_R { + PIN31_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Pin 0"] + #[inline(always)] + pub fn pin0(&mut self) -> PIN0_W<0> { + PIN0_W::new(self) + } + #[doc = "Bit 1 - Pin 1"] + #[inline(always)] + pub fn pin1(&mut self) -> PIN1_W<1> { + PIN1_W::new(self) + } + #[doc = "Bit 2 - Pin 2"] + #[inline(always)] + pub fn pin2(&mut self) -> PIN2_W<2> { + PIN2_W::new(self) + } + #[doc = "Bit 3 - Pin 3"] + #[inline(always)] + pub fn pin3(&mut self) -> PIN3_W<3> { + PIN3_W::new(self) + } + #[doc = "Bit 4 - Pin 4"] + #[inline(always)] + pub fn pin4(&mut self) -> PIN4_W<4> { + PIN4_W::new(self) + } + #[doc = "Bit 5 - Pin 5"] + #[inline(always)] + pub fn pin5(&mut self) -> PIN5_W<5> { + PIN5_W::new(self) + } + #[doc = "Bit 6 - Pin 6"] + #[inline(always)] + pub fn pin6(&mut self) -> PIN6_W<6> { + PIN6_W::new(self) + } + #[doc = "Bit 7 - Pin 7"] + #[inline(always)] + pub fn pin7(&mut self) -> PIN7_W<7> { + PIN7_W::new(self) + } + #[doc = "Bit 8 - Pin 8"] + #[inline(always)] + pub fn pin8(&mut self) -> PIN8_W<8> { + PIN8_W::new(self) + } + #[doc = "Bit 9 - Pin 9"] + #[inline(always)] + pub fn pin9(&mut self) -> PIN9_W<9> { + PIN9_W::new(self) + } + #[doc = "Bit 10 - Pin 10"] + #[inline(always)] + pub fn pin10(&mut self) -> PIN10_W<10> { + PIN10_W::new(self) + } + #[doc = "Bit 11 - Pin 11"] + #[inline(always)] + pub fn pin11(&mut self) -> PIN11_W<11> { + PIN11_W::new(self) + } + #[doc = "Bit 12 - Pin 12"] + #[inline(always)] + pub fn pin12(&mut self) -> PIN12_W<12> { + PIN12_W::new(self) + } + #[doc = "Bit 13 - Pin 13"] + #[inline(always)] + pub fn pin13(&mut self) -> PIN13_W<13> { + PIN13_W::new(self) + } + #[doc = "Bit 14 - Pin 14"] + #[inline(always)] + pub fn pin14(&mut self) -> PIN14_W<14> { + PIN14_W::new(self) + } + #[doc = "Bit 15 - Pin 15"] + #[inline(always)] + pub fn pin15(&mut self) -> PIN15_W<15> { + PIN15_W::new(self) + } + #[doc = "Bit 16 - Pin 16"] + #[inline(always)] + pub fn pin16(&mut self) -> PIN16_W<16> { + PIN16_W::new(self) + } + #[doc = "Bit 17 - Pin 17"] + #[inline(always)] + pub fn pin17(&mut self) -> PIN17_W<17> { + PIN17_W::new(self) + } + #[doc = "Bit 18 - Pin 18"] + #[inline(always)] + pub fn pin18(&mut self) -> PIN18_W<18> { + PIN18_W::new(self) + } + #[doc = "Bit 19 - Pin 19"] + #[inline(always)] + pub fn pin19(&mut self) -> PIN19_W<19> { + PIN19_W::new(self) + } + #[doc = "Bit 20 - Pin 20"] + #[inline(always)] + pub fn pin20(&mut self) -> PIN20_W<20> { + PIN20_W::new(self) + } + #[doc = "Bit 21 - Pin 21"] + #[inline(always)] + pub fn pin21(&mut self) -> PIN21_W<21> { + PIN21_W::new(self) + } + #[doc = "Bit 22 - Pin 22"] + #[inline(always)] + pub fn pin22(&mut self) -> PIN22_W<22> { + PIN22_W::new(self) + } + #[doc = "Bit 23 - Pin 23"] + #[inline(always)] + pub fn pin23(&mut self) -> PIN23_W<23> { + PIN23_W::new(self) + } + #[doc = "Bit 24 - Pin 24"] + #[inline(always)] + pub fn pin24(&mut self) -> PIN24_W<24> { + PIN24_W::new(self) + } + #[doc = "Bit 25 - Pin 25"] + #[inline(always)] + pub fn pin25(&mut self) -> PIN25_W<25> { + PIN25_W::new(self) + } + #[doc = "Bit 26 - Pin 26"] + #[inline(always)] + pub fn pin26(&mut self) -> PIN26_W<26> { + PIN26_W::new(self) + } + #[doc = "Bit 27 - Pin 27"] + #[inline(always)] + pub fn pin27(&mut self) -> PIN27_W<27> { + PIN27_W::new(self) + } + #[doc = "Bit 28 - Pin 28"] + #[inline(always)] + pub fn pin28(&mut self) -> PIN28_W<28> { + PIN28_W::new(self) + } + #[doc = "Bit 29 - Pin 29"] + #[inline(always)] + pub fn pin29(&mut self) -> PIN29_W<29> { + PIN29_W::new(self) + } + #[doc = "Bit 30 - Pin 30"] + #[inline(always)] + pub fn pin30(&mut self) -> PIN30_W<30> { + PIN30_W::new(self) + } + #[doc = "Bit 31 - Pin 31"] + #[inline(always)] + pub fn pin31(&mut self) -> PIN31_W<31> { + PIN31_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Clear individual bits in GPIO port\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [outclr](index.html) module"] +pub struct OUTCLR_SPEC; +impl crate::RegisterSpec for OUTCLR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [outclr::R](R) reader structure"] +impl crate::Readable for OUTCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [outclr::W](W) writer structure"] +impl crate::Writable for OUTCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets OUTCLR to value 0"] +impl crate::Resettable for OUTCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/p0_ns/outset.rs b/pacs/nrf9120-pac/src/p0_ns/outset.rs new file mode 100644 index 00000000..a58a0bdc --- /dev/null +++ b/pacs/nrf9120-pac/src/p0_ns/outset.rs @@ -0,0 +1,2210 @@ +#[doc = "Register `OUTSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `OUTSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PIN0` reader - Pin 0"] +pub type PIN0_R = crate::BitReader; +#[doc = "Pin 0\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN0_A { + #[doc = "0: Read: pin driver is low"] + LOW = 0, + #[doc = "1: Read: pin driver is high"] + HIGH = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN0_A) -> Self { + variant as u8 != 0 + } +} +impl PIN0_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN0_A { + match self.bits { + false => PIN0_A::LOW, + true => PIN0_A::HIGH, + } + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + *self == PIN0_A::LOW + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + *self == PIN0_A::HIGH + } +} +#[doc = "Pin 0\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN0_AW { + #[doc = "1: Write: writing a '1' sets the pin high; writing a '0' has no effect"] + SET = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN0_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PIN0` writer - Pin 0"] +pub type PIN0_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, OUTSET_SPEC, PIN0_AW, O>; +impl<'a, const O: u8> PIN0_W<'a, O> { + #[doc = "Write: writing a '1' sets the pin high; writing a '0' has no effect"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(PIN0_AW::SET) + } +} +#[doc = "Field `PIN1` reader - Pin 1"] +pub type PIN1_R = crate::BitReader; +#[doc = "Pin 1\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN1_A { + #[doc = "0: Read: pin driver is low"] + LOW = 0, + #[doc = "1: Read: pin driver is high"] + HIGH = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN1_A) -> Self { + variant as u8 != 0 + } +} +impl PIN1_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN1_A { + match self.bits { + false => PIN1_A::LOW, + true => PIN1_A::HIGH, + } + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + *self == PIN1_A::LOW + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + *self == PIN1_A::HIGH + } +} +#[doc = "Pin 1\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN1_AW { + #[doc = "1: Write: writing a '1' sets the pin high; writing a '0' has no effect"] + SET = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN1_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PIN1` writer - Pin 1"] +pub type PIN1_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, OUTSET_SPEC, PIN1_AW, O>; +impl<'a, const O: u8> PIN1_W<'a, O> { + #[doc = "Write: writing a '1' sets the pin high; writing a '0' has no effect"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(PIN1_AW::SET) + } +} +#[doc = "Field `PIN2` reader - Pin 2"] +pub type PIN2_R = crate::BitReader; +#[doc = "Pin 2\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN2_A { + #[doc = "0: Read: pin driver is low"] + LOW = 0, + #[doc = "1: Read: pin driver is high"] + HIGH = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN2_A) -> Self { + variant as u8 != 0 + } +} +impl PIN2_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN2_A { + match self.bits { + false => PIN2_A::LOW, + true => PIN2_A::HIGH, + } + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + *self == PIN2_A::LOW + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + *self == PIN2_A::HIGH + } +} +#[doc = "Pin 2\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN2_AW { + #[doc = "1: Write: writing a '1' sets the pin high; writing a '0' has no effect"] + SET = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN2_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PIN2` writer - Pin 2"] +pub type PIN2_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, OUTSET_SPEC, PIN2_AW, O>; +impl<'a, const O: u8> PIN2_W<'a, O> { + #[doc = "Write: writing a '1' sets the pin high; writing a '0' has no effect"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(PIN2_AW::SET) + } +} +#[doc = "Field `PIN3` reader - Pin 3"] +pub type PIN3_R = crate::BitReader; +#[doc = "Pin 3\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN3_A { + #[doc = "0: Read: pin driver is low"] + LOW = 0, + #[doc = "1: Read: pin driver is high"] + HIGH = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN3_A) -> Self { + variant as u8 != 0 + } +} +impl PIN3_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN3_A { + match self.bits { + false => PIN3_A::LOW, + true => PIN3_A::HIGH, + } + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + *self == PIN3_A::LOW + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + *self == PIN3_A::HIGH + } +} +#[doc = "Pin 3\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN3_AW { + #[doc = "1: Write: writing a '1' sets the pin high; writing a '0' has no effect"] + SET = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN3_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PIN3` writer - Pin 3"] +pub type PIN3_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, OUTSET_SPEC, PIN3_AW, O>; +impl<'a, const O: u8> PIN3_W<'a, O> { + #[doc = "Write: writing a '1' sets the pin high; writing a '0' has no effect"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(PIN3_AW::SET) + } +} +#[doc = "Field `PIN4` reader - Pin 4"] +pub type PIN4_R = crate::BitReader; +#[doc = "Pin 4\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN4_A { + #[doc = "0: Read: pin driver is low"] + LOW = 0, + #[doc = "1: Read: pin driver is high"] + HIGH = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN4_A) -> Self { + variant as u8 != 0 + } +} +impl PIN4_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN4_A { + match self.bits { + false => PIN4_A::LOW, + true => PIN4_A::HIGH, + } + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + *self == PIN4_A::LOW + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + *self == PIN4_A::HIGH + } +} +#[doc = "Pin 4\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN4_AW { + #[doc = "1: Write: writing a '1' sets the pin high; writing a '0' has no effect"] + SET = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN4_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PIN4` writer - Pin 4"] +pub type PIN4_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, OUTSET_SPEC, PIN4_AW, O>; +impl<'a, const O: u8> PIN4_W<'a, O> { + #[doc = "Write: writing a '1' sets the pin high; writing a '0' has no effect"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(PIN4_AW::SET) + } +} +#[doc = "Field `PIN5` reader - Pin 5"] +pub type PIN5_R = crate::BitReader; +#[doc = "Pin 5\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN5_A { + #[doc = "0: Read: pin driver is low"] + LOW = 0, + #[doc = "1: Read: pin driver is high"] + HIGH = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN5_A) -> Self { + variant as u8 != 0 + } +} +impl PIN5_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN5_A { + match self.bits { + false => PIN5_A::LOW, + true => PIN5_A::HIGH, + } + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + *self == PIN5_A::LOW + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + *self == PIN5_A::HIGH + } +} +#[doc = "Pin 5\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN5_AW { + #[doc = "1: Write: writing a '1' sets the pin high; writing a '0' has no effect"] + SET = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN5_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PIN5` writer - Pin 5"] +pub type PIN5_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, OUTSET_SPEC, PIN5_AW, O>; +impl<'a, const O: u8> PIN5_W<'a, O> { + #[doc = "Write: writing a '1' sets the pin high; writing a '0' has no effect"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(PIN5_AW::SET) + } +} +#[doc = "Field `PIN6` reader - Pin 6"] +pub type PIN6_R = crate::BitReader; +#[doc = "Pin 6\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN6_A { + #[doc = "0: Read: pin driver is low"] + LOW = 0, + #[doc = "1: Read: pin driver is high"] + HIGH = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN6_A) -> Self { + variant as u8 != 0 + } +} +impl PIN6_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN6_A { + match self.bits { + false => PIN6_A::LOW, + true => PIN6_A::HIGH, + } + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + *self == PIN6_A::LOW + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + *self == PIN6_A::HIGH + } +} +#[doc = "Pin 6\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN6_AW { + #[doc = "1: Write: writing a '1' sets the pin high; writing a '0' has no effect"] + SET = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN6_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PIN6` writer - Pin 6"] +pub type PIN6_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, OUTSET_SPEC, PIN6_AW, O>; +impl<'a, const O: u8> PIN6_W<'a, O> { + #[doc = "Write: writing a '1' sets the pin high; writing a '0' has no effect"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(PIN6_AW::SET) + } +} +#[doc = "Field `PIN7` reader - Pin 7"] +pub type PIN7_R = crate::BitReader; +#[doc = "Pin 7\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN7_A { + #[doc = "0: Read: pin driver is low"] + LOW = 0, + #[doc = "1: Read: pin driver is high"] + HIGH = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN7_A) -> Self { + variant as u8 != 0 + } +} +impl PIN7_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN7_A { + match self.bits { + false => PIN7_A::LOW, + true => PIN7_A::HIGH, + } + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + *self == PIN7_A::LOW + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + *self == PIN7_A::HIGH + } +} +#[doc = "Pin 7\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN7_AW { + #[doc = "1: Write: writing a '1' sets the pin high; writing a '0' has no effect"] + SET = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN7_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PIN7` writer - Pin 7"] +pub type PIN7_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, OUTSET_SPEC, PIN7_AW, O>; +impl<'a, const O: u8> PIN7_W<'a, O> { + #[doc = "Write: writing a '1' sets the pin high; writing a '0' has no effect"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(PIN7_AW::SET) + } +} +#[doc = "Field `PIN8` reader - Pin 8"] +pub type PIN8_R = crate::BitReader; +#[doc = "Pin 8\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN8_A { + #[doc = "0: Read: pin driver is low"] + LOW = 0, + #[doc = "1: Read: pin driver is high"] + HIGH = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN8_A) -> Self { + variant as u8 != 0 + } +} +impl PIN8_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN8_A { + match self.bits { + false => PIN8_A::LOW, + true => PIN8_A::HIGH, + } + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + *self == PIN8_A::LOW + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + *self == PIN8_A::HIGH + } +} +#[doc = "Pin 8\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN8_AW { + #[doc = "1: Write: writing a '1' sets the pin high; writing a '0' has no effect"] + SET = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN8_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PIN8` writer - Pin 8"] +pub type PIN8_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, OUTSET_SPEC, PIN8_AW, O>; +impl<'a, const O: u8> PIN8_W<'a, O> { + #[doc = "Write: writing a '1' sets the pin high; writing a '0' has no effect"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(PIN8_AW::SET) + } +} +#[doc = "Field `PIN9` reader - Pin 9"] +pub type PIN9_R = crate::BitReader; +#[doc = "Pin 9\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN9_A { + #[doc = "0: Read: pin driver is low"] + LOW = 0, + #[doc = "1: Read: pin driver is high"] + HIGH = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN9_A) -> Self { + variant as u8 != 0 + } +} +impl PIN9_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN9_A { + match self.bits { + false => PIN9_A::LOW, + true => PIN9_A::HIGH, + } + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + *self == PIN9_A::LOW + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + *self == PIN9_A::HIGH + } +} +#[doc = "Pin 9\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN9_AW { + #[doc = "1: Write: writing a '1' sets the pin high; writing a '0' has no effect"] + SET = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN9_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PIN9` writer - Pin 9"] +pub type PIN9_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, OUTSET_SPEC, PIN9_AW, O>; +impl<'a, const O: u8> PIN9_W<'a, O> { + #[doc = "Write: writing a '1' sets the pin high; writing a '0' has no effect"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(PIN9_AW::SET) + } +} +#[doc = "Field `PIN10` reader - Pin 10"] +pub type PIN10_R = crate::BitReader; +#[doc = "Pin 10\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN10_A { + #[doc = "0: Read: pin driver is low"] + LOW = 0, + #[doc = "1: Read: pin driver is high"] + HIGH = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN10_A) -> Self { + variant as u8 != 0 + } +} +impl PIN10_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN10_A { + match self.bits { + false => PIN10_A::LOW, + true => PIN10_A::HIGH, + } + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + *self == PIN10_A::LOW + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + *self == PIN10_A::HIGH + } +} +#[doc = "Pin 10\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN10_AW { + #[doc = "1: Write: writing a '1' sets the pin high; writing a '0' has no effect"] + SET = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN10_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PIN10` writer - Pin 10"] +pub type PIN10_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, OUTSET_SPEC, PIN10_AW, O>; +impl<'a, const O: u8> PIN10_W<'a, O> { + #[doc = "Write: writing a '1' sets the pin high; writing a '0' has no effect"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(PIN10_AW::SET) + } +} +#[doc = "Field `PIN11` reader - Pin 11"] +pub type PIN11_R = crate::BitReader; +#[doc = "Pin 11\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN11_A { + #[doc = "0: Read: pin driver is low"] + LOW = 0, + #[doc = "1: Read: pin driver is high"] + HIGH = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN11_A) -> Self { + variant as u8 != 0 + } +} +impl PIN11_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN11_A { + match self.bits { + false => PIN11_A::LOW, + true => PIN11_A::HIGH, + } + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + *self == PIN11_A::LOW + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + *self == PIN11_A::HIGH + } +} +#[doc = "Pin 11\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN11_AW { + #[doc = "1: Write: writing a '1' sets the pin high; writing a '0' has no effect"] + SET = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN11_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PIN11` writer - Pin 11"] +pub type PIN11_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, OUTSET_SPEC, PIN11_AW, O>; +impl<'a, const O: u8> PIN11_W<'a, O> { + #[doc = "Write: writing a '1' sets the pin high; writing a '0' has no effect"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(PIN11_AW::SET) + } +} +#[doc = "Field `PIN12` reader - Pin 12"] +pub type PIN12_R = crate::BitReader; +#[doc = "Pin 12\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN12_A { + #[doc = "0: Read: pin driver is low"] + LOW = 0, + #[doc = "1: Read: pin driver is high"] + HIGH = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN12_A) -> Self { + variant as u8 != 0 + } +} +impl PIN12_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN12_A { + match self.bits { + false => PIN12_A::LOW, + true => PIN12_A::HIGH, + } + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + *self == PIN12_A::LOW + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + *self == PIN12_A::HIGH + } +} +#[doc = "Pin 12\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN12_AW { + #[doc = "1: Write: writing a '1' sets the pin high; writing a '0' has no effect"] + SET = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN12_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PIN12` writer - Pin 12"] +pub type PIN12_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, OUTSET_SPEC, PIN12_AW, O>; +impl<'a, const O: u8> PIN12_W<'a, O> { + #[doc = "Write: writing a '1' sets the pin high; writing a '0' has no effect"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(PIN12_AW::SET) + } +} +#[doc = "Field `PIN13` reader - Pin 13"] +pub type PIN13_R = crate::BitReader; +#[doc = "Pin 13\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN13_A { + #[doc = "0: Read: pin driver is low"] + LOW = 0, + #[doc = "1: Read: pin driver is high"] + HIGH = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN13_A) -> Self { + variant as u8 != 0 + } +} +impl PIN13_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN13_A { + match self.bits { + false => PIN13_A::LOW, + true => PIN13_A::HIGH, + } + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + *self == PIN13_A::LOW + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + *self == PIN13_A::HIGH + } +} +#[doc = "Pin 13\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN13_AW { + #[doc = "1: Write: writing a '1' sets the pin high; writing a '0' has no effect"] + SET = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN13_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PIN13` writer - Pin 13"] +pub type PIN13_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, OUTSET_SPEC, PIN13_AW, O>; +impl<'a, const O: u8> PIN13_W<'a, O> { + #[doc = "Write: writing a '1' sets the pin high; writing a '0' has no effect"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(PIN13_AW::SET) + } +} +#[doc = "Field `PIN14` reader - Pin 14"] +pub type PIN14_R = crate::BitReader; +#[doc = "Pin 14\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN14_A { + #[doc = "0: Read: pin driver is low"] + LOW = 0, + #[doc = "1: Read: pin driver is high"] + HIGH = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN14_A) -> Self { + variant as u8 != 0 + } +} +impl PIN14_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN14_A { + match self.bits { + false => PIN14_A::LOW, + true => PIN14_A::HIGH, + } + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + *self == PIN14_A::LOW + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + *self == PIN14_A::HIGH + } +} +#[doc = "Pin 14\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN14_AW { + #[doc = "1: Write: writing a '1' sets the pin high; writing a '0' has no effect"] + SET = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN14_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PIN14` writer - Pin 14"] +pub type PIN14_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, OUTSET_SPEC, PIN14_AW, O>; +impl<'a, const O: u8> PIN14_W<'a, O> { + #[doc = "Write: writing a '1' sets the pin high; writing a '0' has no effect"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(PIN14_AW::SET) + } +} +#[doc = "Field `PIN15` reader - Pin 15"] +pub type PIN15_R = crate::BitReader; +#[doc = "Pin 15\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN15_A { + #[doc = "0: Read: pin driver is low"] + LOW = 0, + #[doc = "1: Read: pin driver is high"] + HIGH = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN15_A) -> Self { + variant as u8 != 0 + } +} +impl PIN15_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN15_A { + match self.bits { + false => PIN15_A::LOW, + true => PIN15_A::HIGH, + } + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + *self == PIN15_A::LOW + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + *self == PIN15_A::HIGH + } +} +#[doc = "Pin 15\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN15_AW { + #[doc = "1: Write: writing a '1' sets the pin high; writing a '0' has no effect"] + SET = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN15_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PIN15` writer - Pin 15"] +pub type PIN15_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, OUTSET_SPEC, PIN15_AW, O>; +impl<'a, const O: u8> PIN15_W<'a, O> { + #[doc = "Write: writing a '1' sets the pin high; writing a '0' has no effect"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(PIN15_AW::SET) + } +} +#[doc = "Field `PIN16` reader - Pin 16"] +pub type PIN16_R = crate::BitReader; +#[doc = "Pin 16\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN16_A { + #[doc = "0: Read: pin driver is low"] + LOW = 0, + #[doc = "1: Read: pin driver is high"] + HIGH = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN16_A) -> Self { + variant as u8 != 0 + } +} +impl PIN16_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN16_A { + match self.bits { + false => PIN16_A::LOW, + true => PIN16_A::HIGH, + } + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + *self == PIN16_A::LOW + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + *self == PIN16_A::HIGH + } +} +#[doc = "Pin 16\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN16_AW { + #[doc = "1: Write: writing a '1' sets the pin high; writing a '0' has no effect"] + SET = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN16_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PIN16` writer - Pin 16"] +pub type PIN16_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, OUTSET_SPEC, PIN16_AW, O>; +impl<'a, const O: u8> PIN16_W<'a, O> { + #[doc = "Write: writing a '1' sets the pin high; writing a '0' has no effect"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(PIN16_AW::SET) + } +} +#[doc = "Field `PIN17` reader - Pin 17"] +pub type PIN17_R = crate::BitReader; +#[doc = "Pin 17\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN17_A { + #[doc = "0: Read: pin driver is low"] + LOW = 0, + #[doc = "1: Read: pin driver is high"] + HIGH = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN17_A) -> Self { + variant as u8 != 0 + } +} +impl PIN17_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN17_A { + match self.bits { + false => PIN17_A::LOW, + true => PIN17_A::HIGH, + } + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + *self == PIN17_A::LOW + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + *self == PIN17_A::HIGH + } +} +#[doc = "Pin 17\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN17_AW { + #[doc = "1: Write: writing a '1' sets the pin high; writing a '0' has no effect"] + SET = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN17_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PIN17` writer - Pin 17"] +pub type PIN17_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, OUTSET_SPEC, PIN17_AW, O>; +impl<'a, const O: u8> PIN17_W<'a, O> { + #[doc = "Write: writing a '1' sets the pin high; writing a '0' has no effect"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(PIN17_AW::SET) + } +} +#[doc = "Field `PIN18` reader - Pin 18"] +pub type PIN18_R = crate::BitReader; +#[doc = "Pin 18\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN18_A { + #[doc = "0: Read: pin driver is low"] + LOW = 0, + #[doc = "1: Read: pin driver is high"] + HIGH = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN18_A) -> Self { + variant as u8 != 0 + } +} +impl PIN18_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN18_A { + match self.bits { + false => PIN18_A::LOW, + true => PIN18_A::HIGH, + } + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + *self == PIN18_A::LOW + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + *self == PIN18_A::HIGH + } +} +#[doc = "Pin 18\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN18_AW { + #[doc = "1: Write: writing a '1' sets the pin high; writing a '0' has no effect"] + SET = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN18_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PIN18` writer - Pin 18"] +pub type PIN18_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, OUTSET_SPEC, PIN18_AW, O>; +impl<'a, const O: u8> PIN18_W<'a, O> { + #[doc = "Write: writing a '1' sets the pin high; writing a '0' has no effect"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(PIN18_AW::SET) + } +} +#[doc = "Field `PIN19` reader - Pin 19"] +pub type PIN19_R = crate::BitReader; +#[doc = "Pin 19\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN19_A { + #[doc = "0: Read: pin driver is low"] + LOW = 0, + #[doc = "1: Read: pin driver is high"] + HIGH = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN19_A) -> Self { + variant as u8 != 0 + } +} +impl PIN19_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN19_A { + match self.bits { + false => PIN19_A::LOW, + true => PIN19_A::HIGH, + } + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + *self == PIN19_A::LOW + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + *self == PIN19_A::HIGH + } +} +#[doc = "Pin 19\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN19_AW { + #[doc = "1: Write: writing a '1' sets the pin high; writing a '0' has no effect"] + SET = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN19_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PIN19` writer - Pin 19"] +pub type PIN19_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, OUTSET_SPEC, PIN19_AW, O>; +impl<'a, const O: u8> PIN19_W<'a, O> { + #[doc = "Write: writing a '1' sets the pin high; writing a '0' has no effect"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(PIN19_AW::SET) + } +} +#[doc = "Field `PIN20` reader - Pin 20"] +pub type PIN20_R = crate::BitReader; +#[doc = "Pin 20\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN20_A { + #[doc = "0: Read: pin driver is low"] + LOW = 0, + #[doc = "1: Read: pin driver is high"] + HIGH = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN20_A) -> Self { + variant as u8 != 0 + } +} +impl PIN20_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN20_A { + match self.bits { + false => PIN20_A::LOW, + true => PIN20_A::HIGH, + } + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + *self == PIN20_A::LOW + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + *self == PIN20_A::HIGH + } +} +#[doc = "Pin 20\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN20_AW { + #[doc = "1: Write: writing a '1' sets the pin high; writing a '0' has no effect"] + SET = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN20_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PIN20` writer - Pin 20"] +pub type PIN20_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, OUTSET_SPEC, PIN20_AW, O>; +impl<'a, const O: u8> PIN20_W<'a, O> { + #[doc = "Write: writing a '1' sets the pin high; writing a '0' has no effect"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(PIN20_AW::SET) + } +} +#[doc = "Field `PIN21` reader - Pin 21"] +pub type PIN21_R = crate::BitReader; +#[doc = "Pin 21\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN21_A { + #[doc = "0: Read: pin driver is low"] + LOW = 0, + #[doc = "1: Read: pin driver is high"] + HIGH = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN21_A) -> Self { + variant as u8 != 0 + } +} +impl PIN21_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN21_A { + match self.bits { + false => PIN21_A::LOW, + true => PIN21_A::HIGH, + } + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + *self == PIN21_A::LOW + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + *self == PIN21_A::HIGH + } +} +#[doc = "Pin 21\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN21_AW { + #[doc = "1: Write: writing a '1' sets the pin high; writing a '0' has no effect"] + SET = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN21_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PIN21` writer - Pin 21"] +pub type PIN21_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, OUTSET_SPEC, PIN21_AW, O>; +impl<'a, const O: u8> PIN21_W<'a, O> { + #[doc = "Write: writing a '1' sets the pin high; writing a '0' has no effect"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(PIN21_AW::SET) + } +} +#[doc = "Field `PIN22` reader - Pin 22"] +pub type PIN22_R = crate::BitReader; +#[doc = "Pin 22\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN22_A { + #[doc = "0: Read: pin driver is low"] + LOW = 0, + #[doc = "1: Read: pin driver is high"] + HIGH = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN22_A) -> Self { + variant as u8 != 0 + } +} +impl PIN22_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN22_A { + match self.bits { + false => PIN22_A::LOW, + true => PIN22_A::HIGH, + } + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + *self == PIN22_A::LOW + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + *self == PIN22_A::HIGH + } +} +#[doc = "Pin 22\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN22_AW { + #[doc = "1: Write: writing a '1' sets the pin high; writing a '0' has no effect"] + SET = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN22_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PIN22` writer - Pin 22"] +pub type PIN22_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, OUTSET_SPEC, PIN22_AW, O>; +impl<'a, const O: u8> PIN22_W<'a, O> { + #[doc = "Write: writing a '1' sets the pin high; writing a '0' has no effect"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(PIN22_AW::SET) + } +} +#[doc = "Field `PIN23` reader - Pin 23"] +pub type PIN23_R = crate::BitReader; +#[doc = "Pin 23\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN23_A { + #[doc = "0: Read: pin driver is low"] + LOW = 0, + #[doc = "1: Read: pin driver is high"] + HIGH = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN23_A) -> Self { + variant as u8 != 0 + } +} +impl PIN23_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN23_A { + match self.bits { + false => PIN23_A::LOW, + true => PIN23_A::HIGH, + } + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + *self == PIN23_A::LOW + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + *self == PIN23_A::HIGH + } +} +#[doc = "Pin 23\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN23_AW { + #[doc = "1: Write: writing a '1' sets the pin high; writing a '0' has no effect"] + SET = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN23_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PIN23` writer - Pin 23"] +pub type PIN23_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, OUTSET_SPEC, PIN23_AW, O>; +impl<'a, const O: u8> PIN23_W<'a, O> { + #[doc = "Write: writing a '1' sets the pin high; writing a '0' has no effect"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(PIN23_AW::SET) + } +} +#[doc = "Field `PIN24` reader - Pin 24"] +pub type PIN24_R = crate::BitReader; +#[doc = "Pin 24\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN24_A { + #[doc = "0: Read: pin driver is low"] + LOW = 0, + #[doc = "1: Read: pin driver is high"] + HIGH = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN24_A) -> Self { + variant as u8 != 0 + } +} +impl PIN24_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN24_A { + match self.bits { + false => PIN24_A::LOW, + true => PIN24_A::HIGH, + } + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + *self == PIN24_A::LOW + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + *self == PIN24_A::HIGH + } +} +#[doc = "Pin 24\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN24_AW { + #[doc = "1: Write: writing a '1' sets the pin high; writing a '0' has no effect"] + SET = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN24_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PIN24` writer - Pin 24"] +pub type PIN24_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, OUTSET_SPEC, PIN24_AW, O>; +impl<'a, const O: u8> PIN24_W<'a, O> { + #[doc = "Write: writing a '1' sets the pin high; writing a '0' has no effect"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(PIN24_AW::SET) + } +} +#[doc = "Field `PIN25` reader - Pin 25"] +pub type PIN25_R = crate::BitReader; +#[doc = "Pin 25\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN25_A { + #[doc = "0: Read: pin driver is low"] + LOW = 0, + #[doc = "1: Read: pin driver is high"] + HIGH = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN25_A) -> Self { + variant as u8 != 0 + } +} +impl PIN25_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN25_A { + match self.bits { + false => PIN25_A::LOW, + true => PIN25_A::HIGH, + } + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + *self == PIN25_A::LOW + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + *self == PIN25_A::HIGH + } +} +#[doc = "Pin 25\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN25_AW { + #[doc = "1: Write: writing a '1' sets the pin high; writing a '0' has no effect"] + SET = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN25_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PIN25` writer - Pin 25"] +pub type PIN25_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, OUTSET_SPEC, PIN25_AW, O>; +impl<'a, const O: u8> PIN25_W<'a, O> { + #[doc = "Write: writing a '1' sets the pin high; writing a '0' has no effect"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(PIN25_AW::SET) + } +} +#[doc = "Field `PIN26` reader - Pin 26"] +pub type PIN26_R = crate::BitReader; +#[doc = "Pin 26\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN26_A { + #[doc = "0: Read: pin driver is low"] + LOW = 0, + #[doc = "1: Read: pin driver is high"] + HIGH = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN26_A) -> Self { + variant as u8 != 0 + } +} +impl PIN26_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN26_A { + match self.bits { + false => PIN26_A::LOW, + true => PIN26_A::HIGH, + } + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + *self == PIN26_A::LOW + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + *self == PIN26_A::HIGH + } +} +#[doc = "Pin 26\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN26_AW { + #[doc = "1: Write: writing a '1' sets the pin high; writing a '0' has no effect"] + SET = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN26_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PIN26` writer - Pin 26"] +pub type PIN26_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, OUTSET_SPEC, PIN26_AW, O>; +impl<'a, const O: u8> PIN26_W<'a, O> { + #[doc = "Write: writing a '1' sets the pin high; writing a '0' has no effect"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(PIN26_AW::SET) + } +} +#[doc = "Field `PIN27` reader - Pin 27"] +pub type PIN27_R = crate::BitReader; +#[doc = "Pin 27\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN27_A { + #[doc = "0: Read: pin driver is low"] + LOW = 0, + #[doc = "1: Read: pin driver is high"] + HIGH = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN27_A) -> Self { + variant as u8 != 0 + } +} +impl PIN27_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN27_A { + match self.bits { + false => PIN27_A::LOW, + true => PIN27_A::HIGH, + } + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + *self == PIN27_A::LOW + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + *self == PIN27_A::HIGH + } +} +#[doc = "Pin 27\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN27_AW { + #[doc = "1: Write: writing a '1' sets the pin high; writing a '0' has no effect"] + SET = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN27_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PIN27` writer - Pin 27"] +pub type PIN27_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, OUTSET_SPEC, PIN27_AW, O>; +impl<'a, const O: u8> PIN27_W<'a, O> { + #[doc = "Write: writing a '1' sets the pin high; writing a '0' has no effect"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(PIN27_AW::SET) + } +} +#[doc = "Field `PIN28` reader - Pin 28"] +pub type PIN28_R = crate::BitReader; +#[doc = "Pin 28\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN28_A { + #[doc = "0: Read: pin driver is low"] + LOW = 0, + #[doc = "1: Read: pin driver is high"] + HIGH = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN28_A) -> Self { + variant as u8 != 0 + } +} +impl PIN28_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN28_A { + match self.bits { + false => PIN28_A::LOW, + true => PIN28_A::HIGH, + } + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + *self == PIN28_A::LOW + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + *self == PIN28_A::HIGH + } +} +#[doc = "Pin 28\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN28_AW { + #[doc = "1: Write: writing a '1' sets the pin high; writing a '0' has no effect"] + SET = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN28_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PIN28` writer - Pin 28"] +pub type PIN28_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, OUTSET_SPEC, PIN28_AW, O>; +impl<'a, const O: u8> PIN28_W<'a, O> { + #[doc = "Write: writing a '1' sets the pin high; writing a '0' has no effect"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(PIN28_AW::SET) + } +} +#[doc = "Field `PIN29` reader - Pin 29"] +pub type PIN29_R = crate::BitReader; +#[doc = "Pin 29\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN29_A { + #[doc = "0: Read: pin driver is low"] + LOW = 0, + #[doc = "1: Read: pin driver is high"] + HIGH = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN29_A) -> Self { + variant as u8 != 0 + } +} +impl PIN29_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN29_A { + match self.bits { + false => PIN29_A::LOW, + true => PIN29_A::HIGH, + } + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + *self == PIN29_A::LOW + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + *self == PIN29_A::HIGH + } +} +#[doc = "Pin 29\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN29_AW { + #[doc = "1: Write: writing a '1' sets the pin high; writing a '0' has no effect"] + SET = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN29_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PIN29` writer - Pin 29"] +pub type PIN29_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, OUTSET_SPEC, PIN29_AW, O>; +impl<'a, const O: u8> PIN29_W<'a, O> { + #[doc = "Write: writing a '1' sets the pin high; writing a '0' has no effect"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(PIN29_AW::SET) + } +} +#[doc = "Field `PIN30` reader - Pin 30"] +pub type PIN30_R = crate::BitReader; +#[doc = "Pin 30\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN30_A { + #[doc = "0: Read: pin driver is low"] + LOW = 0, + #[doc = "1: Read: pin driver is high"] + HIGH = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN30_A) -> Self { + variant as u8 != 0 + } +} +impl PIN30_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN30_A { + match self.bits { + false => PIN30_A::LOW, + true => PIN30_A::HIGH, + } + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + *self == PIN30_A::LOW + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + *self == PIN30_A::HIGH + } +} +#[doc = "Pin 30\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN30_AW { + #[doc = "1: Write: writing a '1' sets the pin high; writing a '0' has no effect"] + SET = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN30_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PIN30` writer - Pin 30"] +pub type PIN30_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, OUTSET_SPEC, PIN30_AW, O>; +impl<'a, const O: u8> PIN30_W<'a, O> { + #[doc = "Write: writing a '1' sets the pin high; writing a '0' has no effect"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(PIN30_AW::SET) + } +} +#[doc = "Field `PIN31` reader - Pin 31"] +pub type PIN31_R = crate::BitReader; +#[doc = "Pin 31\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN31_A { + #[doc = "0: Read: pin driver is low"] + LOW = 0, + #[doc = "1: Read: pin driver is high"] + HIGH = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN31_A) -> Self { + variant as u8 != 0 + } +} +impl PIN31_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN31_A { + match self.bits { + false => PIN31_A::LOW, + true => PIN31_A::HIGH, + } + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + *self == PIN31_A::LOW + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + *self == PIN31_A::HIGH + } +} +#[doc = "Pin 31\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN31_AW { + #[doc = "1: Write: writing a '1' sets the pin high; writing a '0' has no effect"] + SET = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN31_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PIN31` writer - Pin 31"] +pub type PIN31_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, OUTSET_SPEC, PIN31_AW, O>; +impl<'a, const O: u8> PIN31_W<'a, O> { + #[doc = "Write: writing a '1' sets the pin high; writing a '0' has no effect"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(PIN31_AW::SET) + } +} +impl R { + #[doc = "Bit 0 - Pin 0"] + #[inline(always)] + pub fn pin0(&self) -> PIN0_R { + PIN0_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Pin 1"] + #[inline(always)] + pub fn pin1(&self) -> PIN1_R { + PIN1_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Pin 2"] + #[inline(always)] + pub fn pin2(&self) -> PIN2_R { + PIN2_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Pin 3"] + #[inline(always)] + pub fn pin3(&self) -> PIN3_R { + PIN3_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Pin 4"] + #[inline(always)] + pub fn pin4(&self) -> PIN4_R { + PIN4_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Pin 5"] + #[inline(always)] + pub fn pin5(&self) -> PIN5_R { + PIN5_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Pin 6"] + #[inline(always)] + pub fn pin6(&self) -> PIN6_R { + PIN6_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Pin 7"] + #[inline(always)] + pub fn pin7(&self) -> PIN7_R { + PIN7_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Pin 8"] + #[inline(always)] + pub fn pin8(&self) -> PIN8_R { + PIN8_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Pin 9"] + #[inline(always)] + pub fn pin9(&self) -> PIN9_R { + PIN9_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Pin 10"] + #[inline(always)] + pub fn pin10(&self) -> PIN10_R { + PIN10_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Pin 11"] + #[inline(always)] + pub fn pin11(&self) -> PIN11_R { + PIN11_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Pin 12"] + #[inline(always)] + pub fn pin12(&self) -> PIN12_R { + PIN12_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Pin 13"] + #[inline(always)] + pub fn pin13(&self) -> PIN13_R { + PIN13_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Pin 14"] + #[inline(always)] + pub fn pin14(&self) -> PIN14_R { + PIN14_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Pin 15"] + #[inline(always)] + pub fn pin15(&self) -> PIN15_R { + PIN15_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - Pin 16"] + #[inline(always)] + pub fn pin16(&self) -> PIN16_R { + PIN16_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Pin 17"] + #[inline(always)] + pub fn pin17(&self) -> PIN17_R { + PIN17_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Pin 18"] + #[inline(always)] + pub fn pin18(&self) -> PIN18_R { + PIN18_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Pin 19"] + #[inline(always)] + pub fn pin19(&self) -> PIN19_R { + PIN19_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Pin 20"] + #[inline(always)] + pub fn pin20(&self) -> PIN20_R { + PIN20_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Pin 21"] + #[inline(always)] + pub fn pin21(&self) -> PIN21_R { + PIN21_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Pin 22"] + #[inline(always)] + pub fn pin22(&self) -> PIN22_R { + PIN22_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - Pin 23"] + #[inline(always)] + pub fn pin23(&self) -> PIN23_R { + PIN23_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - Pin 24"] + #[inline(always)] + pub fn pin24(&self) -> PIN24_R { + PIN24_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - Pin 25"] + #[inline(always)] + pub fn pin25(&self) -> PIN25_R { + PIN25_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - Pin 26"] + #[inline(always)] + pub fn pin26(&self) -> PIN26_R { + PIN26_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - Pin 27"] + #[inline(always)] + pub fn pin27(&self) -> PIN27_R { + PIN27_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - Pin 28"] + #[inline(always)] + pub fn pin28(&self) -> PIN28_R { + PIN28_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - Pin 29"] + #[inline(always)] + pub fn pin29(&self) -> PIN29_R { + PIN29_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Pin 30"] + #[inline(always)] + pub fn pin30(&self) -> PIN30_R { + PIN30_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Pin 31"] + #[inline(always)] + pub fn pin31(&self) -> PIN31_R { + PIN31_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Pin 0"] + #[inline(always)] + pub fn pin0(&mut self) -> PIN0_W<0> { + PIN0_W::new(self) + } + #[doc = "Bit 1 - Pin 1"] + #[inline(always)] + pub fn pin1(&mut self) -> PIN1_W<1> { + PIN1_W::new(self) + } + #[doc = "Bit 2 - Pin 2"] + #[inline(always)] + pub fn pin2(&mut self) -> PIN2_W<2> { + PIN2_W::new(self) + } + #[doc = "Bit 3 - Pin 3"] + #[inline(always)] + pub fn pin3(&mut self) -> PIN3_W<3> { + PIN3_W::new(self) + } + #[doc = "Bit 4 - Pin 4"] + #[inline(always)] + pub fn pin4(&mut self) -> PIN4_W<4> { + PIN4_W::new(self) + } + #[doc = "Bit 5 - Pin 5"] + #[inline(always)] + pub fn pin5(&mut self) -> PIN5_W<5> { + PIN5_W::new(self) + } + #[doc = "Bit 6 - Pin 6"] + #[inline(always)] + pub fn pin6(&mut self) -> PIN6_W<6> { + PIN6_W::new(self) + } + #[doc = "Bit 7 - Pin 7"] + #[inline(always)] + pub fn pin7(&mut self) -> PIN7_W<7> { + PIN7_W::new(self) + } + #[doc = "Bit 8 - Pin 8"] + #[inline(always)] + pub fn pin8(&mut self) -> PIN8_W<8> { + PIN8_W::new(self) + } + #[doc = "Bit 9 - Pin 9"] + #[inline(always)] + pub fn pin9(&mut self) -> PIN9_W<9> { + PIN9_W::new(self) + } + #[doc = "Bit 10 - Pin 10"] + #[inline(always)] + pub fn pin10(&mut self) -> PIN10_W<10> { + PIN10_W::new(self) + } + #[doc = "Bit 11 - Pin 11"] + #[inline(always)] + pub fn pin11(&mut self) -> PIN11_W<11> { + PIN11_W::new(self) + } + #[doc = "Bit 12 - Pin 12"] + #[inline(always)] + pub fn pin12(&mut self) -> PIN12_W<12> { + PIN12_W::new(self) + } + #[doc = "Bit 13 - Pin 13"] + #[inline(always)] + pub fn pin13(&mut self) -> PIN13_W<13> { + PIN13_W::new(self) + } + #[doc = "Bit 14 - Pin 14"] + #[inline(always)] + pub fn pin14(&mut self) -> PIN14_W<14> { + PIN14_W::new(self) + } + #[doc = "Bit 15 - Pin 15"] + #[inline(always)] + pub fn pin15(&mut self) -> PIN15_W<15> { + PIN15_W::new(self) + } + #[doc = "Bit 16 - Pin 16"] + #[inline(always)] + pub fn pin16(&mut self) -> PIN16_W<16> { + PIN16_W::new(self) + } + #[doc = "Bit 17 - Pin 17"] + #[inline(always)] + pub fn pin17(&mut self) -> PIN17_W<17> { + PIN17_W::new(self) + } + #[doc = "Bit 18 - Pin 18"] + #[inline(always)] + pub fn pin18(&mut self) -> PIN18_W<18> { + PIN18_W::new(self) + } + #[doc = "Bit 19 - Pin 19"] + #[inline(always)] + pub fn pin19(&mut self) -> PIN19_W<19> { + PIN19_W::new(self) + } + #[doc = "Bit 20 - Pin 20"] + #[inline(always)] + pub fn pin20(&mut self) -> PIN20_W<20> { + PIN20_W::new(self) + } + #[doc = "Bit 21 - Pin 21"] + #[inline(always)] + pub fn pin21(&mut self) -> PIN21_W<21> { + PIN21_W::new(self) + } + #[doc = "Bit 22 - Pin 22"] + #[inline(always)] + pub fn pin22(&mut self) -> PIN22_W<22> { + PIN22_W::new(self) + } + #[doc = "Bit 23 - Pin 23"] + #[inline(always)] + pub fn pin23(&mut self) -> PIN23_W<23> { + PIN23_W::new(self) + } + #[doc = "Bit 24 - Pin 24"] + #[inline(always)] + pub fn pin24(&mut self) -> PIN24_W<24> { + PIN24_W::new(self) + } + #[doc = "Bit 25 - Pin 25"] + #[inline(always)] + pub fn pin25(&mut self) -> PIN25_W<25> { + PIN25_W::new(self) + } + #[doc = "Bit 26 - Pin 26"] + #[inline(always)] + pub fn pin26(&mut self) -> PIN26_W<26> { + PIN26_W::new(self) + } + #[doc = "Bit 27 - Pin 27"] + #[inline(always)] + pub fn pin27(&mut self) -> PIN27_W<27> { + PIN27_W::new(self) + } + #[doc = "Bit 28 - Pin 28"] + #[inline(always)] + pub fn pin28(&mut self) -> PIN28_W<28> { + PIN28_W::new(self) + } + #[doc = "Bit 29 - Pin 29"] + #[inline(always)] + pub fn pin29(&mut self) -> PIN29_W<29> { + PIN29_W::new(self) + } + #[doc = "Bit 30 - Pin 30"] + #[inline(always)] + pub fn pin30(&mut self) -> PIN30_W<30> { + PIN30_W::new(self) + } + #[doc = "Bit 31 - Pin 31"] + #[inline(always)] + pub fn pin31(&mut self) -> PIN31_W<31> { + PIN31_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Set individual bits in GPIO port\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [outset](index.html) module"] +pub struct OUTSET_SPEC; +impl crate::RegisterSpec for OUTSET_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [outset::R](R) reader structure"] +impl crate::Readable for OUTSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [outset::W](W) writer structure"] +impl crate::Writable for OUTSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets OUTSET to value 0"] +impl crate::Resettable for OUTSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/p0_ns/pin_cnf.rs b/pacs/nrf9120-pac/src/p0_ns/pin_cnf.rs new file mode 100644 index 00000000..78fd0c08 --- /dev/null +++ b/pacs/nrf9120-pac/src/p0_ns/pin_cnf.rs @@ -0,0 +1,478 @@ +#[doc = "Register `PIN_CNF[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PIN_CNF[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DIR` reader - Pin direction. Same physical register as DIR register"] +pub type DIR_R = crate::BitReader; +#[doc = "Pin direction. Same physical register as DIR register\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum DIR_A { + #[doc = "0: Configure pin as an input pin"] + INPUT = 0, + #[doc = "1: Configure pin as an output pin"] + OUTPUT = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: DIR_A) -> Self { + variant as u8 != 0 + } +} +impl DIR_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> DIR_A { + match self.bits { + false => DIR_A::INPUT, + true => DIR_A::OUTPUT, + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == DIR_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == DIR_A::OUTPUT + } +} +#[doc = "Field `DIR` writer - Pin direction. Same physical register as DIR register"] +pub type DIR_W<'a, const O: u8> = crate::BitWriter<'a, u32, PIN_CNF_SPEC, DIR_A, O>; +impl<'a, const O: u8> DIR_W<'a, O> { + #[doc = "Configure pin as an input pin"] + #[inline(always)] + pub fn input(self) -> &'a mut W { + self.variant(DIR_A::INPUT) + } + #[doc = "Configure pin as an output pin"] + #[inline(always)] + pub fn output(self) -> &'a mut W { + self.variant(DIR_A::OUTPUT) + } +} +#[doc = "Field `INPUT` reader - Connect or disconnect input buffer"] +pub type INPUT_R = crate::BitReader; +#[doc = "Connect or disconnect input buffer\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum INPUT_A { + #[doc = "0: Connect input buffer"] + CONNECT = 0, + #[doc = "1: Disconnect input buffer"] + DISCONNECT = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: INPUT_A) -> Self { + variant as u8 != 0 + } +} +impl INPUT_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> INPUT_A { + match self.bits { + false => INPUT_A::CONNECT, + true => INPUT_A::DISCONNECT, + } + } + #[doc = "Checks if the value of the field is `CONNECT`"] + #[inline(always)] + pub fn is_connect(&self) -> bool { + *self == INPUT_A::CONNECT + } + #[doc = "Checks if the value of the field is `DISCONNECT`"] + #[inline(always)] + pub fn is_disconnect(&self) -> bool { + *self == INPUT_A::DISCONNECT + } +} +#[doc = "Field `INPUT` writer - Connect or disconnect input buffer"] +pub type INPUT_W<'a, const O: u8> = crate::BitWriter<'a, u32, PIN_CNF_SPEC, INPUT_A, O>; +impl<'a, const O: u8> INPUT_W<'a, O> { + #[doc = "Connect input buffer"] + #[inline(always)] + pub fn connect(self) -> &'a mut W { + self.variant(INPUT_A::CONNECT) + } + #[doc = "Disconnect input buffer"] + #[inline(always)] + pub fn disconnect(self) -> &'a mut W { + self.variant(INPUT_A::DISCONNECT) + } +} +#[doc = "Field `PULL` reader - Pull configuration"] +pub type PULL_R = crate::FieldReader; +#[doc = "Pull configuration\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum PULL_A { + #[doc = "0: No pull"] + DISABLED = 0, + #[doc = "1: Pull down on pin"] + PULLDOWN = 1, + #[doc = "3: Pull up on pin"] + PULLUP = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PULL_A) -> Self { + variant as _ + } +} +impl PULL_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(PULL_A::DISABLED), + 1 => Some(PULL_A::PULLDOWN), + 3 => Some(PULL_A::PULLUP), + _ => None, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == PULL_A::DISABLED + } + #[doc = "Checks if the value of the field is `PULLDOWN`"] + #[inline(always)] + pub fn is_pulldown(&self) -> bool { + *self == PULL_A::PULLDOWN + } + #[doc = "Checks if the value of the field is `PULLUP`"] + #[inline(always)] + pub fn is_pullup(&self) -> bool { + *self == PULL_A::PULLUP + } +} +#[doc = "Field `PULL` writer - Pull configuration"] +pub type PULL_W<'a, const O: u8> = crate::FieldWriter<'a, u32, PIN_CNF_SPEC, u8, PULL_A, 2, O>; +impl<'a, const O: u8> PULL_W<'a, O> { + #[doc = "No pull"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(PULL_A::DISABLED) + } + #[doc = "Pull down on pin"] + #[inline(always)] + pub fn pulldown(self) -> &'a mut W { + self.variant(PULL_A::PULLDOWN) + } + #[doc = "Pull up on pin"] + #[inline(always)] + pub fn pullup(self) -> &'a mut W { + self.variant(PULL_A::PULLUP) + } +} +#[doc = "Field `DRIVE` reader - Drive configuration"] +pub type DRIVE_R = crate::FieldReader; +#[doc = "Drive configuration\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum DRIVE_A { + #[doc = "0: Standard '0', standard '1'"] + S0S1 = 0, + #[doc = "1: High drive '0', standard '1'"] + H0S1 = 1, + #[doc = "2: Standard '0', high drive '1'"] + S0H1 = 2, + #[doc = "3: High drive '0', high 'drive '1''"] + H0H1 = 3, + #[doc = "4: Disconnect '0', standard '1' (normally used for wired-or connections)"] + D0S1 = 4, + #[doc = "5: Disconnect '0', high drive '1' (normally used for wired-or connections)"] + D0H1 = 5, + #[doc = "6: Standard '0', disconnect '1' (normally used for wired-and connections)"] + S0D1 = 6, + #[doc = "7: High drive '0', disconnect '1' (normally used for wired-and connections)"] + H0D1 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: DRIVE_A) -> Self { + variant as _ + } +} +impl DRIVE_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> DRIVE_A { + match self.bits { + 0 => DRIVE_A::S0S1, + 1 => DRIVE_A::H0S1, + 2 => DRIVE_A::S0H1, + 3 => DRIVE_A::H0H1, + 4 => DRIVE_A::D0S1, + 5 => DRIVE_A::D0H1, + 6 => DRIVE_A::S0D1, + 7 => DRIVE_A::H0D1, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `S0S1`"] + #[inline(always)] + pub fn is_s0s1(&self) -> bool { + *self == DRIVE_A::S0S1 + } + #[doc = "Checks if the value of the field is `H0S1`"] + #[inline(always)] + pub fn is_h0s1(&self) -> bool { + *self == DRIVE_A::H0S1 + } + #[doc = "Checks if the value of the field is `S0H1`"] + #[inline(always)] + pub fn is_s0h1(&self) -> bool { + *self == DRIVE_A::S0H1 + } + #[doc = "Checks if the value of the field is `H0H1`"] + #[inline(always)] + pub fn is_h0h1(&self) -> bool { + *self == DRIVE_A::H0H1 + } + #[doc = "Checks if the value of the field is `D0S1`"] + #[inline(always)] + pub fn is_d0s1(&self) -> bool { + *self == DRIVE_A::D0S1 + } + #[doc = "Checks if the value of the field is `D0H1`"] + #[inline(always)] + pub fn is_d0h1(&self) -> bool { + *self == DRIVE_A::D0H1 + } + #[doc = "Checks if the value of the field is `S0D1`"] + #[inline(always)] + pub fn is_s0d1(&self) -> bool { + *self == DRIVE_A::S0D1 + } + #[doc = "Checks if the value of the field is `H0D1`"] + #[inline(always)] + pub fn is_h0d1(&self) -> bool { + *self == DRIVE_A::H0D1 + } +} +#[doc = "Field `DRIVE` writer - Drive configuration"] +pub type DRIVE_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u32, PIN_CNF_SPEC, u8, DRIVE_A, 3, O>; +impl<'a, const O: u8> DRIVE_W<'a, O> { + #[doc = "Standard '0', standard '1'"] + #[inline(always)] + pub fn s0s1(self) -> &'a mut W { + self.variant(DRIVE_A::S0S1) + } + #[doc = "High drive '0', standard '1'"] + #[inline(always)] + pub fn h0s1(self) -> &'a mut W { + self.variant(DRIVE_A::H0S1) + } + #[doc = "Standard '0', high drive '1'"] + #[inline(always)] + pub fn s0h1(self) -> &'a mut W { + self.variant(DRIVE_A::S0H1) + } + #[doc = "High drive '0', high 'drive '1''"] + #[inline(always)] + pub fn h0h1(self) -> &'a mut W { + self.variant(DRIVE_A::H0H1) + } + #[doc = "Disconnect '0', standard '1' (normally used for wired-or connections)"] + #[inline(always)] + pub fn d0s1(self) -> &'a mut W { + self.variant(DRIVE_A::D0S1) + } + #[doc = "Disconnect '0', high drive '1' (normally used for wired-or connections)"] + #[inline(always)] + pub fn d0h1(self) -> &'a mut W { + self.variant(DRIVE_A::D0H1) + } + #[doc = "Standard '0', disconnect '1' (normally used for wired-and connections)"] + #[inline(always)] + pub fn s0d1(self) -> &'a mut W { + self.variant(DRIVE_A::S0D1) + } + #[doc = "High drive '0', disconnect '1' (normally used for wired-and connections)"] + #[inline(always)] + pub fn h0d1(self) -> &'a mut W { + self.variant(DRIVE_A::H0D1) + } +} +#[doc = "Field `SENSE` reader - Pin sensing mechanism"] +pub type SENSE_R = crate::FieldReader; +#[doc = "Pin sensing mechanism\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SENSE_A { + #[doc = "0: Disabled"] + DISABLED = 0, + #[doc = "2: Sense for high level"] + HIGH = 2, + #[doc = "3: Sense for low level"] + LOW = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SENSE_A) -> Self { + variant as _ + } +} +impl SENSE_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SENSE_A::DISABLED), + 2 => Some(SENSE_A::HIGH), + 3 => Some(SENSE_A::LOW), + _ => None, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == SENSE_A::DISABLED + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + *self == SENSE_A::HIGH + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + *self == SENSE_A::LOW + } +} +#[doc = "Field `SENSE` writer - Pin sensing mechanism"] +pub type SENSE_W<'a, const O: u8> = crate::FieldWriter<'a, u32, PIN_CNF_SPEC, u8, SENSE_A, 2, O>; +impl<'a, const O: u8> SENSE_W<'a, O> { + #[doc = "Disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(SENSE_A::DISABLED) + } + #[doc = "Sense for high level"] + #[inline(always)] + pub fn high(self) -> &'a mut W { + self.variant(SENSE_A::HIGH) + } + #[doc = "Sense for low level"] + #[inline(always)] + pub fn low(self) -> &'a mut W { + self.variant(SENSE_A::LOW) + } +} +impl R { + #[doc = "Bit 0 - Pin direction. Same physical register as DIR register"] + #[inline(always)] + pub fn dir(&self) -> DIR_R { + DIR_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Connect or disconnect input buffer"] + #[inline(always)] + pub fn input(&self) -> INPUT_R { + INPUT_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bits 2:3 - Pull configuration"] + #[inline(always)] + pub fn pull(&self) -> PULL_R { + PULL_R::new(((self.bits >> 2) & 3) as u8) + } + #[doc = "Bits 8:10 - Drive configuration"] + #[inline(always)] + pub fn drive(&self) -> DRIVE_R { + DRIVE_R::new(((self.bits >> 8) & 7) as u8) + } + #[doc = "Bits 16:17 - Pin sensing mechanism"] + #[inline(always)] + pub fn sense(&self) -> SENSE_R { + SENSE_R::new(((self.bits >> 16) & 3) as u8) + } +} +impl W { + #[doc = "Bit 0 - Pin direction. Same physical register as DIR register"] + #[inline(always)] + pub fn dir(&mut self) -> DIR_W<0> { + DIR_W::new(self) + } + #[doc = "Bit 1 - Connect or disconnect input buffer"] + #[inline(always)] + pub fn input(&mut self) -> INPUT_W<1> { + INPUT_W::new(self) + } + #[doc = "Bits 2:3 - Pull configuration"] + #[inline(always)] + pub fn pull(&mut self) -> PULL_W<2> { + PULL_W::new(self) + } + #[doc = "Bits 8:10 - Drive configuration"] + #[inline(always)] + pub fn drive(&mut self) -> DRIVE_W<8> { + DRIVE_W::new(self) + } + #[doc = "Bits 16:17 - Pin sensing mechanism"] + #[inline(always)] + pub fn sense(&mut self) -> SENSE_W<16> { + SENSE_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Description collection: Configuration of GPIO pins\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pin_cnf](index.html) module"] +pub struct PIN_CNF_SPEC; +impl crate::RegisterSpec for PIN_CNF_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pin_cnf::R](R) reader structure"] +impl crate::Readable for PIN_CNF_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [pin_cnf::W](W) writer structure"] +impl crate::Writable for PIN_CNF_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PIN_CNF[%s] +to value 0x02"] +impl crate::Resettable for PIN_CNF_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x02 + } +} diff --git a/pacs/nrf9120-pac/src/pdm_ns.rs b/pacs/nrf9120-pac/src/pdm_ns.rs new file mode 100644 index 00000000..9168164d --- /dev/null +++ b/pacs/nrf9120-pac/src/pdm_ns.rs @@ -0,0 +1,140 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Starts continuous PDM transfer"] + pub tasks_start: TASKS_START, + #[doc = "0x04 - Stops PDM transfer"] + pub tasks_stop: TASKS_STOP, + _reserved2: [u8; 0x78], + #[doc = "0x80 - Subscribe configuration for task START"] + pub subscribe_start: SUBSCRIBE_START, + #[doc = "0x84 - Subscribe configuration for task STOP"] + pub subscribe_stop: SUBSCRIBE_STOP, + _reserved4: [u8; 0x78], + #[doc = "0x100 - PDM transfer has started"] + pub events_started: EVENTS_STARTED, + #[doc = "0x104 - PDM transfer has finished"] + pub events_stopped: EVENTS_STOPPED, + #[doc = "0x108 - The PDM has written the last sample specified by SAMPLE.MAXCNT (or the last sample after a STOP task has been received) to Data RAM"] + pub events_end: EVENTS_END, + _reserved7: [u8; 0x74], + #[doc = "0x180 - Publish configuration for event STARTED"] + pub publish_started: PUBLISH_STARTED, + #[doc = "0x184 - Publish configuration for event STOPPED"] + pub publish_stopped: PUBLISH_STOPPED, + #[doc = "0x188 - Publish configuration for event END"] + pub publish_end: PUBLISH_END, + _reserved10: [u8; 0x0174], + #[doc = "0x300 - Enable or disable interrupt"] + pub inten: INTEN, + #[doc = "0x304 - Enable interrupt"] + pub intenset: INTENSET, + #[doc = "0x308 - Disable interrupt"] + pub intenclr: INTENCLR, + _reserved13: [u8; 0x01f4], + #[doc = "0x500 - PDM module enable register"] + pub enable: ENABLE, + #[doc = "0x504 - PDM clock generator control"] + pub pdmclkctrl: PDMCLKCTRL, + #[doc = "0x508 - Defines the routing of the connected PDM microphones' signals"] + pub mode: MODE, + _reserved16: [u8; 0x0c], + #[doc = "0x518 - Left output gain adjustment"] + pub gainl: GAINL, + #[doc = "0x51c - Right output gain adjustment"] + pub gainr: GAINR, + #[doc = "0x520 - Selects the ratio between PDM_CLK and output sample rate. Change PDMCLKCTRL accordingly."] + pub ratio: RATIO, + _reserved19: [u8; 0x1c], + #[doc = "0x540..0x548 - Unspecified"] + pub psel: PSEL, + _reserved20: [u8; 0x18], + #[doc = "0x560..0x568 - Unspecified"] + pub sample: SAMPLE, +} +#[doc = "TASKS_START (w) register accessor: an alias for `Reg`"] +pub type TASKS_START = crate::Reg; +#[doc = "Starts continuous PDM transfer"] +pub mod tasks_start; +#[doc = "TASKS_STOP (w) register accessor: an alias for `Reg`"] +pub type TASKS_STOP = crate::Reg; +#[doc = "Stops PDM transfer"] +pub mod tasks_stop; +#[doc = "SUBSCRIBE_START (rw) register accessor: an alias for `Reg`"] +pub type SUBSCRIBE_START = crate::Reg; +#[doc = "Subscribe configuration for task START"] +pub mod subscribe_start; +#[doc = "SUBSCRIBE_STOP (rw) register accessor: an alias for `Reg`"] +pub type SUBSCRIBE_STOP = crate::Reg; +#[doc = "Subscribe configuration for task STOP"] +pub mod subscribe_stop; +#[doc = "EVENTS_STARTED (rw) register accessor: an alias for `Reg`"] +pub type EVENTS_STARTED = crate::Reg; +#[doc = "PDM transfer has started"] +pub mod events_started; +#[doc = "EVENTS_STOPPED (rw) register accessor: an alias for `Reg`"] +pub type EVENTS_STOPPED = crate::Reg; +#[doc = "PDM transfer has finished"] +pub mod events_stopped; +#[doc = "EVENTS_END (rw) register accessor: an alias for `Reg`"] +pub type EVENTS_END = crate::Reg; +#[doc = "The PDM has written the last sample specified by SAMPLE.MAXCNT (or the last sample after a STOP task has been received) to Data RAM"] +pub mod events_end; +#[doc = "PUBLISH_STARTED (rw) register accessor: an alias for `Reg`"] +pub type PUBLISH_STARTED = crate::Reg; +#[doc = "Publish configuration for event STARTED"] +pub mod publish_started; +#[doc = "PUBLISH_STOPPED (rw) register accessor: an alias for `Reg`"] +pub type PUBLISH_STOPPED = crate::Reg; +#[doc = "Publish configuration for event STOPPED"] +pub mod publish_stopped; +#[doc = "PUBLISH_END (rw) register accessor: an alias for `Reg`"] +pub type PUBLISH_END = crate::Reg; +#[doc = "Publish configuration for event END"] +pub mod publish_end; +#[doc = "INTEN (rw) register accessor: an alias for `Reg`"] +pub type INTEN = crate::Reg; +#[doc = "Enable or disable interrupt"] +pub mod inten; +#[doc = "INTENSET (rw) register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "Enable interrupt"] +pub mod intenset; +#[doc = "INTENCLR (rw) register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "Disable interrupt"] +pub mod intenclr; +#[doc = "ENABLE (rw) register accessor: an alias for `Reg`"] +pub type ENABLE = crate::Reg; +#[doc = "PDM module enable register"] +pub mod enable; +#[doc = "PDMCLKCTRL (rw) register accessor: an alias for `Reg`"] +pub type PDMCLKCTRL = crate::Reg; +#[doc = "PDM clock generator control"] +pub mod pdmclkctrl; +#[doc = "MODE (rw) register accessor: an alias for `Reg`"] +pub type MODE = crate::Reg; +#[doc = "Defines the routing of the connected PDM microphones' signals"] +pub mod mode; +#[doc = "GAINL (rw) register accessor: an alias for `Reg`"] +pub type GAINL = crate::Reg; +#[doc = "Left output gain adjustment"] +pub mod gainl; +#[doc = "GAINR (rw) register accessor: an alias for `Reg`"] +pub type GAINR = crate::Reg; +#[doc = "Right output gain adjustment"] +pub mod gainr; +#[doc = "RATIO (rw) register accessor: an alias for `Reg`"] +pub type RATIO = crate::Reg; +#[doc = "Selects the ratio between PDM_CLK and output sample rate. Change PDMCLKCTRL accordingly."] +pub mod ratio; +#[doc = "Unspecified"] +pub use psel::PSEL; +#[doc = r"Cluster"] +#[doc = "Unspecified"] +pub mod psel; +#[doc = "Unspecified"] +pub use sample::SAMPLE; +#[doc = r"Cluster"] +#[doc = "Unspecified"] +pub mod sample; diff --git a/pacs/nrf9120-pac/src/pdm_ns/enable.rs b/pacs/nrf9120-pac/src/pdm_ns/enable.rs new file mode 100644 index 00000000..b51e25da --- /dev/null +++ b/pacs/nrf9120-pac/src/pdm_ns/enable.rs @@ -0,0 +1,126 @@ +#[doc = "Register `ENABLE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `ENABLE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ENABLE` reader - Enable or disable PDM module"] +pub type ENABLE_R = crate::BitReader; +#[doc = "Enable or disable PDM module\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum ENABLE_A { + #[doc = "0: Disable"] + DISABLED = 0, + #[doc = "1: Enable"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: ENABLE_A) -> Self { + variant as u8 != 0 + } +} +impl ENABLE_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> ENABLE_A { + match self.bits { + false => ENABLE_A::DISABLED, + true => ENABLE_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == ENABLE_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == ENABLE_A::ENABLED + } +} +#[doc = "Field `ENABLE` writer - Enable or disable PDM module"] +pub type ENABLE_W<'a, const O: u8> = crate::BitWriter<'a, u32, ENABLE_SPEC, ENABLE_A, O>; +impl<'a, const O: u8> ENABLE_W<'a, O> { + #[doc = "Disable"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(ENABLE_A::DISABLED) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(ENABLE_A::ENABLED) + } +} +impl R { + #[doc = "Bit 0 - Enable or disable PDM module"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new((self.bits & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Enable or disable PDM module"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W<0> { + ENABLE_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "PDM module enable register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [enable](index.html) module"] +pub struct ENABLE_SPEC; +impl crate::RegisterSpec for ENABLE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [enable::R](R) reader structure"] +impl crate::Readable for ENABLE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [enable::W](W) writer structure"] +impl crate::Writable for ENABLE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets ENABLE to value 0"] +impl crate::Resettable for ENABLE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/pdm_ns/events_end.rs b/pacs/nrf9120-pac/src/pdm_ns/events_end.rs new file mode 100644 index 00000000..1eef1a13 --- /dev/null +++ b/pacs/nrf9120-pac/src/pdm_ns/events_end.rs @@ -0,0 +1,127 @@ +#[doc = "Register `EVENTS_END` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVENTS_END` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `EVENTS_END` reader - The PDM has written the last sample specified by SAMPLE.MAXCNT (or the last sample after a STOP task has been received) to Data RAM"] +pub type EVENTS_END_R = crate::BitReader; +#[doc = "The PDM has written the last sample specified by SAMPLE.MAXCNT (or the last sample after a STOP task has been received) to Data RAM\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum EVENTS_END_A { + #[doc = "0: Event not generated"] + NOT_GENERATED = 0, + #[doc = "1: Event generated"] + GENERATED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: EVENTS_END_A) -> Self { + variant as u8 != 0 + } +} +impl EVENTS_END_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EVENTS_END_A { + match self.bits { + false => EVENTS_END_A::NOT_GENERATED, + true => EVENTS_END_A::GENERATED, + } + } + #[doc = "Checks if the value of the field is `NOT_GENERATED`"] + #[inline(always)] + pub fn is_not_generated(&self) -> bool { + *self == EVENTS_END_A::NOT_GENERATED + } + #[doc = "Checks if the value of the field is `GENERATED`"] + #[inline(always)] + pub fn is_generated(&self) -> bool { + *self == EVENTS_END_A::GENERATED + } +} +#[doc = "Field `EVENTS_END` writer - The PDM has written the last sample specified by SAMPLE.MAXCNT (or the last sample after a STOP task has been received) to Data RAM"] +pub type EVENTS_END_W<'a, const O: u8> = + crate::BitWriter<'a, u32, EVENTS_END_SPEC, EVENTS_END_A, O>; +impl<'a, const O: u8> EVENTS_END_W<'a, O> { + #[doc = "Event not generated"] + #[inline(always)] + pub fn not_generated(self) -> &'a mut W { + self.variant(EVENTS_END_A::NOT_GENERATED) + } + #[doc = "Event generated"] + #[inline(always)] + pub fn generated(self) -> &'a mut W { + self.variant(EVENTS_END_A::GENERATED) + } +} +impl R { + #[doc = "Bit 0 - The PDM has written the last sample specified by SAMPLE.MAXCNT (or the last sample after a STOP task has been received) to Data RAM"] + #[inline(always)] + pub fn events_end(&self) -> EVENTS_END_R { + EVENTS_END_R::new((self.bits & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - The PDM has written the last sample specified by SAMPLE.MAXCNT (or the last sample after a STOP task has been received) to Data RAM"] + #[inline(always)] + pub fn events_end(&mut self) -> EVENTS_END_W<0> { + EVENTS_END_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "The PDM has written the last sample specified by SAMPLE.MAXCNT (or the last sample after a STOP task has been received) to Data RAM\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [events_end](index.html) module"] +pub struct EVENTS_END_SPEC; +impl crate::RegisterSpec for EVENTS_END_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [events_end::R](R) reader structure"] +impl crate::Readable for EVENTS_END_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [events_end::W](W) writer structure"] +impl crate::Writable for EVENTS_END_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EVENTS_END to value 0"] +impl crate::Resettable for EVENTS_END_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/pdm_ns/events_started.rs b/pacs/nrf9120-pac/src/pdm_ns/events_started.rs new file mode 100644 index 00000000..89b96909 --- /dev/null +++ b/pacs/nrf9120-pac/src/pdm_ns/events_started.rs @@ -0,0 +1,127 @@ +#[doc = "Register `EVENTS_STARTED` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVENTS_STARTED` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `EVENTS_STARTED` reader - PDM transfer has started"] +pub type EVENTS_STARTED_R = crate::BitReader; +#[doc = "PDM transfer has started\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum EVENTS_STARTED_A { + #[doc = "0: Event not generated"] + NOT_GENERATED = 0, + #[doc = "1: Event generated"] + GENERATED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: EVENTS_STARTED_A) -> Self { + variant as u8 != 0 + } +} +impl EVENTS_STARTED_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EVENTS_STARTED_A { + match self.bits { + false => EVENTS_STARTED_A::NOT_GENERATED, + true => EVENTS_STARTED_A::GENERATED, + } + } + #[doc = "Checks if the value of the field is `NOT_GENERATED`"] + #[inline(always)] + pub fn is_not_generated(&self) -> bool { + *self == EVENTS_STARTED_A::NOT_GENERATED + } + #[doc = "Checks if the value of the field is `GENERATED`"] + #[inline(always)] + pub fn is_generated(&self) -> bool { + *self == EVENTS_STARTED_A::GENERATED + } +} +#[doc = "Field `EVENTS_STARTED` writer - PDM transfer has started"] +pub type EVENTS_STARTED_W<'a, const O: u8> = + crate::BitWriter<'a, u32, EVENTS_STARTED_SPEC, EVENTS_STARTED_A, O>; +impl<'a, const O: u8> EVENTS_STARTED_W<'a, O> { + #[doc = "Event not generated"] + #[inline(always)] + pub fn not_generated(self) -> &'a mut W { + self.variant(EVENTS_STARTED_A::NOT_GENERATED) + } + #[doc = "Event generated"] + #[inline(always)] + pub fn generated(self) -> &'a mut W { + self.variant(EVENTS_STARTED_A::GENERATED) + } +} +impl R { + #[doc = "Bit 0 - PDM transfer has started"] + #[inline(always)] + pub fn events_started(&self) -> EVENTS_STARTED_R { + EVENTS_STARTED_R::new((self.bits & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - PDM transfer has started"] + #[inline(always)] + pub fn events_started(&mut self) -> EVENTS_STARTED_W<0> { + EVENTS_STARTED_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "PDM transfer has started\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [events_started](index.html) module"] +pub struct EVENTS_STARTED_SPEC; +impl crate::RegisterSpec for EVENTS_STARTED_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [events_started::R](R) reader structure"] +impl crate::Readable for EVENTS_STARTED_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [events_started::W](W) writer structure"] +impl crate::Writable for EVENTS_STARTED_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EVENTS_STARTED to value 0"] +impl crate::Resettable for EVENTS_STARTED_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/pdm_ns/events_stopped.rs b/pacs/nrf9120-pac/src/pdm_ns/events_stopped.rs new file mode 100644 index 00000000..90fe8192 --- /dev/null +++ b/pacs/nrf9120-pac/src/pdm_ns/events_stopped.rs @@ -0,0 +1,127 @@ +#[doc = "Register `EVENTS_STOPPED` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVENTS_STOPPED` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `EVENTS_STOPPED` reader - PDM transfer has finished"] +pub type EVENTS_STOPPED_R = crate::BitReader; +#[doc = "PDM transfer has finished\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum EVENTS_STOPPED_A { + #[doc = "0: Event not generated"] + NOT_GENERATED = 0, + #[doc = "1: Event generated"] + GENERATED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: EVENTS_STOPPED_A) -> Self { + variant as u8 != 0 + } +} +impl EVENTS_STOPPED_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EVENTS_STOPPED_A { + match self.bits { + false => EVENTS_STOPPED_A::NOT_GENERATED, + true => EVENTS_STOPPED_A::GENERATED, + } + } + #[doc = "Checks if the value of the field is `NOT_GENERATED`"] + #[inline(always)] + pub fn is_not_generated(&self) -> bool { + *self == EVENTS_STOPPED_A::NOT_GENERATED + } + #[doc = "Checks if the value of the field is `GENERATED`"] + #[inline(always)] + pub fn is_generated(&self) -> bool { + *self == EVENTS_STOPPED_A::GENERATED + } +} +#[doc = "Field `EVENTS_STOPPED` writer - PDM transfer has finished"] +pub type EVENTS_STOPPED_W<'a, const O: u8> = + crate::BitWriter<'a, u32, EVENTS_STOPPED_SPEC, EVENTS_STOPPED_A, O>; +impl<'a, const O: u8> EVENTS_STOPPED_W<'a, O> { + #[doc = "Event not generated"] + #[inline(always)] + pub fn not_generated(self) -> &'a mut W { + self.variant(EVENTS_STOPPED_A::NOT_GENERATED) + } + #[doc = "Event generated"] + #[inline(always)] + pub fn generated(self) -> &'a mut W { + self.variant(EVENTS_STOPPED_A::GENERATED) + } +} +impl R { + #[doc = "Bit 0 - PDM transfer has finished"] + #[inline(always)] + pub fn events_stopped(&self) -> EVENTS_STOPPED_R { + EVENTS_STOPPED_R::new((self.bits & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - PDM transfer has finished"] + #[inline(always)] + pub fn events_stopped(&mut self) -> EVENTS_STOPPED_W<0> { + EVENTS_STOPPED_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "PDM transfer has finished\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [events_stopped](index.html) module"] +pub struct EVENTS_STOPPED_SPEC; +impl crate::RegisterSpec for EVENTS_STOPPED_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [events_stopped::R](R) reader structure"] +impl crate::Readable for EVENTS_STOPPED_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [events_stopped::W](W) writer structure"] +impl crate::Writable for EVENTS_STOPPED_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EVENTS_STOPPED to value 0"] +impl crate::Resettable for EVENTS_STOPPED_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/pdm_ns/gainl.rs b/pacs/nrf9120-pac/src/pdm_ns/gainl.rs new file mode 100644 index 00000000..797126c1 --- /dev/null +++ b/pacs/nrf9120-pac/src/pdm_ns/gainl.rs @@ -0,0 +1,141 @@ +#[doc = "Register `GAINL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GAINL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `GAINL` reader - Left output gain adjustment, in 0.5 dB steps, around the default module gain (see electrical parameters) 0x00 -20 dB gain adjust 0x01 -19.5 dB gain adjust (...) 0x27 -0.5 dB gain adjust 0x28 0 dB gain adjust 0x29 +0.5 dB gain adjust (...) 0x4F +19.5 dB gain adjust 0x50 +20 dB gain adjust"] +pub type GAINL_R = crate::FieldReader; +#[doc = "Left output gain adjustment, in 0.5 dB steps, around the default module gain (see electrical parameters) 0x00 -20 dB gain adjust 0x01 -19.5 dB gain adjust (...) 0x27 -0.5 dB gain adjust 0x28 0 dB gain adjust 0x29 +0.5 dB gain adjust (...) 0x4F +19.5 dB gain adjust 0x50 +20 dB gain adjust\n\nValue on reset: 40"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum GAINL_A { + #[doc = "0: -20 dB gain adjustment (minimum)"] + MIN_GAIN = 0, + #[doc = "40: 0 dB gain adjustment"] + DEFAULT_GAIN = 40, + #[doc = "80: +20 dB gain adjustment (maximum)"] + MAX_GAIN = 80, +} +impl From for u8 { + #[inline(always)] + fn from(variant: GAINL_A) -> Self { + variant as _ + } +} +impl GAINL_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(GAINL_A::MIN_GAIN), + 40 => Some(GAINL_A::DEFAULT_GAIN), + 80 => Some(GAINL_A::MAX_GAIN), + _ => None, + } + } + #[doc = "Checks if the value of the field is `MIN_GAIN`"] + #[inline(always)] + pub fn is_min_gain(&self) -> bool { + *self == GAINL_A::MIN_GAIN + } + #[doc = "Checks if the value of the field is `DEFAULT_GAIN`"] + #[inline(always)] + pub fn is_default_gain(&self) -> bool { + *self == GAINL_A::DEFAULT_GAIN + } + #[doc = "Checks if the value of the field is `MAX_GAIN`"] + #[inline(always)] + pub fn is_max_gain(&self) -> bool { + *self == GAINL_A::MAX_GAIN + } +} +#[doc = "Field `GAINL` writer - Left output gain adjustment, in 0.5 dB steps, around the default module gain (see electrical parameters) 0x00 -20 dB gain adjust 0x01 -19.5 dB gain adjust (...) 0x27 -0.5 dB gain adjust 0x28 0 dB gain adjust 0x29 +0.5 dB gain adjust (...) 0x4F +19.5 dB gain adjust 0x50 +20 dB gain adjust"] +pub type GAINL_W<'a, const O: u8> = crate::FieldWriter<'a, u32, GAINL_SPEC, u8, GAINL_A, 7, O>; +impl<'a, const O: u8> GAINL_W<'a, O> { + #[doc = "-20 dB gain adjustment (minimum)"] + #[inline(always)] + pub fn min_gain(self) -> &'a mut W { + self.variant(GAINL_A::MIN_GAIN) + } + #[doc = "0 dB gain adjustment"] + #[inline(always)] + pub fn default_gain(self) -> &'a mut W { + self.variant(GAINL_A::DEFAULT_GAIN) + } + #[doc = "+20 dB gain adjustment (maximum)"] + #[inline(always)] + pub fn max_gain(self) -> &'a mut W { + self.variant(GAINL_A::MAX_GAIN) + } +} +impl R { + #[doc = "Bits 0:6 - Left output gain adjustment, in 0.5 dB steps, around the default module gain (see electrical parameters) 0x00 -20 dB gain adjust 0x01 -19.5 dB gain adjust (...) 0x27 -0.5 dB gain adjust 0x28 0 dB gain adjust 0x29 +0.5 dB gain adjust (...) 0x4F +19.5 dB gain adjust 0x50 +20 dB gain adjust"] + #[inline(always)] + pub fn gainl(&self) -> GAINL_R { + GAINL_R::new((self.bits & 0x7f) as u8) + } +} +impl W { + #[doc = "Bits 0:6 - Left output gain adjustment, in 0.5 dB steps, around the default module gain (see electrical parameters) 0x00 -20 dB gain adjust 0x01 -19.5 dB gain adjust (...) 0x27 -0.5 dB gain adjust 0x28 0 dB gain adjust 0x29 +0.5 dB gain adjust (...) 0x4F +19.5 dB gain adjust 0x50 +20 dB gain adjust"] + #[inline(always)] + pub fn gainl(&mut self) -> GAINL_W<0> { + GAINL_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Left output gain adjustment\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gainl](index.html) module"] +pub struct GAINL_SPEC; +impl crate::RegisterSpec for GAINL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gainl::R](R) reader structure"] +impl crate::Readable for GAINL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gainl::W](W) writer structure"] +impl crate::Writable for GAINL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets GAINL to value 0x28"] +impl crate::Resettable for GAINL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x28 + } +} diff --git a/pacs/nrf9120-pac/src/pdm_ns/gainr.rs b/pacs/nrf9120-pac/src/pdm_ns/gainr.rs new file mode 100644 index 00000000..621e3851 --- /dev/null +++ b/pacs/nrf9120-pac/src/pdm_ns/gainr.rs @@ -0,0 +1,141 @@ +#[doc = "Register `GAINR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GAINR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `GAINR` reader - Right output gain adjustment, in 0.5 dB steps, around the default module gain (see electrical parameters)"] +pub type GAINR_R = crate::FieldReader; +#[doc = "Right output gain adjustment, in 0.5 dB steps, around the default module gain (see electrical parameters)\n\nValue on reset: 40"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum GAINR_A { + #[doc = "0: -20 dB gain adjustment (minimum)"] + MIN_GAIN = 0, + #[doc = "40: 0 dB gain adjustment"] + DEFAULT_GAIN = 40, + #[doc = "80: +20 dB gain adjustment (maximum)"] + MAX_GAIN = 80, +} +impl From for u8 { + #[inline(always)] + fn from(variant: GAINR_A) -> Self { + variant as _ + } +} +impl GAINR_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(GAINR_A::MIN_GAIN), + 40 => Some(GAINR_A::DEFAULT_GAIN), + 80 => Some(GAINR_A::MAX_GAIN), + _ => None, + } + } + #[doc = "Checks if the value of the field is `MIN_GAIN`"] + #[inline(always)] + pub fn is_min_gain(&self) -> bool { + *self == GAINR_A::MIN_GAIN + } + #[doc = "Checks if the value of the field is `DEFAULT_GAIN`"] + #[inline(always)] + pub fn is_default_gain(&self) -> bool { + *self == GAINR_A::DEFAULT_GAIN + } + #[doc = "Checks if the value of the field is `MAX_GAIN`"] + #[inline(always)] + pub fn is_max_gain(&self) -> bool { + *self == GAINR_A::MAX_GAIN + } +} +#[doc = "Field `GAINR` writer - Right output gain adjustment, in 0.5 dB steps, around the default module gain (see electrical parameters)"] +pub type GAINR_W<'a, const O: u8> = crate::FieldWriter<'a, u32, GAINR_SPEC, u8, GAINR_A, 7, O>; +impl<'a, const O: u8> GAINR_W<'a, O> { + #[doc = "-20 dB gain adjustment (minimum)"] + #[inline(always)] + pub fn min_gain(self) -> &'a mut W { + self.variant(GAINR_A::MIN_GAIN) + } + #[doc = "0 dB gain adjustment"] + #[inline(always)] + pub fn default_gain(self) -> &'a mut W { + self.variant(GAINR_A::DEFAULT_GAIN) + } + #[doc = "+20 dB gain adjustment (maximum)"] + #[inline(always)] + pub fn max_gain(self) -> &'a mut W { + self.variant(GAINR_A::MAX_GAIN) + } +} +impl R { + #[doc = "Bits 0:6 - Right output gain adjustment, in 0.5 dB steps, around the default module gain (see electrical parameters)"] + #[inline(always)] + pub fn gainr(&self) -> GAINR_R { + GAINR_R::new((self.bits & 0x7f) as u8) + } +} +impl W { + #[doc = "Bits 0:6 - Right output gain adjustment, in 0.5 dB steps, around the default module gain (see electrical parameters)"] + #[inline(always)] + pub fn gainr(&mut self) -> GAINR_W<0> { + GAINR_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Right output gain adjustment\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gainr](index.html) module"] +pub struct GAINR_SPEC; +impl crate::RegisterSpec for GAINR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gainr::R](R) reader structure"] +impl crate::Readable for GAINR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gainr::W](W) writer structure"] +impl crate::Writable for GAINR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets GAINR to value 0x28"] +impl crate::Resettable for GAINR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x28 + } +} diff --git a/pacs/nrf9120-pac/src/pdm_ns/inten.rs b/pacs/nrf9120-pac/src/pdm_ns/inten.rs new file mode 100644 index 00000000..47d1a0da --- /dev/null +++ b/pacs/nrf9120-pac/src/pdm_ns/inten.rs @@ -0,0 +1,246 @@ +#[doc = "Register `INTEN` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTEN` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `STARTED` reader - Enable or disable interrupt for event STARTED"] +pub type STARTED_R = crate::BitReader; +#[doc = "Enable or disable interrupt for event STARTED\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum STARTED_A { + #[doc = "0: Disable"] + DISABLED = 0, + #[doc = "1: Enable"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: STARTED_A) -> Self { + variant as u8 != 0 + } +} +impl STARTED_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> STARTED_A { + match self.bits { + false => STARTED_A::DISABLED, + true => STARTED_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == STARTED_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == STARTED_A::ENABLED + } +} +#[doc = "Field `STARTED` writer - Enable or disable interrupt for event STARTED"] +pub type STARTED_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTEN_SPEC, STARTED_A, O>; +impl<'a, const O: u8> STARTED_W<'a, O> { + #[doc = "Disable"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(STARTED_A::DISABLED) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(STARTED_A::ENABLED) + } +} +#[doc = "Field `STOPPED` reader - Enable or disable interrupt for event STOPPED"] +pub type STOPPED_R = crate::BitReader; +#[doc = "Enable or disable interrupt for event STOPPED\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum STOPPED_A { + #[doc = "0: Disable"] + DISABLED = 0, + #[doc = "1: Enable"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: STOPPED_A) -> Self { + variant as u8 != 0 + } +} +impl STOPPED_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> STOPPED_A { + match self.bits { + false => STOPPED_A::DISABLED, + true => STOPPED_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == STOPPED_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == STOPPED_A::ENABLED + } +} +#[doc = "Field `STOPPED` writer - Enable or disable interrupt for event STOPPED"] +pub type STOPPED_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTEN_SPEC, STOPPED_A, O>; +impl<'a, const O: u8> STOPPED_W<'a, O> { + #[doc = "Disable"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(STOPPED_A::DISABLED) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(STOPPED_A::ENABLED) + } +} +#[doc = "Field `END` reader - Enable or disable interrupt for event END"] +pub type END_R = crate::BitReader; +#[doc = "Enable or disable interrupt for event END\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum END_A { + #[doc = "0: Disable"] + DISABLED = 0, + #[doc = "1: Enable"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: END_A) -> Self { + variant as u8 != 0 + } +} +impl END_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> END_A { + match self.bits { + false => END_A::DISABLED, + true => END_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == END_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == END_A::ENABLED + } +} +#[doc = "Field `END` writer - Enable or disable interrupt for event END"] +pub type END_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTEN_SPEC, END_A, O>; +impl<'a, const O: u8> END_W<'a, O> { + #[doc = "Disable"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(END_A::DISABLED) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(END_A::ENABLED) + } +} +impl R { + #[doc = "Bit 0 - Enable or disable interrupt for event STARTED"] + #[inline(always)] + pub fn started(&self) -> STARTED_R { + STARTED_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Enable or disable interrupt for event STOPPED"] + #[inline(always)] + pub fn stopped(&self) -> STOPPED_R { + STOPPED_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Enable or disable interrupt for event END"] + #[inline(always)] + pub fn end(&self) -> END_R { + END_R::new(((self.bits >> 2) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Enable or disable interrupt for event STARTED"] + #[inline(always)] + pub fn started(&mut self) -> STARTED_W<0> { + STARTED_W::new(self) + } + #[doc = "Bit 1 - Enable or disable interrupt for event STOPPED"] + #[inline(always)] + pub fn stopped(&mut self) -> STOPPED_W<1> { + STOPPED_W::new(self) + } + #[doc = "Bit 2 - Enable or disable interrupt for event END"] + #[inline(always)] + pub fn end(&mut self) -> END_W<2> { + END_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Enable or disable interrupt\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [inten](index.html) module"] +pub struct INTEN_SPEC; +impl crate::RegisterSpec for INTEN_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [inten::R](R) reader structure"] +impl crate::Readable for INTEN_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [inten::W](W) writer structure"] +impl crate::Writable for INTEN_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTEN to value 0"] +impl crate::Resettable for INTEN_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/pdm_ns/intenclr.rs b/pacs/nrf9120-pac/src/pdm_ns/intenclr.rs new file mode 100644 index 00000000..a8f93ddc --- /dev/null +++ b/pacs/nrf9120-pac/src/pdm_ns/intenclr.rs @@ -0,0 +1,267 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `STARTED` reader - Write '1' to disable interrupt for event STARTED"] +pub type STARTED_R = crate::BitReader; +#[doc = "Write '1' to disable interrupt for event STARTED\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum STARTED_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: STARTED_A) -> Self { + variant as u8 != 0 + } +} +impl STARTED_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> STARTED_A { + match self.bits { + false => STARTED_A::DISABLED, + true => STARTED_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == STARTED_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == STARTED_A::ENABLED + } +} +#[doc = "Write '1' to disable interrupt for event STARTED\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum STARTED_AW { + #[doc = "1: Disable"] + CLEAR = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: STARTED_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `STARTED` writer - Write '1' to disable interrupt for event STARTED"] +pub type STARTED_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENCLR_SPEC, STARTED_AW, O>; +impl<'a, const O: u8> STARTED_W<'a, O> { + #[doc = "Disable"] + #[inline(always)] + pub fn clear(self) -> &'a mut W { + self.variant(STARTED_AW::CLEAR) + } +} +#[doc = "Field `STOPPED` reader - Write '1' to disable interrupt for event STOPPED"] +pub type STOPPED_R = crate::BitReader; +#[doc = "Write '1' to disable interrupt for event STOPPED\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum STOPPED_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: STOPPED_A) -> Self { + variant as u8 != 0 + } +} +impl STOPPED_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> STOPPED_A { + match self.bits { + false => STOPPED_A::DISABLED, + true => STOPPED_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == STOPPED_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == STOPPED_A::ENABLED + } +} +#[doc = "Write '1' to disable interrupt for event STOPPED\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum STOPPED_AW { + #[doc = "1: Disable"] + CLEAR = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: STOPPED_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `STOPPED` writer - Write '1' to disable interrupt for event STOPPED"] +pub type STOPPED_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENCLR_SPEC, STOPPED_AW, O>; +impl<'a, const O: u8> STOPPED_W<'a, O> { + #[doc = "Disable"] + #[inline(always)] + pub fn clear(self) -> &'a mut W { + self.variant(STOPPED_AW::CLEAR) + } +} +#[doc = "Field `END` reader - Write '1' to disable interrupt for event END"] +pub type END_R = crate::BitReader; +#[doc = "Write '1' to disable interrupt for event END\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum END_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: END_A) -> Self { + variant as u8 != 0 + } +} +impl END_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> END_A { + match self.bits { + false => END_A::DISABLED, + true => END_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == END_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == END_A::ENABLED + } +} +#[doc = "Write '1' to disable interrupt for event END\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum END_AW { + #[doc = "1: Disable"] + CLEAR = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: END_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `END` writer - Write '1' to disable interrupt for event END"] +pub type END_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENCLR_SPEC, END_AW, O>; +impl<'a, const O: u8> END_W<'a, O> { + #[doc = "Disable"] + #[inline(always)] + pub fn clear(self) -> &'a mut W { + self.variant(END_AW::CLEAR) + } +} +impl R { + #[doc = "Bit 0 - Write '1' to disable interrupt for event STARTED"] + #[inline(always)] + pub fn started(&self) -> STARTED_R { + STARTED_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Write '1' to disable interrupt for event STOPPED"] + #[inline(always)] + pub fn stopped(&self) -> STOPPED_R { + STOPPED_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Write '1' to disable interrupt for event END"] + #[inline(always)] + pub fn end(&self) -> END_R { + END_R::new(((self.bits >> 2) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Write '1' to disable interrupt for event STARTED"] + #[inline(always)] + pub fn started(&mut self) -> STARTED_W<0> { + STARTED_W::new(self) + } + #[doc = "Bit 1 - Write '1' to disable interrupt for event STOPPED"] + #[inline(always)] + pub fn stopped(&mut self) -> STOPPED_W<1> { + STOPPED_W::new(self) + } + #[doc = "Bit 2 - Write '1' to disable interrupt for event END"] + #[inline(always)] + pub fn end(&mut self) -> END_W<2> { + END_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Disable interrupt\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/pdm_ns/intenset.rs b/pacs/nrf9120-pac/src/pdm_ns/intenset.rs new file mode 100644 index 00000000..3129adc2 --- /dev/null +++ b/pacs/nrf9120-pac/src/pdm_ns/intenset.rs @@ -0,0 +1,267 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `STARTED` reader - Write '1' to enable interrupt for event STARTED"] +pub type STARTED_R = crate::BitReader; +#[doc = "Write '1' to enable interrupt for event STARTED\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum STARTED_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: STARTED_A) -> Self { + variant as u8 != 0 + } +} +impl STARTED_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> STARTED_A { + match self.bits { + false => STARTED_A::DISABLED, + true => STARTED_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == STARTED_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == STARTED_A::ENABLED + } +} +#[doc = "Write '1' to enable interrupt for event STARTED\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum STARTED_AW { + #[doc = "1: Enable"] + SET = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: STARTED_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `STARTED` writer - Write '1' to enable interrupt for event STARTED"] +pub type STARTED_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENSET_SPEC, STARTED_AW, O>; +impl<'a, const O: u8> STARTED_W<'a, O> { + #[doc = "Enable"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(STARTED_AW::SET) + } +} +#[doc = "Field `STOPPED` reader - Write '1' to enable interrupt for event STOPPED"] +pub type STOPPED_R = crate::BitReader; +#[doc = "Write '1' to enable interrupt for event STOPPED\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum STOPPED_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: STOPPED_A) -> Self { + variant as u8 != 0 + } +} +impl STOPPED_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> STOPPED_A { + match self.bits { + false => STOPPED_A::DISABLED, + true => STOPPED_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == STOPPED_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == STOPPED_A::ENABLED + } +} +#[doc = "Write '1' to enable interrupt for event STOPPED\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum STOPPED_AW { + #[doc = "1: Enable"] + SET = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: STOPPED_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `STOPPED` writer - Write '1' to enable interrupt for event STOPPED"] +pub type STOPPED_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENSET_SPEC, STOPPED_AW, O>; +impl<'a, const O: u8> STOPPED_W<'a, O> { + #[doc = "Enable"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(STOPPED_AW::SET) + } +} +#[doc = "Field `END` reader - Write '1' to enable interrupt for event END"] +pub type END_R = crate::BitReader; +#[doc = "Write '1' to enable interrupt for event END\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum END_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: END_A) -> Self { + variant as u8 != 0 + } +} +impl END_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> END_A { + match self.bits { + false => END_A::DISABLED, + true => END_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == END_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == END_A::ENABLED + } +} +#[doc = "Write '1' to enable interrupt for event END\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum END_AW { + #[doc = "1: Enable"] + SET = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: END_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `END` writer - Write '1' to enable interrupt for event END"] +pub type END_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENSET_SPEC, END_AW, O>; +impl<'a, const O: u8> END_W<'a, O> { + #[doc = "Enable"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(END_AW::SET) + } +} +impl R { + #[doc = "Bit 0 - Write '1' to enable interrupt for event STARTED"] + #[inline(always)] + pub fn started(&self) -> STARTED_R { + STARTED_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Write '1' to enable interrupt for event STOPPED"] + #[inline(always)] + pub fn stopped(&self) -> STOPPED_R { + STOPPED_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Write '1' to enable interrupt for event END"] + #[inline(always)] + pub fn end(&self) -> END_R { + END_R::new(((self.bits >> 2) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Write '1' to enable interrupt for event STARTED"] + #[inline(always)] + pub fn started(&mut self) -> STARTED_W<0> { + STARTED_W::new(self) + } + #[doc = "Bit 1 - Write '1' to enable interrupt for event STOPPED"] + #[inline(always)] + pub fn stopped(&mut self) -> STOPPED_W<1> { + STOPPED_W::new(self) + } + #[doc = "Bit 2 - Write '1' to enable interrupt for event END"] + #[inline(always)] + pub fn end(&mut self) -> END_W<2> { + END_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Enable interrupt\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/pdm_ns/mode.rs b/pacs/nrf9120-pac/src/pdm_ns/mode.rs new file mode 100644 index 00000000..38bc70e7 --- /dev/null +++ b/pacs/nrf9120-pac/src/pdm_ns/mode.rs @@ -0,0 +1,186 @@ +#[doc = "Register `MODE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `MODE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `OPERATION` reader - Mono or stereo operation"] +pub type OPERATION_R = crate::BitReader; +#[doc = "Mono or stereo operation\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum OPERATION_A { + #[doc = "0: Sample and store one pair (left + right) of 16-bit samples per RAM word R=\\[31:16\\]; L=\\[15:0\\]"] + STEREO = 0, + #[doc = "1: Sample and store two successive left samples (16 bits each) per RAM word L1=\\[31:16\\]; L0=\\[15:0\\]"] + MONO = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: OPERATION_A) -> Self { + variant as u8 != 0 + } +} +impl OPERATION_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> OPERATION_A { + match self.bits { + false => OPERATION_A::STEREO, + true => OPERATION_A::MONO, + } + } + #[doc = "Checks if the value of the field is `STEREO`"] + #[inline(always)] + pub fn is_stereo(&self) -> bool { + *self == OPERATION_A::STEREO + } + #[doc = "Checks if the value of the field is `MONO`"] + #[inline(always)] + pub fn is_mono(&self) -> bool { + *self == OPERATION_A::MONO + } +} +#[doc = "Field `OPERATION` writer - Mono or stereo operation"] +pub type OPERATION_W<'a, const O: u8> = crate::BitWriter<'a, u32, MODE_SPEC, OPERATION_A, O>; +impl<'a, const O: u8> OPERATION_W<'a, O> { + #[doc = "Sample and store one pair (left + right) of 16-bit samples per RAM word R=\\[31:16\\]; L=\\[15:0\\]"] + #[inline(always)] + pub fn stereo(self) -> &'a mut W { + self.variant(OPERATION_A::STEREO) + } + #[doc = "Sample and store two successive left samples (16 bits each) per RAM word L1=\\[31:16\\]; L0=\\[15:0\\]"] + #[inline(always)] + pub fn mono(self) -> &'a mut W { + self.variant(OPERATION_A::MONO) + } +} +#[doc = "Field `EDGE` reader - Defines on which PDM_CLK edge left (or mono) is sampled"] +pub type EDGE_R = crate::BitReader; +#[doc = "Defines on which PDM_CLK edge left (or mono) is sampled\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum EDGE_A { + #[doc = "0: Left (or mono) is sampled on falling edge of PDM_CLK"] + LEFT_FALLING = 0, + #[doc = "1: Left (or mono) is sampled on rising edge of PDM_CLK"] + LEFT_RISING = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: EDGE_A) -> Self { + variant as u8 != 0 + } +} +impl EDGE_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EDGE_A { + match self.bits { + false => EDGE_A::LEFT_FALLING, + true => EDGE_A::LEFT_RISING, + } + } + #[doc = "Checks if the value of the field is `LEFT_FALLING`"] + #[inline(always)] + pub fn is_left_falling(&self) -> bool { + *self == EDGE_A::LEFT_FALLING + } + #[doc = "Checks if the value of the field is `LEFT_RISING`"] + #[inline(always)] + pub fn is_left_rising(&self) -> bool { + *self == EDGE_A::LEFT_RISING + } +} +#[doc = "Field `EDGE` writer - Defines on which PDM_CLK edge left (or mono) is sampled"] +pub type EDGE_W<'a, const O: u8> = crate::BitWriter<'a, u32, MODE_SPEC, EDGE_A, O>; +impl<'a, const O: u8> EDGE_W<'a, O> { + #[doc = "Left (or mono) is sampled on falling edge of PDM_CLK"] + #[inline(always)] + pub fn left_falling(self) -> &'a mut W { + self.variant(EDGE_A::LEFT_FALLING) + } + #[doc = "Left (or mono) is sampled on rising edge of PDM_CLK"] + #[inline(always)] + pub fn left_rising(self) -> &'a mut W { + self.variant(EDGE_A::LEFT_RISING) + } +} +impl R { + #[doc = "Bit 0 - Mono or stereo operation"] + #[inline(always)] + pub fn operation(&self) -> OPERATION_R { + OPERATION_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Defines on which PDM_CLK edge left (or mono) is sampled"] + #[inline(always)] + pub fn edge(&self) -> EDGE_R { + EDGE_R::new(((self.bits >> 1) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Mono or stereo operation"] + #[inline(always)] + pub fn operation(&mut self) -> OPERATION_W<0> { + OPERATION_W::new(self) + } + #[doc = "Bit 1 - Defines on which PDM_CLK edge left (or mono) is sampled"] + #[inline(always)] + pub fn edge(&mut self) -> EDGE_W<1> { + EDGE_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Defines the routing of the connected PDM microphones' signals\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [mode](index.html) module"] +pub struct MODE_SPEC; +impl crate::RegisterSpec for MODE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [mode::R](R) reader structure"] +impl crate::Readable for MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [mode::W](W) writer structure"] +impl crate::Writable for MODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets MODE to value 0"] +impl crate::Resettable for MODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/pdm_ns/pdmclkctrl.rs b/pacs/nrf9120-pac/src/pdm_ns/pdmclkctrl.rs new file mode 100644 index 00000000..5066c469 --- /dev/null +++ b/pacs/nrf9120-pac/src/pdm_ns/pdmclkctrl.rs @@ -0,0 +1,180 @@ +#[doc = "Register `PDMCLKCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PDMCLKCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `FREQ` reader - PDM_CLK frequency configuration."] +pub type FREQ_R = crate::FieldReader; +#[doc = "PDM_CLK frequency configuration.\n\nValue on reset: 138412032"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u32)] +pub enum FREQ_A { + #[doc = "134217728: PDM_CLK = 32 MHz / 32 = 1.000 MHz"] + _1000K = 134217728, + #[doc = "138412032: PDM_CLK = 32 MHz / 31 = 1.032 MHz. Nominal clock for RATIO=Ratio64."] + DEFAULT = 138412032, + #[doc = "142606336: PDM_CLK = 32 MHz / 30 = 1.067 MHz"] + _1067K = 142606336, + #[doc = "159383552: PDM_CLK = 32 MHz / 26 = 1.231 MHz"] + _1231K = 159383552, + #[doc = "167772160: PDM_CLK = 32 MHz / 25 = 1.280 MHz. Nominal clock for RATIO=Ratio80."] + _1280K = 167772160, + #[doc = "176160768: PDM_CLK = 32 MHz / 24 = 1.333 MHz"] + _1333K = 176160768, +} +impl From for u32 { + #[inline(always)] + fn from(variant: FREQ_A) -> Self { + variant as _ + } +} +impl FREQ_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 134217728 => Some(FREQ_A::_1000K), + 138412032 => Some(FREQ_A::DEFAULT), + 142606336 => Some(FREQ_A::_1067K), + 159383552 => Some(FREQ_A::_1231K), + 167772160 => Some(FREQ_A::_1280K), + 176160768 => Some(FREQ_A::_1333K), + _ => None, + } + } + #[doc = "Checks if the value of the field is `_1000K`"] + #[inline(always)] + pub fn is_1000k(&self) -> bool { + *self == FREQ_A::_1000K + } + #[doc = "Checks if the value of the field is `DEFAULT`"] + #[inline(always)] + pub fn is_default(&self) -> bool { + *self == FREQ_A::DEFAULT + } + #[doc = "Checks if the value of the field is `_1067K`"] + #[inline(always)] + pub fn is_1067k(&self) -> bool { + *self == FREQ_A::_1067K + } + #[doc = "Checks if the value of the field is `_1231K`"] + #[inline(always)] + pub fn is_1231k(&self) -> bool { + *self == FREQ_A::_1231K + } + #[doc = "Checks if the value of the field is `_1280K`"] + #[inline(always)] + pub fn is_1280k(&self) -> bool { + *self == FREQ_A::_1280K + } + #[doc = "Checks if the value of the field is `_1333K`"] + #[inline(always)] + pub fn is_1333k(&self) -> bool { + *self == FREQ_A::_1333K + } +} +#[doc = "Field `FREQ` writer - PDM_CLK frequency configuration."] +pub type FREQ_W<'a, const O: u8> = crate::FieldWriter<'a, u32, PDMCLKCTRL_SPEC, u32, FREQ_A, 32, O>; +impl<'a, const O: u8> FREQ_W<'a, O> { + #[doc = "PDM_CLK = 32 MHz / 32 = 1.000 MHz"] + #[inline(always)] + pub fn _1000k(self) -> &'a mut W { + self.variant(FREQ_A::_1000K) + } + #[doc = "PDM_CLK = 32 MHz / 31 = 1.032 MHz. Nominal clock for RATIO=Ratio64."] + #[inline(always)] + pub fn default(self) -> &'a mut W { + self.variant(FREQ_A::DEFAULT) + } + #[doc = "PDM_CLK = 32 MHz / 30 = 1.067 MHz"] + #[inline(always)] + pub fn _1067k(self) -> &'a mut W { + self.variant(FREQ_A::_1067K) + } + #[doc = "PDM_CLK = 32 MHz / 26 = 1.231 MHz"] + #[inline(always)] + pub fn _1231k(self) -> &'a mut W { + self.variant(FREQ_A::_1231K) + } + #[doc = "PDM_CLK = 32 MHz / 25 = 1.280 MHz. Nominal clock for RATIO=Ratio80."] + #[inline(always)] + pub fn _1280k(self) -> &'a mut W { + self.variant(FREQ_A::_1280K) + } + #[doc = "PDM_CLK = 32 MHz / 24 = 1.333 MHz"] + #[inline(always)] + pub fn _1333k(self) -> &'a mut W { + self.variant(FREQ_A::_1333K) + } +} +impl R { + #[doc = "Bits 0:31 - PDM_CLK frequency configuration."] + #[inline(always)] + pub fn freq(&self) -> FREQ_R { + FREQ_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - PDM_CLK frequency configuration."] + #[inline(always)] + pub fn freq(&mut self) -> FREQ_W<0> { + FREQ_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "PDM clock generator control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pdmclkctrl](index.html) module"] +pub struct PDMCLKCTRL_SPEC; +impl crate::RegisterSpec for PDMCLKCTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pdmclkctrl::R](R) reader structure"] +impl crate::Readable for PDMCLKCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [pdmclkctrl::W](W) writer structure"] +impl crate::Writable for PDMCLKCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PDMCLKCTRL to value 0x0840_0000"] +impl crate::Resettable for PDMCLKCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x0840_0000 + } +} diff --git a/pacs/nrf9120-pac/src/pdm_ns/psel.rs b/pacs/nrf9120-pac/src/pdm_ns/psel.rs new file mode 100644 index 00000000..c471ca08 --- /dev/null +++ b/pacs/nrf9120-pac/src/pdm_ns/psel.rs @@ -0,0 +1,16 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct PSEL { + #[doc = "0x00 - Pin number configuration for PDM CLK signal"] + pub clk: CLK, + #[doc = "0x04 - Pin number configuration for PDM DIN signal"] + pub din: DIN, +} +#[doc = "CLK (rw) register accessor: an alias for `Reg`"] +pub type CLK = crate::Reg; +#[doc = "Pin number configuration for PDM CLK signal"] +pub mod clk; +#[doc = "DIN (rw) register accessor: an alias for `Reg`"] +pub type DIN = crate::Reg; +#[doc = "Pin number configuration for PDM DIN signal"] +pub mod din; diff --git a/pacs/nrf9120-pac/src/pdm_ns/psel/clk.rs b/pacs/nrf9120-pac/src/pdm_ns/psel/clk.rs new file mode 100644 index 00000000..03741007 --- /dev/null +++ b/pacs/nrf9120-pac/src/pdm_ns/psel/clk.rs @@ -0,0 +1,140 @@ +#[doc = "Register `CLK` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CLK` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PIN` reader - Pin number"] +pub type PIN_R = crate::FieldReader; +#[doc = "Field `PIN` writer - Pin number"] +pub type PIN_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CLK_SPEC, u8, u8, 5, O>; +#[doc = "Field `CONNECT` reader - Connection"] +pub type CONNECT_R = crate::BitReader; +#[doc = "Connection\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CONNECT_A { + #[doc = "1: Disconnect"] + DISCONNECTED = 1, + #[doc = "0: Connect"] + CONNECTED = 0, +} +impl From for bool { + #[inline(always)] + fn from(variant: CONNECT_A) -> Self { + variant as u8 != 0 + } +} +impl CONNECT_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CONNECT_A { + match self.bits { + true => CONNECT_A::DISCONNECTED, + false => CONNECT_A::CONNECTED, + } + } + #[doc = "Checks if the value of the field is `DISCONNECTED`"] + #[inline(always)] + pub fn is_disconnected(&self) -> bool { + *self == CONNECT_A::DISCONNECTED + } + #[doc = "Checks if the value of the field is `CONNECTED`"] + #[inline(always)] + pub fn is_connected(&self) -> bool { + *self == CONNECT_A::CONNECTED + } +} +#[doc = "Field `CONNECT` writer - Connection"] +pub type CONNECT_W<'a, const O: u8> = crate::BitWriter<'a, u32, CLK_SPEC, CONNECT_A, O>; +impl<'a, const O: u8> CONNECT_W<'a, O> { + #[doc = "Disconnect"] + #[inline(always)] + pub fn disconnected(self) -> &'a mut W { + self.variant(CONNECT_A::DISCONNECTED) + } + #[doc = "Connect"] + #[inline(always)] + pub fn connected(self) -> &'a mut W { + self.variant(CONNECT_A::CONNECTED) + } +} +impl R { + #[doc = "Bits 0:4 - Pin number"] + #[inline(always)] + pub fn pin(&self) -> PIN_R { + PIN_R::new((self.bits & 0x1f) as u8) + } + #[doc = "Bit 31 - Connection"] + #[inline(always)] + pub fn connect(&self) -> CONNECT_R { + CONNECT_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:4 - Pin number"] + #[inline(always)] + pub fn pin(&mut self) -> PIN_W<0> { + PIN_W::new(self) + } + #[doc = "Bit 31 - Connection"] + #[inline(always)] + pub fn connect(&mut self) -> CONNECT_W<31> { + CONNECT_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Pin number configuration for PDM CLK signal\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [clk](index.html) module"] +pub struct CLK_SPEC; +impl crate::RegisterSpec for CLK_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [clk::R](R) reader structure"] +impl crate::Readable for CLK_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [clk::W](W) writer structure"] +impl crate::Writable for CLK_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CLK to value 0xffff_ffff"] +impl crate::Resettable for CLK_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0xffff_ffff + } +} diff --git a/pacs/nrf9120-pac/src/pdm_ns/psel/din.rs b/pacs/nrf9120-pac/src/pdm_ns/psel/din.rs new file mode 100644 index 00000000..82c6d492 --- /dev/null +++ b/pacs/nrf9120-pac/src/pdm_ns/psel/din.rs @@ -0,0 +1,140 @@ +#[doc = "Register `DIN` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DIN` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PIN` reader - Pin number"] +pub type PIN_R = crate::FieldReader; +#[doc = "Field `PIN` writer - Pin number"] +pub type PIN_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DIN_SPEC, u8, u8, 5, O>; +#[doc = "Field `CONNECT` reader - Connection"] +pub type CONNECT_R = crate::BitReader; +#[doc = "Connection\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CONNECT_A { + #[doc = "1: Disconnect"] + DISCONNECTED = 1, + #[doc = "0: Connect"] + CONNECTED = 0, +} +impl From for bool { + #[inline(always)] + fn from(variant: CONNECT_A) -> Self { + variant as u8 != 0 + } +} +impl CONNECT_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CONNECT_A { + match self.bits { + true => CONNECT_A::DISCONNECTED, + false => CONNECT_A::CONNECTED, + } + } + #[doc = "Checks if the value of the field is `DISCONNECTED`"] + #[inline(always)] + pub fn is_disconnected(&self) -> bool { + *self == CONNECT_A::DISCONNECTED + } + #[doc = "Checks if the value of the field is `CONNECTED`"] + #[inline(always)] + pub fn is_connected(&self) -> bool { + *self == CONNECT_A::CONNECTED + } +} +#[doc = "Field `CONNECT` writer - Connection"] +pub type CONNECT_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIN_SPEC, CONNECT_A, O>; +impl<'a, const O: u8> CONNECT_W<'a, O> { + #[doc = "Disconnect"] + #[inline(always)] + pub fn disconnected(self) -> &'a mut W { + self.variant(CONNECT_A::DISCONNECTED) + } + #[doc = "Connect"] + #[inline(always)] + pub fn connected(self) -> &'a mut W { + self.variant(CONNECT_A::CONNECTED) + } +} +impl R { + #[doc = "Bits 0:4 - Pin number"] + #[inline(always)] + pub fn pin(&self) -> PIN_R { + PIN_R::new((self.bits & 0x1f) as u8) + } + #[doc = "Bit 31 - Connection"] + #[inline(always)] + pub fn connect(&self) -> CONNECT_R { + CONNECT_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:4 - Pin number"] + #[inline(always)] + pub fn pin(&mut self) -> PIN_W<0> { + PIN_W::new(self) + } + #[doc = "Bit 31 - Connection"] + #[inline(always)] + pub fn connect(&mut self) -> CONNECT_W<31> { + CONNECT_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Pin number configuration for PDM DIN signal\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [din](index.html) module"] +pub struct DIN_SPEC; +impl crate::RegisterSpec for DIN_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [din::R](R) reader structure"] +impl crate::Readable for DIN_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [din::W](W) writer structure"] +impl crate::Writable for DIN_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DIN to value 0xffff_ffff"] +impl crate::Resettable for DIN_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0xffff_ffff + } +} diff --git a/pacs/nrf9120-pac/src/pdm_ns/publish_end.rs b/pacs/nrf9120-pac/src/pdm_ns/publish_end.rs new file mode 100644 index 00000000..2006d5cf --- /dev/null +++ b/pacs/nrf9120-pac/src/pdm_ns/publish_end.rs @@ -0,0 +1,140 @@ +#[doc = "Register `PUBLISH_END` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PUBLISH_END` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CHIDX` reader - DPPI channel that event END will publish to"] +pub type CHIDX_R = crate::FieldReader; +#[doc = "Field `CHIDX` writer - DPPI channel that event END will publish to"] +pub type CHIDX_W<'a, const O: u8> = crate::FieldWriter<'a, u32, PUBLISH_END_SPEC, u8, u8, 8, O>; +#[doc = "Field `EN` reader - "] +pub type EN_R = crate::BitReader; +#[doc = "\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum EN_A { + #[doc = "0: Disable publishing"] + DISABLED = 0, + #[doc = "1: Enable publishing"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: EN_A) -> Self { + variant as u8 != 0 + } +} +impl EN_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EN_A { + match self.bits { + false => EN_A::DISABLED, + true => EN_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == EN_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == EN_A::ENABLED + } +} +#[doc = "Field `EN` writer - "] +pub type EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, PUBLISH_END_SPEC, EN_A, O>; +impl<'a, const O: u8> EN_W<'a, O> { + #[doc = "Disable publishing"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(EN_A::DISABLED) + } + #[doc = "Enable publishing"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(EN_A::ENABLED) + } +} +impl R { + #[doc = "Bits 0:7 - DPPI channel that event END will publish to"] + #[inline(always)] + pub fn chidx(&self) -> CHIDX_R { + CHIDX_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&self) -> EN_R { + EN_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:7 - DPPI channel that event END will publish to"] + #[inline(always)] + pub fn chidx(&mut self) -> CHIDX_W<0> { + CHIDX_W::new(self) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&mut self) -> EN_W<31> { + EN_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Publish configuration for event END\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [publish_end](index.html) module"] +pub struct PUBLISH_END_SPEC; +impl crate::RegisterSpec for PUBLISH_END_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [publish_end::R](R) reader structure"] +impl crate::Readable for PUBLISH_END_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [publish_end::W](W) writer structure"] +impl crate::Writable for PUBLISH_END_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PUBLISH_END to value 0"] +impl crate::Resettable for PUBLISH_END_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/pdm_ns/publish_started.rs b/pacs/nrf9120-pac/src/pdm_ns/publish_started.rs new file mode 100644 index 00000000..1b0354ef --- /dev/null +++ b/pacs/nrf9120-pac/src/pdm_ns/publish_started.rs @@ -0,0 +1,140 @@ +#[doc = "Register `PUBLISH_STARTED` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PUBLISH_STARTED` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CHIDX` reader - DPPI channel that event STARTED will publish to"] +pub type CHIDX_R = crate::FieldReader; +#[doc = "Field `CHIDX` writer - DPPI channel that event STARTED will publish to"] +pub type CHIDX_W<'a, const O: u8> = crate::FieldWriter<'a, u32, PUBLISH_STARTED_SPEC, u8, u8, 8, O>; +#[doc = "Field `EN` reader - "] +pub type EN_R = crate::BitReader; +#[doc = "\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum EN_A { + #[doc = "0: Disable publishing"] + DISABLED = 0, + #[doc = "1: Enable publishing"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: EN_A) -> Self { + variant as u8 != 0 + } +} +impl EN_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EN_A { + match self.bits { + false => EN_A::DISABLED, + true => EN_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == EN_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == EN_A::ENABLED + } +} +#[doc = "Field `EN` writer - "] +pub type EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, PUBLISH_STARTED_SPEC, EN_A, O>; +impl<'a, const O: u8> EN_W<'a, O> { + #[doc = "Disable publishing"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(EN_A::DISABLED) + } + #[doc = "Enable publishing"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(EN_A::ENABLED) + } +} +impl R { + #[doc = "Bits 0:7 - DPPI channel that event STARTED will publish to"] + #[inline(always)] + pub fn chidx(&self) -> CHIDX_R { + CHIDX_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&self) -> EN_R { + EN_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:7 - DPPI channel that event STARTED will publish to"] + #[inline(always)] + pub fn chidx(&mut self) -> CHIDX_W<0> { + CHIDX_W::new(self) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&mut self) -> EN_W<31> { + EN_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Publish configuration for event STARTED\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [publish_started](index.html) module"] +pub struct PUBLISH_STARTED_SPEC; +impl crate::RegisterSpec for PUBLISH_STARTED_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [publish_started::R](R) reader structure"] +impl crate::Readable for PUBLISH_STARTED_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [publish_started::W](W) writer structure"] +impl crate::Writable for PUBLISH_STARTED_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PUBLISH_STARTED to value 0"] +impl crate::Resettable for PUBLISH_STARTED_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/pdm_ns/publish_stopped.rs b/pacs/nrf9120-pac/src/pdm_ns/publish_stopped.rs new file mode 100644 index 00000000..247f50bf --- /dev/null +++ b/pacs/nrf9120-pac/src/pdm_ns/publish_stopped.rs @@ -0,0 +1,140 @@ +#[doc = "Register `PUBLISH_STOPPED` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PUBLISH_STOPPED` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CHIDX` reader - DPPI channel that event STOPPED will publish to"] +pub type CHIDX_R = crate::FieldReader; +#[doc = "Field `CHIDX` writer - DPPI channel that event STOPPED will publish to"] +pub type CHIDX_W<'a, const O: u8> = crate::FieldWriter<'a, u32, PUBLISH_STOPPED_SPEC, u8, u8, 8, O>; +#[doc = "Field `EN` reader - "] +pub type EN_R = crate::BitReader; +#[doc = "\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum EN_A { + #[doc = "0: Disable publishing"] + DISABLED = 0, + #[doc = "1: Enable publishing"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: EN_A) -> Self { + variant as u8 != 0 + } +} +impl EN_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EN_A { + match self.bits { + false => EN_A::DISABLED, + true => EN_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == EN_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == EN_A::ENABLED + } +} +#[doc = "Field `EN` writer - "] +pub type EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, PUBLISH_STOPPED_SPEC, EN_A, O>; +impl<'a, const O: u8> EN_W<'a, O> { + #[doc = "Disable publishing"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(EN_A::DISABLED) + } + #[doc = "Enable publishing"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(EN_A::ENABLED) + } +} +impl R { + #[doc = "Bits 0:7 - DPPI channel that event STOPPED will publish to"] + #[inline(always)] + pub fn chidx(&self) -> CHIDX_R { + CHIDX_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&self) -> EN_R { + EN_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:7 - DPPI channel that event STOPPED will publish to"] + #[inline(always)] + pub fn chidx(&mut self) -> CHIDX_W<0> { + CHIDX_W::new(self) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&mut self) -> EN_W<31> { + EN_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Publish configuration for event STOPPED\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [publish_stopped](index.html) module"] +pub struct PUBLISH_STOPPED_SPEC; +impl crate::RegisterSpec for PUBLISH_STOPPED_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [publish_stopped::R](R) reader structure"] +impl crate::Readable for PUBLISH_STOPPED_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [publish_stopped::W](W) writer structure"] +impl crate::Writable for PUBLISH_STOPPED_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PUBLISH_STOPPED to value 0"] +impl crate::Resettable for PUBLISH_STOPPED_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/pdm_ns/ratio.rs b/pacs/nrf9120-pac/src/pdm_ns/ratio.rs new file mode 100644 index 00000000..dac25867 --- /dev/null +++ b/pacs/nrf9120-pac/src/pdm_ns/ratio.rs @@ -0,0 +1,126 @@ +#[doc = "Register `RATIO` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `RATIO` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `RATIO` reader - Selects the ratio between PDM_CLK and output sample rate"] +pub type RATIO_R = crate::BitReader; +#[doc = "Selects the ratio between PDM_CLK and output sample rate\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RATIO_A { + #[doc = "0: Ratio of 64"] + RATIO64 = 0, + #[doc = "1: Ratio of 80"] + RATIO80 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RATIO_A) -> Self { + variant as u8 != 0 + } +} +impl RATIO_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RATIO_A { + match self.bits { + false => RATIO_A::RATIO64, + true => RATIO_A::RATIO80, + } + } + #[doc = "Checks if the value of the field is `RATIO64`"] + #[inline(always)] + pub fn is_ratio64(&self) -> bool { + *self == RATIO_A::RATIO64 + } + #[doc = "Checks if the value of the field is `RATIO80`"] + #[inline(always)] + pub fn is_ratio80(&self) -> bool { + *self == RATIO_A::RATIO80 + } +} +#[doc = "Field `RATIO` writer - Selects the ratio between PDM_CLK and output sample rate"] +pub type RATIO_W<'a, const O: u8> = crate::BitWriter<'a, u32, RATIO_SPEC, RATIO_A, O>; +impl<'a, const O: u8> RATIO_W<'a, O> { + #[doc = "Ratio of 64"] + #[inline(always)] + pub fn ratio64(self) -> &'a mut W { + self.variant(RATIO_A::RATIO64) + } + #[doc = "Ratio of 80"] + #[inline(always)] + pub fn ratio80(self) -> &'a mut W { + self.variant(RATIO_A::RATIO80) + } +} +impl R { + #[doc = "Bit 0 - Selects the ratio between PDM_CLK and output sample rate"] + #[inline(always)] + pub fn ratio(&self) -> RATIO_R { + RATIO_R::new((self.bits & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Selects the ratio between PDM_CLK and output sample rate"] + #[inline(always)] + pub fn ratio(&mut self) -> RATIO_W<0> { + RATIO_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Selects the ratio between PDM_CLK and output sample rate. Change PDMCLKCTRL accordingly.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ratio](index.html) module"] +pub struct RATIO_SPEC; +impl crate::RegisterSpec for RATIO_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ratio::R](R) reader structure"] +impl crate::Readable for RATIO_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ratio::W](W) writer structure"] +impl crate::Writable for RATIO_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets RATIO to value 0"] +impl crate::Resettable for RATIO_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/pdm_ns/sample.rs b/pacs/nrf9120-pac/src/pdm_ns/sample.rs new file mode 100644 index 00000000..f8bc9563 --- /dev/null +++ b/pacs/nrf9120-pac/src/pdm_ns/sample.rs @@ -0,0 +1,16 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct SAMPLE { + #[doc = "0x00 - RAM address pointer to write samples to with EasyDMA"] + pub ptr: PTR, + #[doc = "0x04 - Number of samples to allocate memory for in EasyDMA mode"] + pub maxcnt: MAXCNT, +} +#[doc = "PTR (rw) register accessor: an alias for `Reg`"] +pub type PTR = crate::Reg; +#[doc = "RAM address pointer to write samples to with EasyDMA"] +pub mod ptr; +#[doc = "MAXCNT (rw) register accessor: an alias for `Reg`"] +pub type MAXCNT = crate::Reg; +#[doc = "Number of samples to allocate memory for in EasyDMA mode"] +pub mod maxcnt; diff --git a/pacs/nrf9120-pac/src/pdm_ns/sample/maxcnt.rs b/pacs/nrf9120-pac/src/pdm_ns/sample/maxcnt.rs new file mode 100644 index 00000000..9f079ab0 --- /dev/null +++ b/pacs/nrf9120-pac/src/pdm_ns/sample/maxcnt.rs @@ -0,0 +1,80 @@ +#[doc = "Register `MAXCNT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `MAXCNT` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BUFFSIZE` reader - Length of DMA RAM allocation in number of samples"] +pub type BUFFSIZE_R = crate::FieldReader; +#[doc = "Field `BUFFSIZE` writer - Length of DMA RAM allocation in number of samples"] +pub type BUFFSIZE_W<'a, const O: u8> = crate::FieldWriter<'a, u32, MAXCNT_SPEC, u16, u16, 15, O>; +impl R { + #[doc = "Bits 0:14 - Length of DMA RAM allocation in number of samples"] + #[inline(always)] + pub fn buffsize(&self) -> BUFFSIZE_R { + BUFFSIZE_R::new((self.bits & 0x7fff) as u16) + } +} +impl W { + #[doc = "Bits 0:14 - Length of DMA RAM allocation in number of samples"] + #[inline(always)] + pub fn buffsize(&mut self) -> BUFFSIZE_W<0> { + BUFFSIZE_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Number of samples to allocate memory for in EasyDMA mode\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [maxcnt](index.html) module"] +pub struct MAXCNT_SPEC; +impl crate::RegisterSpec for MAXCNT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [maxcnt::R](R) reader structure"] +impl crate::Readable for MAXCNT_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [maxcnt::W](W) writer structure"] +impl crate::Writable for MAXCNT_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets MAXCNT to value 0"] +impl crate::Resettable for MAXCNT_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/pdm_ns/sample/ptr.rs b/pacs/nrf9120-pac/src/pdm_ns/sample/ptr.rs new file mode 100644 index 00000000..18583366 --- /dev/null +++ b/pacs/nrf9120-pac/src/pdm_ns/sample/ptr.rs @@ -0,0 +1,80 @@ +#[doc = "Register `PTR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PTR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SAMPLEPTR` reader - Address to write PDM samples to over DMA"] +pub type SAMPLEPTR_R = crate::FieldReader; +#[doc = "Field `SAMPLEPTR` writer - Address to write PDM samples to over DMA"] +pub type SAMPLEPTR_W<'a, const O: u8> = crate::FieldWriter<'a, u32, PTR_SPEC, u32, u32, 32, O>; +impl R { + #[doc = "Bits 0:31 - Address to write PDM samples to over DMA"] + #[inline(always)] + pub fn sampleptr(&self) -> SAMPLEPTR_R { + SAMPLEPTR_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Address to write PDM samples to over DMA"] + #[inline(always)] + pub fn sampleptr(&mut self) -> SAMPLEPTR_W<0> { + SAMPLEPTR_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "RAM address pointer to write samples to with EasyDMA\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ptr](index.html) module"] +pub struct PTR_SPEC; +impl crate::RegisterSpec for PTR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ptr::R](R) reader structure"] +impl crate::Readable for PTR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ptr::W](W) writer structure"] +impl crate::Writable for PTR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PTR to value 0"] +impl crate::Resettable for PTR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/pdm_ns/subscribe_start.rs b/pacs/nrf9120-pac/src/pdm_ns/subscribe_start.rs new file mode 100644 index 00000000..fb9deced --- /dev/null +++ b/pacs/nrf9120-pac/src/pdm_ns/subscribe_start.rs @@ -0,0 +1,140 @@ +#[doc = "Register `SUBSCRIBE_START` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SUBSCRIBE_START` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CHIDX` reader - DPPI channel that task START will subscribe to"] +pub type CHIDX_R = crate::FieldReader; +#[doc = "Field `CHIDX` writer - DPPI channel that task START will subscribe to"] +pub type CHIDX_W<'a, const O: u8> = crate::FieldWriter<'a, u32, SUBSCRIBE_START_SPEC, u8, u8, 8, O>; +#[doc = "Field `EN` reader - "] +pub type EN_R = crate::BitReader; +#[doc = "\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum EN_A { + #[doc = "0: Disable subscription"] + DISABLED = 0, + #[doc = "1: Enable subscription"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: EN_A) -> Self { + variant as u8 != 0 + } +} +impl EN_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EN_A { + match self.bits { + false => EN_A::DISABLED, + true => EN_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == EN_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == EN_A::ENABLED + } +} +#[doc = "Field `EN` writer - "] +pub type EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, SUBSCRIBE_START_SPEC, EN_A, O>; +impl<'a, const O: u8> EN_W<'a, O> { + #[doc = "Disable subscription"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(EN_A::DISABLED) + } + #[doc = "Enable subscription"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(EN_A::ENABLED) + } +} +impl R { + #[doc = "Bits 0:7 - DPPI channel that task START will subscribe to"] + #[inline(always)] + pub fn chidx(&self) -> CHIDX_R { + CHIDX_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&self) -> EN_R { + EN_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:7 - DPPI channel that task START will subscribe to"] + #[inline(always)] + pub fn chidx(&mut self) -> CHIDX_W<0> { + CHIDX_W::new(self) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&mut self) -> EN_W<31> { + EN_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Subscribe configuration for task START\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [subscribe_start](index.html) module"] +pub struct SUBSCRIBE_START_SPEC; +impl crate::RegisterSpec for SUBSCRIBE_START_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [subscribe_start::R](R) reader structure"] +impl crate::Readable for SUBSCRIBE_START_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [subscribe_start::W](W) writer structure"] +impl crate::Writable for SUBSCRIBE_START_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SUBSCRIBE_START to value 0"] +impl crate::Resettable for SUBSCRIBE_START_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/pdm_ns/subscribe_stop.rs b/pacs/nrf9120-pac/src/pdm_ns/subscribe_stop.rs new file mode 100644 index 00000000..2fe3af58 --- /dev/null +++ b/pacs/nrf9120-pac/src/pdm_ns/subscribe_stop.rs @@ -0,0 +1,140 @@ +#[doc = "Register `SUBSCRIBE_STOP` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SUBSCRIBE_STOP` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CHIDX` reader - DPPI channel that task STOP will subscribe to"] +pub type CHIDX_R = crate::FieldReader; +#[doc = "Field `CHIDX` writer - DPPI channel that task STOP will subscribe to"] +pub type CHIDX_W<'a, const O: u8> = crate::FieldWriter<'a, u32, SUBSCRIBE_STOP_SPEC, u8, u8, 8, O>; +#[doc = "Field `EN` reader - "] +pub type EN_R = crate::BitReader; +#[doc = "\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum EN_A { + #[doc = "0: Disable subscription"] + DISABLED = 0, + #[doc = "1: Enable subscription"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: EN_A) -> Self { + variant as u8 != 0 + } +} +impl EN_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EN_A { + match self.bits { + false => EN_A::DISABLED, + true => EN_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == EN_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == EN_A::ENABLED + } +} +#[doc = "Field `EN` writer - "] +pub type EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, SUBSCRIBE_STOP_SPEC, EN_A, O>; +impl<'a, const O: u8> EN_W<'a, O> { + #[doc = "Disable subscription"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(EN_A::DISABLED) + } + #[doc = "Enable subscription"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(EN_A::ENABLED) + } +} +impl R { + #[doc = "Bits 0:7 - DPPI channel that task STOP will subscribe to"] + #[inline(always)] + pub fn chidx(&self) -> CHIDX_R { + CHIDX_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&self) -> EN_R { + EN_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:7 - DPPI channel that task STOP will subscribe to"] + #[inline(always)] + pub fn chidx(&mut self) -> CHIDX_W<0> { + CHIDX_W::new(self) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&mut self) -> EN_W<31> { + EN_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Subscribe configuration for task STOP\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [subscribe_stop](index.html) module"] +pub struct SUBSCRIBE_STOP_SPEC; +impl crate::RegisterSpec for SUBSCRIBE_STOP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [subscribe_stop::R](R) reader structure"] +impl crate::Readable for SUBSCRIBE_STOP_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [subscribe_stop::W](W) writer structure"] +impl crate::Writable for SUBSCRIBE_STOP_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SUBSCRIBE_STOP to value 0"] +impl crate::Resettable for SUBSCRIBE_STOP_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/pdm_ns/tasks_start.rs b/pacs/nrf9120-pac/src/pdm_ns/tasks_start.rs new file mode 100644 index 00000000..f5ea7e3e --- /dev/null +++ b/pacs/nrf9120-pac/src/pdm_ns/tasks_start.rs @@ -0,0 +1,72 @@ +#[doc = "Register `TASKS_START` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Starts continuous PDM transfer\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum TASKS_START_AW { + #[doc = "1: Trigger task"] + TRIGGER = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TASKS_START_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TASKS_START` writer - Starts continuous PDM transfer"] +pub type TASKS_START_W<'a, const O: u8> = + crate::BitWriter<'a, u32, TASKS_START_SPEC, TASKS_START_AW, O>; +impl<'a, const O: u8> TASKS_START_W<'a, O> { + #[doc = "Trigger task"] + #[inline(always)] + pub fn trigger(self) -> &'a mut W { + self.variant(TASKS_START_AW::TRIGGER) + } +} +impl W { + #[doc = "Bit 0 - Starts continuous PDM transfer"] + #[inline(always)] + pub fn tasks_start(&mut self) -> TASKS_START_W<0> { + TASKS_START_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Starts continuous PDM transfer\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tasks_start](index.html) module"] +pub struct TASKS_START_SPEC; +impl crate::RegisterSpec for TASKS_START_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [tasks_start::W](W) writer structure"] +impl crate::Writable for TASKS_START_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets TASKS_START to value 0"] +impl crate::Resettable for TASKS_START_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/pdm_ns/tasks_stop.rs b/pacs/nrf9120-pac/src/pdm_ns/tasks_stop.rs new file mode 100644 index 00000000..a7090fff --- /dev/null +++ b/pacs/nrf9120-pac/src/pdm_ns/tasks_stop.rs @@ -0,0 +1,72 @@ +#[doc = "Register `TASKS_STOP` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Stops PDM transfer\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum TASKS_STOP_AW { + #[doc = "1: Trigger task"] + TRIGGER = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TASKS_STOP_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TASKS_STOP` writer - Stops PDM transfer"] +pub type TASKS_STOP_W<'a, const O: u8> = + crate::BitWriter<'a, u32, TASKS_STOP_SPEC, TASKS_STOP_AW, O>; +impl<'a, const O: u8> TASKS_STOP_W<'a, O> { + #[doc = "Trigger task"] + #[inline(always)] + pub fn trigger(self) -> &'a mut W { + self.variant(TASKS_STOP_AW::TRIGGER) + } +} +impl W { + #[doc = "Bit 0 - Stops PDM transfer"] + #[inline(always)] + pub fn tasks_stop(&mut self) -> TASKS_STOP_W<0> { + TASKS_STOP_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Stops PDM transfer\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tasks_stop](index.html) module"] +pub struct TASKS_STOP_SPEC; +impl crate::RegisterSpec for TASKS_STOP_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [tasks_stop::W](W) writer structure"] +impl crate::Writable for TASKS_STOP_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets TASKS_STOP to value 0"] +impl crate::Resettable for TASKS_STOP_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/power_ns.rs b/pacs/nrf9120-pac/src/power_ns.rs new file mode 100644 index 00000000..a868092a --- /dev/null +++ b/pacs/nrf9120-pac/src/power_ns.rs @@ -0,0 +1,142 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + _reserved0: [u8; 0x70], + #[doc = "0x70 - Request forcing PWM mode in external DC/DC voltage regulator. (Drives FPWM_DCDC pin high or low depending on a setting in UICR)."] + pub tasks_pwmreqstart: TASKS_PWMREQSTART, + #[doc = "0x74 - Stop requesting forcing PWM mode in external DC/DC voltage regulator"] + pub tasks_pwmreqstop: TASKS_PWMREQSTOP, + #[doc = "0x78 - Enable constant latency mode."] + pub tasks_constlat: TASKS_CONSTLAT, + #[doc = "0x7c - Enable low power mode (variable latency)"] + pub tasks_lowpwr: TASKS_LOWPWR, + _reserved4: [u8; 0x70], + #[doc = "0xf0 - Subscribe configuration for task PWMREQSTART"] + pub subscribe_pwmreqstart: SUBSCRIBE_PWMREQSTART, + #[doc = "0xf4 - Subscribe configuration for task PWMREQSTOP"] + pub subscribe_pwmreqstop: SUBSCRIBE_PWMREQSTOP, + #[doc = "0xf8 - Subscribe configuration for task CONSTLAT"] + pub subscribe_constlat: SUBSCRIBE_CONSTLAT, + #[doc = "0xfc - Subscribe configuration for task LOWPWR"] + pub subscribe_lowpwr: SUBSCRIBE_LOWPWR, + _reserved8: [u8; 0x08], + #[doc = "0x108 - Power failure warning"] + pub events_pofwarn: EVENTS_POFWARN, + _reserved9: [u8; 0x08], + #[doc = "0x114 - CPU entered WFI/WFE sleep"] + pub events_sleepenter: EVENTS_SLEEPENTER, + #[doc = "0x118 - CPU exited WFI/WFE sleep"] + pub events_sleepexit: EVENTS_SLEEPEXIT, + _reserved11: [u8; 0x6c], + #[doc = "0x188 - Publish configuration for event POFWARN"] + pub publish_pofwarn: PUBLISH_POFWARN, + _reserved12: [u8; 0x08], + #[doc = "0x194 - Publish configuration for event SLEEPENTER"] + pub publish_sleepenter: PUBLISH_SLEEPENTER, + #[doc = "0x198 - Publish configuration for event SLEEPEXIT"] + pub publish_sleepexit: PUBLISH_SLEEPEXIT, + _reserved14: [u8; 0x0164], + #[doc = "0x300 - Enable or disable interrupt"] + pub inten: INTEN, + #[doc = "0x304 - Enable interrupt"] + pub intenset: INTENSET, + #[doc = "0x308 - Disable interrupt"] + pub intenclr: INTENCLR, + _reserved17: [u8; 0xf4], + #[doc = "0x400 - Reset reason"] + pub resetreas: RESETREAS, + _reserved18: [u8; 0x3c], + #[doc = "0x440 - Modem domain power status"] + pub powerstatus: POWERSTATUS, + _reserved19: [u8; 0xd8], + #[doc = "0x51c..0x524 - Description collection: General purpose retention register"] + pub gpregret: [GPREGRET; 2], + _reserved20: [u8; 0xec], + #[doc = "0x610..0x618 - LTE Modem"] + pub ltemodem: LTEMODEM, +} +#[doc = "TASKS_PWMREQSTART (w) register accessor: an alias for `Reg`"] +pub type TASKS_PWMREQSTART = crate::Reg; +#[doc = "Request forcing PWM mode in external DC/DC voltage regulator. (Drives FPWM_DCDC pin high or low depending on a setting in UICR)."] +pub mod tasks_pwmreqstart; +#[doc = "TASKS_PWMREQSTOP (w) register accessor: an alias for `Reg`"] +pub type TASKS_PWMREQSTOP = crate::Reg; +#[doc = "Stop requesting forcing PWM mode in external DC/DC voltage regulator"] +pub mod tasks_pwmreqstop; +#[doc = "TASKS_CONSTLAT (w) register accessor: an alias for `Reg`"] +pub type TASKS_CONSTLAT = crate::Reg; +#[doc = "Enable constant latency mode."] +pub mod tasks_constlat; +#[doc = "TASKS_LOWPWR (w) register accessor: an alias for `Reg`"] +pub type TASKS_LOWPWR = crate::Reg; +#[doc = "Enable low power mode (variable latency)"] +pub mod tasks_lowpwr; +#[doc = "SUBSCRIBE_PWMREQSTART (rw) register accessor: an alias for `Reg`"] +pub type SUBSCRIBE_PWMREQSTART = crate::Reg; +#[doc = "Subscribe configuration for task PWMREQSTART"] +pub mod subscribe_pwmreqstart; +#[doc = "SUBSCRIBE_PWMREQSTOP (rw) register accessor: an alias for `Reg`"] +pub type SUBSCRIBE_PWMREQSTOP = crate::Reg; +#[doc = "Subscribe configuration for task PWMREQSTOP"] +pub mod subscribe_pwmreqstop; +#[doc = "SUBSCRIBE_CONSTLAT (rw) register accessor: an alias for `Reg`"] +pub type SUBSCRIBE_CONSTLAT = crate::Reg; +#[doc = "Subscribe configuration for task CONSTLAT"] +pub mod subscribe_constlat; +#[doc = "SUBSCRIBE_LOWPWR (rw) register accessor: an alias for `Reg`"] +pub type SUBSCRIBE_LOWPWR = crate::Reg; +#[doc = "Subscribe configuration for task LOWPWR"] +pub mod subscribe_lowpwr; +#[doc = "EVENTS_POFWARN (rw) register accessor: an alias for `Reg`"] +pub type EVENTS_POFWARN = crate::Reg; +#[doc = "Power failure warning"] +pub mod events_pofwarn; +#[doc = "EVENTS_SLEEPENTER (rw) register accessor: an alias for `Reg`"] +pub type EVENTS_SLEEPENTER = crate::Reg; +#[doc = "CPU entered WFI/WFE sleep"] +pub mod events_sleepenter; +#[doc = "EVENTS_SLEEPEXIT (rw) register accessor: an alias for `Reg`"] +pub type EVENTS_SLEEPEXIT = crate::Reg; +#[doc = "CPU exited WFI/WFE sleep"] +pub mod events_sleepexit; +#[doc = "PUBLISH_POFWARN (rw) register accessor: an alias for `Reg`"] +pub type PUBLISH_POFWARN = crate::Reg; +#[doc = "Publish configuration for event POFWARN"] +pub mod publish_pofwarn; +#[doc = "PUBLISH_SLEEPENTER (rw) register accessor: an alias for `Reg`"] +pub type PUBLISH_SLEEPENTER = crate::Reg; +#[doc = "Publish configuration for event SLEEPENTER"] +pub mod publish_sleepenter; +#[doc = "PUBLISH_SLEEPEXIT (rw) register accessor: an alias for `Reg`"] +pub type PUBLISH_SLEEPEXIT = crate::Reg; +#[doc = "Publish configuration for event SLEEPEXIT"] +pub mod publish_sleepexit; +#[doc = "INTEN (rw) register accessor: an alias for `Reg`"] +pub type INTEN = crate::Reg; +#[doc = "Enable or disable interrupt"] +pub mod inten; +#[doc = "INTENSET (rw) register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "Enable interrupt"] +pub mod intenset; +#[doc = "INTENCLR (rw) register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "Disable interrupt"] +pub mod intenclr; +#[doc = "RESETREAS (rw) register accessor: an alias for `Reg`"] +pub type RESETREAS = crate::Reg; +#[doc = "Reset reason"] +pub mod resetreas; +#[doc = "POWERSTATUS (r) register accessor: an alias for `Reg`"] +pub type POWERSTATUS = crate::Reg; +#[doc = "Modem domain power status"] +pub mod powerstatus; +#[doc = "GPREGRET (rw) register accessor: an alias for `Reg`"] +pub type GPREGRET = crate::Reg; +#[doc = "Description collection: General purpose retention register"] +pub mod gpregret; +#[doc = "LTE Modem"] +pub use ltemodem::LTEMODEM; +#[doc = r"Cluster"] +#[doc = "LTE Modem"] +pub mod ltemodem; diff --git a/pacs/nrf9120-pac/src/power_ns/events_pofwarn.rs b/pacs/nrf9120-pac/src/power_ns/events_pofwarn.rs new file mode 100644 index 00000000..c035ae23 --- /dev/null +++ b/pacs/nrf9120-pac/src/power_ns/events_pofwarn.rs @@ -0,0 +1,127 @@ +#[doc = "Register `EVENTS_POFWARN` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVENTS_POFWARN` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `EVENTS_POFWARN` reader - Power failure warning"] +pub type EVENTS_POFWARN_R = crate::BitReader; +#[doc = "Power failure warning\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum EVENTS_POFWARN_A { + #[doc = "0: Event not generated"] + NOT_GENERATED = 0, + #[doc = "1: Event generated"] + GENERATED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: EVENTS_POFWARN_A) -> Self { + variant as u8 != 0 + } +} +impl EVENTS_POFWARN_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EVENTS_POFWARN_A { + match self.bits { + false => EVENTS_POFWARN_A::NOT_GENERATED, + true => EVENTS_POFWARN_A::GENERATED, + } + } + #[doc = "Checks if the value of the field is `NOT_GENERATED`"] + #[inline(always)] + pub fn is_not_generated(&self) -> bool { + *self == EVENTS_POFWARN_A::NOT_GENERATED + } + #[doc = "Checks if the value of the field is `GENERATED`"] + #[inline(always)] + pub fn is_generated(&self) -> bool { + *self == EVENTS_POFWARN_A::GENERATED + } +} +#[doc = "Field `EVENTS_POFWARN` writer - Power failure warning"] +pub type EVENTS_POFWARN_W<'a, const O: u8> = + crate::BitWriter<'a, u32, EVENTS_POFWARN_SPEC, EVENTS_POFWARN_A, O>; +impl<'a, const O: u8> EVENTS_POFWARN_W<'a, O> { + #[doc = "Event not generated"] + #[inline(always)] + pub fn not_generated(self) -> &'a mut W { + self.variant(EVENTS_POFWARN_A::NOT_GENERATED) + } + #[doc = "Event generated"] + #[inline(always)] + pub fn generated(self) -> &'a mut W { + self.variant(EVENTS_POFWARN_A::GENERATED) + } +} +impl R { + #[doc = "Bit 0 - Power failure warning"] + #[inline(always)] + pub fn events_pofwarn(&self) -> EVENTS_POFWARN_R { + EVENTS_POFWARN_R::new((self.bits & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Power failure warning"] + #[inline(always)] + pub fn events_pofwarn(&mut self) -> EVENTS_POFWARN_W<0> { + EVENTS_POFWARN_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Power failure warning\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [events_pofwarn](index.html) module"] +pub struct EVENTS_POFWARN_SPEC; +impl crate::RegisterSpec for EVENTS_POFWARN_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [events_pofwarn::R](R) reader structure"] +impl crate::Readable for EVENTS_POFWARN_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [events_pofwarn::W](W) writer structure"] +impl crate::Writable for EVENTS_POFWARN_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EVENTS_POFWARN to value 0"] +impl crate::Resettable for EVENTS_POFWARN_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/power_ns/events_sleepenter.rs b/pacs/nrf9120-pac/src/power_ns/events_sleepenter.rs new file mode 100644 index 00000000..2d9fe5d3 --- /dev/null +++ b/pacs/nrf9120-pac/src/power_ns/events_sleepenter.rs @@ -0,0 +1,127 @@ +#[doc = "Register `EVENTS_SLEEPENTER` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVENTS_SLEEPENTER` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `EVENTS_SLEEPENTER` reader - CPU entered WFI/WFE sleep"] +pub type EVENTS_SLEEPENTER_R = crate::BitReader; +#[doc = "CPU entered WFI/WFE sleep\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum EVENTS_SLEEPENTER_A { + #[doc = "0: Event not generated"] + NOT_GENERATED = 0, + #[doc = "1: Event generated"] + GENERATED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: EVENTS_SLEEPENTER_A) -> Self { + variant as u8 != 0 + } +} +impl EVENTS_SLEEPENTER_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EVENTS_SLEEPENTER_A { + match self.bits { + false => EVENTS_SLEEPENTER_A::NOT_GENERATED, + true => EVENTS_SLEEPENTER_A::GENERATED, + } + } + #[doc = "Checks if the value of the field is `NOT_GENERATED`"] + #[inline(always)] + pub fn is_not_generated(&self) -> bool { + *self == EVENTS_SLEEPENTER_A::NOT_GENERATED + } + #[doc = "Checks if the value of the field is `GENERATED`"] + #[inline(always)] + pub fn is_generated(&self) -> bool { + *self == EVENTS_SLEEPENTER_A::GENERATED + } +} +#[doc = "Field `EVENTS_SLEEPENTER` writer - CPU entered WFI/WFE sleep"] +pub type EVENTS_SLEEPENTER_W<'a, const O: u8> = + crate::BitWriter<'a, u32, EVENTS_SLEEPENTER_SPEC, EVENTS_SLEEPENTER_A, O>; +impl<'a, const O: u8> EVENTS_SLEEPENTER_W<'a, O> { + #[doc = "Event not generated"] + #[inline(always)] + pub fn not_generated(self) -> &'a mut W { + self.variant(EVENTS_SLEEPENTER_A::NOT_GENERATED) + } + #[doc = "Event generated"] + #[inline(always)] + pub fn generated(self) -> &'a mut W { + self.variant(EVENTS_SLEEPENTER_A::GENERATED) + } +} +impl R { + #[doc = "Bit 0 - CPU entered WFI/WFE sleep"] + #[inline(always)] + pub fn events_sleepenter(&self) -> EVENTS_SLEEPENTER_R { + EVENTS_SLEEPENTER_R::new((self.bits & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - CPU entered WFI/WFE sleep"] + #[inline(always)] + pub fn events_sleepenter(&mut self) -> EVENTS_SLEEPENTER_W<0> { + EVENTS_SLEEPENTER_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "CPU entered WFI/WFE sleep\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [events_sleepenter](index.html) module"] +pub struct EVENTS_SLEEPENTER_SPEC; +impl crate::RegisterSpec for EVENTS_SLEEPENTER_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [events_sleepenter::R](R) reader structure"] +impl crate::Readable for EVENTS_SLEEPENTER_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [events_sleepenter::W](W) writer structure"] +impl crate::Writable for EVENTS_SLEEPENTER_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EVENTS_SLEEPENTER to value 0"] +impl crate::Resettable for EVENTS_SLEEPENTER_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/power_ns/events_sleepexit.rs b/pacs/nrf9120-pac/src/power_ns/events_sleepexit.rs new file mode 100644 index 00000000..bc54cc90 --- /dev/null +++ b/pacs/nrf9120-pac/src/power_ns/events_sleepexit.rs @@ -0,0 +1,127 @@ +#[doc = "Register `EVENTS_SLEEPEXIT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVENTS_SLEEPEXIT` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `EVENTS_SLEEPEXIT` reader - CPU exited WFI/WFE sleep"] +pub type EVENTS_SLEEPEXIT_R = crate::BitReader; +#[doc = "CPU exited WFI/WFE sleep\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum EVENTS_SLEEPEXIT_A { + #[doc = "0: Event not generated"] + NOT_GENERATED = 0, + #[doc = "1: Event generated"] + GENERATED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: EVENTS_SLEEPEXIT_A) -> Self { + variant as u8 != 0 + } +} +impl EVENTS_SLEEPEXIT_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EVENTS_SLEEPEXIT_A { + match self.bits { + false => EVENTS_SLEEPEXIT_A::NOT_GENERATED, + true => EVENTS_SLEEPEXIT_A::GENERATED, + } + } + #[doc = "Checks if the value of the field is `NOT_GENERATED`"] + #[inline(always)] + pub fn is_not_generated(&self) -> bool { + *self == EVENTS_SLEEPEXIT_A::NOT_GENERATED + } + #[doc = "Checks if the value of the field is `GENERATED`"] + #[inline(always)] + pub fn is_generated(&self) -> bool { + *self == EVENTS_SLEEPEXIT_A::GENERATED + } +} +#[doc = "Field `EVENTS_SLEEPEXIT` writer - CPU exited WFI/WFE sleep"] +pub type EVENTS_SLEEPEXIT_W<'a, const O: u8> = + crate::BitWriter<'a, u32, EVENTS_SLEEPEXIT_SPEC, EVENTS_SLEEPEXIT_A, O>; +impl<'a, const O: u8> EVENTS_SLEEPEXIT_W<'a, O> { + #[doc = "Event not generated"] + #[inline(always)] + pub fn not_generated(self) -> &'a mut W { + self.variant(EVENTS_SLEEPEXIT_A::NOT_GENERATED) + } + #[doc = "Event generated"] + #[inline(always)] + pub fn generated(self) -> &'a mut W { + self.variant(EVENTS_SLEEPEXIT_A::GENERATED) + } +} +impl R { + #[doc = "Bit 0 - CPU exited WFI/WFE sleep"] + #[inline(always)] + pub fn events_sleepexit(&self) -> EVENTS_SLEEPEXIT_R { + EVENTS_SLEEPEXIT_R::new((self.bits & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - CPU exited WFI/WFE sleep"] + #[inline(always)] + pub fn events_sleepexit(&mut self) -> EVENTS_SLEEPEXIT_W<0> { + EVENTS_SLEEPEXIT_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "CPU exited WFI/WFE sleep\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [events_sleepexit](index.html) module"] +pub struct EVENTS_SLEEPEXIT_SPEC; +impl crate::RegisterSpec for EVENTS_SLEEPEXIT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [events_sleepexit::R](R) reader structure"] +impl crate::Readable for EVENTS_SLEEPEXIT_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [events_sleepexit::W](W) writer structure"] +impl crate::Writable for EVENTS_SLEEPEXIT_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EVENTS_SLEEPEXIT to value 0"] +impl crate::Resettable for EVENTS_SLEEPEXIT_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/power_ns/gpregret.rs b/pacs/nrf9120-pac/src/power_ns/gpregret.rs new file mode 100644 index 00000000..bb8ea589 --- /dev/null +++ b/pacs/nrf9120-pac/src/power_ns/gpregret.rs @@ -0,0 +1,81 @@ +#[doc = "Register `GPREGRET[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GPREGRET[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `GPREGRET` reader - General purpose retention register"] +pub type GPREGRET_R = crate::FieldReader; +#[doc = "Field `GPREGRET` writer - General purpose retention register"] +pub type GPREGRET_W<'a, const O: u8> = crate::FieldWriter<'a, u32, GPREGRET_SPEC, u8, u8, 8, O>; +impl R { + #[doc = "Bits 0:7 - General purpose retention register"] + #[inline(always)] + pub fn gpregret(&self) -> GPREGRET_R { + GPREGRET_R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - General purpose retention register"] + #[inline(always)] + pub fn gpregret(&mut self) -> GPREGRET_W<0> { + GPREGRET_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Description collection: General purpose retention register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gpregret](index.html) module"] +pub struct GPREGRET_SPEC; +impl crate::RegisterSpec for GPREGRET_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gpregret::R](R) reader structure"] +impl crate::Readable for GPREGRET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gpregret::W](W) writer structure"] +impl crate::Writable for GPREGRET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets GPREGRET[%s] +to value 0"] +impl crate::Resettable for GPREGRET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/power_ns/inten.rs b/pacs/nrf9120-pac/src/power_ns/inten.rs new file mode 100644 index 00000000..47aecef5 --- /dev/null +++ b/pacs/nrf9120-pac/src/power_ns/inten.rs @@ -0,0 +1,246 @@ +#[doc = "Register `INTEN` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTEN` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `POFWARN` reader - Enable or disable interrupt for event POFWARN"] +pub type POFWARN_R = crate::BitReader; +#[doc = "Enable or disable interrupt for event POFWARN\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum POFWARN_A { + #[doc = "0: Disable"] + DISABLED = 0, + #[doc = "1: Enable"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: POFWARN_A) -> Self { + variant as u8 != 0 + } +} +impl POFWARN_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> POFWARN_A { + match self.bits { + false => POFWARN_A::DISABLED, + true => POFWARN_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == POFWARN_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == POFWARN_A::ENABLED + } +} +#[doc = "Field `POFWARN` writer - Enable or disable interrupt for event POFWARN"] +pub type POFWARN_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTEN_SPEC, POFWARN_A, O>; +impl<'a, const O: u8> POFWARN_W<'a, O> { + #[doc = "Disable"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(POFWARN_A::DISABLED) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(POFWARN_A::ENABLED) + } +} +#[doc = "Field `SLEEPENTER` reader - Enable or disable interrupt for event SLEEPENTER"] +pub type SLEEPENTER_R = crate::BitReader; +#[doc = "Enable or disable interrupt for event SLEEPENTER\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum SLEEPENTER_A { + #[doc = "0: Disable"] + DISABLED = 0, + #[doc = "1: Enable"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: SLEEPENTER_A) -> Self { + variant as u8 != 0 + } +} +impl SLEEPENTER_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> SLEEPENTER_A { + match self.bits { + false => SLEEPENTER_A::DISABLED, + true => SLEEPENTER_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == SLEEPENTER_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == SLEEPENTER_A::ENABLED + } +} +#[doc = "Field `SLEEPENTER` writer - Enable or disable interrupt for event SLEEPENTER"] +pub type SLEEPENTER_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTEN_SPEC, SLEEPENTER_A, O>; +impl<'a, const O: u8> SLEEPENTER_W<'a, O> { + #[doc = "Disable"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(SLEEPENTER_A::DISABLED) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(SLEEPENTER_A::ENABLED) + } +} +#[doc = "Field `SLEEPEXIT` reader - Enable or disable interrupt for event SLEEPEXIT"] +pub type SLEEPEXIT_R = crate::BitReader; +#[doc = "Enable or disable interrupt for event SLEEPEXIT\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum SLEEPEXIT_A { + #[doc = "0: Disable"] + DISABLED = 0, + #[doc = "1: Enable"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: SLEEPEXIT_A) -> Self { + variant as u8 != 0 + } +} +impl SLEEPEXIT_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> SLEEPEXIT_A { + match self.bits { + false => SLEEPEXIT_A::DISABLED, + true => SLEEPEXIT_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == SLEEPEXIT_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == SLEEPEXIT_A::ENABLED + } +} +#[doc = "Field `SLEEPEXIT` writer - Enable or disable interrupt for event SLEEPEXIT"] +pub type SLEEPEXIT_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTEN_SPEC, SLEEPEXIT_A, O>; +impl<'a, const O: u8> SLEEPEXIT_W<'a, O> { + #[doc = "Disable"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(SLEEPEXIT_A::DISABLED) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(SLEEPEXIT_A::ENABLED) + } +} +impl R { + #[doc = "Bit 2 - Enable or disable interrupt for event POFWARN"] + #[inline(always)] + pub fn pofwarn(&self) -> POFWARN_R { + POFWARN_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 5 - Enable or disable interrupt for event SLEEPENTER"] + #[inline(always)] + pub fn sleepenter(&self) -> SLEEPENTER_R { + SLEEPENTER_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Enable or disable interrupt for event SLEEPEXIT"] + #[inline(always)] + pub fn sleepexit(&self) -> SLEEPEXIT_R { + SLEEPEXIT_R::new(((self.bits >> 6) & 1) != 0) + } +} +impl W { + #[doc = "Bit 2 - Enable or disable interrupt for event POFWARN"] + #[inline(always)] + pub fn pofwarn(&mut self) -> POFWARN_W<2> { + POFWARN_W::new(self) + } + #[doc = "Bit 5 - Enable or disable interrupt for event SLEEPENTER"] + #[inline(always)] + pub fn sleepenter(&mut self) -> SLEEPENTER_W<5> { + SLEEPENTER_W::new(self) + } + #[doc = "Bit 6 - Enable or disable interrupt for event SLEEPEXIT"] + #[inline(always)] + pub fn sleepexit(&mut self) -> SLEEPEXIT_W<6> { + SLEEPEXIT_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Enable or disable interrupt\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [inten](index.html) module"] +pub struct INTEN_SPEC; +impl crate::RegisterSpec for INTEN_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [inten::R](R) reader structure"] +impl crate::Readable for INTEN_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [inten::W](W) writer structure"] +impl crate::Writable for INTEN_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTEN to value 0"] +impl crate::Resettable for INTEN_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/power_ns/intenclr.rs b/pacs/nrf9120-pac/src/power_ns/intenclr.rs new file mode 100644 index 00000000..41ca6e57 --- /dev/null +++ b/pacs/nrf9120-pac/src/power_ns/intenclr.rs @@ -0,0 +1,267 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `POFWARN` reader - Write '1' to disable interrupt for event POFWARN"] +pub type POFWARN_R = crate::BitReader; +#[doc = "Write '1' to disable interrupt for event POFWARN\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum POFWARN_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: POFWARN_A) -> Self { + variant as u8 != 0 + } +} +impl POFWARN_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> POFWARN_A { + match self.bits { + false => POFWARN_A::DISABLED, + true => POFWARN_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == POFWARN_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == POFWARN_A::ENABLED + } +} +#[doc = "Write '1' to disable interrupt for event POFWARN\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum POFWARN_AW { + #[doc = "1: Disable"] + CLEAR = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: POFWARN_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `POFWARN` writer - Write '1' to disable interrupt for event POFWARN"] +pub type POFWARN_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENCLR_SPEC, POFWARN_AW, O>; +impl<'a, const O: u8> POFWARN_W<'a, O> { + #[doc = "Disable"] + #[inline(always)] + pub fn clear(self) -> &'a mut W { + self.variant(POFWARN_AW::CLEAR) + } +} +#[doc = "Field `SLEEPENTER` reader - Write '1' to disable interrupt for event SLEEPENTER"] +pub type SLEEPENTER_R = crate::BitReader; +#[doc = "Write '1' to disable interrupt for event SLEEPENTER\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum SLEEPENTER_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: SLEEPENTER_A) -> Self { + variant as u8 != 0 + } +} +impl SLEEPENTER_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> SLEEPENTER_A { + match self.bits { + false => SLEEPENTER_A::DISABLED, + true => SLEEPENTER_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == SLEEPENTER_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == SLEEPENTER_A::ENABLED + } +} +#[doc = "Write '1' to disable interrupt for event SLEEPENTER\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum SLEEPENTER_AW { + #[doc = "1: Disable"] + CLEAR = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: SLEEPENTER_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SLEEPENTER` writer - Write '1' to disable interrupt for event SLEEPENTER"] +pub type SLEEPENTER_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENCLR_SPEC, SLEEPENTER_AW, O>; +impl<'a, const O: u8> SLEEPENTER_W<'a, O> { + #[doc = "Disable"] + #[inline(always)] + pub fn clear(self) -> &'a mut W { + self.variant(SLEEPENTER_AW::CLEAR) + } +} +#[doc = "Field `SLEEPEXIT` reader - Write '1' to disable interrupt for event SLEEPEXIT"] +pub type SLEEPEXIT_R = crate::BitReader; +#[doc = "Write '1' to disable interrupt for event SLEEPEXIT\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum SLEEPEXIT_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: SLEEPEXIT_A) -> Self { + variant as u8 != 0 + } +} +impl SLEEPEXIT_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> SLEEPEXIT_A { + match self.bits { + false => SLEEPEXIT_A::DISABLED, + true => SLEEPEXIT_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == SLEEPEXIT_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == SLEEPEXIT_A::ENABLED + } +} +#[doc = "Write '1' to disable interrupt for event SLEEPEXIT\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum SLEEPEXIT_AW { + #[doc = "1: Disable"] + CLEAR = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: SLEEPEXIT_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SLEEPEXIT` writer - Write '1' to disable interrupt for event SLEEPEXIT"] +pub type SLEEPEXIT_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENCLR_SPEC, SLEEPEXIT_AW, O>; +impl<'a, const O: u8> SLEEPEXIT_W<'a, O> { + #[doc = "Disable"] + #[inline(always)] + pub fn clear(self) -> &'a mut W { + self.variant(SLEEPEXIT_AW::CLEAR) + } +} +impl R { + #[doc = "Bit 2 - Write '1' to disable interrupt for event POFWARN"] + #[inline(always)] + pub fn pofwarn(&self) -> POFWARN_R { + POFWARN_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 5 - Write '1' to disable interrupt for event SLEEPENTER"] + #[inline(always)] + pub fn sleepenter(&self) -> SLEEPENTER_R { + SLEEPENTER_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Write '1' to disable interrupt for event SLEEPEXIT"] + #[inline(always)] + pub fn sleepexit(&self) -> SLEEPEXIT_R { + SLEEPEXIT_R::new(((self.bits >> 6) & 1) != 0) + } +} +impl W { + #[doc = "Bit 2 - Write '1' to disable interrupt for event POFWARN"] + #[inline(always)] + pub fn pofwarn(&mut self) -> POFWARN_W<2> { + POFWARN_W::new(self) + } + #[doc = "Bit 5 - Write '1' to disable interrupt for event SLEEPENTER"] + #[inline(always)] + pub fn sleepenter(&mut self) -> SLEEPENTER_W<5> { + SLEEPENTER_W::new(self) + } + #[doc = "Bit 6 - Write '1' to disable interrupt for event SLEEPEXIT"] + #[inline(always)] + pub fn sleepexit(&mut self) -> SLEEPEXIT_W<6> { + SLEEPEXIT_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Disable interrupt\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/power_ns/intenset.rs b/pacs/nrf9120-pac/src/power_ns/intenset.rs new file mode 100644 index 00000000..046a2ea8 --- /dev/null +++ b/pacs/nrf9120-pac/src/power_ns/intenset.rs @@ -0,0 +1,267 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `POFWARN` reader - Write '1' to enable interrupt for event POFWARN"] +pub type POFWARN_R = crate::BitReader; +#[doc = "Write '1' to enable interrupt for event POFWARN\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum POFWARN_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: POFWARN_A) -> Self { + variant as u8 != 0 + } +} +impl POFWARN_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> POFWARN_A { + match self.bits { + false => POFWARN_A::DISABLED, + true => POFWARN_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == POFWARN_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == POFWARN_A::ENABLED + } +} +#[doc = "Write '1' to enable interrupt for event POFWARN\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum POFWARN_AW { + #[doc = "1: Enable"] + SET = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: POFWARN_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `POFWARN` writer - Write '1' to enable interrupt for event POFWARN"] +pub type POFWARN_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENSET_SPEC, POFWARN_AW, O>; +impl<'a, const O: u8> POFWARN_W<'a, O> { + #[doc = "Enable"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(POFWARN_AW::SET) + } +} +#[doc = "Field `SLEEPENTER` reader - Write '1' to enable interrupt for event SLEEPENTER"] +pub type SLEEPENTER_R = crate::BitReader; +#[doc = "Write '1' to enable interrupt for event SLEEPENTER\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum SLEEPENTER_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: SLEEPENTER_A) -> Self { + variant as u8 != 0 + } +} +impl SLEEPENTER_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> SLEEPENTER_A { + match self.bits { + false => SLEEPENTER_A::DISABLED, + true => SLEEPENTER_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == SLEEPENTER_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == SLEEPENTER_A::ENABLED + } +} +#[doc = "Write '1' to enable interrupt for event SLEEPENTER\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum SLEEPENTER_AW { + #[doc = "1: Enable"] + SET = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: SLEEPENTER_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SLEEPENTER` writer - Write '1' to enable interrupt for event SLEEPENTER"] +pub type SLEEPENTER_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENSET_SPEC, SLEEPENTER_AW, O>; +impl<'a, const O: u8> SLEEPENTER_W<'a, O> { + #[doc = "Enable"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(SLEEPENTER_AW::SET) + } +} +#[doc = "Field `SLEEPEXIT` reader - Write '1' to enable interrupt for event SLEEPEXIT"] +pub type SLEEPEXIT_R = crate::BitReader; +#[doc = "Write '1' to enable interrupt for event SLEEPEXIT\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum SLEEPEXIT_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: SLEEPEXIT_A) -> Self { + variant as u8 != 0 + } +} +impl SLEEPEXIT_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> SLEEPEXIT_A { + match self.bits { + false => SLEEPEXIT_A::DISABLED, + true => SLEEPEXIT_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == SLEEPEXIT_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == SLEEPEXIT_A::ENABLED + } +} +#[doc = "Write '1' to enable interrupt for event SLEEPEXIT\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum SLEEPEXIT_AW { + #[doc = "1: Enable"] + SET = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: SLEEPEXIT_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SLEEPEXIT` writer - Write '1' to enable interrupt for event SLEEPEXIT"] +pub type SLEEPEXIT_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENSET_SPEC, SLEEPEXIT_AW, O>; +impl<'a, const O: u8> SLEEPEXIT_W<'a, O> { + #[doc = "Enable"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(SLEEPEXIT_AW::SET) + } +} +impl R { + #[doc = "Bit 2 - Write '1' to enable interrupt for event POFWARN"] + #[inline(always)] + pub fn pofwarn(&self) -> POFWARN_R { + POFWARN_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 5 - Write '1' to enable interrupt for event SLEEPENTER"] + #[inline(always)] + pub fn sleepenter(&self) -> SLEEPENTER_R { + SLEEPENTER_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Write '1' to enable interrupt for event SLEEPEXIT"] + #[inline(always)] + pub fn sleepexit(&self) -> SLEEPEXIT_R { + SLEEPEXIT_R::new(((self.bits >> 6) & 1) != 0) + } +} +impl W { + #[doc = "Bit 2 - Write '1' to enable interrupt for event POFWARN"] + #[inline(always)] + pub fn pofwarn(&mut self) -> POFWARN_W<2> { + POFWARN_W::new(self) + } + #[doc = "Bit 5 - Write '1' to enable interrupt for event SLEEPENTER"] + #[inline(always)] + pub fn sleepenter(&mut self) -> SLEEPENTER_W<5> { + SLEEPENTER_W::new(self) + } + #[doc = "Bit 6 - Write '1' to enable interrupt for event SLEEPEXIT"] + #[inline(always)] + pub fn sleepexit(&mut self) -> SLEEPEXIT_W<6> { + SLEEPEXIT_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Enable interrupt\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/power_ns/ltemodem.rs b/pacs/nrf9120-pac/src/power_ns/ltemodem.rs new file mode 100644 index 00000000..c6c76041 --- /dev/null +++ b/pacs/nrf9120-pac/src/power_ns/ltemodem.rs @@ -0,0 +1,16 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct LTEMODEM { + #[doc = "0x00 - Start LTE modem"] + pub startn: STARTN, + #[doc = "0x04 - Force off LTE modem"] + pub forceoff: FORCEOFF, +} +#[doc = "STARTN (rw) register accessor: an alias for `Reg`"] +pub type STARTN = crate::Reg; +#[doc = "Start LTE modem"] +pub mod startn; +#[doc = "FORCEOFF (rw) register accessor: an alias for `Reg`"] +pub type FORCEOFF = crate::Reg; +#[doc = "Force off LTE modem"] +pub mod forceoff; diff --git a/pacs/nrf9120-pac/src/power_ns/ltemodem/forceoff.rs b/pacs/nrf9120-pac/src/power_ns/ltemodem/forceoff.rs new file mode 100644 index 00000000..9bcfe107 --- /dev/null +++ b/pacs/nrf9120-pac/src/power_ns/ltemodem/forceoff.rs @@ -0,0 +1,126 @@ +#[doc = "Register `FORCEOFF` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `FORCEOFF` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `FORCEOFF` reader - Force off LTE modem"] +pub type FORCEOFF_R = crate::BitReader; +#[doc = "Force off LTE modem\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum FORCEOFF_A { + #[doc = "0: Release force off"] + RELEASE = 0, + #[doc = "1: Hold force off active"] + HOLD = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: FORCEOFF_A) -> Self { + variant as u8 != 0 + } +} +impl FORCEOFF_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> FORCEOFF_A { + match self.bits { + false => FORCEOFF_A::RELEASE, + true => FORCEOFF_A::HOLD, + } + } + #[doc = "Checks if the value of the field is `RELEASE`"] + #[inline(always)] + pub fn is_release(&self) -> bool { + *self == FORCEOFF_A::RELEASE + } + #[doc = "Checks if the value of the field is `HOLD`"] + #[inline(always)] + pub fn is_hold(&self) -> bool { + *self == FORCEOFF_A::HOLD + } +} +#[doc = "Field `FORCEOFF` writer - Force off LTE modem"] +pub type FORCEOFF_W<'a, const O: u8> = crate::BitWriter<'a, u32, FORCEOFF_SPEC, FORCEOFF_A, O>; +impl<'a, const O: u8> FORCEOFF_W<'a, O> { + #[doc = "Release force off"] + #[inline(always)] + pub fn release(self) -> &'a mut W { + self.variant(FORCEOFF_A::RELEASE) + } + #[doc = "Hold force off active"] + #[inline(always)] + pub fn hold(self) -> &'a mut W { + self.variant(FORCEOFF_A::HOLD) + } +} +impl R { + #[doc = "Bit 0 - Force off LTE modem"] + #[inline(always)] + pub fn forceoff(&self) -> FORCEOFF_R { + FORCEOFF_R::new((self.bits & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Force off LTE modem"] + #[inline(always)] + pub fn forceoff(&mut self) -> FORCEOFF_W<0> { + FORCEOFF_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Force off LTE modem\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [forceoff](index.html) module"] +pub struct FORCEOFF_SPEC; +impl crate::RegisterSpec for FORCEOFF_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [forceoff::R](R) reader structure"] +impl crate::Readable for FORCEOFF_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [forceoff::W](W) writer structure"] +impl crate::Writable for FORCEOFF_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets FORCEOFF to value 0"] +impl crate::Resettable for FORCEOFF_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/power_ns/ltemodem/startn.rs b/pacs/nrf9120-pac/src/power_ns/ltemodem/startn.rs new file mode 100644 index 00000000..4d2aad4a --- /dev/null +++ b/pacs/nrf9120-pac/src/power_ns/ltemodem/startn.rs @@ -0,0 +1,126 @@ +#[doc = "Register `STARTN` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `STARTN` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `STARTN` reader - Start LTE modem"] +pub type STARTN_R = crate::BitReader; +#[doc = "Start LTE modem\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum STARTN_A { + #[doc = "0: Start LTE modem"] + START = 0, + #[doc = "1: Hold LTE modem disabled"] + HOLD = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: STARTN_A) -> Self { + variant as u8 != 0 + } +} +impl STARTN_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> STARTN_A { + match self.bits { + false => STARTN_A::START, + true => STARTN_A::HOLD, + } + } + #[doc = "Checks if the value of the field is `START`"] + #[inline(always)] + pub fn is_start(&self) -> bool { + *self == STARTN_A::START + } + #[doc = "Checks if the value of the field is `HOLD`"] + #[inline(always)] + pub fn is_hold(&self) -> bool { + *self == STARTN_A::HOLD + } +} +#[doc = "Field `STARTN` writer - Start LTE modem"] +pub type STARTN_W<'a, const O: u8> = crate::BitWriter<'a, u32, STARTN_SPEC, STARTN_A, O>; +impl<'a, const O: u8> STARTN_W<'a, O> { + #[doc = "Start LTE modem"] + #[inline(always)] + pub fn start(self) -> &'a mut W { + self.variant(STARTN_A::START) + } + #[doc = "Hold LTE modem disabled"] + #[inline(always)] + pub fn hold(self) -> &'a mut W { + self.variant(STARTN_A::HOLD) + } +} +impl R { + #[doc = "Bit 0 - Start LTE modem"] + #[inline(always)] + pub fn startn(&self) -> STARTN_R { + STARTN_R::new((self.bits & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Start LTE modem"] + #[inline(always)] + pub fn startn(&mut self) -> STARTN_W<0> { + STARTN_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Start LTE modem\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [startn](index.html) module"] +pub struct STARTN_SPEC; +impl crate::RegisterSpec for STARTN_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [startn::R](R) reader structure"] +impl crate::Readable for STARTN_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [startn::W](W) writer structure"] +impl crate::Writable for STARTN_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets STARTN to value 0x01"] +impl crate::Resettable for STARTN_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x01 + } +} diff --git a/pacs/nrf9120-pac/src/power_ns/powerstatus.rs b/pacs/nrf9120-pac/src/power_ns/powerstatus.rs new file mode 100644 index 00000000..7fd8ca5a --- /dev/null +++ b/pacs/nrf9120-pac/src/power_ns/powerstatus.rs @@ -0,0 +1,74 @@ +#[doc = "Register `POWERSTATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `LTEMODEM` reader - LTE modem domain status"] +pub type LTEMODEM_R = crate::BitReader; +#[doc = "LTE modem domain status\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum LTEMODEM_A { + #[doc = "0: LTE modem domain is powered off"] + OFF = 0, + #[doc = "1: LTE modem domain is powered on"] + ON = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: LTEMODEM_A) -> Self { + variant as u8 != 0 + } +} +impl LTEMODEM_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> LTEMODEM_A { + match self.bits { + false => LTEMODEM_A::OFF, + true => LTEMODEM_A::ON, + } + } + #[doc = "Checks if the value of the field is `OFF`"] + #[inline(always)] + pub fn is_off(&self) -> bool { + *self == LTEMODEM_A::OFF + } + #[doc = "Checks if the value of the field is `ON`"] + #[inline(always)] + pub fn is_on(&self) -> bool { + *self == LTEMODEM_A::ON + } +} +impl R { + #[doc = "Bit 0 - LTE modem domain status"] + #[inline(always)] + pub fn ltemodem(&self) -> LTEMODEM_R { + LTEMODEM_R::new((self.bits & 1) != 0) + } +} +#[doc = "Modem domain power status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [powerstatus](index.html) module"] +pub struct POWERSTATUS_SPEC; +impl crate::RegisterSpec for POWERSTATUS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [powerstatus::R](R) reader structure"] +impl crate::Readable for POWERSTATUS_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets POWERSTATUS to value 0"] +impl crate::Resettable for POWERSTATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/power_ns/publish_pofwarn.rs b/pacs/nrf9120-pac/src/power_ns/publish_pofwarn.rs new file mode 100644 index 00000000..9cecf6f2 --- /dev/null +++ b/pacs/nrf9120-pac/src/power_ns/publish_pofwarn.rs @@ -0,0 +1,140 @@ +#[doc = "Register `PUBLISH_POFWARN` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PUBLISH_POFWARN` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CHIDX` reader - DPPI channel that event POFWARN will publish to"] +pub type CHIDX_R = crate::FieldReader; +#[doc = "Field `CHIDX` writer - DPPI channel that event POFWARN will publish to"] +pub type CHIDX_W<'a, const O: u8> = crate::FieldWriter<'a, u32, PUBLISH_POFWARN_SPEC, u8, u8, 8, O>; +#[doc = "Field `EN` reader - "] +pub type EN_R = crate::BitReader; +#[doc = "\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum EN_A { + #[doc = "0: Disable publishing"] + DISABLED = 0, + #[doc = "1: Enable publishing"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: EN_A) -> Self { + variant as u8 != 0 + } +} +impl EN_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EN_A { + match self.bits { + false => EN_A::DISABLED, + true => EN_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == EN_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == EN_A::ENABLED + } +} +#[doc = "Field `EN` writer - "] +pub type EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, PUBLISH_POFWARN_SPEC, EN_A, O>; +impl<'a, const O: u8> EN_W<'a, O> { + #[doc = "Disable publishing"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(EN_A::DISABLED) + } + #[doc = "Enable publishing"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(EN_A::ENABLED) + } +} +impl R { + #[doc = "Bits 0:7 - DPPI channel that event POFWARN will publish to"] + #[inline(always)] + pub fn chidx(&self) -> CHIDX_R { + CHIDX_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&self) -> EN_R { + EN_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:7 - DPPI channel that event POFWARN will publish to"] + #[inline(always)] + pub fn chidx(&mut self) -> CHIDX_W<0> { + CHIDX_W::new(self) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&mut self) -> EN_W<31> { + EN_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Publish configuration for event POFWARN\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [publish_pofwarn](index.html) module"] +pub struct PUBLISH_POFWARN_SPEC; +impl crate::RegisterSpec for PUBLISH_POFWARN_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [publish_pofwarn::R](R) reader structure"] +impl crate::Readable for PUBLISH_POFWARN_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [publish_pofwarn::W](W) writer structure"] +impl crate::Writable for PUBLISH_POFWARN_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PUBLISH_POFWARN to value 0"] +impl crate::Resettable for PUBLISH_POFWARN_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/power_ns/publish_sleepenter.rs b/pacs/nrf9120-pac/src/power_ns/publish_sleepenter.rs new file mode 100644 index 00000000..0de7321a --- /dev/null +++ b/pacs/nrf9120-pac/src/power_ns/publish_sleepenter.rs @@ -0,0 +1,141 @@ +#[doc = "Register `PUBLISH_SLEEPENTER` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PUBLISH_SLEEPENTER` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CHIDX` reader - DPPI channel that event SLEEPENTER will publish to"] +pub type CHIDX_R = crate::FieldReader; +#[doc = "Field `CHIDX` writer - DPPI channel that event SLEEPENTER will publish to"] +pub type CHIDX_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, PUBLISH_SLEEPENTER_SPEC, u8, u8, 8, O>; +#[doc = "Field `EN` reader - "] +pub type EN_R = crate::BitReader; +#[doc = "\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum EN_A { + #[doc = "0: Disable publishing"] + DISABLED = 0, + #[doc = "1: Enable publishing"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: EN_A) -> Self { + variant as u8 != 0 + } +} +impl EN_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EN_A { + match self.bits { + false => EN_A::DISABLED, + true => EN_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == EN_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == EN_A::ENABLED + } +} +#[doc = "Field `EN` writer - "] +pub type EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, PUBLISH_SLEEPENTER_SPEC, EN_A, O>; +impl<'a, const O: u8> EN_W<'a, O> { + #[doc = "Disable publishing"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(EN_A::DISABLED) + } + #[doc = "Enable publishing"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(EN_A::ENABLED) + } +} +impl R { + #[doc = "Bits 0:7 - DPPI channel that event SLEEPENTER will publish to"] + #[inline(always)] + pub fn chidx(&self) -> CHIDX_R { + CHIDX_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&self) -> EN_R { + EN_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:7 - DPPI channel that event SLEEPENTER will publish to"] + #[inline(always)] + pub fn chidx(&mut self) -> CHIDX_W<0> { + CHIDX_W::new(self) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&mut self) -> EN_W<31> { + EN_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Publish configuration for event SLEEPENTER\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [publish_sleepenter](index.html) module"] +pub struct PUBLISH_SLEEPENTER_SPEC; +impl crate::RegisterSpec for PUBLISH_SLEEPENTER_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [publish_sleepenter::R](R) reader structure"] +impl crate::Readable for PUBLISH_SLEEPENTER_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [publish_sleepenter::W](W) writer structure"] +impl crate::Writable for PUBLISH_SLEEPENTER_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PUBLISH_SLEEPENTER to value 0"] +impl crate::Resettable for PUBLISH_SLEEPENTER_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/power_ns/publish_sleepexit.rs b/pacs/nrf9120-pac/src/power_ns/publish_sleepexit.rs new file mode 100644 index 00000000..e4afc89d --- /dev/null +++ b/pacs/nrf9120-pac/src/power_ns/publish_sleepexit.rs @@ -0,0 +1,141 @@ +#[doc = "Register `PUBLISH_SLEEPEXIT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PUBLISH_SLEEPEXIT` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CHIDX` reader - DPPI channel that event SLEEPEXIT will publish to"] +pub type CHIDX_R = crate::FieldReader; +#[doc = "Field `CHIDX` writer - DPPI channel that event SLEEPEXIT will publish to"] +pub type CHIDX_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, PUBLISH_SLEEPEXIT_SPEC, u8, u8, 8, O>; +#[doc = "Field `EN` reader - "] +pub type EN_R = crate::BitReader; +#[doc = "\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum EN_A { + #[doc = "0: Disable publishing"] + DISABLED = 0, + #[doc = "1: Enable publishing"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: EN_A) -> Self { + variant as u8 != 0 + } +} +impl EN_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EN_A { + match self.bits { + false => EN_A::DISABLED, + true => EN_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == EN_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == EN_A::ENABLED + } +} +#[doc = "Field `EN` writer - "] +pub type EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, PUBLISH_SLEEPEXIT_SPEC, EN_A, O>; +impl<'a, const O: u8> EN_W<'a, O> { + #[doc = "Disable publishing"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(EN_A::DISABLED) + } + #[doc = "Enable publishing"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(EN_A::ENABLED) + } +} +impl R { + #[doc = "Bits 0:7 - DPPI channel that event SLEEPEXIT will publish to"] + #[inline(always)] + pub fn chidx(&self) -> CHIDX_R { + CHIDX_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&self) -> EN_R { + EN_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:7 - DPPI channel that event SLEEPEXIT will publish to"] + #[inline(always)] + pub fn chidx(&mut self) -> CHIDX_W<0> { + CHIDX_W::new(self) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&mut self) -> EN_W<31> { + EN_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Publish configuration for event SLEEPEXIT\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [publish_sleepexit](index.html) module"] +pub struct PUBLISH_SLEEPEXIT_SPEC; +impl crate::RegisterSpec for PUBLISH_SLEEPEXIT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [publish_sleepexit::R](R) reader structure"] +impl crate::Readable for PUBLISH_SLEEPEXIT_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [publish_sleepexit::W](W) writer structure"] +impl crate::Writable for PUBLISH_SLEEPEXIT_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PUBLISH_SLEEPEXIT to value 0"] +impl crate::Resettable for PUBLISH_SLEEPEXIT_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/power_ns/resetreas.rs b/pacs/nrf9120-pac/src/power_ns/resetreas.rs new file mode 100644 index 00000000..492703c1 --- /dev/null +++ b/pacs/nrf9120-pac/src/power_ns/resetreas.rs @@ -0,0 +1,486 @@ +#[doc = "Register `RESETREAS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `RESETREAS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `RESETPIN` reader - Reset from pin reset detected"] +pub type RESETPIN_R = crate::BitReader; +#[doc = "Reset from pin reset detected\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RESETPIN_A { + #[doc = "0: Not detected"] + NOT_DETECTED = 0, + #[doc = "1: Detected"] + DETECTED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RESETPIN_A) -> Self { + variant as u8 != 0 + } +} +impl RESETPIN_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RESETPIN_A { + match self.bits { + false => RESETPIN_A::NOT_DETECTED, + true => RESETPIN_A::DETECTED, + } + } + #[doc = "Checks if the value of the field is `NOT_DETECTED`"] + #[inline(always)] + pub fn is_not_detected(&self) -> bool { + *self == RESETPIN_A::NOT_DETECTED + } + #[doc = "Checks if the value of the field is `DETECTED`"] + #[inline(always)] + pub fn is_detected(&self) -> bool { + *self == RESETPIN_A::DETECTED + } +} +#[doc = "Field `RESETPIN` writer - Reset from pin reset detected"] +pub type RESETPIN_W<'a, const O: u8> = crate::BitWriter<'a, u32, RESETREAS_SPEC, RESETPIN_A, O>; +impl<'a, const O: u8> RESETPIN_W<'a, O> { + #[doc = "Not detected"] + #[inline(always)] + pub fn not_detected(self) -> &'a mut W { + self.variant(RESETPIN_A::NOT_DETECTED) + } + #[doc = "Detected"] + #[inline(always)] + pub fn detected(self) -> &'a mut W { + self.variant(RESETPIN_A::DETECTED) + } +} +#[doc = "Field `DOG` reader - Reset from global watchdog detected"] +pub type DOG_R = crate::BitReader; +#[doc = "Reset from global watchdog detected\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum DOG_A { + #[doc = "0: Not detected"] + NOT_DETECTED = 0, + #[doc = "1: Detected"] + DETECTED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: DOG_A) -> Self { + variant as u8 != 0 + } +} +impl DOG_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> DOG_A { + match self.bits { + false => DOG_A::NOT_DETECTED, + true => DOG_A::DETECTED, + } + } + #[doc = "Checks if the value of the field is `NOT_DETECTED`"] + #[inline(always)] + pub fn is_not_detected(&self) -> bool { + *self == DOG_A::NOT_DETECTED + } + #[doc = "Checks if the value of the field is `DETECTED`"] + #[inline(always)] + pub fn is_detected(&self) -> bool { + *self == DOG_A::DETECTED + } +} +#[doc = "Field `DOG` writer - Reset from global watchdog detected"] +pub type DOG_W<'a, const O: u8> = crate::BitWriter<'a, u32, RESETREAS_SPEC, DOG_A, O>; +impl<'a, const O: u8> DOG_W<'a, O> { + #[doc = "Not detected"] + #[inline(always)] + pub fn not_detected(self) -> &'a mut W { + self.variant(DOG_A::NOT_DETECTED) + } + #[doc = "Detected"] + #[inline(always)] + pub fn detected(self) -> &'a mut W { + self.variant(DOG_A::DETECTED) + } +} +#[doc = "Field `OFF` reader - Reset due to wakeup from System OFF mode, when wakeup is triggered by DETECT signal from GPIO"] +pub type OFF_R = crate::BitReader; +#[doc = "Reset due to wakeup from System OFF mode, when wakeup is triggered by DETECT signal from GPIO\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum OFF_A { + #[doc = "0: Not detected"] + NOT_DETECTED = 0, + #[doc = "1: Detected"] + DETECTED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: OFF_A) -> Self { + variant as u8 != 0 + } +} +impl OFF_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> OFF_A { + match self.bits { + false => OFF_A::NOT_DETECTED, + true => OFF_A::DETECTED, + } + } + #[doc = "Checks if the value of the field is `NOT_DETECTED`"] + #[inline(always)] + pub fn is_not_detected(&self) -> bool { + *self == OFF_A::NOT_DETECTED + } + #[doc = "Checks if the value of the field is `DETECTED`"] + #[inline(always)] + pub fn is_detected(&self) -> bool { + *self == OFF_A::DETECTED + } +} +#[doc = "Field `OFF` writer - Reset due to wakeup from System OFF mode, when wakeup is triggered by DETECT signal from GPIO"] +pub type OFF_W<'a, const O: u8> = crate::BitWriter<'a, u32, RESETREAS_SPEC, OFF_A, O>; +impl<'a, const O: u8> OFF_W<'a, O> { + #[doc = "Not detected"] + #[inline(always)] + pub fn not_detected(self) -> &'a mut W { + self.variant(OFF_A::NOT_DETECTED) + } + #[doc = "Detected"] + #[inline(always)] + pub fn detected(self) -> &'a mut W { + self.variant(OFF_A::DETECTED) + } +} +#[doc = "Field `DIF` reader - Reset due to wakeup from System OFF mode, when wakeup is triggered by entering debug interface mode"] +pub type DIF_R = crate::BitReader; +#[doc = "Reset due to wakeup from System OFF mode, when wakeup is triggered by entering debug interface mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum DIF_A { + #[doc = "0: Not detected"] + NOT_DETECTED = 0, + #[doc = "1: Detected"] + DETECTED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: DIF_A) -> Self { + variant as u8 != 0 + } +} +impl DIF_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> DIF_A { + match self.bits { + false => DIF_A::NOT_DETECTED, + true => DIF_A::DETECTED, + } + } + #[doc = "Checks if the value of the field is `NOT_DETECTED`"] + #[inline(always)] + pub fn is_not_detected(&self) -> bool { + *self == DIF_A::NOT_DETECTED + } + #[doc = "Checks if the value of the field is `DETECTED`"] + #[inline(always)] + pub fn is_detected(&self) -> bool { + *self == DIF_A::DETECTED + } +} +#[doc = "Field `DIF` writer - Reset due to wakeup from System OFF mode, when wakeup is triggered by entering debug interface mode"] +pub type DIF_W<'a, const O: u8> = crate::BitWriter<'a, u32, RESETREAS_SPEC, DIF_A, O>; +impl<'a, const O: u8> DIF_W<'a, O> { + #[doc = "Not detected"] + #[inline(always)] + pub fn not_detected(self) -> &'a mut W { + self.variant(DIF_A::NOT_DETECTED) + } + #[doc = "Detected"] + #[inline(always)] + pub fn detected(self) -> &'a mut W { + self.variant(DIF_A::DETECTED) + } +} +#[doc = "Field `SREQ` reader - Reset from AIRCR.SYSRESETREQ detected"] +pub type SREQ_R = crate::BitReader; +#[doc = "Reset from AIRCR.SYSRESETREQ detected\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum SREQ_A { + #[doc = "0: Not detected"] + NOT_DETECTED = 0, + #[doc = "1: Detected"] + DETECTED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: SREQ_A) -> Self { + variant as u8 != 0 + } +} +impl SREQ_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> SREQ_A { + match self.bits { + false => SREQ_A::NOT_DETECTED, + true => SREQ_A::DETECTED, + } + } + #[doc = "Checks if the value of the field is `NOT_DETECTED`"] + #[inline(always)] + pub fn is_not_detected(&self) -> bool { + *self == SREQ_A::NOT_DETECTED + } + #[doc = "Checks if the value of the field is `DETECTED`"] + #[inline(always)] + pub fn is_detected(&self) -> bool { + *self == SREQ_A::DETECTED + } +} +#[doc = "Field `SREQ` writer - Reset from AIRCR.SYSRESETREQ detected"] +pub type SREQ_W<'a, const O: u8> = crate::BitWriter<'a, u32, RESETREAS_SPEC, SREQ_A, O>; +impl<'a, const O: u8> SREQ_W<'a, O> { + #[doc = "Not detected"] + #[inline(always)] + pub fn not_detected(self) -> &'a mut W { + self.variant(SREQ_A::NOT_DETECTED) + } + #[doc = "Detected"] + #[inline(always)] + pub fn detected(self) -> &'a mut W { + self.variant(SREQ_A::DETECTED) + } +} +#[doc = "Field `LOCKUP` reader - Reset from CPU lock-up detected"] +pub type LOCKUP_R = crate::BitReader; +#[doc = "Reset from CPU lock-up detected\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum LOCKUP_A { + #[doc = "0: Not detected"] + NOT_DETECTED = 0, + #[doc = "1: Detected"] + DETECTED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: LOCKUP_A) -> Self { + variant as u8 != 0 + } +} +impl LOCKUP_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> LOCKUP_A { + match self.bits { + false => LOCKUP_A::NOT_DETECTED, + true => LOCKUP_A::DETECTED, + } + } + #[doc = "Checks if the value of the field is `NOT_DETECTED`"] + #[inline(always)] + pub fn is_not_detected(&self) -> bool { + *self == LOCKUP_A::NOT_DETECTED + } + #[doc = "Checks if the value of the field is `DETECTED`"] + #[inline(always)] + pub fn is_detected(&self) -> bool { + *self == LOCKUP_A::DETECTED + } +} +#[doc = "Field `LOCKUP` writer - Reset from CPU lock-up detected"] +pub type LOCKUP_W<'a, const O: u8> = crate::BitWriter<'a, u32, RESETREAS_SPEC, LOCKUP_A, O>; +impl<'a, const O: u8> LOCKUP_W<'a, O> { + #[doc = "Not detected"] + #[inline(always)] + pub fn not_detected(self) -> &'a mut W { + self.variant(LOCKUP_A::NOT_DETECTED) + } + #[doc = "Detected"] + #[inline(always)] + pub fn detected(self) -> &'a mut W { + self.variant(LOCKUP_A::DETECTED) + } +} +#[doc = "Field `CTRLAP` reader - Reset triggered through CTRL-AP"] +pub type CTRLAP_R = crate::BitReader; +#[doc = "Reset triggered through CTRL-AP\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CTRLAP_A { + #[doc = "0: Not detected"] + NOT_DETECTED = 0, + #[doc = "1: Detected"] + DETECTED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CTRLAP_A) -> Self { + variant as u8 != 0 + } +} +impl CTRLAP_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CTRLAP_A { + match self.bits { + false => CTRLAP_A::NOT_DETECTED, + true => CTRLAP_A::DETECTED, + } + } + #[doc = "Checks if the value of the field is `NOT_DETECTED`"] + #[inline(always)] + pub fn is_not_detected(&self) -> bool { + *self == CTRLAP_A::NOT_DETECTED + } + #[doc = "Checks if the value of the field is `DETECTED`"] + #[inline(always)] + pub fn is_detected(&self) -> bool { + *self == CTRLAP_A::DETECTED + } +} +#[doc = "Field `CTRLAP` writer - Reset triggered through CTRL-AP"] +pub type CTRLAP_W<'a, const O: u8> = crate::BitWriter<'a, u32, RESETREAS_SPEC, CTRLAP_A, O>; +impl<'a, const O: u8> CTRLAP_W<'a, O> { + #[doc = "Not detected"] + #[inline(always)] + pub fn not_detected(self) -> &'a mut W { + self.variant(CTRLAP_A::NOT_DETECTED) + } + #[doc = "Detected"] + #[inline(always)] + pub fn detected(self) -> &'a mut W { + self.variant(CTRLAP_A::DETECTED) + } +} +impl R { + #[doc = "Bit 0 - Reset from pin reset detected"] + #[inline(always)] + pub fn resetpin(&self) -> RESETPIN_R { + RESETPIN_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Reset from global watchdog detected"] + #[inline(always)] + pub fn dog(&self) -> DOG_R { + DOG_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Reset due to wakeup from System OFF mode, when wakeup is triggered by DETECT signal from GPIO"] + #[inline(always)] + pub fn off(&self) -> OFF_R { + OFF_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 4 - Reset due to wakeup from System OFF mode, when wakeup is triggered by entering debug interface mode"] + #[inline(always)] + pub fn dif(&self) -> DIF_R { + DIF_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 16 - Reset from AIRCR.SYSRESETREQ detected"] + #[inline(always)] + pub fn sreq(&self) -> SREQ_R { + SREQ_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Reset from CPU lock-up detected"] + #[inline(always)] + pub fn lockup(&self) -> LOCKUP_R { + LOCKUP_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Reset triggered through CTRL-AP"] + #[inline(always)] + pub fn ctrlap(&self) -> CTRLAP_R { + CTRLAP_R::new(((self.bits >> 18) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Reset from pin reset detected"] + #[inline(always)] + pub fn resetpin(&mut self) -> RESETPIN_W<0> { + RESETPIN_W::new(self) + } + #[doc = "Bit 1 - Reset from global watchdog detected"] + #[inline(always)] + pub fn dog(&mut self) -> DOG_W<1> { + DOG_W::new(self) + } + #[doc = "Bit 2 - Reset due to wakeup from System OFF mode, when wakeup is triggered by DETECT signal from GPIO"] + #[inline(always)] + pub fn off(&mut self) -> OFF_W<2> { + OFF_W::new(self) + } + #[doc = "Bit 4 - Reset due to wakeup from System OFF mode, when wakeup is triggered by entering debug interface mode"] + #[inline(always)] + pub fn dif(&mut self) -> DIF_W<4> { + DIF_W::new(self) + } + #[doc = "Bit 16 - Reset from AIRCR.SYSRESETREQ detected"] + #[inline(always)] + pub fn sreq(&mut self) -> SREQ_W<16> { + SREQ_W::new(self) + } + #[doc = "Bit 17 - Reset from CPU lock-up detected"] + #[inline(always)] + pub fn lockup(&mut self) -> LOCKUP_W<17> { + LOCKUP_W::new(self) + } + #[doc = "Bit 18 - Reset triggered through CTRL-AP"] + #[inline(always)] + pub fn ctrlap(&mut self) -> CTRLAP_W<18> { + CTRLAP_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Reset reason\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [resetreas](index.html) module"] +pub struct RESETREAS_SPEC; +impl crate::RegisterSpec for RESETREAS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [resetreas::R](R) reader structure"] +impl crate::Readable for RESETREAS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [resetreas::W](W) writer structure"] +impl crate::Writable for RESETREAS_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets RESETREAS to value 0"] +impl crate::Resettable for RESETREAS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/power_ns/subscribe_constlat.rs b/pacs/nrf9120-pac/src/power_ns/subscribe_constlat.rs new file mode 100644 index 00000000..f28dfbec --- /dev/null +++ b/pacs/nrf9120-pac/src/power_ns/subscribe_constlat.rs @@ -0,0 +1,141 @@ +#[doc = "Register `SUBSCRIBE_CONSTLAT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SUBSCRIBE_CONSTLAT` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CHIDX` reader - DPPI channel that task CONSTLAT will subscribe to"] +pub type CHIDX_R = crate::FieldReader; +#[doc = "Field `CHIDX` writer - DPPI channel that task CONSTLAT will subscribe to"] +pub type CHIDX_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, SUBSCRIBE_CONSTLAT_SPEC, u8, u8, 8, O>; +#[doc = "Field `EN` reader - "] +pub type EN_R = crate::BitReader; +#[doc = "\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum EN_A { + #[doc = "0: Disable subscription"] + DISABLED = 0, + #[doc = "1: Enable subscription"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: EN_A) -> Self { + variant as u8 != 0 + } +} +impl EN_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EN_A { + match self.bits { + false => EN_A::DISABLED, + true => EN_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == EN_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == EN_A::ENABLED + } +} +#[doc = "Field `EN` writer - "] +pub type EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, SUBSCRIBE_CONSTLAT_SPEC, EN_A, O>; +impl<'a, const O: u8> EN_W<'a, O> { + #[doc = "Disable subscription"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(EN_A::DISABLED) + } + #[doc = "Enable subscription"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(EN_A::ENABLED) + } +} +impl R { + #[doc = "Bits 0:7 - DPPI channel that task CONSTLAT will subscribe to"] + #[inline(always)] + pub fn chidx(&self) -> CHIDX_R { + CHIDX_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&self) -> EN_R { + EN_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:7 - DPPI channel that task CONSTLAT will subscribe to"] + #[inline(always)] + pub fn chidx(&mut self) -> CHIDX_W<0> { + CHIDX_W::new(self) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&mut self) -> EN_W<31> { + EN_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Subscribe configuration for task CONSTLAT\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [subscribe_constlat](index.html) module"] +pub struct SUBSCRIBE_CONSTLAT_SPEC; +impl crate::RegisterSpec for SUBSCRIBE_CONSTLAT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [subscribe_constlat::R](R) reader structure"] +impl crate::Readable for SUBSCRIBE_CONSTLAT_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [subscribe_constlat::W](W) writer structure"] +impl crate::Writable for SUBSCRIBE_CONSTLAT_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SUBSCRIBE_CONSTLAT to value 0"] +impl crate::Resettable for SUBSCRIBE_CONSTLAT_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/power_ns/subscribe_lowpwr.rs b/pacs/nrf9120-pac/src/power_ns/subscribe_lowpwr.rs new file mode 100644 index 00000000..f8388945 --- /dev/null +++ b/pacs/nrf9120-pac/src/power_ns/subscribe_lowpwr.rs @@ -0,0 +1,141 @@ +#[doc = "Register `SUBSCRIBE_LOWPWR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SUBSCRIBE_LOWPWR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CHIDX` reader - DPPI channel that task LOWPWR will subscribe to"] +pub type CHIDX_R = crate::FieldReader; +#[doc = "Field `CHIDX` writer - DPPI channel that task LOWPWR will subscribe to"] +pub type CHIDX_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, SUBSCRIBE_LOWPWR_SPEC, u8, u8, 8, O>; +#[doc = "Field `EN` reader - "] +pub type EN_R = crate::BitReader; +#[doc = "\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum EN_A { + #[doc = "0: Disable subscription"] + DISABLED = 0, + #[doc = "1: Enable subscription"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: EN_A) -> Self { + variant as u8 != 0 + } +} +impl EN_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EN_A { + match self.bits { + false => EN_A::DISABLED, + true => EN_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == EN_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == EN_A::ENABLED + } +} +#[doc = "Field `EN` writer - "] +pub type EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, SUBSCRIBE_LOWPWR_SPEC, EN_A, O>; +impl<'a, const O: u8> EN_W<'a, O> { + #[doc = "Disable subscription"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(EN_A::DISABLED) + } + #[doc = "Enable subscription"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(EN_A::ENABLED) + } +} +impl R { + #[doc = "Bits 0:7 - DPPI channel that task LOWPWR will subscribe to"] + #[inline(always)] + pub fn chidx(&self) -> CHIDX_R { + CHIDX_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&self) -> EN_R { + EN_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:7 - DPPI channel that task LOWPWR will subscribe to"] + #[inline(always)] + pub fn chidx(&mut self) -> CHIDX_W<0> { + CHIDX_W::new(self) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&mut self) -> EN_W<31> { + EN_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Subscribe configuration for task LOWPWR\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [subscribe_lowpwr](index.html) module"] +pub struct SUBSCRIBE_LOWPWR_SPEC; +impl crate::RegisterSpec for SUBSCRIBE_LOWPWR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [subscribe_lowpwr::R](R) reader structure"] +impl crate::Readable for SUBSCRIBE_LOWPWR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [subscribe_lowpwr::W](W) writer structure"] +impl crate::Writable for SUBSCRIBE_LOWPWR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SUBSCRIBE_LOWPWR to value 0"] +impl crate::Resettable for SUBSCRIBE_LOWPWR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/power_ns/subscribe_pwmreqstart.rs b/pacs/nrf9120-pac/src/power_ns/subscribe_pwmreqstart.rs new file mode 100644 index 00000000..6df8234e --- /dev/null +++ b/pacs/nrf9120-pac/src/power_ns/subscribe_pwmreqstart.rs @@ -0,0 +1,141 @@ +#[doc = "Register `SUBSCRIBE_PWMREQSTART` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SUBSCRIBE_PWMREQSTART` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CHIDX` reader - DPPI channel that task PWMREQSTART will subscribe to"] +pub type CHIDX_R = crate::FieldReader; +#[doc = "Field `CHIDX` writer - DPPI channel that task PWMREQSTART will subscribe to"] +pub type CHIDX_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, SUBSCRIBE_PWMREQSTART_SPEC, u8, u8, 8, O>; +#[doc = "Field `EN` reader - "] +pub type EN_R = crate::BitReader; +#[doc = "\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum EN_A { + #[doc = "0: Disable subscription"] + DISABLED = 0, + #[doc = "1: Enable subscription"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: EN_A) -> Self { + variant as u8 != 0 + } +} +impl EN_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EN_A { + match self.bits { + false => EN_A::DISABLED, + true => EN_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == EN_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == EN_A::ENABLED + } +} +#[doc = "Field `EN` writer - "] +pub type EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, SUBSCRIBE_PWMREQSTART_SPEC, EN_A, O>; +impl<'a, const O: u8> EN_W<'a, O> { + #[doc = "Disable subscription"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(EN_A::DISABLED) + } + #[doc = "Enable subscription"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(EN_A::ENABLED) + } +} +impl R { + #[doc = "Bits 0:7 - DPPI channel that task PWMREQSTART will subscribe to"] + #[inline(always)] + pub fn chidx(&self) -> CHIDX_R { + CHIDX_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&self) -> EN_R { + EN_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:7 - DPPI channel that task PWMREQSTART will subscribe to"] + #[inline(always)] + pub fn chidx(&mut self) -> CHIDX_W<0> { + CHIDX_W::new(self) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&mut self) -> EN_W<31> { + EN_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Subscribe configuration for task PWMREQSTART\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [subscribe_pwmreqstart](index.html) module"] +pub struct SUBSCRIBE_PWMREQSTART_SPEC; +impl crate::RegisterSpec for SUBSCRIBE_PWMREQSTART_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [subscribe_pwmreqstart::R](R) reader structure"] +impl crate::Readable for SUBSCRIBE_PWMREQSTART_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [subscribe_pwmreqstart::W](W) writer structure"] +impl crate::Writable for SUBSCRIBE_PWMREQSTART_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SUBSCRIBE_PWMREQSTART to value 0"] +impl crate::Resettable for SUBSCRIBE_PWMREQSTART_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/power_ns/subscribe_pwmreqstop.rs b/pacs/nrf9120-pac/src/power_ns/subscribe_pwmreqstop.rs new file mode 100644 index 00000000..40d38606 --- /dev/null +++ b/pacs/nrf9120-pac/src/power_ns/subscribe_pwmreqstop.rs @@ -0,0 +1,141 @@ +#[doc = "Register `SUBSCRIBE_PWMREQSTOP` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SUBSCRIBE_PWMREQSTOP` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CHIDX` reader - DPPI channel that task PWMREQSTOP will subscribe to"] +pub type CHIDX_R = crate::FieldReader; +#[doc = "Field `CHIDX` writer - DPPI channel that task PWMREQSTOP will subscribe to"] +pub type CHIDX_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, SUBSCRIBE_PWMREQSTOP_SPEC, u8, u8, 8, O>; +#[doc = "Field `EN` reader - "] +pub type EN_R = crate::BitReader; +#[doc = "\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum EN_A { + #[doc = "0: Disable subscription"] + DISABLED = 0, + #[doc = "1: Enable subscription"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: EN_A) -> Self { + variant as u8 != 0 + } +} +impl EN_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EN_A { + match self.bits { + false => EN_A::DISABLED, + true => EN_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == EN_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == EN_A::ENABLED + } +} +#[doc = "Field `EN` writer - "] +pub type EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, SUBSCRIBE_PWMREQSTOP_SPEC, EN_A, O>; +impl<'a, const O: u8> EN_W<'a, O> { + #[doc = "Disable subscription"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(EN_A::DISABLED) + } + #[doc = "Enable subscription"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(EN_A::ENABLED) + } +} +impl R { + #[doc = "Bits 0:7 - DPPI channel that task PWMREQSTOP will subscribe to"] + #[inline(always)] + pub fn chidx(&self) -> CHIDX_R { + CHIDX_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&self) -> EN_R { + EN_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:7 - DPPI channel that task PWMREQSTOP will subscribe to"] + #[inline(always)] + pub fn chidx(&mut self) -> CHIDX_W<0> { + CHIDX_W::new(self) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&mut self) -> EN_W<31> { + EN_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Subscribe configuration for task PWMREQSTOP\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [subscribe_pwmreqstop](index.html) module"] +pub struct SUBSCRIBE_PWMREQSTOP_SPEC; +impl crate::RegisterSpec for SUBSCRIBE_PWMREQSTOP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [subscribe_pwmreqstop::R](R) reader structure"] +impl crate::Readable for SUBSCRIBE_PWMREQSTOP_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [subscribe_pwmreqstop::W](W) writer structure"] +impl crate::Writable for SUBSCRIBE_PWMREQSTOP_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SUBSCRIBE_PWMREQSTOP to value 0"] +impl crate::Resettable for SUBSCRIBE_PWMREQSTOP_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/power_ns/tasks_constlat.rs b/pacs/nrf9120-pac/src/power_ns/tasks_constlat.rs new file mode 100644 index 00000000..9bae1bfd --- /dev/null +++ b/pacs/nrf9120-pac/src/power_ns/tasks_constlat.rs @@ -0,0 +1,72 @@ +#[doc = "Register `TASKS_CONSTLAT` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Enable constant latency mode.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum TASKS_CONSTLAT_AW { + #[doc = "1: Trigger task"] + TRIGGER = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TASKS_CONSTLAT_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TASKS_CONSTLAT` writer - Enable constant latency mode."] +pub type TASKS_CONSTLAT_W<'a, const O: u8> = + crate::BitWriter<'a, u32, TASKS_CONSTLAT_SPEC, TASKS_CONSTLAT_AW, O>; +impl<'a, const O: u8> TASKS_CONSTLAT_W<'a, O> { + #[doc = "Trigger task"] + #[inline(always)] + pub fn trigger(self) -> &'a mut W { + self.variant(TASKS_CONSTLAT_AW::TRIGGER) + } +} +impl W { + #[doc = "Bit 0 - Enable constant latency mode."] + #[inline(always)] + pub fn tasks_constlat(&mut self) -> TASKS_CONSTLAT_W<0> { + TASKS_CONSTLAT_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Enable constant latency mode.\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tasks_constlat](index.html) module"] +pub struct TASKS_CONSTLAT_SPEC; +impl crate::RegisterSpec for TASKS_CONSTLAT_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [tasks_constlat::W](W) writer structure"] +impl crate::Writable for TASKS_CONSTLAT_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets TASKS_CONSTLAT to value 0"] +impl crate::Resettable for TASKS_CONSTLAT_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/power_ns/tasks_lowpwr.rs b/pacs/nrf9120-pac/src/power_ns/tasks_lowpwr.rs new file mode 100644 index 00000000..b62fe077 --- /dev/null +++ b/pacs/nrf9120-pac/src/power_ns/tasks_lowpwr.rs @@ -0,0 +1,72 @@ +#[doc = "Register `TASKS_LOWPWR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Enable low power mode (variable latency)\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum TASKS_LOWPWR_AW { + #[doc = "1: Trigger task"] + TRIGGER = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TASKS_LOWPWR_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TASKS_LOWPWR` writer - Enable low power mode (variable latency)"] +pub type TASKS_LOWPWR_W<'a, const O: u8> = + crate::BitWriter<'a, u32, TASKS_LOWPWR_SPEC, TASKS_LOWPWR_AW, O>; +impl<'a, const O: u8> TASKS_LOWPWR_W<'a, O> { + #[doc = "Trigger task"] + #[inline(always)] + pub fn trigger(self) -> &'a mut W { + self.variant(TASKS_LOWPWR_AW::TRIGGER) + } +} +impl W { + #[doc = "Bit 0 - Enable low power mode (variable latency)"] + #[inline(always)] + pub fn tasks_lowpwr(&mut self) -> TASKS_LOWPWR_W<0> { + TASKS_LOWPWR_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Enable low power mode (variable latency)\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tasks_lowpwr](index.html) module"] +pub struct TASKS_LOWPWR_SPEC; +impl crate::RegisterSpec for TASKS_LOWPWR_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [tasks_lowpwr::W](W) writer structure"] +impl crate::Writable for TASKS_LOWPWR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets TASKS_LOWPWR to value 0"] +impl crate::Resettable for TASKS_LOWPWR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/power_ns/tasks_pwmreqstart.rs b/pacs/nrf9120-pac/src/power_ns/tasks_pwmreqstart.rs new file mode 100644 index 00000000..9dfe86e3 --- /dev/null +++ b/pacs/nrf9120-pac/src/power_ns/tasks_pwmreqstart.rs @@ -0,0 +1,72 @@ +#[doc = "Register `TASKS_PWMREQSTART` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Request forcing PWM mode in external DC/DC voltage regulator. (Drives FPWM_DCDC pin high or low depending on a setting in UICR).\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum TASKS_PWMREQSTART_AW { + #[doc = "1: Trigger task"] + TRIGGER = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TASKS_PWMREQSTART_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TASKS_PWMREQSTART` writer - Request forcing PWM mode in external DC/DC voltage regulator. (Drives FPWM_DCDC pin high or low depending on a setting in UICR)."] +pub type TASKS_PWMREQSTART_W<'a, const O: u8> = + crate::BitWriter<'a, u32, TASKS_PWMREQSTART_SPEC, TASKS_PWMREQSTART_AW, O>; +impl<'a, const O: u8> TASKS_PWMREQSTART_W<'a, O> { + #[doc = "Trigger task"] + #[inline(always)] + pub fn trigger(self) -> &'a mut W { + self.variant(TASKS_PWMREQSTART_AW::TRIGGER) + } +} +impl W { + #[doc = "Bit 0 - Request forcing PWM mode in external DC/DC voltage regulator. (Drives FPWM_DCDC pin high or low depending on a setting in UICR)."] + #[inline(always)] + pub fn tasks_pwmreqstart(&mut self) -> TASKS_PWMREQSTART_W<0> { + TASKS_PWMREQSTART_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Request forcing PWM mode in external DC/DC voltage regulator. (Drives FPWM_DCDC pin high or low depending on a setting in UICR).\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tasks_pwmreqstart](index.html) module"] +pub struct TASKS_PWMREQSTART_SPEC; +impl crate::RegisterSpec for TASKS_PWMREQSTART_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [tasks_pwmreqstart::W](W) writer structure"] +impl crate::Writable for TASKS_PWMREQSTART_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets TASKS_PWMREQSTART to value 0"] +impl crate::Resettable for TASKS_PWMREQSTART_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/power_ns/tasks_pwmreqstop.rs b/pacs/nrf9120-pac/src/power_ns/tasks_pwmreqstop.rs new file mode 100644 index 00000000..c92f38fc --- /dev/null +++ b/pacs/nrf9120-pac/src/power_ns/tasks_pwmreqstop.rs @@ -0,0 +1,72 @@ +#[doc = "Register `TASKS_PWMREQSTOP` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Stop requesting forcing PWM mode in external DC/DC voltage regulator\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum TASKS_PWMREQSTOP_AW { + #[doc = "1: Trigger task"] + TRIGGER = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TASKS_PWMREQSTOP_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TASKS_PWMREQSTOP` writer - Stop requesting forcing PWM mode in external DC/DC voltage regulator"] +pub type TASKS_PWMREQSTOP_W<'a, const O: u8> = + crate::BitWriter<'a, u32, TASKS_PWMREQSTOP_SPEC, TASKS_PWMREQSTOP_AW, O>; +impl<'a, const O: u8> TASKS_PWMREQSTOP_W<'a, O> { + #[doc = "Trigger task"] + #[inline(always)] + pub fn trigger(self) -> &'a mut W { + self.variant(TASKS_PWMREQSTOP_AW::TRIGGER) + } +} +impl W { + #[doc = "Bit 0 - Stop requesting forcing PWM mode in external DC/DC voltage regulator"] + #[inline(always)] + pub fn tasks_pwmreqstop(&mut self) -> TASKS_PWMREQSTOP_W<0> { + TASKS_PWMREQSTOP_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Stop requesting forcing PWM mode in external DC/DC voltage regulator\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tasks_pwmreqstop](index.html) module"] +pub struct TASKS_PWMREQSTOP_SPEC; +impl crate::RegisterSpec for TASKS_PWMREQSTOP_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [tasks_pwmreqstop::W](W) writer structure"] +impl crate::Writable for TASKS_PWMREQSTOP_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets TASKS_PWMREQSTOP to value 0"] +impl crate::Resettable for TASKS_PWMREQSTOP_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/pwm0_ns.rs b/pacs/nrf9120-pac/src/pwm0_ns.rs new file mode 100644 index 00000000..a79fc4e0 --- /dev/null +++ b/pacs/nrf9120-pac/src/pwm0_ns.rs @@ -0,0 +1,186 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + _reserved0: [u8; 0x04], + #[doc = "0x04 - Stops PWM pulse generation on all channels at the end of current PWM period, and stops sequence playback"] + pub tasks_stop: TASKS_STOP, + #[doc = "0x08..0x10 - Description collection: Loads the first PWM value on all enabled channels from sequence n, and starts playing that sequence at the rate defined in SEQ\\[n\\]REFRESH and/or DECODER.MODE. Causes PWM generation to start if not running."] + pub tasks_seqstart: [TASKS_SEQSTART; 2], + #[doc = "0x10 - Steps by one value in the current sequence on all enabled channels if DECODER.MODE=NextStep. Does not cause PWM generation to start if not running."] + pub tasks_nextstep: TASKS_NEXTSTEP, + _reserved3: [u8; 0x70], + #[doc = "0x84 - Subscribe configuration for task STOP"] + pub subscribe_stop: SUBSCRIBE_STOP, + #[doc = "0x88..0x90 - Description collection: Subscribe configuration for task SEQSTART\\[n\\]"] + pub subscribe_seqstart: [SUBSCRIBE_SEQSTART; 2], + #[doc = "0x90 - Subscribe configuration for task NEXTSTEP"] + pub subscribe_nextstep: SUBSCRIBE_NEXTSTEP, + _reserved6: [u8; 0x70], + #[doc = "0x104 - Response to STOP task, emitted when PWM pulses are no longer generated"] + pub events_stopped: EVENTS_STOPPED, + #[doc = "0x108..0x110 - Description collection: First PWM period started on sequence n"] + pub events_seqstarted: [EVENTS_SEQSTARTED; 2], + #[doc = "0x110..0x118 - Description collection: Emitted at end of every sequence n, when last value from RAM has been applied to wave counter"] + pub events_seqend: [EVENTS_SEQEND; 2], + #[doc = "0x118 - Emitted at the end of each PWM period"] + pub events_pwmperiodend: EVENTS_PWMPERIODEND, + #[doc = "0x11c - Concatenated sequences have been played the amount of times defined in LOOP.CNT"] + pub events_loopsdone: EVENTS_LOOPSDONE, + _reserved11: [u8; 0x64], + #[doc = "0x184 - Publish configuration for event STOPPED"] + pub publish_stopped: PUBLISH_STOPPED, + #[doc = "0x188..0x190 - Description collection: Publish configuration for event SEQSTARTED\\[n\\]"] + pub publish_seqstarted: [PUBLISH_SEQSTARTED; 2], + #[doc = "0x190..0x198 - Description collection: Publish configuration for event SEQEND\\[n\\]"] + pub publish_seqend: [PUBLISH_SEQEND; 2], + #[doc = "0x198 - Publish configuration for event PWMPERIODEND"] + pub publish_pwmperiodend: PUBLISH_PWMPERIODEND, + #[doc = "0x19c - Publish configuration for event LOOPSDONE"] + pub publish_loopsdone: PUBLISH_LOOPSDONE, + _reserved16: [u8; 0x60], + #[doc = "0x200 - Shortcuts between local events and tasks"] + pub shorts: SHORTS, + _reserved17: [u8; 0xfc], + #[doc = "0x300 - Enable or disable interrupt"] + pub inten: INTEN, + #[doc = "0x304 - Enable interrupt"] + pub intenset: INTENSET, + #[doc = "0x308 - Disable interrupt"] + pub intenclr: INTENCLR, + _reserved20: [u8; 0x01f4], + #[doc = "0x500 - PWM module enable register"] + pub enable: ENABLE, + #[doc = "0x504 - Selects operating mode of the wave counter"] + pub mode: MODE, + #[doc = "0x508 - Value up to which the pulse generator counter counts"] + pub countertop: COUNTERTOP, + #[doc = "0x50c - Configuration for PWM_CLK"] + pub prescaler: PRESCALER, + #[doc = "0x510 - Configuration of the decoder"] + pub decoder: DECODER, + #[doc = "0x514 - Number of playbacks of a loop"] + pub loop_: LOOP, + _reserved26: [u8; 0x08], + #[doc = "0x520..0x530 - Unspecified"] + pub seq0: SEQ, + _reserved27: [u8; 0x10], + #[doc = "0x540..0x550 - Unspecified"] + pub seq1: SEQ, + _reserved28: [u8; 0x10], + #[doc = "0x560..0x570 - Unspecified"] + pub psel: PSEL, +} +#[doc = "TASKS_STOP (w) register accessor: an alias for `Reg`"] +pub type TASKS_STOP = crate::Reg; +#[doc = "Stops PWM pulse generation on all channels at the end of current PWM period, and stops sequence playback"] +pub mod tasks_stop; +#[doc = "TASKS_SEQSTART (w) register accessor: an alias for `Reg`"] +pub type TASKS_SEQSTART = crate::Reg; +#[doc = "Description collection: Loads the first PWM value on all enabled channels from sequence n, and starts playing that sequence at the rate defined in SEQ\\[n\\]REFRESH and/or DECODER.MODE. Causes PWM generation to start if not running."] +pub mod tasks_seqstart; +#[doc = "TASKS_NEXTSTEP (w) register accessor: an alias for `Reg`"] +pub type TASKS_NEXTSTEP = crate::Reg; +#[doc = "Steps by one value in the current sequence on all enabled channels if DECODER.MODE=NextStep. Does not cause PWM generation to start if not running."] +pub mod tasks_nextstep; +#[doc = "SUBSCRIBE_STOP (rw) register accessor: an alias for `Reg`"] +pub type SUBSCRIBE_STOP = crate::Reg; +#[doc = "Subscribe configuration for task STOP"] +pub mod subscribe_stop; +#[doc = "SUBSCRIBE_SEQSTART (rw) register accessor: an alias for `Reg`"] +pub type SUBSCRIBE_SEQSTART = crate::Reg; +#[doc = "Description collection: Subscribe configuration for task SEQSTART\\[n\\]"] +pub mod subscribe_seqstart; +#[doc = "SUBSCRIBE_NEXTSTEP (rw) register accessor: an alias for `Reg`"] +pub type SUBSCRIBE_NEXTSTEP = crate::Reg; +#[doc = "Subscribe configuration for task NEXTSTEP"] +pub mod subscribe_nextstep; +#[doc = "EVENTS_STOPPED (rw) register accessor: an alias for `Reg`"] +pub type EVENTS_STOPPED = crate::Reg; +#[doc = "Response to STOP task, emitted when PWM pulses are no longer generated"] +pub mod events_stopped; +#[doc = "EVENTS_SEQSTARTED (rw) register accessor: an alias for `Reg`"] +pub type EVENTS_SEQSTARTED = crate::Reg; +#[doc = "Description collection: First PWM period started on sequence n"] +pub mod events_seqstarted; +#[doc = "EVENTS_SEQEND (rw) register accessor: an alias for `Reg`"] +pub type EVENTS_SEQEND = crate::Reg; +#[doc = "Description collection: Emitted at end of every sequence n, when last value from RAM has been applied to wave counter"] +pub mod events_seqend; +#[doc = "EVENTS_PWMPERIODEND (rw) register accessor: an alias for `Reg`"] +pub type EVENTS_PWMPERIODEND = crate::Reg; +#[doc = "Emitted at the end of each PWM period"] +pub mod events_pwmperiodend; +#[doc = "EVENTS_LOOPSDONE (rw) register accessor: an alias for `Reg`"] +pub type EVENTS_LOOPSDONE = crate::Reg; +#[doc = "Concatenated sequences have been played the amount of times defined in LOOP.CNT"] +pub mod events_loopsdone; +#[doc = "PUBLISH_STOPPED (rw) register accessor: an alias for `Reg`"] +pub type PUBLISH_STOPPED = crate::Reg; +#[doc = "Publish configuration for event STOPPED"] +pub mod publish_stopped; +#[doc = "PUBLISH_SEQSTARTED (rw) register accessor: an alias for `Reg`"] +pub type PUBLISH_SEQSTARTED = crate::Reg; +#[doc = "Description collection: Publish configuration for event SEQSTARTED\\[n\\]"] +pub mod publish_seqstarted; +#[doc = "PUBLISH_SEQEND (rw) register accessor: an alias for `Reg`"] +pub type PUBLISH_SEQEND = crate::Reg; +#[doc = "Description collection: Publish configuration for event SEQEND\\[n\\]"] +pub mod publish_seqend; +#[doc = "PUBLISH_PWMPERIODEND (rw) register accessor: an alias for `Reg`"] +pub type PUBLISH_PWMPERIODEND = crate::Reg; +#[doc = "Publish configuration for event PWMPERIODEND"] +pub mod publish_pwmperiodend; +#[doc = "PUBLISH_LOOPSDONE (rw) register accessor: an alias for `Reg`"] +pub type PUBLISH_LOOPSDONE = crate::Reg; +#[doc = "Publish configuration for event LOOPSDONE"] +pub mod publish_loopsdone; +#[doc = "SHORTS (rw) register accessor: an alias for `Reg`"] +pub type SHORTS = crate::Reg; +#[doc = "Shortcuts between local events and tasks"] +pub mod shorts; +#[doc = "INTEN (rw) register accessor: an alias for `Reg`"] +pub type INTEN = crate::Reg; +#[doc = "Enable or disable interrupt"] +pub mod inten; +#[doc = "INTENSET (rw) register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "Enable interrupt"] +pub mod intenset; +#[doc = "INTENCLR (rw) register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "Disable interrupt"] +pub mod intenclr; +#[doc = "ENABLE (rw) register accessor: an alias for `Reg`"] +pub type ENABLE = crate::Reg; +#[doc = "PWM module enable register"] +pub mod enable; +#[doc = "MODE (rw) register accessor: an alias for `Reg`"] +pub type MODE = crate::Reg; +#[doc = "Selects operating mode of the wave counter"] +pub mod mode; +#[doc = "COUNTERTOP (rw) register accessor: an alias for `Reg`"] +pub type COUNTERTOP = crate::Reg; +#[doc = "Value up to which the pulse generator counter counts"] +pub mod countertop; +#[doc = "PRESCALER (rw) register accessor: an alias for `Reg`"] +pub type PRESCALER = crate::Reg; +#[doc = "Configuration for PWM_CLK"] +pub mod prescaler; +#[doc = "DECODER (rw) register accessor: an alias for `Reg`"] +pub type DECODER = crate::Reg; +#[doc = "Configuration of the decoder"] +pub mod decoder; +#[doc = "LOOP (rw) register accessor: an alias for `Reg`"] +pub type LOOP = crate::Reg; +#[doc = "Number of playbacks of a loop"] +pub mod loop_; +#[doc = "Unspecified"] +pub use seq::SEQ; +#[doc = r"Cluster"] +#[doc = "Unspecified"] +pub mod seq; +#[doc = "Unspecified"] +pub use psel::PSEL; +#[doc = r"Cluster"] +#[doc = "Unspecified"] +pub mod psel; diff --git a/pacs/nrf9120-pac/src/pwm0_ns/countertop.rs b/pacs/nrf9120-pac/src/pwm0_ns/countertop.rs new file mode 100644 index 00000000..c98379b2 --- /dev/null +++ b/pacs/nrf9120-pac/src/pwm0_ns/countertop.rs @@ -0,0 +1,81 @@ +#[doc = "Register `COUNTERTOP` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `COUNTERTOP` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `COUNTERTOP` reader - Value up to which the pulse generator counter counts. This register is ignored when DECODER.MODE=WaveForm and only values from RAM are used."] +pub type COUNTERTOP_R = crate::FieldReader; +#[doc = "Field `COUNTERTOP` writer - Value up to which the pulse generator counter counts. This register is ignored when DECODER.MODE=WaveForm and only values from RAM are used."] +pub type COUNTERTOP_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, COUNTERTOP_SPEC, u16, u16, 15, O>; +impl R { + #[doc = "Bits 0:14 - Value up to which the pulse generator counter counts. This register is ignored when DECODER.MODE=WaveForm and only values from RAM are used."] + #[inline(always)] + pub fn countertop(&self) -> COUNTERTOP_R { + COUNTERTOP_R::new((self.bits & 0x7fff) as u16) + } +} +impl W { + #[doc = "Bits 0:14 - Value up to which the pulse generator counter counts. This register is ignored when DECODER.MODE=WaveForm and only values from RAM are used."] + #[inline(always)] + pub fn countertop(&mut self) -> COUNTERTOP_W<0> { + COUNTERTOP_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Value up to which the pulse generator counter counts\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [countertop](index.html) module"] +pub struct COUNTERTOP_SPEC; +impl crate::RegisterSpec for COUNTERTOP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [countertop::R](R) reader structure"] +impl crate::Readable for COUNTERTOP_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [countertop::W](W) writer structure"] +impl crate::Writable for COUNTERTOP_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets COUNTERTOP to value 0x03ff"] +impl crate::Resettable for COUNTERTOP_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x03ff + } +} diff --git a/pacs/nrf9120-pac/src/pwm0_ns/decoder.rs b/pacs/nrf9120-pac/src/pwm0_ns/decoder.rs new file mode 100644 index 00000000..7231877e --- /dev/null +++ b/pacs/nrf9120-pac/src/pwm0_ns/decoder.rs @@ -0,0 +1,214 @@ +#[doc = "Register `DECODER` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DECODER` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `LOAD` reader - How a sequence is read from RAM and spread to the compare register"] +pub type LOAD_R = crate::FieldReader; +#[doc = "How a sequence is read from RAM and spread to the compare register\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum LOAD_A { + #[doc = "0: 1st half word (16-bit) used in all PWM channels 0..3"] + COMMON = 0, + #[doc = "1: 1st half word (16-bit) used in channel 0..1; 2nd word in channel 2..3"] + GROUPED = 1, + #[doc = "2: 1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th in ch.3"] + INDIVIDUAL = 2, + #[doc = "3: 1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th in COUNTERTOP"] + WAVE_FORM = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LOAD_A) -> Self { + variant as _ + } +} +impl LOAD_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> LOAD_A { + match self.bits { + 0 => LOAD_A::COMMON, + 1 => LOAD_A::GROUPED, + 2 => LOAD_A::INDIVIDUAL, + 3 => LOAD_A::WAVE_FORM, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `COMMON`"] + #[inline(always)] + pub fn is_common(&self) -> bool { + *self == LOAD_A::COMMON + } + #[doc = "Checks if the value of the field is `GROUPED`"] + #[inline(always)] + pub fn is_grouped(&self) -> bool { + *self == LOAD_A::GROUPED + } + #[doc = "Checks if the value of the field is `INDIVIDUAL`"] + #[inline(always)] + pub fn is_individual(&self) -> bool { + *self == LOAD_A::INDIVIDUAL + } + #[doc = "Checks if the value of the field is `WAVE_FORM`"] + #[inline(always)] + pub fn is_wave_form(&self) -> bool { + *self == LOAD_A::WAVE_FORM + } +} +#[doc = "Field `LOAD` writer - How a sequence is read from RAM and spread to the compare register"] +pub type LOAD_W<'a, const O: u8> = crate::FieldWriterSafe<'a, u32, DECODER_SPEC, u8, LOAD_A, 2, O>; +impl<'a, const O: u8> LOAD_W<'a, O> { + #[doc = "1st half word (16-bit) used in all PWM channels 0..3"] + #[inline(always)] + pub fn common(self) -> &'a mut W { + self.variant(LOAD_A::COMMON) + } + #[doc = "1st half word (16-bit) used in channel 0..1; 2nd word in channel 2..3"] + #[inline(always)] + pub fn grouped(self) -> &'a mut W { + self.variant(LOAD_A::GROUPED) + } + #[doc = "1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th in ch.3"] + #[inline(always)] + pub fn individual(self) -> &'a mut W { + self.variant(LOAD_A::INDIVIDUAL) + } + #[doc = "1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th in COUNTERTOP"] + #[inline(always)] + pub fn wave_form(self) -> &'a mut W { + self.variant(LOAD_A::WAVE_FORM) + } +} +#[doc = "Field `MODE` reader - Selects source for advancing the active sequence"] +pub type MODE_R = crate::BitReader; +#[doc = "Selects source for advancing the active sequence\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum MODE_A { + #[doc = "0: SEQ\\[n\\].REFRESH is used to determine loading internal compare registers"] + REFRESH_COUNT = 0, + #[doc = "1: NEXTSTEP task causes a new value to be loaded to internal compare registers"] + NEXT_STEP = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: MODE_A) -> Self { + variant as u8 != 0 + } +} +impl MODE_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> MODE_A { + match self.bits { + false => MODE_A::REFRESH_COUNT, + true => MODE_A::NEXT_STEP, + } + } + #[doc = "Checks if the value of the field is `REFRESH_COUNT`"] + #[inline(always)] + pub fn is_refresh_count(&self) -> bool { + *self == MODE_A::REFRESH_COUNT + } + #[doc = "Checks if the value of the field is `NEXT_STEP`"] + #[inline(always)] + pub fn is_next_step(&self) -> bool { + *self == MODE_A::NEXT_STEP + } +} +#[doc = "Field `MODE` writer - Selects source for advancing the active sequence"] +pub type MODE_W<'a, const O: u8> = crate::BitWriter<'a, u32, DECODER_SPEC, MODE_A, O>; +impl<'a, const O: u8> MODE_W<'a, O> { + #[doc = "SEQ\\[n\\].REFRESH is used to determine loading internal compare registers"] + #[inline(always)] + pub fn refresh_count(self) -> &'a mut W { + self.variant(MODE_A::REFRESH_COUNT) + } + #[doc = "NEXTSTEP task causes a new value to be loaded to internal compare registers"] + #[inline(always)] + pub fn next_step(self) -> &'a mut W { + self.variant(MODE_A::NEXT_STEP) + } +} +impl R { + #[doc = "Bits 0:1 - How a sequence is read from RAM and spread to the compare register"] + #[inline(always)] + pub fn load(&self) -> LOAD_R { + LOAD_R::new((self.bits & 3) as u8) + } + #[doc = "Bit 8 - Selects source for advancing the active sequence"] + #[inline(always)] + pub fn mode(&self) -> MODE_R { + MODE_R::new(((self.bits >> 8) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:1 - How a sequence is read from RAM and spread to the compare register"] + #[inline(always)] + pub fn load(&mut self) -> LOAD_W<0> { + LOAD_W::new(self) + } + #[doc = "Bit 8 - Selects source for advancing the active sequence"] + #[inline(always)] + pub fn mode(&mut self) -> MODE_W<8> { + MODE_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Configuration of the decoder\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [decoder](index.html) module"] +pub struct DECODER_SPEC; +impl crate::RegisterSpec for DECODER_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [decoder::R](R) reader structure"] +impl crate::Readable for DECODER_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [decoder::W](W) writer structure"] +impl crate::Writable for DECODER_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DECODER to value 0"] +impl crate::Resettable for DECODER_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/pwm0_ns/enable.rs b/pacs/nrf9120-pac/src/pwm0_ns/enable.rs new file mode 100644 index 00000000..0094e121 --- /dev/null +++ b/pacs/nrf9120-pac/src/pwm0_ns/enable.rs @@ -0,0 +1,126 @@ +#[doc = "Register `ENABLE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `ENABLE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ENABLE` reader - Enable or disable PWM module"] +pub type ENABLE_R = crate::BitReader; +#[doc = "Enable or disable PWM module\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum ENABLE_A { + #[doc = "0: Disabled"] + DISABLED = 0, + #[doc = "1: Enable"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: ENABLE_A) -> Self { + variant as u8 != 0 + } +} +impl ENABLE_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> ENABLE_A { + match self.bits { + false => ENABLE_A::DISABLED, + true => ENABLE_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == ENABLE_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == ENABLE_A::ENABLED + } +} +#[doc = "Field `ENABLE` writer - Enable or disable PWM module"] +pub type ENABLE_W<'a, const O: u8> = crate::BitWriter<'a, u32, ENABLE_SPEC, ENABLE_A, O>; +impl<'a, const O: u8> ENABLE_W<'a, O> { + #[doc = "Disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(ENABLE_A::DISABLED) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(ENABLE_A::ENABLED) + } +} +impl R { + #[doc = "Bit 0 - Enable or disable PWM module"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new((self.bits & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Enable or disable PWM module"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W<0> { + ENABLE_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "PWM module enable register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [enable](index.html) module"] +pub struct ENABLE_SPEC; +impl crate::RegisterSpec for ENABLE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [enable::R](R) reader structure"] +impl crate::Readable for ENABLE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [enable::W](W) writer structure"] +impl crate::Writable for ENABLE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets ENABLE to value 0"] +impl crate::Resettable for ENABLE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/pwm0_ns/events_loopsdone.rs b/pacs/nrf9120-pac/src/pwm0_ns/events_loopsdone.rs new file mode 100644 index 00000000..9eb7b564 --- /dev/null +++ b/pacs/nrf9120-pac/src/pwm0_ns/events_loopsdone.rs @@ -0,0 +1,127 @@ +#[doc = "Register `EVENTS_LOOPSDONE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVENTS_LOOPSDONE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `EVENTS_LOOPSDONE` reader - Concatenated sequences have been played the amount of times defined in LOOP.CNT"] +pub type EVENTS_LOOPSDONE_R = crate::BitReader; +#[doc = "Concatenated sequences have been played the amount of times defined in LOOP.CNT\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum EVENTS_LOOPSDONE_A { + #[doc = "0: Event not generated"] + NOT_GENERATED = 0, + #[doc = "1: Event generated"] + GENERATED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: EVENTS_LOOPSDONE_A) -> Self { + variant as u8 != 0 + } +} +impl EVENTS_LOOPSDONE_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EVENTS_LOOPSDONE_A { + match self.bits { + false => EVENTS_LOOPSDONE_A::NOT_GENERATED, + true => EVENTS_LOOPSDONE_A::GENERATED, + } + } + #[doc = "Checks if the value of the field is `NOT_GENERATED`"] + #[inline(always)] + pub fn is_not_generated(&self) -> bool { + *self == EVENTS_LOOPSDONE_A::NOT_GENERATED + } + #[doc = "Checks if the value of the field is `GENERATED`"] + #[inline(always)] + pub fn is_generated(&self) -> bool { + *self == EVENTS_LOOPSDONE_A::GENERATED + } +} +#[doc = "Field `EVENTS_LOOPSDONE` writer - Concatenated sequences have been played the amount of times defined in LOOP.CNT"] +pub type EVENTS_LOOPSDONE_W<'a, const O: u8> = + crate::BitWriter<'a, u32, EVENTS_LOOPSDONE_SPEC, EVENTS_LOOPSDONE_A, O>; +impl<'a, const O: u8> EVENTS_LOOPSDONE_W<'a, O> { + #[doc = "Event not generated"] + #[inline(always)] + pub fn not_generated(self) -> &'a mut W { + self.variant(EVENTS_LOOPSDONE_A::NOT_GENERATED) + } + #[doc = "Event generated"] + #[inline(always)] + pub fn generated(self) -> &'a mut W { + self.variant(EVENTS_LOOPSDONE_A::GENERATED) + } +} +impl R { + #[doc = "Bit 0 - Concatenated sequences have been played the amount of times defined in LOOP.CNT"] + #[inline(always)] + pub fn events_loopsdone(&self) -> EVENTS_LOOPSDONE_R { + EVENTS_LOOPSDONE_R::new((self.bits & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Concatenated sequences have been played the amount of times defined in LOOP.CNT"] + #[inline(always)] + pub fn events_loopsdone(&mut self) -> EVENTS_LOOPSDONE_W<0> { + EVENTS_LOOPSDONE_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Concatenated sequences have been played the amount of times defined in LOOP.CNT\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [events_loopsdone](index.html) module"] +pub struct EVENTS_LOOPSDONE_SPEC; +impl crate::RegisterSpec for EVENTS_LOOPSDONE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [events_loopsdone::R](R) reader structure"] +impl crate::Readable for EVENTS_LOOPSDONE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [events_loopsdone::W](W) writer structure"] +impl crate::Writable for EVENTS_LOOPSDONE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EVENTS_LOOPSDONE to value 0"] +impl crate::Resettable for EVENTS_LOOPSDONE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/pwm0_ns/events_pwmperiodend.rs b/pacs/nrf9120-pac/src/pwm0_ns/events_pwmperiodend.rs new file mode 100644 index 00000000..8fe0f582 --- /dev/null +++ b/pacs/nrf9120-pac/src/pwm0_ns/events_pwmperiodend.rs @@ -0,0 +1,127 @@ +#[doc = "Register `EVENTS_PWMPERIODEND` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVENTS_PWMPERIODEND` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `EVENTS_PWMPERIODEND` reader - Emitted at the end of each PWM period"] +pub type EVENTS_PWMPERIODEND_R = crate::BitReader; +#[doc = "Emitted at the end of each PWM period\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum EVENTS_PWMPERIODEND_A { + #[doc = "0: Event not generated"] + NOT_GENERATED = 0, + #[doc = "1: Event generated"] + GENERATED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: EVENTS_PWMPERIODEND_A) -> Self { + variant as u8 != 0 + } +} +impl EVENTS_PWMPERIODEND_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EVENTS_PWMPERIODEND_A { + match self.bits { + false => EVENTS_PWMPERIODEND_A::NOT_GENERATED, + true => EVENTS_PWMPERIODEND_A::GENERATED, + } + } + #[doc = "Checks if the value of the field is `NOT_GENERATED`"] + #[inline(always)] + pub fn is_not_generated(&self) -> bool { + *self == EVENTS_PWMPERIODEND_A::NOT_GENERATED + } + #[doc = "Checks if the value of the field is `GENERATED`"] + #[inline(always)] + pub fn is_generated(&self) -> bool { + *self == EVENTS_PWMPERIODEND_A::GENERATED + } +} +#[doc = "Field `EVENTS_PWMPERIODEND` writer - Emitted at the end of each PWM period"] +pub type EVENTS_PWMPERIODEND_W<'a, const O: u8> = + crate::BitWriter<'a, u32, EVENTS_PWMPERIODEND_SPEC, EVENTS_PWMPERIODEND_A, O>; +impl<'a, const O: u8> EVENTS_PWMPERIODEND_W<'a, O> { + #[doc = "Event not generated"] + #[inline(always)] + pub fn not_generated(self) -> &'a mut W { + self.variant(EVENTS_PWMPERIODEND_A::NOT_GENERATED) + } + #[doc = "Event generated"] + #[inline(always)] + pub fn generated(self) -> &'a mut W { + self.variant(EVENTS_PWMPERIODEND_A::GENERATED) + } +} +impl R { + #[doc = "Bit 0 - Emitted at the end of each PWM period"] + #[inline(always)] + pub fn events_pwmperiodend(&self) -> EVENTS_PWMPERIODEND_R { + EVENTS_PWMPERIODEND_R::new((self.bits & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Emitted at the end of each PWM period"] + #[inline(always)] + pub fn events_pwmperiodend(&mut self) -> EVENTS_PWMPERIODEND_W<0> { + EVENTS_PWMPERIODEND_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Emitted at the end of each PWM period\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [events_pwmperiodend](index.html) module"] +pub struct EVENTS_PWMPERIODEND_SPEC; +impl crate::RegisterSpec for EVENTS_PWMPERIODEND_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [events_pwmperiodend::R](R) reader structure"] +impl crate::Readable for EVENTS_PWMPERIODEND_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [events_pwmperiodend::W](W) writer structure"] +impl crate::Writable for EVENTS_PWMPERIODEND_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EVENTS_PWMPERIODEND to value 0"] +impl crate::Resettable for EVENTS_PWMPERIODEND_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/pwm0_ns/events_seqend.rs b/pacs/nrf9120-pac/src/pwm0_ns/events_seqend.rs new file mode 100644 index 00000000..b01763d3 --- /dev/null +++ b/pacs/nrf9120-pac/src/pwm0_ns/events_seqend.rs @@ -0,0 +1,128 @@ +#[doc = "Register `EVENTS_SEQEND[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVENTS_SEQEND[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `EVENTS_SEQEND` reader - Emitted at end of every sequence n, when last value from RAM has been applied to wave counter"] +pub type EVENTS_SEQEND_R = crate::BitReader; +#[doc = "Emitted at end of every sequence n, when last value from RAM has been applied to wave counter\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum EVENTS_SEQEND_A { + #[doc = "0: Event not generated"] + NOT_GENERATED = 0, + #[doc = "1: Event generated"] + GENERATED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: EVENTS_SEQEND_A) -> Self { + variant as u8 != 0 + } +} +impl EVENTS_SEQEND_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EVENTS_SEQEND_A { + match self.bits { + false => EVENTS_SEQEND_A::NOT_GENERATED, + true => EVENTS_SEQEND_A::GENERATED, + } + } + #[doc = "Checks if the value of the field is `NOT_GENERATED`"] + #[inline(always)] + pub fn is_not_generated(&self) -> bool { + *self == EVENTS_SEQEND_A::NOT_GENERATED + } + #[doc = "Checks if the value of the field is `GENERATED`"] + #[inline(always)] + pub fn is_generated(&self) -> bool { + *self == EVENTS_SEQEND_A::GENERATED + } +} +#[doc = "Field `EVENTS_SEQEND` writer - Emitted at end of every sequence n, when last value from RAM has been applied to wave counter"] +pub type EVENTS_SEQEND_W<'a, const O: u8> = + crate::BitWriter<'a, u32, EVENTS_SEQEND_SPEC, EVENTS_SEQEND_A, O>; +impl<'a, const O: u8> EVENTS_SEQEND_W<'a, O> { + #[doc = "Event not generated"] + #[inline(always)] + pub fn not_generated(self) -> &'a mut W { + self.variant(EVENTS_SEQEND_A::NOT_GENERATED) + } + #[doc = "Event generated"] + #[inline(always)] + pub fn generated(self) -> &'a mut W { + self.variant(EVENTS_SEQEND_A::GENERATED) + } +} +impl R { + #[doc = "Bit 0 - Emitted at end of every sequence n, when last value from RAM has been applied to wave counter"] + #[inline(always)] + pub fn events_seqend(&self) -> EVENTS_SEQEND_R { + EVENTS_SEQEND_R::new((self.bits & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Emitted at end of every sequence n, when last value from RAM has been applied to wave counter"] + #[inline(always)] + pub fn events_seqend(&mut self) -> EVENTS_SEQEND_W<0> { + EVENTS_SEQEND_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Description collection: Emitted at end of every sequence n, when last value from RAM has been applied to wave counter\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [events_seqend](index.html) module"] +pub struct EVENTS_SEQEND_SPEC; +impl crate::RegisterSpec for EVENTS_SEQEND_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [events_seqend::R](R) reader structure"] +impl crate::Readable for EVENTS_SEQEND_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [events_seqend::W](W) writer structure"] +impl crate::Writable for EVENTS_SEQEND_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EVENTS_SEQEND[%s] +to value 0"] +impl crate::Resettable for EVENTS_SEQEND_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/pwm0_ns/events_seqstarted.rs b/pacs/nrf9120-pac/src/pwm0_ns/events_seqstarted.rs new file mode 100644 index 00000000..b2611db4 --- /dev/null +++ b/pacs/nrf9120-pac/src/pwm0_ns/events_seqstarted.rs @@ -0,0 +1,128 @@ +#[doc = "Register `EVENTS_SEQSTARTED[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVENTS_SEQSTARTED[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `EVENTS_SEQSTARTED` reader - First PWM period started on sequence n"] +pub type EVENTS_SEQSTARTED_R = crate::BitReader; +#[doc = "First PWM period started on sequence n\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum EVENTS_SEQSTARTED_A { + #[doc = "0: Event not generated"] + NOT_GENERATED = 0, + #[doc = "1: Event generated"] + GENERATED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: EVENTS_SEQSTARTED_A) -> Self { + variant as u8 != 0 + } +} +impl EVENTS_SEQSTARTED_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EVENTS_SEQSTARTED_A { + match self.bits { + false => EVENTS_SEQSTARTED_A::NOT_GENERATED, + true => EVENTS_SEQSTARTED_A::GENERATED, + } + } + #[doc = "Checks if the value of the field is `NOT_GENERATED`"] + #[inline(always)] + pub fn is_not_generated(&self) -> bool { + *self == EVENTS_SEQSTARTED_A::NOT_GENERATED + } + #[doc = "Checks if the value of the field is `GENERATED`"] + #[inline(always)] + pub fn is_generated(&self) -> bool { + *self == EVENTS_SEQSTARTED_A::GENERATED + } +} +#[doc = "Field `EVENTS_SEQSTARTED` writer - First PWM period started on sequence n"] +pub type EVENTS_SEQSTARTED_W<'a, const O: u8> = + crate::BitWriter<'a, u32, EVENTS_SEQSTARTED_SPEC, EVENTS_SEQSTARTED_A, O>; +impl<'a, const O: u8> EVENTS_SEQSTARTED_W<'a, O> { + #[doc = "Event not generated"] + #[inline(always)] + pub fn not_generated(self) -> &'a mut W { + self.variant(EVENTS_SEQSTARTED_A::NOT_GENERATED) + } + #[doc = "Event generated"] + #[inline(always)] + pub fn generated(self) -> &'a mut W { + self.variant(EVENTS_SEQSTARTED_A::GENERATED) + } +} +impl R { + #[doc = "Bit 0 - First PWM period started on sequence n"] + #[inline(always)] + pub fn events_seqstarted(&self) -> EVENTS_SEQSTARTED_R { + EVENTS_SEQSTARTED_R::new((self.bits & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - First PWM period started on sequence n"] + #[inline(always)] + pub fn events_seqstarted(&mut self) -> EVENTS_SEQSTARTED_W<0> { + EVENTS_SEQSTARTED_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Description collection: First PWM period started on sequence n\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [events_seqstarted](index.html) module"] +pub struct EVENTS_SEQSTARTED_SPEC; +impl crate::RegisterSpec for EVENTS_SEQSTARTED_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [events_seqstarted::R](R) reader structure"] +impl crate::Readable for EVENTS_SEQSTARTED_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [events_seqstarted::W](W) writer structure"] +impl crate::Writable for EVENTS_SEQSTARTED_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EVENTS_SEQSTARTED[%s] +to value 0"] +impl crate::Resettable for EVENTS_SEQSTARTED_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/pwm0_ns/events_stopped.rs b/pacs/nrf9120-pac/src/pwm0_ns/events_stopped.rs new file mode 100644 index 00000000..63011861 --- /dev/null +++ b/pacs/nrf9120-pac/src/pwm0_ns/events_stopped.rs @@ -0,0 +1,127 @@ +#[doc = "Register `EVENTS_STOPPED` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVENTS_STOPPED` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `EVENTS_STOPPED` reader - Response to STOP task, emitted when PWM pulses are no longer generated"] +pub type EVENTS_STOPPED_R = crate::BitReader; +#[doc = "Response to STOP task, emitted when PWM pulses are no longer generated\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum EVENTS_STOPPED_A { + #[doc = "0: Event not generated"] + NOT_GENERATED = 0, + #[doc = "1: Event generated"] + GENERATED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: EVENTS_STOPPED_A) -> Self { + variant as u8 != 0 + } +} +impl EVENTS_STOPPED_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EVENTS_STOPPED_A { + match self.bits { + false => EVENTS_STOPPED_A::NOT_GENERATED, + true => EVENTS_STOPPED_A::GENERATED, + } + } + #[doc = "Checks if the value of the field is `NOT_GENERATED`"] + #[inline(always)] + pub fn is_not_generated(&self) -> bool { + *self == EVENTS_STOPPED_A::NOT_GENERATED + } + #[doc = "Checks if the value of the field is `GENERATED`"] + #[inline(always)] + pub fn is_generated(&self) -> bool { + *self == EVENTS_STOPPED_A::GENERATED + } +} +#[doc = "Field `EVENTS_STOPPED` writer - Response to STOP task, emitted when PWM pulses are no longer generated"] +pub type EVENTS_STOPPED_W<'a, const O: u8> = + crate::BitWriter<'a, u32, EVENTS_STOPPED_SPEC, EVENTS_STOPPED_A, O>; +impl<'a, const O: u8> EVENTS_STOPPED_W<'a, O> { + #[doc = "Event not generated"] + #[inline(always)] + pub fn not_generated(self) -> &'a mut W { + self.variant(EVENTS_STOPPED_A::NOT_GENERATED) + } + #[doc = "Event generated"] + #[inline(always)] + pub fn generated(self) -> &'a mut W { + self.variant(EVENTS_STOPPED_A::GENERATED) + } +} +impl R { + #[doc = "Bit 0 - Response to STOP task, emitted when PWM pulses are no longer generated"] + #[inline(always)] + pub fn events_stopped(&self) -> EVENTS_STOPPED_R { + EVENTS_STOPPED_R::new((self.bits & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Response to STOP task, emitted when PWM pulses are no longer generated"] + #[inline(always)] + pub fn events_stopped(&mut self) -> EVENTS_STOPPED_W<0> { + EVENTS_STOPPED_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Response to STOP task, emitted when PWM pulses are no longer generated\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [events_stopped](index.html) module"] +pub struct EVENTS_STOPPED_SPEC; +impl crate::RegisterSpec for EVENTS_STOPPED_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [events_stopped::R](R) reader structure"] +impl crate::Readable for EVENTS_STOPPED_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [events_stopped::W](W) writer structure"] +impl crate::Writable for EVENTS_STOPPED_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EVENTS_STOPPED to value 0"] +impl crate::Resettable for EVENTS_STOPPED_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/pwm0_ns/inten.rs b/pacs/nrf9120-pac/src/pwm0_ns/inten.rs new file mode 100644 index 00000000..74b1759f --- /dev/null +++ b/pacs/nrf9120-pac/src/pwm0_ns/inten.rs @@ -0,0 +1,486 @@ +#[doc = "Register `INTEN` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTEN` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `STOPPED` reader - Enable or disable interrupt for event STOPPED"] +pub type STOPPED_R = crate::BitReader; +#[doc = "Enable or disable interrupt for event STOPPED\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum STOPPED_A { + #[doc = "0: Disable"] + DISABLED = 0, + #[doc = "1: Enable"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: STOPPED_A) -> Self { + variant as u8 != 0 + } +} +impl STOPPED_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> STOPPED_A { + match self.bits { + false => STOPPED_A::DISABLED, + true => STOPPED_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == STOPPED_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == STOPPED_A::ENABLED + } +} +#[doc = "Field `STOPPED` writer - Enable or disable interrupt for event STOPPED"] +pub type STOPPED_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTEN_SPEC, STOPPED_A, O>; +impl<'a, const O: u8> STOPPED_W<'a, O> { + #[doc = "Disable"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(STOPPED_A::DISABLED) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(STOPPED_A::ENABLED) + } +} +#[doc = "Field `SEQSTARTED0` reader - Enable or disable interrupt for event SEQSTARTED\\[0\\]"] +pub type SEQSTARTED0_R = crate::BitReader; +#[doc = "Enable or disable interrupt for event SEQSTARTED\\[0\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum SEQSTARTED0_A { + #[doc = "0: Disable"] + DISABLED = 0, + #[doc = "1: Enable"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: SEQSTARTED0_A) -> Self { + variant as u8 != 0 + } +} +impl SEQSTARTED0_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> SEQSTARTED0_A { + match self.bits { + false => SEQSTARTED0_A::DISABLED, + true => SEQSTARTED0_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == SEQSTARTED0_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == SEQSTARTED0_A::ENABLED + } +} +#[doc = "Field `SEQSTARTED0` writer - Enable or disable interrupt for event SEQSTARTED\\[0\\]"] +pub type SEQSTARTED0_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTEN_SPEC, SEQSTARTED0_A, O>; +impl<'a, const O: u8> SEQSTARTED0_W<'a, O> { + #[doc = "Disable"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(SEQSTARTED0_A::DISABLED) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(SEQSTARTED0_A::ENABLED) + } +} +#[doc = "Field `SEQSTARTED1` reader - Enable or disable interrupt for event SEQSTARTED\\[1\\]"] +pub type SEQSTARTED1_R = crate::BitReader; +#[doc = "Enable or disable interrupt for event SEQSTARTED\\[1\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum SEQSTARTED1_A { + #[doc = "0: Disable"] + DISABLED = 0, + #[doc = "1: Enable"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: SEQSTARTED1_A) -> Self { + variant as u8 != 0 + } +} +impl SEQSTARTED1_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> SEQSTARTED1_A { + match self.bits { + false => SEQSTARTED1_A::DISABLED, + true => SEQSTARTED1_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == SEQSTARTED1_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == SEQSTARTED1_A::ENABLED + } +} +#[doc = "Field `SEQSTARTED1` writer - Enable or disable interrupt for event SEQSTARTED\\[1\\]"] +pub type SEQSTARTED1_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTEN_SPEC, SEQSTARTED1_A, O>; +impl<'a, const O: u8> SEQSTARTED1_W<'a, O> { + #[doc = "Disable"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(SEQSTARTED1_A::DISABLED) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(SEQSTARTED1_A::ENABLED) + } +} +#[doc = "Field `SEQEND0` reader - Enable or disable interrupt for event SEQEND\\[0\\]"] +pub type SEQEND0_R = crate::BitReader; +#[doc = "Enable or disable interrupt for event SEQEND\\[0\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum SEQEND0_A { + #[doc = "0: Disable"] + DISABLED = 0, + #[doc = "1: Enable"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: SEQEND0_A) -> Self { + variant as u8 != 0 + } +} +impl SEQEND0_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> SEQEND0_A { + match self.bits { + false => SEQEND0_A::DISABLED, + true => SEQEND0_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == SEQEND0_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == SEQEND0_A::ENABLED + } +} +#[doc = "Field `SEQEND0` writer - Enable or disable interrupt for event SEQEND\\[0\\]"] +pub type SEQEND0_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTEN_SPEC, SEQEND0_A, O>; +impl<'a, const O: u8> SEQEND0_W<'a, O> { + #[doc = "Disable"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(SEQEND0_A::DISABLED) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(SEQEND0_A::ENABLED) + } +} +#[doc = "Field `SEQEND1` reader - Enable or disable interrupt for event SEQEND\\[1\\]"] +pub type SEQEND1_R = crate::BitReader; +#[doc = "Enable or disable interrupt for event SEQEND\\[1\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum SEQEND1_A { + #[doc = "0: Disable"] + DISABLED = 0, + #[doc = "1: Enable"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: SEQEND1_A) -> Self { + variant as u8 != 0 + } +} +impl SEQEND1_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> SEQEND1_A { + match self.bits { + false => SEQEND1_A::DISABLED, + true => SEQEND1_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == SEQEND1_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == SEQEND1_A::ENABLED + } +} +#[doc = "Field `SEQEND1` writer - Enable or disable interrupt for event SEQEND\\[1\\]"] +pub type SEQEND1_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTEN_SPEC, SEQEND1_A, O>; +impl<'a, const O: u8> SEQEND1_W<'a, O> { + #[doc = "Disable"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(SEQEND1_A::DISABLED) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(SEQEND1_A::ENABLED) + } +} +#[doc = "Field `PWMPERIODEND` reader - Enable or disable interrupt for event PWMPERIODEND"] +pub type PWMPERIODEND_R = crate::BitReader; +#[doc = "Enable or disable interrupt for event PWMPERIODEND\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PWMPERIODEND_A { + #[doc = "0: Disable"] + DISABLED = 0, + #[doc = "1: Enable"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PWMPERIODEND_A) -> Self { + variant as u8 != 0 + } +} +impl PWMPERIODEND_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PWMPERIODEND_A { + match self.bits { + false => PWMPERIODEND_A::DISABLED, + true => PWMPERIODEND_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == PWMPERIODEND_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == PWMPERIODEND_A::ENABLED + } +} +#[doc = "Field `PWMPERIODEND` writer - Enable or disable interrupt for event PWMPERIODEND"] +pub type PWMPERIODEND_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTEN_SPEC, PWMPERIODEND_A, O>; +impl<'a, const O: u8> PWMPERIODEND_W<'a, O> { + #[doc = "Disable"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(PWMPERIODEND_A::DISABLED) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(PWMPERIODEND_A::ENABLED) + } +} +#[doc = "Field `LOOPSDONE` reader - Enable or disable interrupt for event LOOPSDONE"] +pub type LOOPSDONE_R = crate::BitReader; +#[doc = "Enable or disable interrupt for event LOOPSDONE\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum LOOPSDONE_A { + #[doc = "0: Disable"] + DISABLED = 0, + #[doc = "1: Enable"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: LOOPSDONE_A) -> Self { + variant as u8 != 0 + } +} +impl LOOPSDONE_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> LOOPSDONE_A { + match self.bits { + false => LOOPSDONE_A::DISABLED, + true => LOOPSDONE_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == LOOPSDONE_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == LOOPSDONE_A::ENABLED + } +} +#[doc = "Field `LOOPSDONE` writer - Enable or disable interrupt for event LOOPSDONE"] +pub type LOOPSDONE_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTEN_SPEC, LOOPSDONE_A, O>; +impl<'a, const O: u8> LOOPSDONE_W<'a, O> { + #[doc = "Disable"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(LOOPSDONE_A::DISABLED) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(LOOPSDONE_A::ENABLED) + } +} +impl R { + #[doc = "Bit 1 - Enable or disable interrupt for event STOPPED"] + #[inline(always)] + pub fn stopped(&self) -> STOPPED_R { + STOPPED_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Enable or disable interrupt for event SEQSTARTED\\[0\\]"] + #[inline(always)] + pub fn seqstarted0(&self) -> SEQSTARTED0_R { + SEQSTARTED0_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Enable or disable interrupt for event SEQSTARTED\\[1\\]"] + #[inline(always)] + pub fn seqstarted1(&self) -> SEQSTARTED1_R { + SEQSTARTED1_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Enable or disable interrupt for event SEQEND\\[0\\]"] + #[inline(always)] + pub fn seqend0(&self) -> SEQEND0_R { + SEQEND0_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Enable or disable interrupt for event SEQEND\\[1\\]"] + #[inline(always)] + pub fn seqend1(&self) -> SEQEND1_R { + SEQEND1_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Enable or disable interrupt for event PWMPERIODEND"] + #[inline(always)] + pub fn pwmperiodend(&self) -> PWMPERIODEND_R { + PWMPERIODEND_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Enable or disable interrupt for event LOOPSDONE"] + #[inline(always)] + pub fn loopsdone(&self) -> LOOPSDONE_R { + LOOPSDONE_R::new(((self.bits >> 7) & 1) != 0) + } +} +impl W { + #[doc = "Bit 1 - Enable or disable interrupt for event STOPPED"] + #[inline(always)] + pub fn stopped(&mut self) -> STOPPED_W<1> { + STOPPED_W::new(self) + } + #[doc = "Bit 2 - Enable or disable interrupt for event SEQSTARTED\\[0\\]"] + #[inline(always)] + pub fn seqstarted0(&mut self) -> SEQSTARTED0_W<2> { + SEQSTARTED0_W::new(self) + } + #[doc = "Bit 3 - Enable or disable interrupt for event SEQSTARTED\\[1\\]"] + #[inline(always)] + pub fn seqstarted1(&mut self) -> SEQSTARTED1_W<3> { + SEQSTARTED1_W::new(self) + } + #[doc = "Bit 4 - Enable or disable interrupt for event SEQEND\\[0\\]"] + #[inline(always)] + pub fn seqend0(&mut self) -> SEQEND0_W<4> { + SEQEND0_W::new(self) + } + #[doc = "Bit 5 - Enable or disable interrupt for event SEQEND\\[1\\]"] + #[inline(always)] + pub fn seqend1(&mut self) -> SEQEND1_W<5> { + SEQEND1_W::new(self) + } + #[doc = "Bit 6 - Enable or disable interrupt for event PWMPERIODEND"] + #[inline(always)] + pub fn pwmperiodend(&mut self) -> PWMPERIODEND_W<6> { + PWMPERIODEND_W::new(self) + } + #[doc = "Bit 7 - Enable or disable interrupt for event LOOPSDONE"] + #[inline(always)] + pub fn loopsdone(&mut self) -> LOOPSDONE_W<7> { + LOOPSDONE_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Enable or disable interrupt\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [inten](index.html) module"] +pub struct INTEN_SPEC; +impl crate::RegisterSpec for INTEN_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [inten::R](R) reader structure"] +impl crate::Readable for INTEN_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [inten::W](W) writer structure"] +impl crate::Writable for INTEN_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTEN to value 0"] +impl crate::Resettable for INTEN_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/pwm0_ns/intenclr.rs b/pacs/nrf9120-pac/src/pwm0_ns/intenclr.rs new file mode 100644 index 00000000..448a2073 --- /dev/null +++ b/pacs/nrf9120-pac/src/pwm0_ns/intenclr.rs @@ -0,0 +1,538 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `STOPPED` reader - Write '1' to disable interrupt for event STOPPED"] +pub type STOPPED_R = crate::BitReader; +#[doc = "Write '1' to disable interrupt for event STOPPED\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum STOPPED_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: STOPPED_A) -> Self { + variant as u8 != 0 + } +} +impl STOPPED_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> STOPPED_A { + match self.bits { + false => STOPPED_A::DISABLED, + true => STOPPED_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == STOPPED_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == STOPPED_A::ENABLED + } +} +#[doc = "Write '1' to disable interrupt for event STOPPED\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum STOPPED_AW { + #[doc = "1: Disable"] + CLEAR = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: STOPPED_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `STOPPED` writer - Write '1' to disable interrupt for event STOPPED"] +pub type STOPPED_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENCLR_SPEC, STOPPED_AW, O>; +impl<'a, const O: u8> STOPPED_W<'a, O> { + #[doc = "Disable"] + #[inline(always)] + pub fn clear(self) -> &'a mut W { + self.variant(STOPPED_AW::CLEAR) + } +} +#[doc = "Field `SEQSTARTED0` reader - Write '1' to disable interrupt for event SEQSTARTED\\[0\\]"] +pub type SEQSTARTED0_R = crate::BitReader; +#[doc = "Write '1' to disable interrupt for event SEQSTARTED\\[0\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum SEQSTARTED0_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: SEQSTARTED0_A) -> Self { + variant as u8 != 0 + } +} +impl SEQSTARTED0_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> SEQSTARTED0_A { + match self.bits { + false => SEQSTARTED0_A::DISABLED, + true => SEQSTARTED0_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == SEQSTARTED0_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == SEQSTARTED0_A::ENABLED + } +} +#[doc = "Write '1' to disable interrupt for event SEQSTARTED\\[0\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum SEQSTARTED0_AW { + #[doc = "1: Disable"] + CLEAR = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: SEQSTARTED0_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SEQSTARTED0` writer - Write '1' to disable interrupt for event SEQSTARTED\\[0\\]"] +pub type SEQSTARTED0_W<'a, const O: u8> = + crate::BitWriter<'a, u32, INTENCLR_SPEC, SEQSTARTED0_AW, O>; +impl<'a, const O: u8> SEQSTARTED0_W<'a, O> { + #[doc = "Disable"] + #[inline(always)] + pub fn clear(self) -> &'a mut W { + self.variant(SEQSTARTED0_AW::CLEAR) + } +} +#[doc = "Field `SEQSTARTED1` reader - Write '1' to disable interrupt for event SEQSTARTED\\[1\\]"] +pub type SEQSTARTED1_R = crate::BitReader; +#[doc = "Write '1' to disable interrupt for event SEQSTARTED\\[1\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum SEQSTARTED1_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: SEQSTARTED1_A) -> Self { + variant as u8 != 0 + } +} +impl SEQSTARTED1_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> SEQSTARTED1_A { + match self.bits { + false => SEQSTARTED1_A::DISABLED, + true => SEQSTARTED1_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == SEQSTARTED1_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == SEQSTARTED1_A::ENABLED + } +} +#[doc = "Write '1' to disable interrupt for event SEQSTARTED\\[1\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum SEQSTARTED1_AW { + #[doc = "1: Disable"] + CLEAR = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: SEQSTARTED1_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SEQSTARTED1` writer - Write '1' to disable interrupt for event SEQSTARTED\\[1\\]"] +pub type SEQSTARTED1_W<'a, const O: u8> = + crate::BitWriter<'a, u32, INTENCLR_SPEC, SEQSTARTED1_AW, O>; +impl<'a, const O: u8> SEQSTARTED1_W<'a, O> { + #[doc = "Disable"] + #[inline(always)] + pub fn clear(self) -> &'a mut W { + self.variant(SEQSTARTED1_AW::CLEAR) + } +} +#[doc = "Field `SEQEND0` reader - Write '1' to disable interrupt for event SEQEND\\[0\\]"] +pub type SEQEND0_R = crate::BitReader; +#[doc = "Write '1' to disable interrupt for event SEQEND\\[0\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum SEQEND0_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: SEQEND0_A) -> Self { + variant as u8 != 0 + } +} +impl SEQEND0_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> SEQEND0_A { + match self.bits { + false => SEQEND0_A::DISABLED, + true => SEQEND0_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == SEQEND0_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == SEQEND0_A::ENABLED + } +} +#[doc = "Write '1' to disable interrupt for event SEQEND\\[0\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum SEQEND0_AW { + #[doc = "1: Disable"] + CLEAR = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: SEQEND0_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SEQEND0` writer - Write '1' to disable interrupt for event SEQEND\\[0\\]"] +pub type SEQEND0_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENCLR_SPEC, SEQEND0_AW, O>; +impl<'a, const O: u8> SEQEND0_W<'a, O> { + #[doc = "Disable"] + #[inline(always)] + pub fn clear(self) -> &'a mut W { + self.variant(SEQEND0_AW::CLEAR) + } +} +#[doc = "Field `SEQEND1` reader - Write '1' to disable interrupt for event SEQEND\\[1\\]"] +pub type SEQEND1_R = crate::BitReader; +#[doc = "Write '1' to disable interrupt for event SEQEND\\[1\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum SEQEND1_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: SEQEND1_A) -> Self { + variant as u8 != 0 + } +} +impl SEQEND1_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> SEQEND1_A { + match self.bits { + false => SEQEND1_A::DISABLED, + true => SEQEND1_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == SEQEND1_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == SEQEND1_A::ENABLED + } +} +#[doc = "Write '1' to disable interrupt for event SEQEND\\[1\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum SEQEND1_AW { + #[doc = "1: Disable"] + CLEAR = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: SEQEND1_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SEQEND1` writer - Write '1' to disable interrupt for event SEQEND\\[1\\]"] +pub type SEQEND1_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENCLR_SPEC, SEQEND1_AW, O>; +impl<'a, const O: u8> SEQEND1_W<'a, O> { + #[doc = "Disable"] + #[inline(always)] + pub fn clear(self) -> &'a mut W { + self.variant(SEQEND1_AW::CLEAR) + } +} +#[doc = "Field `PWMPERIODEND` reader - Write '1' to disable interrupt for event PWMPERIODEND"] +pub type PWMPERIODEND_R = crate::BitReader; +#[doc = "Write '1' to disable interrupt for event PWMPERIODEND\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PWMPERIODEND_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PWMPERIODEND_A) -> Self { + variant as u8 != 0 + } +} +impl PWMPERIODEND_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PWMPERIODEND_A { + match self.bits { + false => PWMPERIODEND_A::DISABLED, + true => PWMPERIODEND_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == PWMPERIODEND_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == PWMPERIODEND_A::ENABLED + } +} +#[doc = "Write '1' to disable interrupt for event PWMPERIODEND\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PWMPERIODEND_AW { + #[doc = "1: Disable"] + CLEAR = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PWMPERIODEND_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PWMPERIODEND` writer - Write '1' to disable interrupt for event PWMPERIODEND"] +pub type PWMPERIODEND_W<'a, const O: u8> = + crate::BitWriter<'a, u32, INTENCLR_SPEC, PWMPERIODEND_AW, O>; +impl<'a, const O: u8> PWMPERIODEND_W<'a, O> { + #[doc = "Disable"] + #[inline(always)] + pub fn clear(self) -> &'a mut W { + self.variant(PWMPERIODEND_AW::CLEAR) + } +} +#[doc = "Field `LOOPSDONE` reader - Write '1' to disable interrupt for event LOOPSDONE"] +pub type LOOPSDONE_R = crate::BitReader; +#[doc = "Write '1' to disable interrupt for event LOOPSDONE\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum LOOPSDONE_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: LOOPSDONE_A) -> Self { + variant as u8 != 0 + } +} +impl LOOPSDONE_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> LOOPSDONE_A { + match self.bits { + false => LOOPSDONE_A::DISABLED, + true => LOOPSDONE_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == LOOPSDONE_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == LOOPSDONE_A::ENABLED + } +} +#[doc = "Write '1' to disable interrupt for event LOOPSDONE\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum LOOPSDONE_AW { + #[doc = "1: Disable"] + CLEAR = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: LOOPSDONE_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LOOPSDONE` writer - Write '1' to disable interrupt for event LOOPSDONE"] +pub type LOOPSDONE_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENCLR_SPEC, LOOPSDONE_AW, O>; +impl<'a, const O: u8> LOOPSDONE_W<'a, O> { + #[doc = "Disable"] + #[inline(always)] + pub fn clear(self) -> &'a mut W { + self.variant(LOOPSDONE_AW::CLEAR) + } +} +impl R { + #[doc = "Bit 1 - Write '1' to disable interrupt for event STOPPED"] + #[inline(always)] + pub fn stopped(&self) -> STOPPED_R { + STOPPED_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Write '1' to disable interrupt for event SEQSTARTED\\[0\\]"] + #[inline(always)] + pub fn seqstarted0(&self) -> SEQSTARTED0_R { + SEQSTARTED0_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Write '1' to disable interrupt for event SEQSTARTED\\[1\\]"] + #[inline(always)] + pub fn seqstarted1(&self) -> SEQSTARTED1_R { + SEQSTARTED1_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Write '1' to disable interrupt for event SEQEND\\[0\\]"] + #[inline(always)] + pub fn seqend0(&self) -> SEQEND0_R { + SEQEND0_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Write '1' to disable interrupt for event SEQEND\\[1\\]"] + #[inline(always)] + pub fn seqend1(&self) -> SEQEND1_R { + SEQEND1_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Write '1' to disable interrupt for event PWMPERIODEND"] + #[inline(always)] + pub fn pwmperiodend(&self) -> PWMPERIODEND_R { + PWMPERIODEND_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Write '1' to disable interrupt for event LOOPSDONE"] + #[inline(always)] + pub fn loopsdone(&self) -> LOOPSDONE_R { + LOOPSDONE_R::new(((self.bits >> 7) & 1) != 0) + } +} +impl W { + #[doc = "Bit 1 - Write '1' to disable interrupt for event STOPPED"] + #[inline(always)] + pub fn stopped(&mut self) -> STOPPED_W<1> { + STOPPED_W::new(self) + } + #[doc = "Bit 2 - Write '1' to disable interrupt for event SEQSTARTED\\[0\\]"] + #[inline(always)] + pub fn seqstarted0(&mut self) -> SEQSTARTED0_W<2> { + SEQSTARTED0_W::new(self) + } + #[doc = "Bit 3 - Write '1' to disable interrupt for event SEQSTARTED\\[1\\]"] + #[inline(always)] + pub fn seqstarted1(&mut self) -> SEQSTARTED1_W<3> { + SEQSTARTED1_W::new(self) + } + #[doc = "Bit 4 - Write '1' to disable interrupt for event SEQEND\\[0\\]"] + #[inline(always)] + pub fn seqend0(&mut self) -> SEQEND0_W<4> { + SEQEND0_W::new(self) + } + #[doc = "Bit 5 - Write '1' to disable interrupt for event SEQEND\\[1\\]"] + #[inline(always)] + pub fn seqend1(&mut self) -> SEQEND1_W<5> { + SEQEND1_W::new(self) + } + #[doc = "Bit 6 - Write '1' to disable interrupt for event PWMPERIODEND"] + #[inline(always)] + pub fn pwmperiodend(&mut self) -> PWMPERIODEND_W<6> { + PWMPERIODEND_W::new(self) + } + #[doc = "Bit 7 - Write '1' to disable interrupt for event LOOPSDONE"] + #[inline(always)] + pub fn loopsdone(&mut self) -> LOOPSDONE_W<7> { + LOOPSDONE_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Disable interrupt\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/pwm0_ns/intenset.rs b/pacs/nrf9120-pac/src/pwm0_ns/intenset.rs new file mode 100644 index 00000000..46cd7633 --- /dev/null +++ b/pacs/nrf9120-pac/src/pwm0_ns/intenset.rs @@ -0,0 +1,538 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `STOPPED` reader - Write '1' to enable interrupt for event STOPPED"] +pub type STOPPED_R = crate::BitReader; +#[doc = "Write '1' to enable interrupt for event STOPPED\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum STOPPED_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: STOPPED_A) -> Self { + variant as u8 != 0 + } +} +impl STOPPED_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> STOPPED_A { + match self.bits { + false => STOPPED_A::DISABLED, + true => STOPPED_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == STOPPED_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == STOPPED_A::ENABLED + } +} +#[doc = "Write '1' to enable interrupt for event STOPPED\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum STOPPED_AW { + #[doc = "1: Enable"] + SET = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: STOPPED_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `STOPPED` writer - Write '1' to enable interrupt for event STOPPED"] +pub type STOPPED_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENSET_SPEC, STOPPED_AW, O>; +impl<'a, const O: u8> STOPPED_W<'a, O> { + #[doc = "Enable"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(STOPPED_AW::SET) + } +} +#[doc = "Field `SEQSTARTED0` reader - Write '1' to enable interrupt for event SEQSTARTED\\[0\\]"] +pub type SEQSTARTED0_R = crate::BitReader; +#[doc = "Write '1' to enable interrupt for event SEQSTARTED\\[0\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum SEQSTARTED0_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: SEQSTARTED0_A) -> Self { + variant as u8 != 0 + } +} +impl SEQSTARTED0_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> SEQSTARTED0_A { + match self.bits { + false => SEQSTARTED0_A::DISABLED, + true => SEQSTARTED0_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == SEQSTARTED0_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == SEQSTARTED0_A::ENABLED + } +} +#[doc = "Write '1' to enable interrupt for event SEQSTARTED\\[0\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum SEQSTARTED0_AW { + #[doc = "1: Enable"] + SET = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: SEQSTARTED0_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SEQSTARTED0` writer - Write '1' to enable interrupt for event SEQSTARTED\\[0\\]"] +pub type SEQSTARTED0_W<'a, const O: u8> = + crate::BitWriter<'a, u32, INTENSET_SPEC, SEQSTARTED0_AW, O>; +impl<'a, const O: u8> SEQSTARTED0_W<'a, O> { + #[doc = "Enable"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(SEQSTARTED0_AW::SET) + } +} +#[doc = "Field `SEQSTARTED1` reader - Write '1' to enable interrupt for event SEQSTARTED\\[1\\]"] +pub type SEQSTARTED1_R = crate::BitReader; +#[doc = "Write '1' to enable interrupt for event SEQSTARTED\\[1\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum SEQSTARTED1_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: SEQSTARTED1_A) -> Self { + variant as u8 != 0 + } +} +impl SEQSTARTED1_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> SEQSTARTED1_A { + match self.bits { + false => SEQSTARTED1_A::DISABLED, + true => SEQSTARTED1_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == SEQSTARTED1_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == SEQSTARTED1_A::ENABLED + } +} +#[doc = "Write '1' to enable interrupt for event SEQSTARTED\\[1\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum SEQSTARTED1_AW { + #[doc = "1: Enable"] + SET = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: SEQSTARTED1_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SEQSTARTED1` writer - Write '1' to enable interrupt for event SEQSTARTED\\[1\\]"] +pub type SEQSTARTED1_W<'a, const O: u8> = + crate::BitWriter<'a, u32, INTENSET_SPEC, SEQSTARTED1_AW, O>; +impl<'a, const O: u8> SEQSTARTED1_W<'a, O> { + #[doc = "Enable"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(SEQSTARTED1_AW::SET) + } +} +#[doc = "Field `SEQEND0` reader - Write '1' to enable interrupt for event SEQEND\\[0\\]"] +pub type SEQEND0_R = crate::BitReader; +#[doc = "Write '1' to enable interrupt for event SEQEND\\[0\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum SEQEND0_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: SEQEND0_A) -> Self { + variant as u8 != 0 + } +} +impl SEQEND0_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> SEQEND0_A { + match self.bits { + false => SEQEND0_A::DISABLED, + true => SEQEND0_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == SEQEND0_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == SEQEND0_A::ENABLED + } +} +#[doc = "Write '1' to enable interrupt for event SEQEND\\[0\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum SEQEND0_AW { + #[doc = "1: Enable"] + SET = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: SEQEND0_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SEQEND0` writer - Write '1' to enable interrupt for event SEQEND\\[0\\]"] +pub type SEQEND0_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENSET_SPEC, SEQEND0_AW, O>; +impl<'a, const O: u8> SEQEND0_W<'a, O> { + #[doc = "Enable"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(SEQEND0_AW::SET) + } +} +#[doc = "Field `SEQEND1` reader - Write '1' to enable interrupt for event SEQEND\\[1\\]"] +pub type SEQEND1_R = crate::BitReader; +#[doc = "Write '1' to enable interrupt for event SEQEND\\[1\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum SEQEND1_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: SEQEND1_A) -> Self { + variant as u8 != 0 + } +} +impl SEQEND1_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> SEQEND1_A { + match self.bits { + false => SEQEND1_A::DISABLED, + true => SEQEND1_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == SEQEND1_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == SEQEND1_A::ENABLED + } +} +#[doc = "Write '1' to enable interrupt for event SEQEND\\[1\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum SEQEND1_AW { + #[doc = "1: Enable"] + SET = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: SEQEND1_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SEQEND1` writer - Write '1' to enable interrupt for event SEQEND\\[1\\]"] +pub type SEQEND1_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENSET_SPEC, SEQEND1_AW, O>; +impl<'a, const O: u8> SEQEND1_W<'a, O> { + #[doc = "Enable"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(SEQEND1_AW::SET) + } +} +#[doc = "Field `PWMPERIODEND` reader - Write '1' to enable interrupt for event PWMPERIODEND"] +pub type PWMPERIODEND_R = crate::BitReader; +#[doc = "Write '1' to enable interrupt for event PWMPERIODEND\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PWMPERIODEND_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PWMPERIODEND_A) -> Self { + variant as u8 != 0 + } +} +impl PWMPERIODEND_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PWMPERIODEND_A { + match self.bits { + false => PWMPERIODEND_A::DISABLED, + true => PWMPERIODEND_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == PWMPERIODEND_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == PWMPERIODEND_A::ENABLED + } +} +#[doc = "Write '1' to enable interrupt for event PWMPERIODEND\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PWMPERIODEND_AW { + #[doc = "1: Enable"] + SET = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PWMPERIODEND_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PWMPERIODEND` writer - Write '1' to enable interrupt for event PWMPERIODEND"] +pub type PWMPERIODEND_W<'a, const O: u8> = + crate::BitWriter<'a, u32, INTENSET_SPEC, PWMPERIODEND_AW, O>; +impl<'a, const O: u8> PWMPERIODEND_W<'a, O> { + #[doc = "Enable"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(PWMPERIODEND_AW::SET) + } +} +#[doc = "Field `LOOPSDONE` reader - Write '1' to enable interrupt for event LOOPSDONE"] +pub type LOOPSDONE_R = crate::BitReader; +#[doc = "Write '1' to enable interrupt for event LOOPSDONE\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum LOOPSDONE_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: LOOPSDONE_A) -> Self { + variant as u8 != 0 + } +} +impl LOOPSDONE_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> LOOPSDONE_A { + match self.bits { + false => LOOPSDONE_A::DISABLED, + true => LOOPSDONE_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == LOOPSDONE_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == LOOPSDONE_A::ENABLED + } +} +#[doc = "Write '1' to enable interrupt for event LOOPSDONE\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum LOOPSDONE_AW { + #[doc = "1: Enable"] + SET = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: LOOPSDONE_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LOOPSDONE` writer - Write '1' to enable interrupt for event LOOPSDONE"] +pub type LOOPSDONE_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENSET_SPEC, LOOPSDONE_AW, O>; +impl<'a, const O: u8> LOOPSDONE_W<'a, O> { + #[doc = "Enable"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(LOOPSDONE_AW::SET) + } +} +impl R { + #[doc = "Bit 1 - Write '1' to enable interrupt for event STOPPED"] + #[inline(always)] + pub fn stopped(&self) -> STOPPED_R { + STOPPED_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Write '1' to enable interrupt for event SEQSTARTED\\[0\\]"] + #[inline(always)] + pub fn seqstarted0(&self) -> SEQSTARTED0_R { + SEQSTARTED0_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Write '1' to enable interrupt for event SEQSTARTED\\[1\\]"] + #[inline(always)] + pub fn seqstarted1(&self) -> SEQSTARTED1_R { + SEQSTARTED1_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Write '1' to enable interrupt for event SEQEND\\[0\\]"] + #[inline(always)] + pub fn seqend0(&self) -> SEQEND0_R { + SEQEND0_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Write '1' to enable interrupt for event SEQEND\\[1\\]"] + #[inline(always)] + pub fn seqend1(&self) -> SEQEND1_R { + SEQEND1_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Write '1' to enable interrupt for event PWMPERIODEND"] + #[inline(always)] + pub fn pwmperiodend(&self) -> PWMPERIODEND_R { + PWMPERIODEND_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Write '1' to enable interrupt for event LOOPSDONE"] + #[inline(always)] + pub fn loopsdone(&self) -> LOOPSDONE_R { + LOOPSDONE_R::new(((self.bits >> 7) & 1) != 0) + } +} +impl W { + #[doc = "Bit 1 - Write '1' to enable interrupt for event STOPPED"] + #[inline(always)] + pub fn stopped(&mut self) -> STOPPED_W<1> { + STOPPED_W::new(self) + } + #[doc = "Bit 2 - Write '1' to enable interrupt for event SEQSTARTED\\[0\\]"] + #[inline(always)] + pub fn seqstarted0(&mut self) -> SEQSTARTED0_W<2> { + SEQSTARTED0_W::new(self) + } + #[doc = "Bit 3 - Write '1' to enable interrupt for event SEQSTARTED\\[1\\]"] + #[inline(always)] + pub fn seqstarted1(&mut self) -> SEQSTARTED1_W<3> { + SEQSTARTED1_W::new(self) + } + #[doc = "Bit 4 - Write '1' to enable interrupt for event SEQEND\\[0\\]"] + #[inline(always)] + pub fn seqend0(&mut self) -> SEQEND0_W<4> { + SEQEND0_W::new(self) + } + #[doc = "Bit 5 - Write '1' to enable interrupt for event SEQEND\\[1\\]"] + #[inline(always)] + pub fn seqend1(&mut self) -> SEQEND1_W<5> { + SEQEND1_W::new(self) + } + #[doc = "Bit 6 - Write '1' to enable interrupt for event PWMPERIODEND"] + #[inline(always)] + pub fn pwmperiodend(&mut self) -> PWMPERIODEND_W<6> { + PWMPERIODEND_W::new(self) + } + #[doc = "Bit 7 - Write '1' to enable interrupt for event LOOPSDONE"] + #[inline(always)] + pub fn loopsdone(&mut self) -> LOOPSDONE_W<7> { + LOOPSDONE_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Enable interrupt\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/pwm0_ns/loop_.rs b/pacs/nrf9120-pac/src/pwm0_ns/loop_.rs new file mode 100644 index 00000000..6779834e --- /dev/null +++ b/pacs/nrf9120-pac/src/pwm0_ns/loop_.rs @@ -0,0 +1,115 @@ +#[doc = "Register `LOOP` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `LOOP` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CNT` reader - Number of playbacks of pattern cycles"] +pub type CNT_R = crate::FieldReader; +#[doc = "Number of playbacks of pattern cycles\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u16)] +pub enum CNT_A { + #[doc = "0: Looping disabled (stop at the end of the sequence)"] + DISABLED = 0, +} +impl From for u16 { + #[inline(always)] + fn from(variant: CNT_A) -> Self { + variant as _ + } +} +impl CNT_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(CNT_A::DISABLED), + _ => None, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == CNT_A::DISABLED + } +} +#[doc = "Field `CNT` writer - Number of playbacks of pattern cycles"] +pub type CNT_W<'a, const O: u8> = crate::FieldWriter<'a, u32, LOOP_SPEC, u16, CNT_A, 16, O>; +impl<'a, const O: u8> CNT_W<'a, O> { + #[doc = "Looping disabled (stop at the end of the sequence)"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(CNT_A::DISABLED) + } +} +impl R { + #[doc = "Bits 0:15 - Number of playbacks of pattern cycles"] + #[inline(always)] + pub fn cnt(&self) -> CNT_R { + CNT_R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Number of playbacks of pattern cycles"] + #[inline(always)] + pub fn cnt(&mut self) -> CNT_W<0> { + CNT_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Number of playbacks of a loop\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [loop_](index.html) module"] +pub struct LOOP_SPEC; +impl crate::RegisterSpec for LOOP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [loop_::R](R) reader structure"] +impl crate::Readable for LOOP_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [loop_::W](W) writer structure"] +impl crate::Writable for LOOP_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets LOOP to value 0"] +impl crate::Resettable for LOOP_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/pwm0_ns/mode.rs b/pacs/nrf9120-pac/src/pwm0_ns/mode.rs new file mode 100644 index 00000000..9392395b --- /dev/null +++ b/pacs/nrf9120-pac/src/pwm0_ns/mode.rs @@ -0,0 +1,126 @@ +#[doc = "Register `MODE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `MODE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `UPDOWN` reader - Selects up mode or up-and-down mode for the counter"] +pub type UPDOWN_R = crate::BitReader; +#[doc = "Selects up mode or up-and-down mode for the counter\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum UPDOWN_A { + #[doc = "0: Up counter, edge-aligned PWM duty cycle"] + UP = 0, + #[doc = "1: Up and down counter, center-aligned PWM duty cycle"] + UP_AND_DOWN = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: UPDOWN_A) -> Self { + variant as u8 != 0 + } +} +impl UPDOWN_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> UPDOWN_A { + match self.bits { + false => UPDOWN_A::UP, + true => UPDOWN_A::UP_AND_DOWN, + } + } + #[doc = "Checks if the value of the field is `UP`"] + #[inline(always)] + pub fn is_up(&self) -> bool { + *self == UPDOWN_A::UP + } + #[doc = "Checks if the value of the field is `UP_AND_DOWN`"] + #[inline(always)] + pub fn is_up_and_down(&self) -> bool { + *self == UPDOWN_A::UP_AND_DOWN + } +} +#[doc = "Field `UPDOWN` writer - Selects up mode or up-and-down mode for the counter"] +pub type UPDOWN_W<'a, const O: u8> = crate::BitWriter<'a, u32, MODE_SPEC, UPDOWN_A, O>; +impl<'a, const O: u8> UPDOWN_W<'a, O> { + #[doc = "Up counter, edge-aligned PWM duty cycle"] + #[inline(always)] + pub fn up(self) -> &'a mut W { + self.variant(UPDOWN_A::UP) + } + #[doc = "Up and down counter, center-aligned PWM duty cycle"] + #[inline(always)] + pub fn up_and_down(self) -> &'a mut W { + self.variant(UPDOWN_A::UP_AND_DOWN) + } +} +impl R { + #[doc = "Bit 0 - Selects up mode or up-and-down mode for the counter"] + #[inline(always)] + pub fn updown(&self) -> UPDOWN_R { + UPDOWN_R::new((self.bits & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Selects up mode or up-and-down mode for the counter"] + #[inline(always)] + pub fn updown(&mut self) -> UPDOWN_W<0> { + UPDOWN_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Selects operating mode of the wave counter\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [mode](index.html) module"] +pub struct MODE_SPEC; +impl crate::RegisterSpec for MODE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [mode::R](R) reader structure"] +impl crate::Readable for MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [mode::W](W) writer structure"] +impl crate::Writable for MODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets MODE to value 0"] +impl crate::Resettable for MODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/pwm0_ns/prescaler.rs b/pacs/nrf9120-pac/src/pwm0_ns/prescaler.rs new file mode 100644 index 00000000..8f49446b --- /dev/null +++ b/pacs/nrf9120-pac/src/pwm0_ns/prescaler.rs @@ -0,0 +1,207 @@ +#[doc = "Register `PRESCALER` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PRESCALER` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PRESCALER` reader - Prescaler of PWM_CLK"] +pub type PRESCALER_R = crate::FieldReader; +#[doc = "Prescaler of PWM_CLK\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum PRESCALER_A { + #[doc = "0: Divide by 1 (16 MHz)"] + DIV_1 = 0, + #[doc = "1: Divide by 2 (8 MHz)"] + DIV_2 = 1, + #[doc = "2: Divide by 4 (4 MHz)"] + DIV_4 = 2, + #[doc = "3: Divide by 8 (2 MHz)"] + DIV_8 = 3, + #[doc = "4: Divide by 16 (1 MHz)"] + DIV_16 = 4, + #[doc = "5: Divide by 32 (500 kHz)"] + DIV_32 = 5, + #[doc = "6: Divide by 64 (250 kHz)"] + DIV_64 = 6, + #[doc = "7: Divide by 128 (125 kHz)"] + DIV_128 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PRESCALER_A) -> Self { + variant as _ + } +} +impl PRESCALER_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PRESCALER_A { + match self.bits { + 0 => PRESCALER_A::DIV_1, + 1 => PRESCALER_A::DIV_2, + 2 => PRESCALER_A::DIV_4, + 3 => PRESCALER_A::DIV_8, + 4 => PRESCALER_A::DIV_16, + 5 => PRESCALER_A::DIV_32, + 6 => PRESCALER_A::DIV_64, + 7 => PRESCALER_A::DIV_128, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DIV_1`"] + #[inline(always)] + pub fn is_div_1(&self) -> bool { + *self == PRESCALER_A::DIV_1 + } + #[doc = "Checks if the value of the field is `DIV_2`"] + #[inline(always)] + pub fn is_div_2(&self) -> bool { + *self == PRESCALER_A::DIV_2 + } + #[doc = "Checks if the value of the field is `DIV_4`"] + #[inline(always)] + pub fn is_div_4(&self) -> bool { + *self == PRESCALER_A::DIV_4 + } + #[doc = "Checks if the value of the field is `DIV_8`"] + #[inline(always)] + pub fn is_div_8(&self) -> bool { + *self == PRESCALER_A::DIV_8 + } + #[doc = "Checks if the value of the field is `DIV_16`"] + #[inline(always)] + pub fn is_div_16(&self) -> bool { + *self == PRESCALER_A::DIV_16 + } + #[doc = "Checks if the value of the field is `DIV_32`"] + #[inline(always)] + pub fn is_div_32(&self) -> bool { + *self == PRESCALER_A::DIV_32 + } + #[doc = "Checks if the value of the field is `DIV_64`"] + #[inline(always)] + pub fn is_div_64(&self) -> bool { + *self == PRESCALER_A::DIV_64 + } + #[doc = "Checks if the value of the field is `DIV_128`"] + #[inline(always)] + pub fn is_div_128(&self) -> bool { + *self == PRESCALER_A::DIV_128 + } +} +#[doc = "Field `PRESCALER` writer - Prescaler of PWM_CLK"] +pub type PRESCALER_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u32, PRESCALER_SPEC, u8, PRESCALER_A, 3, O>; +impl<'a, const O: u8> PRESCALER_W<'a, O> { + #[doc = "Divide by 1 (16 MHz)"] + #[inline(always)] + pub fn div_1(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV_1) + } + #[doc = "Divide by 2 (8 MHz)"] + #[inline(always)] + pub fn div_2(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV_2) + } + #[doc = "Divide by 4 (4 MHz)"] + #[inline(always)] + pub fn div_4(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV_4) + } + #[doc = "Divide by 8 (2 MHz)"] + #[inline(always)] + pub fn div_8(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV_8) + } + #[doc = "Divide by 16 (1 MHz)"] + #[inline(always)] + pub fn div_16(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV_16) + } + #[doc = "Divide by 32 (500 kHz)"] + #[inline(always)] + pub fn div_32(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV_32) + } + #[doc = "Divide by 64 (250 kHz)"] + #[inline(always)] + pub fn div_64(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV_64) + } + #[doc = "Divide by 128 (125 kHz)"] + #[inline(always)] + pub fn div_128(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV_128) + } +} +impl R { + #[doc = "Bits 0:2 - Prescaler of PWM_CLK"] + #[inline(always)] + pub fn prescaler(&self) -> PRESCALER_R { + PRESCALER_R::new((self.bits & 7) as u8) + } +} +impl W { + #[doc = "Bits 0:2 - Prescaler of PWM_CLK"] + #[inline(always)] + pub fn prescaler(&mut self) -> PRESCALER_W<0> { + PRESCALER_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Configuration for PWM_CLK\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [prescaler](index.html) module"] +pub struct PRESCALER_SPEC; +impl crate::RegisterSpec for PRESCALER_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [prescaler::R](R) reader structure"] +impl crate::Readable for PRESCALER_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [prescaler::W](W) writer structure"] +impl crate::Writable for PRESCALER_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PRESCALER to value 0"] +impl crate::Resettable for PRESCALER_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/pwm0_ns/psel.rs b/pacs/nrf9120-pac/src/pwm0_ns/psel.rs new file mode 100644 index 00000000..600585b1 --- /dev/null +++ b/pacs/nrf9120-pac/src/pwm0_ns/psel.rs @@ -0,0 +1,10 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct PSEL { + #[doc = "0x00..0x10 - Description collection: Output pin select for PWM channel n"] + pub out: [OUT; 4], +} +#[doc = "OUT (rw) register accessor: an alias for `Reg`"] +pub type OUT = crate::Reg; +#[doc = "Description collection: Output pin select for PWM channel n"] +pub mod out; diff --git a/pacs/nrf9120-pac/src/pwm0_ns/psel/out.rs b/pacs/nrf9120-pac/src/pwm0_ns/psel/out.rs new file mode 100644 index 00000000..ae16858b --- /dev/null +++ b/pacs/nrf9120-pac/src/pwm0_ns/psel/out.rs @@ -0,0 +1,141 @@ +#[doc = "Register `OUT[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `OUT[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PIN` reader - Pin number"] +pub type PIN_R = crate::FieldReader; +#[doc = "Field `PIN` writer - Pin number"] +pub type PIN_W<'a, const O: u8> = crate::FieldWriter<'a, u32, OUT_SPEC, u8, u8, 5, O>; +#[doc = "Field `CONNECT` reader - Connection"] +pub type CONNECT_R = crate::BitReader; +#[doc = "Connection\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CONNECT_A { + #[doc = "1: Disconnect"] + DISCONNECTED = 1, + #[doc = "0: Connect"] + CONNECTED = 0, +} +impl From for bool { + #[inline(always)] + fn from(variant: CONNECT_A) -> Self { + variant as u8 != 0 + } +} +impl CONNECT_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CONNECT_A { + match self.bits { + true => CONNECT_A::DISCONNECTED, + false => CONNECT_A::CONNECTED, + } + } + #[doc = "Checks if the value of the field is `DISCONNECTED`"] + #[inline(always)] + pub fn is_disconnected(&self) -> bool { + *self == CONNECT_A::DISCONNECTED + } + #[doc = "Checks if the value of the field is `CONNECTED`"] + #[inline(always)] + pub fn is_connected(&self) -> bool { + *self == CONNECT_A::CONNECTED + } +} +#[doc = "Field `CONNECT` writer - Connection"] +pub type CONNECT_W<'a, const O: u8> = crate::BitWriter<'a, u32, OUT_SPEC, CONNECT_A, O>; +impl<'a, const O: u8> CONNECT_W<'a, O> { + #[doc = "Disconnect"] + #[inline(always)] + pub fn disconnected(self) -> &'a mut W { + self.variant(CONNECT_A::DISCONNECTED) + } + #[doc = "Connect"] + #[inline(always)] + pub fn connected(self) -> &'a mut W { + self.variant(CONNECT_A::CONNECTED) + } +} +impl R { + #[doc = "Bits 0:4 - Pin number"] + #[inline(always)] + pub fn pin(&self) -> PIN_R { + PIN_R::new((self.bits & 0x1f) as u8) + } + #[doc = "Bit 31 - Connection"] + #[inline(always)] + pub fn connect(&self) -> CONNECT_R { + CONNECT_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:4 - Pin number"] + #[inline(always)] + pub fn pin(&mut self) -> PIN_W<0> { + PIN_W::new(self) + } + #[doc = "Bit 31 - Connection"] + #[inline(always)] + pub fn connect(&mut self) -> CONNECT_W<31> { + CONNECT_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Description collection: Output pin select for PWM channel n\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [out](index.html) module"] +pub struct OUT_SPEC; +impl crate::RegisterSpec for OUT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [out::R](R) reader structure"] +impl crate::Readable for OUT_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [out::W](W) writer structure"] +impl crate::Writable for OUT_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets OUT[%s] +to value 0xffff_ffff"] +impl crate::Resettable for OUT_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0xffff_ffff + } +} diff --git a/pacs/nrf9120-pac/src/pwm0_ns/publish_loopsdone.rs b/pacs/nrf9120-pac/src/pwm0_ns/publish_loopsdone.rs new file mode 100644 index 00000000..f1d388a1 --- /dev/null +++ b/pacs/nrf9120-pac/src/pwm0_ns/publish_loopsdone.rs @@ -0,0 +1,141 @@ +#[doc = "Register `PUBLISH_LOOPSDONE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PUBLISH_LOOPSDONE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CHIDX` reader - DPPI channel that event LOOPSDONE will publish to"] +pub type CHIDX_R = crate::FieldReader; +#[doc = "Field `CHIDX` writer - DPPI channel that event LOOPSDONE will publish to"] +pub type CHIDX_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, PUBLISH_LOOPSDONE_SPEC, u8, u8, 8, O>; +#[doc = "Field `EN` reader - "] +pub type EN_R = crate::BitReader; +#[doc = "\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum EN_A { + #[doc = "0: Disable publishing"] + DISABLED = 0, + #[doc = "1: Enable publishing"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: EN_A) -> Self { + variant as u8 != 0 + } +} +impl EN_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EN_A { + match self.bits { + false => EN_A::DISABLED, + true => EN_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == EN_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == EN_A::ENABLED + } +} +#[doc = "Field `EN` writer - "] +pub type EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, PUBLISH_LOOPSDONE_SPEC, EN_A, O>; +impl<'a, const O: u8> EN_W<'a, O> { + #[doc = "Disable publishing"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(EN_A::DISABLED) + } + #[doc = "Enable publishing"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(EN_A::ENABLED) + } +} +impl R { + #[doc = "Bits 0:7 - DPPI channel that event LOOPSDONE will publish to"] + #[inline(always)] + pub fn chidx(&self) -> CHIDX_R { + CHIDX_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&self) -> EN_R { + EN_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:7 - DPPI channel that event LOOPSDONE will publish to"] + #[inline(always)] + pub fn chidx(&mut self) -> CHIDX_W<0> { + CHIDX_W::new(self) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&mut self) -> EN_W<31> { + EN_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Publish configuration for event LOOPSDONE\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [publish_loopsdone](index.html) module"] +pub struct PUBLISH_LOOPSDONE_SPEC; +impl crate::RegisterSpec for PUBLISH_LOOPSDONE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [publish_loopsdone::R](R) reader structure"] +impl crate::Readable for PUBLISH_LOOPSDONE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [publish_loopsdone::W](W) writer structure"] +impl crate::Writable for PUBLISH_LOOPSDONE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PUBLISH_LOOPSDONE to value 0"] +impl crate::Resettable for PUBLISH_LOOPSDONE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/pwm0_ns/publish_pwmperiodend.rs b/pacs/nrf9120-pac/src/pwm0_ns/publish_pwmperiodend.rs new file mode 100644 index 00000000..1e9d4dfb --- /dev/null +++ b/pacs/nrf9120-pac/src/pwm0_ns/publish_pwmperiodend.rs @@ -0,0 +1,141 @@ +#[doc = "Register `PUBLISH_PWMPERIODEND` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PUBLISH_PWMPERIODEND` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CHIDX` reader - DPPI channel that event PWMPERIODEND will publish to"] +pub type CHIDX_R = crate::FieldReader; +#[doc = "Field `CHIDX` writer - DPPI channel that event PWMPERIODEND will publish to"] +pub type CHIDX_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, PUBLISH_PWMPERIODEND_SPEC, u8, u8, 8, O>; +#[doc = "Field `EN` reader - "] +pub type EN_R = crate::BitReader; +#[doc = "\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum EN_A { + #[doc = "0: Disable publishing"] + DISABLED = 0, + #[doc = "1: Enable publishing"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: EN_A) -> Self { + variant as u8 != 0 + } +} +impl EN_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EN_A { + match self.bits { + false => EN_A::DISABLED, + true => EN_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == EN_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == EN_A::ENABLED + } +} +#[doc = "Field `EN` writer - "] +pub type EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, PUBLISH_PWMPERIODEND_SPEC, EN_A, O>; +impl<'a, const O: u8> EN_W<'a, O> { + #[doc = "Disable publishing"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(EN_A::DISABLED) + } + #[doc = "Enable publishing"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(EN_A::ENABLED) + } +} +impl R { + #[doc = "Bits 0:7 - DPPI channel that event PWMPERIODEND will publish to"] + #[inline(always)] + pub fn chidx(&self) -> CHIDX_R { + CHIDX_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&self) -> EN_R { + EN_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:7 - DPPI channel that event PWMPERIODEND will publish to"] + #[inline(always)] + pub fn chidx(&mut self) -> CHIDX_W<0> { + CHIDX_W::new(self) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&mut self) -> EN_W<31> { + EN_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Publish configuration for event PWMPERIODEND\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [publish_pwmperiodend](index.html) module"] +pub struct PUBLISH_PWMPERIODEND_SPEC; +impl crate::RegisterSpec for PUBLISH_PWMPERIODEND_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [publish_pwmperiodend::R](R) reader structure"] +impl crate::Readable for PUBLISH_PWMPERIODEND_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [publish_pwmperiodend::W](W) writer structure"] +impl crate::Writable for PUBLISH_PWMPERIODEND_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PUBLISH_PWMPERIODEND to value 0"] +impl crate::Resettable for PUBLISH_PWMPERIODEND_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/pwm0_ns/publish_seqend.rs b/pacs/nrf9120-pac/src/pwm0_ns/publish_seqend.rs new file mode 100644 index 00000000..d636b354 --- /dev/null +++ b/pacs/nrf9120-pac/src/pwm0_ns/publish_seqend.rs @@ -0,0 +1,145 @@ +#[doc = "Register `PUBLISH_SEQEND[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PUBLISH_SEQEND[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CHIDX` reader - DPPI channel that event SEQEND\\[n\\] +will publish to"] +pub type CHIDX_R = crate::FieldReader; +#[doc = "Field `CHIDX` writer - DPPI channel that event SEQEND\\[n\\] +will publish to"] +pub type CHIDX_W<'a, const O: u8> = crate::FieldWriter<'a, u32, PUBLISH_SEQEND_SPEC, u8, u8, 8, O>; +#[doc = "Field `EN` reader - "] +pub type EN_R = crate::BitReader; +#[doc = "\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum EN_A { + #[doc = "0: Disable publishing"] + DISABLED = 0, + #[doc = "1: Enable publishing"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: EN_A) -> Self { + variant as u8 != 0 + } +} +impl EN_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EN_A { + match self.bits { + false => EN_A::DISABLED, + true => EN_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == EN_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == EN_A::ENABLED + } +} +#[doc = "Field `EN` writer - "] +pub type EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, PUBLISH_SEQEND_SPEC, EN_A, O>; +impl<'a, const O: u8> EN_W<'a, O> { + #[doc = "Disable publishing"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(EN_A::DISABLED) + } + #[doc = "Enable publishing"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(EN_A::ENABLED) + } +} +impl R { + #[doc = "Bits 0:7 - DPPI channel that event SEQEND\\[n\\] +will publish to"] + #[inline(always)] + pub fn chidx(&self) -> CHIDX_R { + CHIDX_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&self) -> EN_R { + EN_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:7 - DPPI channel that event SEQEND\\[n\\] +will publish to"] + #[inline(always)] + pub fn chidx(&mut self) -> CHIDX_W<0> { + CHIDX_W::new(self) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&mut self) -> EN_W<31> { + EN_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Description collection: Publish configuration for event SEQEND\\[n\\]\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [publish_seqend](index.html) module"] +pub struct PUBLISH_SEQEND_SPEC; +impl crate::RegisterSpec for PUBLISH_SEQEND_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [publish_seqend::R](R) reader structure"] +impl crate::Readable for PUBLISH_SEQEND_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [publish_seqend::W](W) writer structure"] +impl crate::Writable for PUBLISH_SEQEND_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PUBLISH_SEQEND[%s] +to value 0"] +impl crate::Resettable for PUBLISH_SEQEND_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/pwm0_ns/publish_seqstarted.rs b/pacs/nrf9120-pac/src/pwm0_ns/publish_seqstarted.rs new file mode 100644 index 00000000..c822559b --- /dev/null +++ b/pacs/nrf9120-pac/src/pwm0_ns/publish_seqstarted.rs @@ -0,0 +1,146 @@ +#[doc = "Register `PUBLISH_SEQSTARTED[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PUBLISH_SEQSTARTED[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CHIDX` reader - DPPI channel that event SEQSTARTED\\[n\\] +will publish to"] +pub type CHIDX_R = crate::FieldReader; +#[doc = "Field `CHIDX` writer - DPPI channel that event SEQSTARTED\\[n\\] +will publish to"] +pub type CHIDX_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, PUBLISH_SEQSTARTED_SPEC, u8, u8, 8, O>; +#[doc = "Field `EN` reader - "] +pub type EN_R = crate::BitReader; +#[doc = "\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum EN_A { + #[doc = "0: Disable publishing"] + DISABLED = 0, + #[doc = "1: Enable publishing"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: EN_A) -> Self { + variant as u8 != 0 + } +} +impl EN_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EN_A { + match self.bits { + false => EN_A::DISABLED, + true => EN_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == EN_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == EN_A::ENABLED + } +} +#[doc = "Field `EN` writer - "] +pub type EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, PUBLISH_SEQSTARTED_SPEC, EN_A, O>; +impl<'a, const O: u8> EN_W<'a, O> { + #[doc = "Disable publishing"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(EN_A::DISABLED) + } + #[doc = "Enable publishing"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(EN_A::ENABLED) + } +} +impl R { + #[doc = "Bits 0:7 - DPPI channel that event SEQSTARTED\\[n\\] +will publish to"] + #[inline(always)] + pub fn chidx(&self) -> CHIDX_R { + CHIDX_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&self) -> EN_R { + EN_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:7 - DPPI channel that event SEQSTARTED\\[n\\] +will publish to"] + #[inline(always)] + pub fn chidx(&mut self) -> CHIDX_W<0> { + CHIDX_W::new(self) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&mut self) -> EN_W<31> { + EN_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Description collection: Publish configuration for event SEQSTARTED\\[n\\]\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [publish_seqstarted](index.html) module"] +pub struct PUBLISH_SEQSTARTED_SPEC; +impl crate::RegisterSpec for PUBLISH_SEQSTARTED_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [publish_seqstarted::R](R) reader structure"] +impl crate::Readable for PUBLISH_SEQSTARTED_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [publish_seqstarted::W](W) writer structure"] +impl crate::Writable for PUBLISH_SEQSTARTED_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PUBLISH_SEQSTARTED[%s] +to value 0"] +impl crate::Resettable for PUBLISH_SEQSTARTED_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/pwm0_ns/publish_stopped.rs b/pacs/nrf9120-pac/src/pwm0_ns/publish_stopped.rs new file mode 100644 index 00000000..247f50bf --- /dev/null +++ b/pacs/nrf9120-pac/src/pwm0_ns/publish_stopped.rs @@ -0,0 +1,140 @@ +#[doc = "Register `PUBLISH_STOPPED` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PUBLISH_STOPPED` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CHIDX` reader - DPPI channel that event STOPPED will publish to"] +pub type CHIDX_R = crate::FieldReader; +#[doc = "Field `CHIDX` writer - DPPI channel that event STOPPED will publish to"] +pub type CHIDX_W<'a, const O: u8> = crate::FieldWriter<'a, u32, PUBLISH_STOPPED_SPEC, u8, u8, 8, O>; +#[doc = "Field `EN` reader - "] +pub type EN_R = crate::BitReader; +#[doc = "\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum EN_A { + #[doc = "0: Disable publishing"] + DISABLED = 0, + #[doc = "1: Enable publishing"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: EN_A) -> Self { + variant as u8 != 0 + } +} +impl EN_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EN_A { + match self.bits { + false => EN_A::DISABLED, + true => EN_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == EN_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == EN_A::ENABLED + } +} +#[doc = "Field `EN` writer - "] +pub type EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, PUBLISH_STOPPED_SPEC, EN_A, O>; +impl<'a, const O: u8> EN_W<'a, O> { + #[doc = "Disable publishing"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(EN_A::DISABLED) + } + #[doc = "Enable publishing"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(EN_A::ENABLED) + } +} +impl R { + #[doc = "Bits 0:7 - DPPI channel that event STOPPED will publish to"] + #[inline(always)] + pub fn chidx(&self) -> CHIDX_R { + CHIDX_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&self) -> EN_R { + EN_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:7 - DPPI channel that event STOPPED will publish to"] + #[inline(always)] + pub fn chidx(&mut self) -> CHIDX_W<0> { + CHIDX_W::new(self) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&mut self) -> EN_W<31> { + EN_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Publish configuration for event STOPPED\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [publish_stopped](index.html) module"] +pub struct PUBLISH_STOPPED_SPEC; +impl crate::RegisterSpec for PUBLISH_STOPPED_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [publish_stopped::R](R) reader structure"] +impl crate::Readable for PUBLISH_STOPPED_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [publish_stopped::W](W) writer structure"] +impl crate::Writable for PUBLISH_STOPPED_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PUBLISH_STOPPED to value 0"] +impl crate::Resettable for PUBLISH_STOPPED_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/pwm0_ns/seq.rs b/pacs/nrf9120-pac/src/pwm0_ns/seq.rs new file mode 100644 index 00000000..37e30642 --- /dev/null +++ b/pacs/nrf9120-pac/src/pwm0_ns/seq.rs @@ -0,0 +1,28 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct SEQ { + #[doc = "0x00 - Description cluster: Beginning address in RAM of this sequence"] + pub ptr: PTR, + #[doc = "0x04 - Description cluster: Number of values (duty cycles) in this sequence"] + pub cnt: CNT, + #[doc = "0x08 - Description cluster: Number of additional PWM periods between samples loaded into compare register"] + pub refresh: REFRESH, + #[doc = "0x0c - Description cluster: Time added after the sequence"] + pub enddelay: ENDDELAY, +} +#[doc = "PTR (rw) register accessor: an alias for `Reg`"] +pub type PTR = crate::Reg; +#[doc = "Description cluster: Beginning address in RAM of this sequence"] +pub mod ptr; +#[doc = "CNT (rw) register accessor: an alias for `Reg`"] +pub type CNT = crate::Reg; +#[doc = "Description cluster: Number of values (duty cycles) in this sequence"] +pub mod cnt; +#[doc = "REFRESH (rw) register accessor: an alias for `Reg`"] +pub type REFRESH = crate::Reg; +#[doc = "Description cluster: Number of additional PWM periods between samples loaded into compare register"] +pub mod refresh; +#[doc = "ENDDELAY (rw) register accessor: an alias for `Reg`"] +pub type ENDDELAY = crate::Reg; +#[doc = "Description cluster: Time added after the sequence"] +pub mod enddelay; diff --git a/pacs/nrf9120-pac/src/pwm0_ns/seq/cnt.rs b/pacs/nrf9120-pac/src/pwm0_ns/seq/cnt.rs new file mode 100644 index 00000000..677c422c --- /dev/null +++ b/pacs/nrf9120-pac/src/pwm0_ns/seq/cnt.rs @@ -0,0 +1,115 @@ +#[doc = "Register `CNT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CNT` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CNT` reader - Number of values (duty cycles) in this sequence"] +pub type CNT_R = crate::FieldReader; +#[doc = "Number of values (duty cycles) in this sequence\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u16)] +pub enum CNT_A { + #[doc = "0: Sequence is disabled, and shall not be started as it is empty"] + DISABLED = 0, +} +impl From for u16 { + #[inline(always)] + fn from(variant: CNT_A) -> Self { + variant as _ + } +} +impl CNT_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(CNT_A::DISABLED), + _ => None, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == CNT_A::DISABLED + } +} +#[doc = "Field `CNT` writer - Number of values (duty cycles) in this sequence"] +pub type CNT_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CNT_SPEC, u16, CNT_A, 15, O>; +impl<'a, const O: u8> CNT_W<'a, O> { + #[doc = "Sequence is disabled, and shall not be started as it is empty"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(CNT_A::DISABLED) + } +} +impl R { + #[doc = "Bits 0:14 - Number of values (duty cycles) in this sequence"] + #[inline(always)] + pub fn cnt(&self) -> CNT_R { + CNT_R::new((self.bits & 0x7fff) as u16) + } +} +impl W { + #[doc = "Bits 0:14 - Number of values (duty cycles) in this sequence"] + #[inline(always)] + pub fn cnt(&mut self) -> CNT_W<0> { + CNT_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Description cluster: Number of values (duty cycles) in this sequence\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cnt](index.html) module"] +pub struct CNT_SPEC; +impl crate::RegisterSpec for CNT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cnt::R](R) reader structure"] +impl crate::Readable for CNT_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [cnt::W](W) writer structure"] +impl crate::Writable for CNT_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CNT to value 0"] +impl crate::Resettable for CNT_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/pwm0_ns/seq/enddelay.rs b/pacs/nrf9120-pac/src/pwm0_ns/seq/enddelay.rs new file mode 100644 index 00000000..fdea2b4a --- /dev/null +++ b/pacs/nrf9120-pac/src/pwm0_ns/seq/enddelay.rs @@ -0,0 +1,80 @@ +#[doc = "Register `ENDDELAY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `ENDDELAY` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CNT` reader - Time added after the sequence in PWM periods"] +pub type CNT_R = crate::FieldReader; +#[doc = "Field `CNT` writer - Time added after the sequence in PWM periods"] +pub type CNT_W<'a, const O: u8> = crate::FieldWriter<'a, u32, ENDDELAY_SPEC, u32, u32, 24, O>; +impl R { + #[doc = "Bits 0:23 - Time added after the sequence in PWM periods"] + #[inline(always)] + pub fn cnt(&self) -> CNT_R { + CNT_R::new((self.bits & 0x00ff_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:23 - Time added after the sequence in PWM periods"] + #[inline(always)] + pub fn cnt(&mut self) -> CNT_W<0> { + CNT_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Description cluster: Time added after the sequence\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [enddelay](index.html) module"] +pub struct ENDDELAY_SPEC; +impl crate::RegisterSpec for ENDDELAY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [enddelay::R](R) reader structure"] +impl crate::Readable for ENDDELAY_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [enddelay::W](W) writer structure"] +impl crate::Writable for ENDDELAY_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets ENDDELAY to value 0"] +impl crate::Resettable for ENDDELAY_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/pwm0_ns/seq/ptr.rs b/pacs/nrf9120-pac/src/pwm0_ns/seq/ptr.rs new file mode 100644 index 00000000..16bbff89 --- /dev/null +++ b/pacs/nrf9120-pac/src/pwm0_ns/seq/ptr.rs @@ -0,0 +1,80 @@ +#[doc = "Register `PTR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PTR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PTR` reader - Beginning address in RAM of this sequence"] +pub type PTR_R = crate::FieldReader; +#[doc = "Field `PTR` writer - Beginning address in RAM of this sequence"] +pub type PTR_W<'a, const O: u8> = crate::FieldWriter<'a, u32, PTR_SPEC, u32, u32, 32, O>; +impl R { + #[doc = "Bits 0:31 - Beginning address in RAM of this sequence"] + #[inline(always)] + pub fn ptr(&self) -> PTR_R { + PTR_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Beginning address in RAM of this sequence"] + #[inline(always)] + pub fn ptr(&mut self) -> PTR_W<0> { + PTR_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Description cluster: Beginning address in RAM of this sequence\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ptr](index.html) module"] +pub struct PTR_SPEC; +impl crate::RegisterSpec for PTR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ptr::R](R) reader structure"] +impl crate::Readable for PTR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ptr::W](W) writer structure"] +impl crate::Writable for PTR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PTR to value 0"] +impl crate::Resettable for PTR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/pwm0_ns/seq/refresh.rs b/pacs/nrf9120-pac/src/pwm0_ns/seq/refresh.rs new file mode 100644 index 00000000..bfd51c9a --- /dev/null +++ b/pacs/nrf9120-pac/src/pwm0_ns/seq/refresh.rs @@ -0,0 +1,115 @@ +#[doc = "Register `REFRESH` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `REFRESH` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CNT` reader - Number of additional PWM periods between samples loaded into compare register (load every REFRESH.CNT+1 PWM periods)"] +pub type CNT_R = crate::FieldReader; +#[doc = "Number of additional PWM periods between samples loaded into compare register (load every REFRESH.CNT+1 PWM periods)\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u32)] +pub enum CNT_A { + #[doc = "0: Update every PWM period"] + CONTINUOUS = 0, +} +impl From for u32 { + #[inline(always)] + fn from(variant: CNT_A) -> Self { + variant as _ + } +} +impl CNT_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(CNT_A::CONTINUOUS), + _ => None, + } + } + #[doc = "Checks if the value of the field is `CONTINUOUS`"] + #[inline(always)] + pub fn is_continuous(&self) -> bool { + *self == CNT_A::CONTINUOUS + } +} +#[doc = "Field `CNT` writer - Number of additional PWM periods between samples loaded into compare register (load every REFRESH.CNT+1 PWM periods)"] +pub type CNT_W<'a, const O: u8> = crate::FieldWriter<'a, u32, REFRESH_SPEC, u32, CNT_A, 24, O>; +impl<'a, const O: u8> CNT_W<'a, O> { + #[doc = "Update every PWM period"] + #[inline(always)] + pub fn continuous(self) -> &'a mut W { + self.variant(CNT_A::CONTINUOUS) + } +} +impl R { + #[doc = "Bits 0:23 - Number of additional PWM periods between samples loaded into compare register (load every REFRESH.CNT+1 PWM periods)"] + #[inline(always)] + pub fn cnt(&self) -> CNT_R { + CNT_R::new((self.bits & 0x00ff_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:23 - Number of additional PWM periods between samples loaded into compare register (load every REFRESH.CNT+1 PWM periods)"] + #[inline(always)] + pub fn cnt(&mut self) -> CNT_W<0> { + CNT_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Description cluster: Number of additional PWM periods between samples loaded into compare register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [refresh](index.html) module"] +pub struct REFRESH_SPEC; +impl crate::RegisterSpec for REFRESH_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [refresh::R](R) reader structure"] +impl crate::Readable for REFRESH_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [refresh::W](W) writer structure"] +impl crate::Writable for REFRESH_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets REFRESH to value 0x01"] +impl crate::Resettable for REFRESH_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x01 + } +} diff --git a/pacs/nrf9120-pac/src/pwm0_ns/shorts.rs b/pacs/nrf9120-pac/src/pwm0_ns/shorts.rs new file mode 100644 index 00000000..cd392993 --- /dev/null +++ b/pacs/nrf9120-pac/src/pwm0_ns/shorts.rs @@ -0,0 +1,381 @@ +#[doc = "Register `SHORTS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SHORTS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SEQEND0_STOP` reader - Shortcut between event SEQEND\\[0\\] +and task STOP"] +pub type SEQEND0_STOP_R = crate::BitReader; +#[doc = "Shortcut between event SEQEND\\[0\\] +and task STOP\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum SEQEND0_STOP_A { + #[doc = "0: Disable shortcut"] + DISABLED = 0, + #[doc = "1: Enable shortcut"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: SEQEND0_STOP_A) -> Self { + variant as u8 != 0 + } +} +impl SEQEND0_STOP_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> SEQEND0_STOP_A { + match self.bits { + false => SEQEND0_STOP_A::DISABLED, + true => SEQEND0_STOP_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == SEQEND0_STOP_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == SEQEND0_STOP_A::ENABLED + } +} +#[doc = "Field `SEQEND0_STOP` writer - Shortcut between event SEQEND\\[0\\] +and task STOP"] +pub type SEQEND0_STOP_W<'a, const O: u8> = + crate::BitWriter<'a, u32, SHORTS_SPEC, SEQEND0_STOP_A, O>; +impl<'a, const O: u8> SEQEND0_STOP_W<'a, O> { + #[doc = "Disable shortcut"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(SEQEND0_STOP_A::DISABLED) + } + #[doc = "Enable shortcut"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(SEQEND0_STOP_A::ENABLED) + } +} +#[doc = "Field `SEQEND1_STOP` reader - Shortcut between event SEQEND\\[1\\] +and task STOP"] +pub type SEQEND1_STOP_R = crate::BitReader; +#[doc = "Shortcut between event SEQEND\\[1\\] +and task STOP\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum SEQEND1_STOP_A { + #[doc = "0: Disable shortcut"] + DISABLED = 0, + #[doc = "1: Enable shortcut"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: SEQEND1_STOP_A) -> Self { + variant as u8 != 0 + } +} +impl SEQEND1_STOP_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> SEQEND1_STOP_A { + match self.bits { + false => SEQEND1_STOP_A::DISABLED, + true => SEQEND1_STOP_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == SEQEND1_STOP_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == SEQEND1_STOP_A::ENABLED + } +} +#[doc = "Field `SEQEND1_STOP` writer - Shortcut between event SEQEND\\[1\\] +and task STOP"] +pub type SEQEND1_STOP_W<'a, const O: u8> = + crate::BitWriter<'a, u32, SHORTS_SPEC, SEQEND1_STOP_A, O>; +impl<'a, const O: u8> SEQEND1_STOP_W<'a, O> { + #[doc = "Disable shortcut"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(SEQEND1_STOP_A::DISABLED) + } + #[doc = "Enable shortcut"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(SEQEND1_STOP_A::ENABLED) + } +} +#[doc = "Field `LOOPSDONE_SEQSTART0` reader - Shortcut between event LOOPSDONE and task SEQSTART\\[0\\]"] +pub type LOOPSDONE_SEQSTART0_R = crate::BitReader; +#[doc = "Shortcut between event LOOPSDONE and task SEQSTART\\[0\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum LOOPSDONE_SEQSTART0_A { + #[doc = "0: Disable shortcut"] + DISABLED = 0, + #[doc = "1: Enable shortcut"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: LOOPSDONE_SEQSTART0_A) -> Self { + variant as u8 != 0 + } +} +impl LOOPSDONE_SEQSTART0_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> LOOPSDONE_SEQSTART0_A { + match self.bits { + false => LOOPSDONE_SEQSTART0_A::DISABLED, + true => LOOPSDONE_SEQSTART0_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == LOOPSDONE_SEQSTART0_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == LOOPSDONE_SEQSTART0_A::ENABLED + } +} +#[doc = "Field `LOOPSDONE_SEQSTART0` writer - Shortcut between event LOOPSDONE and task SEQSTART\\[0\\]"] +pub type LOOPSDONE_SEQSTART0_W<'a, const O: u8> = + crate::BitWriter<'a, u32, SHORTS_SPEC, LOOPSDONE_SEQSTART0_A, O>; +impl<'a, const O: u8> LOOPSDONE_SEQSTART0_W<'a, O> { + #[doc = "Disable shortcut"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(LOOPSDONE_SEQSTART0_A::DISABLED) + } + #[doc = "Enable shortcut"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(LOOPSDONE_SEQSTART0_A::ENABLED) + } +} +#[doc = "Field `LOOPSDONE_SEQSTART1` reader - Shortcut between event LOOPSDONE and task SEQSTART\\[1\\]"] +pub type LOOPSDONE_SEQSTART1_R = crate::BitReader; +#[doc = "Shortcut between event LOOPSDONE and task SEQSTART\\[1\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum LOOPSDONE_SEQSTART1_A { + #[doc = "0: Disable shortcut"] + DISABLED = 0, + #[doc = "1: Enable shortcut"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: LOOPSDONE_SEQSTART1_A) -> Self { + variant as u8 != 0 + } +} +impl LOOPSDONE_SEQSTART1_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> LOOPSDONE_SEQSTART1_A { + match self.bits { + false => LOOPSDONE_SEQSTART1_A::DISABLED, + true => LOOPSDONE_SEQSTART1_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == LOOPSDONE_SEQSTART1_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == LOOPSDONE_SEQSTART1_A::ENABLED + } +} +#[doc = "Field `LOOPSDONE_SEQSTART1` writer - Shortcut between event LOOPSDONE and task SEQSTART\\[1\\]"] +pub type LOOPSDONE_SEQSTART1_W<'a, const O: u8> = + crate::BitWriter<'a, u32, SHORTS_SPEC, LOOPSDONE_SEQSTART1_A, O>; +impl<'a, const O: u8> LOOPSDONE_SEQSTART1_W<'a, O> { + #[doc = "Disable shortcut"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(LOOPSDONE_SEQSTART1_A::DISABLED) + } + #[doc = "Enable shortcut"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(LOOPSDONE_SEQSTART1_A::ENABLED) + } +} +#[doc = "Field `LOOPSDONE_STOP` reader - Shortcut between event LOOPSDONE and task STOP"] +pub type LOOPSDONE_STOP_R = crate::BitReader; +#[doc = "Shortcut between event LOOPSDONE and task STOP\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum LOOPSDONE_STOP_A { + #[doc = "0: Disable shortcut"] + DISABLED = 0, + #[doc = "1: Enable shortcut"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: LOOPSDONE_STOP_A) -> Self { + variant as u8 != 0 + } +} +impl LOOPSDONE_STOP_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> LOOPSDONE_STOP_A { + match self.bits { + false => LOOPSDONE_STOP_A::DISABLED, + true => LOOPSDONE_STOP_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == LOOPSDONE_STOP_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == LOOPSDONE_STOP_A::ENABLED + } +} +#[doc = "Field `LOOPSDONE_STOP` writer - Shortcut between event LOOPSDONE and task STOP"] +pub type LOOPSDONE_STOP_W<'a, const O: u8> = + crate::BitWriter<'a, u32, SHORTS_SPEC, LOOPSDONE_STOP_A, O>; +impl<'a, const O: u8> LOOPSDONE_STOP_W<'a, O> { + #[doc = "Disable shortcut"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(LOOPSDONE_STOP_A::DISABLED) + } + #[doc = "Enable shortcut"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(LOOPSDONE_STOP_A::ENABLED) + } +} +impl R { + #[doc = "Bit 0 - Shortcut between event SEQEND\\[0\\] +and task STOP"] + #[inline(always)] + pub fn seqend0_stop(&self) -> SEQEND0_STOP_R { + SEQEND0_STOP_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Shortcut between event SEQEND\\[1\\] +and task STOP"] + #[inline(always)] + pub fn seqend1_stop(&self) -> SEQEND1_STOP_R { + SEQEND1_STOP_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Shortcut between event LOOPSDONE and task SEQSTART\\[0\\]"] + #[inline(always)] + pub fn loopsdone_seqstart0(&self) -> LOOPSDONE_SEQSTART0_R { + LOOPSDONE_SEQSTART0_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Shortcut between event LOOPSDONE and task SEQSTART\\[1\\]"] + #[inline(always)] + pub fn loopsdone_seqstart1(&self) -> LOOPSDONE_SEQSTART1_R { + LOOPSDONE_SEQSTART1_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Shortcut between event LOOPSDONE and task STOP"] + #[inline(always)] + pub fn loopsdone_stop(&self) -> LOOPSDONE_STOP_R { + LOOPSDONE_STOP_R::new(((self.bits >> 4) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Shortcut between event SEQEND\\[0\\] +and task STOP"] + #[inline(always)] + pub fn seqend0_stop(&mut self) -> SEQEND0_STOP_W<0> { + SEQEND0_STOP_W::new(self) + } + #[doc = "Bit 1 - Shortcut between event SEQEND\\[1\\] +and task STOP"] + #[inline(always)] + pub fn seqend1_stop(&mut self) -> SEQEND1_STOP_W<1> { + SEQEND1_STOP_W::new(self) + } + #[doc = "Bit 2 - Shortcut between event LOOPSDONE and task SEQSTART\\[0\\]"] + #[inline(always)] + pub fn loopsdone_seqstart0(&mut self) -> LOOPSDONE_SEQSTART0_W<2> { + LOOPSDONE_SEQSTART0_W::new(self) + } + #[doc = "Bit 3 - Shortcut between event LOOPSDONE and task SEQSTART\\[1\\]"] + #[inline(always)] + pub fn loopsdone_seqstart1(&mut self) -> LOOPSDONE_SEQSTART1_W<3> { + LOOPSDONE_SEQSTART1_W::new(self) + } + #[doc = "Bit 4 - Shortcut between event LOOPSDONE and task STOP"] + #[inline(always)] + pub fn loopsdone_stop(&mut self) -> LOOPSDONE_STOP_W<4> { + LOOPSDONE_STOP_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Shortcuts between local events and tasks\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [shorts](index.html) module"] +pub struct SHORTS_SPEC; +impl crate::RegisterSpec for SHORTS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [shorts::R](R) reader structure"] +impl crate::Readable for SHORTS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [shorts::W](W) writer structure"] +impl crate::Writable for SHORTS_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SHORTS to value 0"] +impl crate::Resettable for SHORTS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/pwm0_ns/subscribe_nextstep.rs b/pacs/nrf9120-pac/src/pwm0_ns/subscribe_nextstep.rs new file mode 100644 index 00000000..4dbdcf0a --- /dev/null +++ b/pacs/nrf9120-pac/src/pwm0_ns/subscribe_nextstep.rs @@ -0,0 +1,141 @@ +#[doc = "Register `SUBSCRIBE_NEXTSTEP` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SUBSCRIBE_NEXTSTEP` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CHIDX` reader - DPPI channel that task NEXTSTEP will subscribe to"] +pub type CHIDX_R = crate::FieldReader; +#[doc = "Field `CHIDX` writer - DPPI channel that task NEXTSTEP will subscribe to"] +pub type CHIDX_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, SUBSCRIBE_NEXTSTEP_SPEC, u8, u8, 8, O>; +#[doc = "Field `EN` reader - "] +pub type EN_R = crate::BitReader; +#[doc = "\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum EN_A { + #[doc = "0: Disable subscription"] + DISABLED = 0, + #[doc = "1: Enable subscription"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: EN_A) -> Self { + variant as u8 != 0 + } +} +impl EN_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EN_A { + match self.bits { + false => EN_A::DISABLED, + true => EN_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == EN_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == EN_A::ENABLED + } +} +#[doc = "Field `EN` writer - "] +pub type EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, SUBSCRIBE_NEXTSTEP_SPEC, EN_A, O>; +impl<'a, const O: u8> EN_W<'a, O> { + #[doc = "Disable subscription"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(EN_A::DISABLED) + } + #[doc = "Enable subscription"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(EN_A::ENABLED) + } +} +impl R { + #[doc = "Bits 0:7 - DPPI channel that task NEXTSTEP will subscribe to"] + #[inline(always)] + pub fn chidx(&self) -> CHIDX_R { + CHIDX_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&self) -> EN_R { + EN_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:7 - DPPI channel that task NEXTSTEP will subscribe to"] + #[inline(always)] + pub fn chidx(&mut self) -> CHIDX_W<0> { + CHIDX_W::new(self) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&mut self) -> EN_W<31> { + EN_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Subscribe configuration for task NEXTSTEP\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [subscribe_nextstep](index.html) module"] +pub struct SUBSCRIBE_NEXTSTEP_SPEC; +impl crate::RegisterSpec for SUBSCRIBE_NEXTSTEP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [subscribe_nextstep::R](R) reader structure"] +impl crate::Readable for SUBSCRIBE_NEXTSTEP_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [subscribe_nextstep::W](W) writer structure"] +impl crate::Writable for SUBSCRIBE_NEXTSTEP_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SUBSCRIBE_NEXTSTEP to value 0"] +impl crate::Resettable for SUBSCRIBE_NEXTSTEP_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/pwm0_ns/subscribe_seqstart.rs b/pacs/nrf9120-pac/src/pwm0_ns/subscribe_seqstart.rs new file mode 100644 index 00000000..9876edc1 --- /dev/null +++ b/pacs/nrf9120-pac/src/pwm0_ns/subscribe_seqstart.rs @@ -0,0 +1,146 @@ +#[doc = "Register `SUBSCRIBE_SEQSTART[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SUBSCRIBE_SEQSTART[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CHIDX` reader - DPPI channel that task SEQSTART\\[n\\] +will subscribe to"] +pub type CHIDX_R = crate::FieldReader; +#[doc = "Field `CHIDX` writer - DPPI channel that task SEQSTART\\[n\\] +will subscribe to"] +pub type CHIDX_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, SUBSCRIBE_SEQSTART_SPEC, u8, u8, 8, O>; +#[doc = "Field `EN` reader - "] +pub type EN_R = crate::BitReader; +#[doc = "\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum EN_A { + #[doc = "0: Disable subscription"] + DISABLED = 0, + #[doc = "1: Enable subscription"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: EN_A) -> Self { + variant as u8 != 0 + } +} +impl EN_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EN_A { + match self.bits { + false => EN_A::DISABLED, + true => EN_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == EN_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == EN_A::ENABLED + } +} +#[doc = "Field `EN` writer - "] +pub type EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, SUBSCRIBE_SEQSTART_SPEC, EN_A, O>; +impl<'a, const O: u8> EN_W<'a, O> { + #[doc = "Disable subscription"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(EN_A::DISABLED) + } + #[doc = "Enable subscription"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(EN_A::ENABLED) + } +} +impl R { + #[doc = "Bits 0:7 - DPPI channel that task SEQSTART\\[n\\] +will subscribe to"] + #[inline(always)] + pub fn chidx(&self) -> CHIDX_R { + CHIDX_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&self) -> EN_R { + EN_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:7 - DPPI channel that task SEQSTART\\[n\\] +will subscribe to"] + #[inline(always)] + pub fn chidx(&mut self) -> CHIDX_W<0> { + CHIDX_W::new(self) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&mut self) -> EN_W<31> { + EN_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Description collection: Subscribe configuration for task SEQSTART\\[n\\]\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [subscribe_seqstart](index.html) module"] +pub struct SUBSCRIBE_SEQSTART_SPEC; +impl crate::RegisterSpec for SUBSCRIBE_SEQSTART_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [subscribe_seqstart::R](R) reader structure"] +impl crate::Readable for SUBSCRIBE_SEQSTART_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [subscribe_seqstart::W](W) writer structure"] +impl crate::Writable for SUBSCRIBE_SEQSTART_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SUBSCRIBE_SEQSTART[%s] +to value 0"] +impl crate::Resettable for SUBSCRIBE_SEQSTART_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/pwm0_ns/subscribe_stop.rs b/pacs/nrf9120-pac/src/pwm0_ns/subscribe_stop.rs new file mode 100644 index 00000000..2fe3af58 --- /dev/null +++ b/pacs/nrf9120-pac/src/pwm0_ns/subscribe_stop.rs @@ -0,0 +1,140 @@ +#[doc = "Register `SUBSCRIBE_STOP` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SUBSCRIBE_STOP` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CHIDX` reader - DPPI channel that task STOP will subscribe to"] +pub type CHIDX_R = crate::FieldReader; +#[doc = "Field `CHIDX` writer - DPPI channel that task STOP will subscribe to"] +pub type CHIDX_W<'a, const O: u8> = crate::FieldWriter<'a, u32, SUBSCRIBE_STOP_SPEC, u8, u8, 8, O>; +#[doc = "Field `EN` reader - "] +pub type EN_R = crate::BitReader; +#[doc = "\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum EN_A { + #[doc = "0: Disable subscription"] + DISABLED = 0, + #[doc = "1: Enable subscription"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: EN_A) -> Self { + variant as u8 != 0 + } +} +impl EN_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EN_A { + match self.bits { + false => EN_A::DISABLED, + true => EN_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == EN_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == EN_A::ENABLED + } +} +#[doc = "Field `EN` writer - "] +pub type EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, SUBSCRIBE_STOP_SPEC, EN_A, O>; +impl<'a, const O: u8> EN_W<'a, O> { + #[doc = "Disable subscription"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(EN_A::DISABLED) + } + #[doc = "Enable subscription"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(EN_A::ENABLED) + } +} +impl R { + #[doc = "Bits 0:7 - DPPI channel that task STOP will subscribe to"] + #[inline(always)] + pub fn chidx(&self) -> CHIDX_R { + CHIDX_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&self) -> EN_R { + EN_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:7 - DPPI channel that task STOP will subscribe to"] + #[inline(always)] + pub fn chidx(&mut self) -> CHIDX_W<0> { + CHIDX_W::new(self) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&mut self) -> EN_W<31> { + EN_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Subscribe configuration for task STOP\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [subscribe_stop](index.html) module"] +pub struct SUBSCRIBE_STOP_SPEC; +impl crate::RegisterSpec for SUBSCRIBE_STOP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [subscribe_stop::R](R) reader structure"] +impl crate::Readable for SUBSCRIBE_STOP_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [subscribe_stop::W](W) writer structure"] +impl crate::Writable for SUBSCRIBE_STOP_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SUBSCRIBE_STOP to value 0"] +impl crate::Resettable for SUBSCRIBE_STOP_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/pwm0_ns/tasks_nextstep.rs b/pacs/nrf9120-pac/src/pwm0_ns/tasks_nextstep.rs new file mode 100644 index 00000000..f72a8060 --- /dev/null +++ b/pacs/nrf9120-pac/src/pwm0_ns/tasks_nextstep.rs @@ -0,0 +1,72 @@ +#[doc = "Register `TASKS_NEXTSTEP` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Steps by one value in the current sequence on all enabled channels if DECODER.MODE=NextStep. Does not cause PWM generation to start if not running.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum TASKS_NEXTSTEP_AW { + #[doc = "1: Trigger task"] + TRIGGER = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TASKS_NEXTSTEP_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TASKS_NEXTSTEP` writer - Steps by one value in the current sequence on all enabled channels if DECODER.MODE=NextStep. Does not cause PWM generation to start if not running."] +pub type TASKS_NEXTSTEP_W<'a, const O: u8> = + crate::BitWriter<'a, u32, TASKS_NEXTSTEP_SPEC, TASKS_NEXTSTEP_AW, O>; +impl<'a, const O: u8> TASKS_NEXTSTEP_W<'a, O> { + #[doc = "Trigger task"] + #[inline(always)] + pub fn trigger(self) -> &'a mut W { + self.variant(TASKS_NEXTSTEP_AW::TRIGGER) + } +} +impl W { + #[doc = "Bit 0 - Steps by one value in the current sequence on all enabled channels if DECODER.MODE=NextStep. Does not cause PWM generation to start if not running."] + #[inline(always)] + pub fn tasks_nextstep(&mut self) -> TASKS_NEXTSTEP_W<0> { + TASKS_NEXTSTEP_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Steps by one value in the current sequence on all enabled channels if DECODER.MODE=NextStep. Does not cause PWM generation to start if not running.\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tasks_nextstep](index.html) module"] +pub struct TASKS_NEXTSTEP_SPEC; +impl crate::RegisterSpec for TASKS_NEXTSTEP_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [tasks_nextstep::W](W) writer structure"] +impl crate::Writable for TASKS_NEXTSTEP_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets TASKS_NEXTSTEP to value 0"] +impl crate::Resettable for TASKS_NEXTSTEP_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/pwm0_ns/tasks_seqstart.rs b/pacs/nrf9120-pac/src/pwm0_ns/tasks_seqstart.rs new file mode 100644 index 00000000..9dd76bd7 --- /dev/null +++ b/pacs/nrf9120-pac/src/pwm0_ns/tasks_seqstart.rs @@ -0,0 +1,73 @@ +#[doc = "Register `TASKS_SEQSTART[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Loads the first PWM value on all enabled channels from sequence n, and starts playing that sequence at the rate defined in SEQ\\[n\\]REFRESH and/or DECODER.MODE. Causes PWM generation to start if not running.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum TASKS_SEQSTART_AW { + #[doc = "1: Trigger task"] + TRIGGER = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TASKS_SEQSTART_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TASKS_SEQSTART` writer - Loads the first PWM value on all enabled channels from sequence n, and starts playing that sequence at the rate defined in SEQ\\[n\\]REFRESH and/or DECODER.MODE. Causes PWM generation to start if not running."] +pub type TASKS_SEQSTART_W<'a, const O: u8> = + crate::BitWriter<'a, u32, TASKS_SEQSTART_SPEC, TASKS_SEQSTART_AW, O>; +impl<'a, const O: u8> TASKS_SEQSTART_W<'a, O> { + #[doc = "Trigger task"] + #[inline(always)] + pub fn trigger(self) -> &'a mut W { + self.variant(TASKS_SEQSTART_AW::TRIGGER) + } +} +impl W { + #[doc = "Bit 0 - Loads the first PWM value on all enabled channels from sequence n, and starts playing that sequence at the rate defined in SEQ\\[n\\]REFRESH and/or DECODER.MODE. Causes PWM generation to start if not running."] + #[inline(always)] + pub fn tasks_seqstart(&mut self) -> TASKS_SEQSTART_W<0> { + TASKS_SEQSTART_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Description collection: Loads the first PWM value on all enabled channels from sequence n, and starts playing that sequence at the rate defined in SEQ\\[n\\]REFRESH and/or DECODER.MODE. Causes PWM generation to start if not running.\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tasks_seqstart](index.html) module"] +pub struct TASKS_SEQSTART_SPEC; +impl crate::RegisterSpec for TASKS_SEQSTART_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [tasks_seqstart::W](W) writer structure"] +impl crate::Writable for TASKS_SEQSTART_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets TASKS_SEQSTART[%s] +to value 0"] +impl crate::Resettable for TASKS_SEQSTART_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/pwm0_ns/tasks_stop.rs b/pacs/nrf9120-pac/src/pwm0_ns/tasks_stop.rs new file mode 100644 index 00000000..d710c799 --- /dev/null +++ b/pacs/nrf9120-pac/src/pwm0_ns/tasks_stop.rs @@ -0,0 +1,72 @@ +#[doc = "Register `TASKS_STOP` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Stops PWM pulse generation on all channels at the end of current PWM period, and stops sequence playback\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum TASKS_STOP_AW { + #[doc = "1: Trigger task"] + TRIGGER = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TASKS_STOP_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TASKS_STOP` writer - Stops PWM pulse generation on all channels at the end of current PWM period, and stops sequence playback"] +pub type TASKS_STOP_W<'a, const O: u8> = + crate::BitWriter<'a, u32, TASKS_STOP_SPEC, TASKS_STOP_AW, O>; +impl<'a, const O: u8> TASKS_STOP_W<'a, O> { + #[doc = "Trigger task"] + #[inline(always)] + pub fn trigger(self) -> &'a mut W { + self.variant(TASKS_STOP_AW::TRIGGER) + } +} +impl W { + #[doc = "Bit 0 - Stops PWM pulse generation on all channels at the end of current PWM period, and stops sequence playback"] + #[inline(always)] + pub fn tasks_stop(&mut self) -> TASKS_STOP_W<0> { + TASKS_STOP_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Stops PWM pulse generation on all channels at the end of current PWM period, and stops sequence playback\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tasks_stop](index.html) module"] +pub struct TASKS_STOP_SPEC; +impl crate::RegisterSpec for TASKS_STOP_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [tasks_stop::W](W) writer structure"] +impl crate::Writable for TASKS_STOP_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets TASKS_STOP to value 0"] +impl crate::Resettable for TASKS_STOP_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/regulators_ns.rs b/pacs/nrf9120-pac/src/regulators_ns.rs new file mode 100644 index 00000000..ba737dc8 --- /dev/null +++ b/pacs/nrf9120-pac/src/regulators_ns.rs @@ -0,0 +1,25 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + _reserved0: [u8; 0x0500], + #[doc = "0x500 - System OFF register"] + pub systemoff: SYSTEMOFF, + _reserved1: [u8; 0x10], + #[doc = "0x514 - External power failure warning configuration"] + pub extpofcon: EXTPOFCON, + _reserved2: [u8; 0x60], + #[doc = "0x578 - Enable DC/DC mode of the main voltage regulator."] + pub dcdcen: DCDCEN, +} +#[doc = "SYSTEMOFF (w) register accessor: an alias for `Reg`"] +pub type SYSTEMOFF = crate::Reg; +#[doc = "System OFF register"] +pub mod systemoff; +#[doc = "EXTPOFCON (rw) register accessor: an alias for `Reg`"] +pub type EXTPOFCON = crate::Reg; +#[doc = "External power failure warning configuration"] +pub mod extpofcon; +#[doc = "DCDCEN (rw) register accessor: an alias for `Reg`"] +pub type DCDCEN = crate::Reg; +#[doc = "Enable DC/DC mode of the main voltage regulator."] +pub mod dcdcen; diff --git a/pacs/nrf9120-pac/src/regulators_ns/dcdcen.rs b/pacs/nrf9120-pac/src/regulators_ns/dcdcen.rs new file mode 100644 index 00000000..724f347b --- /dev/null +++ b/pacs/nrf9120-pac/src/regulators_ns/dcdcen.rs @@ -0,0 +1,126 @@ +#[doc = "Register `DCDCEN` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DCDCEN` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DCDCEN` reader - Enable DC/DC converter"] +pub type DCDCEN_R = crate::BitReader; +#[doc = "Enable DC/DC converter\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum DCDCEN_A { + #[doc = "0: DC/DC mode is disabled"] + DISABLED = 0, + #[doc = "1: DC/DC mode is enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: DCDCEN_A) -> Self { + variant as u8 != 0 + } +} +impl DCDCEN_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> DCDCEN_A { + match self.bits { + false => DCDCEN_A::DISABLED, + true => DCDCEN_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == DCDCEN_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == DCDCEN_A::ENABLED + } +} +#[doc = "Field `DCDCEN` writer - Enable DC/DC converter"] +pub type DCDCEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, DCDCEN_SPEC, DCDCEN_A, O>; +impl<'a, const O: u8> DCDCEN_W<'a, O> { + #[doc = "DC/DC mode is disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(DCDCEN_A::DISABLED) + } + #[doc = "DC/DC mode is enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(DCDCEN_A::ENABLED) + } +} +impl R { + #[doc = "Bit 0 - Enable DC/DC converter"] + #[inline(always)] + pub fn dcdcen(&self) -> DCDCEN_R { + DCDCEN_R::new((self.bits & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Enable DC/DC converter"] + #[inline(always)] + pub fn dcdcen(&mut self) -> DCDCEN_W<0> { + DCDCEN_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Enable DC/DC mode of the main voltage regulator.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dcdcen](index.html) module"] +pub struct DCDCEN_SPEC; +impl crate::RegisterSpec for DCDCEN_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dcdcen::R](R) reader structure"] +impl crate::Readable for DCDCEN_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dcdcen::W](W) writer structure"] +impl crate::Writable for DCDCEN_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DCDCEN to value 0"] +impl crate::Resettable for DCDCEN_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/regulators_ns/extpofcon.rs b/pacs/nrf9120-pac/src/regulators_ns/extpofcon.rs new file mode 100644 index 00000000..a9f142f1 --- /dev/null +++ b/pacs/nrf9120-pac/src/regulators_ns/extpofcon.rs @@ -0,0 +1,126 @@ +#[doc = "Register `EXTPOFCON` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EXTPOFCON` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `POF` reader - Enable or disable external power failure warning"] +pub type POF_R = crate::BitReader; +#[doc = "Enable or disable external power failure warning\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum POF_A { + #[doc = "0: Disable"] + DISABLED = 0, + #[doc = "1: Enable"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: POF_A) -> Self { + variant as u8 != 0 + } +} +impl POF_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> POF_A { + match self.bits { + false => POF_A::DISABLED, + true => POF_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == POF_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == POF_A::ENABLED + } +} +#[doc = "Field `POF` writer - Enable or disable external power failure warning"] +pub type POF_W<'a, const O: u8> = crate::BitWriter<'a, u32, EXTPOFCON_SPEC, POF_A, O>; +impl<'a, const O: u8> POF_W<'a, O> { + #[doc = "Disable"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(POF_A::DISABLED) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(POF_A::ENABLED) + } +} +impl R { + #[doc = "Bit 0 - Enable or disable external power failure warning"] + #[inline(always)] + pub fn pof(&self) -> POF_R { + POF_R::new((self.bits & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Enable or disable external power failure warning"] + #[inline(always)] + pub fn pof(&mut self) -> POF_W<0> { + POF_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "External power failure warning configuration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [extpofcon](index.html) module"] +pub struct EXTPOFCON_SPEC; +impl crate::RegisterSpec for EXTPOFCON_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [extpofcon::R](R) reader structure"] +impl crate::Readable for EXTPOFCON_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [extpofcon::W](W) writer structure"] +impl crate::Writable for EXTPOFCON_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EXTPOFCON to value 0"] +impl crate::Resettable for EXTPOFCON_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/regulators_ns/systemoff.rs b/pacs/nrf9120-pac/src/regulators_ns/systemoff.rs new file mode 100644 index 00000000..f84bd454 --- /dev/null +++ b/pacs/nrf9120-pac/src/regulators_ns/systemoff.rs @@ -0,0 +1,71 @@ +#[doc = "Register `SYSTEMOFF` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Enable System OFF mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum SYSTEMOFF_AW { + #[doc = "1: Enable System OFF mode"] + ENABLE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: SYSTEMOFF_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SYSTEMOFF` writer - Enable System OFF mode"] +pub type SYSTEMOFF_W<'a, const O: u8> = crate::BitWriter<'a, u32, SYSTEMOFF_SPEC, SYSTEMOFF_AW, O>; +impl<'a, const O: u8> SYSTEMOFF_W<'a, O> { + #[doc = "Enable System OFF mode"] + #[inline(always)] + pub fn enable(self) -> &'a mut W { + self.variant(SYSTEMOFF_AW::ENABLE) + } +} +impl W { + #[doc = "Bit 0 - Enable System OFF mode"] + #[inline(always)] + pub fn systemoff(&mut self) -> SYSTEMOFF_W<0> { + SYSTEMOFF_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "System OFF register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [systemoff](index.html) module"] +pub struct SYSTEMOFF_SPEC; +impl crate::RegisterSpec for SYSTEMOFF_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [systemoff::W](W) writer structure"] +impl crate::Writable for SYSTEMOFF_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SYSTEMOFF to value 0"] +impl crate::Resettable for SYSTEMOFF_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/rtc0_ns.rs b/pacs/nrf9120-pac/src/rtc0_ns.rs new file mode 100644 index 00000000..1e5f6f67 --- /dev/null +++ b/pacs/nrf9120-pac/src/rtc0_ns.rs @@ -0,0 +1,147 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Start RTC counter"] + pub tasks_start: TASKS_START, + #[doc = "0x04 - Stop RTC counter"] + pub tasks_stop: TASKS_STOP, + #[doc = "0x08 - Clear RTC counter"] + pub tasks_clear: TASKS_CLEAR, + #[doc = "0x0c - Set counter to 0xFFFFF0"] + pub tasks_trigovrflw: TASKS_TRIGOVRFLW, + _reserved4: [u8; 0x70], + #[doc = "0x80 - Subscribe configuration for task START"] + pub subscribe_start: SUBSCRIBE_START, + #[doc = "0x84 - Subscribe configuration for task STOP"] + pub subscribe_stop: SUBSCRIBE_STOP, + #[doc = "0x88 - Subscribe configuration for task CLEAR"] + pub subscribe_clear: SUBSCRIBE_CLEAR, + #[doc = "0x8c - Subscribe configuration for task TRIGOVRFLW"] + pub subscribe_trigovrflw: SUBSCRIBE_TRIGOVRFLW, + _reserved8: [u8; 0x70], + #[doc = "0x100 - Event on counter increment"] + pub events_tick: EVENTS_TICK, + #[doc = "0x104 - Event on counter overflow"] + pub events_ovrflw: EVENTS_OVRFLW, + _reserved10: [u8; 0x38], + #[doc = "0x140..0x150 - Description collection: Compare event on CC\\[n\\] +match"] + pub events_compare: [EVENTS_COMPARE; 4], + _reserved11: [u8; 0x30], + #[doc = "0x180 - Publish configuration for event TICK"] + pub publish_tick: PUBLISH_TICK, + #[doc = "0x184 - Publish configuration for event OVRFLW"] + pub publish_ovrflw: PUBLISH_OVRFLW, + _reserved13: [u8; 0x38], + #[doc = "0x1c0..0x1d0 - Description collection: Publish configuration for event COMPARE\\[n\\]"] + pub publish_compare: [PUBLISH_COMPARE; 4], + _reserved14: [u8; 0x0134], + #[doc = "0x304 - Enable interrupt"] + pub intenset: INTENSET, + #[doc = "0x308 - Disable interrupt"] + pub intenclr: INTENCLR, + _reserved16: [u8; 0x34], + #[doc = "0x340 - Enable or disable event routing"] + pub evten: EVTEN, + #[doc = "0x344 - Enable event routing"] + pub evtenset: EVTENSET, + #[doc = "0x348 - Disable event routing"] + pub evtenclr: EVTENCLR, + _reserved19: [u8; 0x01b8], + #[doc = "0x504 - Current counter value"] + pub counter: COUNTER, + #[doc = "0x508 - 12-bit prescaler for counter frequency (32768/(PRESCALER+1)). Must be written when RTC is stopped."] + pub prescaler: PRESCALER, + _reserved21: [u8; 0x34], + #[doc = "0x540..0x550 - Description collection: Compare register n"] + pub cc: [CC; 4], +} +#[doc = "TASKS_START (w) register accessor: an alias for `Reg`"] +pub type TASKS_START = crate::Reg; +#[doc = "Start RTC counter"] +pub mod tasks_start; +#[doc = "TASKS_STOP (w) register accessor: an alias for `Reg`"] +pub type TASKS_STOP = crate::Reg; +#[doc = "Stop RTC counter"] +pub mod tasks_stop; +#[doc = "TASKS_CLEAR (w) register accessor: an alias for `Reg`"] +pub type TASKS_CLEAR = crate::Reg; +#[doc = "Clear RTC counter"] +pub mod tasks_clear; +#[doc = "TASKS_TRIGOVRFLW (w) register accessor: an alias for `Reg`"] +pub type TASKS_TRIGOVRFLW = crate::Reg; +#[doc = "Set counter to 0xFFFFF0"] +pub mod tasks_trigovrflw; +#[doc = "SUBSCRIBE_START (rw) register accessor: an alias for `Reg`"] +pub type SUBSCRIBE_START = crate::Reg; +#[doc = "Subscribe configuration for task START"] +pub mod subscribe_start; +#[doc = "SUBSCRIBE_STOP (rw) register accessor: an alias for `Reg`"] +pub type SUBSCRIBE_STOP = crate::Reg; +#[doc = "Subscribe configuration for task STOP"] +pub mod subscribe_stop; +#[doc = "SUBSCRIBE_CLEAR (rw) register accessor: an alias for `Reg`"] +pub type SUBSCRIBE_CLEAR = crate::Reg; +#[doc = "Subscribe configuration for task CLEAR"] +pub mod subscribe_clear; +#[doc = "SUBSCRIBE_TRIGOVRFLW (rw) register accessor: an alias for `Reg`"] +pub type SUBSCRIBE_TRIGOVRFLW = crate::Reg; +#[doc = "Subscribe configuration for task TRIGOVRFLW"] +pub mod subscribe_trigovrflw; +#[doc = "EVENTS_TICK (rw) register accessor: an alias for `Reg`"] +pub type EVENTS_TICK = crate::Reg; +#[doc = "Event on counter increment"] +pub mod events_tick; +#[doc = "EVENTS_OVRFLW (rw) register accessor: an alias for `Reg`"] +pub type EVENTS_OVRFLW = crate::Reg; +#[doc = "Event on counter overflow"] +pub mod events_ovrflw; +#[doc = "EVENTS_COMPARE (rw) register accessor: an alias for `Reg`"] +pub type EVENTS_COMPARE = crate::Reg; +#[doc = "Description collection: Compare event on CC\\[n\\] +match"] +pub mod events_compare; +#[doc = "PUBLISH_TICK (rw) register accessor: an alias for `Reg`"] +pub type PUBLISH_TICK = crate::Reg; +#[doc = "Publish configuration for event TICK"] +pub mod publish_tick; +#[doc = "PUBLISH_OVRFLW (rw) register accessor: an alias for `Reg`"] +pub type PUBLISH_OVRFLW = crate::Reg; +#[doc = "Publish configuration for event OVRFLW"] +pub mod publish_ovrflw; +#[doc = "PUBLISH_COMPARE (rw) register accessor: an alias for `Reg`"] +pub type PUBLISH_COMPARE = crate::Reg; +#[doc = "Description collection: Publish configuration for event COMPARE\\[n\\]"] +pub mod publish_compare; +#[doc = "INTENSET (rw) register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "Enable interrupt"] +pub mod intenset; +#[doc = "INTENCLR (rw) register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "Disable interrupt"] +pub mod intenclr; +#[doc = "EVTEN (rw) register accessor: an alias for `Reg`"] +pub type EVTEN = crate::Reg; +#[doc = "Enable or disable event routing"] +pub mod evten; +#[doc = "EVTENSET (rw) register accessor: an alias for `Reg`"] +pub type EVTENSET = crate::Reg; +#[doc = "Enable event routing"] +pub mod evtenset; +#[doc = "EVTENCLR (rw) register accessor: an alias for `Reg`"] +pub type EVTENCLR = crate::Reg; +#[doc = "Disable event routing"] +pub mod evtenclr; +#[doc = "COUNTER (r) register accessor: an alias for `Reg`"] +pub type COUNTER = crate::Reg; +#[doc = "Current counter value"] +pub mod counter; +#[doc = "PRESCALER (rw) register accessor: an alias for `Reg`"] +pub type PRESCALER = crate::Reg; +#[doc = "12-bit prescaler for counter frequency (32768/(PRESCALER+1)). Must be written when RTC is stopped."] +pub mod prescaler; +#[doc = "CC (rw) register accessor: an alias for `Reg`"] +pub type CC = crate::Reg; +#[doc = "Description collection: Compare register n"] +pub mod cc; diff --git a/pacs/nrf9120-pac/src/rtc0_ns/cc.rs b/pacs/nrf9120-pac/src/rtc0_ns/cc.rs new file mode 100644 index 00000000..65587ab8 --- /dev/null +++ b/pacs/nrf9120-pac/src/rtc0_ns/cc.rs @@ -0,0 +1,81 @@ +#[doc = "Register `CC[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CC[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `COMPARE` reader - Compare value"] +pub type COMPARE_R = crate::FieldReader; +#[doc = "Field `COMPARE` writer - Compare value"] +pub type COMPARE_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CC_SPEC, u32, u32, 24, O>; +impl R { + #[doc = "Bits 0:23 - Compare value"] + #[inline(always)] + pub fn compare(&self) -> COMPARE_R { + COMPARE_R::new((self.bits & 0x00ff_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:23 - Compare value"] + #[inline(always)] + pub fn compare(&mut self) -> COMPARE_W<0> { + COMPARE_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Description collection: Compare register n\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cc](index.html) module"] +pub struct CC_SPEC; +impl crate::RegisterSpec for CC_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cc::R](R) reader structure"] +impl crate::Readable for CC_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [cc::W](W) writer structure"] +impl crate::Writable for CC_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CC[%s] +to value 0"] +impl crate::Resettable for CC_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/rtc0_ns/counter.rs b/pacs/nrf9120-pac/src/rtc0_ns/counter.rs new file mode 100644 index 00000000..81b11c7e --- /dev/null +++ b/pacs/nrf9120-pac/src/rtc0_ns/counter.rs @@ -0,0 +1,40 @@ +#[doc = "Register `COUNTER` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `COUNTER` reader - Counter value"] +pub type COUNTER_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:23 - Counter value"] + #[inline(always)] + pub fn counter(&self) -> COUNTER_R { + COUNTER_R::new((self.bits & 0x00ff_ffff) as u32) + } +} +#[doc = "Current counter value\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [counter](index.html) module"] +pub struct COUNTER_SPEC; +impl crate::RegisterSpec for COUNTER_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [counter::R](R) reader structure"] +impl crate::Readable for COUNTER_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets COUNTER to value 0"] +impl crate::Resettable for COUNTER_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/rtc0_ns/events_compare.rs b/pacs/nrf9120-pac/src/rtc0_ns/events_compare.rs new file mode 100644 index 00000000..07f8b944 --- /dev/null +++ b/pacs/nrf9120-pac/src/rtc0_ns/events_compare.rs @@ -0,0 +1,134 @@ +#[doc = "Register `EVENTS_COMPARE[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVENTS_COMPARE[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `EVENTS_COMPARE` reader - Compare event on CC\\[n\\] +match"] +pub type EVENTS_COMPARE_R = crate::BitReader; +#[doc = "Compare event on CC\\[n\\] +match\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum EVENTS_COMPARE_A { + #[doc = "0: Event not generated"] + NOT_GENERATED = 0, + #[doc = "1: Event generated"] + GENERATED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: EVENTS_COMPARE_A) -> Self { + variant as u8 != 0 + } +} +impl EVENTS_COMPARE_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EVENTS_COMPARE_A { + match self.bits { + false => EVENTS_COMPARE_A::NOT_GENERATED, + true => EVENTS_COMPARE_A::GENERATED, + } + } + #[doc = "Checks if the value of the field is `NOT_GENERATED`"] + #[inline(always)] + pub fn is_not_generated(&self) -> bool { + *self == EVENTS_COMPARE_A::NOT_GENERATED + } + #[doc = "Checks if the value of the field is `GENERATED`"] + #[inline(always)] + pub fn is_generated(&self) -> bool { + *self == EVENTS_COMPARE_A::GENERATED + } +} +#[doc = "Field `EVENTS_COMPARE` writer - Compare event on CC\\[n\\] +match"] +pub type EVENTS_COMPARE_W<'a, const O: u8> = + crate::BitWriter<'a, u32, EVENTS_COMPARE_SPEC, EVENTS_COMPARE_A, O>; +impl<'a, const O: u8> EVENTS_COMPARE_W<'a, O> { + #[doc = "Event not generated"] + #[inline(always)] + pub fn not_generated(self) -> &'a mut W { + self.variant(EVENTS_COMPARE_A::NOT_GENERATED) + } + #[doc = "Event generated"] + #[inline(always)] + pub fn generated(self) -> &'a mut W { + self.variant(EVENTS_COMPARE_A::GENERATED) + } +} +impl R { + #[doc = "Bit 0 - Compare event on CC\\[n\\] +match"] + #[inline(always)] + pub fn events_compare(&self) -> EVENTS_COMPARE_R { + EVENTS_COMPARE_R::new((self.bits & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Compare event on CC\\[n\\] +match"] + #[inline(always)] + pub fn events_compare(&mut self) -> EVENTS_COMPARE_W<0> { + EVENTS_COMPARE_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Description collection: Compare event on CC\\[n\\] +match\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [events_compare](index.html) module"] +pub struct EVENTS_COMPARE_SPEC; +impl crate::RegisterSpec for EVENTS_COMPARE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [events_compare::R](R) reader structure"] +impl crate::Readable for EVENTS_COMPARE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [events_compare::W](W) writer structure"] +impl crate::Writable for EVENTS_COMPARE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EVENTS_COMPARE[%s] +to value 0"] +impl crate::Resettable for EVENTS_COMPARE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/rtc0_ns/events_ovrflw.rs b/pacs/nrf9120-pac/src/rtc0_ns/events_ovrflw.rs new file mode 100644 index 00000000..14ec7d39 --- /dev/null +++ b/pacs/nrf9120-pac/src/rtc0_ns/events_ovrflw.rs @@ -0,0 +1,127 @@ +#[doc = "Register `EVENTS_OVRFLW` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVENTS_OVRFLW` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `EVENTS_OVRFLW` reader - Event on counter overflow"] +pub type EVENTS_OVRFLW_R = crate::BitReader; +#[doc = "Event on counter overflow\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum EVENTS_OVRFLW_A { + #[doc = "0: Event not generated"] + NOT_GENERATED = 0, + #[doc = "1: Event generated"] + GENERATED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: EVENTS_OVRFLW_A) -> Self { + variant as u8 != 0 + } +} +impl EVENTS_OVRFLW_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EVENTS_OVRFLW_A { + match self.bits { + false => EVENTS_OVRFLW_A::NOT_GENERATED, + true => EVENTS_OVRFLW_A::GENERATED, + } + } + #[doc = "Checks if the value of the field is `NOT_GENERATED`"] + #[inline(always)] + pub fn is_not_generated(&self) -> bool { + *self == EVENTS_OVRFLW_A::NOT_GENERATED + } + #[doc = "Checks if the value of the field is `GENERATED`"] + #[inline(always)] + pub fn is_generated(&self) -> bool { + *self == EVENTS_OVRFLW_A::GENERATED + } +} +#[doc = "Field `EVENTS_OVRFLW` writer - Event on counter overflow"] +pub type EVENTS_OVRFLW_W<'a, const O: u8> = + crate::BitWriter<'a, u32, EVENTS_OVRFLW_SPEC, EVENTS_OVRFLW_A, O>; +impl<'a, const O: u8> EVENTS_OVRFLW_W<'a, O> { + #[doc = "Event not generated"] + #[inline(always)] + pub fn not_generated(self) -> &'a mut W { + self.variant(EVENTS_OVRFLW_A::NOT_GENERATED) + } + #[doc = "Event generated"] + #[inline(always)] + pub fn generated(self) -> &'a mut W { + self.variant(EVENTS_OVRFLW_A::GENERATED) + } +} +impl R { + #[doc = "Bit 0 - Event on counter overflow"] + #[inline(always)] + pub fn events_ovrflw(&self) -> EVENTS_OVRFLW_R { + EVENTS_OVRFLW_R::new((self.bits & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Event on counter overflow"] + #[inline(always)] + pub fn events_ovrflw(&mut self) -> EVENTS_OVRFLW_W<0> { + EVENTS_OVRFLW_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Event on counter overflow\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [events_ovrflw](index.html) module"] +pub struct EVENTS_OVRFLW_SPEC; +impl crate::RegisterSpec for EVENTS_OVRFLW_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [events_ovrflw::R](R) reader structure"] +impl crate::Readable for EVENTS_OVRFLW_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [events_ovrflw::W](W) writer structure"] +impl crate::Writable for EVENTS_OVRFLW_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EVENTS_OVRFLW to value 0"] +impl crate::Resettable for EVENTS_OVRFLW_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/rtc0_ns/events_tick.rs b/pacs/nrf9120-pac/src/rtc0_ns/events_tick.rs new file mode 100644 index 00000000..4cccd4a8 --- /dev/null +++ b/pacs/nrf9120-pac/src/rtc0_ns/events_tick.rs @@ -0,0 +1,127 @@ +#[doc = "Register `EVENTS_TICK` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVENTS_TICK` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `EVENTS_TICK` reader - Event on counter increment"] +pub type EVENTS_TICK_R = crate::BitReader; +#[doc = "Event on counter increment\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum EVENTS_TICK_A { + #[doc = "0: Event not generated"] + NOT_GENERATED = 0, + #[doc = "1: Event generated"] + GENERATED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: EVENTS_TICK_A) -> Self { + variant as u8 != 0 + } +} +impl EVENTS_TICK_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EVENTS_TICK_A { + match self.bits { + false => EVENTS_TICK_A::NOT_GENERATED, + true => EVENTS_TICK_A::GENERATED, + } + } + #[doc = "Checks if the value of the field is `NOT_GENERATED`"] + #[inline(always)] + pub fn is_not_generated(&self) -> bool { + *self == EVENTS_TICK_A::NOT_GENERATED + } + #[doc = "Checks if the value of the field is `GENERATED`"] + #[inline(always)] + pub fn is_generated(&self) -> bool { + *self == EVENTS_TICK_A::GENERATED + } +} +#[doc = "Field `EVENTS_TICK` writer - Event on counter increment"] +pub type EVENTS_TICK_W<'a, const O: u8> = + crate::BitWriter<'a, u32, EVENTS_TICK_SPEC, EVENTS_TICK_A, O>; +impl<'a, const O: u8> EVENTS_TICK_W<'a, O> { + #[doc = "Event not generated"] + #[inline(always)] + pub fn not_generated(self) -> &'a mut W { + self.variant(EVENTS_TICK_A::NOT_GENERATED) + } + #[doc = "Event generated"] + #[inline(always)] + pub fn generated(self) -> &'a mut W { + self.variant(EVENTS_TICK_A::GENERATED) + } +} +impl R { + #[doc = "Bit 0 - Event on counter increment"] + #[inline(always)] + pub fn events_tick(&self) -> EVENTS_TICK_R { + EVENTS_TICK_R::new((self.bits & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Event on counter increment"] + #[inline(always)] + pub fn events_tick(&mut self) -> EVENTS_TICK_W<0> { + EVENTS_TICK_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Event on counter increment\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [events_tick](index.html) module"] +pub struct EVENTS_TICK_SPEC; +impl crate::RegisterSpec for EVENTS_TICK_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [events_tick::R](R) reader structure"] +impl crate::Readable for EVENTS_TICK_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [events_tick::W](W) writer structure"] +impl crate::Writable for EVENTS_TICK_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EVENTS_TICK to value 0"] +impl crate::Resettable for EVENTS_TICK_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/rtc0_ns/evten.rs b/pacs/nrf9120-pac/src/rtc0_ns/evten.rs new file mode 100644 index 00000000..b4a88652 --- /dev/null +++ b/pacs/nrf9120-pac/src/rtc0_ns/evten.rs @@ -0,0 +1,426 @@ +#[doc = "Register `EVTEN` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVTEN` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `TICK` reader - Enable or disable event routing for event TICK"] +pub type TICK_R = crate::BitReader; +#[doc = "Enable or disable event routing for event TICK\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum TICK_A { + #[doc = "0: Disable"] + DISABLED = 0, + #[doc = "1: Enable"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TICK_A) -> Self { + variant as u8 != 0 + } +} +impl TICK_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> TICK_A { + match self.bits { + false => TICK_A::DISABLED, + true => TICK_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == TICK_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == TICK_A::ENABLED + } +} +#[doc = "Field `TICK` writer - Enable or disable event routing for event TICK"] +pub type TICK_W<'a, const O: u8> = crate::BitWriter<'a, u32, EVTEN_SPEC, TICK_A, O>; +impl<'a, const O: u8> TICK_W<'a, O> { + #[doc = "Disable"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(TICK_A::DISABLED) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(TICK_A::ENABLED) + } +} +#[doc = "Field `OVRFLW` reader - Enable or disable event routing for event OVRFLW"] +pub type OVRFLW_R = crate::BitReader; +#[doc = "Enable or disable event routing for event OVRFLW\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum OVRFLW_A { + #[doc = "0: Disable"] + DISABLED = 0, + #[doc = "1: Enable"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: OVRFLW_A) -> Self { + variant as u8 != 0 + } +} +impl OVRFLW_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> OVRFLW_A { + match self.bits { + false => OVRFLW_A::DISABLED, + true => OVRFLW_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == OVRFLW_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == OVRFLW_A::ENABLED + } +} +#[doc = "Field `OVRFLW` writer - Enable or disable event routing for event OVRFLW"] +pub type OVRFLW_W<'a, const O: u8> = crate::BitWriter<'a, u32, EVTEN_SPEC, OVRFLW_A, O>; +impl<'a, const O: u8> OVRFLW_W<'a, O> { + #[doc = "Disable"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(OVRFLW_A::DISABLED) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(OVRFLW_A::ENABLED) + } +} +#[doc = "Field `COMPARE0` reader - Enable or disable event routing for event COMPARE\\[0\\]"] +pub type COMPARE0_R = crate::BitReader; +#[doc = "Enable or disable event routing for event COMPARE\\[0\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum COMPARE0_A { + #[doc = "0: Disable"] + DISABLED = 0, + #[doc = "1: Enable"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: COMPARE0_A) -> Self { + variant as u8 != 0 + } +} +impl COMPARE0_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> COMPARE0_A { + match self.bits { + false => COMPARE0_A::DISABLED, + true => COMPARE0_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == COMPARE0_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == COMPARE0_A::ENABLED + } +} +#[doc = "Field `COMPARE0` writer - Enable or disable event routing for event COMPARE\\[0\\]"] +pub type COMPARE0_W<'a, const O: u8> = crate::BitWriter<'a, u32, EVTEN_SPEC, COMPARE0_A, O>; +impl<'a, const O: u8> COMPARE0_W<'a, O> { + #[doc = "Disable"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(COMPARE0_A::DISABLED) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(COMPARE0_A::ENABLED) + } +} +#[doc = "Field `COMPARE1` reader - Enable or disable event routing for event COMPARE\\[1\\]"] +pub type COMPARE1_R = crate::BitReader; +#[doc = "Enable or disable event routing for event COMPARE\\[1\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum COMPARE1_A { + #[doc = "0: Disable"] + DISABLED = 0, + #[doc = "1: Enable"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: COMPARE1_A) -> Self { + variant as u8 != 0 + } +} +impl COMPARE1_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> COMPARE1_A { + match self.bits { + false => COMPARE1_A::DISABLED, + true => COMPARE1_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == COMPARE1_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == COMPARE1_A::ENABLED + } +} +#[doc = "Field `COMPARE1` writer - Enable or disable event routing for event COMPARE\\[1\\]"] +pub type COMPARE1_W<'a, const O: u8> = crate::BitWriter<'a, u32, EVTEN_SPEC, COMPARE1_A, O>; +impl<'a, const O: u8> COMPARE1_W<'a, O> { + #[doc = "Disable"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(COMPARE1_A::DISABLED) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(COMPARE1_A::ENABLED) + } +} +#[doc = "Field `COMPARE2` reader - Enable or disable event routing for event COMPARE\\[2\\]"] +pub type COMPARE2_R = crate::BitReader; +#[doc = "Enable or disable event routing for event COMPARE\\[2\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum COMPARE2_A { + #[doc = "0: Disable"] + DISABLED = 0, + #[doc = "1: Enable"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: COMPARE2_A) -> Self { + variant as u8 != 0 + } +} +impl COMPARE2_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> COMPARE2_A { + match self.bits { + false => COMPARE2_A::DISABLED, + true => COMPARE2_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == COMPARE2_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == COMPARE2_A::ENABLED + } +} +#[doc = "Field `COMPARE2` writer - Enable or disable event routing for event COMPARE\\[2\\]"] +pub type COMPARE2_W<'a, const O: u8> = crate::BitWriter<'a, u32, EVTEN_SPEC, COMPARE2_A, O>; +impl<'a, const O: u8> COMPARE2_W<'a, O> { + #[doc = "Disable"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(COMPARE2_A::DISABLED) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(COMPARE2_A::ENABLED) + } +} +#[doc = "Field `COMPARE3` reader - Enable or disable event routing for event COMPARE\\[3\\]"] +pub type COMPARE3_R = crate::BitReader; +#[doc = "Enable or disable event routing for event COMPARE\\[3\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum COMPARE3_A { + #[doc = "0: Disable"] + DISABLED = 0, + #[doc = "1: Enable"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: COMPARE3_A) -> Self { + variant as u8 != 0 + } +} +impl COMPARE3_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> COMPARE3_A { + match self.bits { + false => COMPARE3_A::DISABLED, + true => COMPARE3_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == COMPARE3_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == COMPARE3_A::ENABLED + } +} +#[doc = "Field `COMPARE3` writer - Enable or disable event routing for event COMPARE\\[3\\]"] +pub type COMPARE3_W<'a, const O: u8> = crate::BitWriter<'a, u32, EVTEN_SPEC, COMPARE3_A, O>; +impl<'a, const O: u8> COMPARE3_W<'a, O> { + #[doc = "Disable"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(COMPARE3_A::DISABLED) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(COMPARE3_A::ENABLED) + } +} +impl R { + #[doc = "Bit 0 - Enable or disable event routing for event TICK"] + #[inline(always)] + pub fn tick(&self) -> TICK_R { + TICK_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Enable or disable event routing for event OVRFLW"] + #[inline(always)] + pub fn ovrflw(&self) -> OVRFLW_R { + OVRFLW_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 16 - Enable or disable event routing for event COMPARE\\[0\\]"] + #[inline(always)] + pub fn compare0(&self) -> COMPARE0_R { + COMPARE0_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Enable or disable event routing for event COMPARE\\[1\\]"] + #[inline(always)] + pub fn compare1(&self) -> COMPARE1_R { + COMPARE1_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Enable or disable event routing for event COMPARE\\[2\\]"] + #[inline(always)] + pub fn compare2(&self) -> COMPARE2_R { + COMPARE2_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Enable or disable event routing for event COMPARE\\[3\\]"] + #[inline(always)] + pub fn compare3(&self) -> COMPARE3_R { + COMPARE3_R::new(((self.bits >> 19) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Enable or disable event routing for event TICK"] + #[inline(always)] + pub fn tick(&mut self) -> TICK_W<0> { + TICK_W::new(self) + } + #[doc = "Bit 1 - Enable or disable event routing for event OVRFLW"] + #[inline(always)] + pub fn ovrflw(&mut self) -> OVRFLW_W<1> { + OVRFLW_W::new(self) + } + #[doc = "Bit 16 - Enable or disable event routing for event COMPARE\\[0\\]"] + #[inline(always)] + pub fn compare0(&mut self) -> COMPARE0_W<16> { + COMPARE0_W::new(self) + } + #[doc = "Bit 17 - Enable or disable event routing for event COMPARE\\[1\\]"] + #[inline(always)] + pub fn compare1(&mut self) -> COMPARE1_W<17> { + COMPARE1_W::new(self) + } + #[doc = "Bit 18 - Enable or disable event routing for event COMPARE\\[2\\]"] + #[inline(always)] + pub fn compare2(&mut self) -> COMPARE2_W<18> { + COMPARE2_W::new(self) + } + #[doc = "Bit 19 - Enable or disable event routing for event COMPARE\\[3\\]"] + #[inline(always)] + pub fn compare3(&mut self) -> COMPARE3_W<19> { + COMPARE3_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Enable or disable event routing\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [evten](index.html) module"] +pub struct EVTEN_SPEC; +impl crate::RegisterSpec for EVTEN_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [evten::R](R) reader structure"] +impl crate::Readable for EVTEN_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [evten::W](W) writer structure"] +impl crate::Writable for EVTEN_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EVTEN to value 0"] +impl crate::Resettable for EVTEN_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/rtc0_ns/evtenclr.rs b/pacs/nrf9120-pac/src/rtc0_ns/evtenclr.rs new file mode 100644 index 00000000..64de7102 --- /dev/null +++ b/pacs/nrf9120-pac/src/rtc0_ns/evtenclr.rs @@ -0,0 +1,468 @@ +#[doc = "Register `EVTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `TICK` reader - Write '1' to disable event routing for event TICK"] +pub type TICK_R = crate::BitReader; +#[doc = "Write '1' to disable event routing for event TICK\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum TICK_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TICK_A) -> Self { + variant as u8 != 0 + } +} +impl TICK_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> TICK_A { + match self.bits { + false => TICK_A::DISABLED, + true => TICK_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == TICK_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == TICK_A::ENABLED + } +} +#[doc = "Write '1' to disable event routing for event TICK\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum TICK_AW { + #[doc = "1: Disable"] + CLEAR = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TICK_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TICK` writer - Write '1' to disable event routing for event TICK"] +pub type TICK_W<'a, const O: u8> = crate::BitWriter<'a, u32, EVTENCLR_SPEC, TICK_AW, O>; +impl<'a, const O: u8> TICK_W<'a, O> { + #[doc = "Disable"] + #[inline(always)] + pub fn clear(self) -> &'a mut W { + self.variant(TICK_AW::CLEAR) + } +} +#[doc = "Field `OVRFLW` reader - Write '1' to disable event routing for event OVRFLW"] +pub type OVRFLW_R = crate::BitReader; +#[doc = "Write '1' to disable event routing for event OVRFLW\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum OVRFLW_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: OVRFLW_A) -> Self { + variant as u8 != 0 + } +} +impl OVRFLW_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> OVRFLW_A { + match self.bits { + false => OVRFLW_A::DISABLED, + true => OVRFLW_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == OVRFLW_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == OVRFLW_A::ENABLED + } +} +#[doc = "Write '1' to disable event routing for event OVRFLW\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum OVRFLW_AW { + #[doc = "1: Disable"] + CLEAR = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: OVRFLW_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `OVRFLW` writer - Write '1' to disable event routing for event OVRFLW"] +pub type OVRFLW_W<'a, const O: u8> = crate::BitWriter<'a, u32, EVTENCLR_SPEC, OVRFLW_AW, O>; +impl<'a, const O: u8> OVRFLW_W<'a, O> { + #[doc = "Disable"] + #[inline(always)] + pub fn clear(self) -> &'a mut W { + self.variant(OVRFLW_AW::CLEAR) + } +} +#[doc = "Field `COMPARE0` reader - Write '1' to disable event routing for event COMPARE\\[0\\]"] +pub type COMPARE0_R = crate::BitReader; +#[doc = "Write '1' to disable event routing for event COMPARE\\[0\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum COMPARE0_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: COMPARE0_A) -> Self { + variant as u8 != 0 + } +} +impl COMPARE0_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> COMPARE0_A { + match self.bits { + false => COMPARE0_A::DISABLED, + true => COMPARE0_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == COMPARE0_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == COMPARE0_A::ENABLED + } +} +#[doc = "Write '1' to disable event routing for event COMPARE\\[0\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum COMPARE0_AW { + #[doc = "1: Disable"] + CLEAR = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: COMPARE0_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `COMPARE0` writer - Write '1' to disable event routing for event COMPARE\\[0\\]"] +pub type COMPARE0_W<'a, const O: u8> = crate::BitWriter<'a, u32, EVTENCLR_SPEC, COMPARE0_AW, O>; +impl<'a, const O: u8> COMPARE0_W<'a, O> { + #[doc = "Disable"] + #[inline(always)] + pub fn clear(self) -> &'a mut W { + self.variant(COMPARE0_AW::CLEAR) + } +} +#[doc = "Field `COMPARE1` reader - Write '1' to disable event routing for event COMPARE\\[1\\]"] +pub type COMPARE1_R = crate::BitReader; +#[doc = "Write '1' to disable event routing for event COMPARE\\[1\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum COMPARE1_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: COMPARE1_A) -> Self { + variant as u8 != 0 + } +} +impl COMPARE1_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> COMPARE1_A { + match self.bits { + false => COMPARE1_A::DISABLED, + true => COMPARE1_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == COMPARE1_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == COMPARE1_A::ENABLED + } +} +#[doc = "Write '1' to disable event routing for event COMPARE\\[1\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum COMPARE1_AW { + #[doc = "1: Disable"] + CLEAR = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: COMPARE1_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `COMPARE1` writer - Write '1' to disable event routing for event COMPARE\\[1\\]"] +pub type COMPARE1_W<'a, const O: u8> = crate::BitWriter<'a, u32, EVTENCLR_SPEC, COMPARE1_AW, O>; +impl<'a, const O: u8> COMPARE1_W<'a, O> { + #[doc = "Disable"] + #[inline(always)] + pub fn clear(self) -> &'a mut W { + self.variant(COMPARE1_AW::CLEAR) + } +} +#[doc = "Field `COMPARE2` reader - Write '1' to disable event routing for event COMPARE\\[2\\]"] +pub type COMPARE2_R = crate::BitReader; +#[doc = "Write '1' to disable event routing for event COMPARE\\[2\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum COMPARE2_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: COMPARE2_A) -> Self { + variant as u8 != 0 + } +} +impl COMPARE2_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> COMPARE2_A { + match self.bits { + false => COMPARE2_A::DISABLED, + true => COMPARE2_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == COMPARE2_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == COMPARE2_A::ENABLED + } +} +#[doc = "Write '1' to disable event routing for event COMPARE\\[2\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum COMPARE2_AW { + #[doc = "1: Disable"] + CLEAR = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: COMPARE2_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `COMPARE2` writer - Write '1' to disable event routing for event COMPARE\\[2\\]"] +pub type COMPARE2_W<'a, const O: u8> = crate::BitWriter<'a, u32, EVTENCLR_SPEC, COMPARE2_AW, O>; +impl<'a, const O: u8> COMPARE2_W<'a, O> { + #[doc = "Disable"] + #[inline(always)] + pub fn clear(self) -> &'a mut W { + self.variant(COMPARE2_AW::CLEAR) + } +} +#[doc = "Field `COMPARE3` reader - Write '1' to disable event routing for event COMPARE\\[3\\]"] +pub type COMPARE3_R = crate::BitReader; +#[doc = "Write '1' to disable event routing for event COMPARE\\[3\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum COMPARE3_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: COMPARE3_A) -> Self { + variant as u8 != 0 + } +} +impl COMPARE3_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> COMPARE3_A { + match self.bits { + false => COMPARE3_A::DISABLED, + true => COMPARE3_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == COMPARE3_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == COMPARE3_A::ENABLED + } +} +#[doc = "Write '1' to disable event routing for event COMPARE\\[3\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum COMPARE3_AW { + #[doc = "1: Disable"] + CLEAR = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: COMPARE3_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `COMPARE3` writer - Write '1' to disable event routing for event COMPARE\\[3\\]"] +pub type COMPARE3_W<'a, const O: u8> = crate::BitWriter<'a, u32, EVTENCLR_SPEC, COMPARE3_AW, O>; +impl<'a, const O: u8> COMPARE3_W<'a, O> { + #[doc = "Disable"] + #[inline(always)] + pub fn clear(self) -> &'a mut W { + self.variant(COMPARE3_AW::CLEAR) + } +} +impl R { + #[doc = "Bit 0 - Write '1' to disable event routing for event TICK"] + #[inline(always)] + pub fn tick(&self) -> TICK_R { + TICK_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Write '1' to disable event routing for event OVRFLW"] + #[inline(always)] + pub fn ovrflw(&self) -> OVRFLW_R { + OVRFLW_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 16 - Write '1' to disable event routing for event COMPARE\\[0\\]"] + #[inline(always)] + pub fn compare0(&self) -> COMPARE0_R { + COMPARE0_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Write '1' to disable event routing for event COMPARE\\[1\\]"] + #[inline(always)] + pub fn compare1(&self) -> COMPARE1_R { + COMPARE1_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Write '1' to disable event routing for event COMPARE\\[2\\]"] + #[inline(always)] + pub fn compare2(&self) -> COMPARE2_R { + COMPARE2_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Write '1' to disable event routing for event COMPARE\\[3\\]"] + #[inline(always)] + pub fn compare3(&self) -> COMPARE3_R { + COMPARE3_R::new(((self.bits >> 19) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Write '1' to disable event routing for event TICK"] + #[inline(always)] + pub fn tick(&mut self) -> TICK_W<0> { + TICK_W::new(self) + } + #[doc = "Bit 1 - Write '1' to disable event routing for event OVRFLW"] + #[inline(always)] + pub fn ovrflw(&mut self) -> OVRFLW_W<1> { + OVRFLW_W::new(self) + } + #[doc = "Bit 16 - Write '1' to disable event routing for event COMPARE\\[0\\]"] + #[inline(always)] + pub fn compare0(&mut self) -> COMPARE0_W<16> { + COMPARE0_W::new(self) + } + #[doc = "Bit 17 - Write '1' to disable event routing for event COMPARE\\[1\\]"] + #[inline(always)] + pub fn compare1(&mut self) -> COMPARE1_W<17> { + COMPARE1_W::new(self) + } + #[doc = "Bit 18 - Write '1' to disable event routing for event COMPARE\\[2\\]"] + #[inline(always)] + pub fn compare2(&mut self) -> COMPARE2_W<18> { + COMPARE2_W::new(self) + } + #[doc = "Bit 19 - Write '1' to disable event routing for event COMPARE\\[3\\]"] + #[inline(always)] + pub fn compare3(&mut self) -> COMPARE3_W<19> { + COMPARE3_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Disable event routing\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [evtenclr](index.html) module"] +pub struct EVTENCLR_SPEC; +impl crate::RegisterSpec for EVTENCLR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [evtenclr::R](R) reader structure"] +impl crate::Readable for EVTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [evtenclr::W](W) writer structure"] +impl crate::Writable for EVTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EVTENCLR to value 0"] +impl crate::Resettable for EVTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/rtc0_ns/evtenset.rs b/pacs/nrf9120-pac/src/rtc0_ns/evtenset.rs new file mode 100644 index 00000000..dd71c51e --- /dev/null +++ b/pacs/nrf9120-pac/src/rtc0_ns/evtenset.rs @@ -0,0 +1,468 @@ +#[doc = "Register `EVTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `TICK` reader - Write '1' to enable event routing for event TICK"] +pub type TICK_R = crate::BitReader; +#[doc = "Write '1' to enable event routing for event TICK\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum TICK_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TICK_A) -> Self { + variant as u8 != 0 + } +} +impl TICK_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> TICK_A { + match self.bits { + false => TICK_A::DISABLED, + true => TICK_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == TICK_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == TICK_A::ENABLED + } +} +#[doc = "Write '1' to enable event routing for event TICK\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum TICK_AW { + #[doc = "1: Enable"] + SET = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TICK_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TICK` writer - Write '1' to enable event routing for event TICK"] +pub type TICK_W<'a, const O: u8> = crate::BitWriter<'a, u32, EVTENSET_SPEC, TICK_AW, O>; +impl<'a, const O: u8> TICK_W<'a, O> { + #[doc = "Enable"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(TICK_AW::SET) + } +} +#[doc = "Field `OVRFLW` reader - Write '1' to enable event routing for event OVRFLW"] +pub type OVRFLW_R = crate::BitReader; +#[doc = "Write '1' to enable event routing for event OVRFLW\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum OVRFLW_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: OVRFLW_A) -> Self { + variant as u8 != 0 + } +} +impl OVRFLW_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> OVRFLW_A { + match self.bits { + false => OVRFLW_A::DISABLED, + true => OVRFLW_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == OVRFLW_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == OVRFLW_A::ENABLED + } +} +#[doc = "Write '1' to enable event routing for event OVRFLW\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum OVRFLW_AW { + #[doc = "1: Enable"] + SET = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: OVRFLW_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `OVRFLW` writer - Write '1' to enable event routing for event OVRFLW"] +pub type OVRFLW_W<'a, const O: u8> = crate::BitWriter<'a, u32, EVTENSET_SPEC, OVRFLW_AW, O>; +impl<'a, const O: u8> OVRFLW_W<'a, O> { + #[doc = "Enable"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(OVRFLW_AW::SET) + } +} +#[doc = "Field `COMPARE0` reader - Write '1' to enable event routing for event COMPARE\\[0\\]"] +pub type COMPARE0_R = crate::BitReader; +#[doc = "Write '1' to enable event routing for event COMPARE\\[0\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum COMPARE0_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: COMPARE0_A) -> Self { + variant as u8 != 0 + } +} +impl COMPARE0_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> COMPARE0_A { + match self.bits { + false => COMPARE0_A::DISABLED, + true => COMPARE0_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == COMPARE0_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == COMPARE0_A::ENABLED + } +} +#[doc = "Write '1' to enable event routing for event COMPARE\\[0\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum COMPARE0_AW { + #[doc = "1: Enable"] + SET = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: COMPARE0_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `COMPARE0` writer - Write '1' to enable event routing for event COMPARE\\[0\\]"] +pub type COMPARE0_W<'a, const O: u8> = crate::BitWriter<'a, u32, EVTENSET_SPEC, COMPARE0_AW, O>; +impl<'a, const O: u8> COMPARE0_W<'a, O> { + #[doc = "Enable"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(COMPARE0_AW::SET) + } +} +#[doc = "Field `COMPARE1` reader - Write '1' to enable event routing for event COMPARE\\[1\\]"] +pub type COMPARE1_R = crate::BitReader; +#[doc = "Write '1' to enable event routing for event COMPARE\\[1\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum COMPARE1_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: COMPARE1_A) -> Self { + variant as u8 != 0 + } +} +impl COMPARE1_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> COMPARE1_A { + match self.bits { + false => COMPARE1_A::DISABLED, + true => COMPARE1_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == COMPARE1_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == COMPARE1_A::ENABLED + } +} +#[doc = "Write '1' to enable event routing for event COMPARE\\[1\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum COMPARE1_AW { + #[doc = "1: Enable"] + SET = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: COMPARE1_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `COMPARE1` writer - Write '1' to enable event routing for event COMPARE\\[1\\]"] +pub type COMPARE1_W<'a, const O: u8> = crate::BitWriter<'a, u32, EVTENSET_SPEC, COMPARE1_AW, O>; +impl<'a, const O: u8> COMPARE1_W<'a, O> { + #[doc = "Enable"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(COMPARE1_AW::SET) + } +} +#[doc = "Field `COMPARE2` reader - Write '1' to enable event routing for event COMPARE\\[2\\]"] +pub type COMPARE2_R = crate::BitReader; +#[doc = "Write '1' to enable event routing for event COMPARE\\[2\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum COMPARE2_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: COMPARE2_A) -> Self { + variant as u8 != 0 + } +} +impl COMPARE2_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> COMPARE2_A { + match self.bits { + false => COMPARE2_A::DISABLED, + true => COMPARE2_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == COMPARE2_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == COMPARE2_A::ENABLED + } +} +#[doc = "Write '1' to enable event routing for event COMPARE\\[2\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum COMPARE2_AW { + #[doc = "1: Enable"] + SET = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: COMPARE2_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `COMPARE2` writer - Write '1' to enable event routing for event COMPARE\\[2\\]"] +pub type COMPARE2_W<'a, const O: u8> = crate::BitWriter<'a, u32, EVTENSET_SPEC, COMPARE2_AW, O>; +impl<'a, const O: u8> COMPARE2_W<'a, O> { + #[doc = "Enable"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(COMPARE2_AW::SET) + } +} +#[doc = "Field `COMPARE3` reader - Write '1' to enable event routing for event COMPARE\\[3\\]"] +pub type COMPARE3_R = crate::BitReader; +#[doc = "Write '1' to enable event routing for event COMPARE\\[3\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum COMPARE3_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: COMPARE3_A) -> Self { + variant as u8 != 0 + } +} +impl COMPARE3_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> COMPARE3_A { + match self.bits { + false => COMPARE3_A::DISABLED, + true => COMPARE3_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == COMPARE3_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == COMPARE3_A::ENABLED + } +} +#[doc = "Write '1' to enable event routing for event COMPARE\\[3\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum COMPARE3_AW { + #[doc = "1: Enable"] + SET = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: COMPARE3_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `COMPARE3` writer - Write '1' to enable event routing for event COMPARE\\[3\\]"] +pub type COMPARE3_W<'a, const O: u8> = crate::BitWriter<'a, u32, EVTENSET_SPEC, COMPARE3_AW, O>; +impl<'a, const O: u8> COMPARE3_W<'a, O> { + #[doc = "Enable"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(COMPARE3_AW::SET) + } +} +impl R { + #[doc = "Bit 0 - Write '1' to enable event routing for event TICK"] + #[inline(always)] + pub fn tick(&self) -> TICK_R { + TICK_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Write '1' to enable event routing for event OVRFLW"] + #[inline(always)] + pub fn ovrflw(&self) -> OVRFLW_R { + OVRFLW_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 16 - Write '1' to enable event routing for event COMPARE\\[0\\]"] + #[inline(always)] + pub fn compare0(&self) -> COMPARE0_R { + COMPARE0_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Write '1' to enable event routing for event COMPARE\\[1\\]"] + #[inline(always)] + pub fn compare1(&self) -> COMPARE1_R { + COMPARE1_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Write '1' to enable event routing for event COMPARE\\[2\\]"] + #[inline(always)] + pub fn compare2(&self) -> COMPARE2_R { + COMPARE2_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Write '1' to enable event routing for event COMPARE\\[3\\]"] + #[inline(always)] + pub fn compare3(&self) -> COMPARE3_R { + COMPARE3_R::new(((self.bits >> 19) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Write '1' to enable event routing for event TICK"] + #[inline(always)] + pub fn tick(&mut self) -> TICK_W<0> { + TICK_W::new(self) + } + #[doc = "Bit 1 - Write '1' to enable event routing for event OVRFLW"] + #[inline(always)] + pub fn ovrflw(&mut self) -> OVRFLW_W<1> { + OVRFLW_W::new(self) + } + #[doc = "Bit 16 - Write '1' to enable event routing for event COMPARE\\[0\\]"] + #[inline(always)] + pub fn compare0(&mut self) -> COMPARE0_W<16> { + COMPARE0_W::new(self) + } + #[doc = "Bit 17 - Write '1' to enable event routing for event COMPARE\\[1\\]"] + #[inline(always)] + pub fn compare1(&mut self) -> COMPARE1_W<17> { + COMPARE1_W::new(self) + } + #[doc = "Bit 18 - Write '1' to enable event routing for event COMPARE\\[2\\]"] + #[inline(always)] + pub fn compare2(&mut self) -> COMPARE2_W<18> { + COMPARE2_W::new(self) + } + #[doc = "Bit 19 - Write '1' to enable event routing for event COMPARE\\[3\\]"] + #[inline(always)] + pub fn compare3(&mut self) -> COMPARE3_W<19> { + COMPARE3_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Enable event routing\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [evtenset](index.html) module"] +pub struct EVTENSET_SPEC; +impl crate::RegisterSpec for EVTENSET_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [evtenset::R](R) reader structure"] +impl crate::Readable for EVTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [evtenset::W](W) writer structure"] +impl crate::Writable for EVTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EVTENSET to value 0"] +impl crate::Resettable for EVTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/rtc0_ns/intenclr.rs b/pacs/nrf9120-pac/src/rtc0_ns/intenclr.rs new file mode 100644 index 00000000..429d0d0f --- /dev/null +++ b/pacs/nrf9120-pac/src/rtc0_ns/intenclr.rs @@ -0,0 +1,468 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `TICK` reader - Write '1' to disable interrupt for event TICK"] +pub type TICK_R = crate::BitReader; +#[doc = "Write '1' to disable interrupt for event TICK\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum TICK_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TICK_A) -> Self { + variant as u8 != 0 + } +} +impl TICK_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> TICK_A { + match self.bits { + false => TICK_A::DISABLED, + true => TICK_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == TICK_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == TICK_A::ENABLED + } +} +#[doc = "Write '1' to disable interrupt for event TICK\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum TICK_AW { + #[doc = "1: Disable"] + CLEAR = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TICK_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TICK` writer - Write '1' to disable interrupt for event TICK"] +pub type TICK_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENCLR_SPEC, TICK_AW, O>; +impl<'a, const O: u8> TICK_W<'a, O> { + #[doc = "Disable"] + #[inline(always)] + pub fn clear(self) -> &'a mut W { + self.variant(TICK_AW::CLEAR) + } +} +#[doc = "Field `OVRFLW` reader - Write '1' to disable interrupt for event OVRFLW"] +pub type OVRFLW_R = crate::BitReader; +#[doc = "Write '1' to disable interrupt for event OVRFLW\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum OVRFLW_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: OVRFLW_A) -> Self { + variant as u8 != 0 + } +} +impl OVRFLW_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> OVRFLW_A { + match self.bits { + false => OVRFLW_A::DISABLED, + true => OVRFLW_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == OVRFLW_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == OVRFLW_A::ENABLED + } +} +#[doc = "Write '1' to disable interrupt for event OVRFLW\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum OVRFLW_AW { + #[doc = "1: Disable"] + CLEAR = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: OVRFLW_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `OVRFLW` writer - Write '1' to disable interrupt for event OVRFLW"] +pub type OVRFLW_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENCLR_SPEC, OVRFLW_AW, O>; +impl<'a, const O: u8> OVRFLW_W<'a, O> { + #[doc = "Disable"] + #[inline(always)] + pub fn clear(self) -> &'a mut W { + self.variant(OVRFLW_AW::CLEAR) + } +} +#[doc = "Field `COMPARE0` reader - Write '1' to disable interrupt for event COMPARE\\[0\\]"] +pub type COMPARE0_R = crate::BitReader; +#[doc = "Write '1' to disable interrupt for event COMPARE\\[0\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum COMPARE0_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: COMPARE0_A) -> Self { + variant as u8 != 0 + } +} +impl COMPARE0_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> COMPARE0_A { + match self.bits { + false => COMPARE0_A::DISABLED, + true => COMPARE0_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == COMPARE0_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == COMPARE0_A::ENABLED + } +} +#[doc = "Write '1' to disable interrupt for event COMPARE\\[0\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum COMPARE0_AW { + #[doc = "1: Disable"] + CLEAR = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: COMPARE0_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `COMPARE0` writer - Write '1' to disable interrupt for event COMPARE\\[0\\]"] +pub type COMPARE0_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENCLR_SPEC, COMPARE0_AW, O>; +impl<'a, const O: u8> COMPARE0_W<'a, O> { + #[doc = "Disable"] + #[inline(always)] + pub fn clear(self) -> &'a mut W { + self.variant(COMPARE0_AW::CLEAR) + } +} +#[doc = "Field `COMPARE1` reader - Write '1' to disable interrupt for event COMPARE\\[1\\]"] +pub type COMPARE1_R = crate::BitReader; +#[doc = "Write '1' to disable interrupt for event COMPARE\\[1\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum COMPARE1_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: COMPARE1_A) -> Self { + variant as u8 != 0 + } +} +impl COMPARE1_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> COMPARE1_A { + match self.bits { + false => COMPARE1_A::DISABLED, + true => COMPARE1_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == COMPARE1_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == COMPARE1_A::ENABLED + } +} +#[doc = "Write '1' to disable interrupt for event COMPARE\\[1\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum COMPARE1_AW { + #[doc = "1: Disable"] + CLEAR = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: COMPARE1_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `COMPARE1` writer - Write '1' to disable interrupt for event COMPARE\\[1\\]"] +pub type COMPARE1_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENCLR_SPEC, COMPARE1_AW, O>; +impl<'a, const O: u8> COMPARE1_W<'a, O> { + #[doc = "Disable"] + #[inline(always)] + pub fn clear(self) -> &'a mut W { + self.variant(COMPARE1_AW::CLEAR) + } +} +#[doc = "Field `COMPARE2` reader - Write '1' to disable interrupt for event COMPARE\\[2\\]"] +pub type COMPARE2_R = crate::BitReader; +#[doc = "Write '1' to disable interrupt for event COMPARE\\[2\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum COMPARE2_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: COMPARE2_A) -> Self { + variant as u8 != 0 + } +} +impl COMPARE2_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> COMPARE2_A { + match self.bits { + false => COMPARE2_A::DISABLED, + true => COMPARE2_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == COMPARE2_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == COMPARE2_A::ENABLED + } +} +#[doc = "Write '1' to disable interrupt for event COMPARE\\[2\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum COMPARE2_AW { + #[doc = "1: Disable"] + CLEAR = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: COMPARE2_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `COMPARE2` writer - Write '1' to disable interrupt for event COMPARE\\[2\\]"] +pub type COMPARE2_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENCLR_SPEC, COMPARE2_AW, O>; +impl<'a, const O: u8> COMPARE2_W<'a, O> { + #[doc = "Disable"] + #[inline(always)] + pub fn clear(self) -> &'a mut W { + self.variant(COMPARE2_AW::CLEAR) + } +} +#[doc = "Field `COMPARE3` reader - Write '1' to disable interrupt for event COMPARE\\[3\\]"] +pub type COMPARE3_R = crate::BitReader; +#[doc = "Write '1' to disable interrupt for event COMPARE\\[3\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum COMPARE3_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: COMPARE3_A) -> Self { + variant as u8 != 0 + } +} +impl COMPARE3_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> COMPARE3_A { + match self.bits { + false => COMPARE3_A::DISABLED, + true => COMPARE3_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == COMPARE3_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == COMPARE3_A::ENABLED + } +} +#[doc = "Write '1' to disable interrupt for event COMPARE\\[3\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum COMPARE3_AW { + #[doc = "1: Disable"] + CLEAR = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: COMPARE3_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `COMPARE3` writer - Write '1' to disable interrupt for event COMPARE\\[3\\]"] +pub type COMPARE3_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENCLR_SPEC, COMPARE3_AW, O>; +impl<'a, const O: u8> COMPARE3_W<'a, O> { + #[doc = "Disable"] + #[inline(always)] + pub fn clear(self) -> &'a mut W { + self.variant(COMPARE3_AW::CLEAR) + } +} +impl R { + #[doc = "Bit 0 - Write '1' to disable interrupt for event TICK"] + #[inline(always)] + pub fn tick(&self) -> TICK_R { + TICK_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Write '1' to disable interrupt for event OVRFLW"] + #[inline(always)] + pub fn ovrflw(&self) -> OVRFLW_R { + OVRFLW_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 16 - Write '1' to disable interrupt for event COMPARE\\[0\\]"] + #[inline(always)] + pub fn compare0(&self) -> COMPARE0_R { + COMPARE0_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Write '1' to disable interrupt for event COMPARE\\[1\\]"] + #[inline(always)] + pub fn compare1(&self) -> COMPARE1_R { + COMPARE1_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Write '1' to disable interrupt for event COMPARE\\[2\\]"] + #[inline(always)] + pub fn compare2(&self) -> COMPARE2_R { + COMPARE2_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Write '1' to disable interrupt for event COMPARE\\[3\\]"] + #[inline(always)] + pub fn compare3(&self) -> COMPARE3_R { + COMPARE3_R::new(((self.bits >> 19) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Write '1' to disable interrupt for event TICK"] + #[inline(always)] + pub fn tick(&mut self) -> TICK_W<0> { + TICK_W::new(self) + } + #[doc = "Bit 1 - Write '1' to disable interrupt for event OVRFLW"] + #[inline(always)] + pub fn ovrflw(&mut self) -> OVRFLW_W<1> { + OVRFLW_W::new(self) + } + #[doc = "Bit 16 - Write '1' to disable interrupt for event COMPARE\\[0\\]"] + #[inline(always)] + pub fn compare0(&mut self) -> COMPARE0_W<16> { + COMPARE0_W::new(self) + } + #[doc = "Bit 17 - Write '1' to disable interrupt for event COMPARE\\[1\\]"] + #[inline(always)] + pub fn compare1(&mut self) -> COMPARE1_W<17> { + COMPARE1_W::new(self) + } + #[doc = "Bit 18 - Write '1' to disable interrupt for event COMPARE\\[2\\]"] + #[inline(always)] + pub fn compare2(&mut self) -> COMPARE2_W<18> { + COMPARE2_W::new(self) + } + #[doc = "Bit 19 - Write '1' to disable interrupt for event COMPARE\\[3\\]"] + #[inline(always)] + pub fn compare3(&mut self) -> COMPARE3_W<19> { + COMPARE3_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Disable interrupt\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/rtc0_ns/intenset.rs b/pacs/nrf9120-pac/src/rtc0_ns/intenset.rs new file mode 100644 index 00000000..2a5a7c42 --- /dev/null +++ b/pacs/nrf9120-pac/src/rtc0_ns/intenset.rs @@ -0,0 +1,468 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `TICK` reader - Write '1' to enable interrupt for event TICK"] +pub type TICK_R = crate::BitReader; +#[doc = "Write '1' to enable interrupt for event TICK\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum TICK_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TICK_A) -> Self { + variant as u8 != 0 + } +} +impl TICK_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> TICK_A { + match self.bits { + false => TICK_A::DISABLED, + true => TICK_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == TICK_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == TICK_A::ENABLED + } +} +#[doc = "Write '1' to enable interrupt for event TICK\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum TICK_AW { + #[doc = "1: Enable"] + SET = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TICK_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TICK` writer - Write '1' to enable interrupt for event TICK"] +pub type TICK_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENSET_SPEC, TICK_AW, O>; +impl<'a, const O: u8> TICK_W<'a, O> { + #[doc = "Enable"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(TICK_AW::SET) + } +} +#[doc = "Field `OVRFLW` reader - Write '1' to enable interrupt for event OVRFLW"] +pub type OVRFLW_R = crate::BitReader; +#[doc = "Write '1' to enable interrupt for event OVRFLW\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum OVRFLW_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: OVRFLW_A) -> Self { + variant as u8 != 0 + } +} +impl OVRFLW_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> OVRFLW_A { + match self.bits { + false => OVRFLW_A::DISABLED, + true => OVRFLW_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == OVRFLW_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == OVRFLW_A::ENABLED + } +} +#[doc = "Write '1' to enable interrupt for event OVRFLW\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum OVRFLW_AW { + #[doc = "1: Enable"] + SET = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: OVRFLW_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `OVRFLW` writer - Write '1' to enable interrupt for event OVRFLW"] +pub type OVRFLW_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENSET_SPEC, OVRFLW_AW, O>; +impl<'a, const O: u8> OVRFLW_W<'a, O> { + #[doc = "Enable"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(OVRFLW_AW::SET) + } +} +#[doc = "Field `COMPARE0` reader - Write '1' to enable interrupt for event COMPARE\\[0\\]"] +pub type COMPARE0_R = crate::BitReader; +#[doc = "Write '1' to enable interrupt for event COMPARE\\[0\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum COMPARE0_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: COMPARE0_A) -> Self { + variant as u8 != 0 + } +} +impl COMPARE0_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> COMPARE0_A { + match self.bits { + false => COMPARE0_A::DISABLED, + true => COMPARE0_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == COMPARE0_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == COMPARE0_A::ENABLED + } +} +#[doc = "Write '1' to enable interrupt for event COMPARE\\[0\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum COMPARE0_AW { + #[doc = "1: Enable"] + SET = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: COMPARE0_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `COMPARE0` writer - Write '1' to enable interrupt for event COMPARE\\[0\\]"] +pub type COMPARE0_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENSET_SPEC, COMPARE0_AW, O>; +impl<'a, const O: u8> COMPARE0_W<'a, O> { + #[doc = "Enable"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(COMPARE0_AW::SET) + } +} +#[doc = "Field `COMPARE1` reader - Write '1' to enable interrupt for event COMPARE\\[1\\]"] +pub type COMPARE1_R = crate::BitReader; +#[doc = "Write '1' to enable interrupt for event COMPARE\\[1\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum COMPARE1_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: COMPARE1_A) -> Self { + variant as u8 != 0 + } +} +impl COMPARE1_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> COMPARE1_A { + match self.bits { + false => COMPARE1_A::DISABLED, + true => COMPARE1_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == COMPARE1_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == COMPARE1_A::ENABLED + } +} +#[doc = "Write '1' to enable interrupt for event COMPARE\\[1\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum COMPARE1_AW { + #[doc = "1: Enable"] + SET = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: COMPARE1_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `COMPARE1` writer - Write '1' to enable interrupt for event COMPARE\\[1\\]"] +pub type COMPARE1_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENSET_SPEC, COMPARE1_AW, O>; +impl<'a, const O: u8> COMPARE1_W<'a, O> { + #[doc = "Enable"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(COMPARE1_AW::SET) + } +} +#[doc = "Field `COMPARE2` reader - Write '1' to enable interrupt for event COMPARE\\[2\\]"] +pub type COMPARE2_R = crate::BitReader; +#[doc = "Write '1' to enable interrupt for event COMPARE\\[2\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum COMPARE2_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: COMPARE2_A) -> Self { + variant as u8 != 0 + } +} +impl COMPARE2_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> COMPARE2_A { + match self.bits { + false => COMPARE2_A::DISABLED, + true => COMPARE2_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == COMPARE2_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == COMPARE2_A::ENABLED + } +} +#[doc = "Write '1' to enable interrupt for event COMPARE\\[2\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum COMPARE2_AW { + #[doc = "1: Enable"] + SET = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: COMPARE2_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `COMPARE2` writer - Write '1' to enable interrupt for event COMPARE\\[2\\]"] +pub type COMPARE2_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENSET_SPEC, COMPARE2_AW, O>; +impl<'a, const O: u8> COMPARE2_W<'a, O> { + #[doc = "Enable"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(COMPARE2_AW::SET) + } +} +#[doc = "Field `COMPARE3` reader - Write '1' to enable interrupt for event COMPARE\\[3\\]"] +pub type COMPARE3_R = crate::BitReader; +#[doc = "Write '1' to enable interrupt for event COMPARE\\[3\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum COMPARE3_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: COMPARE3_A) -> Self { + variant as u8 != 0 + } +} +impl COMPARE3_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> COMPARE3_A { + match self.bits { + false => COMPARE3_A::DISABLED, + true => COMPARE3_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == COMPARE3_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == COMPARE3_A::ENABLED + } +} +#[doc = "Write '1' to enable interrupt for event COMPARE\\[3\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum COMPARE3_AW { + #[doc = "1: Enable"] + SET = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: COMPARE3_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `COMPARE3` writer - Write '1' to enable interrupt for event COMPARE\\[3\\]"] +pub type COMPARE3_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENSET_SPEC, COMPARE3_AW, O>; +impl<'a, const O: u8> COMPARE3_W<'a, O> { + #[doc = "Enable"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(COMPARE3_AW::SET) + } +} +impl R { + #[doc = "Bit 0 - Write '1' to enable interrupt for event TICK"] + #[inline(always)] + pub fn tick(&self) -> TICK_R { + TICK_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Write '1' to enable interrupt for event OVRFLW"] + #[inline(always)] + pub fn ovrflw(&self) -> OVRFLW_R { + OVRFLW_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 16 - Write '1' to enable interrupt for event COMPARE\\[0\\]"] + #[inline(always)] + pub fn compare0(&self) -> COMPARE0_R { + COMPARE0_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Write '1' to enable interrupt for event COMPARE\\[1\\]"] + #[inline(always)] + pub fn compare1(&self) -> COMPARE1_R { + COMPARE1_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Write '1' to enable interrupt for event COMPARE\\[2\\]"] + #[inline(always)] + pub fn compare2(&self) -> COMPARE2_R { + COMPARE2_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Write '1' to enable interrupt for event COMPARE\\[3\\]"] + #[inline(always)] + pub fn compare3(&self) -> COMPARE3_R { + COMPARE3_R::new(((self.bits >> 19) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Write '1' to enable interrupt for event TICK"] + #[inline(always)] + pub fn tick(&mut self) -> TICK_W<0> { + TICK_W::new(self) + } + #[doc = "Bit 1 - Write '1' to enable interrupt for event OVRFLW"] + #[inline(always)] + pub fn ovrflw(&mut self) -> OVRFLW_W<1> { + OVRFLW_W::new(self) + } + #[doc = "Bit 16 - Write '1' to enable interrupt for event COMPARE\\[0\\]"] + #[inline(always)] + pub fn compare0(&mut self) -> COMPARE0_W<16> { + COMPARE0_W::new(self) + } + #[doc = "Bit 17 - Write '1' to enable interrupt for event COMPARE\\[1\\]"] + #[inline(always)] + pub fn compare1(&mut self) -> COMPARE1_W<17> { + COMPARE1_W::new(self) + } + #[doc = "Bit 18 - Write '1' to enable interrupt for event COMPARE\\[2\\]"] + #[inline(always)] + pub fn compare2(&mut self) -> COMPARE2_W<18> { + COMPARE2_W::new(self) + } + #[doc = "Bit 19 - Write '1' to enable interrupt for event COMPARE\\[3\\]"] + #[inline(always)] + pub fn compare3(&mut self) -> COMPARE3_W<19> { + COMPARE3_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Enable interrupt\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/rtc0_ns/prescaler.rs b/pacs/nrf9120-pac/src/rtc0_ns/prescaler.rs new file mode 100644 index 00000000..05f9d924 --- /dev/null +++ b/pacs/nrf9120-pac/src/rtc0_ns/prescaler.rs @@ -0,0 +1,81 @@ +#[doc = "Register `PRESCALER` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PRESCALER` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PRESCALER` reader - Prescaler value"] +pub type PRESCALER_R = crate::FieldReader; +#[doc = "Field `PRESCALER` writer - Prescaler value"] +pub type PRESCALER_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, PRESCALER_SPEC, u16, u16, 12, O>; +impl R { + #[doc = "Bits 0:11 - Prescaler value"] + #[inline(always)] + pub fn prescaler(&self) -> PRESCALER_R { + PRESCALER_R::new((self.bits & 0x0fff) as u16) + } +} +impl W { + #[doc = "Bits 0:11 - Prescaler value"] + #[inline(always)] + pub fn prescaler(&mut self) -> PRESCALER_W<0> { + PRESCALER_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "12-bit prescaler for counter frequency (32768/(PRESCALER+1)). Must be written when RTC is stopped.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [prescaler](index.html) module"] +pub struct PRESCALER_SPEC; +impl crate::RegisterSpec for PRESCALER_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [prescaler::R](R) reader structure"] +impl crate::Readable for PRESCALER_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [prescaler::W](W) writer structure"] +impl crate::Writable for PRESCALER_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PRESCALER to value 0"] +impl crate::Resettable for PRESCALER_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/rtc0_ns/publish_compare.rs b/pacs/nrf9120-pac/src/rtc0_ns/publish_compare.rs new file mode 100644 index 00000000..0de6a146 --- /dev/null +++ b/pacs/nrf9120-pac/src/rtc0_ns/publish_compare.rs @@ -0,0 +1,145 @@ +#[doc = "Register `PUBLISH_COMPARE[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PUBLISH_COMPARE[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CHIDX` reader - DPPI channel that event COMPARE\\[n\\] +will publish to"] +pub type CHIDX_R = crate::FieldReader; +#[doc = "Field `CHIDX` writer - DPPI channel that event COMPARE\\[n\\] +will publish to"] +pub type CHIDX_W<'a, const O: u8> = crate::FieldWriter<'a, u32, PUBLISH_COMPARE_SPEC, u8, u8, 8, O>; +#[doc = "Field `EN` reader - "] +pub type EN_R = crate::BitReader; +#[doc = "\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum EN_A { + #[doc = "0: Disable publishing"] + DISABLED = 0, + #[doc = "1: Enable publishing"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: EN_A) -> Self { + variant as u8 != 0 + } +} +impl EN_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EN_A { + match self.bits { + false => EN_A::DISABLED, + true => EN_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == EN_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == EN_A::ENABLED + } +} +#[doc = "Field `EN` writer - "] +pub type EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, PUBLISH_COMPARE_SPEC, EN_A, O>; +impl<'a, const O: u8> EN_W<'a, O> { + #[doc = "Disable publishing"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(EN_A::DISABLED) + } + #[doc = "Enable publishing"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(EN_A::ENABLED) + } +} +impl R { + #[doc = "Bits 0:7 - DPPI channel that event COMPARE\\[n\\] +will publish to"] + #[inline(always)] + pub fn chidx(&self) -> CHIDX_R { + CHIDX_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&self) -> EN_R { + EN_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:7 - DPPI channel that event COMPARE\\[n\\] +will publish to"] + #[inline(always)] + pub fn chidx(&mut self) -> CHIDX_W<0> { + CHIDX_W::new(self) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&mut self) -> EN_W<31> { + EN_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Description collection: Publish configuration for event COMPARE\\[n\\]\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [publish_compare](index.html) module"] +pub struct PUBLISH_COMPARE_SPEC; +impl crate::RegisterSpec for PUBLISH_COMPARE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [publish_compare::R](R) reader structure"] +impl crate::Readable for PUBLISH_COMPARE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [publish_compare::W](W) writer structure"] +impl crate::Writable for PUBLISH_COMPARE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PUBLISH_COMPARE[%s] +to value 0"] +impl crate::Resettable for PUBLISH_COMPARE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/rtc0_ns/publish_ovrflw.rs b/pacs/nrf9120-pac/src/rtc0_ns/publish_ovrflw.rs new file mode 100644 index 00000000..97ae4db1 --- /dev/null +++ b/pacs/nrf9120-pac/src/rtc0_ns/publish_ovrflw.rs @@ -0,0 +1,140 @@ +#[doc = "Register `PUBLISH_OVRFLW` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PUBLISH_OVRFLW` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CHIDX` reader - DPPI channel that event OVRFLW will publish to"] +pub type CHIDX_R = crate::FieldReader; +#[doc = "Field `CHIDX` writer - DPPI channel that event OVRFLW will publish to"] +pub type CHIDX_W<'a, const O: u8> = crate::FieldWriter<'a, u32, PUBLISH_OVRFLW_SPEC, u8, u8, 8, O>; +#[doc = "Field `EN` reader - "] +pub type EN_R = crate::BitReader; +#[doc = "\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum EN_A { + #[doc = "0: Disable publishing"] + DISABLED = 0, + #[doc = "1: Enable publishing"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: EN_A) -> Self { + variant as u8 != 0 + } +} +impl EN_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EN_A { + match self.bits { + false => EN_A::DISABLED, + true => EN_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == EN_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == EN_A::ENABLED + } +} +#[doc = "Field `EN` writer - "] +pub type EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, PUBLISH_OVRFLW_SPEC, EN_A, O>; +impl<'a, const O: u8> EN_W<'a, O> { + #[doc = "Disable publishing"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(EN_A::DISABLED) + } + #[doc = "Enable publishing"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(EN_A::ENABLED) + } +} +impl R { + #[doc = "Bits 0:7 - DPPI channel that event OVRFLW will publish to"] + #[inline(always)] + pub fn chidx(&self) -> CHIDX_R { + CHIDX_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&self) -> EN_R { + EN_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:7 - DPPI channel that event OVRFLW will publish to"] + #[inline(always)] + pub fn chidx(&mut self) -> CHIDX_W<0> { + CHIDX_W::new(self) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&mut self) -> EN_W<31> { + EN_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Publish configuration for event OVRFLW\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [publish_ovrflw](index.html) module"] +pub struct PUBLISH_OVRFLW_SPEC; +impl crate::RegisterSpec for PUBLISH_OVRFLW_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [publish_ovrflw::R](R) reader structure"] +impl crate::Readable for PUBLISH_OVRFLW_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [publish_ovrflw::W](W) writer structure"] +impl crate::Writable for PUBLISH_OVRFLW_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PUBLISH_OVRFLW to value 0"] +impl crate::Resettable for PUBLISH_OVRFLW_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/rtc0_ns/publish_tick.rs b/pacs/nrf9120-pac/src/rtc0_ns/publish_tick.rs new file mode 100644 index 00000000..2dbefbba --- /dev/null +++ b/pacs/nrf9120-pac/src/rtc0_ns/publish_tick.rs @@ -0,0 +1,140 @@ +#[doc = "Register `PUBLISH_TICK` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PUBLISH_TICK` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CHIDX` reader - DPPI channel that event TICK will publish to"] +pub type CHIDX_R = crate::FieldReader; +#[doc = "Field `CHIDX` writer - DPPI channel that event TICK will publish to"] +pub type CHIDX_W<'a, const O: u8> = crate::FieldWriter<'a, u32, PUBLISH_TICK_SPEC, u8, u8, 8, O>; +#[doc = "Field `EN` reader - "] +pub type EN_R = crate::BitReader; +#[doc = "\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum EN_A { + #[doc = "0: Disable publishing"] + DISABLED = 0, + #[doc = "1: Enable publishing"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: EN_A) -> Self { + variant as u8 != 0 + } +} +impl EN_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EN_A { + match self.bits { + false => EN_A::DISABLED, + true => EN_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == EN_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == EN_A::ENABLED + } +} +#[doc = "Field `EN` writer - "] +pub type EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, PUBLISH_TICK_SPEC, EN_A, O>; +impl<'a, const O: u8> EN_W<'a, O> { + #[doc = "Disable publishing"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(EN_A::DISABLED) + } + #[doc = "Enable publishing"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(EN_A::ENABLED) + } +} +impl R { + #[doc = "Bits 0:7 - DPPI channel that event TICK will publish to"] + #[inline(always)] + pub fn chidx(&self) -> CHIDX_R { + CHIDX_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&self) -> EN_R { + EN_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:7 - DPPI channel that event TICK will publish to"] + #[inline(always)] + pub fn chidx(&mut self) -> CHIDX_W<0> { + CHIDX_W::new(self) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&mut self) -> EN_W<31> { + EN_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Publish configuration for event TICK\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [publish_tick](index.html) module"] +pub struct PUBLISH_TICK_SPEC; +impl crate::RegisterSpec for PUBLISH_TICK_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [publish_tick::R](R) reader structure"] +impl crate::Readable for PUBLISH_TICK_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [publish_tick::W](W) writer structure"] +impl crate::Writable for PUBLISH_TICK_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PUBLISH_TICK to value 0"] +impl crate::Resettable for PUBLISH_TICK_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/rtc0_ns/subscribe_clear.rs b/pacs/nrf9120-pac/src/rtc0_ns/subscribe_clear.rs new file mode 100644 index 00000000..0930663f --- /dev/null +++ b/pacs/nrf9120-pac/src/rtc0_ns/subscribe_clear.rs @@ -0,0 +1,140 @@ +#[doc = "Register `SUBSCRIBE_CLEAR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SUBSCRIBE_CLEAR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CHIDX` reader - DPPI channel that task CLEAR will subscribe to"] +pub type CHIDX_R = crate::FieldReader; +#[doc = "Field `CHIDX` writer - DPPI channel that task CLEAR will subscribe to"] +pub type CHIDX_W<'a, const O: u8> = crate::FieldWriter<'a, u32, SUBSCRIBE_CLEAR_SPEC, u8, u8, 8, O>; +#[doc = "Field `EN` reader - "] +pub type EN_R = crate::BitReader; +#[doc = "\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum EN_A { + #[doc = "0: Disable subscription"] + DISABLED = 0, + #[doc = "1: Enable subscription"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: EN_A) -> Self { + variant as u8 != 0 + } +} +impl EN_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EN_A { + match self.bits { + false => EN_A::DISABLED, + true => EN_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == EN_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == EN_A::ENABLED + } +} +#[doc = "Field `EN` writer - "] +pub type EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, SUBSCRIBE_CLEAR_SPEC, EN_A, O>; +impl<'a, const O: u8> EN_W<'a, O> { + #[doc = "Disable subscription"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(EN_A::DISABLED) + } + #[doc = "Enable subscription"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(EN_A::ENABLED) + } +} +impl R { + #[doc = "Bits 0:7 - DPPI channel that task CLEAR will subscribe to"] + #[inline(always)] + pub fn chidx(&self) -> CHIDX_R { + CHIDX_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&self) -> EN_R { + EN_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:7 - DPPI channel that task CLEAR will subscribe to"] + #[inline(always)] + pub fn chidx(&mut self) -> CHIDX_W<0> { + CHIDX_W::new(self) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&mut self) -> EN_W<31> { + EN_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Subscribe configuration for task CLEAR\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [subscribe_clear](index.html) module"] +pub struct SUBSCRIBE_CLEAR_SPEC; +impl crate::RegisterSpec for SUBSCRIBE_CLEAR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [subscribe_clear::R](R) reader structure"] +impl crate::Readable for SUBSCRIBE_CLEAR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [subscribe_clear::W](W) writer structure"] +impl crate::Writable for SUBSCRIBE_CLEAR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SUBSCRIBE_CLEAR to value 0"] +impl crate::Resettable for SUBSCRIBE_CLEAR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/rtc0_ns/subscribe_start.rs b/pacs/nrf9120-pac/src/rtc0_ns/subscribe_start.rs new file mode 100644 index 00000000..fb9deced --- /dev/null +++ b/pacs/nrf9120-pac/src/rtc0_ns/subscribe_start.rs @@ -0,0 +1,140 @@ +#[doc = "Register `SUBSCRIBE_START` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SUBSCRIBE_START` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CHIDX` reader - DPPI channel that task START will subscribe to"] +pub type CHIDX_R = crate::FieldReader; +#[doc = "Field `CHIDX` writer - DPPI channel that task START will subscribe to"] +pub type CHIDX_W<'a, const O: u8> = crate::FieldWriter<'a, u32, SUBSCRIBE_START_SPEC, u8, u8, 8, O>; +#[doc = "Field `EN` reader - "] +pub type EN_R = crate::BitReader; +#[doc = "\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum EN_A { + #[doc = "0: Disable subscription"] + DISABLED = 0, + #[doc = "1: Enable subscription"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: EN_A) -> Self { + variant as u8 != 0 + } +} +impl EN_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EN_A { + match self.bits { + false => EN_A::DISABLED, + true => EN_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == EN_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == EN_A::ENABLED + } +} +#[doc = "Field `EN` writer - "] +pub type EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, SUBSCRIBE_START_SPEC, EN_A, O>; +impl<'a, const O: u8> EN_W<'a, O> { + #[doc = "Disable subscription"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(EN_A::DISABLED) + } + #[doc = "Enable subscription"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(EN_A::ENABLED) + } +} +impl R { + #[doc = "Bits 0:7 - DPPI channel that task START will subscribe to"] + #[inline(always)] + pub fn chidx(&self) -> CHIDX_R { + CHIDX_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&self) -> EN_R { + EN_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:7 - DPPI channel that task START will subscribe to"] + #[inline(always)] + pub fn chidx(&mut self) -> CHIDX_W<0> { + CHIDX_W::new(self) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&mut self) -> EN_W<31> { + EN_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Subscribe configuration for task START\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [subscribe_start](index.html) module"] +pub struct SUBSCRIBE_START_SPEC; +impl crate::RegisterSpec for SUBSCRIBE_START_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [subscribe_start::R](R) reader structure"] +impl crate::Readable for SUBSCRIBE_START_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [subscribe_start::W](W) writer structure"] +impl crate::Writable for SUBSCRIBE_START_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SUBSCRIBE_START to value 0"] +impl crate::Resettable for SUBSCRIBE_START_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/rtc0_ns/subscribe_stop.rs b/pacs/nrf9120-pac/src/rtc0_ns/subscribe_stop.rs new file mode 100644 index 00000000..2fe3af58 --- /dev/null +++ b/pacs/nrf9120-pac/src/rtc0_ns/subscribe_stop.rs @@ -0,0 +1,140 @@ +#[doc = "Register `SUBSCRIBE_STOP` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SUBSCRIBE_STOP` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CHIDX` reader - DPPI channel that task STOP will subscribe to"] +pub type CHIDX_R = crate::FieldReader; +#[doc = "Field `CHIDX` writer - DPPI channel that task STOP will subscribe to"] +pub type CHIDX_W<'a, const O: u8> = crate::FieldWriter<'a, u32, SUBSCRIBE_STOP_SPEC, u8, u8, 8, O>; +#[doc = "Field `EN` reader - "] +pub type EN_R = crate::BitReader; +#[doc = "\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum EN_A { + #[doc = "0: Disable subscription"] + DISABLED = 0, + #[doc = "1: Enable subscription"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: EN_A) -> Self { + variant as u8 != 0 + } +} +impl EN_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EN_A { + match self.bits { + false => EN_A::DISABLED, + true => EN_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == EN_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == EN_A::ENABLED + } +} +#[doc = "Field `EN` writer - "] +pub type EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, SUBSCRIBE_STOP_SPEC, EN_A, O>; +impl<'a, const O: u8> EN_W<'a, O> { + #[doc = "Disable subscription"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(EN_A::DISABLED) + } + #[doc = "Enable subscription"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(EN_A::ENABLED) + } +} +impl R { + #[doc = "Bits 0:7 - DPPI channel that task STOP will subscribe to"] + #[inline(always)] + pub fn chidx(&self) -> CHIDX_R { + CHIDX_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&self) -> EN_R { + EN_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:7 - DPPI channel that task STOP will subscribe to"] + #[inline(always)] + pub fn chidx(&mut self) -> CHIDX_W<0> { + CHIDX_W::new(self) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&mut self) -> EN_W<31> { + EN_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Subscribe configuration for task STOP\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [subscribe_stop](index.html) module"] +pub struct SUBSCRIBE_STOP_SPEC; +impl crate::RegisterSpec for SUBSCRIBE_STOP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [subscribe_stop::R](R) reader structure"] +impl crate::Readable for SUBSCRIBE_STOP_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [subscribe_stop::W](W) writer structure"] +impl crate::Writable for SUBSCRIBE_STOP_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SUBSCRIBE_STOP to value 0"] +impl crate::Resettable for SUBSCRIBE_STOP_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/rtc0_ns/subscribe_trigovrflw.rs b/pacs/nrf9120-pac/src/rtc0_ns/subscribe_trigovrflw.rs new file mode 100644 index 00000000..6f56ea09 --- /dev/null +++ b/pacs/nrf9120-pac/src/rtc0_ns/subscribe_trigovrflw.rs @@ -0,0 +1,141 @@ +#[doc = "Register `SUBSCRIBE_TRIGOVRFLW` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SUBSCRIBE_TRIGOVRFLW` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CHIDX` reader - DPPI channel that task TRIGOVRFLW will subscribe to"] +pub type CHIDX_R = crate::FieldReader; +#[doc = "Field `CHIDX` writer - DPPI channel that task TRIGOVRFLW will subscribe to"] +pub type CHIDX_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, SUBSCRIBE_TRIGOVRFLW_SPEC, u8, u8, 8, O>; +#[doc = "Field `EN` reader - "] +pub type EN_R = crate::BitReader; +#[doc = "\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum EN_A { + #[doc = "0: Disable subscription"] + DISABLED = 0, + #[doc = "1: Enable subscription"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: EN_A) -> Self { + variant as u8 != 0 + } +} +impl EN_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EN_A { + match self.bits { + false => EN_A::DISABLED, + true => EN_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == EN_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == EN_A::ENABLED + } +} +#[doc = "Field `EN` writer - "] +pub type EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, SUBSCRIBE_TRIGOVRFLW_SPEC, EN_A, O>; +impl<'a, const O: u8> EN_W<'a, O> { + #[doc = "Disable subscription"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(EN_A::DISABLED) + } + #[doc = "Enable subscription"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(EN_A::ENABLED) + } +} +impl R { + #[doc = "Bits 0:7 - DPPI channel that task TRIGOVRFLW will subscribe to"] + #[inline(always)] + pub fn chidx(&self) -> CHIDX_R { + CHIDX_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&self) -> EN_R { + EN_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:7 - DPPI channel that task TRIGOVRFLW will subscribe to"] + #[inline(always)] + pub fn chidx(&mut self) -> CHIDX_W<0> { + CHIDX_W::new(self) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&mut self) -> EN_W<31> { + EN_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Subscribe configuration for task TRIGOVRFLW\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [subscribe_trigovrflw](index.html) module"] +pub struct SUBSCRIBE_TRIGOVRFLW_SPEC; +impl crate::RegisterSpec for SUBSCRIBE_TRIGOVRFLW_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [subscribe_trigovrflw::R](R) reader structure"] +impl crate::Readable for SUBSCRIBE_TRIGOVRFLW_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [subscribe_trigovrflw::W](W) writer structure"] +impl crate::Writable for SUBSCRIBE_TRIGOVRFLW_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SUBSCRIBE_TRIGOVRFLW to value 0"] +impl crate::Resettable for SUBSCRIBE_TRIGOVRFLW_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/rtc0_ns/tasks_clear.rs b/pacs/nrf9120-pac/src/rtc0_ns/tasks_clear.rs new file mode 100644 index 00000000..15ee821f --- /dev/null +++ b/pacs/nrf9120-pac/src/rtc0_ns/tasks_clear.rs @@ -0,0 +1,72 @@ +#[doc = "Register `TASKS_CLEAR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Clear RTC counter\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum TASKS_CLEAR_AW { + #[doc = "1: Trigger task"] + TRIGGER = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TASKS_CLEAR_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TASKS_CLEAR` writer - Clear RTC counter"] +pub type TASKS_CLEAR_W<'a, const O: u8> = + crate::BitWriter<'a, u32, TASKS_CLEAR_SPEC, TASKS_CLEAR_AW, O>; +impl<'a, const O: u8> TASKS_CLEAR_W<'a, O> { + #[doc = "Trigger task"] + #[inline(always)] + pub fn trigger(self) -> &'a mut W { + self.variant(TASKS_CLEAR_AW::TRIGGER) + } +} +impl W { + #[doc = "Bit 0 - Clear RTC counter"] + #[inline(always)] + pub fn tasks_clear(&mut self) -> TASKS_CLEAR_W<0> { + TASKS_CLEAR_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Clear RTC counter\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tasks_clear](index.html) module"] +pub struct TASKS_CLEAR_SPEC; +impl crate::RegisterSpec for TASKS_CLEAR_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [tasks_clear::W](W) writer structure"] +impl crate::Writable for TASKS_CLEAR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets TASKS_CLEAR to value 0"] +impl crate::Resettable for TASKS_CLEAR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/rtc0_ns/tasks_start.rs b/pacs/nrf9120-pac/src/rtc0_ns/tasks_start.rs new file mode 100644 index 00000000..c284c521 --- /dev/null +++ b/pacs/nrf9120-pac/src/rtc0_ns/tasks_start.rs @@ -0,0 +1,72 @@ +#[doc = "Register `TASKS_START` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Start RTC counter\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum TASKS_START_AW { + #[doc = "1: Trigger task"] + TRIGGER = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TASKS_START_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TASKS_START` writer - Start RTC counter"] +pub type TASKS_START_W<'a, const O: u8> = + crate::BitWriter<'a, u32, TASKS_START_SPEC, TASKS_START_AW, O>; +impl<'a, const O: u8> TASKS_START_W<'a, O> { + #[doc = "Trigger task"] + #[inline(always)] + pub fn trigger(self) -> &'a mut W { + self.variant(TASKS_START_AW::TRIGGER) + } +} +impl W { + #[doc = "Bit 0 - Start RTC counter"] + #[inline(always)] + pub fn tasks_start(&mut self) -> TASKS_START_W<0> { + TASKS_START_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Start RTC counter\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tasks_start](index.html) module"] +pub struct TASKS_START_SPEC; +impl crate::RegisterSpec for TASKS_START_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [tasks_start::W](W) writer structure"] +impl crate::Writable for TASKS_START_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets TASKS_START to value 0"] +impl crate::Resettable for TASKS_START_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/rtc0_ns/tasks_stop.rs b/pacs/nrf9120-pac/src/rtc0_ns/tasks_stop.rs new file mode 100644 index 00000000..f408246a --- /dev/null +++ b/pacs/nrf9120-pac/src/rtc0_ns/tasks_stop.rs @@ -0,0 +1,72 @@ +#[doc = "Register `TASKS_STOP` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Stop RTC counter\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum TASKS_STOP_AW { + #[doc = "1: Trigger task"] + TRIGGER = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TASKS_STOP_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TASKS_STOP` writer - Stop RTC counter"] +pub type TASKS_STOP_W<'a, const O: u8> = + crate::BitWriter<'a, u32, TASKS_STOP_SPEC, TASKS_STOP_AW, O>; +impl<'a, const O: u8> TASKS_STOP_W<'a, O> { + #[doc = "Trigger task"] + #[inline(always)] + pub fn trigger(self) -> &'a mut W { + self.variant(TASKS_STOP_AW::TRIGGER) + } +} +impl W { + #[doc = "Bit 0 - Stop RTC counter"] + #[inline(always)] + pub fn tasks_stop(&mut self) -> TASKS_STOP_W<0> { + TASKS_STOP_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Stop RTC counter\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tasks_stop](index.html) module"] +pub struct TASKS_STOP_SPEC; +impl crate::RegisterSpec for TASKS_STOP_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [tasks_stop::W](W) writer structure"] +impl crate::Writable for TASKS_STOP_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets TASKS_STOP to value 0"] +impl crate::Resettable for TASKS_STOP_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/rtc0_ns/tasks_trigovrflw.rs b/pacs/nrf9120-pac/src/rtc0_ns/tasks_trigovrflw.rs new file mode 100644 index 00000000..ff9a6ab1 --- /dev/null +++ b/pacs/nrf9120-pac/src/rtc0_ns/tasks_trigovrflw.rs @@ -0,0 +1,72 @@ +#[doc = "Register `TASKS_TRIGOVRFLW` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Set counter to 0xFFFFF0\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum TASKS_TRIGOVRFLW_AW { + #[doc = "1: Trigger task"] + TRIGGER = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TASKS_TRIGOVRFLW_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TASKS_TRIGOVRFLW` writer - Set counter to 0xFFFFF0"] +pub type TASKS_TRIGOVRFLW_W<'a, const O: u8> = + crate::BitWriter<'a, u32, TASKS_TRIGOVRFLW_SPEC, TASKS_TRIGOVRFLW_AW, O>; +impl<'a, const O: u8> TASKS_TRIGOVRFLW_W<'a, O> { + #[doc = "Trigger task"] + #[inline(always)] + pub fn trigger(self) -> &'a mut W { + self.variant(TASKS_TRIGOVRFLW_AW::TRIGGER) + } +} +impl W { + #[doc = "Bit 0 - Set counter to 0xFFFFF0"] + #[inline(always)] + pub fn tasks_trigovrflw(&mut self) -> TASKS_TRIGOVRFLW_W<0> { + TASKS_TRIGOVRFLW_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Set counter to 0xFFFFF0\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tasks_trigovrflw](index.html) module"] +pub struct TASKS_TRIGOVRFLW_SPEC; +impl crate::RegisterSpec for TASKS_TRIGOVRFLW_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [tasks_trigovrflw::W](W) writer structure"] +impl crate::Writable for TASKS_TRIGOVRFLW_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets TASKS_TRIGOVRFLW to value 0"] +impl crate::Resettable for TASKS_TRIGOVRFLW_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/saadc_ns.rs b/pacs/nrf9120-pac/src/saadc_ns.rs new file mode 100644 index 00000000..bd69fef6 --- /dev/null +++ b/pacs/nrf9120-pac/src/saadc_ns.rs @@ -0,0 +1,210 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Start the ADC and prepare the result buffer in RAM"] + pub tasks_start: TASKS_START, + #[doc = "0x04 - Take one ADC sample, if scan is enabled all channels are sampled"] + pub tasks_sample: TASKS_SAMPLE, + #[doc = "0x08 - Stop the ADC and terminate any on-going conversion"] + pub tasks_stop: TASKS_STOP, + #[doc = "0x0c - Starts offset auto-calibration"] + pub tasks_calibrateoffset: TASKS_CALIBRATEOFFSET, + _reserved4: [u8; 0x70], + #[doc = "0x80 - Subscribe configuration for task START"] + pub subscribe_start: SUBSCRIBE_START, + #[doc = "0x84 - Subscribe configuration for task SAMPLE"] + pub subscribe_sample: SUBSCRIBE_SAMPLE, + #[doc = "0x88 - Subscribe configuration for task STOP"] + pub subscribe_stop: SUBSCRIBE_STOP, + #[doc = "0x8c - Subscribe configuration for task CALIBRATEOFFSET"] + pub subscribe_calibrateoffset: SUBSCRIBE_CALIBRATEOFFSET, + _reserved8: [u8; 0x70], + #[doc = "0x100 - The ADC has started"] + pub events_started: EVENTS_STARTED, + #[doc = "0x104 - The ADC has filled up the Result buffer"] + pub events_end: EVENTS_END, + #[doc = "0x108 - A conversion task has been completed. Depending on the mode, multiple conversions might be needed for a result to be transferred to RAM."] + pub events_done: EVENTS_DONE, + #[doc = "0x10c - A result is ready to get transferred to RAM."] + pub events_resultdone: EVENTS_RESULTDONE, + #[doc = "0x110 - Calibration is complete"] + pub events_calibratedone: EVENTS_CALIBRATEDONE, + #[doc = "0x114 - The ADC has stopped"] + pub events_stopped: EVENTS_STOPPED, + #[doc = "0x118..0x158 - Peripheral events."] + pub events_ch: [EVENTS_CH; 8], + _reserved15: [u8; 0x28], + #[doc = "0x180 - Publish configuration for event STARTED"] + pub publish_started: PUBLISH_STARTED, + #[doc = "0x184 - Publish configuration for event END"] + pub publish_end: PUBLISH_END, + #[doc = "0x188 - Publish configuration for event DONE"] + pub publish_done: PUBLISH_DONE, + #[doc = "0x18c - Publish configuration for event RESULTDONE"] + pub publish_resultdone: PUBLISH_RESULTDONE, + #[doc = "0x190 - Publish configuration for event CALIBRATEDONE"] + pub publish_calibratedone: PUBLISH_CALIBRATEDONE, + #[doc = "0x194 - Publish configuration for event STOPPED"] + pub publish_stopped: PUBLISH_STOPPED, + #[doc = "0x198..0x1d8 - Publish configuration for events"] + pub publish_ch: [PUBLISH_CH; 8], + _reserved22: [u8; 0x0128], + #[doc = "0x300 - Enable or disable interrupt"] + pub inten: INTEN, + #[doc = "0x304 - Enable interrupt"] + pub intenset: INTENSET, + #[doc = "0x308 - Disable interrupt"] + pub intenclr: INTENCLR, + _reserved25: [u8; 0xf4], + #[doc = "0x400 - Status"] + pub status: STATUS, + _reserved26: [u8; 0xfc], + #[doc = "0x500 - Enable or disable ADC"] + pub enable: ENABLE, + _reserved27: [u8; 0x0c], + #[doc = "0x510..0x590 - Unspecified"] + pub ch: [CH; 8], + _reserved28: [u8; 0x60], + #[doc = "0x5f0 - Resolution configuration"] + pub resolution: RESOLUTION, + #[doc = "0x5f4 - Oversampling configuration. OVERSAMPLE should not be combined with SCAN. The RESOLUTION is applied before averaging, thus for high OVERSAMPLE a higher RESOLUTION should be used."] + pub oversample: OVERSAMPLE, + #[doc = "0x5f8 - Controls normal or continuous sample rate"] + pub samplerate: SAMPLERATE, + _reserved31: [u8; 0x30], + #[doc = "0x62c..0x638 - RESULT EasyDMA channel"] + pub result: RESULT, +} +#[doc = "TASKS_START (w) register accessor: an alias for `Reg`"] +pub type TASKS_START = crate::Reg; +#[doc = "Start the ADC and prepare the result buffer in RAM"] +pub mod tasks_start; +#[doc = "TASKS_SAMPLE (w) register accessor: an alias for `Reg`"] +pub type TASKS_SAMPLE = crate::Reg; +#[doc = "Take one ADC sample, if scan is enabled all channels are sampled"] +pub mod tasks_sample; +#[doc = "TASKS_STOP (w) register accessor: an alias for `Reg`"] +pub type TASKS_STOP = crate::Reg; +#[doc = "Stop the ADC and terminate any on-going conversion"] +pub mod tasks_stop; +#[doc = "TASKS_CALIBRATEOFFSET (w) register accessor: an alias for `Reg`"] +pub type TASKS_CALIBRATEOFFSET = crate::Reg; +#[doc = "Starts offset auto-calibration"] +pub mod tasks_calibrateoffset; +#[doc = "SUBSCRIBE_START (rw) register accessor: an alias for `Reg`"] +pub type SUBSCRIBE_START = crate::Reg; +#[doc = "Subscribe configuration for task START"] +pub mod subscribe_start; +#[doc = "SUBSCRIBE_SAMPLE (rw) register accessor: an alias for `Reg`"] +pub type SUBSCRIBE_SAMPLE = crate::Reg; +#[doc = "Subscribe configuration for task SAMPLE"] +pub mod subscribe_sample; +#[doc = "SUBSCRIBE_STOP (rw) register accessor: an alias for `Reg`"] +pub type SUBSCRIBE_STOP = crate::Reg; +#[doc = "Subscribe configuration for task STOP"] +pub mod subscribe_stop; +#[doc = "SUBSCRIBE_CALIBRATEOFFSET (rw) register accessor: an alias for `Reg`"] +pub type SUBSCRIBE_CALIBRATEOFFSET = + crate::Reg; +#[doc = "Subscribe configuration for task CALIBRATEOFFSET"] +pub mod subscribe_calibrateoffset; +#[doc = "EVENTS_STARTED (rw) register accessor: an alias for `Reg`"] +pub type EVENTS_STARTED = crate::Reg; +#[doc = "The ADC has started"] +pub mod events_started; +#[doc = "EVENTS_END (rw) register accessor: an alias for `Reg`"] +pub type EVENTS_END = crate::Reg; +#[doc = "The ADC has filled up the Result buffer"] +pub mod events_end; +#[doc = "EVENTS_DONE (rw) register accessor: an alias for `Reg`"] +pub type EVENTS_DONE = crate::Reg; +#[doc = "A conversion task has been completed. Depending on the mode, multiple conversions might be needed for a result to be transferred to RAM."] +pub mod events_done; +#[doc = "EVENTS_RESULTDONE (rw) register accessor: an alias for `Reg`"] +pub type EVENTS_RESULTDONE = crate::Reg; +#[doc = "A result is ready to get transferred to RAM."] +pub mod events_resultdone; +#[doc = "EVENTS_CALIBRATEDONE (rw) register accessor: an alias for `Reg`"] +pub type EVENTS_CALIBRATEDONE = crate::Reg; +#[doc = "Calibration is complete"] +pub mod events_calibratedone; +#[doc = "EVENTS_STOPPED (rw) register accessor: an alias for `Reg`"] +pub type EVENTS_STOPPED = crate::Reg; +#[doc = "The ADC has stopped"] +pub mod events_stopped; +#[doc = "Peripheral events."] +pub use events_ch::EVENTS_CH; +#[doc = r"Cluster"] +#[doc = "Peripheral events."] +pub mod events_ch; +#[doc = "PUBLISH_STARTED (rw) register accessor: an alias for `Reg`"] +pub type PUBLISH_STARTED = crate::Reg; +#[doc = "Publish configuration for event STARTED"] +pub mod publish_started; +#[doc = "PUBLISH_END (rw) register accessor: an alias for `Reg`"] +pub type PUBLISH_END = crate::Reg; +#[doc = "Publish configuration for event END"] +pub mod publish_end; +#[doc = "PUBLISH_DONE (rw) register accessor: an alias for `Reg`"] +pub type PUBLISH_DONE = crate::Reg; +#[doc = "Publish configuration for event DONE"] +pub mod publish_done; +#[doc = "PUBLISH_RESULTDONE (rw) register accessor: an alias for `Reg`"] +pub type PUBLISH_RESULTDONE = crate::Reg; +#[doc = "Publish configuration for event RESULTDONE"] +pub mod publish_resultdone; +#[doc = "PUBLISH_CALIBRATEDONE (rw) register accessor: an alias for `Reg`"] +pub type PUBLISH_CALIBRATEDONE = crate::Reg; +#[doc = "Publish configuration for event CALIBRATEDONE"] +pub mod publish_calibratedone; +#[doc = "PUBLISH_STOPPED (rw) register accessor: an alias for `Reg`"] +pub type PUBLISH_STOPPED = crate::Reg; +#[doc = "Publish configuration for event STOPPED"] +pub mod publish_stopped; +#[doc = "Publish configuration for events"] +pub use publish_ch::PUBLISH_CH; +#[doc = r"Cluster"] +#[doc = "Publish configuration for events"] +pub mod publish_ch; +#[doc = "INTEN (rw) register accessor: an alias for `Reg`"] +pub type INTEN = crate::Reg; +#[doc = "Enable or disable interrupt"] +pub mod inten; +#[doc = "INTENSET (rw) register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "Enable interrupt"] +pub mod intenset; +#[doc = "INTENCLR (rw) register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "Disable interrupt"] +pub mod intenclr; +#[doc = "STATUS (r) register accessor: an alias for `Reg`"] +pub type STATUS = crate::Reg; +#[doc = "Status"] +pub mod status; +#[doc = "ENABLE (rw) register accessor: an alias for `Reg`"] +pub type ENABLE = crate::Reg; +#[doc = "Enable or disable ADC"] +pub mod enable; +#[doc = "Unspecified"] +pub use ch::CH; +#[doc = r"Cluster"] +#[doc = "Unspecified"] +pub mod ch; +#[doc = "RESOLUTION (rw) register accessor: an alias for `Reg`"] +pub type RESOLUTION = crate::Reg; +#[doc = "Resolution configuration"] +pub mod resolution; +#[doc = "OVERSAMPLE (rw) register accessor: an alias for `Reg`"] +pub type OVERSAMPLE = crate::Reg; +#[doc = "Oversampling configuration. OVERSAMPLE should not be combined with SCAN. The RESOLUTION is applied before averaging, thus for high OVERSAMPLE a higher RESOLUTION should be used."] +pub mod oversample; +#[doc = "SAMPLERATE (rw) register accessor: an alias for `Reg`"] +pub type SAMPLERATE = crate::Reg; +#[doc = "Controls normal or continuous sample rate"] +pub mod samplerate; +#[doc = "RESULT EasyDMA channel"] +pub use result::RESULT; +#[doc = r"Cluster"] +#[doc = "RESULT EasyDMA channel"] +pub mod result; diff --git a/pacs/nrf9120-pac/src/saadc_ns/ch.rs b/pacs/nrf9120-pac/src/saadc_ns/ch.rs new file mode 100644 index 00000000..63b5159b --- /dev/null +++ b/pacs/nrf9120-pac/src/saadc_ns/ch.rs @@ -0,0 +1,28 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct CH { + #[doc = "0x00 - Description cluster: Input positive pin selection for CH\\[n\\]"] + pub pselp: PSELP, + #[doc = "0x04 - Description cluster: Input negative pin selection for CH\\[n\\]"] + pub pseln: PSELN, + #[doc = "0x08 - Description cluster: Input configuration for CH\\[n\\]"] + pub config: CONFIG, + #[doc = "0x0c - Description cluster: High/low limits for event monitoring a channel"] + pub limit: LIMIT, +} +#[doc = "PSELP (rw) register accessor: an alias for `Reg`"] +pub type PSELP = crate::Reg; +#[doc = "Description cluster: Input positive pin selection for CH\\[n\\]"] +pub mod pselp; +#[doc = "PSELN (rw) register accessor: an alias for `Reg`"] +pub type PSELN = crate::Reg; +#[doc = "Description cluster: Input negative pin selection for CH\\[n\\]"] +pub mod pseln; +#[doc = "CONFIG (rw) register accessor: an alias for `Reg`"] +pub type CONFIG = crate::Reg; +#[doc = "Description cluster: Input configuration for CH\\[n\\]"] +pub mod config; +#[doc = "LIMIT (rw) register accessor: an alias for `Reg`"] +pub type LIMIT = crate::Reg; +#[doc = "Description cluster: High/low limits for event monitoring a channel"] +pub mod limit; diff --git a/pacs/nrf9120-pac/src/saadc_ns/ch/config.rs b/pacs/nrf9120-pac/src/saadc_ns/ch/config.rs new file mode 100644 index 00000000..f865a5bd --- /dev/null +++ b/pacs/nrf9120-pac/src/saadc_ns/ch/config.rs @@ -0,0 +1,676 @@ +#[doc = "Register `CONFIG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CONFIG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `RESP` reader - Positive channel resistor control"] +pub type RESP_R = crate::FieldReader; +#[doc = "Positive channel resistor control\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum RESP_A { + #[doc = "0: Bypass resistor ladder"] + BYPASS = 0, + #[doc = "1: Pull-down to GND"] + PULLDOWN = 1, + #[doc = "2: Pull-up to VDD_GPIO"] + PULLUP = 2, + #[doc = "3: Set input at VDD_GPIO/2"] + VDD1_2 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: RESP_A) -> Self { + variant as _ + } +} +impl RESP_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RESP_A { + match self.bits { + 0 => RESP_A::BYPASS, + 1 => RESP_A::PULLDOWN, + 2 => RESP_A::PULLUP, + 3 => RESP_A::VDD1_2, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `BYPASS`"] + #[inline(always)] + pub fn is_bypass(&self) -> bool { + *self == RESP_A::BYPASS + } + #[doc = "Checks if the value of the field is `PULLDOWN`"] + #[inline(always)] + pub fn is_pulldown(&self) -> bool { + *self == RESP_A::PULLDOWN + } + #[doc = "Checks if the value of the field is `PULLUP`"] + #[inline(always)] + pub fn is_pullup(&self) -> bool { + *self == RESP_A::PULLUP + } + #[doc = "Checks if the value of the field is `VDD1_2`"] + #[inline(always)] + pub fn is_vdd1_2(&self) -> bool { + *self == RESP_A::VDD1_2 + } +} +#[doc = "Field `RESP` writer - Positive channel resistor control"] +pub type RESP_W<'a, const O: u8> = crate::FieldWriterSafe<'a, u32, CONFIG_SPEC, u8, RESP_A, 2, O>; +impl<'a, const O: u8> RESP_W<'a, O> { + #[doc = "Bypass resistor ladder"] + #[inline(always)] + pub fn bypass(self) -> &'a mut W { + self.variant(RESP_A::BYPASS) + } + #[doc = "Pull-down to GND"] + #[inline(always)] + pub fn pulldown(self) -> &'a mut W { + self.variant(RESP_A::PULLDOWN) + } + #[doc = "Pull-up to VDD_GPIO"] + #[inline(always)] + pub fn pullup(self) -> &'a mut W { + self.variant(RESP_A::PULLUP) + } + #[doc = "Set input at VDD_GPIO/2"] + #[inline(always)] + pub fn vdd1_2(self) -> &'a mut W { + self.variant(RESP_A::VDD1_2) + } +} +#[doc = "Field `RESN` reader - Negative channel resistor control"] +pub type RESN_R = crate::FieldReader; +#[doc = "Negative channel resistor control\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum RESN_A { + #[doc = "0: Bypass resistor ladder"] + BYPASS = 0, + #[doc = "1: Pull-down to GND"] + PULLDOWN = 1, + #[doc = "2: Pull-up to VDD_GPIO"] + PULLUP = 2, + #[doc = "3: Set input at VDD_GPIO/2"] + VDD1_2 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: RESN_A) -> Self { + variant as _ + } +} +impl RESN_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RESN_A { + match self.bits { + 0 => RESN_A::BYPASS, + 1 => RESN_A::PULLDOWN, + 2 => RESN_A::PULLUP, + 3 => RESN_A::VDD1_2, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `BYPASS`"] + #[inline(always)] + pub fn is_bypass(&self) -> bool { + *self == RESN_A::BYPASS + } + #[doc = "Checks if the value of the field is `PULLDOWN`"] + #[inline(always)] + pub fn is_pulldown(&self) -> bool { + *self == RESN_A::PULLDOWN + } + #[doc = "Checks if the value of the field is `PULLUP`"] + #[inline(always)] + pub fn is_pullup(&self) -> bool { + *self == RESN_A::PULLUP + } + #[doc = "Checks if the value of the field is `VDD1_2`"] + #[inline(always)] + pub fn is_vdd1_2(&self) -> bool { + *self == RESN_A::VDD1_2 + } +} +#[doc = "Field `RESN` writer - Negative channel resistor control"] +pub type RESN_W<'a, const O: u8> = crate::FieldWriterSafe<'a, u32, CONFIG_SPEC, u8, RESN_A, 2, O>; +impl<'a, const O: u8> RESN_W<'a, O> { + #[doc = "Bypass resistor ladder"] + #[inline(always)] + pub fn bypass(self) -> &'a mut W { + self.variant(RESN_A::BYPASS) + } + #[doc = "Pull-down to GND"] + #[inline(always)] + pub fn pulldown(self) -> &'a mut W { + self.variant(RESN_A::PULLDOWN) + } + #[doc = "Pull-up to VDD_GPIO"] + #[inline(always)] + pub fn pullup(self) -> &'a mut W { + self.variant(RESN_A::PULLUP) + } + #[doc = "Set input at VDD_GPIO/2"] + #[inline(always)] + pub fn vdd1_2(self) -> &'a mut W { + self.variant(RESN_A::VDD1_2) + } +} +#[doc = "Field `GAIN` reader - Gain control"] +pub type GAIN_R = crate::FieldReader; +#[doc = "Gain control\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum GAIN_A { + #[doc = "0: 1/6"] + GAIN1_6 = 0, + #[doc = "1: 1/5"] + GAIN1_5 = 1, + #[doc = "2: 1/4"] + GAIN1_4 = 2, + #[doc = "3: 1/3"] + GAIN1_3 = 3, + #[doc = "4: 1/2"] + GAIN1_2 = 4, + #[doc = "5: 1"] + GAIN1 = 5, + #[doc = "6: 2"] + GAIN2 = 6, + #[doc = "7: 4"] + GAIN4 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: GAIN_A) -> Self { + variant as _ + } +} +impl GAIN_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> GAIN_A { + match self.bits { + 0 => GAIN_A::GAIN1_6, + 1 => GAIN_A::GAIN1_5, + 2 => GAIN_A::GAIN1_4, + 3 => GAIN_A::GAIN1_3, + 4 => GAIN_A::GAIN1_2, + 5 => GAIN_A::GAIN1, + 6 => GAIN_A::GAIN2, + 7 => GAIN_A::GAIN4, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `GAIN1_6`"] + #[inline(always)] + pub fn is_gain1_6(&self) -> bool { + *self == GAIN_A::GAIN1_6 + } + #[doc = "Checks if the value of the field is `GAIN1_5`"] + #[inline(always)] + pub fn is_gain1_5(&self) -> bool { + *self == GAIN_A::GAIN1_5 + } + #[doc = "Checks if the value of the field is `GAIN1_4`"] + #[inline(always)] + pub fn is_gain1_4(&self) -> bool { + *self == GAIN_A::GAIN1_4 + } + #[doc = "Checks if the value of the field is `GAIN1_3`"] + #[inline(always)] + pub fn is_gain1_3(&self) -> bool { + *self == GAIN_A::GAIN1_3 + } + #[doc = "Checks if the value of the field is `GAIN1_2`"] + #[inline(always)] + pub fn is_gain1_2(&self) -> bool { + *self == GAIN_A::GAIN1_2 + } + #[doc = "Checks if the value of the field is `GAIN1`"] + #[inline(always)] + pub fn is_gain1(&self) -> bool { + *self == GAIN_A::GAIN1 + } + #[doc = "Checks if the value of the field is `GAIN2`"] + #[inline(always)] + pub fn is_gain2(&self) -> bool { + *self == GAIN_A::GAIN2 + } + #[doc = "Checks if the value of the field is `GAIN4`"] + #[inline(always)] + pub fn is_gain4(&self) -> bool { + *self == GAIN_A::GAIN4 + } +} +#[doc = "Field `GAIN` writer - Gain control"] +pub type GAIN_W<'a, const O: u8> = crate::FieldWriterSafe<'a, u32, CONFIG_SPEC, u8, GAIN_A, 3, O>; +impl<'a, const O: u8> GAIN_W<'a, O> { + #[doc = "1/6"] + #[inline(always)] + pub fn gain1_6(self) -> &'a mut W { + self.variant(GAIN_A::GAIN1_6) + } + #[doc = "1/5"] + #[inline(always)] + pub fn gain1_5(self) -> &'a mut W { + self.variant(GAIN_A::GAIN1_5) + } + #[doc = "1/4"] + #[inline(always)] + pub fn gain1_4(self) -> &'a mut W { + self.variant(GAIN_A::GAIN1_4) + } + #[doc = "1/3"] + #[inline(always)] + pub fn gain1_3(self) -> &'a mut W { + self.variant(GAIN_A::GAIN1_3) + } + #[doc = "1/2"] + #[inline(always)] + pub fn gain1_2(self) -> &'a mut W { + self.variant(GAIN_A::GAIN1_2) + } + #[doc = "1"] + #[inline(always)] + pub fn gain1(self) -> &'a mut W { + self.variant(GAIN_A::GAIN1) + } + #[doc = "2"] + #[inline(always)] + pub fn gain2(self) -> &'a mut W { + self.variant(GAIN_A::GAIN2) + } + #[doc = "4"] + #[inline(always)] + pub fn gain4(self) -> &'a mut W { + self.variant(GAIN_A::GAIN4) + } +} +#[doc = "Field `REFSEL` reader - Reference control"] +pub type REFSEL_R = crate::BitReader; +#[doc = "Reference control\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum REFSEL_A { + #[doc = "0: Internal reference (0.6 V)"] + INTERNAL = 0, + #[doc = "1: VDD_GPIO/4 as reference"] + VDD1_4 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: REFSEL_A) -> Self { + variant as u8 != 0 + } +} +impl REFSEL_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> REFSEL_A { + match self.bits { + false => REFSEL_A::INTERNAL, + true => REFSEL_A::VDD1_4, + } + } + #[doc = "Checks if the value of the field is `INTERNAL`"] + #[inline(always)] + pub fn is_internal(&self) -> bool { + *self == REFSEL_A::INTERNAL + } + #[doc = "Checks if the value of the field is `VDD1_4`"] + #[inline(always)] + pub fn is_vdd1_4(&self) -> bool { + *self == REFSEL_A::VDD1_4 + } +} +#[doc = "Field `REFSEL` writer - Reference control"] +pub type REFSEL_W<'a, const O: u8> = crate::BitWriter<'a, u32, CONFIG_SPEC, REFSEL_A, O>; +impl<'a, const O: u8> REFSEL_W<'a, O> { + #[doc = "Internal reference (0.6 V)"] + #[inline(always)] + pub fn internal(self) -> &'a mut W { + self.variant(REFSEL_A::INTERNAL) + } + #[doc = "VDD_GPIO/4 as reference"] + #[inline(always)] + pub fn vdd1_4(self) -> &'a mut W { + self.variant(REFSEL_A::VDD1_4) + } +} +#[doc = "Field `TACQ` reader - Acquisition time, the time the ADC uses to sample the input voltage"] +pub type TACQ_R = crate::FieldReader; +#[doc = "Acquisition time, the time the ADC uses to sample the input voltage\n\nValue on reset: 2"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum TACQ_A { + #[doc = "0: 3 us"] + _3US = 0, + #[doc = "1: 5 us"] + _5US = 1, + #[doc = "2: 10 us"] + _10US = 2, + #[doc = "3: 15 us"] + _15US = 3, + #[doc = "4: 20 us"] + _20US = 4, + #[doc = "5: 40 us"] + _40US = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: TACQ_A) -> Self { + variant as _ + } +} +impl TACQ_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(TACQ_A::_3US), + 1 => Some(TACQ_A::_5US), + 2 => Some(TACQ_A::_10US), + 3 => Some(TACQ_A::_15US), + 4 => Some(TACQ_A::_20US), + 5 => Some(TACQ_A::_40US), + _ => None, + } + } + #[doc = "Checks if the value of the field is `_3US`"] + #[inline(always)] + pub fn is_3us(&self) -> bool { + *self == TACQ_A::_3US + } + #[doc = "Checks if the value of the field is `_5US`"] + #[inline(always)] + pub fn is_5us(&self) -> bool { + *self == TACQ_A::_5US + } + #[doc = "Checks if the value of the field is `_10US`"] + #[inline(always)] + pub fn is_10us(&self) -> bool { + *self == TACQ_A::_10US + } + #[doc = "Checks if the value of the field is `_15US`"] + #[inline(always)] + pub fn is_15us(&self) -> bool { + *self == TACQ_A::_15US + } + #[doc = "Checks if the value of the field is `_20US`"] + #[inline(always)] + pub fn is_20us(&self) -> bool { + *self == TACQ_A::_20US + } + #[doc = "Checks if the value of the field is `_40US`"] + #[inline(always)] + pub fn is_40us(&self) -> bool { + *self == TACQ_A::_40US + } +} +#[doc = "Field `TACQ` writer - Acquisition time, the time the ADC uses to sample the input voltage"] +pub type TACQ_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CONFIG_SPEC, u8, TACQ_A, 3, O>; +impl<'a, const O: u8> TACQ_W<'a, O> { + #[doc = "3 us"] + #[inline(always)] + pub fn _3us(self) -> &'a mut W { + self.variant(TACQ_A::_3US) + } + #[doc = "5 us"] + #[inline(always)] + pub fn _5us(self) -> &'a mut W { + self.variant(TACQ_A::_5US) + } + #[doc = "10 us"] + #[inline(always)] + pub fn _10us(self) -> &'a mut W { + self.variant(TACQ_A::_10US) + } + #[doc = "15 us"] + #[inline(always)] + pub fn _15us(self) -> &'a mut W { + self.variant(TACQ_A::_15US) + } + #[doc = "20 us"] + #[inline(always)] + pub fn _20us(self) -> &'a mut W { + self.variant(TACQ_A::_20US) + } + #[doc = "40 us"] + #[inline(always)] + pub fn _40us(self) -> &'a mut W { + self.variant(TACQ_A::_40US) + } +} +#[doc = "Field `MODE` reader - Enable differential mode"] +pub type MODE_R = crate::BitReader; +#[doc = "Enable differential mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum MODE_A { + #[doc = "0: Single ended, PSELN will be ignored, negative input to ADC shorted to GND"] + SE = 0, + #[doc = "1: Differential"] + DIFF = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: MODE_A) -> Self { + variant as u8 != 0 + } +} +impl MODE_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> MODE_A { + match self.bits { + false => MODE_A::SE, + true => MODE_A::DIFF, + } + } + #[doc = "Checks if the value of the field is `SE`"] + #[inline(always)] + pub fn is_se(&self) -> bool { + *self == MODE_A::SE + } + #[doc = "Checks if the value of the field is `DIFF`"] + #[inline(always)] + pub fn is_diff(&self) -> bool { + *self == MODE_A::DIFF + } +} +#[doc = "Field `MODE` writer - Enable differential mode"] +pub type MODE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CONFIG_SPEC, MODE_A, O>; +impl<'a, const O: u8> MODE_W<'a, O> { + #[doc = "Single ended, PSELN will be ignored, negative input to ADC shorted to GND"] + #[inline(always)] + pub fn se(self) -> &'a mut W { + self.variant(MODE_A::SE) + } + #[doc = "Differential"] + #[inline(always)] + pub fn diff(self) -> &'a mut W { + self.variant(MODE_A::DIFF) + } +} +#[doc = "Field `BURST` reader - Enable burst mode"] +pub type BURST_R = crate::BitReader; +#[doc = "Enable burst mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum BURST_A { + #[doc = "0: Burst mode is disabled (normal operation)"] + DISABLED = 0, + #[doc = "1: Burst mode is enabled. SAADC takes 2^OVERSAMPLE number of samples as fast as it can, and sends the average to Data RAM."] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: BURST_A) -> Self { + variant as u8 != 0 + } +} +impl BURST_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> BURST_A { + match self.bits { + false => BURST_A::DISABLED, + true => BURST_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == BURST_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == BURST_A::ENABLED + } +} +#[doc = "Field `BURST` writer - Enable burst mode"] +pub type BURST_W<'a, const O: u8> = crate::BitWriter<'a, u32, CONFIG_SPEC, BURST_A, O>; +impl<'a, const O: u8> BURST_W<'a, O> { + #[doc = "Burst mode is disabled (normal operation)"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(BURST_A::DISABLED) + } + #[doc = "Burst mode is enabled. SAADC takes 2^OVERSAMPLE number of samples as fast as it can, and sends the average to Data RAM."] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(BURST_A::ENABLED) + } +} +impl R { + #[doc = "Bits 0:1 - Positive channel resistor control"] + #[inline(always)] + pub fn resp(&self) -> RESP_R { + RESP_R::new((self.bits & 3) as u8) + } + #[doc = "Bits 4:5 - Negative channel resistor control"] + #[inline(always)] + pub fn resn(&self) -> RESN_R { + RESN_R::new(((self.bits >> 4) & 3) as u8) + } + #[doc = "Bits 8:10 - Gain control"] + #[inline(always)] + pub fn gain(&self) -> GAIN_R { + GAIN_R::new(((self.bits >> 8) & 7) as u8) + } + #[doc = "Bit 12 - Reference control"] + #[inline(always)] + pub fn refsel(&self) -> REFSEL_R { + REFSEL_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bits 16:18 - Acquisition time, the time the ADC uses to sample the input voltage"] + #[inline(always)] + pub fn tacq(&self) -> TACQ_R { + TACQ_R::new(((self.bits >> 16) & 7) as u8) + } + #[doc = "Bit 20 - Enable differential mode"] + #[inline(always)] + pub fn mode(&self) -> MODE_R { + MODE_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 24 - Enable burst mode"] + #[inline(always)] + pub fn burst(&self) -> BURST_R { + BURST_R::new(((self.bits >> 24) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:1 - Positive channel resistor control"] + #[inline(always)] + pub fn resp(&mut self) -> RESP_W<0> { + RESP_W::new(self) + } + #[doc = "Bits 4:5 - Negative channel resistor control"] + #[inline(always)] + pub fn resn(&mut self) -> RESN_W<4> { + RESN_W::new(self) + } + #[doc = "Bits 8:10 - Gain control"] + #[inline(always)] + pub fn gain(&mut self) -> GAIN_W<8> { + GAIN_W::new(self) + } + #[doc = "Bit 12 - Reference control"] + #[inline(always)] + pub fn refsel(&mut self) -> REFSEL_W<12> { + REFSEL_W::new(self) + } + #[doc = "Bits 16:18 - Acquisition time, the time the ADC uses to sample the input voltage"] + #[inline(always)] + pub fn tacq(&mut self) -> TACQ_W<16> { + TACQ_W::new(self) + } + #[doc = "Bit 20 - Enable differential mode"] + #[inline(always)] + pub fn mode(&mut self) -> MODE_W<20> { + MODE_W::new(self) + } + #[doc = "Bit 24 - Enable burst mode"] + #[inline(always)] + pub fn burst(&mut self) -> BURST_W<24> { + BURST_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Description cluster: Input configuration for CH\\[n\\]\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [config](index.html) module"] +pub struct CONFIG_SPEC; +impl crate::RegisterSpec for CONFIG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [config::R](R) reader structure"] +impl crate::Readable for CONFIG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [config::W](W) writer structure"] +impl crate::Writable for CONFIG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CONFIG to value 0x0002_0000"] +impl crate::Resettable for CONFIG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x0002_0000 + } +} diff --git a/pacs/nrf9120-pac/src/saadc_ns/ch/limit.rs b/pacs/nrf9120-pac/src/saadc_ns/ch/limit.rs new file mode 100644 index 00000000..c0c3bf38 --- /dev/null +++ b/pacs/nrf9120-pac/src/saadc_ns/ch/limit.rs @@ -0,0 +1,94 @@ +#[doc = "Register `LIMIT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `LIMIT` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `LOW` reader - Low level limit"] +pub type LOW_R = crate::FieldReader; +#[doc = "Field `LOW` writer - Low level limit"] +pub type LOW_W<'a, const O: u8> = crate::FieldWriter<'a, u32, LIMIT_SPEC, u16, u16, 16, O>; +#[doc = "Field `HIGH` reader - High level limit"] +pub type HIGH_R = crate::FieldReader; +#[doc = "Field `HIGH` writer - High level limit"] +pub type HIGH_W<'a, const O: u8> = crate::FieldWriter<'a, u32, LIMIT_SPEC, u16, u16, 16, O>; +impl R { + #[doc = "Bits 0:15 - Low level limit"] + #[inline(always)] + pub fn low(&self) -> LOW_R { + LOW_R::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:31 - High level limit"] + #[inline(always)] + pub fn high(&self) -> HIGH_R { + HIGH_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Low level limit"] + #[inline(always)] + pub fn low(&mut self) -> LOW_W<0> { + LOW_W::new(self) + } + #[doc = "Bits 16:31 - High level limit"] + #[inline(always)] + pub fn high(&mut self) -> HIGH_W<16> { + HIGH_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Description cluster: High/low limits for event monitoring a channel\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [limit](index.html) module"] +pub struct LIMIT_SPEC; +impl crate::RegisterSpec for LIMIT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [limit::R](R) reader structure"] +impl crate::Readable for LIMIT_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [limit::W](W) writer structure"] +impl crate::Writable for LIMIT_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets LIMIT to value 0x7fff_8000"] +impl crate::Resettable for LIMIT_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x7fff_8000 + } +} diff --git a/pacs/nrf9120-pac/src/saadc_ns/ch/pseln.rs b/pacs/nrf9120-pac/src/saadc_ns/ch/pseln.rs new file mode 100644 index 00000000..c7ea87e4 --- /dev/null +++ b/pacs/nrf9120-pac/src/saadc_ns/ch/pseln.rs @@ -0,0 +1,232 @@ +#[doc = "Register `PSELN` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PSELN` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PSELN` reader - Analog negative input, enables differential channel"] +pub type PSELN_R = crate::FieldReader; +#[doc = "Analog negative input, enables differential channel\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum PSELN_A { + #[doc = "0: Not connected"] + NC = 0, + #[doc = "1: AIN0"] + ANALOG_INPUT0 = 1, + #[doc = "2: AIN1"] + ANALOG_INPUT1 = 2, + #[doc = "3: AIN2"] + ANALOG_INPUT2 = 3, + #[doc = "4: AIN3"] + ANALOG_INPUT3 = 4, + #[doc = "5: AIN4"] + ANALOG_INPUT4 = 5, + #[doc = "6: AIN5"] + ANALOG_INPUT5 = 6, + #[doc = "7: AIN6"] + ANALOG_INPUT6 = 7, + #[doc = "8: AIN7"] + ANALOG_INPUT7 = 8, + #[doc = "9: VDD_GPIO"] + VDD_GPIO = 9, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PSELN_A) -> Self { + variant as _ + } +} +impl PSELN_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(PSELN_A::NC), + 1 => Some(PSELN_A::ANALOG_INPUT0), + 2 => Some(PSELN_A::ANALOG_INPUT1), + 3 => Some(PSELN_A::ANALOG_INPUT2), + 4 => Some(PSELN_A::ANALOG_INPUT3), + 5 => Some(PSELN_A::ANALOG_INPUT4), + 6 => Some(PSELN_A::ANALOG_INPUT5), + 7 => Some(PSELN_A::ANALOG_INPUT6), + 8 => Some(PSELN_A::ANALOG_INPUT7), + 9 => Some(PSELN_A::VDD_GPIO), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NC`"] + #[inline(always)] + pub fn is_nc(&self) -> bool { + *self == PSELN_A::NC + } + #[doc = "Checks if the value of the field is `ANALOG_INPUT0`"] + #[inline(always)] + pub fn is_analog_input0(&self) -> bool { + *self == PSELN_A::ANALOG_INPUT0 + } + #[doc = "Checks if the value of the field is `ANALOG_INPUT1`"] + #[inline(always)] + pub fn is_analog_input1(&self) -> bool { + *self == PSELN_A::ANALOG_INPUT1 + } + #[doc = "Checks if the value of the field is `ANALOG_INPUT2`"] + #[inline(always)] + pub fn is_analog_input2(&self) -> bool { + *self == PSELN_A::ANALOG_INPUT2 + } + #[doc = "Checks if the value of the field is `ANALOG_INPUT3`"] + #[inline(always)] + pub fn is_analog_input3(&self) -> bool { + *self == PSELN_A::ANALOG_INPUT3 + } + #[doc = "Checks if the value of the field is `ANALOG_INPUT4`"] + #[inline(always)] + pub fn is_analog_input4(&self) -> bool { + *self == PSELN_A::ANALOG_INPUT4 + } + #[doc = "Checks if the value of the field is `ANALOG_INPUT5`"] + #[inline(always)] + pub fn is_analog_input5(&self) -> bool { + *self == PSELN_A::ANALOG_INPUT5 + } + #[doc = "Checks if the value of the field is `ANALOG_INPUT6`"] + #[inline(always)] + pub fn is_analog_input6(&self) -> bool { + *self == PSELN_A::ANALOG_INPUT6 + } + #[doc = "Checks if the value of the field is `ANALOG_INPUT7`"] + #[inline(always)] + pub fn is_analog_input7(&self) -> bool { + *self == PSELN_A::ANALOG_INPUT7 + } + #[doc = "Checks if the value of the field is `VDD_GPIO`"] + #[inline(always)] + pub fn is_vdd_gpio(&self) -> bool { + *self == PSELN_A::VDD_GPIO + } +} +#[doc = "Field `PSELN` writer - Analog negative input, enables differential channel"] +pub type PSELN_W<'a, const O: u8> = crate::FieldWriter<'a, u32, PSELN_SPEC, u8, PSELN_A, 5, O>; +impl<'a, const O: u8> PSELN_W<'a, O> { + #[doc = "Not connected"] + #[inline(always)] + pub fn nc(self) -> &'a mut W { + self.variant(PSELN_A::NC) + } + #[doc = "AIN0"] + #[inline(always)] + pub fn analog_input0(self) -> &'a mut W { + self.variant(PSELN_A::ANALOG_INPUT0) + } + #[doc = "AIN1"] + #[inline(always)] + pub fn analog_input1(self) -> &'a mut W { + self.variant(PSELN_A::ANALOG_INPUT1) + } + #[doc = "AIN2"] + #[inline(always)] + pub fn analog_input2(self) -> &'a mut W { + self.variant(PSELN_A::ANALOG_INPUT2) + } + #[doc = "AIN3"] + #[inline(always)] + pub fn analog_input3(self) -> &'a mut W { + self.variant(PSELN_A::ANALOG_INPUT3) + } + #[doc = "AIN4"] + #[inline(always)] + pub fn analog_input4(self) -> &'a mut W { + self.variant(PSELN_A::ANALOG_INPUT4) + } + #[doc = "AIN5"] + #[inline(always)] + pub fn analog_input5(self) -> &'a mut W { + self.variant(PSELN_A::ANALOG_INPUT5) + } + #[doc = "AIN6"] + #[inline(always)] + pub fn analog_input6(self) -> &'a mut W { + self.variant(PSELN_A::ANALOG_INPUT6) + } + #[doc = "AIN7"] + #[inline(always)] + pub fn analog_input7(self) -> &'a mut W { + self.variant(PSELN_A::ANALOG_INPUT7) + } + #[doc = "VDD_GPIO"] + #[inline(always)] + pub fn vdd_gpio(self) -> &'a mut W { + self.variant(PSELN_A::VDD_GPIO) + } +} +impl R { + #[doc = "Bits 0:4 - Analog negative input, enables differential channel"] + #[inline(always)] + pub fn pseln(&self) -> PSELN_R { + PSELN_R::new((self.bits & 0x1f) as u8) + } +} +impl W { + #[doc = "Bits 0:4 - Analog negative input, enables differential channel"] + #[inline(always)] + pub fn pseln(&mut self) -> PSELN_W<0> { + PSELN_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Description cluster: Input negative pin selection for CH\\[n\\]\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pseln](index.html) module"] +pub struct PSELN_SPEC; +impl crate::RegisterSpec for PSELN_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pseln::R](R) reader structure"] +impl crate::Readable for PSELN_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [pseln::W](W) writer structure"] +impl crate::Writable for PSELN_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PSELN to value 0"] +impl crate::Resettable for PSELN_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/saadc_ns/ch/pselp.rs b/pacs/nrf9120-pac/src/saadc_ns/ch/pselp.rs new file mode 100644 index 00000000..008904d3 --- /dev/null +++ b/pacs/nrf9120-pac/src/saadc_ns/ch/pselp.rs @@ -0,0 +1,232 @@ +#[doc = "Register `PSELP` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PSELP` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PSELP` reader - Analog positive input channel"] +pub type PSELP_R = crate::FieldReader; +#[doc = "Analog positive input channel\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum PSELP_A { + #[doc = "0: Not connected"] + NC = 0, + #[doc = "1: AIN0"] + ANALOG_INPUT0 = 1, + #[doc = "2: AIN1"] + ANALOG_INPUT1 = 2, + #[doc = "3: AIN2"] + ANALOG_INPUT2 = 3, + #[doc = "4: AIN3"] + ANALOG_INPUT3 = 4, + #[doc = "5: AIN4"] + ANALOG_INPUT4 = 5, + #[doc = "6: AIN5"] + ANALOG_INPUT5 = 6, + #[doc = "7: AIN6"] + ANALOG_INPUT6 = 7, + #[doc = "8: AIN7"] + ANALOG_INPUT7 = 8, + #[doc = "9: VDD_GPIO"] + VDDGPIO = 9, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PSELP_A) -> Self { + variant as _ + } +} +impl PSELP_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(PSELP_A::NC), + 1 => Some(PSELP_A::ANALOG_INPUT0), + 2 => Some(PSELP_A::ANALOG_INPUT1), + 3 => Some(PSELP_A::ANALOG_INPUT2), + 4 => Some(PSELP_A::ANALOG_INPUT3), + 5 => Some(PSELP_A::ANALOG_INPUT4), + 6 => Some(PSELP_A::ANALOG_INPUT5), + 7 => Some(PSELP_A::ANALOG_INPUT6), + 8 => Some(PSELP_A::ANALOG_INPUT7), + 9 => Some(PSELP_A::VDDGPIO), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NC`"] + #[inline(always)] + pub fn is_nc(&self) -> bool { + *self == PSELP_A::NC + } + #[doc = "Checks if the value of the field is `ANALOG_INPUT0`"] + #[inline(always)] + pub fn is_analog_input0(&self) -> bool { + *self == PSELP_A::ANALOG_INPUT0 + } + #[doc = "Checks if the value of the field is `ANALOG_INPUT1`"] + #[inline(always)] + pub fn is_analog_input1(&self) -> bool { + *self == PSELP_A::ANALOG_INPUT1 + } + #[doc = "Checks if the value of the field is `ANALOG_INPUT2`"] + #[inline(always)] + pub fn is_analog_input2(&self) -> bool { + *self == PSELP_A::ANALOG_INPUT2 + } + #[doc = "Checks if the value of the field is `ANALOG_INPUT3`"] + #[inline(always)] + pub fn is_analog_input3(&self) -> bool { + *self == PSELP_A::ANALOG_INPUT3 + } + #[doc = "Checks if the value of the field is `ANALOG_INPUT4`"] + #[inline(always)] + pub fn is_analog_input4(&self) -> bool { + *self == PSELP_A::ANALOG_INPUT4 + } + #[doc = "Checks if the value of the field is `ANALOG_INPUT5`"] + #[inline(always)] + pub fn is_analog_input5(&self) -> bool { + *self == PSELP_A::ANALOG_INPUT5 + } + #[doc = "Checks if the value of the field is `ANALOG_INPUT6`"] + #[inline(always)] + pub fn is_analog_input6(&self) -> bool { + *self == PSELP_A::ANALOG_INPUT6 + } + #[doc = "Checks if the value of the field is `ANALOG_INPUT7`"] + #[inline(always)] + pub fn is_analog_input7(&self) -> bool { + *self == PSELP_A::ANALOG_INPUT7 + } + #[doc = "Checks if the value of the field is `VDDGPIO`"] + #[inline(always)] + pub fn is_vddgpio(&self) -> bool { + *self == PSELP_A::VDDGPIO + } +} +#[doc = "Field `PSELP` writer - Analog positive input channel"] +pub type PSELP_W<'a, const O: u8> = crate::FieldWriter<'a, u32, PSELP_SPEC, u8, PSELP_A, 5, O>; +impl<'a, const O: u8> PSELP_W<'a, O> { + #[doc = "Not connected"] + #[inline(always)] + pub fn nc(self) -> &'a mut W { + self.variant(PSELP_A::NC) + } + #[doc = "AIN0"] + #[inline(always)] + pub fn analog_input0(self) -> &'a mut W { + self.variant(PSELP_A::ANALOG_INPUT0) + } + #[doc = "AIN1"] + #[inline(always)] + pub fn analog_input1(self) -> &'a mut W { + self.variant(PSELP_A::ANALOG_INPUT1) + } + #[doc = "AIN2"] + #[inline(always)] + pub fn analog_input2(self) -> &'a mut W { + self.variant(PSELP_A::ANALOG_INPUT2) + } + #[doc = "AIN3"] + #[inline(always)] + pub fn analog_input3(self) -> &'a mut W { + self.variant(PSELP_A::ANALOG_INPUT3) + } + #[doc = "AIN4"] + #[inline(always)] + pub fn analog_input4(self) -> &'a mut W { + self.variant(PSELP_A::ANALOG_INPUT4) + } + #[doc = "AIN5"] + #[inline(always)] + pub fn analog_input5(self) -> &'a mut W { + self.variant(PSELP_A::ANALOG_INPUT5) + } + #[doc = "AIN6"] + #[inline(always)] + pub fn analog_input6(self) -> &'a mut W { + self.variant(PSELP_A::ANALOG_INPUT6) + } + #[doc = "AIN7"] + #[inline(always)] + pub fn analog_input7(self) -> &'a mut W { + self.variant(PSELP_A::ANALOG_INPUT7) + } + #[doc = "VDD_GPIO"] + #[inline(always)] + pub fn vddgpio(self) -> &'a mut W { + self.variant(PSELP_A::VDDGPIO) + } +} +impl R { + #[doc = "Bits 0:4 - Analog positive input channel"] + #[inline(always)] + pub fn pselp(&self) -> PSELP_R { + PSELP_R::new((self.bits & 0x1f) as u8) + } +} +impl W { + #[doc = "Bits 0:4 - Analog positive input channel"] + #[inline(always)] + pub fn pselp(&mut self) -> PSELP_W<0> { + PSELP_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Description cluster: Input positive pin selection for CH\\[n\\]\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pselp](index.html) module"] +pub struct PSELP_SPEC; +impl crate::RegisterSpec for PSELP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pselp::R](R) reader structure"] +impl crate::Readable for PSELP_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [pselp::W](W) writer structure"] +impl crate::Writable for PSELP_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PSELP to value 0"] +impl crate::Resettable for PSELP_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/saadc_ns/enable.rs b/pacs/nrf9120-pac/src/saadc_ns/enable.rs new file mode 100644 index 00000000..8d8473c0 --- /dev/null +++ b/pacs/nrf9120-pac/src/saadc_ns/enable.rs @@ -0,0 +1,126 @@ +#[doc = "Register `ENABLE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `ENABLE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ENABLE` reader - Enable or disable ADC"] +pub type ENABLE_R = crate::BitReader; +#[doc = "Enable or disable ADC\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum ENABLE_A { + #[doc = "0: Disable ADC"] + DISABLED = 0, + #[doc = "1: Enable ADC"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: ENABLE_A) -> Self { + variant as u8 != 0 + } +} +impl ENABLE_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> ENABLE_A { + match self.bits { + false => ENABLE_A::DISABLED, + true => ENABLE_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == ENABLE_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == ENABLE_A::ENABLED + } +} +#[doc = "Field `ENABLE` writer - Enable or disable ADC"] +pub type ENABLE_W<'a, const O: u8> = crate::BitWriter<'a, u32, ENABLE_SPEC, ENABLE_A, O>; +impl<'a, const O: u8> ENABLE_W<'a, O> { + #[doc = "Disable ADC"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(ENABLE_A::DISABLED) + } + #[doc = "Enable ADC"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(ENABLE_A::ENABLED) + } +} +impl R { + #[doc = "Bit 0 - Enable or disable ADC"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new((self.bits & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Enable or disable ADC"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W<0> { + ENABLE_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Enable or disable ADC\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [enable](index.html) module"] +pub struct ENABLE_SPEC; +impl crate::RegisterSpec for ENABLE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [enable::R](R) reader structure"] +impl crate::Readable for ENABLE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [enable::W](W) writer structure"] +impl crate::Writable for ENABLE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets ENABLE to value 0"] +impl crate::Resettable for ENABLE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/saadc_ns/events_calibratedone.rs b/pacs/nrf9120-pac/src/saadc_ns/events_calibratedone.rs new file mode 100644 index 00000000..5ee19a5d --- /dev/null +++ b/pacs/nrf9120-pac/src/saadc_ns/events_calibratedone.rs @@ -0,0 +1,127 @@ +#[doc = "Register `EVENTS_CALIBRATEDONE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVENTS_CALIBRATEDONE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `EVENTS_CALIBRATEDONE` reader - Calibration is complete"] +pub type EVENTS_CALIBRATEDONE_R = crate::BitReader; +#[doc = "Calibration is complete\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum EVENTS_CALIBRATEDONE_A { + #[doc = "0: Event not generated"] + NOT_GENERATED = 0, + #[doc = "1: Event generated"] + GENERATED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: EVENTS_CALIBRATEDONE_A) -> Self { + variant as u8 != 0 + } +} +impl EVENTS_CALIBRATEDONE_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EVENTS_CALIBRATEDONE_A { + match self.bits { + false => EVENTS_CALIBRATEDONE_A::NOT_GENERATED, + true => EVENTS_CALIBRATEDONE_A::GENERATED, + } + } + #[doc = "Checks if the value of the field is `NOT_GENERATED`"] + #[inline(always)] + pub fn is_not_generated(&self) -> bool { + *self == EVENTS_CALIBRATEDONE_A::NOT_GENERATED + } + #[doc = "Checks if the value of the field is `GENERATED`"] + #[inline(always)] + pub fn is_generated(&self) -> bool { + *self == EVENTS_CALIBRATEDONE_A::GENERATED + } +} +#[doc = "Field `EVENTS_CALIBRATEDONE` writer - Calibration is complete"] +pub type EVENTS_CALIBRATEDONE_W<'a, const O: u8> = + crate::BitWriter<'a, u32, EVENTS_CALIBRATEDONE_SPEC, EVENTS_CALIBRATEDONE_A, O>; +impl<'a, const O: u8> EVENTS_CALIBRATEDONE_W<'a, O> { + #[doc = "Event not generated"] + #[inline(always)] + pub fn not_generated(self) -> &'a mut W { + self.variant(EVENTS_CALIBRATEDONE_A::NOT_GENERATED) + } + #[doc = "Event generated"] + #[inline(always)] + pub fn generated(self) -> &'a mut W { + self.variant(EVENTS_CALIBRATEDONE_A::GENERATED) + } +} +impl R { + #[doc = "Bit 0 - Calibration is complete"] + #[inline(always)] + pub fn events_calibratedone(&self) -> EVENTS_CALIBRATEDONE_R { + EVENTS_CALIBRATEDONE_R::new((self.bits & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Calibration is complete"] + #[inline(always)] + pub fn events_calibratedone(&mut self) -> EVENTS_CALIBRATEDONE_W<0> { + EVENTS_CALIBRATEDONE_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Calibration is complete\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [events_calibratedone](index.html) module"] +pub struct EVENTS_CALIBRATEDONE_SPEC; +impl crate::RegisterSpec for EVENTS_CALIBRATEDONE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [events_calibratedone::R](R) reader structure"] +impl crate::Readable for EVENTS_CALIBRATEDONE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [events_calibratedone::W](W) writer structure"] +impl crate::Writable for EVENTS_CALIBRATEDONE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EVENTS_CALIBRATEDONE to value 0"] +impl crate::Resettable for EVENTS_CALIBRATEDONE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/saadc_ns/events_ch.rs b/pacs/nrf9120-pac/src/saadc_ns/events_ch.rs new file mode 100644 index 00000000..e1e19cf7 --- /dev/null +++ b/pacs/nrf9120-pac/src/saadc_ns/events_ch.rs @@ -0,0 +1,16 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct EVENTS_CH { + #[doc = "0x00 - Description cluster: Last results is equal or above CH\\[n\\].LIMIT.HIGH"] + pub limith: LIMITH, + #[doc = "0x04 - Description cluster: Last results is equal or below CH\\[n\\].LIMIT.LOW"] + pub limitl: LIMITL, +} +#[doc = "LIMITH (rw) register accessor: an alias for `Reg`"] +pub type LIMITH = crate::Reg; +#[doc = "Description cluster: Last results is equal or above CH\\[n\\].LIMIT.HIGH"] +pub mod limith; +#[doc = "LIMITL (rw) register accessor: an alias for `Reg`"] +pub type LIMITL = crate::Reg; +#[doc = "Description cluster: Last results is equal or below CH\\[n\\].LIMIT.LOW"] +pub mod limitl; diff --git a/pacs/nrf9120-pac/src/saadc_ns/events_ch/limith.rs b/pacs/nrf9120-pac/src/saadc_ns/events_ch/limith.rs new file mode 100644 index 00000000..ac838d20 --- /dev/null +++ b/pacs/nrf9120-pac/src/saadc_ns/events_ch/limith.rs @@ -0,0 +1,126 @@ +#[doc = "Register `LIMITH` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `LIMITH` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `LIMITH` reader - Last results is equal or above CH\\[n\\].LIMIT.HIGH"] +pub type LIMITH_R = crate::BitReader; +#[doc = "Last results is equal or above CH\\[n\\].LIMIT.HIGH\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum LIMITH_A { + #[doc = "0: Event not generated"] + NOT_GENERATED = 0, + #[doc = "1: Event generated"] + GENERATED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: LIMITH_A) -> Self { + variant as u8 != 0 + } +} +impl LIMITH_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> LIMITH_A { + match self.bits { + false => LIMITH_A::NOT_GENERATED, + true => LIMITH_A::GENERATED, + } + } + #[doc = "Checks if the value of the field is `NOT_GENERATED`"] + #[inline(always)] + pub fn is_not_generated(&self) -> bool { + *self == LIMITH_A::NOT_GENERATED + } + #[doc = "Checks if the value of the field is `GENERATED`"] + #[inline(always)] + pub fn is_generated(&self) -> bool { + *self == LIMITH_A::GENERATED + } +} +#[doc = "Field `LIMITH` writer - Last results is equal or above CH\\[n\\].LIMIT.HIGH"] +pub type LIMITH_W<'a, const O: u8> = crate::BitWriter<'a, u32, LIMITH_SPEC, LIMITH_A, O>; +impl<'a, const O: u8> LIMITH_W<'a, O> { + #[doc = "Event not generated"] + #[inline(always)] + pub fn not_generated(self) -> &'a mut W { + self.variant(LIMITH_A::NOT_GENERATED) + } + #[doc = "Event generated"] + #[inline(always)] + pub fn generated(self) -> &'a mut W { + self.variant(LIMITH_A::GENERATED) + } +} +impl R { + #[doc = "Bit 0 - Last results is equal or above CH\\[n\\].LIMIT.HIGH"] + #[inline(always)] + pub fn limith(&self) -> LIMITH_R { + LIMITH_R::new((self.bits & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Last results is equal or above CH\\[n\\].LIMIT.HIGH"] + #[inline(always)] + pub fn limith(&mut self) -> LIMITH_W<0> { + LIMITH_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Description cluster: Last results is equal or above CH\\[n\\].LIMIT.HIGH\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [limith](index.html) module"] +pub struct LIMITH_SPEC; +impl crate::RegisterSpec for LIMITH_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [limith::R](R) reader structure"] +impl crate::Readable for LIMITH_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [limith::W](W) writer structure"] +impl crate::Writable for LIMITH_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets LIMITH to value 0"] +impl crate::Resettable for LIMITH_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/saadc_ns/events_ch/limitl.rs b/pacs/nrf9120-pac/src/saadc_ns/events_ch/limitl.rs new file mode 100644 index 00000000..09e8c60c --- /dev/null +++ b/pacs/nrf9120-pac/src/saadc_ns/events_ch/limitl.rs @@ -0,0 +1,126 @@ +#[doc = "Register `LIMITL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `LIMITL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `LIMITL` reader - Last results is equal or below CH\\[n\\].LIMIT.LOW"] +pub type LIMITL_R = crate::BitReader; +#[doc = "Last results is equal or below CH\\[n\\].LIMIT.LOW\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum LIMITL_A { + #[doc = "0: Event not generated"] + NOT_GENERATED = 0, + #[doc = "1: Event generated"] + GENERATED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: LIMITL_A) -> Self { + variant as u8 != 0 + } +} +impl LIMITL_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> LIMITL_A { + match self.bits { + false => LIMITL_A::NOT_GENERATED, + true => LIMITL_A::GENERATED, + } + } + #[doc = "Checks if the value of the field is `NOT_GENERATED`"] + #[inline(always)] + pub fn is_not_generated(&self) -> bool { + *self == LIMITL_A::NOT_GENERATED + } + #[doc = "Checks if the value of the field is `GENERATED`"] + #[inline(always)] + pub fn is_generated(&self) -> bool { + *self == LIMITL_A::GENERATED + } +} +#[doc = "Field `LIMITL` writer - Last results is equal or below CH\\[n\\].LIMIT.LOW"] +pub type LIMITL_W<'a, const O: u8> = crate::BitWriter<'a, u32, LIMITL_SPEC, LIMITL_A, O>; +impl<'a, const O: u8> LIMITL_W<'a, O> { + #[doc = "Event not generated"] + #[inline(always)] + pub fn not_generated(self) -> &'a mut W { + self.variant(LIMITL_A::NOT_GENERATED) + } + #[doc = "Event generated"] + #[inline(always)] + pub fn generated(self) -> &'a mut W { + self.variant(LIMITL_A::GENERATED) + } +} +impl R { + #[doc = "Bit 0 - Last results is equal or below CH\\[n\\].LIMIT.LOW"] + #[inline(always)] + pub fn limitl(&self) -> LIMITL_R { + LIMITL_R::new((self.bits & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Last results is equal or below CH\\[n\\].LIMIT.LOW"] + #[inline(always)] + pub fn limitl(&mut self) -> LIMITL_W<0> { + LIMITL_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Description cluster: Last results is equal or below CH\\[n\\].LIMIT.LOW\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [limitl](index.html) module"] +pub struct LIMITL_SPEC; +impl crate::RegisterSpec for LIMITL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [limitl::R](R) reader structure"] +impl crate::Readable for LIMITL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [limitl::W](W) writer structure"] +impl crate::Writable for LIMITL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets LIMITL to value 0"] +impl crate::Resettable for LIMITL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/saadc_ns/events_done.rs b/pacs/nrf9120-pac/src/saadc_ns/events_done.rs new file mode 100644 index 00000000..998948b4 --- /dev/null +++ b/pacs/nrf9120-pac/src/saadc_ns/events_done.rs @@ -0,0 +1,127 @@ +#[doc = "Register `EVENTS_DONE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVENTS_DONE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `EVENTS_DONE` reader - A conversion task has been completed. Depending on the mode, multiple conversions might be needed for a result to be transferred to RAM."] +pub type EVENTS_DONE_R = crate::BitReader; +#[doc = "A conversion task has been completed. Depending on the mode, multiple conversions might be needed for a result to be transferred to RAM.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum EVENTS_DONE_A { + #[doc = "0: Event not generated"] + NOT_GENERATED = 0, + #[doc = "1: Event generated"] + GENERATED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: EVENTS_DONE_A) -> Self { + variant as u8 != 0 + } +} +impl EVENTS_DONE_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EVENTS_DONE_A { + match self.bits { + false => EVENTS_DONE_A::NOT_GENERATED, + true => EVENTS_DONE_A::GENERATED, + } + } + #[doc = "Checks if the value of the field is `NOT_GENERATED`"] + #[inline(always)] + pub fn is_not_generated(&self) -> bool { + *self == EVENTS_DONE_A::NOT_GENERATED + } + #[doc = "Checks if the value of the field is `GENERATED`"] + #[inline(always)] + pub fn is_generated(&self) -> bool { + *self == EVENTS_DONE_A::GENERATED + } +} +#[doc = "Field `EVENTS_DONE` writer - A conversion task has been completed. Depending on the mode, multiple conversions might be needed for a result to be transferred to RAM."] +pub type EVENTS_DONE_W<'a, const O: u8> = + crate::BitWriter<'a, u32, EVENTS_DONE_SPEC, EVENTS_DONE_A, O>; +impl<'a, const O: u8> EVENTS_DONE_W<'a, O> { + #[doc = "Event not generated"] + #[inline(always)] + pub fn not_generated(self) -> &'a mut W { + self.variant(EVENTS_DONE_A::NOT_GENERATED) + } + #[doc = "Event generated"] + #[inline(always)] + pub fn generated(self) -> &'a mut W { + self.variant(EVENTS_DONE_A::GENERATED) + } +} +impl R { + #[doc = "Bit 0 - A conversion task has been completed. Depending on the mode, multiple conversions might be needed for a result to be transferred to RAM."] + #[inline(always)] + pub fn events_done(&self) -> EVENTS_DONE_R { + EVENTS_DONE_R::new((self.bits & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - A conversion task has been completed. Depending on the mode, multiple conversions might be needed for a result to be transferred to RAM."] + #[inline(always)] + pub fn events_done(&mut self) -> EVENTS_DONE_W<0> { + EVENTS_DONE_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "A conversion task has been completed. Depending on the mode, multiple conversions might be needed for a result to be transferred to RAM.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [events_done](index.html) module"] +pub struct EVENTS_DONE_SPEC; +impl crate::RegisterSpec for EVENTS_DONE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [events_done::R](R) reader structure"] +impl crate::Readable for EVENTS_DONE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [events_done::W](W) writer structure"] +impl crate::Writable for EVENTS_DONE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EVENTS_DONE to value 0"] +impl crate::Resettable for EVENTS_DONE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/saadc_ns/events_end.rs b/pacs/nrf9120-pac/src/saadc_ns/events_end.rs new file mode 100644 index 00000000..54a97c10 --- /dev/null +++ b/pacs/nrf9120-pac/src/saadc_ns/events_end.rs @@ -0,0 +1,127 @@ +#[doc = "Register `EVENTS_END` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVENTS_END` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `EVENTS_END` reader - The ADC has filled up the Result buffer"] +pub type EVENTS_END_R = crate::BitReader; +#[doc = "The ADC has filled up the Result buffer\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum EVENTS_END_A { + #[doc = "0: Event not generated"] + NOT_GENERATED = 0, + #[doc = "1: Event generated"] + GENERATED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: EVENTS_END_A) -> Self { + variant as u8 != 0 + } +} +impl EVENTS_END_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EVENTS_END_A { + match self.bits { + false => EVENTS_END_A::NOT_GENERATED, + true => EVENTS_END_A::GENERATED, + } + } + #[doc = "Checks if the value of the field is `NOT_GENERATED`"] + #[inline(always)] + pub fn is_not_generated(&self) -> bool { + *self == EVENTS_END_A::NOT_GENERATED + } + #[doc = "Checks if the value of the field is `GENERATED`"] + #[inline(always)] + pub fn is_generated(&self) -> bool { + *self == EVENTS_END_A::GENERATED + } +} +#[doc = "Field `EVENTS_END` writer - The ADC has filled up the Result buffer"] +pub type EVENTS_END_W<'a, const O: u8> = + crate::BitWriter<'a, u32, EVENTS_END_SPEC, EVENTS_END_A, O>; +impl<'a, const O: u8> EVENTS_END_W<'a, O> { + #[doc = "Event not generated"] + #[inline(always)] + pub fn not_generated(self) -> &'a mut W { + self.variant(EVENTS_END_A::NOT_GENERATED) + } + #[doc = "Event generated"] + #[inline(always)] + pub fn generated(self) -> &'a mut W { + self.variant(EVENTS_END_A::GENERATED) + } +} +impl R { + #[doc = "Bit 0 - The ADC has filled up the Result buffer"] + #[inline(always)] + pub fn events_end(&self) -> EVENTS_END_R { + EVENTS_END_R::new((self.bits & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - The ADC has filled up the Result buffer"] + #[inline(always)] + pub fn events_end(&mut self) -> EVENTS_END_W<0> { + EVENTS_END_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "The ADC has filled up the Result buffer\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [events_end](index.html) module"] +pub struct EVENTS_END_SPEC; +impl crate::RegisterSpec for EVENTS_END_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [events_end::R](R) reader structure"] +impl crate::Readable for EVENTS_END_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [events_end::W](W) writer structure"] +impl crate::Writable for EVENTS_END_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EVENTS_END to value 0"] +impl crate::Resettable for EVENTS_END_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/saadc_ns/events_resultdone.rs b/pacs/nrf9120-pac/src/saadc_ns/events_resultdone.rs new file mode 100644 index 00000000..b370e593 --- /dev/null +++ b/pacs/nrf9120-pac/src/saadc_ns/events_resultdone.rs @@ -0,0 +1,127 @@ +#[doc = "Register `EVENTS_RESULTDONE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVENTS_RESULTDONE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `EVENTS_RESULTDONE` reader - A result is ready to get transferred to RAM."] +pub type EVENTS_RESULTDONE_R = crate::BitReader; +#[doc = "A result is ready to get transferred to RAM.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum EVENTS_RESULTDONE_A { + #[doc = "0: Event not generated"] + NOT_GENERATED = 0, + #[doc = "1: Event generated"] + GENERATED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: EVENTS_RESULTDONE_A) -> Self { + variant as u8 != 0 + } +} +impl EVENTS_RESULTDONE_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EVENTS_RESULTDONE_A { + match self.bits { + false => EVENTS_RESULTDONE_A::NOT_GENERATED, + true => EVENTS_RESULTDONE_A::GENERATED, + } + } + #[doc = "Checks if the value of the field is `NOT_GENERATED`"] + #[inline(always)] + pub fn is_not_generated(&self) -> bool { + *self == EVENTS_RESULTDONE_A::NOT_GENERATED + } + #[doc = "Checks if the value of the field is `GENERATED`"] + #[inline(always)] + pub fn is_generated(&self) -> bool { + *self == EVENTS_RESULTDONE_A::GENERATED + } +} +#[doc = "Field `EVENTS_RESULTDONE` writer - A result is ready to get transferred to RAM."] +pub type EVENTS_RESULTDONE_W<'a, const O: u8> = + crate::BitWriter<'a, u32, EVENTS_RESULTDONE_SPEC, EVENTS_RESULTDONE_A, O>; +impl<'a, const O: u8> EVENTS_RESULTDONE_W<'a, O> { + #[doc = "Event not generated"] + #[inline(always)] + pub fn not_generated(self) -> &'a mut W { + self.variant(EVENTS_RESULTDONE_A::NOT_GENERATED) + } + #[doc = "Event generated"] + #[inline(always)] + pub fn generated(self) -> &'a mut W { + self.variant(EVENTS_RESULTDONE_A::GENERATED) + } +} +impl R { + #[doc = "Bit 0 - A result is ready to get transferred to RAM."] + #[inline(always)] + pub fn events_resultdone(&self) -> EVENTS_RESULTDONE_R { + EVENTS_RESULTDONE_R::new((self.bits & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - A result is ready to get transferred to RAM."] + #[inline(always)] + pub fn events_resultdone(&mut self) -> EVENTS_RESULTDONE_W<0> { + EVENTS_RESULTDONE_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "A result is ready to get transferred to RAM.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [events_resultdone](index.html) module"] +pub struct EVENTS_RESULTDONE_SPEC; +impl crate::RegisterSpec for EVENTS_RESULTDONE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [events_resultdone::R](R) reader structure"] +impl crate::Readable for EVENTS_RESULTDONE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [events_resultdone::W](W) writer structure"] +impl crate::Writable for EVENTS_RESULTDONE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EVENTS_RESULTDONE to value 0"] +impl crate::Resettable for EVENTS_RESULTDONE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/saadc_ns/events_started.rs b/pacs/nrf9120-pac/src/saadc_ns/events_started.rs new file mode 100644 index 00000000..5f5449d8 --- /dev/null +++ b/pacs/nrf9120-pac/src/saadc_ns/events_started.rs @@ -0,0 +1,127 @@ +#[doc = "Register `EVENTS_STARTED` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVENTS_STARTED` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `EVENTS_STARTED` reader - The ADC has started"] +pub type EVENTS_STARTED_R = crate::BitReader; +#[doc = "The ADC has started\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum EVENTS_STARTED_A { + #[doc = "0: Event not generated"] + NOT_GENERATED = 0, + #[doc = "1: Event generated"] + GENERATED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: EVENTS_STARTED_A) -> Self { + variant as u8 != 0 + } +} +impl EVENTS_STARTED_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EVENTS_STARTED_A { + match self.bits { + false => EVENTS_STARTED_A::NOT_GENERATED, + true => EVENTS_STARTED_A::GENERATED, + } + } + #[doc = "Checks if the value of the field is `NOT_GENERATED`"] + #[inline(always)] + pub fn is_not_generated(&self) -> bool { + *self == EVENTS_STARTED_A::NOT_GENERATED + } + #[doc = "Checks if the value of the field is `GENERATED`"] + #[inline(always)] + pub fn is_generated(&self) -> bool { + *self == EVENTS_STARTED_A::GENERATED + } +} +#[doc = "Field `EVENTS_STARTED` writer - The ADC has started"] +pub type EVENTS_STARTED_W<'a, const O: u8> = + crate::BitWriter<'a, u32, EVENTS_STARTED_SPEC, EVENTS_STARTED_A, O>; +impl<'a, const O: u8> EVENTS_STARTED_W<'a, O> { + #[doc = "Event not generated"] + #[inline(always)] + pub fn not_generated(self) -> &'a mut W { + self.variant(EVENTS_STARTED_A::NOT_GENERATED) + } + #[doc = "Event generated"] + #[inline(always)] + pub fn generated(self) -> &'a mut W { + self.variant(EVENTS_STARTED_A::GENERATED) + } +} +impl R { + #[doc = "Bit 0 - The ADC has started"] + #[inline(always)] + pub fn events_started(&self) -> EVENTS_STARTED_R { + EVENTS_STARTED_R::new((self.bits & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - The ADC has started"] + #[inline(always)] + pub fn events_started(&mut self) -> EVENTS_STARTED_W<0> { + EVENTS_STARTED_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "The ADC has started\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [events_started](index.html) module"] +pub struct EVENTS_STARTED_SPEC; +impl crate::RegisterSpec for EVENTS_STARTED_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [events_started::R](R) reader structure"] +impl crate::Readable for EVENTS_STARTED_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [events_started::W](W) writer structure"] +impl crate::Writable for EVENTS_STARTED_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EVENTS_STARTED to value 0"] +impl crate::Resettable for EVENTS_STARTED_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/saadc_ns/events_stopped.rs b/pacs/nrf9120-pac/src/saadc_ns/events_stopped.rs new file mode 100644 index 00000000..14be08c0 --- /dev/null +++ b/pacs/nrf9120-pac/src/saadc_ns/events_stopped.rs @@ -0,0 +1,127 @@ +#[doc = "Register `EVENTS_STOPPED` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVENTS_STOPPED` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `EVENTS_STOPPED` reader - The ADC has stopped"] +pub type EVENTS_STOPPED_R = crate::BitReader; +#[doc = "The ADC has stopped\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum EVENTS_STOPPED_A { + #[doc = "0: Event not generated"] + NOT_GENERATED = 0, + #[doc = "1: Event generated"] + GENERATED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: EVENTS_STOPPED_A) -> Self { + variant as u8 != 0 + } +} +impl EVENTS_STOPPED_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EVENTS_STOPPED_A { + match self.bits { + false => EVENTS_STOPPED_A::NOT_GENERATED, + true => EVENTS_STOPPED_A::GENERATED, + } + } + #[doc = "Checks if the value of the field is `NOT_GENERATED`"] + #[inline(always)] + pub fn is_not_generated(&self) -> bool { + *self == EVENTS_STOPPED_A::NOT_GENERATED + } + #[doc = "Checks if the value of the field is `GENERATED`"] + #[inline(always)] + pub fn is_generated(&self) -> bool { + *self == EVENTS_STOPPED_A::GENERATED + } +} +#[doc = "Field `EVENTS_STOPPED` writer - The ADC has stopped"] +pub type EVENTS_STOPPED_W<'a, const O: u8> = + crate::BitWriter<'a, u32, EVENTS_STOPPED_SPEC, EVENTS_STOPPED_A, O>; +impl<'a, const O: u8> EVENTS_STOPPED_W<'a, O> { + #[doc = "Event not generated"] + #[inline(always)] + pub fn not_generated(self) -> &'a mut W { + self.variant(EVENTS_STOPPED_A::NOT_GENERATED) + } + #[doc = "Event generated"] + #[inline(always)] + pub fn generated(self) -> &'a mut W { + self.variant(EVENTS_STOPPED_A::GENERATED) + } +} +impl R { + #[doc = "Bit 0 - The ADC has stopped"] + #[inline(always)] + pub fn events_stopped(&self) -> EVENTS_STOPPED_R { + EVENTS_STOPPED_R::new((self.bits & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - The ADC has stopped"] + #[inline(always)] + pub fn events_stopped(&mut self) -> EVENTS_STOPPED_W<0> { + EVENTS_STOPPED_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "The ADC has stopped\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [events_stopped](index.html) module"] +pub struct EVENTS_STOPPED_SPEC; +impl crate::RegisterSpec for EVENTS_STOPPED_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [events_stopped::R](R) reader structure"] +impl crate::Readable for EVENTS_STOPPED_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [events_stopped::W](W) writer structure"] +impl crate::Writable for EVENTS_STOPPED_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EVENTS_STOPPED to value 0"] +impl crate::Resettable for EVENTS_STOPPED_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/saadc_ns/inten.rs b/pacs/nrf9120-pac/src/saadc_ns/inten.rs new file mode 100644 index 00000000..dad1b65d --- /dev/null +++ b/pacs/nrf9120-pac/src/saadc_ns/inten.rs @@ -0,0 +1,1387 @@ +#[doc = "Register `INTEN` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTEN` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `STARTED` reader - Enable or disable interrupt for event STARTED"] +pub type STARTED_R = crate::BitReader; +#[doc = "Enable or disable interrupt for event STARTED\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum STARTED_A { + #[doc = "0: Disable"] + DISABLED = 0, + #[doc = "1: Enable"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: STARTED_A) -> Self { + variant as u8 != 0 + } +} +impl STARTED_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> STARTED_A { + match self.bits { + false => STARTED_A::DISABLED, + true => STARTED_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == STARTED_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == STARTED_A::ENABLED + } +} +#[doc = "Field `STARTED` writer - Enable or disable interrupt for event STARTED"] +pub type STARTED_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTEN_SPEC, STARTED_A, O>; +impl<'a, const O: u8> STARTED_W<'a, O> { + #[doc = "Disable"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(STARTED_A::DISABLED) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(STARTED_A::ENABLED) + } +} +#[doc = "Field `END` reader - Enable or disable interrupt for event END"] +pub type END_R = crate::BitReader; +#[doc = "Enable or disable interrupt for event END\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum END_A { + #[doc = "0: Disable"] + DISABLED = 0, + #[doc = "1: Enable"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: END_A) -> Self { + variant as u8 != 0 + } +} +impl END_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> END_A { + match self.bits { + false => END_A::DISABLED, + true => END_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == END_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == END_A::ENABLED + } +} +#[doc = "Field `END` writer - Enable or disable interrupt for event END"] +pub type END_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTEN_SPEC, END_A, O>; +impl<'a, const O: u8> END_W<'a, O> { + #[doc = "Disable"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(END_A::DISABLED) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(END_A::ENABLED) + } +} +#[doc = "Field `DONE` reader - Enable or disable interrupt for event DONE"] +pub type DONE_R = crate::BitReader; +#[doc = "Enable or disable interrupt for event DONE\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum DONE_A { + #[doc = "0: Disable"] + DISABLED = 0, + #[doc = "1: Enable"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: DONE_A) -> Self { + variant as u8 != 0 + } +} +impl DONE_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> DONE_A { + match self.bits { + false => DONE_A::DISABLED, + true => DONE_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == DONE_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == DONE_A::ENABLED + } +} +#[doc = "Field `DONE` writer - Enable or disable interrupt for event DONE"] +pub type DONE_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTEN_SPEC, DONE_A, O>; +impl<'a, const O: u8> DONE_W<'a, O> { + #[doc = "Disable"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(DONE_A::DISABLED) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(DONE_A::ENABLED) + } +} +#[doc = "Field `RESULTDONE` reader - Enable or disable interrupt for event RESULTDONE"] +pub type RESULTDONE_R = crate::BitReader; +#[doc = "Enable or disable interrupt for event RESULTDONE\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RESULTDONE_A { + #[doc = "0: Disable"] + DISABLED = 0, + #[doc = "1: Enable"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RESULTDONE_A) -> Self { + variant as u8 != 0 + } +} +impl RESULTDONE_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RESULTDONE_A { + match self.bits { + false => RESULTDONE_A::DISABLED, + true => RESULTDONE_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == RESULTDONE_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == RESULTDONE_A::ENABLED + } +} +#[doc = "Field `RESULTDONE` writer - Enable or disable interrupt for event RESULTDONE"] +pub type RESULTDONE_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTEN_SPEC, RESULTDONE_A, O>; +impl<'a, const O: u8> RESULTDONE_W<'a, O> { + #[doc = "Disable"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(RESULTDONE_A::DISABLED) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(RESULTDONE_A::ENABLED) + } +} +#[doc = "Field `CALIBRATEDONE` reader - Enable or disable interrupt for event CALIBRATEDONE"] +pub type CALIBRATEDONE_R = crate::BitReader; +#[doc = "Enable or disable interrupt for event CALIBRATEDONE\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CALIBRATEDONE_A { + #[doc = "0: Disable"] + DISABLED = 0, + #[doc = "1: Enable"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CALIBRATEDONE_A) -> Self { + variant as u8 != 0 + } +} +impl CALIBRATEDONE_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CALIBRATEDONE_A { + match self.bits { + false => CALIBRATEDONE_A::DISABLED, + true => CALIBRATEDONE_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == CALIBRATEDONE_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == CALIBRATEDONE_A::ENABLED + } +} +#[doc = "Field `CALIBRATEDONE` writer - Enable or disable interrupt for event CALIBRATEDONE"] +pub type CALIBRATEDONE_W<'a, const O: u8> = + crate::BitWriter<'a, u32, INTEN_SPEC, CALIBRATEDONE_A, O>; +impl<'a, const O: u8> CALIBRATEDONE_W<'a, O> { + #[doc = "Disable"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(CALIBRATEDONE_A::DISABLED) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(CALIBRATEDONE_A::ENABLED) + } +} +#[doc = "Field `STOPPED` reader - Enable or disable interrupt for event STOPPED"] +pub type STOPPED_R = crate::BitReader; +#[doc = "Enable or disable interrupt for event STOPPED\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum STOPPED_A { + #[doc = "0: Disable"] + DISABLED = 0, + #[doc = "1: Enable"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: STOPPED_A) -> Self { + variant as u8 != 0 + } +} +impl STOPPED_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> STOPPED_A { + match self.bits { + false => STOPPED_A::DISABLED, + true => STOPPED_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == STOPPED_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == STOPPED_A::ENABLED + } +} +#[doc = "Field `STOPPED` writer - Enable or disable interrupt for event STOPPED"] +pub type STOPPED_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTEN_SPEC, STOPPED_A, O>; +impl<'a, const O: u8> STOPPED_W<'a, O> { + #[doc = "Disable"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(STOPPED_A::DISABLED) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(STOPPED_A::ENABLED) + } +} +#[doc = "Field `CH0LIMITH` reader - Enable or disable interrupt for event CH0LIMITH"] +pub type CH0LIMITH_R = crate::BitReader; +#[doc = "Enable or disable interrupt for event CH0LIMITH\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CH0LIMITH_A { + #[doc = "0: Disable"] + DISABLED = 0, + #[doc = "1: Enable"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CH0LIMITH_A) -> Self { + variant as u8 != 0 + } +} +impl CH0LIMITH_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CH0LIMITH_A { + match self.bits { + false => CH0LIMITH_A::DISABLED, + true => CH0LIMITH_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == CH0LIMITH_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == CH0LIMITH_A::ENABLED + } +} +#[doc = "Field `CH0LIMITH` writer - Enable or disable interrupt for event CH0LIMITH"] +pub type CH0LIMITH_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTEN_SPEC, CH0LIMITH_A, O>; +impl<'a, const O: u8> CH0LIMITH_W<'a, O> { + #[doc = "Disable"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(CH0LIMITH_A::DISABLED) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(CH0LIMITH_A::ENABLED) + } +} +#[doc = "Field `CH0LIMITL` reader - Enable or disable interrupt for event CH0LIMITL"] +pub type CH0LIMITL_R = crate::BitReader; +#[doc = "Enable or disable interrupt for event CH0LIMITL\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CH0LIMITL_A { + #[doc = "0: Disable"] + DISABLED = 0, + #[doc = "1: Enable"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CH0LIMITL_A) -> Self { + variant as u8 != 0 + } +} +impl CH0LIMITL_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CH0LIMITL_A { + match self.bits { + false => CH0LIMITL_A::DISABLED, + true => CH0LIMITL_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == CH0LIMITL_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == CH0LIMITL_A::ENABLED + } +} +#[doc = "Field `CH0LIMITL` writer - Enable or disable interrupt for event CH0LIMITL"] +pub type CH0LIMITL_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTEN_SPEC, CH0LIMITL_A, O>; +impl<'a, const O: u8> CH0LIMITL_W<'a, O> { + #[doc = "Disable"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(CH0LIMITL_A::DISABLED) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(CH0LIMITL_A::ENABLED) + } +} +#[doc = "Field `CH1LIMITH` reader - Enable or disable interrupt for event CH1LIMITH"] +pub type CH1LIMITH_R = crate::BitReader; +#[doc = "Enable or disable interrupt for event CH1LIMITH\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CH1LIMITH_A { + #[doc = "0: Disable"] + DISABLED = 0, + #[doc = "1: Enable"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CH1LIMITH_A) -> Self { + variant as u8 != 0 + } +} +impl CH1LIMITH_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CH1LIMITH_A { + match self.bits { + false => CH1LIMITH_A::DISABLED, + true => CH1LIMITH_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == CH1LIMITH_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == CH1LIMITH_A::ENABLED + } +} +#[doc = "Field `CH1LIMITH` writer - Enable or disable interrupt for event CH1LIMITH"] +pub type CH1LIMITH_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTEN_SPEC, CH1LIMITH_A, O>; +impl<'a, const O: u8> CH1LIMITH_W<'a, O> { + #[doc = "Disable"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(CH1LIMITH_A::DISABLED) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(CH1LIMITH_A::ENABLED) + } +} +#[doc = "Field `CH1LIMITL` reader - Enable or disable interrupt for event CH1LIMITL"] +pub type CH1LIMITL_R = crate::BitReader; +#[doc = "Enable or disable interrupt for event CH1LIMITL\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CH1LIMITL_A { + #[doc = "0: Disable"] + DISABLED = 0, + #[doc = "1: Enable"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CH1LIMITL_A) -> Self { + variant as u8 != 0 + } +} +impl CH1LIMITL_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CH1LIMITL_A { + match self.bits { + false => CH1LIMITL_A::DISABLED, + true => CH1LIMITL_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == CH1LIMITL_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == CH1LIMITL_A::ENABLED + } +} +#[doc = "Field `CH1LIMITL` writer - Enable or disable interrupt for event CH1LIMITL"] +pub type CH1LIMITL_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTEN_SPEC, CH1LIMITL_A, O>; +impl<'a, const O: u8> CH1LIMITL_W<'a, O> { + #[doc = "Disable"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(CH1LIMITL_A::DISABLED) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(CH1LIMITL_A::ENABLED) + } +} +#[doc = "Field `CH2LIMITH` reader - Enable or disable interrupt for event CH2LIMITH"] +pub type CH2LIMITH_R = crate::BitReader; +#[doc = "Enable or disable interrupt for event CH2LIMITH\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CH2LIMITH_A { + #[doc = "0: Disable"] + DISABLED = 0, + #[doc = "1: Enable"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CH2LIMITH_A) -> Self { + variant as u8 != 0 + } +} +impl CH2LIMITH_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CH2LIMITH_A { + match self.bits { + false => CH2LIMITH_A::DISABLED, + true => CH2LIMITH_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == CH2LIMITH_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == CH2LIMITH_A::ENABLED + } +} +#[doc = "Field `CH2LIMITH` writer - Enable or disable interrupt for event CH2LIMITH"] +pub type CH2LIMITH_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTEN_SPEC, CH2LIMITH_A, O>; +impl<'a, const O: u8> CH2LIMITH_W<'a, O> { + #[doc = "Disable"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(CH2LIMITH_A::DISABLED) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(CH2LIMITH_A::ENABLED) + } +} +#[doc = "Field `CH2LIMITL` reader - Enable or disable interrupt for event CH2LIMITL"] +pub type CH2LIMITL_R = crate::BitReader; +#[doc = "Enable or disable interrupt for event CH2LIMITL\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CH2LIMITL_A { + #[doc = "0: Disable"] + DISABLED = 0, + #[doc = "1: Enable"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CH2LIMITL_A) -> Self { + variant as u8 != 0 + } +} +impl CH2LIMITL_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CH2LIMITL_A { + match self.bits { + false => CH2LIMITL_A::DISABLED, + true => CH2LIMITL_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == CH2LIMITL_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == CH2LIMITL_A::ENABLED + } +} +#[doc = "Field `CH2LIMITL` writer - Enable or disable interrupt for event CH2LIMITL"] +pub type CH2LIMITL_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTEN_SPEC, CH2LIMITL_A, O>; +impl<'a, const O: u8> CH2LIMITL_W<'a, O> { + #[doc = "Disable"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(CH2LIMITL_A::DISABLED) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(CH2LIMITL_A::ENABLED) + } +} +#[doc = "Field `CH3LIMITH` reader - Enable or disable interrupt for event CH3LIMITH"] +pub type CH3LIMITH_R = crate::BitReader; +#[doc = "Enable or disable interrupt for event CH3LIMITH\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CH3LIMITH_A { + #[doc = "0: Disable"] + DISABLED = 0, + #[doc = "1: Enable"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CH3LIMITH_A) -> Self { + variant as u8 != 0 + } +} +impl CH3LIMITH_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CH3LIMITH_A { + match self.bits { + false => CH3LIMITH_A::DISABLED, + true => CH3LIMITH_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == CH3LIMITH_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == CH3LIMITH_A::ENABLED + } +} +#[doc = "Field `CH3LIMITH` writer - Enable or disable interrupt for event CH3LIMITH"] +pub type CH3LIMITH_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTEN_SPEC, CH3LIMITH_A, O>; +impl<'a, const O: u8> CH3LIMITH_W<'a, O> { + #[doc = "Disable"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(CH3LIMITH_A::DISABLED) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(CH3LIMITH_A::ENABLED) + } +} +#[doc = "Field `CH3LIMITL` reader - Enable or disable interrupt for event CH3LIMITL"] +pub type CH3LIMITL_R = crate::BitReader; +#[doc = "Enable or disable interrupt for event CH3LIMITL\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CH3LIMITL_A { + #[doc = "0: Disable"] + DISABLED = 0, + #[doc = "1: Enable"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CH3LIMITL_A) -> Self { + variant as u8 != 0 + } +} +impl CH3LIMITL_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CH3LIMITL_A { + match self.bits { + false => CH3LIMITL_A::DISABLED, + true => CH3LIMITL_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == CH3LIMITL_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == CH3LIMITL_A::ENABLED + } +} +#[doc = "Field `CH3LIMITL` writer - Enable or disable interrupt for event CH3LIMITL"] +pub type CH3LIMITL_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTEN_SPEC, CH3LIMITL_A, O>; +impl<'a, const O: u8> CH3LIMITL_W<'a, O> { + #[doc = "Disable"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(CH3LIMITL_A::DISABLED) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(CH3LIMITL_A::ENABLED) + } +} +#[doc = "Field `CH4LIMITH` reader - Enable or disable interrupt for event CH4LIMITH"] +pub type CH4LIMITH_R = crate::BitReader; +#[doc = "Enable or disable interrupt for event CH4LIMITH\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CH4LIMITH_A { + #[doc = "0: Disable"] + DISABLED = 0, + #[doc = "1: Enable"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CH4LIMITH_A) -> Self { + variant as u8 != 0 + } +} +impl CH4LIMITH_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CH4LIMITH_A { + match self.bits { + false => CH4LIMITH_A::DISABLED, + true => CH4LIMITH_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == CH4LIMITH_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == CH4LIMITH_A::ENABLED + } +} +#[doc = "Field `CH4LIMITH` writer - Enable or disable interrupt for event CH4LIMITH"] +pub type CH4LIMITH_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTEN_SPEC, CH4LIMITH_A, O>; +impl<'a, const O: u8> CH4LIMITH_W<'a, O> { + #[doc = "Disable"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(CH4LIMITH_A::DISABLED) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(CH4LIMITH_A::ENABLED) + } +} +#[doc = "Field `CH4LIMITL` reader - Enable or disable interrupt for event CH4LIMITL"] +pub type CH4LIMITL_R = crate::BitReader; +#[doc = "Enable or disable interrupt for event CH4LIMITL\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CH4LIMITL_A { + #[doc = "0: Disable"] + DISABLED = 0, + #[doc = "1: Enable"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CH4LIMITL_A) -> Self { + variant as u8 != 0 + } +} +impl CH4LIMITL_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CH4LIMITL_A { + match self.bits { + false => CH4LIMITL_A::DISABLED, + true => CH4LIMITL_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == CH4LIMITL_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == CH4LIMITL_A::ENABLED + } +} +#[doc = "Field `CH4LIMITL` writer - Enable or disable interrupt for event CH4LIMITL"] +pub type CH4LIMITL_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTEN_SPEC, CH4LIMITL_A, O>; +impl<'a, const O: u8> CH4LIMITL_W<'a, O> { + #[doc = "Disable"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(CH4LIMITL_A::DISABLED) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(CH4LIMITL_A::ENABLED) + } +} +#[doc = "Field `CH5LIMITH` reader - Enable or disable interrupt for event CH5LIMITH"] +pub type CH5LIMITH_R = crate::BitReader; +#[doc = "Enable or disable interrupt for event CH5LIMITH\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CH5LIMITH_A { + #[doc = "0: Disable"] + DISABLED = 0, + #[doc = "1: Enable"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CH5LIMITH_A) -> Self { + variant as u8 != 0 + } +} +impl CH5LIMITH_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CH5LIMITH_A { + match self.bits { + false => CH5LIMITH_A::DISABLED, + true => CH5LIMITH_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == CH5LIMITH_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == CH5LIMITH_A::ENABLED + } +} +#[doc = "Field `CH5LIMITH` writer - Enable or disable interrupt for event CH5LIMITH"] +pub type CH5LIMITH_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTEN_SPEC, CH5LIMITH_A, O>; +impl<'a, const O: u8> CH5LIMITH_W<'a, O> { + #[doc = "Disable"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(CH5LIMITH_A::DISABLED) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(CH5LIMITH_A::ENABLED) + } +} +#[doc = "Field `CH5LIMITL` reader - Enable or disable interrupt for event CH5LIMITL"] +pub type CH5LIMITL_R = crate::BitReader; +#[doc = "Enable or disable interrupt for event CH5LIMITL\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CH5LIMITL_A { + #[doc = "0: Disable"] + DISABLED = 0, + #[doc = "1: Enable"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CH5LIMITL_A) -> Self { + variant as u8 != 0 + } +} +impl CH5LIMITL_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CH5LIMITL_A { + match self.bits { + false => CH5LIMITL_A::DISABLED, + true => CH5LIMITL_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == CH5LIMITL_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == CH5LIMITL_A::ENABLED + } +} +#[doc = "Field `CH5LIMITL` writer - Enable or disable interrupt for event CH5LIMITL"] +pub type CH5LIMITL_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTEN_SPEC, CH5LIMITL_A, O>; +impl<'a, const O: u8> CH5LIMITL_W<'a, O> { + #[doc = "Disable"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(CH5LIMITL_A::DISABLED) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(CH5LIMITL_A::ENABLED) + } +} +#[doc = "Field `CH6LIMITH` reader - Enable or disable interrupt for event CH6LIMITH"] +pub type CH6LIMITH_R = crate::BitReader; +#[doc = "Enable or disable interrupt for event CH6LIMITH\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CH6LIMITH_A { + #[doc = "0: Disable"] + DISABLED = 0, + #[doc = "1: Enable"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CH6LIMITH_A) -> Self { + variant as u8 != 0 + } +} +impl CH6LIMITH_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CH6LIMITH_A { + match self.bits { + false => CH6LIMITH_A::DISABLED, + true => CH6LIMITH_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == CH6LIMITH_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == CH6LIMITH_A::ENABLED + } +} +#[doc = "Field `CH6LIMITH` writer - Enable or disable interrupt for event CH6LIMITH"] +pub type CH6LIMITH_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTEN_SPEC, CH6LIMITH_A, O>; +impl<'a, const O: u8> CH6LIMITH_W<'a, O> { + #[doc = "Disable"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(CH6LIMITH_A::DISABLED) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(CH6LIMITH_A::ENABLED) + } +} +#[doc = "Field `CH6LIMITL` reader - Enable or disable interrupt for event CH6LIMITL"] +pub type CH6LIMITL_R = crate::BitReader; +#[doc = "Enable or disable interrupt for event CH6LIMITL\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CH6LIMITL_A { + #[doc = "0: Disable"] + DISABLED = 0, + #[doc = "1: Enable"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CH6LIMITL_A) -> Self { + variant as u8 != 0 + } +} +impl CH6LIMITL_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CH6LIMITL_A { + match self.bits { + false => CH6LIMITL_A::DISABLED, + true => CH6LIMITL_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == CH6LIMITL_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == CH6LIMITL_A::ENABLED + } +} +#[doc = "Field `CH6LIMITL` writer - Enable or disable interrupt for event CH6LIMITL"] +pub type CH6LIMITL_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTEN_SPEC, CH6LIMITL_A, O>; +impl<'a, const O: u8> CH6LIMITL_W<'a, O> { + #[doc = "Disable"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(CH6LIMITL_A::DISABLED) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(CH6LIMITL_A::ENABLED) + } +} +#[doc = "Field `CH7LIMITH` reader - Enable or disable interrupt for event CH7LIMITH"] +pub type CH7LIMITH_R = crate::BitReader; +#[doc = "Enable or disable interrupt for event CH7LIMITH\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CH7LIMITH_A { + #[doc = "0: Disable"] + DISABLED = 0, + #[doc = "1: Enable"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CH7LIMITH_A) -> Self { + variant as u8 != 0 + } +} +impl CH7LIMITH_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CH7LIMITH_A { + match self.bits { + false => CH7LIMITH_A::DISABLED, + true => CH7LIMITH_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == CH7LIMITH_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == CH7LIMITH_A::ENABLED + } +} +#[doc = "Field `CH7LIMITH` writer - Enable or disable interrupt for event CH7LIMITH"] +pub type CH7LIMITH_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTEN_SPEC, CH7LIMITH_A, O>; +impl<'a, const O: u8> CH7LIMITH_W<'a, O> { + #[doc = "Disable"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(CH7LIMITH_A::DISABLED) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(CH7LIMITH_A::ENABLED) + } +} +#[doc = "Field `CH7LIMITL` reader - Enable or disable interrupt for event CH7LIMITL"] +pub type CH7LIMITL_R = crate::BitReader; +#[doc = "Enable or disable interrupt for event CH7LIMITL\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CH7LIMITL_A { + #[doc = "0: Disable"] + DISABLED = 0, + #[doc = "1: Enable"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CH7LIMITL_A) -> Self { + variant as u8 != 0 + } +} +impl CH7LIMITL_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CH7LIMITL_A { + match self.bits { + false => CH7LIMITL_A::DISABLED, + true => CH7LIMITL_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == CH7LIMITL_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == CH7LIMITL_A::ENABLED + } +} +#[doc = "Field `CH7LIMITL` writer - Enable or disable interrupt for event CH7LIMITL"] +pub type CH7LIMITL_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTEN_SPEC, CH7LIMITL_A, O>; +impl<'a, const O: u8> CH7LIMITL_W<'a, O> { + #[doc = "Disable"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(CH7LIMITL_A::DISABLED) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(CH7LIMITL_A::ENABLED) + } +} +impl R { + #[doc = "Bit 0 - Enable or disable interrupt for event STARTED"] + #[inline(always)] + pub fn started(&self) -> STARTED_R { + STARTED_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Enable or disable interrupt for event END"] + #[inline(always)] + pub fn end(&self) -> END_R { + END_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Enable or disable interrupt for event DONE"] + #[inline(always)] + pub fn done(&self) -> DONE_R { + DONE_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Enable or disable interrupt for event RESULTDONE"] + #[inline(always)] + pub fn resultdone(&self) -> RESULTDONE_R { + RESULTDONE_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Enable or disable interrupt for event CALIBRATEDONE"] + #[inline(always)] + pub fn calibratedone(&self) -> CALIBRATEDONE_R { + CALIBRATEDONE_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Enable or disable interrupt for event STOPPED"] + #[inline(always)] + pub fn stopped(&self) -> STOPPED_R { + STOPPED_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Enable or disable interrupt for event CH0LIMITH"] + #[inline(always)] + pub fn ch0limith(&self) -> CH0LIMITH_R { + CH0LIMITH_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Enable or disable interrupt for event CH0LIMITL"] + #[inline(always)] + pub fn ch0limitl(&self) -> CH0LIMITL_R { + CH0LIMITL_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Enable or disable interrupt for event CH1LIMITH"] + #[inline(always)] + pub fn ch1limith(&self) -> CH1LIMITH_R { + CH1LIMITH_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Enable or disable interrupt for event CH1LIMITL"] + #[inline(always)] + pub fn ch1limitl(&self) -> CH1LIMITL_R { + CH1LIMITL_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Enable or disable interrupt for event CH2LIMITH"] + #[inline(always)] + pub fn ch2limith(&self) -> CH2LIMITH_R { + CH2LIMITH_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Enable or disable interrupt for event CH2LIMITL"] + #[inline(always)] + pub fn ch2limitl(&self) -> CH2LIMITL_R { + CH2LIMITL_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Enable or disable interrupt for event CH3LIMITH"] + #[inline(always)] + pub fn ch3limith(&self) -> CH3LIMITH_R { + CH3LIMITH_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Enable or disable interrupt for event CH3LIMITL"] + #[inline(always)] + pub fn ch3limitl(&self) -> CH3LIMITL_R { + CH3LIMITL_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Enable or disable interrupt for event CH4LIMITH"] + #[inline(always)] + pub fn ch4limith(&self) -> CH4LIMITH_R { + CH4LIMITH_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Enable or disable interrupt for event CH4LIMITL"] + #[inline(always)] + pub fn ch4limitl(&self) -> CH4LIMITL_R { + CH4LIMITL_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - Enable or disable interrupt for event CH5LIMITH"] + #[inline(always)] + pub fn ch5limith(&self) -> CH5LIMITH_R { + CH5LIMITH_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Enable or disable interrupt for event CH5LIMITL"] + #[inline(always)] + pub fn ch5limitl(&self) -> CH5LIMITL_R { + CH5LIMITL_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Enable or disable interrupt for event CH6LIMITH"] + #[inline(always)] + pub fn ch6limith(&self) -> CH6LIMITH_R { + CH6LIMITH_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Enable or disable interrupt for event CH6LIMITL"] + #[inline(always)] + pub fn ch6limitl(&self) -> CH6LIMITL_R { + CH6LIMITL_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Enable or disable interrupt for event CH7LIMITH"] + #[inline(always)] + pub fn ch7limith(&self) -> CH7LIMITH_R { + CH7LIMITH_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Enable or disable interrupt for event CH7LIMITL"] + #[inline(always)] + pub fn ch7limitl(&self) -> CH7LIMITL_R { + CH7LIMITL_R::new(((self.bits >> 21) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Enable or disable interrupt for event STARTED"] + #[inline(always)] + pub fn started(&mut self) -> STARTED_W<0> { + STARTED_W::new(self) + } + #[doc = "Bit 1 - Enable or disable interrupt for event END"] + #[inline(always)] + pub fn end(&mut self) -> END_W<1> { + END_W::new(self) + } + #[doc = "Bit 2 - Enable or disable interrupt for event DONE"] + #[inline(always)] + pub fn done(&mut self) -> DONE_W<2> { + DONE_W::new(self) + } + #[doc = "Bit 3 - Enable or disable interrupt for event RESULTDONE"] + #[inline(always)] + pub fn resultdone(&mut self) -> RESULTDONE_W<3> { + RESULTDONE_W::new(self) + } + #[doc = "Bit 4 - Enable or disable interrupt for event CALIBRATEDONE"] + #[inline(always)] + pub fn calibratedone(&mut self) -> CALIBRATEDONE_W<4> { + CALIBRATEDONE_W::new(self) + } + #[doc = "Bit 5 - Enable or disable interrupt for event STOPPED"] + #[inline(always)] + pub fn stopped(&mut self) -> STOPPED_W<5> { + STOPPED_W::new(self) + } + #[doc = "Bit 6 - Enable or disable interrupt for event CH0LIMITH"] + #[inline(always)] + pub fn ch0limith(&mut self) -> CH0LIMITH_W<6> { + CH0LIMITH_W::new(self) + } + #[doc = "Bit 7 - Enable or disable interrupt for event CH0LIMITL"] + #[inline(always)] + pub fn ch0limitl(&mut self) -> CH0LIMITL_W<7> { + CH0LIMITL_W::new(self) + } + #[doc = "Bit 8 - Enable or disable interrupt for event CH1LIMITH"] + #[inline(always)] + pub fn ch1limith(&mut self) -> CH1LIMITH_W<8> { + CH1LIMITH_W::new(self) + } + #[doc = "Bit 9 - Enable or disable interrupt for event CH1LIMITL"] + #[inline(always)] + pub fn ch1limitl(&mut self) -> CH1LIMITL_W<9> { + CH1LIMITL_W::new(self) + } + #[doc = "Bit 10 - Enable or disable interrupt for event CH2LIMITH"] + #[inline(always)] + pub fn ch2limith(&mut self) -> CH2LIMITH_W<10> { + CH2LIMITH_W::new(self) + } + #[doc = "Bit 11 - Enable or disable interrupt for event CH2LIMITL"] + #[inline(always)] + pub fn ch2limitl(&mut self) -> CH2LIMITL_W<11> { + CH2LIMITL_W::new(self) + } + #[doc = "Bit 12 - Enable or disable interrupt for event CH3LIMITH"] + #[inline(always)] + pub fn ch3limith(&mut self) -> CH3LIMITH_W<12> { + CH3LIMITH_W::new(self) + } + #[doc = "Bit 13 - Enable or disable interrupt for event CH3LIMITL"] + #[inline(always)] + pub fn ch3limitl(&mut self) -> CH3LIMITL_W<13> { + CH3LIMITL_W::new(self) + } + #[doc = "Bit 14 - Enable or disable interrupt for event CH4LIMITH"] + #[inline(always)] + pub fn ch4limith(&mut self) -> CH4LIMITH_W<14> { + CH4LIMITH_W::new(self) + } + #[doc = "Bit 15 - Enable or disable interrupt for event CH4LIMITL"] + #[inline(always)] + pub fn ch4limitl(&mut self) -> CH4LIMITL_W<15> { + CH4LIMITL_W::new(self) + } + #[doc = "Bit 16 - Enable or disable interrupt for event CH5LIMITH"] + #[inline(always)] + pub fn ch5limith(&mut self) -> CH5LIMITH_W<16> { + CH5LIMITH_W::new(self) + } + #[doc = "Bit 17 - Enable or disable interrupt for event CH5LIMITL"] + #[inline(always)] + pub fn ch5limitl(&mut self) -> CH5LIMITL_W<17> { + CH5LIMITL_W::new(self) + } + #[doc = "Bit 18 - Enable or disable interrupt for event CH6LIMITH"] + #[inline(always)] + pub fn ch6limith(&mut self) -> CH6LIMITH_W<18> { + CH6LIMITH_W::new(self) + } + #[doc = "Bit 19 - Enable or disable interrupt for event CH6LIMITL"] + #[inline(always)] + pub fn ch6limitl(&mut self) -> CH6LIMITL_W<19> { + CH6LIMITL_W::new(self) + } + #[doc = "Bit 20 - Enable or disable interrupt for event CH7LIMITH"] + #[inline(always)] + pub fn ch7limith(&mut self) -> CH7LIMITH_W<20> { + CH7LIMITH_W::new(self) + } + #[doc = "Bit 21 - Enable or disable interrupt for event CH7LIMITL"] + #[inline(always)] + pub fn ch7limitl(&mut self) -> CH7LIMITL_W<21> { + CH7LIMITL_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Enable or disable interrupt\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [inten](index.html) module"] +pub struct INTEN_SPEC; +impl crate::RegisterSpec for INTEN_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [inten::R](R) reader structure"] +impl crate::Readable for INTEN_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [inten::W](W) writer structure"] +impl crate::Writable for INTEN_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTEN to value 0"] +impl crate::Resettable for INTEN_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/saadc_ns/intenclr.rs b/pacs/nrf9120-pac/src/saadc_ns/intenclr.rs new file mode 100644 index 00000000..ee085d6e --- /dev/null +++ b/pacs/nrf9120-pac/src/saadc_ns/intenclr.rs @@ -0,0 +1,1541 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `STARTED` reader - Write '1' to disable interrupt for event STARTED"] +pub type STARTED_R = crate::BitReader; +#[doc = "Write '1' to disable interrupt for event STARTED\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum STARTED_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: STARTED_A) -> Self { + variant as u8 != 0 + } +} +impl STARTED_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> STARTED_A { + match self.bits { + false => STARTED_A::DISABLED, + true => STARTED_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == STARTED_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == STARTED_A::ENABLED + } +} +#[doc = "Write '1' to disable interrupt for event STARTED\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum STARTED_AW { + #[doc = "1: Disable"] + CLEAR = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: STARTED_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `STARTED` writer - Write '1' to disable interrupt for event STARTED"] +pub type STARTED_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENCLR_SPEC, STARTED_AW, O>; +impl<'a, const O: u8> STARTED_W<'a, O> { + #[doc = "Disable"] + #[inline(always)] + pub fn clear(self) -> &'a mut W { + self.variant(STARTED_AW::CLEAR) + } +} +#[doc = "Field `END` reader - Write '1' to disable interrupt for event END"] +pub type END_R = crate::BitReader; +#[doc = "Write '1' to disable interrupt for event END\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum END_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: END_A) -> Self { + variant as u8 != 0 + } +} +impl END_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> END_A { + match self.bits { + false => END_A::DISABLED, + true => END_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == END_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == END_A::ENABLED + } +} +#[doc = "Write '1' to disable interrupt for event END\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum END_AW { + #[doc = "1: Disable"] + CLEAR = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: END_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `END` writer - Write '1' to disable interrupt for event END"] +pub type END_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENCLR_SPEC, END_AW, O>; +impl<'a, const O: u8> END_W<'a, O> { + #[doc = "Disable"] + #[inline(always)] + pub fn clear(self) -> &'a mut W { + self.variant(END_AW::CLEAR) + } +} +#[doc = "Field `DONE` reader - Write '1' to disable interrupt for event DONE"] +pub type DONE_R = crate::BitReader; +#[doc = "Write '1' to disable interrupt for event DONE\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum DONE_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: DONE_A) -> Self { + variant as u8 != 0 + } +} +impl DONE_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> DONE_A { + match self.bits { + false => DONE_A::DISABLED, + true => DONE_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == DONE_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == DONE_A::ENABLED + } +} +#[doc = "Write '1' to disable interrupt for event DONE\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum DONE_AW { + #[doc = "1: Disable"] + CLEAR = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: DONE_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DONE` writer - Write '1' to disable interrupt for event DONE"] +pub type DONE_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENCLR_SPEC, DONE_AW, O>; +impl<'a, const O: u8> DONE_W<'a, O> { + #[doc = "Disable"] + #[inline(always)] + pub fn clear(self) -> &'a mut W { + self.variant(DONE_AW::CLEAR) + } +} +#[doc = "Field `RESULTDONE` reader - Write '1' to disable interrupt for event RESULTDONE"] +pub type RESULTDONE_R = crate::BitReader; +#[doc = "Write '1' to disable interrupt for event RESULTDONE\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RESULTDONE_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RESULTDONE_A) -> Self { + variant as u8 != 0 + } +} +impl RESULTDONE_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RESULTDONE_A { + match self.bits { + false => RESULTDONE_A::DISABLED, + true => RESULTDONE_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == RESULTDONE_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == RESULTDONE_A::ENABLED + } +} +#[doc = "Write '1' to disable interrupt for event RESULTDONE\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RESULTDONE_AW { + #[doc = "1: Disable"] + CLEAR = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RESULTDONE_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RESULTDONE` writer - Write '1' to disable interrupt for event RESULTDONE"] +pub type RESULTDONE_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENCLR_SPEC, RESULTDONE_AW, O>; +impl<'a, const O: u8> RESULTDONE_W<'a, O> { + #[doc = "Disable"] + #[inline(always)] + pub fn clear(self) -> &'a mut W { + self.variant(RESULTDONE_AW::CLEAR) + } +} +#[doc = "Field `CALIBRATEDONE` reader - Write '1' to disable interrupt for event CALIBRATEDONE"] +pub type CALIBRATEDONE_R = crate::BitReader; +#[doc = "Write '1' to disable interrupt for event CALIBRATEDONE\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CALIBRATEDONE_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CALIBRATEDONE_A) -> Self { + variant as u8 != 0 + } +} +impl CALIBRATEDONE_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CALIBRATEDONE_A { + match self.bits { + false => CALIBRATEDONE_A::DISABLED, + true => CALIBRATEDONE_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == CALIBRATEDONE_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == CALIBRATEDONE_A::ENABLED + } +} +#[doc = "Write '1' to disable interrupt for event CALIBRATEDONE\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CALIBRATEDONE_AW { + #[doc = "1: Disable"] + CLEAR = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CALIBRATEDONE_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CALIBRATEDONE` writer - Write '1' to disable interrupt for event CALIBRATEDONE"] +pub type CALIBRATEDONE_W<'a, const O: u8> = + crate::BitWriter<'a, u32, INTENCLR_SPEC, CALIBRATEDONE_AW, O>; +impl<'a, const O: u8> CALIBRATEDONE_W<'a, O> { + #[doc = "Disable"] + #[inline(always)] + pub fn clear(self) -> &'a mut W { + self.variant(CALIBRATEDONE_AW::CLEAR) + } +} +#[doc = "Field `STOPPED` reader - Write '1' to disable interrupt for event STOPPED"] +pub type STOPPED_R = crate::BitReader; +#[doc = "Write '1' to disable interrupt for event STOPPED\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum STOPPED_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: STOPPED_A) -> Self { + variant as u8 != 0 + } +} +impl STOPPED_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> STOPPED_A { + match self.bits { + false => STOPPED_A::DISABLED, + true => STOPPED_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == STOPPED_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == STOPPED_A::ENABLED + } +} +#[doc = "Write '1' to disable interrupt for event STOPPED\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum STOPPED_AW { + #[doc = "1: Disable"] + CLEAR = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: STOPPED_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `STOPPED` writer - Write '1' to disable interrupt for event STOPPED"] +pub type STOPPED_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENCLR_SPEC, STOPPED_AW, O>; +impl<'a, const O: u8> STOPPED_W<'a, O> { + #[doc = "Disable"] + #[inline(always)] + pub fn clear(self) -> &'a mut W { + self.variant(STOPPED_AW::CLEAR) + } +} +#[doc = "Field `CH0LIMITH` reader - Write '1' to disable interrupt for event CH0LIMITH"] +pub type CH0LIMITH_R = crate::BitReader; +#[doc = "Write '1' to disable interrupt for event CH0LIMITH\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CH0LIMITH_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CH0LIMITH_A) -> Self { + variant as u8 != 0 + } +} +impl CH0LIMITH_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CH0LIMITH_A { + match self.bits { + false => CH0LIMITH_A::DISABLED, + true => CH0LIMITH_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == CH0LIMITH_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == CH0LIMITH_A::ENABLED + } +} +#[doc = "Write '1' to disable interrupt for event CH0LIMITH\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CH0LIMITH_AW { + #[doc = "1: Disable"] + CLEAR = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CH0LIMITH_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CH0LIMITH` writer - Write '1' to disable interrupt for event CH0LIMITH"] +pub type CH0LIMITH_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENCLR_SPEC, CH0LIMITH_AW, O>; +impl<'a, const O: u8> CH0LIMITH_W<'a, O> { + #[doc = "Disable"] + #[inline(always)] + pub fn clear(self) -> &'a mut W { + self.variant(CH0LIMITH_AW::CLEAR) + } +} +#[doc = "Field `CH0LIMITL` reader - Write '1' to disable interrupt for event CH0LIMITL"] +pub type CH0LIMITL_R = crate::BitReader; +#[doc = "Write '1' to disable interrupt for event CH0LIMITL\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CH0LIMITL_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CH0LIMITL_A) -> Self { + variant as u8 != 0 + } +} +impl CH0LIMITL_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CH0LIMITL_A { + match self.bits { + false => CH0LIMITL_A::DISABLED, + true => CH0LIMITL_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == CH0LIMITL_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == CH0LIMITL_A::ENABLED + } +} +#[doc = "Write '1' to disable interrupt for event CH0LIMITL\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CH0LIMITL_AW { + #[doc = "1: Disable"] + CLEAR = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CH0LIMITL_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CH0LIMITL` writer - Write '1' to disable interrupt for event CH0LIMITL"] +pub type CH0LIMITL_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENCLR_SPEC, CH0LIMITL_AW, O>; +impl<'a, const O: u8> CH0LIMITL_W<'a, O> { + #[doc = "Disable"] + #[inline(always)] + pub fn clear(self) -> &'a mut W { + self.variant(CH0LIMITL_AW::CLEAR) + } +} +#[doc = "Field `CH1LIMITH` reader - Write '1' to disable interrupt for event CH1LIMITH"] +pub type CH1LIMITH_R = crate::BitReader; +#[doc = "Write '1' to disable interrupt for event CH1LIMITH\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CH1LIMITH_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CH1LIMITH_A) -> Self { + variant as u8 != 0 + } +} +impl CH1LIMITH_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CH1LIMITH_A { + match self.bits { + false => CH1LIMITH_A::DISABLED, + true => CH1LIMITH_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == CH1LIMITH_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == CH1LIMITH_A::ENABLED + } +} +#[doc = "Write '1' to disable interrupt for event CH1LIMITH\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CH1LIMITH_AW { + #[doc = "1: Disable"] + CLEAR = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CH1LIMITH_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CH1LIMITH` writer - Write '1' to disable interrupt for event CH1LIMITH"] +pub type CH1LIMITH_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENCLR_SPEC, CH1LIMITH_AW, O>; +impl<'a, const O: u8> CH1LIMITH_W<'a, O> { + #[doc = "Disable"] + #[inline(always)] + pub fn clear(self) -> &'a mut W { + self.variant(CH1LIMITH_AW::CLEAR) + } +} +#[doc = "Field `CH1LIMITL` reader - Write '1' to disable interrupt for event CH1LIMITL"] +pub type CH1LIMITL_R = crate::BitReader; +#[doc = "Write '1' to disable interrupt for event CH1LIMITL\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CH1LIMITL_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CH1LIMITL_A) -> Self { + variant as u8 != 0 + } +} +impl CH1LIMITL_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CH1LIMITL_A { + match self.bits { + false => CH1LIMITL_A::DISABLED, + true => CH1LIMITL_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == CH1LIMITL_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == CH1LIMITL_A::ENABLED + } +} +#[doc = "Write '1' to disable interrupt for event CH1LIMITL\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CH1LIMITL_AW { + #[doc = "1: Disable"] + CLEAR = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CH1LIMITL_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CH1LIMITL` writer - Write '1' to disable interrupt for event CH1LIMITL"] +pub type CH1LIMITL_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENCLR_SPEC, CH1LIMITL_AW, O>; +impl<'a, const O: u8> CH1LIMITL_W<'a, O> { + #[doc = "Disable"] + #[inline(always)] + pub fn clear(self) -> &'a mut W { + self.variant(CH1LIMITL_AW::CLEAR) + } +} +#[doc = "Field `CH2LIMITH` reader - Write '1' to disable interrupt for event CH2LIMITH"] +pub type CH2LIMITH_R = crate::BitReader; +#[doc = "Write '1' to disable interrupt for event CH2LIMITH\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CH2LIMITH_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CH2LIMITH_A) -> Self { + variant as u8 != 0 + } +} +impl CH2LIMITH_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CH2LIMITH_A { + match self.bits { + false => CH2LIMITH_A::DISABLED, + true => CH2LIMITH_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == CH2LIMITH_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == CH2LIMITH_A::ENABLED + } +} +#[doc = "Write '1' to disable interrupt for event CH2LIMITH\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CH2LIMITH_AW { + #[doc = "1: Disable"] + CLEAR = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CH2LIMITH_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CH2LIMITH` writer - Write '1' to disable interrupt for event CH2LIMITH"] +pub type CH2LIMITH_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENCLR_SPEC, CH2LIMITH_AW, O>; +impl<'a, const O: u8> CH2LIMITH_W<'a, O> { + #[doc = "Disable"] + #[inline(always)] + pub fn clear(self) -> &'a mut W { + self.variant(CH2LIMITH_AW::CLEAR) + } +} +#[doc = "Field `CH2LIMITL` reader - Write '1' to disable interrupt for event CH2LIMITL"] +pub type CH2LIMITL_R = crate::BitReader; +#[doc = "Write '1' to disable interrupt for event CH2LIMITL\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CH2LIMITL_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CH2LIMITL_A) -> Self { + variant as u8 != 0 + } +} +impl CH2LIMITL_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CH2LIMITL_A { + match self.bits { + false => CH2LIMITL_A::DISABLED, + true => CH2LIMITL_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == CH2LIMITL_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == CH2LIMITL_A::ENABLED + } +} +#[doc = "Write '1' to disable interrupt for event CH2LIMITL\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CH2LIMITL_AW { + #[doc = "1: Disable"] + CLEAR = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CH2LIMITL_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CH2LIMITL` writer - Write '1' to disable interrupt for event CH2LIMITL"] +pub type CH2LIMITL_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENCLR_SPEC, CH2LIMITL_AW, O>; +impl<'a, const O: u8> CH2LIMITL_W<'a, O> { + #[doc = "Disable"] + #[inline(always)] + pub fn clear(self) -> &'a mut W { + self.variant(CH2LIMITL_AW::CLEAR) + } +} +#[doc = "Field `CH3LIMITH` reader - Write '1' to disable interrupt for event CH3LIMITH"] +pub type CH3LIMITH_R = crate::BitReader; +#[doc = "Write '1' to disable interrupt for event CH3LIMITH\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CH3LIMITH_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CH3LIMITH_A) -> Self { + variant as u8 != 0 + } +} +impl CH3LIMITH_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CH3LIMITH_A { + match self.bits { + false => CH3LIMITH_A::DISABLED, + true => CH3LIMITH_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == CH3LIMITH_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == CH3LIMITH_A::ENABLED + } +} +#[doc = "Write '1' to disable interrupt for event CH3LIMITH\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CH3LIMITH_AW { + #[doc = "1: Disable"] + CLEAR = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CH3LIMITH_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CH3LIMITH` writer - Write '1' to disable interrupt for event CH3LIMITH"] +pub type CH3LIMITH_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENCLR_SPEC, CH3LIMITH_AW, O>; +impl<'a, const O: u8> CH3LIMITH_W<'a, O> { + #[doc = "Disable"] + #[inline(always)] + pub fn clear(self) -> &'a mut W { + self.variant(CH3LIMITH_AW::CLEAR) + } +} +#[doc = "Field `CH3LIMITL` reader - Write '1' to disable interrupt for event CH3LIMITL"] +pub type CH3LIMITL_R = crate::BitReader; +#[doc = "Write '1' to disable interrupt for event CH3LIMITL\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CH3LIMITL_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CH3LIMITL_A) -> Self { + variant as u8 != 0 + } +} +impl CH3LIMITL_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CH3LIMITL_A { + match self.bits { + false => CH3LIMITL_A::DISABLED, + true => CH3LIMITL_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == CH3LIMITL_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == CH3LIMITL_A::ENABLED + } +} +#[doc = "Write '1' to disable interrupt for event CH3LIMITL\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CH3LIMITL_AW { + #[doc = "1: Disable"] + CLEAR = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CH3LIMITL_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CH3LIMITL` writer - Write '1' to disable interrupt for event CH3LIMITL"] +pub type CH3LIMITL_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENCLR_SPEC, CH3LIMITL_AW, O>; +impl<'a, const O: u8> CH3LIMITL_W<'a, O> { + #[doc = "Disable"] + #[inline(always)] + pub fn clear(self) -> &'a mut W { + self.variant(CH3LIMITL_AW::CLEAR) + } +} +#[doc = "Field `CH4LIMITH` reader - Write '1' to disable interrupt for event CH4LIMITH"] +pub type CH4LIMITH_R = crate::BitReader; +#[doc = "Write '1' to disable interrupt for event CH4LIMITH\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CH4LIMITH_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CH4LIMITH_A) -> Self { + variant as u8 != 0 + } +} +impl CH4LIMITH_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CH4LIMITH_A { + match self.bits { + false => CH4LIMITH_A::DISABLED, + true => CH4LIMITH_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == CH4LIMITH_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == CH4LIMITH_A::ENABLED + } +} +#[doc = "Write '1' to disable interrupt for event CH4LIMITH\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CH4LIMITH_AW { + #[doc = "1: Disable"] + CLEAR = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CH4LIMITH_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CH4LIMITH` writer - Write '1' to disable interrupt for event CH4LIMITH"] +pub type CH4LIMITH_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENCLR_SPEC, CH4LIMITH_AW, O>; +impl<'a, const O: u8> CH4LIMITH_W<'a, O> { + #[doc = "Disable"] + #[inline(always)] + pub fn clear(self) -> &'a mut W { + self.variant(CH4LIMITH_AW::CLEAR) + } +} +#[doc = "Field `CH4LIMITL` reader - Write '1' to disable interrupt for event CH4LIMITL"] +pub type CH4LIMITL_R = crate::BitReader; +#[doc = "Write '1' to disable interrupt for event CH4LIMITL\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CH4LIMITL_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CH4LIMITL_A) -> Self { + variant as u8 != 0 + } +} +impl CH4LIMITL_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CH4LIMITL_A { + match self.bits { + false => CH4LIMITL_A::DISABLED, + true => CH4LIMITL_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == CH4LIMITL_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == CH4LIMITL_A::ENABLED + } +} +#[doc = "Write '1' to disable interrupt for event CH4LIMITL\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CH4LIMITL_AW { + #[doc = "1: Disable"] + CLEAR = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CH4LIMITL_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CH4LIMITL` writer - Write '1' to disable interrupt for event CH4LIMITL"] +pub type CH4LIMITL_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENCLR_SPEC, CH4LIMITL_AW, O>; +impl<'a, const O: u8> CH4LIMITL_W<'a, O> { + #[doc = "Disable"] + #[inline(always)] + pub fn clear(self) -> &'a mut W { + self.variant(CH4LIMITL_AW::CLEAR) + } +} +#[doc = "Field `CH5LIMITH` reader - Write '1' to disable interrupt for event CH5LIMITH"] +pub type CH5LIMITH_R = crate::BitReader; +#[doc = "Write '1' to disable interrupt for event CH5LIMITH\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CH5LIMITH_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CH5LIMITH_A) -> Self { + variant as u8 != 0 + } +} +impl CH5LIMITH_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CH5LIMITH_A { + match self.bits { + false => CH5LIMITH_A::DISABLED, + true => CH5LIMITH_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == CH5LIMITH_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == CH5LIMITH_A::ENABLED + } +} +#[doc = "Write '1' to disable interrupt for event CH5LIMITH\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CH5LIMITH_AW { + #[doc = "1: Disable"] + CLEAR = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CH5LIMITH_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CH5LIMITH` writer - Write '1' to disable interrupt for event CH5LIMITH"] +pub type CH5LIMITH_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENCLR_SPEC, CH5LIMITH_AW, O>; +impl<'a, const O: u8> CH5LIMITH_W<'a, O> { + #[doc = "Disable"] + #[inline(always)] + pub fn clear(self) -> &'a mut W { + self.variant(CH5LIMITH_AW::CLEAR) + } +} +#[doc = "Field `CH5LIMITL` reader - Write '1' to disable interrupt for event CH5LIMITL"] +pub type CH5LIMITL_R = crate::BitReader; +#[doc = "Write '1' to disable interrupt for event CH5LIMITL\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CH5LIMITL_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CH5LIMITL_A) -> Self { + variant as u8 != 0 + } +} +impl CH5LIMITL_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CH5LIMITL_A { + match self.bits { + false => CH5LIMITL_A::DISABLED, + true => CH5LIMITL_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == CH5LIMITL_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == CH5LIMITL_A::ENABLED + } +} +#[doc = "Write '1' to disable interrupt for event CH5LIMITL\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CH5LIMITL_AW { + #[doc = "1: Disable"] + CLEAR = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CH5LIMITL_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CH5LIMITL` writer - Write '1' to disable interrupt for event CH5LIMITL"] +pub type CH5LIMITL_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENCLR_SPEC, CH5LIMITL_AW, O>; +impl<'a, const O: u8> CH5LIMITL_W<'a, O> { + #[doc = "Disable"] + #[inline(always)] + pub fn clear(self) -> &'a mut W { + self.variant(CH5LIMITL_AW::CLEAR) + } +} +#[doc = "Field `CH6LIMITH` reader - Write '1' to disable interrupt for event CH6LIMITH"] +pub type CH6LIMITH_R = crate::BitReader; +#[doc = "Write '1' to disable interrupt for event CH6LIMITH\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CH6LIMITH_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CH6LIMITH_A) -> Self { + variant as u8 != 0 + } +} +impl CH6LIMITH_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CH6LIMITH_A { + match self.bits { + false => CH6LIMITH_A::DISABLED, + true => CH6LIMITH_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == CH6LIMITH_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == CH6LIMITH_A::ENABLED + } +} +#[doc = "Write '1' to disable interrupt for event CH6LIMITH\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CH6LIMITH_AW { + #[doc = "1: Disable"] + CLEAR = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CH6LIMITH_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CH6LIMITH` writer - Write '1' to disable interrupt for event CH6LIMITH"] +pub type CH6LIMITH_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENCLR_SPEC, CH6LIMITH_AW, O>; +impl<'a, const O: u8> CH6LIMITH_W<'a, O> { + #[doc = "Disable"] + #[inline(always)] + pub fn clear(self) -> &'a mut W { + self.variant(CH6LIMITH_AW::CLEAR) + } +} +#[doc = "Field `CH6LIMITL` reader - Write '1' to disable interrupt for event CH6LIMITL"] +pub type CH6LIMITL_R = crate::BitReader; +#[doc = "Write '1' to disable interrupt for event CH6LIMITL\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CH6LIMITL_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CH6LIMITL_A) -> Self { + variant as u8 != 0 + } +} +impl CH6LIMITL_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CH6LIMITL_A { + match self.bits { + false => CH6LIMITL_A::DISABLED, + true => CH6LIMITL_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == CH6LIMITL_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == CH6LIMITL_A::ENABLED + } +} +#[doc = "Write '1' to disable interrupt for event CH6LIMITL\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CH6LIMITL_AW { + #[doc = "1: Disable"] + CLEAR = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CH6LIMITL_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CH6LIMITL` writer - Write '1' to disable interrupt for event CH6LIMITL"] +pub type CH6LIMITL_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENCLR_SPEC, CH6LIMITL_AW, O>; +impl<'a, const O: u8> CH6LIMITL_W<'a, O> { + #[doc = "Disable"] + #[inline(always)] + pub fn clear(self) -> &'a mut W { + self.variant(CH6LIMITL_AW::CLEAR) + } +} +#[doc = "Field `CH7LIMITH` reader - Write '1' to disable interrupt for event CH7LIMITH"] +pub type CH7LIMITH_R = crate::BitReader; +#[doc = "Write '1' to disable interrupt for event CH7LIMITH\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CH7LIMITH_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CH7LIMITH_A) -> Self { + variant as u8 != 0 + } +} +impl CH7LIMITH_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CH7LIMITH_A { + match self.bits { + false => CH7LIMITH_A::DISABLED, + true => CH7LIMITH_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == CH7LIMITH_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == CH7LIMITH_A::ENABLED + } +} +#[doc = "Write '1' to disable interrupt for event CH7LIMITH\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CH7LIMITH_AW { + #[doc = "1: Disable"] + CLEAR = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CH7LIMITH_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CH7LIMITH` writer - Write '1' to disable interrupt for event CH7LIMITH"] +pub type CH7LIMITH_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENCLR_SPEC, CH7LIMITH_AW, O>; +impl<'a, const O: u8> CH7LIMITH_W<'a, O> { + #[doc = "Disable"] + #[inline(always)] + pub fn clear(self) -> &'a mut W { + self.variant(CH7LIMITH_AW::CLEAR) + } +} +#[doc = "Field `CH7LIMITL` reader - Write '1' to disable interrupt for event CH7LIMITL"] +pub type CH7LIMITL_R = crate::BitReader; +#[doc = "Write '1' to disable interrupt for event CH7LIMITL\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CH7LIMITL_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CH7LIMITL_A) -> Self { + variant as u8 != 0 + } +} +impl CH7LIMITL_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CH7LIMITL_A { + match self.bits { + false => CH7LIMITL_A::DISABLED, + true => CH7LIMITL_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == CH7LIMITL_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == CH7LIMITL_A::ENABLED + } +} +#[doc = "Write '1' to disable interrupt for event CH7LIMITL\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CH7LIMITL_AW { + #[doc = "1: Disable"] + CLEAR = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CH7LIMITL_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CH7LIMITL` writer - Write '1' to disable interrupt for event CH7LIMITL"] +pub type CH7LIMITL_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENCLR_SPEC, CH7LIMITL_AW, O>; +impl<'a, const O: u8> CH7LIMITL_W<'a, O> { + #[doc = "Disable"] + #[inline(always)] + pub fn clear(self) -> &'a mut W { + self.variant(CH7LIMITL_AW::CLEAR) + } +} +impl R { + #[doc = "Bit 0 - Write '1' to disable interrupt for event STARTED"] + #[inline(always)] + pub fn started(&self) -> STARTED_R { + STARTED_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Write '1' to disable interrupt for event END"] + #[inline(always)] + pub fn end(&self) -> END_R { + END_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Write '1' to disable interrupt for event DONE"] + #[inline(always)] + pub fn done(&self) -> DONE_R { + DONE_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Write '1' to disable interrupt for event RESULTDONE"] + #[inline(always)] + pub fn resultdone(&self) -> RESULTDONE_R { + RESULTDONE_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Write '1' to disable interrupt for event CALIBRATEDONE"] + #[inline(always)] + pub fn calibratedone(&self) -> CALIBRATEDONE_R { + CALIBRATEDONE_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Write '1' to disable interrupt for event STOPPED"] + #[inline(always)] + pub fn stopped(&self) -> STOPPED_R { + STOPPED_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Write '1' to disable interrupt for event CH0LIMITH"] + #[inline(always)] + pub fn ch0limith(&self) -> CH0LIMITH_R { + CH0LIMITH_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Write '1' to disable interrupt for event CH0LIMITL"] + #[inline(always)] + pub fn ch0limitl(&self) -> CH0LIMITL_R { + CH0LIMITL_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Write '1' to disable interrupt for event CH1LIMITH"] + #[inline(always)] + pub fn ch1limith(&self) -> CH1LIMITH_R { + CH1LIMITH_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Write '1' to disable interrupt for event CH1LIMITL"] + #[inline(always)] + pub fn ch1limitl(&self) -> CH1LIMITL_R { + CH1LIMITL_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Write '1' to disable interrupt for event CH2LIMITH"] + #[inline(always)] + pub fn ch2limith(&self) -> CH2LIMITH_R { + CH2LIMITH_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Write '1' to disable interrupt for event CH2LIMITL"] + #[inline(always)] + pub fn ch2limitl(&self) -> CH2LIMITL_R { + CH2LIMITL_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Write '1' to disable interrupt for event CH3LIMITH"] + #[inline(always)] + pub fn ch3limith(&self) -> CH3LIMITH_R { + CH3LIMITH_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Write '1' to disable interrupt for event CH3LIMITL"] + #[inline(always)] + pub fn ch3limitl(&self) -> CH3LIMITL_R { + CH3LIMITL_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Write '1' to disable interrupt for event CH4LIMITH"] + #[inline(always)] + pub fn ch4limith(&self) -> CH4LIMITH_R { + CH4LIMITH_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Write '1' to disable interrupt for event CH4LIMITL"] + #[inline(always)] + pub fn ch4limitl(&self) -> CH4LIMITL_R { + CH4LIMITL_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - Write '1' to disable interrupt for event CH5LIMITH"] + #[inline(always)] + pub fn ch5limith(&self) -> CH5LIMITH_R { + CH5LIMITH_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Write '1' to disable interrupt for event CH5LIMITL"] + #[inline(always)] + pub fn ch5limitl(&self) -> CH5LIMITL_R { + CH5LIMITL_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Write '1' to disable interrupt for event CH6LIMITH"] + #[inline(always)] + pub fn ch6limith(&self) -> CH6LIMITH_R { + CH6LIMITH_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Write '1' to disable interrupt for event CH6LIMITL"] + #[inline(always)] + pub fn ch6limitl(&self) -> CH6LIMITL_R { + CH6LIMITL_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Write '1' to disable interrupt for event CH7LIMITH"] + #[inline(always)] + pub fn ch7limith(&self) -> CH7LIMITH_R { + CH7LIMITH_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Write '1' to disable interrupt for event CH7LIMITL"] + #[inline(always)] + pub fn ch7limitl(&self) -> CH7LIMITL_R { + CH7LIMITL_R::new(((self.bits >> 21) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Write '1' to disable interrupt for event STARTED"] + #[inline(always)] + pub fn started(&mut self) -> STARTED_W<0> { + STARTED_W::new(self) + } + #[doc = "Bit 1 - Write '1' to disable interrupt for event END"] + #[inline(always)] + pub fn end(&mut self) -> END_W<1> { + END_W::new(self) + } + #[doc = "Bit 2 - Write '1' to disable interrupt for event DONE"] + #[inline(always)] + pub fn done(&mut self) -> DONE_W<2> { + DONE_W::new(self) + } + #[doc = "Bit 3 - Write '1' to disable interrupt for event RESULTDONE"] + #[inline(always)] + pub fn resultdone(&mut self) -> RESULTDONE_W<3> { + RESULTDONE_W::new(self) + } + #[doc = "Bit 4 - Write '1' to disable interrupt for event CALIBRATEDONE"] + #[inline(always)] + pub fn calibratedone(&mut self) -> CALIBRATEDONE_W<4> { + CALIBRATEDONE_W::new(self) + } + #[doc = "Bit 5 - Write '1' to disable interrupt for event STOPPED"] + #[inline(always)] + pub fn stopped(&mut self) -> STOPPED_W<5> { + STOPPED_W::new(self) + } + #[doc = "Bit 6 - Write '1' to disable interrupt for event CH0LIMITH"] + #[inline(always)] + pub fn ch0limith(&mut self) -> CH0LIMITH_W<6> { + CH0LIMITH_W::new(self) + } + #[doc = "Bit 7 - Write '1' to disable interrupt for event CH0LIMITL"] + #[inline(always)] + pub fn ch0limitl(&mut self) -> CH0LIMITL_W<7> { + CH0LIMITL_W::new(self) + } + #[doc = "Bit 8 - Write '1' to disable interrupt for event CH1LIMITH"] + #[inline(always)] + pub fn ch1limith(&mut self) -> CH1LIMITH_W<8> { + CH1LIMITH_W::new(self) + } + #[doc = "Bit 9 - Write '1' to disable interrupt for event CH1LIMITL"] + #[inline(always)] + pub fn ch1limitl(&mut self) -> CH1LIMITL_W<9> { + CH1LIMITL_W::new(self) + } + #[doc = "Bit 10 - Write '1' to disable interrupt for event CH2LIMITH"] + #[inline(always)] + pub fn ch2limith(&mut self) -> CH2LIMITH_W<10> { + CH2LIMITH_W::new(self) + } + #[doc = "Bit 11 - Write '1' to disable interrupt for event CH2LIMITL"] + #[inline(always)] + pub fn ch2limitl(&mut self) -> CH2LIMITL_W<11> { + CH2LIMITL_W::new(self) + } + #[doc = "Bit 12 - Write '1' to disable interrupt for event CH3LIMITH"] + #[inline(always)] + pub fn ch3limith(&mut self) -> CH3LIMITH_W<12> { + CH3LIMITH_W::new(self) + } + #[doc = "Bit 13 - Write '1' to disable interrupt for event CH3LIMITL"] + #[inline(always)] + pub fn ch3limitl(&mut self) -> CH3LIMITL_W<13> { + CH3LIMITL_W::new(self) + } + #[doc = "Bit 14 - Write '1' to disable interrupt for event CH4LIMITH"] + #[inline(always)] + pub fn ch4limith(&mut self) -> CH4LIMITH_W<14> { + CH4LIMITH_W::new(self) + } + #[doc = "Bit 15 - Write '1' to disable interrupt for event CH4LIMITL"] + #[inline(always)] + pub fn ch4limitl(&mut self) -> CH4LIMITL_W<15> { + CH4LIMITL_W::new(self) + } + #[doc = "Bit 16 - Write '1' to disable interrupt for event CH5LIMITH"] + #[inline(always)] + pub fn ch5limith(&mut self) -> CH5LIMITH_W<16> { + CH5LIMITH_W::new(self) + } + #[doc = "Bit 17 - Write '1' to disable interrupt for event CH5LIMITL"] + #[inline(always)] + pub fn ch5limitl(&mut self) -> CH5LIMITL_W<17> { + CH5LIMITL_W::new(self) + } + #[doc = "Bit 18 - Write '1' to disable interrupt for event CH6LIMITH"] + #[inline(always)] + pub fn ch6limith(&mut self) -> CH6LIMITH_W<18> { + CH6LIMITH_W::new(self) + } + #[doc = "Bit 19 - Write '1' to disable interrupt for event CH6LIMITL"] + #[inline(always)] + pub fn ch6limitl(&mut self) -> CH6LIMITL_W<19> { + CH6LIMITL_W::new(self) + } + #[doc = "Bit 20 - Write '1' to disable interrupt for event CH7LIMITH"] + #[inline(always)] + pub fn ch7limith(&mut self) -> CH7LIMITH_W<20> { + CH7LIMITH_W::new(self) + } + #[doc = "Bit 21 - Write '1' to disable interrupt for event CH7LIMITL"] + #[inline(always)] + pub fn ch7limitl(&mut self) -> CH7LIMITL_W<21> { + CH7LIMITL_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Disable interrupt\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/saadc_ns/intenset.rs b/pacs/nrf9120-pac/src/saadc_ns/intenset.rs new file mode 100644 index 00000000..731ced6c --- /dev/null +++ b/pacs/nrf9120-pac/src/saadc_ns/intenset.rs @@ -0,0 +1,1541 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `STARTED` reader - Write '1' to enable interrupt for event STARTED"] +pub type STARTED_R = crate::BitReader; +#[doc = "Write '1' to enable interrupt for event STARTED\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum STARTED_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: STARTED_A) -> Self { + variant as u8 != 0 + } +} +impl STARTED_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> STARTED_A { + match self.bits { + false => STARTED_A::DISABLED, + true => STARTED_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == STARTED_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == STARTED_A::ENABLED + } +} +#[doc = "Write '1' to enable interrupt for event STARTED\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum STARTED_AW { + #[doc = "1: Enable"] + SET = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: STARTED_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `STARTED` writer - Write '1' to enable interrupt for event STARTED"] +pub type STARTED_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENSET_SPEC, STARTED_AW, O>; +impl<'a, const O: u8> STARTED_W<'a, O> { + #[doc = "Enable"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(STARTED_AW::SET) + } +} +#[doc = "Field `END` reader - Write '1' to enable interrupt for event END"] +pub type END_R = crate::BitReader; +#[doc = "Write '1' to enable interrupt for event END\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum END_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: END_A) -> Self { + variant as u8 != 0 + } +} +impl END_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> END_A { + match self.bits { + false => END_A::DISABLED, + true => END_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == END_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == END_A::ENABLED + } +} +#[doc = "Write '1' to enable interrupt for event END\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum END_AW { + #[doc = "1: Enable"] + SET = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: END_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `END` writer - Write '1' to enable interrupt for event END"] +pub type END_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENSET_SPEC, END_AW, O>; +impl<'a, const O: u8> END_W<'a, O> { + #[doc = "Enable"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(END_AW::SET) + } +} +#[doc = "Field `DONE` reader - Write '1' to enable interrupt for event DONE"] +pub type DONE_R = crate::BitReader; +#[doc = "Write '1' to enable interrupt for event DONE\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum DONE_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: DONE_A) -> Self { + variant as u8 != 0 + } +} +impl DONE_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> DONE_A { + match self.bits { + false => DONE_A::DISABLED, + true => DONE_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == DONE_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == DONE_A::ENABLED + } +} +#[doc = "Write '1' to enable interrupt for event DONE\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum DONE_AW { + #[doc = "1: Enable"] + SET = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: DONE_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DONE` writer - Write '1' to enable interrupt for event DONE"] +pub type DONE_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENSET_SPEC, DONE_AW, O>; +impl<'a, const O: u8> DONE_W<'a, O> { + #[doc = "Enable"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(DONE_AW::SET) + } +} +#[doc = "Field `RESULTDONE` reader - Write '1' to enable interrupt for event RESULTDONE"] +pub type RESULTDONE_R = crate::BitReader; +#[doc = "Write '1' to enable interrupt for event RESULTDONE\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RESULTDONE_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RESULTDONE_A) -> Self { + variant as u8 != 0 + } +} +impl RESULTDONE_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RESULTDONE_A { + match self.bits { + false => RESULTDONE_A::DISABLED, + true => RESULTDONE_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == RESULTDONE_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == RESULTDONE_A::ENABLED + } +} +#[doc = "Write '1' to enable interrupt for event RESULTDONE\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RESULTDONE_AW { + #[doc = "1: Enable"] + SET = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RESULTDONE_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RESULTDONE` writer - Write '1' to enable interrupt for event RESULTDONE"] +pub type RESULTDONE_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENSET_SPEC, RESULTDONE_AW, O>; +impl<'a, const O: u8> RESULTDONE_W<'a, O> { + #[doc = "Enable"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(RESULTDONE_AW::SET) + } +} +#[doc = "Field `CALIBRATEDONE` reader - Write '1' to enable interrupt for event CALIBRATEDONE"] +pub type CALIBRATEDONE_R = crate::BitReader; +#[doc = "Write '1' to enable interrupt for event CALIBRATEDONE\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CALIBRATEDONE_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CALIBRATEDONE_A) -> Self { + variant as u8 != 0 + } +} +impl CALIBRATEDONE_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CALIBRATEDONE_A { + match self.bits { + false => CALIBRATEDONE_A::DISABLED, + true => CALIBRATEDONE_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == CALIBRATEDONE_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == CALIBRATEDONE_A::ENABLED + } +} +#[doc = "Write '1' to enable interrupt for event CALIBRATEDONE\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CALIBRATEDONE_AW { + #[doc = "1: Enable"] + SET = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CALIBRATEDONE_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CALIBRATEDONE` writer - Write '1' to enable interrupt for event CALIBRATEDONE"] +pub type CALIBRATEDONE_W<'a, const O: u8> = + crate::BitWriter<'a, u32, INTENSET_SPEC, CALIBRATEDONE_AW, O>; +impl<'a, const O: u8> CALIBRATEDONE_W<'a, O> { + #[doc = "Enable"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(CALIBRATEDONE_AW::SET) + } +} +#[doc = "Field `STOPPED` reader - Write '1' to enable interrupt for event STOPPED"] +pub type STOPPED_R = crate::BitReader; +#[doc = "Write '1' to enable interrupt for event STOPPED\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum STOPPED_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: STOPPED_A) -> Self { + variant as u8 != 0 + } +} +impl STOPPED_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> STOPPED_A { + match self.bits { + false => STOPPED_A::DISABLED, + true => STOPPED_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == STOPPED_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == STOPPED_A::ENABLED + } +} +#[doc = "Write '1' to enable interrupt for event STOPPED\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum STOPPED_AW { + #[doc = "1: Enable"] + SET = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: STOPPED_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `STOPPED` writer - Write '1' to enable interrupt for event STOPPED"] +pub type STOPPED_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENSET_SPEC, STOPPED_AW, O>; +impl<'a, const O: u8> STOPPED_W<'a, O> { + #[doc = "Enable"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(STOPPED_AW::SET) + } +} +#[doc = "Field `CH0LIMITH` reader - Write '1' to enable interrupt for event CH0LIMITH"] +pub type CH0LIMITH_R = crate::BitReader; +#[doc = "Write '1' to enable interrupt for event CH0LIMITH\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CH0LIMITH_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CH0LIMITH_A) -> Self { + variant as u8 != 0 + } +} +impl CH0LIMITH_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CH0LIMITH_A { + match self.bits { + false => CH0LIMITH_A::DISABLED, + true => CH0LIMITH_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == CH0LIMITH_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == CH0LIMITH_A::ENABLED + } +} +#[doc = "Write '1' to enable interrupt for event CH0LIMITH\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CH0LIMITH_AW { + #[doc = "1: Enable"] + SET = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CH0LIMITH_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CH0LIMITH` writer - Write '1' to enable interrupt for event CH0LIMITH"] +pub type CH0LIMITH_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENSET_SPEC, CH0LIMITH_AW, O>; +impl<'a, const O: u8> CH0LIMITH_W<'a, O> { + #[doc = "Enable"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(CH0LIMITH_AW::SET) + } +} +#[doc = "Field `CH0LIMITL` reader - Write '1' to enable interrupt for event CH0LIMITL"] +pub type CH0LIMITL_R = crate::BitReader; +#[doc = "Write '1' to enable interrupt for event CH0LIMITL\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CH0LIMITL_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CH0LIMITL_A) -> Self { + variant as u8 != 0 + } +} +impl CH0LIMITL_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CH0LIMITL_A { + match self.bits { + false => CH0LIMITL_A::DISABLED, + true => CH0LIMITL_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == CH0LIMITL_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == CH0LIMITL_A::ENABLED + } +} +#[doc = "Write '1' to enable interrupt for event CH0LIMITL\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CH0LIMITL_AW { + #[doc = "1: Enable"] + SET = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CH0LIMITL_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CH0LIMITL` writer - Write '1' to enable interrupt for event CH0LIMITL"] +pub type CH0LIMITL_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENSET_SPEC, CH0LIMITL_AW, O>; +impl<'a, const O: u8> CH0LIMITL_W<'a, O> { + #[doc = "Enable"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(CH0LIMITL_AW::SET) + } +} +#[doc = "Field `CH1LIMITH` reader - Write '1' to enable interrupt for event CH1LIMITH"] +pub type CH1LIMITH_R = crate::BitReader; +#[doc = "Write '1' to enable interrupt for event CH1LIMITH\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CH1LIMITH_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CH1LIMITH_A) -> Self { + variant as u8 != 0 + } +} +impl CH1LIMITH_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CH1LIMITH_A { + match self.bits { + false => CH1LIMITH_A::DISABLED, + true => CH1LIMITH_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == CH1LIMITH_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == CH1LIMITH_A::ENABLED + } +} +#[doc = "Write '1' to enable interrupt for event CH1LIMITH\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CH1LIMITH_AW { + #[doc = "1: Enable"] + SET = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CH1LIMITH_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CH1LIMITH` writer - Write '1' to enable interrupt for event CH1LIMITH"] +pub type CH1LIMITH_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENSET_SPEC, CH1LIMITH_AW, O>; +impl<'a, const O: u8> CH1LIMITH_W<'a, O> { + #[doc = "Enable"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(CH1LIMITH_AW::SET) + } +} +#[doc = "Field `CH1LIMITL` reader - Write '1' to enable interrupt for event CH1LIMITL"] +pub type CH1LIMITL_R = crate::BitReader; +#[doc = "Write '1' to enable interrupt for event CH1LIMITL\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CH1LIMITL_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CH1LIMITL_A) -> Self { + variant as u8 != 0 + } +} +impl CH1LIMITL_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CH1LIMITL_A { + match self.bits { + false => CH1LIMITL_A::DISABLED, + true => CH1LIMITL_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == CH1LIMITL_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == CH1LIMITL_A::ENABLED + } +} +#[doc = "Write '1' to enable interrupt for event CH1LIMITL\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CH1LIMITL_AW { + #[doc = "1: Enable"] + SET = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CH1LIMITL_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CH1LIMITL` writer - Write '1' to enable interrupt for event CH1LIMITL"] +pub type CH1LIMITL_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENSET_SPEC, CH1LIMITL_AW, O>; +impl<'a, const O: u8> CH1LIMITL_W<'a, O> { + #[doc = "Enable"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(CH1LIMITL_AW::SET) + } +} +#[doc = "Field `CH2LIMITH` reader - Write '1' to enable interrupt for event CH2LIMITH"] +pub type CH2LIMITH_R = crate::BitReader; +#[doc = "Write '1' to enable interrupt for event CH2LIMITH\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CH2LIMITH_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CH2LIMITH_A) -> Self { + variant as u8 != 0 + } +} +impl CH2LIMITH_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CH2LIMITH_A { + match self.bits { + false => CH2LIMITH_A::DISABLED, + true => CH2LIMITH_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == CH2LIMITH_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == CH2LIMITH_A::ENABLED + } +} +#[doc = "Write '1' to enable interrupt for event CH2LIMITH\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CH2LIMITH_AW { + #[doc = "1: Enable"] + SET = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CH2LIMITH_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CH2LIMITH` writer - Write '1' to enable interrupt for event CH2LIMITH"] +pub type CH2LIMITH_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENSET_SPEC, CH2LIMITH_AW, O>; +impl<'a, const O: u8> CH2LIMITH_W<'a, O> { + #[doc = "Enable"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(CH2LIMITH_AW::SET) + } +} +#[doc = "Field `CH2LIMITL` reader - Write '1' to enable interrupt for event CH2LIMITL"] +pub type CH2LIMITL_R = crate::BitReader; +#[doc = "Write '1' to enable interrupt for event CH2LIMITL\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CH2LIMITL_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CH2LIMITL_A) -> Self { + variant as u8 != 0 + } +} +impl CH2LIMITL_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CH2LIMITL_A { + match self.bits { + false => CH2LIMITL_A::DISABLED, + true => CH2LIMITL_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == CH2LIMITL_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == CH2LIMITL_A::ENABLED + } +} +#[doc = "Write '1' to enable interrupt for event CH2LIMITL\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CH2LIMITL_AW { + #[doc = "1: Enable"] + SET = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CH2LIMITL_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CH2LIMITL` writer - Write '1' to enable interrupt for event CH2LIMITL"] +pub type CH2LIMITL_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENSET_SPEC, CH2LIMITL_AW, O>; +impl<'a, const O: u8> CH2LIMITL_W<'a, O> { + #[doc = "Enable"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(CH2LIMITL_AW::SET) + } +} +#[doc = "Field `CH3LIMITH` reader - Write '1' to enable interrupt for event CH3LIMITH"] +pub type CH3LIMITH_R = crate::BitReader; +#[doc = "Write '1' to enable interrupt for event CH3LIMITH\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CH3LIMITH_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CH3LIMITH_A) -> Self { + variant as u8 != 0 + } +} +impl CH3LIMITH_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CH3LIMITH_A { + match self.bits { + false => CH3LIMITH_A::DISABLED, + true => CH3LIMITH_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == CH3LIMITH_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == CH3LIMITH_A::ENABLED + } +} +#[doc = "Write '1' to enable interrupt for event CH3LIMITH\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CH3LIMITH_AW { + #[doc = "1: Enable"] + SET = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CH3LIMITH_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CH3LIMITH` writer - Write '1' to enable interrupt for event CH3LIMITH"] +pub type CH3LIMITH_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENSET_SPEC, CH3LIMITH_AW, O>; +impl<'a, const O: u8> CH3LIMITH_W<'a, O> { + #[doc = "Enable"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(CH3LIMITH_AW::SET) + } +} +#[doc = "Field `CH3LIMITL` reader - Write '1' to enable interrupt for event CH3LIMITL"] +pub type CH3LIMITL_R = crate::BitReader; +#[doc = "Write '1' to enable interrupt for event CH3LIMITL\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CH3LIMITL_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CH3LIMITL_A) -> Self { + variant as u8 != 0 + } +} +impl CH3LIMITL_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CH3LIMITL_A { + match self.bits { + false => CH3LIMITL_A::DISABLED, + true => CH3LIMITL_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == CH3LIMITL_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == CH3LIMITL_A::ENABLED + } +} +#[doc = "Write '1' to enable interrupt for event CH3LIMITL\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CH3LIMITL_AW { + #[doc = "1: Enable"] + SET = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CH3LIMITL_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CH3LIMITL` writer - Write '1' to enable interrupt for event CH3LIMITL"] +pub type CH3LIMITL_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENSET_SPEC, CH3LIMITL_AW, O>; +impl<'a, const O: u8> CH3LIMITL_W<'a, O> { + #[doc = "Enable"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(CH3LIMITL_AW::SET) + } +} +#[doc = "Field `CH4LIMITH` reader - Write '1' to enable interrupt for event CH4LIMITH"] +pub type CH4LIMITH_R = crate::BitReader; +#[doc = "Write '1' to enable interrupt for event CH4LIMITH\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CH4LIMITH_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CH4LIMITH_A) -> Self { + variant as u8 != 0 + } +} +impl CH4LIMITH_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CH4LIMITH_A { + match self.bits { + false => CH4LIMITH_A::DISABLED, + true => CH4LIMITH_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == CH4LIMITH_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == CH4LIMITH_A::ENABLED + } +} +#[doc = "Write '1' to enable interrupt for event CH4LIMITH\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CH4LIMITH_AW { + #[doc = "1: Enable"] + SET = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CH4LIMITH_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CH4LIMITH` writer - Write '1' to enable interrupt for event CH4LIMITH"] +pub type CH4LIMITH_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENSET_SPEC, CH4LIMITH_AW, O>; +impl<'a, const O: u8> CH4LIMITH_W<'a, O> { + #[doc = "Enable"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(CH4LIMITH_AW::SET) + } +} +#[doc = "Field `CH4LIMITL` reader - Write '1' to enable interrupt for event CH4LIMITL"] +pub type CH4LIMITL_R = crate::BitReader; +#[doc = "Write '1' to enable interrupt for event CH4LIMITL\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CH4LIMITL_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CH4LIMITL_A) -> Self { + variant as u8 != 0 + } +} +impl CH4LIMITL_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CH4LIMITL_A { + match self.bits { + false => CH4LIMITL_A::DISABLED, + true => CH4LIMITL_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == CH4LIMITL_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == CH4LIMITL_A::ENABLED + } +} +#[doc = "Write '1' to enable interrupt for event CH4LIMITL\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CH4LIMITL_AW { + #[doc = "1: Enable"] + SET = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CH4LIMITL_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CH4LIMITL` writer - Write '1' to enable interrupt for event CH4LIMITL"] +pub type CH4LIMITL_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENSET_SPEC, CH4LIMITL_AW, O>; +impl<'a, const O: u8> CH4LIMITL_W<'a, O> { + #[doc = "Enable"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(CH4LIMITL_AW::SET) + } +} +#[doc = "Field `CH5LIMITH` reader - Write '1' to enable interrupt for event CH5LIMITH"] +pub type CH5LIMITH_R = crate::BitReader; +#[doc = "Write '1' to enable interrupt for event CH5LIMITH\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CH5LIMITH_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CH5LIMITH_A) -> Self { + variant as u8 != 0 + } +} +impl CH5LIMITH_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CH5LIMITH_A { + match self.bits { + false => CH5LIMITH_A::DISABLED, + true => CH5LIMITH_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == CH5LIMITH_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == CH5LIMITH_A::ENABLED + } +} +#[doc = "Write '1' to enable interrupt for event CH5LIMITH\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CH5LIMITH_AW { + #[doc = "1: Enable"] + SET = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CH5LIMITH_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CH5LIMITH` writer - Write '1' to enable interrupt for event CH5LIMITH"] +pub type CH5LIMITH_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENSET_SPEC, CH5LIMITH_AW, O>; +impl<'a, const O: u8> CH5LIMITH_W<'a, O> { + #[doc = "Enable"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(CH5LIMITH_AW::SET) + } +} +#[doc = "Field `CH5LIMITL` reader - Write '1' to enable interrupt for event CH5LIMITL"] +pub type CH5LIMITL_R = crate::BitReader; +#[doc = "Write '1' to enable interrupt for event CH5LIMITL\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CH5LIMITL_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CH5LIMITL_A) -> Self { + variant as u8 != 0 + } +} +impl CH5LIMITL_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CH5LIMITL_A { + match self.bits { + false => CH5LIMITL_A::DISABLED, + true => CH5LIMITL_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == CH5LIMITL_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == CH5LIMITL_A::ENABLED + } +} +#[doc = "Write '1' to enable interrupt for event CH5LIMITL\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CH5LIMITL_AW { + #[doc = "1: Enable"] + SET = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CH5LIMITL_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CH5LIMITL` writer - Write '1' to enable interrupt for event CH5LIMITL"] +pub type CH5LIMITL_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENSET_SPEC, CH5LIMITL_AW, O>; +impl<'a, const O: u8> CH5LIMITL_W<'a, O> { + #[doc = "Enable"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(CH5LIMITL_AW::SET) + } +} +#[doc = "Field `CH6LIMITH` reader - Write '1' to enable interrupt for event CH6LIMITH"] +pub type CH6LIMITH_R = crate::BitReader; +#[doc = "Write '1' to enable interrupt for event CH6LIMITH\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CH6LIMITH_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CH6LIMITH_A) -> Self { + variant as u8 != 0 + } +} +impl CH6LIMITH_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CH6LIMITH_A { + match self.bits { + false => CH6LIMITH_A::DISABLED, + true => CH6LIMITH_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == CH6LIMITH_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == CH6LIMITH_A::ENABLED + } +} +#[doc = "Write '1' to enable interrupt for event CH6LIMITH\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CH6LIMITH_AW { + #[doc = "1: Enable"] + SET = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CH6LIMITH_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CH6LIMITH` writer - Write '1' to enable interrupt for event CH6LIMITH"] +pub type CH6LIMITH_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENSET_SPEC, CH6LIMITH_AW, O>; +impl<'a, const O: u8> CH6LIMITH_W<'a, O> { + #[doc = "Enable"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(CH6LIMITH_AW::SET) + } +} +#[doc = "Field `CH6LIMITL` reader - Write '1' to enable interrupt for event CH6LIMITL"] +pub type CH6LIMITL_R = crate::BitReader; +#[doc = "Write '1' to enable interrupt for event CH6LIMITL\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CH6LIMITL_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CH6LIMITL_A) -> Self { + variant as u8 != 0 + } +} +impl CH6LIMITL_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CH6LIMITL_A { + match self.bits { + false => CH6LIMITL_A::DISABLED, + true => CH6LIMITL_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == CH6LIMITL_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == CH6LIMITL_A::ENABLED + } +} +#[doc = "Write '1' to enable interrupt for event CH6LIMITL\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CH6LIMITL_AW { + #[doc = "1: Enable"] + SET = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CH6LIMITL_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CH6LIMITL` writer - Write '1' to enable interrupt for event CH6LIMITL"] +pub type CH6LIMITL_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENSET_SPEC, CH6LIMITL_AW, O>; +impl<'a, const O: u8> CH6LIMITL_W<'a, O> { + #[doc = "Enable"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(CH6LIMITL_AW::SET) + } +} +#[doc = "Field `CH7LIMITH` reader - Write '1' to enable interrupt for event CH7LIMITH"] +pub type CH7LIMITH_R = crate::BitReader; +#[doc = "Write '1' to enable interrupt for event CH7LIMITH\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CH7LIMITH_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CH7LIMITH_A) -> Self { + variant as u8 != 0 + } +} +impl CH7LIMITH_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CH7LIMITH_A { + match self.bits { + false => CH7LIMITH_A::DISABLED, + true => CH7LIMITH_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == CH7LIMITH_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == CH7LIMITH_A::ENABLED + } +} +#[doc = "Write '1' to enable interrupt for event CH7LIMITH\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CH7LIMITH_AW { + #[doc = "1: Enable"] + SET = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CH7LIMITH_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CH7LIMITH` writer - Write '1' to enable interrupt for event CH7LIMITH"] +pub type CH7LIMITH_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENSET_SPEC, CH7LIMITH_AW, O>; +impl<'a, const O: u8> CH7LIMITH_W<'a, O> { + #[doc = "Enable"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(CH7LIMITH_AW::SET) + } +} +#[doc = "Field `CH7LIMITL` reader - Write '1' to enable interrupt for event CH7LIMITL"] +pub type CH7LIMITL_R = crate::BitReader; +#[doc = "Write '1' to enable interrupt for event CH7LIMITL\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CH7LIMITL_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CH7LIMITL_A) -> Self { + variant as u8 != 0 + } +} +impl CH7LIMITL_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CH7LIMITL_A { + match self.bits { + false => CH7LIMITL_A::DISABLED, + true => CH7LIMITL_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == CH7LIMITL_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == CH7LIMITL_A::ENABLED + } +} +#[doc = "Write '1' to enable interrupt for event CH7LIMITL\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CH7LIMITL_AW { + #[doc = "1: Enable"] + SET = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CH7LIMITL_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CH7LIMITL` writer - Write '1' to enable interrupt for event CH7LIMITL"] +pub type CH7LIMITL_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENSET_SPEC, CH7LIMITL_AW, O>; +impl<'a, const O: u8> CH7LIMITL_W<'a, O> { + #[doc = "Enable"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(CH7LIMITL_AW::SET) + } +} +impl R { + #[doc = "Bit 0 - Write '1' to enable interrupt for event STARTED"] + #[inline(always)] + pub fn started(&self) -> STARTED_R { + STARTED_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Write '1' to enable interrupt for event END"] + #[inline(always)] + pub fn end(&self) -> END_R { + END_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Write '1' to enable interrupt for event DONE"] + #[inline(always)] + pub fn done(&self) -> DONE_R { + DONE_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Write '1' to enable interrupt for event RESULTDONE"] + #[inline(always)] + pub fn resultdone(&self) -> RESULTDONE_R { + RESULTDONE_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Write '1' to enable interrupt for event CALIBRATEDONE"] + #[inline(always)] + pub fn calibratedone(&self) -> CALIBRATEDONE_R { + CALIBRATEDONE_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Write '1' to enable interrupt for event STOPPED"] + #[inline(always)] + pub fn stopped(&self) -> STOPPED_R { + STOPPED_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Write '1' to enable interrupt for event CH0LIMITH"] + #[inline(always)] + pub fn ch0limith(&self) -> CH0LIMITH_R { + CH0LIMITH_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Write '1' to enable interrupt for event CH0LIMITL"] + #[inline(always)] + pub fn ch0limitl(&self) -> CH0LIMITL_R { + CH0LIMITL_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Write '1' to enable interrupt for event CH1LIMITH"] + #[inline(always)] + pub fn ch1limith(&self) -> CH1LIMITH_R { + CH1LIMITH_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Write '1' to enable interrupt for event CH1LIMITL"] + #[inline(always)] + pub fn ch1limitl(&self) -> CH1LIMITL_R { + CH1LIMITL_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Write '1' to enable interrupt for event CH2LIMITH"] + #[inline(always)] + pub fn ch2limith(&self) -> CH2LIMITH_R { + CH2LIMITH_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Write '1' to enable interrupt for event CH2LIMITL"] + #[inline(always)] + pub fn ch2limitl(&self) -> CH2LIMITL_R { + CH2LIMITL_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Write '1' to enable interrupt for event CH3LIMITH"] + #[inline(always)] + pub fn ch3limith(&self) -> CH3LIMITH_R { + CH3LIMITH_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Write '1' to enable interrupt for event CH3LIMITL"] + #[inline(always)] + pub fn ch3limitl(&self) -> CH3LIMITL_R { + CH3LIMITL_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Write '1' to enable interrupt for event CH4LIMITH"] + #[inline(always)] + pub fn ch4limith(&self) -> CH4LIMITH_R { + CH4LIMITH_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Write '1' to enable interrupt for event CH4LIMITL"] + #[inline(always)] + pub fn ch4limitl(&self) -> CH4LIMITL_R { + CH4LIMITL_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - Write '1' to enable interrupt for event CH5LIMITH"] + #[inline(always)] + pub fn ch5limith(&self) -> CH5LIMITH_R { + CH5LIMITH_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Write '1' to enable interrupt for event CH5LIMITL"] + #[inline(always)] + pub fn ch5limitl(&self) -> CH5LIMITL_R { + CH5LIMITL_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Write '1' to enable interrupt for event CH6LIMITH"] + #[inline(always)] + pub fn ch6limith(&self) -> CH6LIMITH_R { + CH6LIMITH_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Write '1' to enable interrupt for event CH6LIMITL"] + #[inline(always)] + pub fn ch6limitl(&self) -> CH6LIMITL_R { + CH6LIMITL_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Write '1' to enable interrupt for event CH7LIMITH"] + #[inline(always)] + pub fn ch7limith(&self) -> CH7LIMITH_R { + CH7LIMITH_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Write '1' to enable interrupt for event CH7LIMITL"] + #[inline(always)] + pub fn ch7limitl(&self) -> CH7LIMITL_R { + CH7LIMITL_R::new(((self.bits >> 21) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Write '1' to enable interrupt for event STARTED"] + #[inline(always)] + pub fn started(&mut self) -> STARTED_W<0> { + STARTED_W::new(self) + } + #[doc = "Bit 1 - Write '1' to enable interrupt for event END"] + #[inline(always)] + pub fn end(&mut self) -> END_W<1> { + END_W::new(self) + } + #[doc = "Bit 2 - Write '1' to enable interrupt for event DONE"] + #[inline(always)] + pub fn done(&mut self) -> DONE_W<2> { + DONE_W::new(self) + } + #[doc = "Bit 3 - Write '1' to enable interrupt for event RESULTDONE"] + #[inline(always)] + pub fn resultdone(&mut self) -> RESULTDONE_W<3> { + RESULTDONE_W::new(self) + } + #[doc = "Bit 4 - Write '1' to enable interrupt for event CALIBRATEDONE"] + #[inline(always)] + pub fn calibratedone(&mut self) -> CALIBRATEDONE_W<4> { + CALIBRATEDONE_W::new(self) + } + #[doc = "Bit 5 - Write '1' to enable interrupt for event STOPPED"] + #[inline(always)] + pub fn stopped(&mut self) -> STOPPED_W<5> { + STOPPED_W::new(self) + } + #[doc = "Bit 6 - Write '1' to enable interrupt for event CH0LIMITH"] + #[inline(always)] + pub fn ch0limith(&mut self) -> CH0LIMITH_W<6> { + CH0LIMITH_W::new(self) + } + #[doc = "Bit 7 - Write '1' to enable interrupt for event CH0LIMITL"] + #[inline(always)] + pub fn ch0limitl(&mut self) -> CH0LIMITL_W<7> { + CH0LIMITL_W::new(self) + } + #[doc = "Bit 8 - Write '1' to enable interrupt for event CH1LIMITH"] + #[inline(always)] + pub fn ch1limith(&mut self) -> CH1LIMITH_W<8> { + CH1LIMITH_W::new(self) + } + #[doc = "Bit 9 - Write '1' to enable interrupt for event CH1LIMITL"] + #[inline(always)] + pub fn ch1limitl(&mut self) -> CH1LIMITL_W<9> { + CH1LIMITL_W::new(self) + } + #[doc = "Bit 10 - Write '1' to enable interrupt for event CH2LIMITH"] + #[inline(always)] + pub fn ch2limith(&mut self) -> CH2LIMITH_W<10> { + CH2LIMITH_W::new(self) + } + #[doc = "Bit 11 - Write '1' to enable interrupt for event CH2LIMITL"] + #[inline(always)] + pub fn ch2limitl(&mut self) -> CH2LIMITL_W<11> { + CH2LIMITL_W::new(self) + } + #[doc = "Bit 12 - Write '1' to enable interrupt for event CH3LIMITH"] + #[inline(always)] + pub fn ch3limith(&mut self) -> CH3LIMITH_W<12> { + CH3LIMITH_W::new(self) + } + #[doc = "Bit 13 - Write '1' to enable interrupt for event CH3LIMITL"] + #[inline(always)] + pub fn ch3limitl(&mut self) -> CH3LIMITL_W<13> { + CH3LIMITL_W::new(self) + } + #[doc = "Bit 14 - Write '1' to enable interrupt for event CH4LIMITH"] + #[inline(always)] + pub fn ch4limith(&mut self) -> CH4LIMITH_W<14> { + CH4LIMITH_W::new(self) + } + #[doc = "Bit 15 - Write '1' to enable interrupt for event CH4LIMITL"] + #[inline(always)] + pub fn ch4limitl(&mut self) -> CH4LIMITL_W<15> { + CH4LIMITL_W::new(self) + } + #[doc = "Bit 16 - Write '1' to enable interrupt for event CH5LIMITH"] + #[inline(always)] + pub fn ch5limith(&mut self) -> CH5LIMITH_W<16> { + CH5LIMITH_W::new(self) + } + #[doc = "Bit 17 - Write '1' to enable interrupt for event CH5LIMITL"] + #[inline(always)] + pub fn ch5limitl(&mut self) -> CH5LIMITL_W<17> { + CH5LIMITL_W::new(self) + } + #[doc = "Bit 18 - Write '1' to enable interrupt for event CH6LIMITH"] + #[inline(always)] + pub fn ch6limith(&mut self) -> CH6LIMITH_W<18> { + CH6LIMITH_W::new(self) + } + #[doc = "Bit 19 - Write '1' to enable interrupt for event CH6LIMITL"] + #[inline(always)] + pub fn ch6limitl(&mut self) -> CH6LIMITL_W<19> { + CH6LIMITL_W::new(self) + } + #[doc = "Bit 20 - Write '1' to enable interrupt for event CH7LIMITH"] + #[inline(always)] + pub fn ch7limith(&mut self) -> CH7LIMITH_W<20> { + CH7LIMITH_W::new(self) + } + #[doc = "Bit 21 - Write '1' to enable interrupt for event CH7LIMITL"] + #[inline(always)] + pub fn ch7limitl(&mut self) -> CH7LIMITL_W<21> { + CH7LIMITL_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Enable interrupt\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/saadc_ns/oversample.rs b/pacs/nrf9120-pac/src/saadc_ns/oversample.rs new file mode 100644 index 00000000..e07aa48e --- /dev/null +++ b/pacs/nrf9120-pac/src/saadc_ns/oversample.rs @@ -0,0 +1,220 @@ +#[doc = "Register `OVERSAMPLE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `OVERSAMPLE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `OVERSAMPLE` reader - Oversample control"] +pub type OVERSAMPLE_R = crate::FieldReader; +#[doc = "Oversample control\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum OVERSAMPLE_A { + #[doc = "0: Bypass oversampling"] + BYPASS = 0, + #[doc = "1: Oversample 2x"] + OVER2X = 1, + #[doc = "2: Oversample 4x"] + OVER4X = 2, + #[doc = "3: Oversample 8x"] + OVER8X = 3, + #[doc = "4: Oversample 16x"] + OVER16X = 4, + #[doc = "5: Oversample 32x"] + OVER32X = 5, + #[doc = "6: Oversample 64x"] + OVER64X = 6, + #[doc = "7: Oversample 128x"] + OVER128X = 7, + #[doc = "8: Oversample 256x"] + OVER256X = 8, +} +impl From for u8 { + #[inline(always)] + fn from(variant: OVERSAMPLE_A) -> Self { + variant as _ + } +} +impl OVERSAMPLE_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(OVERSAMPLE_A::BYPASS), + 1 => Some(OVERSAMPLE_A::OVER2X), + 2 => Some(OVERSAMPLE_A::OVER4X), + 3 => Some(OVERSAMPLE_A::OVER8X), + 4 => Some(OVERSAMPLE_A::OVER16X), + 5 => Some(OVERSAMPLE_A::OVER32X), + 6 => Some(OVERSAMPLE_A::OVER64X), + 7 => Some(OVERSAMPLE_A::OVER128X), + 8 => Some(OVERSAMPLE_A::OVER256X), + _ => None, + } + } + #[doc = "Checks if the value of the field is `BYPASS`"] + #[inline(always)] + pub fn is_bypass(&self) -> bool { + *self == OVERSAMPLE_A::BYPASS + } + #[doc = "Checks if the value of the field is `OVER2X`"] + #[inline(always)] + pub fn is_over2x(&self) -> bool { + *self == OVERSAMPLE_A::OVER2X + } + #[doc = "Checks if the value of the field is `OVER4X`"] + #[inline(always)] + pub fn is_over4x(&self) -> bool { + *self == OVERSAMPLE_A::OVER4X + } + #[doc = "Checks if the value of the field is `OVER8X`"] + #[inline(always)] + pub fn is_over8x(&self) -> bool { + *self == OVERSAMPLE_A::OVER8X + } + #[doc = "Checks if the value of the field is `OVER16X`"] + #[inline(always)] + pub fn is_over16x(&self) -> bool { + *self == OVERSAMPLE_A::OVER16X + } + #[doc = "Checks if the value of the field is `OVER32X`"] + #[inline(always)] + pub fn is_over32x(&self) -> bool { + *self == OVERSAMPLE_A::OVER32X + } + #[doc = "Checks if the value of the field is `OVER64X`"] + #[inline(always)] + pub fn is_over64x(&self) -> bool { + *self == OVERSAMPLE_A::OVER64X + } + #[doc = "Checks if the value of the field is `OVER128X`"] + #[inline(always)] + pub fn is_over128x(&self) -> bool { + *self == OVERSAMPLE_A::OVER128X + } + #[doc = "Checks if the value of the field is `OVER256X`"] + #[inline(always)] + pub fn is_over256x(&self) -> bool { + *self == OVERSAMPLE_A::OVER256X + } +} +#[doc = "Field `OVERSAMPLE` writer - Oversample control"] +pub type OVERSAMPLE_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, OVERSAMPLE_SPEC, u8, OVERSAMPLE_A, 4, O>; +impl<'a, const O: u8> OVERSAMPLE_W<'a, O> { + #[doc = "Bypass oversampling"] + #[inline(always)] + pub fn bypass(self) -> &'a mut W { + self.variant(OVERSAMPLE_A::BYPASS) + } + #[doc = "Oversample 2x"] + #[inline(always)] + pub fn over2x(self) -> &'a mut W { + self.variant(OVERSAMPLE_A::OVER2X) + } + #[doc = "Oversample 4x"] + #[inline(always)] + pub fn over4x(self) -> &'a mut W { + self.variant(OVERSAMPLE_A::OVER4X) + } + #[doc = "Oversample 8x"] + #[inline(always)] + pub fn over8x(self) -> &'a mut W { + self.variant(OVERSAMPLE_A::OVER8X) + } + #[doc = "Oversample 16x"] + #[inline(always)] + pub fn over16x(self) -> &'a mut W { + self.variant(OVERSAMPLE_A::OVER16X) + } + #[doc = "Oversample 32x"] + #[inline(always)] + pub fn over32x(self) -> &'a mut W { + self.variant(OVERSAMPLE_A::OVER32X) + } + #[doc = "Oversample 64x"] + #[inline(always)] + pub fn over64x(self) -> &'a mut W { + self.variant(OVERSAMPLE_A::OVER64X) + } + #[doc = "Oversample 128x"] + #[inline(always)] + pub fn over128x(self) -> &'a mut W { + self.variant(OVERSAMPLE_A::OVER128X) + } + #[doc = "Oversample 256x"] + #[inline(always)] + pub fn over256x(self) -> &'a mut W { + self.variant(OVERSAMPLE_A::OVER256X) + } +} +impl R { + #[doc = "Bits 0:3 - Oversample control"] + #[inline(always)] + pub fn oversample(&self) -> OVERSAMPLE_R { + OVERSAMPLE_R::new((self.bits & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - Oversample control"] + #[inline(always)] + pub fn oversample(&mut self) -> OVERSAMPLE_W<0> { + OVERSAMPLE_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Oversampling configuration. OVERSAMPLE should not be combined with SCAN. The RESOLUTION is applied before averaging, thus for high OVERSAMPLE a higher RESOLUTION should be used.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [oversample](index.html) module"] +pub struct OVERSAMPLE_SPEC; +impl crate::RegisterSpec for OVERSAMPLE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [oversample::R](R) reader structure"] +impl crate::Readable for OVERSAMPLE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [oversample::W](W) writer structure"] +impl crate::Writable for OVERSAMPLE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets OVERSAMPLE to value 0"] +impl crate::Resettable for OVERSAMPLE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/saadc_ns/publish_calibratedone.rs b/pacs/nrf9120-pac/src/saadc_ns/publish_calibratedone.rs new file mode 100644 index 00000000..7dfec538 --- /dev/null +++ b/pacs/nrf9120-pac/src/saadc_ns/publish_calibratedone.rs @@ -0,0 +1,141 @@ +#[doc = "Register `PUBLISH_CALIBRATEDONE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PUBLISH_CALIBRATEDONE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CHIDX` reader - DPPI channel that event CALIBRATEDONE will publish to"] +pub type CHIDX_R = crate::FieldReader; +#[doc = "Field `CHIDX` writer - DPPI channel that event CALIBRATEDONE will publish to"] +pub type CHIDX_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, PUBLISH_CALIBRATEDONE_SPEC, u8, u8, 8, O>; +#[doc = "Field `EN` reader - "] +pub type EN_R = crate::BitReader; +#[doc = "\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum EN_A { + #[doc = "0: Disable publishing"] + DISABLED = 0, + #[doc = "1: Enable publishing"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: EN_A) -> Self { + variant as u8 != 0 + } +} +impl EN_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EN_A { + match self.bits { + false => EN_A::DISABLED, + true => EN_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == EN_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == EN_A::ENABLED + } +} +#[doc = "Field `EN` writer - "] +pub type EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, PUBLISH_CALIBRATEDONE_SPEC, EN_A, O>; +impl<'a, const O: u8> EN_W<'a, O> { + #[doc = "Disable publishing"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(EN_A::DISABLED) + } + #[doc = "Enable publishing"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(EN_A::ENABLED) + } +} +impl R { + #[doc = "Bits 0:7 - DPPI channel that event CALIBRATEDONE will publish to"] + #[inline(always)] + pub fn chidx(&self) -> CHIDX_R { + CHIDX_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&self) -> EN_R { + EN_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:7 - DPPI channel that event CALIBRATEDONE will publish to"] + #[inline(always)] + pub fn chidx(&mut self) -> CHIDX_W<0> { + CHIDX_W::new(self) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&mut self) -> EN_W<31> { + EN_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Publish configuration for event CALIBRATEDONE\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [publish_calibratedone](index.html) module"] +pub struct PUBLISH_CALIBRATEDONE_SPEC; +impl crate::RegisterSpec for PUBLISH_CALIBRATEDONE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [publish_calibratedone::R](R) reader structure"] +impl crate::Readable for PUBLISH_CALIBRATEDONE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [publish_calibratedone::W](W) writer structure"] +impl crate::Writable for PUBLISH_CALIBRATEDONE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PUBLISH_CALIBRATEDONE to value 0"] +impl crate::Resettable for PUBLISH_CALIBRATEDONE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/saadc_ns/publish_ch.rs b/pacs/nrf9120-pac/src/saadc_ns/publish_ch.rs new file mode 100644 index 00000000..3f666021 --- /dev/null +++ b/pacs/nrf9120-pac/src/saadc_ns/publish_ch.rs @@ -0,0 +1,16 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct PUBLISH_CH { + #[doc = "0x00 - Description cluster: Publish configuration for event CH\\[n\\].LIMITH"] + pub limith: LIMITH, + #[doc = "0x04 - Description cluster: Publish configuration for event CH\\[n\\].LIMITL"] + pub limitl: LIMITL, +} +#[doc = "LIMITH (rw) register accessor: an alias for `Reg`"] +pub type LIMITH = crate::Reg; +#[doc = "Description cluster: Publish configuration for event CH\\[n\\].LIMITH"] +pub mod limith; +#[doc = "LIMITL (rw) register accessor: an alias for `Reg`"] +pub type LIMITL = crate::Reg; +#[doc = "Description cluster: Publish configuration for event CH\\[n\\].LIMITL"] +pub mod limitl; diff --git a/pacs/nrf9120-pac/src/saadc_ns/publish_ch/limith.rs b/pacs/nrf9120-pac/src/saadc_ns/publish_ch/limith.rs new file mode 100644 index 00000000..ab0a96bc --- /dev/null +++ b/pacs/nrf9120-pac/src/saadc_ns/publish_ch/limith.rs @@ -0,0 +1,140 @@ +#[doc = "Register `LIMITH` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `LIMITH` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CHIDX` reader - DPPI channel that event CH\\[n\\].LIMITH will publish to"] +pub type CHIDX_R = crate::FieldReader; +#[doc = "Field `CHIDX` writer - DPPI channel that event CH\\[n\\].LIMITH will publish to"] +pub type CHIDX_W<'a, const O: u8> = crate::FieldWriter<'a, u32, LIMITH_SPEC, u8, u8, 8, O>; +#[doc = "Field `EN` reader - "] +pub type EN_R = crate::BitReader; +#[doc = "\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum EN_A { + #[doc = "0: Disable publishing"] + DISABLED = 0, + #[doc = "1: Enable publishing"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: EN_A) -> Self { + variant as u8 != 0 + } +} +impl EN_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EN_A { + match self.bits { + false => EN_A::DISABLED, + true => EN_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == EN_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == EN_A::ENABLED + } +} +#[doc = "Field `EN` writer - "] +pub type EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, LIMITH_SPEC, EN_A, O>; +impl<'a, const O: u8> EN_W<'a, O> { + #[doc = "Disable publishing"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(EN_A::DISABLED) + } + #[doc = "Enable publishing"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(EN_A::ENABLED) + } +} +impl R { + #[doc = "Bits 0:7 - DPPI channel that event CH\\[n\\].LIMITH will publish to"] + #[inline(always)] + pub fn chidx(&self) -> CHIDX_R { + CHIDX_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&self) -> EN_R { + EN_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:7 - DPPI channel that event CH\\[n\\].LIMITH will publish to"] + #[inline(always)] + pub fn chidx(&mut self) -> CHIDX_W<0> { + CHIDX_W::new(self) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&mut self) -> EN_W<31> { + EN_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Description cluster: Publish configuration for event CH\\[n\\].LIMITH\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [limith](index.html) module"] +pub struct LIMITH_SPEC; +impl crate::RegisterSpec for LIMITH_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [limith::R](R) reader structure"] +impl crate::Readable for LIMITH_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [limith::W](W) writer structure"] +impl crate::Writable for LIMITH_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets LIMITH to value 0"] +impl crate::Resettable for LIMITH_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/saadc_ns/publish_ch/limitl.rs b/pacs/nrf9120-pac/src/saadc_ns/publish_ch/limitl.rs new file mode 100644 index 00000000..92bda542 --- /dev/null +++ b/pacs/nrf9120-pac/src/saadc_ns/publish_ch/limitl.rs @@ -0,0 +1,140 @@ +#[doc = "Register `LIMITL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `LIMITL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CHIDX` reader - DPPI channel that event CH\\[n\\].LIMITL will publish to"] +pub type CHIDX_R = crate::FieldReader; +#[doc = "Field `CHIDX` writer - DPPI channel that event CH\\[n\\].LIMITL will publish to"] +pub type CHIDX_W<'a, const O: u8> = crate::FieldWriter<'a, u32, LIMITL_SPEC, u8, u8, 8, O>; +#[doc = "Field `EN` reader - "] +pub type EN_R = crate::BitReader; +#[doc = "\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum EN_A { + #[doc = "0: Disable publishing"] + DISABLED = 0, + #[doc = "1: Enable publishing"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: EN_A) -> Self { + variant as u8 != 0 + } +} +impl EN_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EN_A { + match self.bits { + false => EN_A::DISABLED, + true => EN_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == EN_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == EN_A::ENABLED + } +} +#[doc = "Field `EN` writer - "] +pub type EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, LIMITL_SPEC, EN_A, O>; +impl<'a, const O: u8> EN_W<'a, O> { + #[doc = "Disable publishing"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(EN_A::DISABLED) + } + #[doc = "Enable publishing"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(EN_A::ENABLED) + } +} +impl R { + #[doc = "Bits 0:7 - DPPI channel that event CH\\[n\\].LIMITL will publish to"] + #[inline(always)] + pub fn chidx(&self) -> CHIDX_R { + CHIDX_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&self) -> EN_R { + EN_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:7 - DPPI channel that event CH\\[n\\].LIMITL will publish to"] + #[inline(always)] + pub fn chidx(&mut self) -> CHIDX_W<0> { + CHIDX_W::new(self) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&mut self) -> EN_W<31> { + EN_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Description cluster: Publish configuration for event CH\\[n\\].LIMITL\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [limitl](index.html) module"] +pub struct LIMITL_SPEC; +impl crate::RegisterSpec for LIMITL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [limitl::R](R) reader structure"] +impl crate::Readable for LIMITL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [limitl::W](W) writer structure"] +impl crate::Writable for LIMITL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets LIMITL to value 0"] +impl crate::Resettable for LIMITL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/saadc_ns/publish_done.rs b/pacs/nrf9120-pac/src/saadc_ns/publish_done.rs new file mode 100644 index 00000000..2d1a231c --- /dev/null +++ b/pacs/nrf9120-pac/src/saadc_ns/publish_done.rs @@ -0,0 +1,140 @@ +#[doc = "Register `PUBLISH_DONE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PUBLISH_DONE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CHIDX` reader - DPPI channel that event DONE will publish to"] +pub type CHIDX_R = crate::FieldReader; +#[doc = "Field `CHIDX` writer - DPPI channel that event DONE will publish to"] +pub type CHIDX_W<'a, const O: u8> = crate::FieldWriter<'a, u32, PUBLISH_DONE_SPEC, u8, u8, 8, O>; +#[doc = "Field `EN` reader - "] +pub type EN_R = crate::BitReader; +#[doc = "\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum EN_A { + #[doc = "0: Disable publishing"] + DISABLED = 0, + #[doc = "1: Enable publishing"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: EN_A) -> Self { + variant as u8 != 0 + } +} +impl EN_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EN_A { + match self.bits { + false => EN_A::DISABLED, + true => EN_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == EN_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == EN_A::ENABLED + } +} +#[doc = "Field `EN` writer - "] +pub type EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, PUBLISH_DONE_SPEC, EN_A, O>; +impl<'a, const O: u8> EN_W<'a, O> { + #[doc = "Disable publishing"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(EN_A::DISABLED) + } + #[doc = "Enable publishing"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(EN_A::ENABLED) + } +} +impl R { + #[doc = "Bits 0:7 - DPPI channel that event DONE will publish to"] + #[inline(always)] + pub fn chidx(&self) -> CHIDX_R { + CHIDX_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&self) -> EN_R { + EN_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:7 - DPPI channel that event DONE will publish to"] + #[inline(always)] + pub fn chidx(&mut self) -> CHIDX_W<0> { + CHIDX_W::new(self) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&mut self) -> EN_W<31> { + EN_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Publish configuration for event DONE\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [publish_done](index.html) module"] +pub struct PUBLISH_DONE_SPEC; +impl crate::RegisterSpec for PUBLISH_DONE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [publish_done::R](R) reader structure"] +impl crate::Readable for PUBLISH_DONE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [publish_done::W](W) writer structure"] +impl crate::Writable for PUBLISH_DONE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PUBLISH_DONE to value 0"] +impl crate::Resettable for PUBLISH_DONE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/saadc_ns/publish_end.rs b/pacs/nrf9120-pac/src/saadc_ns/publish_end.rs new file mode 100644 index 00000000..2006d5cf --- /dev/null +++ b/pacs/nrf9120-pac/src/saadc_ns/publish_end.rs @@ -0,0 +1,140 @@ +#[doc = "Register `PUBLISH_END` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PUBLISH_END` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CHIDX` reader - DPPI channel that event END will publish to"] +pub type CHIDX_R = crate::FieldReader; +#[doc = "Field `CHIDX` writer - DPPI channel that event END will publish to"] +pub type CHIDX_W<'a, const O: u8> = crate::FieldWriter<'a, u32, PUBLISH_END_SPEC, u8, u8, 8, O>; +#[doc = "Field `EN` reader - "] +pub type EN_R = crate::BitReader; +#[doc = "\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum EN_A { + #[doc = "0: Disable publishing"] + DISABLED = 0, + #[doc = "1: Enable publishing"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: EN_A) -> Self { + variant as u8 != 0 + } +} +impl EN_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EN_A { + match self.bits { + false => EN_A::DISABLED, + true => EN_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == EN_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == EN_A::ENABLED + } +} +#[doc = "Field `EN` writer - "] +pub type EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, PUBLISH_END_SPEC, EN_A, O>; +impl<'a, const O: u8> EN_W<'a, O> { + #[doc = "Disable publishing"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(EN_A::DISABLED) + } + #[doc = "Enable publishing"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(EN_A::ENABLED) + } +} +impl R { + #[doc = "Bits 0:7 - DPPI channel that event END will publish to"] + #[inline(always)] + pub fn chidx(&self) -> CHIDX_R { + CHIDX_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&self) -> EN_R { + EN_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:7 - DPPI channel that event END will publish to"] + #[inline(always)] + pub fn chidx(&mut self) -> CHIDX_W<0> { + CHIDX_W::new(self) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&mut self) -> EN_W<31> { + EN_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Publish configuration for event END\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [publish_end](index.html) module"] +pub struct PUBLISH_END_SPEC; +impl crate::RegisterSpec for PUBLISH_END_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [publish_end::R](R) reader structure"] +impl crate::Readable for PUBLISH_END_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [publish_end::W](W) writer structure"] +impl crate::Writable for PUBLISH_END_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PUBLISH_END to value 0"] +impl crate::Resettable for PUBLISH_END_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/saadc_ns/publish_resultdone.rs b/pacs/nrf9120-pac/src/saadc_ns/publish_resultdone.rs new file mode 100644 index 00000000..5cf7ada8 --- /dev/null +++ b/pacs/nrf9120-pac/src/saadc_ns/publish_resultdone.rs @@ -0,0 +1,141 @@ +#[doc = "Register `PUBLISH_RESULTDONE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PUBLISH_RESULTDONE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CHIDX` reader - DPPI channel that event RESULTDONE will publish to"] +pub type CHIDX_R = crate::FieldReader; +#[doc = "Field `CHIDX` writer - DPPI channel that event RESULTDONE will publish to"] +pub type CHIDX_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, PUBLISH_RESULTDONE_SPEC, u8, u8, 8, O>; +#[doc = "Field `EN` reader - "] +pub type EN_R = crate::BitReader; +#[doc = "\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum EN_A { + #[doc = "0: Disable publishing"] + DISABLED = 0, + #[doc = "1: Enable publishing"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: EN_A) -> Self { + variant as u8 != 0 + } +} +impl EN_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EN_A { + match self.bits { + false => EN_A::DISABLED, + true => EN_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == EN_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == EN_A::ENABLED + } +} +#[doc = "Field `EN` writer - "] +pub type EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, PUBLISH_RESULTDONE_SPEC, EN_A, O>; +impl<'a, const O: u8> EN_W<'a, O> { + #[doc = "Disable publishing"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(EN_A::DISABLED) + } + #[doc = "Enable publishing"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(EN_A::ENABLED) + } +} +impl R { + #[doc = "Bits 0:7 - DPPI channel that event RESULTDONE will publish to"] + #[inline(always)] + pub fn chidx(&self) -> CHIDX_R { + CHIDX_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&self) -> EN_R { + EN_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:7 - DPPI channel that event RESULTDONE will publish to"] + #[inline(always)] + pub fn chidx(&mut self) -> CHIDX_W<0> { + CHIDX_W::new(self) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&mut self) -> EN_W<31> { + EN_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Publish configuration for event RESULTDONE\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [publish_resultdone](index.html) module"] +pub struct PUBLISH_RESULTDONE_SPEC; +impl crate::RegisterSpec for PUBLISH_RESULTDONE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [publish_resultdone::R](R) reader structure"] +impl crate::Readable for PUBLISH_RESULTDONE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [publish_resultdone::W](W) writer structure"] +impl crate::Writable for PUBLISH_RESULTDONE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PUBLISH_RESULTDONE to value 0"] +impl crate::Resettable for PUBLISH_RESULTDONE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/saadc_ns/publish_started.rs b/pacs/nrf9120-pac/src/saadc_ns/publish_started.rs new file mode 100644 index 00000000..1b0354ef --- /dev/null +++ b/pacs/nrf9120-pac/src/saadc_ns/publish_started.rs @@ -0,0 +1,140 @@ +#[doc = "Register `PUBLISH_STARTED` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PUBLISH_STARTED` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CHIDX` reader - DPPI channel that event STARTED will publish to"] +pub type CHIDX_R = crate::FieldReader; +#[doc = "Field `CHIDX` writer - DPPI channel that event STARTED will publish to"] +pub type CHIDX_W<'a, const O: u8> = crate::FieldWriter<'a, u32, PUBLISH_STARTED_SPEC, u8, u8, 8, O>; +#[doc = "Field `EN` reader - "] +pub type EN_R = crate::BitReader; +#[doc = "\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum EN_A { + #[doc = "0: Disable publishing"] + DISABLED = 0, + #[doc = "1: Enable publishing"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: EN_A) -> Self { + variant as u8 != 0 + } +} +impl EN_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EN_A { + match self.bits { + false => EN_A::DISABLED, + true => EN_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == EN_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == EN_A::ENABLED + } +} +#[doc = "Field `EN` writer - "] +pub type EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, PUBLISH_STARTED_SPEC, EN_A, O>; +impl<'a, const O: u8> EN_W<'a, O> { + #[doc = "Disable publishing"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(EN_A::DISABLED) + } + #[doc = "Enable publishing"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(EN_A::ENABLED) + } +} +impl R { + #[doc = "Bits 0:7 - DPPI channel that event STARTED will publish to"] + #[inline(always)] + pub fn chidx(&self) -> CHIDX_R { + CHIDX_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&self) -> EN_R { + EN_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:7 - DPPI channel that event STARTED will publish to"] + #[inline(always)] + pub fn chidx(&mut self) -> CHIDX_W<0> { + CHIDX_W::new(self) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&mut self) -> EN_W<31> { + EN_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Publish configuration for event STARTED\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [publish_started](index.html) module"] +pub struct PUBLISH_STARTED_SPEC; +impl crate::RegisterSpec for PUBLISH_STARTED_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [publish_started::R](R) reader structure"] +impl crate::Readable for PUBLISH_STARTED_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [publish_started::W](W) writer structure"] +impl crate::Writable for PUBLISH_STARTED_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PUBLISH_STARTED to value 0"] +impl crate::Resettable for PUBLISH_STARTED_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/saadc_ns/publish_stopped.rs b/pacs/nrf9120-pac/src/saadc_ns/publish_stopped.rs new file mode 100644 index 00000000..247f50bf --- /dev/null +++ b/pacs/nrf9120-pac/src/saadc_ns/publish_stopped.rs @@ -0,0 +1,140 @@ +#[doc = "Register `PUBLISH_STOPPED` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PUBLISH_STOPPED` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CHIDX` reader - DPPI channel that event STOPPED will publish to"] +pub type CHIDX_R = crate::FieldReader; +#[doc = "Field `CHIDX` writer - DPPI channel that event STOPPED will publish to"] +pub type CHIDX_W<'a, const O: u8> = crate::FieldWriter<'a, u32, PUBLISH_STOPPED_SPEC, u8, u8, 8, O>; +#[doc = "Field `EN` reader - "] +pub type EN_R = crate::BitReader; +#[doc = "\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum EN_A { + #[doc = "0: Disable publishing"] + DISABLED = 0, + #[doc = "1: Enable publishing"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: EN_A) -> Self { + variant as u8 != 0 + } +} +impl EN_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EN_A { + match self.bits { + false => EN_A::DISABLED, + true => EN_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == EN_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == EN_A::ENABLED + } +} +#[doc = "Field `EN` writer - "] +pub type EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, PUBLISH_STOPPED_SPEC, EN_A, O>; +impl<'a, const O: u8> EN_W<'a, O> { + #[doc = "Disable publishing"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(EN_A::DISABLED) + } + #[doc = "Enable publishing"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(EN_A::ENABLED) + } +} +impl R { + #[doc = "Bits 0:7 - DPPI channel that event STOPPED will publish to"] + #[inline(always)] + pub fn chidx(&self) -> CHIDX_R { + CHIDX_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&self) -> EN_R { + EN_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:7 - DPPI channel that event STOPPED will publish to"] + #[inline(always)] + pub fn chidx(&mut self) -> CHIDX_W<0> { + CHIDX_W::new(self) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&mut self) -> EN_W<31> { + EN_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Publish configuration for event STOPPED\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [publish_stopped](index.html) module"] +pub struct PUBLISH_STOPPED_SPEC; +impl crate::RegisterSpec for PUBLISH_STOPPED_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [publish_stopped::R](R) reader structure"] +impl crate::Readable for PUBLISH_STOPPED_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [publish_stopped::W](W) writer structure"] +impl crate::Writable for PUBLISH_STOPPED_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PUBLISH_STOPPED to value 0"] +impl crate::Resettable for PUBLISH_STOPPED_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/saadc_ns/resolution.rs b/pacs/nrf9120-pac/src/saadc_ns/resolution.rs new file mode 100644 index 00000000..672e257c --- /dev/null +++ b/pacs/nrf9120-pac/src/saadc_ns/resolution.rs @@ -0,0 +1,154 @@ +#[doc = "Register `RESOLUTION` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `RESOLUTION` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `VAL` reader - Set the resolution"] +pub type VAL_R = crate::FieldReader; +#[doc = "Set the resolution\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum VAL_A { + #[doc = "0: 8 bit"] + _8BIT = 0, + #[doc = "1: 10 bit"] + _10BIT = 1, + #[doc = "2: 12 bit"] + _12BIT = 2, + #[doc = "3: 14 bit"] + _14BIT = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: VAL_A) -> Self { + variant as _ + } +} +impl VAL_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(VAL_A::_8BIT), + 1 => Some(VAL_A::_10BIT), + 2 => Some(VAL_A::_12BIT), + 3 => Some(VAL_A::_14BIT), + _ => None, + } + } + #[doc = "Checks if the value of the field is `_8BIT`"] + #[inline(always)] + pub fn is_8bit(&self) -> bool { + *self == VAL_A::_8BIT + } + #[doc = "Checks if the value of the field is `_10BIT`"] + #[inline(always)] + pub fn is_10bit(&self) -> bool { + *self == VAL_A::_10BIT + } + #[doc = "Checks if the value of the field is `_12BIT`"] + #[inline(always)] + pub fn is_12bit(&self) -> bool { + *self == VAL_A::_12BIT + } + #[doc = "Checks if the value of the field is `_14BIT`"] + #[inline(always)] + pub fn is_14bit(&self) -> bool { + *self == VAL_A::_14BIT + } +} +#[doc = "Field `VAL` writer - Set the resolution"] +pub type VAL_W<'a, const O: u8> = crate::FieldWriter<'a, u32, RESOLUTION_SPEC, u8, VAL_A, 3, O>; +impl<'a, const O: u8> VAL_W<'a, O> { + #[doc = "8 bit"] + #[inline(always)] + pub fn _8bit(self) -> &'a mut W { + self.variant(VAL_A::_8BIT) + } + #[doc = "10 bit"] + #[inline(always)] + pub fn _10bit(self) -> &'a mut W { + self.variant(VAL_A::_10BIT) + } + #[doc = "12 bit"] + #[inline(always)] + pub fn _12bit(self) -> &'a mut W { + self.variant(VAL_A::_12BIT) + } + #[doc = "14 bit"] + #[inline(always)] + pub fn _14bit(self) -> &'a mut W { + self.variant(VAL_A::_14BIT) + } +} +impl R { + #[doc = "Bits 0:2 - Set the resolution"] + #[inline(always)] + pub fn val(&self) -> VAL_R { + VAL_R::new((self.bits & 7) as u8) + } +} +impl W { + #[doc = "Bits 0:2 - Set the resolution"] + #[inline(always)] + pub fn val(&mut self) -> VAL_W<0> { + VAL_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Resolution configuration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [resolution](index.html) module"] +pub struct RESOLUTION_SPEC; +impl crate::RegisterSpec for RESOLUTION_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [resolution::R](R) reader structure"] +impl crate::Readable for RESOLUTION_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [resolution::W](W) writer structure"] +impl crate::Writable for RESOLUTION_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets RESOLUTION to value 0x01"] +impl crate::Resettable for RESOLUTION_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x01 + } +} diff --git a/pacs/nrf9120-pac/src/saadc_ns/result.rs b/pacs/nrf9120-pac/src/saadc_ns/result.rs new file mode 100644 index 00000000..719c5f5d --- /dev/null +++ b/pacs/nrf9120-pac/src/saadc_ns/result.rs @@ -0,0 +1,22 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RESULT { + #[doc = "0x00 - Data pointer"] + pub ptr: PTR, + #[doc = "0x04 - Maximum number of buffer words to transfer"] + pub maxcnt: MAXCNT, + #[doc = "0x08 - Number of buffer words transferred since last START"] + pub amount: AMOUNT, +} +#[doc = "PTR (rw) register accessor: an alias for `Reg`"] +pub type PTR = crate::Reg; +#[doc = "Data pointer"] +pub mod ptr; +#[doc = "MAXCNT (rw) register accessor: an alias for `Reg`"] +pub type MAXCNT = crate::Reg; +#[doc = "Maximum number of buffer words to transfer"] +pub mod maxcnt; +#[doc = "AMOUNT (r) register accessor: an alias for `Reg`"] +pub type AMOUNT = crate::Reg; +#[doc = "Number of buffer words transferred since last START"] +pub mod amount; diff --git a/pacs/nrf9120-pac/src/saadc_ns/result/amount.rs b/pacs/nrf9120-pac/src/saadc_ns/result/amount.rs new file mode 100644 index 00000000..631f70ac --- /dev/null +++ b/pacs/nrf9120-pac/src/saadc_ns/result/amount.rs @@ -0,0 +1,40 @@ +#[doc = "Register `AMOUNT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `AMOUNT` reader - Number of buffer words transferred since last START. This register can be read after an END or STOPPED event."] +pub type AMOUNT_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:14 - Number of buffer words transferred since last START. This register can be read after an END or STOPPED event."] + #[inline(always)] + pub fn amount(&self) -> AMOUNT_R { + AMOUNT_R::new((self.bits & 0x7fff) as u16) + } +} +#[doc = "Number of buffer words transferred since last START\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [amount](index.html) module"] +pub struct AMOUNT_SPEC; +impl crate::RegisterSpec for AMOUNT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [amount::R](R) reader structure"] +impl crate::Readable for AMOUNT_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets AMOUNT to value 0"] +impl crate::Resettable for AMOUNT_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/saadc_ns/result/maxcnt.rs b/pacs/nrf9120-pac/src/saadc_ns/result/maxcnt.rs new file mode 100644 index 00000000..1f68bdeb --- /dev/null +++ b/pacs/nrf9120-pac/src/saadc_ns/result/maxcnt.rs @@ -0,0 +1,80 @@ +#[doc = "Register `MAXCNT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `MAXCNT` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `MAXCNT` reader - Maximum number of buffer words to transfer"] +pub type MAXCNT_R = crate::FieldReader; +#[doc = "Field `MAXCNT` writer - Maximum number of buffer words to transfer"] +pub type MAXCNT_W<'a, const O: u8> = crate::FieldWriter<'a, u32, MAXCNT_SPEC, u16, u16, 15, O>; +impl R { + #[doc = "Bits 0:14 - Maximum number of buffer words to transfer"] + #[inline(always)] + pub fn maxcnt(&self) -> MAXCNT_R { + MAXCNT_R::new((self.bits & 0x7fff) as u16) + } +} +impl W { + #[doc = "Bits 0:14 - Maximum number of buffer words to transfer"] + #[inline(always)] + pub fn maxcnt(&mut self) -> MAXCNT_W<0> { + MAXCNT_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Maximum number of buffer words to transfer\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [maxcnt](index.html) module"] +pub struct MAXCNT_SPEC; +impl crate::RegisterSpec for MAXCNT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [maxcnt::R](R) reader structure"] +impl crate::Readable for MAXCNT_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [maxcnt::W](W) writer structure"] +impl crate::Writable for MAXCNT_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets MAXCNT to value 0"] +impl crate::Resettable for MAXCNT_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/saadc_ns/result/ptr.rs b/pacs/nrf9120-pac/src/saadc_ns/result/ptr.rs new file mode 100644 index 00000000..d5f98439 --- /dev/null +++ b/pacs/nrf9120-pac/src/saadc_ns/result/ptr.rs @@ -0,0 +1,80 @@ +#[doc = "Register `PTR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PTR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PTR` reader - Data pointer"] +pub type PTR_R = crate::FieldReader; +#[doc = "Field `PTR` writer - Data pointer"] +pub type PTR_W<'a, const O: u8> = crate::FieldWriter<'a, u32, PTR_SPEC, u32, u32, 32, O>; +impl R { + #[doc = "Bits 0:31 - Data pointer"] + #[inline(always)] + pub fn ptr(&self) -> PTR_R { + PTR_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Data pointer"] + #[inline(always)] + pub fn ptr(&mut self) -> PTR_W<0> { + PTR_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Data pointer\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ptr](index.html) module"] +pub struct PTR_SPEC; +impl crate::RegisterSpec for PTR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ptr::R](R) reader structure"] +impl crate::Readable for PTR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ptr::W](W) writer structure"] +impl crate::Writable for PTR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PTR to value 0"] +impl crate::Resettable for PTR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/saadc_ns/samplerate.rs b/pacs/nrf9120-pac/src/saadc_ns/samplerate.rs new file mode 100644 index 00000000..3547d356 --- /dev/null +++ b/pacs/nrf9120-pac/src/saadc_ns/samplerate.rs @@ -0,0 +1,140 @@ +#[doc = "Register `SAMPLERATE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SAMPLERATE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CC` reader - Capture and compare value. Sample rate is 16 MHz/CC"] +pub type CC_R = crate::FieldReader; +#[doc = "Field `CC` writer - Capture and compare value. Sample rate is 16 MHz/CC"] +pub type CC_W<'a, const O: u8> = crate::FieldWriter<'a, u32, SAMPLERATE_SPEC, u16, u16, 11, O>; +#[doc = "Field `MODE` reader - Select mode for sample rate control"] +pub type MODE_R = crate::BitReader; +#[doc = "Select mode for sample rate control\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum MODE_A { + #[doc = "0: Rate is controlled from SAMPLE task"] + TASK = 0, + #[doc = "1: Rate is controlled from local timer (use CC to control the rate)"] + TIMERS = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: MODE_A) -> Self { + variant as u8 != 0 + } +} +impl MODE_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> MODE_A { + match self.bits { + false => MODE_A::TASK, + true => MODE_A::TIMERS, + } + } + #[doc = "Checks if the value of the field is `TASK`"] + #[inline(always)] + pub fn is_task(&self) -> bool { + *self == MODE_A::TASK + } + #[doc = "Checks if the value of the field is `TIMERS`"] + #[inline(always)] + pub fn is_timers(&self) -> bool { + *self == MODE_A::TIMERS + } +} +#[doc = "Field `MODE` writer - Select mode for sample rate control"] +pub type MODE_W<'a, const O: u8> = crate::BitWriter<'a, u32, SAMPLERATE_SPEC, MODE_A, O>; +impl<'a, const O: u8> MODE_W<'a, O> { + #[doc = "Rate is controlled from SAMPLE task"] + #[inline(always)] + pub fn task(self) -> &'a mut W { + self.variant(MODE_A::TASK) + } + #[doc = "Rate is controlled from local timer (use CC to control the rate)"] + #[inline(always)] + pub fn timers(self) -> &'a mut W { + self.variant(MODE_A::TIMERS) + } +} +impl R { + #[doc = "Bits 0:10 - Capture and compare value. Sample rate is 16 MHz/CC"] + #[inline(always)] + pub fn cc(&self) -> CC_R { + CC_R::new((self.bits & 0x07ff) as u16) + } + #[doc = "Bit 12 - Select mode for sample rate control"] + #[inline(always)] + pub fn mode(&self) -> MODE_R { + MODE_R::new(((self.bits >> 12) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:10 - Capture and compare value. Sample rate is 16 MHz/CC"] + #[inline(always)] + pub fn cc(&mut self) -> CC_W<0> { + CC_W::new(self) + } + #[doc = "Bit 12 - Select mode for sample rate control"] + #[inline(always)] + pub fn mode(&mut self) -> MODE_W<12> { + MODE_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Controls normal or continuous sample rate\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [samplerate](index.html) module"] +pub struct SAMPLERATE_SPEC; +impl crate::RegisterSpec for SAMPLERATE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [samplerate::R](R) reader structure"] +impl crate::Readable for SAMPLERATE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [samplerate::W](W) writer structure"] +impl crate::Writable for SAMPLERATE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SAMPLERATE to value 0"] +impl crate::Resettable for SAMPLERATE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/saadc_ns/status.rs b/pacs/nrf9120-pac/src/saadc_ns/status.rs new file mode 100644 index 00000000..d92fd05d --- /dev/null +++ b/pacs/nrf9120-pac/src/saadc_ns/status.rs @@ -0,0 +1,74 @@ +#[doc = "Register `STATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `STATUS` reader - Status"] +pub type STATUS_R = crate::BitReader; +#[doc = "Status\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum STATUS_A { + #[doc = "0: ADC is ready. No on-going conversion."] + READY = 0, + #[doc = "1: ADC is busy. Single conversion in progress."] + BUSY = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: STATUS_A) -> Self { + variant as u8 != 0 + } +} +impl STATUS_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> STATUS_A { + match self.bits { + false => STATUS_A::READY, + true => STATUS_A::BUSY, + } + } + #[doc = "Checks if the value of the field is `READY`"] + #[inline(always)] + pub fn is_ready(&self) -> bool { + *self == STATUS_A::READY + } + #[doc = "Checks if the value of the field is `BUSY`"] + #[inline(always)] + pub fn is_busy(&self) -> bool { + *self == STATUS_A::BUSY + } +} +impl R { + #[doc = "Bit 0 - Status"] + #[inline(always)] + pub fn status(&self) -> STATUS_R { + STATUS_R::new((self.bits & 1) != 0) + } +} +#[doc = "Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [status::R](R) reader structure"] +impl crate::Readable for STATUS_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets STATUS to value 0"] +impl crate::Resettable for STATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/saadc_ns/subscribe_calibrateoffset.rs b/pacs/nrf9120-pac/src/saadc_ns/subscribe_calibrateoffset.rs new file mode 100644 index 00000000..f167e620 --- /dev/null +++ b/pacs/nrf9120-pac/src/saadc_ns/subscribe_calibrateoffset.rs @@ -0,0 +1,141 @@ +#[doc = "Register `SUBSCRIBE_CALIBRATEOFFSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SUBSCRIBE_CALIBRATEOFFSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CHIDX` reader - DPPI channel that task CALIBRATEOFFSET will subscribe to"] +pub type CHIDX_R = crate::FieldReader; +#[doc = "Field `CHIDX` writer - DPPI channel that task CALIBRATEOFFSET will subscribe to"] +pub type CHIDX_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, SUBSCRIBE_CALIBRATEOFFSET_SPEC, u8, u8, 8, O>; +#[doc = "Field `EN` reader - "] +pub type EN_R = crate::BitReader; +#[doc = "\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum EN_A { + #[doc = "0: Disable subscription"] + DISABLED = 0, + #[doc = "1: Enable subscription"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: EN_A) -> Self { + variant as u8 != 0 + } +} +impl EN_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EN_A { + match self.bits { + false => EN_A::DISABLED, + true => EN_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == EN_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == EN_A::ENABLED + } +} +#[doc = "Field `EN` writer - "] +pub type EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, SUBSCRIBE_CALIBRATEOFFSET_SPEC, EN_A, O>; +impl<'a, const O: u8> EN_W<'a, O> { + #[doc = "Disable subscription"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(EN_A::DISABLED) + } + #[doc = "Enable subscription"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(EN_A::ENABLED) + } +} +impl R { + #[doc = "Bits 0:7 - DPPI channel that task CALIBRATEOFFSET will subscribe to"] + #[inline(always)] + pub fn chidx(&self) -> CHIDX_R { + CHIDX_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&self) -> EN_R { + EN_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:7 - DPPI channel that task CALIBRATEOFFSET will subscribe to"] + #[inline(always)] + pub fn chidx(&mut self) -> CHIDX_W<0> { + CHIDX_W::new(self) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&mut self) -> EN_W<31> { + EN_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Subscribe configuration for task CALIBRATEOFFSET\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [subscribe_calibrateoffset](index.html) module"] +pub struct SUBSCRIBE_CALIBRATEOFFSET_SPEC; +impl crate::RegisterSpec for SUBSCRIBE_CALIBRATEOFFSET_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [subscribe_calibrateoffset::R](R) reader structure"] +impl crate::Readable for SUBSCRIBE_CALIBRATEOFFSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [subscribe_calibrateoffset::W](W) writer structure"] +impl crate::Writable for SUBSCRIBE_CALIBRATEOFFSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SUBSCRIBE_CALIBRATEOFFSET to value 0"] +impl crate::Resettable for SUBSCRIBE_CALIBRATEOFFSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/saadc_ns/subscribe_sample.rs b/pacs/nrf9120-pac/src/saadc_ns/subscribe_sample.rs new file mode 100644 index 00000000..60cadb87 --- /dev/null +++ b/pacs/nrf9120-pac/src/saadc_ns/subscribe_sample.rs @@ -0,0 +1,141 @@ +#[doc = "Register `SUBSCRIBE_SAMPLE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SUBSCRIBE_SAMPLE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CHIDX` reader - DPPI channel that task SAMPLE will subscribe to"] +pub type CHIDX_R = crate::FieldReader; +#[doc = "Field `CHIDX` writer - DPPI channel that task SAMPLE will subscribe to"] +pub type CHIDX_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, SUBSCRIBE_SAMPLE_SPEC, u8, u8, 8, O>; +#[doc = "Field `EN` reader - "] +pub type EN_R = crate::BitReader; +#[doc = "\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum EN_A { + #[doc = "0: Disable subscription"] + DISABLED = 0, + #[doc = "1: Enable subscription"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: EN_A) -> Self { + variant as u8 != 0 + } +} +impl EN_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EN_A { + match self.bits { + false => EN_A::DISABLED, + true => EN_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == EN_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == EN_A::ENABLED + } +} +#[doc = "Field `EN` writer - "] +pub type EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, SUBSCRIBE_SAMPLE_SPEC, EN_A, O>; +impl<'a, const O: u8> EN_W<'a, O> { + #[doc = "Disable subscription"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(EN_A::DISABLED) + } + #[doc = "Enable subscription"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(EN_A::ENABLED) + } +} +impl R { + #[doc = "Bits 0:7 - DPPI channel that task SAMPLE will subscribe to"] + #[inline(always)] + pub fn chidx(&self) -> CHIDX_R { + CHIDX_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&self) -> EN_R { + EN_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:7 - DPPI channel that task SAMPLE will subscribe to"] + #[inline(always)] + pub fn chidx(&mut self) -> CHIDX_W<0> { + CHIDX_W::new(self) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&mut self) -> EN_W<31> { + EN_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Subscribe configuration for task SAMPLE\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [subscribe_sample](index.html) module"] +pub struct SUBSCRIBE_SAMPLE_SPEC; +impl crate::RegisterSpec for SUBSCRIBE_SAMPLE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [subscribe_sample::R](R) reader structure"] +impl crate::Readable for SUBSCRIBE_SAMPLE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [subscribe_sample::W](W) writer structure"] +impl crate::Writable for SUBSCRIBE_SAMPLE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SUBSCRIBE_SAMPLE to value 0"] +impl crate::Resettable for SUBSCRIBE_SAMPLE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/saadc_ns/subscribe_start.rs b/pacs/nrf9120-pac/src/saadc_ns/subscribe_start.rs new file mode 100644 index 00000000..fb9deced --- /dev/null +++ b/pacs/nrf9120-pac/src/saadc_ns/subscribe_start.rs @@ -0,0 +1,140 @@ +#[doc = "Register `SUBSCRIBE_START` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SUBSCRIBE_START` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CHIDX` reader - DPPI channel that task START will subscribe to"] +pub type CHIDX_R = crate::FieldReader; +#[doc = "Field `CHIDX` writer - DPPI channel that task START will subscribe to"] +pub type CHIDX_W<'a, const O: u8> = crate::FieldWriter<'a, u32, SUBSCRIBE_START_SPEC, u8, u8, 8, O>; +#[doc = "Field `EN` reader - "] +pub type EN_R = crate::BitReader; +#[doc = "\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum EN_A { + #[doc = "0: Disable subscription"] + DISABLED = 0, + #[doc = "1: Enable subscription"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: EN_A) -> Self { + variant as u8 != 0 + } +} +impl EN_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EN_A { + match self.bits { + false => EN_A::DISABLED, + true => EN_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == EN_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == EN_A::ENABLED + } +} +#[doc = "Field `EN` writer - "] +pub type EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, SUBSCRIBE_START_SPEC, EN_A, O>; +impl<'a, const O: u8> EN_W<'a, O> { + #[doc = "Disable subscription"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(EN_A::DISABLED) + } + #[doc = "Enable subscription"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(EN_A::ENABLED) + } +} +impl R { + #[doc = "Bits 0:7 - DPPI channel that task START will subscribe to"] + #[inline(always)] + pub fn chidx(&self) -> CHIDX_R { + CHIDX_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&self) -> EN_R { + EN_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:7 - DPPI channel that task START will subscribe to"] + #[inline(always)] + pub fn chidx(&mut self) -> CHIDX_W<0> { + CHIDX_W::new(self) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&mut self) -> EN_W<31> { + EN_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Subscribe configuration for task START\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [subscribe_start](index.html) module"] +pub struct SUBSCRIBE_START_SPEC; +impl crate::RegisterSpec for SUBSCRIBE_START_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [subscribe_start::R](R) reader structure"] +impl crate::Readable for SUBSCRIBE_START_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [subscribe_start::W](W) writer structure"] +impl crate::Writable for SUBSCRIBE_START_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SUBSCRIBE_START to value 0"] +impl crate::Resettable for SUBSCRIBE_START_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/saadc_ns/subscribe_stop.rs b/pacs/nrf9120-pac/src/saadc_ns/subscribe_stop.rs new file mode 100644 index 00000000..2fe3af58 --- /dev/null +++ b/pacs/nrf9120-pac/src/saadc_ns/subscribe_stop.rs @@ -0,0 +1,140 @@ +#[doc = "Register `SUBSCRIBE_STOP` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SUBSCRIBE_STOP` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CHIDX` reader - DPPI channel that task STOP will subscribe to"] +pub type CHIDX_R = crate::FieldReader; +#[doc = "Field `CHIDX` writer - DPPI channel that task STOP will subscribe to"] +pub type CHIDX_W<'a, const O: u8> = crate::FieldWriter<'a, u32, SUBSCRIBE_STOP_SPEC, u8, u8, 8, O>; +#[doc = "Field `EN` reader - "] +pub type EN_R = crate::BitReader; +#[doc = "\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum EN_A { + #[doc = "0: Disable subscription"] + DISABLED = 0, + #[doc = "1: Enable subscription"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: EN_A) -> Self { + variant as u8 != 0 + } +} +impl EN_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EN_A { + match self.bits { + false => EN_A::DISABLED, + true => EN_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == EN_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == EN_A::ENABLED + } +} +#[doc = "Field `EN` writer - "] +pub type EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, SUBSCRIBE_STOP_SPEC, EN_A, O>; +impl<'a, const O: u8> EN_W<'a, O> { + #[doc = "Disable subscription"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(EN_A::DISABLED) + } + #[doc = "Enable subscription"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(EN_A::ENABLED) + } +} +impl R { + #[doc = "Bits 0:7 - DPPI channel that task STOP will subscribe to"] + #[inline(always)] + pub fn chidx(&self) -> CHIDX_R { + CHIDX_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&self) -> EN_R { + EN_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:7 - DPPI channel that task STOP will subscribe to"] + #[inline(always)] + pub fn chidx(&mut self) -> CHIDX_W<0> { + CHIDX_W::new(self) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&mut self) -> EN_W<31> { + EN_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Subscribe configuration for task STOP\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [subscribe_stop](index.html) module"] +pub struct SUBSCRIBE_STOP_SPEC; +impl crate::RegisterSpec for SUBSCRIBE_STOP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [subscribe_stop::R](R) reader structure"] +impl crate::Readable for SUBSCRIBE_STOP_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [subscribe_stop::W](W) writer structure"] +impl crate::Writable for SUBSCRIBE_STOP_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SUBSCRIBE_STOP to value 0"] +impl crate::Resettable for SUBSCRIBE_STOP_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/saadc_ns/tasks_calibrateoffset.rs b/pacs/nrf9120-pac/src/saadc_ns/tasks_calibrateoffset.rs new file mode 100644 index 00000000..371a94eb --- /dev/null +++ b/pacs/nrf9120-pac/src/saadc_ns/tasks_calibrateoffset.rs @@ -0,0 +1,72 @@ +#[doc = "Register `TASKS_CALIBRATEOFFSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Starts offset auto-calibration\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum TASKS_CALIBRATEOFFSET_AW { + #[doc = "1: Trigger task"] + TRIGGER = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TASKS_CALIBRATEOFFSET_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TASKS_CALIBRATEOFFSET` writer - Starts offset auto-calibration"] +pub type TASKS_CALIBRATEOFFSET_W<'a, const O: u8> = + crate::BitWriter<'a, u32, TASKS_CALIBRATEOFFSET_SPEC, TASKS_CALIBRATEOFFSET_AW, O>; +impl<'a, const O: u8> TASKS_CALIBRATEOFFSET_W<'a, O> { + #[doc = "Trigger task"] + #[inline(always)] + pub fn trigger(self) -> &'a mut W { + self.variant(TASKS_CALIBRATEOFFSET_AW::TRIGGER) + } +} +impl W { + #[doc = "Bit 0 - Starts offset auto-calibration"] + #[inline(always)] + pub fn tasks_calibrateoffset(&mut self) -> TASKS_CALIBRATEOFFSET_W<0> { + TASKS_CALIBRATEOFFSET_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Starts offset auto-calibration\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tasks_calibrateoffset](index.html) module"] +pub struct TASKS_CALIBRATEOFFSET_SPEC; +impl crate::RegisterSpec for TASKS_CALIBRATEOFFSET_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [tasks_calibrateoffset::W](W) writer structure"] +impl crate::Writable for TASKS_CALIBRATEOFFSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets TASKS_CALIBRATEOFFSET to value 0"] +impl crate::Resettable for TASKS_CALIBRATEOFFSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/saadc_ns/tasks_sample.rs b/pacs/nrf9120-pac/src/saadc_ns/tasks_sample.rs new file mode 100644 index 00000000..4656f9f9 --- /dev/null +++ b/pacs/nrf9120-pac/src/saadc_ns/tasks_sample.rs @@ -0,0 +1,72 @@ +#[doc = "Register `TASKS_SAMPLE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Take one ADC sample, if scan is enabled all channels are sampled\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum TASKS_SAMPLE_AW { + #[doc = "1: Trigger task"] + TRIGGER = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TASKS_SAMPLE_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TASKS_SAMPLE` writer - Take one ADC sample, if scan is enabled all channels are sampled"] +pub type TASKS_SAMPLE_W<'a, const O: u8> = + crate::BitWriter<'a, u32, TASKS_SAMPLE_SPEC, TASKS_SAMPLE_AW, O>; +impl<'a, const O: u8> TASKS_SAMPLE_W<'a, O> { + #[doc = "Trigger task"] + #[inline(always)] + pub fn trigger(self) -> &'a mut W { + self.variant(TASKS_SAMPLE_AW::TRIGGER) + } +} +impl W { + #[doc = "Bit 0 - Take one ADC sample, if scan is enabled all channels are sampled"] + #[inline(always)] + pub fn tasks_sample(&mut self) -> TASKS_SAMPLE_W<0> { + TASKS_SAMPLE_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Take one ADC sample, if scan is enabled all channels are sampled\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tasks_sample](index.html) module"] +pub struct TASKS_SAMPLE_SPEC; +impl crate::RegisterSpec for TASKS_SAMPLE_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [tasks_sample::W](W) writer structure"] +impl crate::Writable for TASKS_SAMPLE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets TASKS_SAMPLE to value 0"] +impl crate::Resettable for TASKS_SAMPLE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/saadc_ns/tasks_start.rs b/pacs/nrf9120-pac/src/saadc_ns/tasks_start.rs new file mode 100644 index 00000000..e605fa0a --- /dev/null +++ b/pacs/nrf9120-pac/src/saadc_ns/tasks_start.rs @@ -0,0 +1,72 @@ +#[doc = "Register `TASKS_START` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Start the ADC and prepare the result buffer in RAM\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum TASKS_START_AW { + #[doc = "1: Trigger task"] + TRIGGER = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TASKS_START_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TASKS_START` writer - Start the ADC and prepare the result buffer in RAM"] +pub type TASKS_START_W<'a, const O: u8> = + crate::BitWriter<'a, u32, TASKS_START_SPEC, TASKS_START_AW, O>; +impl<'a, const O: u8> TASKS_START_W<'a, O> { + #[doc = "Trigger task"] + #[inline(always)] + pub fn trigger(self) -> &'a mut W { + self.variant(TASKS_START_AW::TRIGGER) + } +} +impl W { + #[doc = "Bit 0 - Start the ADC and prepare the result buffer in RAM"] + #[inline(always)] + pub fn tasks_start(&mut self) -> TASKS_START_W<0> { + TASKS_START_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Start the ADC and prepare the result buffer in RAM\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tasks_start](index.html) module"] +pub struct TASKS_START_SPEC; +impl crate::RegisterSpec for TASKS_START_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [tasks_start::W](W) writer structure"] +impl crate::Writable for TASKS_START_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets TASKS_START to value 0"] +impl crate::Resettable for TASKS_START_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/saadc_ns/tasks_stop.rs b/pacs/nrf9120-pac/src/saadc_ns/tasks_stop.rs new file mode 100644 index 00000000..72925e03 --- /dev/null +++ b/pacs/nrf9120-pac/src/saadc_ns/tasks_stop.rs @@ -0,0 +1,72 @@ +#[doc = "Register `TASKS_STOP` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Stop the ADC and terminate any on-going conversion\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum TASKS_STOP_AW { + #[doc = "1: Trigger task"] + TRIGGER = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TASKS_STOP_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TASKS_STOP` writer - Stop the ADC and terminate any on-going conversion"] +pub type TASKS_STOP_W<'a, const O: u8> = + crate::BitWriter<'a, u32, TASKS_STOP_SPEC, TASKS_STOP_AW, O>; +impl<'a, const O: u8> TASKS_STOP_W<'a, O> { + #[doc = "Trigger task"] + #[inline(always)] + pub fn trigger(self) -> &'a mut W { + self.variant(TASKS_STOP_AW::TRIGGER) + } +} +impl W { + #[doc = "Bit 0 - Stop the ADC and terminate any on-going conversion"] + #[inline(always)] + pub fn tasks_stop(&mut self) -> TASKS_STOP_W<0> { + TASKS_STOP_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Stop the ADC and terminate any on-going conversion\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tasks_stop](index.html) module"] +pub struct TASKS_STOP_SPEC; +impl crate::RegisterSpec for TASKS_STOP_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [tasks_stop::W](W) writer structure"] +impl crate::Writable for TASKS_STOP_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets TASKS_STOP to value 0"] +impl crate::Resettable for TASKS_STOP_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/spim0_ns.rs b/pacs/nrf9120-pac/src/spim0_ns.rs new file mode 100644 index 00000000..cb772f3a --- /dev/null +++ b/pacs/nrf9120-pac/src/spim0_ns.rs @@ -0,0 +1,196 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + _reserved0: [u8; 0x10], + #[doc = "0x10 - Start SPI transaction"] + pub tasks_start: TASKS_START, + #[doc = "0x14 - Stop SPI transaction"] + pub tasks_stop: TASKS_STOP, + _reserved2: [u8; 0x04], + #[doc = "0x1c - Suspend SPI transaction"] + pub tasks_suspend: TASKS_SUSPEND, + #[doc = "0x20 - Resume SPI transaction"] + pub tasks_resume: TASKS_RESUME, + _reserved4: [u8; 0x6c], + #[doc = "0x90 - Subscribe configuration for task START"] + pub subscribe_start: SUBSCRIBE_START, + #[doc = "0x94 - Subscribe configuration for task STOP"] + pub subscribe_stop: SUBSCRIBE_STOP, + _reserved6: [u8; 0x04], + #[doc = "0x9c - Subscribe configuration for task SUSPEND"] + pub subscribe_suspend: SUBSCRIBE_SUSPEND, + #[doc = "0xa0 - Subscribe configuration for task RESUME"] + pub subscribe_resume: SUBSCRIBE_RESUME, + _reserved8: [u8; 0x60], + #[doc = "0x104 - SPI transaction has stopped"] + pub events_stopped: EVENTS_STOPPED, + _reserved9: [u8; 0x08], + #[doc = "0x110 - End of RXD buffer reached"] + pub events_endrx: EVENTS_ENDRX, + _reserved10: [u8; 0x04], + #[doc = "0x118 - End of RXD buffer and TXD buffer reached"] + pub events_end: EVENTS_END, + _reserved11: [u8; 0x04], + #[doc = "0x120 - End of TXD buffer reached"] + pub events_endtx: EVENTS_ENDTX, + _reserved12: [u8; 0x28], + #[doc = "0x14c - Transaction started"] + pub events_started: EVENTS_STARTED, + _reserved13: [u8; 0x34], + #[doc = "0x184 - Publish configuration for event STOPPED"] + pub publish_stopped: PUBLISH_STOPPED, + _reserved14: [u8; 0x08], + #[doc = "0x190 - Publish configuration for event ENDRX"] + pub publish_endrx: PUBLISH_ENDRX, + _reserved15: [u8; 0x04], + #[doc = "0x198 - Publish configuration for event END"] + pub publish_end: PUBLISH_END, + _reserved16: [u8; 0x04], + #[doc = "0x1a0 - Publish configuration for event ENDTX"] + pub publish_endtx: PUBLISH_ENDTX, + _reserved17: [u8; 0x28], + #[doc = "0x1cc - Publish configuration for event STARTED"] + pub publish_started: PUBLISH_STARTED, + _reserved18: [u8; 0x30], + #[doc = "0x200 - Shortcuts between local events and tasks"] + pub shorts: SHORTS, + _reserved19: [u8; 0x0100], + #[doc = "0x304 - Enable interrupt"] + pub intenset: INTENSET, + #[doc = "0x308 - Disable interrupt"] + pub intenclr: INTENCLR, + _reserved21: [u8; 0x01f4], + #[doc = "0x500 - Enable SPIM"] + pub enable: ENABLE, + _reserved22: [u8; 0x04], + #[doc = "0x508..0x514 - Unspecified"] + pub psel: PSEL, + _reserved23: [u8; 0x10], + #[doc = "0x524 - SPI frequency. Accuracy depends on the HFCLK source selected."] + pub frequency: FREQUENCY, + _reserved24: [u8; 0x0c], + #[doc = "0x534..0x544 - RXD EasyDMA channel"] + pub rxd: RXD, + #[doc = "0x544..0x554 - TXD EasyDMA channel"] + pub txd: TXD, + #[doc = "0x554 - Configuration register"] + pub config: CONFIG, + _reserved27: [u8; 0x68], + #[doc = "0x5c0 - Over-read character. Character clocked out in case an over-read of the TXD buffer."] + pub orc: ORC, +} +#[doc = "TASKS_START (w) register accessor: an alias for `Reg`"] +pub type TASKS_START = crate::Reg; +#[doc = "Start SPI transaction"] +pub mod tasks_start; +#[doc = "TASKS_STOP (w) register accessor: an alias for `Reg`"] +pub type TASKS_STOP = crate::Reg; +#[doc = "Stop SPI transaction"] +pub mod tasks_stop; +#[doc = "TASKS_SUSPEND (w) register accessor: an alias for `Reg`"] +pub type TASKS_SUSPEND = crate::Reg; +#[doc = "Suspend SPI transaction"] +pub mod tasks_suspend; +#[doc = "TASKS_RESUME (w) register accessor: an alias for `Reg`"] +pub type TASKS_RESUME = crate::Reg; +#[doc = "Resume SPI transaction"] +pub mod tasks_resume; +#[doc = "SUBSCRIBE_START (rw) register accessor: an alias for `Reg`"] +pub type SUBSCRIBE_START = crate::Reg; +#[doc = "Subscribe configuration for task START"] +pub mod subscribe_start; +#[doc = "SUBSCRIBE_STOP (rw) register accessor: an alias for `Reg`"] +pub type SUBSCRIBE_STOP = crate::Reg; +#[doc = "Subscribe configuration for task STOP"] +pub mod subscribe_stop; +#[doc = "SUBSCRIBE_SUSPEND (rw) register accessor: an alias for `Reg`"] +pub type SUBSCRIBE_SUSPEND = crate::Reg; +#[doc = "Subscribe configuration for task SUSPEND"] +pub mod subscribe_suspend; +#[doc = "SUBSCRIBE_RESUME (rw) register accessor: an alias for `Reg`"] +pub type SUBSCRIBE_RESUME = crate::Reg; +#[doc = "Subscribe configuration for task RESUME"] +pub mod subscribe_resume; +#[doc = "EVENTS_STOPPED (rw) register accessor: an alias for `Reg`"] +pub type EVENTS_STOPPED = crate::Reg; +#[doc = "SPI transaction has stopped"] +pub mod events_stopped; +#[doc = "EVENTS_ENDRX (rw) register accessor: an alias for `Reg`"] +pub type EVENTS_ENDRX = crate::Reg; +#[doc = "End of RXD buffer reached"] +pub mod events_endrx; +#[doc = "EVENTS_END (rw) register accessor: an alias for `Reg`"] +pub type EVENTS_END = crate::Reg; +#[doc = "End of RXD buffer and TXD buffer reached"] +pub mod events_end; +#[doc = "EVENTS_ENDTX (rw) register accessor: an alias for `Reg`"] +pub type EVENTS_ENDTX = crate::Reg; +#[doc = "End of TXD buffer reached"] +pub mod events_endtx; +#[doc = "EVENTS_STARTED (rw) register accessor: an alias for `Reg`"] +pub type EVENTS_STARTED = crate::Reg; +#[doc = "Transaction started"] +pub mod events_started; +#[doc = "PUBLISH_STOPPED (rw) register accessor: an alias for `Reg`"] +pub type PUBLISH_STOPPED = crate::Reg; +#[doc = "Publish configuration for event STOPPED"] +pub mod publish_stopped; +#[doc = "PUBLISH_ENDRX (rw) register accessor: an alias for `Reg`"] +pub type PUBLISH_ENDRX = crate::Reg; +#[doc = "Publish configuration for event ENDRX"] +pub mod publish_endrx; +#[doc = "PUBLISH_END (rw) register accessor: an alias for `Reg`"] +pub type PUBLISH_END = crate::Reg; +#[doc = "Publish configuration for event END"] +pub mod publish_end; +#[doc = "PUBLISH_ENDTX (rw) register accessor: an alias for `Reg`"] +pub type PUBLISH_ENDTX = crate::Reg; +#[doc = "Publish configuration for event ENDTX"] +pub mod publish_endtx; +#[doc = "PUBLISH_STARTED (rw) register accessor: an alias for `Reg`"] +pub type PUBLISH_STARTED = crate::Reg; +#[doc = "Publish configuration for event STARTED"] +pub mod publish_started; +#[doc = "SHORTS (rw) register accessor: an alias for `Reg`"] +pub type SHORTS = crate::Reg; +#[doc = "Shortcuts between local events and tasks"] +pub mod shorts; +#[doc = "INTENSET (rw) register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "Enable interrupt"] +pub mod intenset; +#[doc = "INTENCLR (rw) register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "Disable interrupt"] +pub mod intenclr; +#[doc = "ENABLE (rw) register accessor: an alias for `Reg`"] +pub type ENABLE = crate::Reg; +#[doc = "Enable SPIM"] +pub mod enable; +#[doc = "Unspecified"] +pub use psel::PSEL; +#[doc = r"Cluster"] +#[doc = "Unspecified"] +pub mod psel; +#[doc = "FREQUENCY (rw) register accessor: an alias for `Reg`"] +pub type FREQUENCY = crate::Reg; +#[doc = "SPI frequency. Accuracy depends on the HFCLK source selected."] +pub mod frequency; +#[doc = "RXD EasyDMA channel"] +pub use rxd::RXD; +#[doc = r"Cluster"] +#[doc = "RXD EasyDMA channel"] +pub mod rxd; +#[doc = "TXD EasyDMA channel"] +pub use txd::TXD; +#[doc = r"Cluster"] +#[doc = "TXD EasyDMA channel"] +pub mod txd; +#[doc = "CONFIG (rw) register accessor: an alias for `Reg`"] +pub type CONFIG = crate::Reg; +#[doc = "Configuration register"] +pub mod config; +#[doc = "ORC (rw) register accessor: an alias for `Reg`"] +pub type ORC = crate::Reg; +#[doc = "Over-read character. Character clocked out in case an over-read of the TXD buffer."] +pub mod orc; diff --git a/pacs/nrf9120-pac/src/spim0_ns/config.rs b/pacs/nrf9120-pac/src/spim0_ns/config.rs new file mode 100644 index 00000000..e5f6d9e9 --- /dev/null +++ b/pacs/nrf9120-pac/src/spim0_ns/config.rs @@ -0,0 +1,246 @@ +#[doc = "Register `CONFIG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CONFIG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ORDER` reader - Bit order"] +pub type ORDER_R = crate::BitReader; +#[doc = "Bit order\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum ORDER_A { + #[doc = "0: Most significant bit shifted out first"] + MSB_FIRST = 0, + #[doc = "1: Least significant bit shifted out first"] + LSB_FIRST = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: ORDER_A) -> Self { + variant as u8 != 0 + } +} +impl ORDER_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> ORDER_A { + match self.bits { + false => ORDER_A::MSB_FIRST, + true => ORDER_A::LSB_FIRST, + } + } + #[doc = "Checks if the value of the field is `MSB_FIRST`"] + #[inline(always)] + pub fn is_msb_first(&self) -> bool { + *self == ORDER_A::MSB_FIRST + } + #[doc = "Checks if the value of the field is `LSB_FIRST`"] + #[inline(always)] + pub fn is_lsb_first(&self) -> bool { + *self == ORDER_A::LSB_FIRST + } +} +#[doc = "Field `ORDER` writer - Bit order"] +pub type ORDER_W<'a, const O: u8> = crate::BitWriter<'a, u32, CONFIG_SPEC, ORDER_A, O>; +impl<'a, const O: u8> ORDER_W<'a, O> { + #[doc = "Most significant bit shifted out first"] + #[inline(always)] + pub fn msb_first(self) -> &'a mut W { + self.variant(ORDER_A::MSB_FIRST) + } + #[doc = "Least significant bit shifted out first"] + #[inline(always)] + pub fn lsb_first(self) -> &'a mut W { + self.variant(ORDER_A::LSB_FIRST) + } +} +#[doc = "Field `CPHA` reader - Serial clock (SCK) phase"] +pub type CPHA_R = crate::BitReader; +#[doc = "Serial clock (SCK) phase\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CPHA_A { + #[doc = "0: Sample on leading edge of clock, shift serial data on trailing edge"] + LEADING = 0, + #[doc = "1: Sample on trailing edge of clock, shift serial data on leading edge"] + TRAILING = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CPHA_A) -> Self { + variant as u8 != 0 + } +} +impl CPHA_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CPHA_A { + match self.bits { + false => CPHA_A::LEADING, + true => CPHA_A::TRAILING, + } + } + #[doc = "Checks if the value of the field is `LEADING`"] + #[inline(always)] + pub fn is_leading(&self) -> bool { + *self == CPHA_A::LEADING + } + #[doc = "Checks if the value of the field is `TRAILING`"] + #[inline(always)] + pub fn is_trailing(&self) -> bool { + *self == CPHA_A::TRAILING + } +} +#[doc = "Field `CPHA` writer - Serial clock (SCK) phase"] +pub type CPHA_W<'a, const O: u8> = crate::BitWriter<'a, u32, CONFIG_SPEC, CPHA_A, O>; +impl<'a, const O: u8> CPHA_W<'a, O> { + #[doc = "Sample on leading edge of clock, shift serial data on trailing edge"] + #[inline(always)] + pub fn leading(self) -> &'a mut W { + self.variant(CPHA_A::LEADING) + } + #[doc = "Sample on trailing edge of clock, shift serial data on leading edge"] + #[inline(always)] + pub fn trailing(self) -> &'a mut W { + self.variant(CPHA_A::TRAILING) + } +} +#[doc = "Field `CPOL` reader - Serial clock (SCK) polarity"] +pub type CPOL_R = crate::BitReader; +#[doc = "Serial clock (SCK) polarity\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CPOL_A { + #[doc = "0: Active high"] + ACTIVE_HIGH = 0, + #[doc = "1: Active low"] + ACTIVE_LOW = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CPOL_A) -> Self { + variant as u8 != 0 + } +} +impl CPOL_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CPOL_A { + match self.bits { + false => CPOL_A::ACTIVE_HIGH, + true => CPOL_A::ACTIVE_LOW, + } + } + #[doc = "Checks if the value of the field is `ACTIVE_HIGH`"] + #[inline(always)] + pub fn is_active_high(&self) -> bool { + *self == CPOL_A::ACTIVE_HIGH + } + #[doc = "Checks if the value of the field is `ACTIVE_LOW`"] + #[inline(always)] + pub fn is_active_low(&self) -> bool { + *self == CPOL_A::ACTIVE_LOW + } +} +#[doc = "Field `CPOL` writer - Serial clock (SCK) polarity"] +pub type CPOL_W<'a, const O: u8> = crate::BitWriter<'a, u32, CONFIG_SPEC, CPOL_A, O>; +impl<'a, const O: u8> CPOL_W<'a, O> { + #[doc = "Active high"] + #[inline(always)] + pub fn active_high(self) -> &'a mut W { + self.variant(CPOL_A::ACTIVE_HIGH) + } + #[doc = "Active low"] + #[inline(always)] + pub fn active_low(self) -> &'a mut W { + self.variant(CPOL_A::ACTIVE_LOW) + } +} +impl R { + #[doc = "Bit 0 - Bit order"] + #[inline(always)] + pub fn order(&self) -> ORDER_R { + ORDER_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Serial clock (SCK) phase"] + #[inline(always)] + pub fn cpha(&self) -> CPHA_R { + CPHA_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Serial clock (SCK) polarity"] + #[inline(always)] + pub fn cpol(&self) -> CPOL_R { + CPOL_R::new(((self.bits >> 2) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Bit order"] + #[inline(always)] + pub fn order(&mut self) -> ORDER_W<0> { + ORDER_W::new(self) + } + #[doc = "Bit 1 - Serial clock (SCK) phase"] + #[inline(always)] + pub fn cpha(&mut self) -> CPHA_W<1> { + CPHA_W::new(self) + } + #[doc = "Bit 2 - Serial clock (SCK) polarity"] + #[inline(always)] + pub fn cpol(&mut self) -> CPOL_W<2> { + CPOL_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Configuration register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [config](index.html) module"] +pub struct CONFIG_SPEC; +impl crate::RegisterSpec for CONFIG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [config::R](R) reader structure"] +impl crate::Readable for CONFIG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [config::W](W) writer structure"] +impl crate::Writable for CONFIG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CONFIG to value 0"] +impl crate::Resettable for CONFIG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/spim0_ns/enable.rs b/pacs/nrf9120-pac/src/spim0_ns/enable.rs new file mode 100644 index 00000000..ab1a1149 --- /dev/null +++ b/pacs/nrf9120-pac/src/spim0_ns/enable.rs @@ -0,0 +1,128 @@ +#[doc = "Register `ENABLE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `ENABLE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ENABLE` reader - Enable or disable SPIM"] +pub type ENABLE_R = crate::FieldReader; +#[doc = "Enable or disable SPIM\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum ENABLE_A { + #[doc = "0: Disable SPIM"] + DISABLED = 0, + #[doc = "7: Enable SPIM"] + ENABLED = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: ENABLE_A) -> Self { + variant as _ + } +} +impl ENABLE_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(ENABLE_A::DISABLED), + 7 => Some(ENABLE_A::ENABLED), + _ => None, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == ENABLE_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == ENABLE_A::ENABLED + } +} +#[doc = "Field `ENABLE` writer - Enable or disable SPIM"] +pub type ENABLE_W<'a, const O: u8> = crate::FieldWriter<'a, u32, ENABLE_SPEC, u8, ENABLE_A, 4, O>; +impl<'a, const O: u8> ENABLE_W<'a, O> { + #[doc = "Disable SPIM"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(ENABLE_A::DISABLED) + } + #[doc = "Enable SPIM"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(ENABLE_A::ENABLED) + } +} +impl R { + #[doc = "Bits 0:3 - Enable or disable SPIM"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new((self.bits & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - Enable or disable SPIM"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W<0> { + ENABLE_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Enable SPIM\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [enable](index.html) module"] +pub struct ENABLE_SPEC; +impl crate::RegisterSpec for ENABLE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [enable::R](R) reader structure"] +impl crate::Readable for ENABLE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [enable::W](W) writer structure"] +impl crate::Writable for ENABLE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets ENABLE to value 0"] +impl crate::Resettable for ENABLE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/spim0_ns/events_end.rs b/pacs/nrf9120-pac/src/spim0_ns/events_end.rs new file mode 100644 index 00000000..8735713e --- /dev/null +++ b/pacs/nrf9120-pac/src/spim0_ns/events_end.rs @@ -0,0 +1,127 @@ +#[doc = "Register `EVENTS_END` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVENTS_END` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `EVENTS_END` reader - End of RXD buffer and TXD buffer reached"] +pub type EVENTS_END_R = crate::BitReader; +#[doc = "End of RXD buffer and TXD buffer reached\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum EVENTS_END_A { + #[doc = "0: Event not generated"] + NOT_GENERATED = 0, + #[doc = "1: Event generated"] + GENERATED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: EVENTS_END_A) -> Self { + variant as u8 != 0 + } +} +impl EVENTS_END_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EVENTS_END_A { + match self.bits { + false => EVENTS_END_A::NOT_GENERATED, + true => EVENTS_END_A::GENERATED, + } + } + #[doc = "Checks if the value of the field is `NOT_GENERATED`"] + #[inline(always)] + pub fn is_not_generated(&self) -> bool { + *self == EVENTS_END_A::NOT_GENERATED + } + #[doc = "Checks if the value of the field is `GENERATED`"] + #[inline(always)] + pub fn is_generated(&self) -> bool { + *self == EVENTS_END_A::GENERATED + } +} +#[doc = "Field `EVENTS_END` writer - End of RXD buffer and TXD buffer reached"] +pub type EVENTS_END_W<'a, const O: u8> = + crate::BitWriter<'a, u32, EVENTS_END_SPEC, EVENTS_END_A, O>; +impl<'a, const O: u8> EVENTS_END_W<'a, O> { + #[doc = "Event not generated"] + #[inline(always)] + pub fn not_generated(self) -> &'a mut W { + self.variant(EVENTS_END_A::NOT_GENERATED) + } + #[doc = "Event generated"] + #[inline(always)] + pub fn generated(self) -> &'a mut W { + self.variant(EVENTS_END_A::GENERATED) + } +} +impl R { + #[doc = "Bit 0 - End of RXD buffer and TXD buffer reached"] + #[inline(always)] + pub fn events_end(&self) -> EVENTS_END_R { + EVENTS_END_R::new((self.bits & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - End of RXD buffer and TXD buffer reached"] + #[inline(always)] + pub fn events_end(&mut self) -> EVENTS_END_W<0> { + EVENTS_END_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "End of RXD buffer and TXD buffer reached\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [events_end](index.html) module"] +pub struct EVENTS_END_SPEC; +impl crate::RegisterSpec for EVENTS_END_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [events_end::R](R) reader structure"] +impl crate::Readable for EVENTS_END_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [events_end::W](W) writer structure"] +impl crate::Writable for EVENTS_END_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EVENTS_END to value 0"] +impl crate::Resettable for EVENTS_END_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/spim0_ns/events_endrx.rs b/pacs/nrf9120-pac/src/spim0_ns/events_endrx.rs new file mode 100644 index 00000000..0963d202 --- /dev/null +++ b/pacs/nrf9120-pac/src/spim0_ns/events_endrx.rs @@ -0,0 +1,127 @@ +#[doc = "Register `EVENTS_ENDRX` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVENTS_ENDRX` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `EVENTS_ENDRX` reader - End of RXD buffer reached"] +pub type EVENTS_ENDRX_R = crate::BitReader; +#[doc = "End of RXD buffer reached\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum EVENTS_ENDRX_A { + #[doc = "0: Event not generated"] + NOT_GENERATED = 0, + #[doc = "1: Event generated"] + GENERATED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: EVENTS_ENDRX_A) -> Self { + variant as u8 != 0 + } +} +impl EVENTS_ENDRX_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EVENTS_ENDRX_A { + match self.bits { + false => EVENTS_ENDRX_A::NOT_GENERATED, + true => EVENTS_ENDRX_A::GENERATED, + } + } + #[doc = "Checks if the value of the field is `NOT_GENERATED`"] + #[inline(always)] + pub fn is_not_generated(&self) -> bool { + *self == EVENTS_ENDRX_A::NOT_GENERATED + } + #[doc = "Checks if the value of the field is `GENERATED`"] + #[inline(always)] + pub fn is_generated(&self) -> bool { + *self == EVENTS_ENDRX_A::GENERATED + } +} +#[doc = "Field `EVENTS_ENDRX` writer - End of RXD buffer reached"] +pub type EVENTS_ENDRX_W<'a, const O: u8> = + crate::BitWriter<'a, u32, EVENTS_ENDRX_SPEC, EVENTS_ENDRX_A, O>; +impl<'a, const O: u8> EVENTS_ENDRX_W<'a, O> { + #[doc = "Event not generated"] + #[inline(always)] + pub fn not_generated(self) -> &'a mut W { + self.variant(EVENTS_ENDRX_A::NOT_GENERATED) + } + #[doc = "Event generated"] + #[inline(always)] + pub fn generated(self) -> &'a mut W { + self.variant(EVENTS_ENDRX_A::GENERATED) + } +} +impl R { + #[doc = "Bit 0 - End of RXD buffer reached"] + #[inline(always)] + pub fn events_endrx(&self) -> EVENTS_ENDRX_R { + EVENTS_ENDRX_R::new((self.bits & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - End of RXD buffer reached"] + #[inline(always)] + pub fn events_endrx(&mut self) -> EVENTS_ENDRX_W<0> { + EVENTS_ENDRX_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "End of RXD buffer reached\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [events_endrx](index.html) module"] +pub struct EVENTS_ENDRX_SPEC; +impl crate::RegisterSpec for EVENTS_ENDRX_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [events_endrx::R](R) reader structure"] +impl crate::Readable for EVENTS_ENDRX_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [events_endrx::W](W) writer structure"] +impl crate::Writable for EVENTS_ENDRX_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EVENTS_ENDRX to value 0"] +impl crate::Resettable for EVENTS_ENDRX_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/spim0_ns/events_endtx.rs b/pacs/nrf9120-pac/src/spim0_ns/events_endtx.rs new file mode 100644 index 00000000..6ede50ce --- /dev/null +++ b/pacs/nrf9120-pac/src/spim0_ns/events_endtx.rs @@ -0,0 +1,127 @@ +#[doc = "Register `EVENTS_ENDTX` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVENTS_ENDTX` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `EVENTS_ENDTX` reader - End of TXD buffer reached"] +pub type EVENTS_ENDTX_R = crate::BitReader; +#[doc = "End of TXD buffer reached\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum EVENTS_ENDTX_A { + #[doc = "0: Event not generated"] + NOT_GENERATED = 0, + #[doc = "1: Event generated"] + GENERATED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: EVENTS_ENDTX_A) -> Self { + variant as u8 != 0 + } +} +impl EVENTS_ENDTX_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EVENTS_ENDTX_A { + match self.bits { + false => EVENTS_ENDTX_A::NOT_GENERATED, + true => EVENTS_ENDTX_A::GENERATED, + } + } + #[doc = "Checks if the value of the field is `NOT_GENERATED`"] + #[inline(always)] + pub fn is_not_generated(&self) -> bool { + *self == EVENTS_ENDTX_A::NOT_GENERATED + } + #[doc = "Checks if the value of the field is `GENERATED`"] + #[inline(always)] + pub fn is_generated(&self) -> bool { + *self == EVENTS_ENDTX_A::GENERATED + } +} +#[doc = "Field `EVENTS_ENDTX` writer - End of TXD buffer reached"] +pub type EVENTS_ENDTX_W<'a, const O: u8> = + crate::BitWriter<'a, u32, EVENTS_ENDTX_SPEC, EVENTS_ENDTX_A, O>; +impl<'a, const O: u8> EVENTS_ENDTX_W<'a, O> { + #[doc = "Event not generated"] + #[inline(always)] + pub fn not_generated(self) -> &'a mut W { + self.variant(EVENTS_ENDTX_A::NOT_GENERATED) + } + #[doc = "Event generated"] + #[inline(always)] + pub fn generated(self) -> &'a mut W { + self.variant(EVENTS_ENDTX_A::GENERATED) + } +} +impl R { + #[doc = "Bit 0 - End of TXD buffer reached"] + #[inline(always)] + pub fn events_endtx(&self) -> EVENTS_ENDTX_R { + EVENTS_ENDTX_R::new((self.bits & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - End of TXD buffer reached"] + #[inline(always)] + pub fn events_endtx(&mut self) -> EVENTS_ENDTX_W<0> { + EVENTS_ENDTX_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "End of TXD buffer reached\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [events_endtx](index.html) module"] +pub struct EVENTS_ENDTX_SPEC; +impl crate::RegisterSpec for EVENTS_ENDTX_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [events_endtx::R](R) reader structure"] +impl crate::Readable for EVENTS_ENDTX_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [events_endtx::W](W) writer structure"] +impl crate::Writable for EVENTS_ENDTX_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EVENTS_ENDTX to value 0"] +impl crate::Resettable for EVENTS_ENDTX_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/spim0_ns/events_started.rs b/pacs/nrf9120-pac/src/spim0_ns/events_started.rs new file mode 100644 index 00000000..28d01aed --- /dev/null +++ b/pacs/nrf9120-pac/src/spim0_ns/events_started.rs @@ -0,0 +1,127 @@ +#[doc = "Register `EVENTS_STARTED` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVENTS_STARTED` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `EVENTS_STARTED` reader - Transaction started"] +pub type EVENTS_STARTED_R = crate::BitReader; +#[doc = "Transaction started\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum EVENTS_STARTED_A { + #[doc = "0: Event not generated"] + NOT_GENERATED = 0, + #[doc = "1: Event generated"] + GENERATED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: EVENTS_STARTED_A) -> Self { + variant as u8 != 0 + } +} +impl EVENTS_STARTED_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EVENTS_STARTED_A { + match self.bits { + false => EVENTS_STARTED_A::NOT_GENERATED, + true => EVENTS_STARTED_A::GENERATED, + } + } + #[doc = "Checks if the value of the field is `NOT_GENERATED`"] + #[inline(always)] + pub fn is_not_generated(&self) -> bool { + *self == EVENTS_STARTED_A::NOT_GENERATED + } + #[doc = "Checks if the value of the field is `GENERATED`"] + #[inline(always)] + pub fn is_generated(&self) -> bool { + *self == EVENTS_STARTED_A::GENERATED + } +} +#[doc = "Field `EVENTS_STARTED` writer - Transaction started"] +pub type EVENTS_STARTED_W<'a, const O: u8> = + crate::BitWriter<'a, u32, EVENTS_STARTED_SPEC, EVENTS_STARTED_A, O>; +impl<'a, const O: u8> EVENTS_STARTED_W<'a, O> { + #[doc = "Event not generated"] + #[inline(always)] + pub fn not_generated(self) -> &'a mut W { + self.variant(EVENTS_STARTED_A::NOT_GENERATED) + } + #[doc = "Event generated"] + #[inline(always)] + pub fn generated(self) -> &'a mut W { + self.variant(EVENTS_STARTED_A::GENERATED) + } +} +impl R { + #[doc = "Bit 0 - Transaction started"] + #[inline(always)] + pub fn events_started(&self) -> EVENTS_STARTED_R { + EVENTS_STARTED_R::new((self.bits & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Transaction started"] + #[inline(always)] + pub fn events_started(&mut self) -> EVENTS_STARTED_W<0> { + EVENTS_STARTED_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Transaction started\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [events_started](index.html) module"] +pub struct EVENTS_STARTED_SPEC; +impl crate::RegisterSpec for EVENTS_STARTED_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [events_started::R](R) reader structure"] +impl crate::Readable for EVENTS_STARTED_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [events_started::W](W) writer structure"] +impl crate::Writable for EVENTS_STARTED_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EVENTS_STARTED to value 0"] +impl crate::Resettable for EVENTS_STARTED_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/spim0_ns/events_stopped.rs b/pacs/nrf9120-pac/src/spim0_ns/events_stopped.rs new file mode 100644 index 00000000..69567a3a --- /dev/null +++ b/pacs/nrf9120-pac/src/spim0_ns/events_stopped.rs @@ -0,0 +1,127 @@ +#[doc = "Register `EVENTS_STOPPED` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVENTS_STOPPED` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `EVENTS_STOPPED` reader - SPI transaction has stopped"] +pub type EVENTS_STOPPED_R = crate::BitReader; +#[doc = "SPI transaction has stopped\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum EVENTS_STOPPED_A { + #[doc = "0: Event not generated"] + NOT_GENERATED = 0, + #[doc = "1: Event generated"] + GENERATED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: EVENTS_STOPPED_A) -> Self { + variant as u8 != 0 + } +} +impl EVENTS_STOPPED_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EVENTS_STOPPED_A { + match self.bits { + false => EVENTS_STOPPED_A::NOT_GENERATED, + true => EVENTS_STOPPED_A::GENERATED, + } + } + #[doc = "Checks if the value of the field is `NOT_GENERATED`"] + #[inline(always)] + pub fn is_not_generated(&self) -> bool { + *self == EVENTS_STOPPED_A::NOT_GENERATED + } + #[doc = "Checks if the value of the field is `GENERATED`"] + #[inline(always)] + pub fn is_generated(&self) -> bool { + *self == EVENTS_STOPPED_A::GENERATED + } +} +#[doc = "Field `EVENTS_STOPPED` writer - SPI transaction has stopped"] +pub type EVENTS_STOPPED_W<'a, const O: u8> = + crate::BitWriter<'a, u32, EVENTS_STOPPED_SPEC, EVENTS_STOPPED_A, O>; +impl<'a, const O: u8> EVENTS_STOPPED_W<'a, O> { + #[doc = "Event not generated"] + #[inline(always)] + pub fn not_generated(self) -> &'a mut W { + self.variant(EVENTS_STOPPED_A::NOT_GENERATED) + } + #[doc = "Event generated"] + #[inline(always)] + pub fn generated(self) -> &'a mut W { + self.variant(EVENTS_STOPPED_A::GENERATED) + } +} +impl R { + #[doc = "Bit 0 - SPI transaction has stopped"] + #[inline(always)] + pub fn events_stopped(&self) -> EVENTS_STOPPED_R { + EVENTS_STOPPED_R::new((self.bits & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - SPI transaction has stopped"] + #[inline(always)] + pub fn events_stopped(&mut self) -> EVENTS_STOPPED_W<0> { + EVENTS_STOPPED_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPI transaction has stopped\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [events_stopped](index.html) module"] +pub struct EVENTS_STOPPED_SPEC; +impl crate::RegisterSpec for EVENTS_STOPPED_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [events_stopped::R](R) reader structure"] +impl crate::Readable for EVENTS_STOPPED_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [events_stopped::W](W) writer structure"] +impl crate::Writable for EVENTS_STOPPED_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EVENTS_STOPPED to value 0"] +impl crate::Resettable for EVENTS_STOPPED_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/spim0_ns/frequency.rs b/pacs/nrf9120-pac/src/spim0_ns/frequency.rs new file mode 100644 index 00000000..46bef419 --- /dev/null +++ b/pacs/nrf9120-pac/src/spim0_ns/frequency.rs @@ -0,0 +1,194 @@ +#[doc = "Register `FREQUENCY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `FREQUENCY` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `FREQUENCY` reader - SPI master data rate"] +pub type FREQUENCY_R = crate::FieldReader; +#[doc = "SPI master data rate\n\nValue on reset: 67108864"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u32)] +pub enum FREQUENCY_A { + #[doc = "33554432: 125 kbps"] + K125 = 33554432, + #[doc = "67108864: 250 kbps"] + K250 = 67108864, + #[doc = "134217728: 500 kbps"] + K500 = 134217728, + #[doc = "268435456: 1 Mbps"] + M1 = 268435456, + #[doc = "536870912: 2 Mbps"] + M2 = 536870912, + #[doc = "1073741824: 4 Mbps"] + M4 = 1073741824, + #[doc = "2147483648: 8 Mbps"] + M8 = 2147483648, +} +impl From for u32 { + #[inline(always)] + fn from(variant: FREQUENCY_A) -> Self { + variant as _ + } +} +impl FREQUENCY_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 33554432 => Some(FREQUENCY_A::K125), + 67108864 => Some(FREQUENCY_A::K250), + 134217728 => Some(FREQUENCY_A::K500), + 268435456 => Some(FREQUENCY_A::M1), + 536870912 => Some(FREQUENCY_A::M2), + 1073741824 => Some(FREQUENCY_A::M4), + 2147483648 => Some(FREQUENCY_A::M8), + _ => None, + } + } + #[doc = "Checks if the value of the field is `K125`"] + #[inline(always)] + pub fn is_k125(&self) -> bool { + *self == FREQUENCY_A::K125 + } + #[doc = "Checks if the value of the field is `K250`"] + #[inline(always)] + pub fn is_k250(&self) -> bool { + *self == FREQUENCY_A::K250 + } + #[doc = "Checks if the value of the field is `K500`"] + #[inline(always)] + pub fn is_k500(&self) -> bool { + *self == FREQUENCY_A::K500 + } + #[doc = "Checks if the value of the field is `M1`"] + #[inline(always)] + pub fn is_m1(&self) -> bool { + *self == FREQUENCY_A::M1 + } + #[doc = "Checks if the value of the field is `M2`"] + #[inline(always)] + pub fn is_m2(&self) -> bool { + *self == FREQUENCY_A::M2 + } + #[doc = "Checks if the value of the field is `M4`"] + #[inline(always)] + pub fn is_m4(&self) -> bool { + *self == FREQUENCY_A::M4 + } + #[doc = "Checks if the value of the field is `M8`"] + #[inline(always)] + pub fn is_m8(&self) -> bool { + *self == FREQUENCY_A::M8 + } +} +#[doc = "Field `FREQUENCY` writer - SPI master data rate"] +pub type FREQUENCY_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, FREQUENCY_SPEC, u32, FREQUENCY_A, 32, O>; +impl<'a, const O: u8> FREQUENCY_W<'a, O> { + #[doc = "125 kbps"] + #[inline(always)] + pub fn k125(self) -> &'a mut W { + self.variant(FREQUENCY_A::K125) + } + #[doc = "250 kbps"] + #[inline(always)] + pub fn k250(self) -> &'a mut W { + self.variant(FREQUENCY_A::K250) + } + #[doc = "500 kbps"] + #[inline(always)] + pub fn k500(self) -> &'a mut W { + self.variant(FREQUENCY_A::K500) + } + #[doc = "1 Mbps"] + #[inline(always)] + pub fn m1(self) -> &'a mut W { + self.variant(FREQUENCY_A::M1) + } + #[doc = "2 Mbps"] + #[inline(always)] + pub fn m2(self) -> &'a mut W { + self.variant(FREQUENCY_A::M2) + } + #[doc = "4 Mbps"] + #[inline(always)] + pub fn m4(self) -> &'a mut W { + self.variant(FREQUENCY_A::M4) + } + #[doc = "8 Mbps"] + #[inline(always)] + pub fn m8(self) -> &'a mut W { + self.variant(FREQUENCY_A::M8) + } +} +impl R { + #[doc = "Bits 0:31 - SPI master data rate"] + #[inline(always)] + pub fn frequency(&self) -> FREQUENCY_R { + FREQUENCY_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - SPI master data rate"] + #[inline(always)] + pub fn frequency(&mut self) -> FREQUENCY_W<0> { + FREQUENCY_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPI frequency. Accuracy depends on the HFCLK source selected.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [frequency](index.html) module"] +pub struct FREQUENCY_SPEC; +impl crate::RegisterSpec for FREQUENCY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [frequency::R](R) reader structure"] +impl crate::Readable for FREQUENCY_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [frequency::W](W) writer structure"] +impl crate::Writable for FREQUENCY_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets FREQUENCY to value 0x0400_0000"] +impl crate::Resettable for FREQUENCY_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x0400_0000 + } +} diff --git a/pacs/nrf9120-pac/src/spim0_ns/intenclr.rs b/pacs/nrf9120-pac/src/spim0_ns/intenclr.rs new file mode 100644 index 00000000..c63062f0 --- /dev/null +++ b/pacs/nrf9120-pac/src/spim0_ns/intenclr.rs @@ -0,0 +1,401 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `STOPPED` reader - Write '1' to disable interrupt for event STOPPED"] +pub type STOPPED_R = crate::BitReader; +#[doc = "Write '1' to disable interrupt for event STOPPED\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum STOPPED_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: STOPPED_A) -> Self { + variant as u8 != 0 + } +} +impl STOPPED_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> STOPPED_A { + match self.bits { + false => STOPPED_A::DISABLED, + true => STOPPED_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == STOPPED_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == STOPPED_A::ENABLED + } +} +#[doc = "Write '1' to disable interrupt for event STOPPED\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum STOPPED_AW { + #[doc = "1: Disable"] + CLEAR = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: STOPPED_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `STOPPED` writer - Write '1' to disable interrupt for event STOPPED"] +pub type STOPPED_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENCLR_SPEC, STOPPED_AW, O>; +impl<'a, const O: u8> STOPPED_W<'a, O> { + #[doc = "Disable"] + #[inline(always)] + pub fn clear(self) -> &'a mut W { + self.variant(STOPPED_AW::CLEAR) + } +} +#[doc = "Field `ENDRX` reader - Write '1' to disable interrupt for event ENDRX"] +pub type ENDRX_R = crate::BitReader; +#[doc = "Write '1' to disable interrupt for event ENDRX\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum ENDRX_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: ENDRX_A) -> Self { + variant as u8 != 0 + } +} +impl ENDRX_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> ENDRX_A { + match self.bits { + false => ENDRX_A::DISABLED, + true => ENDRX_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == ENDRX_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == ENDRX_A::ENABLED + } +} +#[doc = "Write '1' to disable interrupt for event ENDRX\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum ENDRX_AW { + #[doc = "1: Disable"] + CLEAR = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: ENDRX_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ENDRX` writer - Write '1' to disable interrupt for event ENDRX"] +pub type ENDRX_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENCLR_SPEC, ENDRX_AW, O>; +impl<'a, const O: u8> ENDRX_W<'a, O> { + #[doc = "Disable"] + #[inline(always)] + pub fn clear(self) -> &'a mut W { + self.variant(ENDRX_AW::CLEAR) + } +} +#[doc = "Field `END` reader - Write '1' to disable interrupt for event END"] +pub type END_R = crate::BitReader; +#[doc = "Write '1' to disable interrupt for event END\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum END_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: END_A) -> Self { + variant as u8 != 0 + } +} +impl END_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> END_A { + match self.bits { + false => END_A::DISABLED, + true => END_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == END_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == END_A::ENABLED + } +} +#[doc = "Write '1' to disable interrupt for event END\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum END_AW { + #[doc = "1: Disable"] + CLEAR = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: END_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `END` writer - Write '1' to disable interrupt for event END"] +pub type END_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENCLR_SPEC, END_AW, O>; +impl<'a, const O: u8> END_W<'a, O> { + #[doc = "Disable"] + #[inline(always)] + pub fn clear(self) -> &'a mut W { + self.variant(END_AW::CLEAR) + } +} +#[doc = "Field `ENDTX` reader - Write '1' to disable interrupt for event ENDTX"] +pub type ENDTX_R = crate::BitReader; +#[doc = "Write '1' to disable interrupt for event ENDTX\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum ENDTX_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: ENDTX_A) -> Self { + variant as u8 != 0 + } +} +impl ENDTX_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> ENDTX_A { + match self.bits { + false => ENDTX_A::DISABLED, + true => ENDTX_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == ENDTX_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == ENDTX_A::ENABLED + } +} +#[doc = "Write '1' to disable interrupt for event ENDTX\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum ENDTX_AW { + #[doc = "1: Disable"] + CLEAR = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: ENDTX_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ENDTX` writer - Write '1' to disable interrupt for event ENDTX"] +pub type ENDTX_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENCLR_SPEC, ENDTX_AW, O>; +impl<'a, const O: u8> ENDTX_W<'a, O> { + #[doc = "Disable"] + #[inline(always)] + pub fn clear(self) -> &'a mut W { + self.variant(ENDTX_AW::CLEAR) + } +} +#[doc = "Field `STARTED` reader - Write '1' to disable interrupt for event STARTED"] +pub type STARTED_R = crate::BitReader; +#[doc = "Write '1' to disable interrupt for event STARTED\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum STARTED_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: STARTED_A) -> Self { + variant as u8 != 0 + } +} +impl STARTED_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> STARTED_A { + match self.bits { + false => STARTED_A::DISABLED, + true => STARTED_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == STARTED_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == STARTED_A::ENABLED + } +} +#[doc = "Write '1' to disable interrupt for event STARTED\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum STARTED_AW { + #[doc = "1: Disable"] + CLEAR = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: STARTED_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `STARTED` writer - Write '1' to disable interrupt for event STARTED"] +pub type STARTED_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENCLR_SPEC, STARTED_AW, O>; +impl<'a, const O: u8> STARTED_W<'a, O> { + #[doc = "Disable"] + #[inline(always)] + pub fn clear(self) -> &'a mut W { + self.variant(STARTED_AW::CLEAR) + } +} +impl R { + #[doc = "Bit 1 - Write '1' to disable interrupt for event STOPPED"] + #[inline(always)] + pub fn stopped(&self) -> STOPPED_R { + STOPPED_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 4 - Write '1' to disable interrupt for event ENDRX"] + #[inline(always)] + pub fn endrx(&self) -> ENDRX_R { + ENDRX_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 6 - Write '1' to disable interrupt for event END"] + #[inline(always)] + pub fn end(&self) -> END_R { + END_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 8 - Write '1' to disable interrupt for event ENDTX"] + #[inline(always)] + pub fn endtx(&self) -> ENDTX_R { + ENDTX_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 19 - Write '1' to disable interrupt for event STARTED"] + #[inline(always)] + pub fn started(&self) -> STARTED_R { + STARTED_R::new(((self.bits >> 19) & 1) != 0) + } +} +impl W { + #[doc = "Bit 1 - Write '1' to disable interrupt for event STOPPED"] + #[inline(always)] + pub fn stopped(&mut self) -> STOPPED_W<1> { + STOPPED_W::new(self) + } + #[doc = "Bit 4 - Write '1' to disable interrupt for event ENDRX"] + #[inline(always)] + pub fn endrx(&mut self) -> ENDRX_W<4> { + ENDRX_W::new(self) + } + #[doc = "Bit 6 - Write '1' to disable interrupt for event END"] + #[inline(always)] + pub fn end(&mut self) -> END_W<6> { + END_W::new(self) + } + #[doc = "Bit 8 - Write '1' to disable interrupt for event ENDTX"] + #[inline(always)] + pub fn endtx(&mut self) -> ENDTX_W<8> { + ENDTX_W::new(self) + } + #[doc = "Bit 19 - Write '1' to disable interrupt for event STARTED"] + #[inline(always)] + pub fn started(&mut self) -> STARTED_W<19> { + STARTED_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Disable interrupt\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/spim0_ns/intenset.rs b/pacs/nrf9120-pac/src/spim0_ns/intenset.rs new file mode 100644 index 00000000..74e1b8cd --- /dev/null +++ b/pacs/nrf9120-pac/src/spim0_ns/intenset.rs @@ -0,0 +1,401 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `STOPPED` reader - Write '1' to enable interrupt for event STOPPED"] +pub type STOPPED_R = crate::BitReader; +#[doc = "Write '1' to enable interrupt for event STOPPED\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum STOPPED_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: STOPPED_A) -> Self { + variant as u8 != 0 + } +} +impl STOPPED_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> STOPPED_A { + match self.bits { + false => STOPPED_A::DISABLED, + true => STOPPED_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == STOPPED_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == STOPPED_A::ENABLED + } +} +#[doc = "Write '1' to enable interrupt for event STOPPED\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum STOPPED_AW { + #[doc = "1: Enable"] + SET = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: STOPPED_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `STOPPED` writer - Write '1' to enable interrupt for event STOPPED"] +pub type STOPPED_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENSET_SPEC, STOPPED_AW, O>; +impl<'a, const O: u8> STOPPED_W<'a, O> { + #[doc = "Enable"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(STOPPED_AW::SET) + } +} +#[doc = "Field `ENDRX` reader - Write '1' to enable interrupt for event ENDRX"] +pub type ENDRX_R = crate::BitReader; +#[doc = "Write '1' to enable interrupt for event ENDRX\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum ENDRX_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: ENDRX_A) -> Self { + variant as u8 != 0 + } +} +impl ENDRX_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> ENDRX_A { + match self.bits { + false => ENDRX_A::DISABLED, + true => ENDRX_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == ENDRX_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == ENDRX_A::ENABLED + } +} +#[doc = "Write '1' to enable interrupt for event ENDRX\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum ENDRX_AW { + #[doc = "1: Enable"] + SET = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: ENDRX_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ENDRX` writer - Write '1' to enable interrupt for event ENDRX"] +pub type ENDRX_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENSET_SPEC, ENDRX_AW, O>; +impl<'a, const O: u8> ENDRX_W<'a, O> { + #[doc = "Enable"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(ENDRX_AW::SET) + } +} +#[doc = "Field `END` reader - Write '1' to enable interrupt for event END"] +pub type END_R = crate::BitReader; +#[doc = "Write '1' to enable interrupt for event END\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum END_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: END_A) -> Self { + variant as u8 != 0 + } +} +impl END_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> END_A { + match self.bits { + false => END_A::DISABLED, + true => END_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == END_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == END_A::ENABLED + } +} +#[doc = "Write '1' to enable interrupt for event END\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum END_AW { + #[doc = "1: Enable"] + SET = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: END_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `END` writer - Write '1' to enable interrupt for event END"] +pub type END_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENSET_SPEC, END_AW, O>; +impl<'a, const O: u8> END_W<'a, O> { + #[doc = "Enable"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(END_AW::SET) + } +} +#[doc = "Field `ENDTX` reader - Write '1' to enable interrupt for event ENDTX"] +pub type ENDTX_R = crate::BitReader; +#[doc = "Write '1' to enable interrupt for event ENDTX\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum ENDTX_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: ENDTX_A) -> Self { + variant as u8 != 0 + } +} +impl ENDTX_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> ENDTX_A { + match self.bits { + false => ENDTX_A::DISABLED, + true => ENDTX_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == ENDTX_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == ENDTX_A::ENABLED + } +} +#[doc = "Write '1' to enable interrupt for event ENDTX\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum ENDTX_AW { + #[doc = "1: Enable"] + SET = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: ENDTX_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ENDTX` writer - Write '1' to enable interrupt for event ENDTX"] +pub type ENDTX_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENSET_SPEC, ENDTX_AW, O>; +impl<'a, const O: u8> ENDTX_W<'a, O> { + #[doc = "Enable"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(ENDTX_AW::SET) + } +} +#[doc = "Field `STARTED` reader - Write '1' to enable interrupt for event STARTED"] +pub type STARTED_R = crate::BitReader; +#[doc = "Write '1' to enable interrupt for event STARTED\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum STARTED_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: STARTED_A) -> Self { + variant as u8 != 0 + } +} +impl STARTED_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> STARTED_A { + match self.bits { + false => STARTED_A::DISABLED, + true => STARTED_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == STARTED_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == STARTED_A::ENABLED + } +} +#[doc = "Write '1' to enable interrupt for event STARTED\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum STARTED_AW { + #[doc = "1: Enable"] + SET = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: STARTED_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `STARTED` writer - Write '1' to enable interrupt for event STARTED"] +pub type STARTED_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENSET_SPEC, STARTED_AW, O>; +impl<'a, const O: u8> STARTED_W<'a, O> { + #[doc = "Enable"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(STARTED_AW::SET) + } +} +impl R { + #[doc = "Bit 1 - Write '1' to enable interrupt for event STOPPED"] + #[inline(always)] + pub fn stopped(&self) -> STOPPED_R { + STOPPED_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 4 - Write '1' to enable interrupt for event ENDRX"] + #[inline(always)] + pub fn endrx(&self) -> ENDRX_R { + ENDRX_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 6 - Write '1' to enable interrupt for event END"] + #[inline(always)] + pub fn end(&self) -> END_R { + END_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 8 - Write '1' to enable interrupt for event ENDTX"] + #[inline(always)] + pub fn endtx(&self) -> ENDTX_R { + ENDTX_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 19 - Write '1' to enable interrupt for event STARTED"] + #[inline(always)] + pub fn started(&self) -> STARTED_R { + STARTED_R::new(((self.bits >> 19) & 1) != 0) + } +} +impl W { + #[doc = "Bit 1 - Write '1' to enable interrupt for event STOPPED"] + #[inline(always)] + pub fn stopped(&mut self) -> STOPPED_W<1> { + STOPPED_W::new(self) + } + #[doc = "Bit 4 - Write '1' to enable interrupt for event ENDRX"] + #[inline(always)] + pub fn endrx(&mut self) -> ENDRX_W<4> { + ENDRX_W::new(self) + } + #[doc = "Bit 6 - Write '1' to enable interrupt for event END"] + #[inline(always)] + pub fn end(&mut self) -> END_W<6> { + END_W::new(self) + } + #[doc = "Bit 8 - Write '1' to enable interrupt for event ENDTX"] + #[inline(always)] + pub fn endtx(&mut self) -> ENDTX_W<8> { + ENDTX_W::new(self) + } + #[doc = "Bit 19 - Write '1' to enable interrupt for event STARTED"] + #[inline(always)] + pub fn started(&mut self) -> STARTED_W<19> { + STARTED_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Enable interrupt\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/spim0_ns/orc.rs b/pacs/nrf9120-pac/src/spim0_ns/orc.rs new file mode 100644 index 00000000..a16f4132 --- /dev/null +++ b/pacs/nrf9120-pac/src/spim0_ns/orc.rs @@ -0,0 +1,80 @@ +#[doc = "Register `ORC` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `ORC` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ORC` reader - Over-read character. Character clocked out in case an over-read of the TXD buffer."] +pub type ORC_R = crate::FieldReader; +#[doc = "Field `ORC` writer - Over-read character. Character clocked out in case an over-read of the TXD buffer."] +pub type ORC_W<'a, const O: u8> = crate::FieldWriter<'a, u32, ORC_SPEC, u8, u8, 8, O>; +impl R { + #[doc = "Bits 0:7 - Over-read character. Character clocked out in case an over-read of the TXD buffer."] + #[inline(always)] + pub fn orc(&self) -> ORC_R { + ORC_R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Over-read character. Character clocked out in case an over-read of the TXD buffer."] + #[inline(always)] + pub fn orc(&mut self) -> ORC_W<0> { + ORC_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Over-read character. Character clocked out in case an over-read of the TXD buffer.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [orc](index.html) module"] +pub struct ORC_SPEC; +impl crate::RegisterSpec for ORC_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [orc::R](R) reader structure"] +impl crate::Readable for ORC_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [orc::W](W) writer structure"] +impl crate::Writable for ORC_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets ORC to value 0"] +impl crate::Resettable for ORC_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/spim0_ns/psel.rs b/pacs/nrf9120-pac/src/spim0_ns/psel.rs new file mode 100644 index 00000000..fc62a65a --- /dev/null +++ b/pacs/nrf9120-pac/src/spim0_ns/psel.rs @@ -0,0 +1,22 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct PSEL { + #[doc = "0x00 - Pin select for SCK"] + pub sck: SCK, + #[doc = "0x04 - Pin select for MOSI signal"] + pub mosi: MOSI, + #[doc = "0x08 - Pin select for MISO signal"] + pub miso: MISO, +} +#[doc = "SCK (rw) register accessor: an alias for `Reg`"] +pub type SCK = crate::Reg; +#[doc = "Pin select for SCK"] +pub mod sck; +#[doc = "MOSI (rw) register accessor: an alias for `Reg`"] +pub type MOSI = crate::Reg; +#[doc = "Pin select for MOSI signal"] +pub mod mosi; +#[doc = "MISO (rw) register accessor: an alias for `Reg`"] +pub type MISO = crate::Reg; +#[doc = "Pin select for MISO signal"] +pub mod miso; diff --git a/pacs/nrf9120-pac/src/spim0_ns/psel/miso.rs b/pacs/nrf9120-pac/src/spim0_ns/psel/miso.rs new file mode 100644 index 00000000..23df3916 --- /dev/null +++ b/pacs/nrf9120-pac/src/spim0_ns/psel/miso.rs @@ -0,0 +1,140 @@ +#[doc = "Register `MISO` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `MISO` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PIN` reader - Pin number"] +pub type PIN_R = crate::FieldReader; +#[doc = "Field `PIN` writer - Pin number"] +pub type PIN_W<'a, const O: u8> = crate::FieldWriter<'a, u32, MISO_SPEC, u8, u8, 5, O>; +#[doc = "Field `CONNECT` reader - Connection"] +pub type CONNECT_R = crate::BitReader; +#[doc = "Connection\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CONNECT_A { + #[doc = "1: Disconnect"] + DISCONNECTED = 1, + #[doc = "0: Connect"] + CONNECTED = 0, +} +impl From for bool { + #[inline(always)] + fn from(variant: CONNECT_A) -> Self { + variant as u8 != 0 + } +} +impl CONNECT_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CONNECT_A { + match self.bits { + true => CONNECT_A::DISCONNECTED, + false => CONNECT_A::CONNECTED, + } + } + #[doc = "Checks if the value of the field is `DISCONNECTED`"] + #[inline(always)] + pub fn is_disconnected(&self) -> bool { + *self == CONNECT_A::DISCONNECTED + } + #[doc = "Checks if the value of the field is `CONNECTED`"] + #[inline(always)] + pub fn is_connected(&self) -> bool { + *self == CONNECT_A::CONNECTED + } +} +#[doc = "Field `CONNECT` writer - Connection"] +pub type CONNECT_W<'a, const O: u8> = crate::BitWriter<'a, u32, MISO_SPEC, CONNECT_A, O>; +impl<'a, const O: u8> CONNECT_W<'a, O> { + #[doc = "Disconnect"] + #[inline(always)] + pub fn disconnected(self) -> &'a mut W { + self.variant(CONNECT_A::DISCONNECTED) + } + #[doc = "Connect"] + #[inline(always)] + pub fn connected(self) -> &'a mut W { + self.variant(CONNECT_A::CONNECTED) + } +} +impl R { + #[doc = "Bits 0:4 - Pin number"] + #[inline(always)] + pub fn pin(&self) -> PIN_R { + PIN_R::new((self.bits & 0x1f) as u8) + } + #[doc = "Bit 31 - Connection"] + #[inline(always)] + pub fn connect(&self) -> CONNECT_R { + CONNECT_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:4 - Pin number"] + #[inline(always)] + pub fn pin(&mut self) -> PIN_W<0> { + PIN_W::new(self) + } + #[doc = "Bit 31 - Connection"] + #[inline(always)] + pub fn connect(&mut self) -> CONNECT_W<31> { + CONNECT_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Pin select for MISO signal\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [miso](index.html) module"] +pub struct MISO_SPEC; +impl crate::RegisterSpec for MISO_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [miso::R](R) reader structure"] +impl crate::Readable for MISO_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [miso::W](W) writer structure"] +impl crate::Writable for MISO_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets MISO to value 0xffff_ffff"] +impl crate::Resettable for MISO_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0xffff_ffff + } +} diff --git a/pacs/nrf9120-pac/src/spim0_ns/psel/mosi.rs b/pacs/nrf9120-pac/src/spim0_ns/psel/mosi.rs new file mode 100644 index 00000000..628e39d7 --- /dev/null +++ b/pacs/nrf9120-pac/src/spim0_ns/psel/mosi.rs @@ -0,0 +1,140 @@ +#[doc = "Register `MOSI` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `MOSI` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PIN` reader - Pin number"] +pub type PIN_R = crate::FieldReader; +#[doc = "Field `PIN` writer - Pin number"] +pub type PIN_W<'a, const O: u8> = crate::FieldWriter<'a, u32, MOSI_SPEC, u8, u8, 5, O>; +#[doc = "Field `CONNECT` reader - Connection"] +pub type CONNECT_R = crate::BitReader; +#[doc = "Connection\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CONNECT_A { + #[doc = "1: Disconnect"] + DISCONNECTED = 1, + #[doc = "0: Connect"] + CONNECTED = 0, +} +impl From for bool { + #[inline(always)] + fn from(variant: CONNECT_A) -> Self { + variant as u8 != 0 + } +} +impl CONNECT_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CONNECT_A { + match self.bits { + true => CONNECT_A::DISCONNECTED, + false => CONNECT_A::CONNECTED, + } + } + #[doc = "Checks if the value of the field is `DISCONNECTED`"] + #[inline(always)] + pub fn is_disconnected(&self) -> bool { + *self == CONNECT_A::DISCONNECTED + } + #[doc = "Checks if the value of the field is `CONNECTED`"] + #[inline(always)] + pub fn is_connected(&self) -> bool { + *self == CONNECT_A::CONNECTED + } +} +#[doc = "Field `CONNECT` writer - Connection"] +pub type CONNECT_W<'a, const O: u8> = crate::BitWriter<'a, u32, MOSI_SPEC, CONNECT_A, O>; +impl<'a, const O: u8> CONNECT_W<'a, O> { + #[doc = "Disconnect"] + #[inline(always)] + pub fn disconnected(self) -> &'a mut W { + self.variant(CONNECT_A::DISCONNECTED) + } + #[doc = "Connect"] + #[inline(always)] + pub fn connected(self) -> &'a mut W { + self.variant(CONNECT_A::CONNECTED) + } +} +impl R { + #[doc = "Bits 0:4 - Pin number"] + #[inline(always)] + pub fn pin(&self) -> PIN_R { + PIN_R::new((self.bits & 0x1f) as u8) + } + #[doc = "Bit 31 - Connection"] + #[inline(always)] + pub fn connect(&self) -> CONNECT_R { + CONNECT_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:4 - Pin number"] + #[inline(always)] + pub fn pin(&mut self) -> PIN_W<0> { + PIN_W::new(self) + } + #[doc = "Bit 31 - Connection"] + #[inline(always)] + pub fn connect(&mut self) -> CONNECT_W<31> { + CONNECT_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Pin select for MOSI signal\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [mosi](index.html) module"] +pub struct MOSI_SPEC; +impl crate::RegisterSpec for MOSI_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [mosi::R](R) reader structure"] +impl crate::Readable for MOSI_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [mosi::W](W) writer structure"] +impl crate::Writable for MOSI_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets MOSI to value 0xffff_ffff"] +impl crate::Resettable for MOSI_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0xffff_ffff + } +} diff --git a/pacs/nrf9120-pac/src/spim0_ns/psel/sck.rs b/pacs/nrf9120-pac/src/spim0_ns/psel/sck.rs new file mode 100644 index 00000000..0b259c1c --- /dev/null +++ b/pacs/nrf9120-pac/src/spim0_ns/psel/sck.rs @@ -0,0 +1,140 @@ +#[doc = "Register `SCK` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SCK` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PIN` reader - Pin number"] +pub type PIN_R = crate::FieldReader; +#[doc = "Field `PIN` writer - Pin number"] +pub type PIN_W<'a, const O: u8> = crate::FieldWriter<'a, u32, SCK_SPEC, u8, u8, 5, O>; +#[doc = "Field `CONNECT` reader - Connection"] +pub type CONNECT_R = crate::BitReader; +#[doc = "Connection\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CONNECT_A { + #[doc = "1: Disconnect"] + DISCONNECTED = 1, + #[doc = "0: Connect"] + CONNECTED = 0, +} +impl From for bool { + #[inline(always)] + fn from(variant: CONNECT_A) -> Self { + variant as u8 != 0 + } +} +impl CONNECT_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CONNECT_A { + match self.bits { + true => CONNECT_A::DISCONNECTED, + false => CONNECT_A::CONNECTED, + } + } + #[doc = "Checks if the value of the field is `DISCONNECTED`"] + #[inline(always)] + pub fn is_disconnected(&self) -> bool { + *self == CONNECT_A::DISCONNECTED + } + #[doc = "Checks if the value of the field is `CONNECTED`"] + #[inline(always)] + pub fn is_connected(&self) -> bool { + *self == CONNECT_A::CONNECTED + } +} +#[doc = "Field `CONNECT` writer - Connection"] +pub type CONNECT_W<'a, const O: u8> = crate::BitWriter<'a, u32, SCK_SPEC, CONNECT_A, O>; +impl<'a, const O: u8> CONNECT_W<'a, O> { + #[doc = "Disconnect"] + #[inline(always)] + pub fn disconnected(self) -> &'a mut W { + self.variant(CONNECT_A::DISCONNECTED) + } + #[doc = "Connect"] + #[inline(always)] + pub fn connected(self) -> &'a mut W { + self.variant(CONNECT_A::CONNECTED) + } +} +impl R { + #[doc = "Bits 0:4 - Pin number"] + #[inline(always)] + pub fn pin(&self) -> PIN_R { + PIN_R::new((self.bits & 0x1f) as u8) + } + #[doc = "Bit 31 - Connection"] + #[inline(always)] + pub fn connect(&self) -> CONNECT_R { + CONNECT_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:4 - Pin number"] + #[inline(always)] + pub fn pin(&mut self) -> PIN_W<0> { + PIN_W::new(self) + } + #[doc = "Bit 31 - Connection"] + #[inline(always)] + pub fn connect(&mut self) -> CONNECT_W<31> { + CONNECT_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Pin select for SCK\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sck](index.html) module"] +pub struct SCK_SPEC; +impl crate::RegisterSpec for SCK_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [sck::R](R) reader structure"] +impl crate::Readable for SCK_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [sck::W](W) writer structure"] +impl crate::Writable for SCK_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SCK to value 0xffff_ffff"] +impl crate::Resettable for SCK_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0xffff_ffff + } +} diff --git a/pacs/nrf9120-pac/src/spim0_ns/publish_end.rs b/pacs/nrf9120-pac/src/spim0_ns/publish_end.rs new file mode 100644 index 00000000..2006d5cf --- /dev/null +++ b/pacs/nrf9120-pac/src/spim0_ns/publish_end.rs @@ -0,0 +1,140 @@ +#[doc = "Register `PUBLISH_END` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PUBLISH_END` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CHIDX` reader - DPPI channel that event END will publish to"] +pub type CHIDX_R = crate::FieldReader; +#[doc = "Field `CHIDX` writer - DPPI channel that event END will publish to"] +pub type CHIDX_W<'a, const O: u8> = crate::FieldWriter<'a, u32, PUBLISH_END_SPEC, u8, u8, 8, O>; +#[doc = "Field `EN` reader - "] +pub type EN_R = crate::BitReader; +#[doc = "\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum EN_A { + #[doc = "0: Disable publishing"] + DISABLED = 0, + #[doc = "1: Enable publishing"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: EN_A) -> Self { + variant as u8 != 0 + } +} +impl EN_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EN_A { + match self.bits { + false => EN_A::DISABLED, + true => EN_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == EN_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == EN_A::ENABLED + } +} +#[doc = "Field `EN` writer - "] +pub type EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, PUBLISH_END_SPEC, EN_A, O>; +impl<'a, const O: u8> EN_W<'a, O> { + #[doc = "Disable publishing"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(EN_A::DISABLED) + } + #[doc = "Enable publishing"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(EN_A::ENABLED) + } +} +impl R { + #[doc = "Bits 0:7 - DPPI channel that event END will publish to"] + #[inline(always)] + pub fn chidx(&self) -> CHIDX_R { + CHIDX_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&self) -> EN_R { + EN_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:7 - DPPI channel that event END will publish to"] + #[inline(always)] + pub fn chidx(&mut self) -> CHIDX_W<0> { + CHIDX_W::new(self) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&mut self) -> EN_W<31> { + EN_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Publish configuration for event END\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [publish_end](index.html) module"] +pub struct PUBLISH_END_SPEC; +impl crate::RegisterSpec for PUBLISH_END_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [publish_end::R](R) reader structure"] +impl crate::Readable for PUBLISH_END_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [publish_end::W](W) writer structure"] +impl crate::Writable for PUBLISH_END_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PUBLISH_END to value 0"] +impl crate::Resettable for PUBLISH_END_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/spim0_ns/publish_endrx.rs b/pacs/nrf9120-pac/src/spim0_ns/publish_endrx.rs new file mode 100644 index 00000000..1c25570b --- /dev/null +++ b/pacs/nrf9120-pac/src/spim0_ns/publish_endrx.rs @@ -0,0 +1,140 @@ +#[doc = "Register `PUBLISH_ENDRX` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PUBLISH_ENDRX` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CHIDX` reader - DPPI channel that event ENDRX will publish to"] +pub type CHIDX_R = crate::FieldReader; +#[doc = "Field `CHIDX` writer - DPPI channel that event ENDRX will publish to"] +pub type CHIDX_W<'a, const O: u8> = crate::FieldWriter<'a, u32, PUBLISH_ENDRX_SPEC, u8, u8, 8, O>; +#[doc = "Field `EN` reader - "] +pub type EN_R = crate::BitReader; +#[doc = "\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum EN_A { + #[doc = "0: Disable publishing"] + DISABLED = 0, + #[doc = "1: Enable publishing"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: EN_A) -> Self { + variant as u8 != 0 + } +} +impl EN_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EN_A { + match self.bits { + false => EN_A::DISABLED, + true => EN_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == EN_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == EN_A::ENABLED + } +} +#[doc = "Field `EN` writer - "] +pub type EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, PUBLISH_ENDRX_SPEC, EN_A, O>; +impl<'a, const O: u8> EN_W<'a, O> { + #[doc = "Disable publishing"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(EN_A::DISABLED) + } + #[doc = "Enable publishing"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(EN_A::ENABLED) + } +} +impl R { + #[doc = "Bits 0:7 - DPPI channel that event ENDRX will publish to"] + #[inline(always)] + pub fn chidx(&self) -> CHIDX_R { + CHIDX_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&self) -> EN_R { + EN_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:7 - DPPI channel that event ENDRX will publish to"] + #[inline(always)] + pub fn chidx(&mut self) -> CHIDX_W<0> { + CHIDX_W::new(self) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&mut self) -> EN_W<31> { + EN_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Publish configuration for event ENDRX\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [publish_endrx](index.html) module"] +pub struct PUBLISH_ENDRX_SPEC; +impl crate::RegisterSpec for PUBLISH_ENDRX_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [publish_endrx::R](R) reader structure"] +impl crate::Readable for PUBLISH_ENDRX_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [publish_endrx::W](W) writer structure"] +impl crate::Writable for PUBLISH_ENDRX_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PUBLISH_ENDRX to value 0"] +impl crate::Resettable for PUBLISH_ENDRX_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/spim0_ns/publish_endtx.rs b/pacs/nrf9120-pac/src/spim0_ns/publish_endtx.rs new file mode 100644 index 00000000..ebaa02ca --- /dev/null +++ b/pacs/nrf9120-pac/src/spim0_ns/publish_endtx.rs @@ -0,0 +1,140 @@ +#[doc = "Register `PUBLISH_ENDTX` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PUBLISH_ENDTX` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CHIDX` reader - DPPI channel that event ENDTX will publish to"] +pub type CHIDX_R = crate::FieldReader; +#[doc = "Field `CHIDX` writer - DPPI channel that event ENDTX will publish to"] +pub type CHIDX_W<'a, const O: u8> = crate::FieldWriter<'a, u32, PUBLISH_ENDTX_SPEC, u8, u8, 8, O>; +#[doc = "Field `EN` reader - "] +pub type EN_R = crate::BitReader; +#[doc = "\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum EN_A { + #[doc = "0: Disable publishing"] + DISABLED = 0, + #[doc = "1: Enable publishing"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: EN_A) -> Self { + variant as u8 != 0 + } +} +impl EN_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EN_A { + match self.bits { + false => EN_A::DISABLED, + true => EN_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == EN_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == EN_A::ENABLED + } +} +#[doc = "Field `EN` writer - "] +pub type EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, PUBLISH_ENDTX_SPEC, EN_A, O>; +impl<'a, const O: u8> EN_W<'a, O> { + #[doc = "Disable publishing"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(EN_A::DISABLED) + } + #[doc = "Enable publishing"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(EN_A::ENABLED) + } +} +impl R { + #[doc = "Bits 0:7 - DPPI channel that event ENDTX will publish to"] + #[inline(always)] + pub fn chidx(&self) -> CHIDX_R { + CHIDX_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&self) -> EN_R { + EN_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:7 - DPPI channel that event ENDTX will publish to"] + #[inline(always)] + pub fn chidx(&mut self) -> CHIDX_W<0> { + CHIDX_W::new(self) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&mut self) -> EN_W<31> { + EN_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Publish configuration for event ENDTX\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [publish_endtx](index.html) module"] +pub struct PUBLISH_ENDTX_SPEC; +impl crate::RegisterSpec for PUBLISH_ENDTX_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [publish_endtx::R](R) reader structure"] +impl crate::Readable for PUBLISH_ENDTX_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [publish_endtx::W](W) writer structure"] +impl crate::Writable for PUBLISH_ENDTX_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PUBLISH_ENDTX to value 0"] +impl crate::Resettable for PUBLISH_ENDTX_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/spim0_ns/publish_started.rs b/pacs/nrf9120-pac/src/spim0_ns/publish_started.rs new file mode 100644 index 00000000..1b0354ef --- /dev/null +++ b/pacs/nrf9120-pac/src/spim0_ns/publish_started.rs @@ -0,0 +1,140 @@ +#[doc = "Register `PUBLISH_STARTED` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PUBLISH_STARTED` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CHIDX` reader - DPPI channel that event STARTED will publish to"] +pub type CHIDX_R = crate::FieldReader; +#[doc = "Field `CHIDX` writer - DPPI channel that event STARTED will publish to"] +pub type CHIDX_W<'a, const O: u8> = crate::FieldWriter<'a, u32, PUBLISH_STARTED_SPEC, u8, u8, 8, O>; +#[doc = "Field `EN` reader - "] +pub type EN_R = crate::BitReader; +#[doc = "\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum EN_A { + #[doc = "0: Disable publishing"] + DISABLED = 0, + #[doc = "1: Enable publishing"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: EN_A) -> Self { + variant as u8 != 0 + } +} +impl EN_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EN_A { + match self.bits { + false => EN_A::DISABLED, + true => EN_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == EN_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == EN_A::ENABLED + } +} +#[doc = "Field `EN` writer - "] +pub type EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, PUBLISH_STARTED_SPEC, EN_A, O>; +impl<'a, const O: u8> EN_W<'a, O> { + #[doc = "Disable publishing"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(EN_A::DISABLED) + } + #[doc = "Enable publishing"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(EN_A::ENABLED) + } +} +impl R { + #[doc = "Bits 0:7 - DPPI channel that event STARTED will publish to"] + #[inline(always)] + pub fn chidx(&self) -> CHIDX_R { + CHIDX_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&self) -> EN_R { + EN_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:7 - DPPI channel that event STARTED will publish to"] + #[inline(always)] + pub fn chidx(&mut self) -> CHIDX_W<0> { + CHIDX_W::new(self) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&mut self) -> EN_W<31> { + EN_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Publish configuration for event STARTED\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [publish_started](index.html) module"] +pub struct PUBLISH_STARTED_SPEC; +impl crate::RegisterSpec for PUBLISH_STARTED_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [publish_started::R](R) reader structure"] +impl crate::Readable for PUBLISH_STARTED_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [publish_started::W](W) writer structure"] +impl crate::Writable for PUBLISH_STARTED_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PUBLISH_STARTED to value 0"] +impl crate::Resettable for PUBLISH_STARTED_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/spim0_ns/publish_stopped.rs b/pacs/nrf9120-pac/src/spim0_ns/publish_stopped.rs new file mode 100644 index 00000000..247f50bf --- /dev/null +++ b/pacs/nrf9120-pac/src/spim0_ns/publish_stopped.rs @@ -0,0 +1,140 @@ +#[doc = "Register `PUBLISH_STOPPED` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PUBLISH_STOPPED` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CHIDX` reader - DPPI channel that event STOPPED will publish to"] +pub type CHIDX_R = crate::FieldReader; +#[doc = "Field `CHIDX` writer - DPPI channel that event STOPPED will publish to"] +pub type CHIDX_W<'a, const O: u8> = crate::FieldWriter<'a, u32, PUBLISH_STOPPED_SPEC, u8, u8, 8, O>; +#[doc = "Field `EN` reader - "] +pub type EN_R = crate::BitReader; +#[doc = "\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum EN_A { + #[doc = "0: Disable publishing"] + DISABLED = 0, + #[doc = "1: Enable publishing"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: EN_A) -> Self { + variant as u8 != 0 + } +} +impl EN_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EN_A { + match self.bits { + false => EN_A::DISABLED, + true => EN_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == EN_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == EN_A::ENABLED + } +} +#[doc = "Field `EN` writer - "] +pub type EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, PUBLISH_STOPPED_SPEC, EN_A, O>; +impl<'a, const O: u8> EN_W<'a, O> { + #[doc = "Disable publishing"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(EN_A::DISABLED) + } + #[doc = "Enable publishing"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(EN_A::ENABLED) + } +} +impl R { + #[doc = "Bits 0:7 - DPPI channel that event STOPPED will publish to"] + #[inline(always)] + pub fn chidx(&self) -> CHIDX_R { + CHIDX_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&self) -> EN_R { + EN_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:7 - DPPI channel that event STOPPED will publish to"] + #[inline(always)] + pub fn chidx(&mut self) -> CHIDX_W<0> { + CHIDX_W::new(self) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&mut self) -> EN_W<31> { + EN_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Publish configuration for event STOPPED\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [publish_stopped](index.html) module"] +pub struct PUBLISH_STOPPED_SPEC; +impl crate::RegisterSpec for PUBLISH_STOPPED_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [publish_stopped::R](R) reader structure"] +impl crate::Readable for PUBLISH_STOPPED_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [publish_stopped::W](W) writer structure"] +impl crate::Writable for PUBLISH_STOPPED_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PUBLISH_STOPPED to value 0"] +impl crate::Resettable for PUBLISH_STOPPED_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/spim0_ns/rxd.rs b/pacs/nrf9120-pac/src/spim0_ns/rxd.rs new file mode 100644 index 00000000..6a264182 --- /dev/null +++ b/pacs/nrf9120-pac/src/spim0_ns/rxd.rs @@ -0,0 +1,28 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RXD { + #[doc = "0x00 - Data pointer"] + pub ptr: PTR, + #[doc = "0x04 - Maximum number of bytes in receive buffer"] + pub maxcnt: MAXCNT, + #[doc = "0x08 - Number of bytes transferred in the last transaction"] + pub amount: AMOUNT, + #[doc = "0x0c - EasyDMA list type"] + pub list: LIST, +} +#[doc = "PTR (rw) register accessor: an alias for `Reg`"] +pub type PTR = crate::Reg; +#[doc = "Data pointer"] +pub mod ptr; +#[doc = "MAXCNT (rw) register accessor: an alias for `Reg`"] +pub type MAXCNT = crate::Reg; +#[doc = "Maximum number of bytes in receive buffer"] +pub mod maxcnt; +#[doc = "AMOUNT (r) register accessor: an alias for `Reg`"] +pub type AMOUNT = crate::Reg; +#[doc = "Number of bytes transferred in the last transaction"] +pub mod amount; +#[doc = "LIST (rw) register accessor: an alias for `Reg`"] +pub type LIST = crate::Reg; +#[doc = "EasyDMA list type"] +pub mod list; diff --git a/pacs/nrf9120-pac/src/spim0_ns/rxd/amount.rs b/pacs/nrf9120-pac/src/spim0_ns/rxd/amount.rs new file mode 100644 index 00000000..b8909afa --- /dev/null +++ b/pacs/nrf9120-pac/src/spim0_ns/rxd/amount.rs @@ -0,0 +1,40 @@ +#[doc = "Register `AMOUNT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `AMOUNT` reader - Number of bytes transferred in the last transaction"] +pub type AMOUNT_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:12 - Number of bytes transferred in the last transaction"] + #[inline(always)] + pub fn amount(&self) -> AMOUNT_R { + AMOUNT_R::new((self.bits & 0x1fff) as u16) + } +} +#[doc = "Number of bytes transferred in the last transaction\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [amount](index.html) module"] +pub struct AMOUNT_SPEC; +impl crate::RegisterSpec for AMOUNT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [amount::R](R) reader structure"] +impl crate::Readable for AMOUNT_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets AMOUNT to value 0"] +impl crate::Resettable for AMOUNT_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/spim0_ns/rxd/list.rs b/pacs/nrf9120-pac/src/spim0_ns/rxd/list.rs new file mode 100644 index 00000000..aa379b8c --- /dev/null +++ b/pacs/nrf9120-pac/src/spim0_ns/rxd/list.rs @@ -0,0 +1,128 @@ +#[doc = "Register `LIST` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `LIST` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `LIST` reader - List type"] +pub type LIST_R = crate::FieldReader; +#[doc = "List type\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum LIST_A { + #[doc = "0: Disable EasyDMA list"] + DISABLED = 0, + #[doc = "1: Use array list"] + ARRAY_LIST = 1, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LIST_A) -> Self { + variant as _ + } +} +impl LIST_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(LIST_A::DISABLED), + 1 => Some(LIST_A::ARRAY_LIST), + _ => None, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == LIST_A::DISABLED + } + #[doc = "Checks if the value of the field is `ARRAY_LIST`"] + #[inline(always)] + pub fn is_array_list(&self) -> bool { + *self == LIST_A::ARRAY_LIST + } +} +#[doc = "Field `LIST` writer - List type"] +pub type LIST_W<'a, const O: u8> = crate::FieldWriter<'a, u32, LIST_SPEC, u8, LIST_A, 2, O>; +impl<'a, const O: u8> LIST_W<'a, O> { + #[doc = "Disable EasyDMA list"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(LIST_A::DISABLED) + } + #[doc = "Use array list"] + #[inline(always)] + pub fn array_list(self) -> &'a mut W { + self.variant(LIST_A::ARRAY_LIST) + } +} +impl R { + #[doc = "Bits 0:1 - List type"] + #[inline(always)] + pub fn list(&self) -> LIST_R { + LIST_R::new((self.bits & 3) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - List type"] + #[inline(always)] + pub fn list(&mut self) -> LIST_W<0> { + LIST_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "EasyDMA list type\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [list](index.html) module"] +pub struct LIST_SPEC; +impl crate::RegisterSpec for LIST_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [list::R](R) reader structure"] +impl crate::Readable for LIST_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [list::W](W) writer structure"] +impl crate::Writable for LIST_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets LIST to value 0"] +impl crate::Resettable for LIST_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/spim0_ns/rxd/maxcnt.rs b/pacs/nrf9120-pac/src/spim0_ns/rxd/maxcnt.rs new file mode 100644 index 00000000..0344ca9e --- /dev/null +++ b/pacs/nrf9120-pac/src/spim0_ns/rxd/maxcnt.rs @@ -0,0 +1,80 @@ +#[doc = "Register `MAXCNT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `MAXCNT` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `MAXCNT` reader - Maximum number of bytes in receive buffer"] +pub type MAXCNT_R = crate::FieldReader; +#[doc = "Field `MAXCNT` writer - Maximum number of bytes in receive buffer"] +pub type MAXCNT_W<'a, const O: u8> = crate::FieldWriter<'a, u32, MAXCNT_SPEC, u16, u16, 13, O>; +impl R { + #[doc = "Bits 0:12 - Maximum number of bytes in receive buffer"] + #[inline(always)] + pub fn maxcnt(&self) -> MAXCNT_R { + MAXCNT_R::new((self.bits & 0x1fff) as u16) + } +} +impl W { + #[doc = "Bits 0:12 - Maximum number of bytes in receive buffer"] + #[inline(always)] + pub fn maxcnt(&mut self) -> MAXCNT_W<0> { + MAXCNT_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Maximum number of bytes in receive buffer\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [maxcnt](index.html) module"] +pub struct MAXCNT_SPEC; +impl crate::RegisterSpec for MAXCNT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [maxcnt::R](R) reader structure"] +impl crate::Readable for MAXCNT_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [maxcnt::W](W) writer structure"] +impl crate::Writable for MAXCNT_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets MAXCNT to value 0"] +impl crate::Resettable for MAXCNT_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/spim0_ns/rxd/ptr.rs b/pacs/nrf9120-pac/src/spim0_ns/rxd/ptr.rs new file mode 100644 index 00000000..d5f98439 --- /dev/null +++ b/pacs/nrf9120-pac/src/spim0_ns/rxd/ptr.rs @@ -0,0 +1,80 @@ +#[doc = "Register `PTR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PTR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PTR` reader - Data pointer"] +pub type PTR_R = crate::FieldReader; +#[doc = "Field `PTR` writer - Data pointer"] +pub type PTR_W<'a, const O: u8> = crate::FieldWriter<'a, u32, PTR_SPEC, u32, u32, 32, O>; +impl R { + #[doc = "Bits 0:31 - Data pointer"] + #[inline(always)] + pub fn ptr(&self) -> PTR_R { + PTR_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Data pointer"] + #[inline(always)] + pub fn ptr(&mut self) -> PTR_W<0> { + PTR_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Data pointer\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ptr](index.html) module"] +pub struct PTR_SPEC; +impl crate::RegisterSpec for PTR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ptr::R](R) reader structure"] +impl crate::Readable for PTR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ptr::W](W) writer structure"] +impl crate::Writable for PTR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PTR to value 0"] +impl crate::Resettable for PTR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/spim0_ns/shorts.rs b/pacs/nrf9120-pac/src/spim0_ns/shorts.rs new file mode 100644 index 00000000..91ce1e9e --- /dev/null +++ b/pacs/nrf9120-pac/src/spim0_ns/shorts.rs @@ -0,0 +1,126 @@ +#[doc = "Register `SHORTS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SHORTS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `END_START` reader - Shortcut between event END and task START"] +pub type END_START_R = crate::BitReader; +#[doc = "Shortcut between event END and task START\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum END_START_A { + #[doc = "0: Disable shortcut"] + DISABLED = 0, + #[doc = "1: Enable shortcut"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: END_START_A) -> Self { + variant as u8 != 0 + } +} +impl END_START_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> END_START_A { + match self.bits { + false => END_START_A::DISABLED, + true => END_START_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == END_START_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == END_START_A::ENABLED + } +} +#[doc = "Field `END_START` writer - Shortcut between event END and task START"] +pub type END_START_W<'a, const O: u8> = crate::BitWriter<'a, u32, SHORTS_SPEC, END_START_A, O>; +impl<'a, const O: u8> END_START_W<'a, O> { + #[doc = "Disable shortcut"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(END_START_A::DISABLED) + } + #[doc = "Enable shortcut"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(END_START_A::ENABLED) + } +} +impl R { + #[doc = "Bit 17 - Shortcut between event END and task START"] + #[inline(always)] + pub fn end_start(&self) -> END_START_R { + END_START_R::new(((self.bits >> 17) & 1) != 0) + } +} +impl W { + #[doc = "Bit 17 - Shortcut between event END and task START"] + #[inline(always)] + pub fn end_start(&mut self) -> END_START_W<17> { + END_START_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Shortcuts between local events and tasks\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [shorts](index.html) module"] +pub struct SHORTS_SPEC; +impl crate::RegisterSpec for SHORTS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [shorts::R](R) reader structure"] +impl crate::Readable for SHORTS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [shorts::W](W) writer structure"] +impl crate::Writable for SHORTS_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SHORTS to value 0"] +impl crate::Resettable for SHORTS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/spim0_ns/subscribe_resume.rs b/pacs/nrf9120-pac/src/spim0_ns/subscribe_resume.rs new file mode 100644 index 00000000..cef10f00 --- /dev/null +++ b/pacs/nrf9120-pac/src/spim0_ns/subscribe_resume.rs @@ -0,0 +1,141 @@ +#[doc = "Register `SUBSCRIBE_RESUME` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SUBSCRIBE_RESUME` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CHIDX` reader - DPPI channel that task RESUME will subscribe to"] +pub type CHIDX_R = crate::FieldReader; +#[doc = "Field `CHIDX` writer - DPPI channel that task RESUME will subscribe to"] +pub type CHIDX_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, SUBSCRIBE_RESUME_SPEC, u8, u8, 8, O>; +#[doc = "Field `EN` reader - "] +pub type EN_R = crate::BitReader; +#[doc = "\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum EN_A { + #[doc = "0: Disable subscription"] + DISABLED = 0, + #[doc = "1: Enable subscription"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: EN_A) -> Self { + variant as u8 != 0 + } +} +impl EN_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EN_A { + match self.bits { + false => EN_A::DISABLED, + true => EN_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == EN_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == EN_A::ENABLED + } +} +#[doc = "Field `EN` writer - "] +pub type EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, SUBSCRIBE_RESUME_SPEC, EN_A, O>; +impl<'a, const O: u8> EN_W<'a, O> { + #[doc = "Disable subscription"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(EN_A::DISABLED) + } + #[doc = "Enable subscription"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(EN_A::ENABLED) + } +} +impl R { + #[doc = "Bits 0:7 - DPPI channel that task RESUME will subscribe to"] + #[inline(always)] + pub fn chidx(&self) -> CHIDX_R { + CHIDX_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&self) -> EN_R { + EN_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:7 - DPPI channel that task RESUME will subscribe to"] + #[inline(always)] + pub fn chidx(&mut self) -> CHIDX_W<0> { + CHIDX_W::new(self) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&mut self) -> EN_W<31> { + EN_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Subscribe configuration for task RESUME\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [subscribe_resume](index.html) module"] +pub struct SUBSCRIBE_RESUME_SPEC; +impl crate::RegisterSpec for SUBSCRIBE_RESUME_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [subscribe_resume::R](R) reader structure"] +impl crate::Readable for SUBSCRIBE_RESUME_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [subscribe_resume::W](W) writer structure"] +impl crate::Writable for SUBSCRIBE_RESUME_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SUBSCRIBE_RESUME to value 0"] +impl crate::Resettable for SUBSCRIBE_RESUME_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/spim0_ns/subscribe_start.rs b/pacs/nrf9120-pac/src/spim0_ns/subscribe_start.rs new file mode 100644 index 00000000..fb9deced --- /dev/null +++ b/pacs/nrf9120-pac/src/spim0_ns/subscribe_start.rs @@ -0,0 +1,140 @@ +#[doc = "Register `SUBSCRIBE_START` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SUBSCRIBE_START` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CHIDX` reader - DPPI channel that task START will subscribe to"] +pub type CHIDX_R = crate::FieldReader; +#[doc = "Field `CHIDX` writer - DPPI channel that task START will subscribe to"] +pub type CHIDX_W<'a, const O: u8> = crate::FieldWriter<'a, u32, SUBSCRIBE_START_SPEC, u8, u8, 8, O>; +#[doc = "Field `EN` reader - "] +pub type EN_R = crate::BitReader; +#[doc = "\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum EN_A { + #[doc = "0: Disable subscription"] + DISABLED = 0, + #[doc = "1: Enable subscription"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: EN_A) -> Self { + variant as u8 != 0 + } +} +impl EN_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EN_A { + match self.bits { + false => EN_A::DISABLED, + true => EN_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == EN_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == EN_A::ENABLED + } +} +#[doc = "Field `EN` writer - "] +pub type EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, SUBSCRIBE_START_SPEC, EN_A, O>; +impl<'a, const O: u8> EN_W<'a, O> { + #[doc = "Disable subscription"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(EN_A::DISABLED) + } + #[doc = "Enable subscription"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(EN_A::ENABLED) + } +} +impl R { + #[doc = "Bits 0:7 - DPPI channel that task START will subscribe to"] + #[inline(always)] + pub fn chidx(&self) -> CHIDX_R { + CHIDX_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&self) -> EN_R { + EN_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:7 - DPPI channel that task START will subscribe to"] + #[inline(always)] + pub fn chidx(&mut self) -> CHIDX_W<0> { + CHIDX_W::new(self) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&mut self) -> EN_W<31> { + EN_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Subscribe configuration for task START\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [subscribe_start](index.html) module"] +pub struct SUBSCRIBE_START_SPEC; +impl crate::RegisterSpec for SUBSCRIBE_START_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [subscribe_start::R](R) reader structure"] +impl crate::Readable for SUBSCRIBE_START_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [subscribe_start::W](W) writer structure"] +impl crate::Writable for SUBSCRIBE_START_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SUBSCRIBE_START to value 0"] +impl crate::Resettable for SUBSCRIBE_START_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/spim0_ns/subscribe_stop.rs b/pacs/nrf9120-pac/src/spim0_ns/subscribe_stop.rs new file mode 100644 index 00000000..2fe3af58 --- /dev/null +++ b/pacs/nrf9120-pac/src/spim0_ns/subscribe_stop.rs @@ -0,0 +1,140 @@ +#[doc = "Register `SUBSCRIBE_STOP` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SUBSCRIBE_STOP` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CHIDX` reader - DPPI channel that task STOP will subscribe to"] +pub type CHIDX_R = crate::FieldReader; +#[doc = "Field `CHIDX` writer - DPPI channel that task STOP will subscribe to"] +pub type CHIDX_W<'a, const O: u8> = crate::FieldWriter<'a, u32, SUBSCRIBE_STOP_SPEC, u8, u8, 8, O>; +#[doc = "Field `EN` reader - "] +pub type EN_R = crate::BitReader; +#[doc = "\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum EN_A { + #[doc = "0: Disable subscription"] + DISABLED = 0, + #[doc = "1: Enable subscription"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: EN_A) -> Self { + variant as u8 != 0 + } +} +impl EN_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EN_A { + match self.bits { + false => EN_A::DISABLED, + true => EN_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == EN_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == EN_A::ENABLED + } +} +#[doc = "Field `EN` writer - "] +pub type EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, SUBSCRIBE_STOP_SPEC, EN_A, O>; +impl<'a, const O: u8> EN_W<'a, O> { + #[doc = "Disable subscription"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(EN_A::DISABLED) + } + #[doc = "Enable subscription"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(EN_A::ENABLED) + } +} +impl R { + #[doc = "Bits 0:7 - DPPI channel that task STOP will subscribe to"] + #[inline(always)] + pub fn chidx(&self) -> CHIDX_R { + CHIDX_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&self) -> EN_R { + EN_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:7 - DPPI channel that task STOP will subscribe to"] + #[inline(always)] + pub fn chidx(&mut self) -> CHIDX_W<0> { + CHIDX_W::new(self) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&mut self) -> EN_W<31> { + EN_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Subscribe configuration for task STOP\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [subscribe_stop](index.html) module"] +pub struct SUBSCRIBE_STOP_SPEC; +impl crate::RegisterSpec for SUBSCRIBE_STOP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [subscribe_stop::R](R) reader structure"] +impl crate::Readable for SUBSCRIBE_STOP_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [subscribe_stop::W](W) writer structure"] +impl crate::Writable for SUBSCRIBE_STOP_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SUBSCRIBE_STOP to value 0"] +impl crate::Resettable for SUBSCRIBE_STOP_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/spim0_ns/subscribe_suspend.rs b/pacs/nrf9120-pac/src/spim0_ns/subscribe_suspend.rs new file mode 100644 index 00000000..b3fe4912 --- /dev/null +++ b/pacs/nrf9120-pac/src/spim0_ns/subscribe_suspend.rs @@ -0,0 +1,141 @@ +#[doc = "Register `SUBSCRIBE_SUSPEND` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SUBSCRIBE_SUSPEND` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CHIDX` reader - DPPI channel that task SUSPEND will subscribe to"] +pub type CHIDX_R = crate::FieldReader; +#[doc = "Field `CHIDX` writer - DPPI channel that task SUSPEND will subscribe to"] +pub type CHIDX_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, SUBSCRIBE_SUSPEND_SPEC, u8, u8, 8, O>; +#[doc = "Field `EN` reader - "] +pub type EN_R = crate::BitReader; +#[doc = "\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum EN_A { + #[doc = "0: Disable subscription"] + DISABLED = 0, + #[doc = "1: Enable subscription"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: EN_A) -> Self { + variant as u8 != 0 + } +} +impl EN_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EN_A { + match self.bits { + false => EN_A::DISABLED, + true => EN_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == EN_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == EN_A::ENABLED + } +} +#[doc = "Field `EN` writer - "] +pub type EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, SUBSCRIBE_SUSPEND_SPEC, EN_A, O>; +impl<'a, const O: u8> EN_W<'a, O> { + #[doc = "Disable subscription"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(EN_A::DISABLED) + } + #[doc = "Enable subscription"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(EN_A::ENABLED) + } +} +impl R { + #[doc = "Bits 0:7 - DPPI channel that task SUSPEND will subscribe to"] + #[inline(always)] + pub fn chidx(&self) -> CHIDX_R { + CHIDX_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&self) -> EN_R { + EN_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:7 - DPPI channel that task SUSPEND will subscribe to"] + #[inline(always)] + pub fn chidx(&mut self) -> CHIDX_W<0> { + CHIDX_W::new(self) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&mut self) -> EN_W<31> { + EN_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Subscribe configuration for task SUSPEND\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [subscribe_suspend](index.html) module"] +pub struct SUBSCRIBE_SUSPEND_SPEC; +impl crate::RegisterSpec for SUBSCRIBE_SUSPEND_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [subscribe_suspend::R](R) reader structure"] +impl crate::Readable for SUBSCRIBE_SUSPEND_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [subscribe_suspend::W](W) writer structure"] +impl crate::Writable for SUBSCRIBE_SUSPEND_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SUBSCRIBE_SUSPEND to value 0"] +impl crate::Resettable for SUBSCRIBE_SUSPEND_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/spim0_ns/tasks_resume.rs b/pacs/nrf9120-pac/src/spim0_ns/tasks_resume.rs new file mode 100644 index 00000000..8c0da4ad --- /dev/null +++ b/pacs/nrf9120-pac/src/spim0_ns/tasks_resume.rs @@ -0,0 +1,72 @@ +#[doc = "Register `TASKS_RESUME` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Resume SPI transaction\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum TASKS_RESUME_AW { + #[doc = "1: Trigger task"] + TRIGGER = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TASKS_RESUME_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TASKS_RESUME` writer - Resume SPI transaction"] +pub type TASKS_RESUME_W<'a, const O: u8> = + crate::BitWriter<'a, u32, TASKS_RESUME_SPEC, TASKS_RESUME_AW, O>; +impl<'a, const O: u8> TASKS_RESUME_W<'a, O> { + #[doc = "Trigger task"] + #[inline(always)] + pub fn trigger(self) -> &'a mut W { + self.variant(TASKS_RESUME_AW::TRIGGER) + } +} +impl W { + #[doc = "Bit 0 - Resume SPI transaction"] + #[inline(always)] + pub fn tasks_resume(&mut self) -> TASKS_RESUME_W<0> { + TASKS_RESUME_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Resume SPI transaction\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tasks_resume](index.html) module"] +pub struct TASKS_RESUME_SPEC; +impl crate::RegisterSpec for TASKS_RESUME_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [tasks_resume::W](W) writer structure"] +impl crate::Writable for TASKS_RESUME_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets TASKS_RESUME to value 0"] +impl crate::Resettable for TASKS_RESUME_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/spim0_ns/tasks_start.rs b/pacs/nrf9120-pac/src/spim0_ns/tasks_start.rs new file mode 100644 index 00000000..9c03f047 --- /dev/null +++ b/pacs/nrf9120-pac/src/spim0_ns/tasks_start.rs @@ -0,0 +1,72 @@ +#[doc = "Register `TASKS_START` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Start SPI transaction\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum TASKS_START_AW { + #[doc = "1: Trigger task"] + TRIGGER = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TASKS_START_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TASKS_START` writer - Start SPI transaction"] +pub type TASKS_START_W<'a, const O: u8> = + crate::BitWriter<'a, u32, TASKS_START_SPEC, TASKS_START_AW, O>; +impl<'a, const O: u8> TASKS_START_W<'a, O> { + #[doc = "Trigger task"] + #[inline(always)] + pub fn trigger(self) -> &'a mut W { + self.variant(TASKS_START_AW::TRIGGER) + } +} +impl W { + #[doc = "Bit 0 - Start SPI transaction"] + #[inline(always)] + pub fn tasks_start(&mut self) -> TASKS_START_W<0> { + TASKS_START_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Start SPI transaction\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tasks_start](index.html) module"] +pub struct TASKS_START_SPEC; +impl crate::RegisterSpec for TASKS_START_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [tasks_start::W](W) writer structure"] +impl crate::Writable for TASKS_START_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets TASKS_START to value 0"] +impl crate::Resettable for TASKS_START_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/spim0_ns/tasks_stop.rs b/pacs/nrf9120-pac/src/spim0_ns/tasks_stop.rs new file mode 100644 index 00000000..1d97e5d2 --- /dev/null +++ b/pacs/nrf9120-pac/src/spim0_ns/tasks_stop.rs @@ -0,0 +1,72 @@ +#[doc = "Register `TASKS_STOP` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Stop SPI transaction\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum TASKS_STOP_AW { + #[doc = "1: Trigger task"] + TRIGGER = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TASKS_STOP_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TASKS_STOP` writer - Stop SPI transaction"] +pub type TASKS_STOP_W<'a, const O: u8> = + crate::BitWriter<'a, u32, TASKS_STOP_SPEC, TASKS_STOP_AW, O>; +impl<'a, const O: u8> TASKS_STOP_W<'a, O> { + #[doc = "Trigger task"] + #[inline(always)] + pub fn trigger(self) -> &'a mut W { + self.variant(TASKS_STOP_AW::TRIGGER) + } +} +impl W { + #[doc = "Bit 0 - Stop SPI transaction"] + #[inline(always)] + pub fn tasks_stop(&mut self) -> TASKS_STOP_W<0> { + TASKS_STOP_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Stop SPI transaction\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tasks_stop](index.html) module"] +pub struct TASKS_STOP_SPEC; +impl crate::RegisterSpec for TASKS_STOP_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [tasks_stop::W](W) writer structure"] +impl crate::Writable for TASKS_STOP_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets TASKS_STOP to value 0"] +impl crate::Resettable for TASKS_STOP_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/spim0_ns/tasks_suspend.rs b/pacs/nrf9120-pac/src/spim0_ns/tasks_suspend.rs new file mode 100644 index 00000000..b9a698f7 --- /dev/null +++ b/pacs/nrf9120-pac/src/spim0_ns/tasks_suspend.rs @@ -0,0 +1,72 @@ +#[doc = "Register `TASKS_SUSPEND` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Suspend SPI transaction\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum TASKS_SUSPEND_AW { + #[doc = "1: Trigger task"] + TRIGGER = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TASKS_SUSPEND_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TASKS_SUSPEND` writer - Suspend SPI transaction"] +pub type TASKS_SUSPEND_W<'a, const O: u8> = + crate::BitWriter<'a, u32, TASKS_SUSPEND_SPEC, TASKS_SUSPEND_AW, O>; +impl<'a, const O: u8> TASKS_SUSPEND_W<'a, O> { + #[doc = "Trigger task"] + #[inline(always)] + pub fn trigger(self) -> &'a mut W { + self.variant(TASKS_SUSPEND_AW::TRIGGER) + } +} +impl W { + #[doc = "Bit 0 - Suspend SPI transaction"] + #[inline(always)] + pub fn tasks_suspend(&mut self) -> TASKS_SUSPEND_W<0> { + TASKS_SUSPEND_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Suspend SPI transaction\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tasks_suspend](index.html) module"] +pub struct TASKS_SUSPEND_SPEC; +impl crate::RegisterSpec for TASKS_SUSPEND_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [tasks_suspend::W](W) writer structure"] +impl crate::Writable for TASKS_SUSPEND_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets TASKS_SUSPEND to value 0"] +impl crate::Resettable for TASKS_SUSPEND_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/spim0_ns/txd.rs b/pacs/nrf9120-pac/src/spim0_ns/txd.rs new file mode 100644 index 00000000..19ea101d --- /dev/null +++ b/pacs/nrf9120-pac/src/spim0_ns/txd.rs @@ -0,0 +1,28 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct TXD { + #[doc = "0x00 - Data pointer"] + pub ptr: PTR, + #[doc = "0x04 - Maximum number of bytes in transmit buffer"] + pub maxcnt: MAXCNT, + #[doc = "0x08 - Number of bytes transferred in the last transaction"] + pub amount: AMOUNT, + #[doc = "0x0c - EasyDMA list type"] + pub list: LIST, +} +#[doc = "PTR (rw) register accessor: an alias for `Reg`"] +pub type PTR = crate::Reg; +#[doc = "Data pointer"] +pub mod ptr; +#[doc = "MAXCNT (rw) register accessor: an alias for `Reg`"] +pub type MAXCNT = crate::Reg; +#[doc = "Maximum number of bytes in transmit buffer"] +pub mod maxcnt; +#[doc = "AMOUNT (r) register accessor: an alias for `Reg`"] +pub type AMOUNT = crate::Reg; +#[doc = "Number of bytes transferred in the last transaction"] +pub mod amount; +#[doc = "LIST (rw) register accessor: an alias for `Reg`"] +pub type LIST = crate::Reg; +#[doc = "EasyDMA list type"] +pub mod list; diff --git a/pacs/nrf9120-pac/src/spim0_ns/txd/amount.rs b/pacs/nrf9120-pac/src/spim0_ns/txd/amount.rs new file mode 100644 index 00000000..b8909afa --- /dev/null +++ b/pacs/nrf9120-pac/src/spim0_ns/txd/amount.rs @@ -0,0 +1,40 @@ +#[doc = "Register `AMOUNT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `AMOUNT` reader - Number of bytes transferred in the last transaction"] +pub type AMOUNT_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:12 - Number of bytes transferred in the last transaction"] + #[inline(always)] + pub fn amount(&self) -> AMOUNT_R { + AMOUNT_R::new((self.bits & 0x1fff) as u16) + } +} +#[doc = "Number of bytes transferred in the last transaction\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [amount](index.html) module"] +pub struct AMOUNT_SPEC; +impl crate::RegisterSpec for AMOUNT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [amount::R](R) reader structure"] +impl crate::Readable for AMOUNT_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets AMOUNT to value 0"] +impl crate::Resettable for AMOUNT_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/spim0_ns/txd/list.rs b/pacs/nrf9120-pac/src/spim0_ns/txd/list.rs new file mode 100644 index 00000000..aa379b8c --- /dev/null +++ b/pacs/nrf9120-pac/src/spim0_ns/txd/list.rs @@ -0,0 +1,128 @@ +#[doc = "Register `LIST` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `LIST` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `LIST` reader - List type"] +pub type LIST_R = crate::FieldReader; +#[doc = "List type\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum LIST_A { + #[doc = "0: Disable EasyDMA list"] + DISABLED = 0, + #[doc = "1: Use array list"] + ARRAY_LIST = 1, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LIST_A) -> Self { + variant as _ + } +} +impl LIST_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(LIST_A::DISABLED), + 1 => Some(LIST_A::ARRAY_LIST), + _ => None, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == LIST_A::DISABLED + } + #[doc = "Checks if the value of the field is `ARRAY_LIST`"] + #[inline(always)] + pub fn is_array_list(&self) -> bool { + *self == LIST_A::ARRAY_LIST + } +} +#[doc = "Field `LIST` writer - List type"] +pub type LIST_W<'a, const O: u8> = crate::FieldWriter<'a, u32, LIST_SPEC, u8, LIST_A, 2, O>; +impl<'a, const O: u8> LIST_W<'a, O> { + #[doc = "Disable EasyDMA list"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(LIST_A::DISABLED) + } + #[doc = "Use array list"] + #[inline(always)] + pub fn array_list(self) -> &'a mut W { + self.variant(LIST_A::ARRAY_LIST) + } +} +impl R { + #[doc = "Bits 0:1 - List type"] + #[inline(always)] + pub fn list(&self) -> LIST_R { + LIST_R::new((self.bits & 3) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - List type"] + #[inline(always)] + pub fn list(&mut self) -> LIST_W<0> { + LIST_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "EasyDMA list type\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [list](index.html) module"] +pub struct LIST_SPEC; +impl crate::RegisterSpec for LIST_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [list::R](R) reader structure"] +impl crate::Readable for LIST_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [list::W](W) writer structure"] +impl crate::Writable for LIST_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets LIST to value 0"] +impl crate::Resettable for LIST_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/spim0_ns/txd/maxcnt.rs b/pacs/nrf9120-pac/src/spim0_ns/txd/maxcnt.rs new file mode 100644 index 00000000..7ae96778 --- /dev/null +++ b/pacs/nrf9120-pac/src/spim0_ns/txd/maxcnt.rs @@ -0,0 +1,80 @@ +#[doc = "Register `MAXCNT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `MAXCNT` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `MAXCNT` reader - Maximum number of bytes in transmit buffer"] +pub type MAXCNT_R = crate::FieldReader; +#[doc = "Field `MAXCNT` writer - Maximum number of bytes in transmit buffer"] +pub type MAXCNT_W<'a, const O: u8> = crate::FieldWriter<'a, u32, MAXCNT_SPEC, u16, u16, 13, O>; +impl R { + #[doc = "Bits 0:12 - Maximum number of bytes in transmit buffer"] + #[inline(always)] + pub fn maxcnt(&self) -> MAXCNT_R { + MAXCNT_R::new((self.bits & 0x1fff) as u16) + } +} +impl W { + #[doc = "Bits 0:12 - Maximum number of bytes in transmit buffer"] + #[inline(always)] + pub fn maxcnt(&mut self) -> MAXCNT_W<0> { + MAXCNT_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Maximum number of bytes in transmit buffer\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [maxcnt](index.html) module"] +pub struct MAXCNT_SPEC; +impl crate::RegisterSpec for MAXCNT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [maxcnt::R](R) reader structure"] +impl crate::Readable for MAXCNT_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [maxcnt::W](W) writer structure"] +impl crate::Writable for MAXCNT_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets MAXCNT to value 0"] +impl crate::Resettable for MAXCNT_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/spim0_ns/txd/ptr.rs b/pacs/nrf9120-pac/src/spim0_ns/txd/ptr.rs new file mode 100644 index 00000000..d5f98439 --- /dev/null +++ b/pacs/nrf9120-pac/src/spim0_ns/txd/ptr.rs @@ -0,0 +1,80 @@ +#[doc = "Register `PTR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PTR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PTR` reader - Data pointer"] +pub type PTR_R = crate::FieldReader; +#[doc = "Field `PTR` writer - Data pointer"] +pub type PTR_W<'a, const O: u8> = crate::FieldWriter<'a, u32, PTR_SPEC, u32, u32, 32, O>; +impl R { + #[doc = "Bits 0:31 - Data pointer"] + #[inline(always)] + pub fn ptr(&self) -> PTR_R { + PTR_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Data pointer"] + #[inline(always)] + pub fn ptr(&mut self) -> PTR_W<0> { + PTR_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Data pointer\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ptr](index.html) module"] +pub struct PTR_SPEC; +impl crate::RegisterSpec for PTR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ptr::R](R) reader structure"] +impl crate::Readable for PTR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ptr::W](W) writer structure"] +impl crate::Writable for PTR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PTR to value 0"] +impl crate::Resettable for PTR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/spis0_ns.rs b/pacs/nrf9120-pac/src/spis0_ns.rs new file mode 100644 index 00000000..46342655 --- /dev/null +++ b/pacs/nrf9120-pac/src/spis0_ns.rs @@ -0,0 +1,156 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + _reserved0: [u8; 0x24], + #[doc = "0x24 - Acquire SPI semaphore"] + pub tasks_acquire: TASKS_ACQUIRE, + #[doc = "0x28 - Release SPI semaphore, enabling the SPI slave to acquire it"] + pub tasks_release: TASKS_RELEASE, + _reserved2: [u8; 0x78], + #[doc = "0xa4 - Subscribe configuration for task ACQUIRE"] + pub subscribe_acquire: SUBSCRIBE_ACQUIRE, + #[doc = "0xa8 - Subscribe configuration for task RELEASE"] + pub subscribe_release: SUBSCRIBE_RELEASE, + _reserved4: [u8; 0x58], + #[doc = "0x104 - Granted transaction completed"] + pub events_end: EVENTS_END, + _reserved5: [u8; 0x08], + #[doc = "0x110 - End of RXD buffer reached"] + pub events_endrx: EVENTS_ENDRX, + _reserved6: [u8; 0x14], + #[doc = "0x128 - Semaphore acquired"] + pub events_acquired: EVENTS_ACQUIRED, + _reserved7: [u8; 0x58], + #[doc = "0x184 - Publish configuration for event END"] + pub publish_end: PUBLISH_END, + _reserved8: [u8; 0x08], + #[doc = "0x190 - Publish configuration for event ENDRX"] + pub publish_endrx: PUBLISH_ENDRX, + _reserved9: [u8; 0x14], + #[doc = "0x1a8 - Publish configuration for event ACQUIRED"] + pub publish_acquired: PUBLISH_ACQUIRED, + _reserved10: [u8; 0x54], + #[doc = "0x200 - Shortcuts between local events and tasks"] + pub shorts: SHORTS, + _reserved11: [u8; 0x0100], + #[doc = "0x304 - Enable interrupt"] + pub intenset: INTENSET, + #[doc = "0x308 - Disable interrupt"] + pub intenclr: INTENCLR, + _reserved13: [u8; 0xf4], + #[doc = "0x400 - Semaphore status register"] + pub semstat: SEMSTAT, + _reserved14: [u8; 0x3c], + #[doc = "0x440 - Status from last transaction"] + pub status: STATUS, + _reserved15: [u8; 0xbc], + #[doc = "0x500 - Enable SPI slave"] + pub enable: ENABLE, + _reserved16: [u8; 0x04], + #[doc = "0x508..0x518 - Unspecified"] + pub psel: PSEL, + _reserved17: [u8; 0x1c], + #[doc = "0x534..0x544 - Unspecified"] + pub rxd: RXD, + #[doc = "0x544..0x554 - Unspecified"] + pub txd: TXD, + #[doc = "0x554 - Configuration register"] + pub config: CONFIG, + _reserved20: [u8; 0x04], + #[doc = "0x55c - Default character. Character clocked out in case of an ignored transaction."] + pub def: DEF, + _reserved21: [u8; 0x60], + #[doc = "0x5c0 - Over-read character"] + pub orc: ORC, +} +#[doc = "TASKS_ACQUIRE (w) register accessor: an alias for `Reg`"] +pub type TASKS_ACQUIRE = crate::Reg; +#[doc = "Acquire SPI semaphore"] +pub mod tasks_acquire; +#[doc = "TASKS_RELEASE (w) register accessor: an alias for `Reg`"] +pub type TASKS_RELEASE = crate::Reg; +#[doc = "Release SPI semaphore, enabling the SPI slave to acquire it"] +pub mod tasks_release; +#[doc = "SUBSCRIBE_ACQUIRE (rw) register accessor: an alias for `Reg`"] +pub type SUBSCRIBE_ACQUIRE = crate::Reg; +#[doc = "Subscribe configuration for task ACQUIRE"] +pub mod subscribe_acquire; +#[doc = "SUBSCRIBE_RELEASE (rw) register accessor: an alias for `Reg`"] +pub type SUBSCRIBE_RELEASE = crate::Reg; +#[doc = "Subscribe configuration for task RELEASE"] +pub mod subscribe_release; +#[doc = "EVENTS_END (rw) register accessor: an alias for `Reg`"] +pub type EVENTS_END = crate::Reg; +#[doc = "Granted transaction completed"] +pub mod events_end; +#[doc = "EVENTS_ENDRX (rw) register accessor: an alias for `Reg`"] +pub type EVENTS_ENDRX = crate::Reg; +#[doc = "End of RXD buffer reached"] +pub mod events_endrx; +#[doc = "EVENTS_ACQUIRED (rw) register accessor: an alias for `Reg`"] +pub type EVENTS_ACQUIRED = crate::Reg; +#[doc = "Semaphore acquired"] +pub mod events_acquired; +#[doc = "PUBLISH_END (rw) register accessor: an alias for `Reg`"] +pub type PUBLISH_END = crate::Reg; +#[doc = "Publish configuration for event END"] +pub mod publish_end; +#[doc = "PUBLISH_ENDRX (rw) register accessor: an alias for `Reg`"] +pub type PUBLISH_ENDRX = crate::Reg; +#[doc = "Publish configuration for event ENDRX"] +pub mod publish_endrx; +#[doc = "PUBLISH_ACQUIRED (rw) register accessor: an alias for `Reg`"] +pub type PUBLISH_ACQUIRED = crate::Reg; +#[doc = "Publish configuration for event ACQUIRED"] +pub mod publish_acquired; +#[doc = "SHORTS (rw) register accessor: an alias for `Reg`"] +pub type SHORTS = crate::Reg; +#[doc = "Shortcuts between local events and tasks"] +pub mod shorts; +#[doc = "INTENSET (rw) register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "Enable interrupt"] +pub mod intenset; +#[doc = "INTENCLR (rw) register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "Disable interrupt"] +pub mod intenclr; +#[doc = "SEMSTAT (r) register accessor: an alias for `Reg`"] +pub type SEMSTAT = crate::Reg; +#[doc = "Semaphore status register"] +pub mod semstat; +#[doc = "STATUS (rw) register accessor: an alias for `Reg`"] +pub type STATUS = crate::Reg; +#[doc = "Status from last transaction"] +pub mod status; +#[doc = "ENABLE (rw) register accessor: an alias for `Reg`"] +pub type ENABLE = crate::Reg; +#[doc = "Enable SPI slave"] +pub mod enable; +#[doc = "Unspecified"] +pub use psel::PSEL; +#[doc = r"Cluster"] +#[doc = "Unspecified"] +pub mod psel; +#[doc = "Unspecified"] +pub use rxd::RXD; +#[doc = r"Cluster"] +#[doc = "Unspecified"] +pub mod rxd; +#[doc = "Unspecified"] +pub use txd::TXD; +#[doc = r"Cluster"] +#[doc = "Unspecified"] +pub mod txd; +#[doc = "CONFIG (rw) register accessor: an alias for `Reg`"] +pub type CONFIG = crate::Reg; +#[doc = "Configuration register"] +pub mod config; +#[doc = "DEF (rw) register accessor: an alias for `Reg`"] +pub type DEF = crate::Reg; +#[doc = "Default character. Character clocked out in case of an ignored transaction."] +pub mod def; +#[doc = "ORC (rw) register accessor: an alias for `Reg`"] +pub type ORC = crate::Reg; +#[doc = "Over-read character"] +pub mod orc; diff --git a/pacs/nrf9120-pac/src/spis0_ns/config.rs b/pacs/nrf9120-pac/src/spis0_ns/config.rs new file mode 100644 index 00000000..e5f6d9e9 --- /dev/null +++ b/pacs/nrf9120-pac/src/spis0_ns/config.rs @@ -0,0 +1,246 @@ +#[doc = "Register `CONFIG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CONFIG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ORDER` reader - Bit order"] +pub type ORDER_R = crate::BitReader; +#[doc = "Bit order\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum ORDER_A { + #[doc = "0: Most significant bit shifted out first"] + MSB_FIRST = 0, + #[doc = "1: Least significant bit shifted out first"] + LSB_FIRST = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: ORDER_A) -> Self { + variant as u8 != 0 + } +} +impl ORDER_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> ORDER_A { + match self.bits { + false => ORDER_A::MSB_FIRST, + true => ORDER_A::LSB_FIRST, + } + } + #[doc = "Checks if the value of the field is `MSB_FIRST`"] + #[inline(always)] + pub fn is_msb_first(&self) -> bool { + *self == ORDER_A::MSB_FIRST + } + #[doc = "Checks if the value of the field is `LSB_FIRST`"] + #[inline(always)] + pub fn is_lsb_first(&self) -> bool { + *self == ORDER_A::LSB_FIRST + } +} +#[doc = "Field `ORDER` writer - Bit order"] +pub type ORDER_W<'a, const O: u8> = crate::BitWriter<'a, u32, CONFIG_SPEC, ORDER_A, O>; +impl<'a, const O: u8> ORDER_W<'a, O> { + #[doc = "Most significant bit shifted out first"] + #[inline(always)] + pub fn msb_first(self) -> &'a mut W { + self.variant(ORDER_A::MSB_FIRST) + } + #[doc = "Least significant bit shifted out first"] + #[inline(always)] + pub fn lsb_first(self) -> &'a mut W { + self.variant(ORDER_A::LSB_FIRST) + } +} +#[doc = "Field `CPHA` reader - Serial clock (SCK) phase"] +pub type CPHA_R = crate::BitReader; +#[doc = "Serial clock (SCK) phase\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CPHA_A { + #[doc = "0: Sample on leading edge of clock, shift serial data on trailing edge"] + LEADING = 0, + #[doc = "1: Sample on trailing edge of clock, shift serial data on leading edge"] + TRAILING = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CPHA_A) -> Self { + variant as u8 != 0 + } +} +impl CPHA_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CPHA_A { + match self.bits { + false => CPHA_A::LEADING, + true => CPHA_A::TRAILING, + } + } + #[doc = "Checks if the value of the field is `LEADING`"] + #[inline(always)] + pub fn is_leading(&self) -> bool { + *self == CPHA_A::LEADING + } + #[doc = "Checks if the value of the field is `TRAILING`"] + #[inline(always)] + pub fn is_trailing(&self) -> bool { + *self == CPHA_A::TRAILING + } +} +#[doc = "Field `CPHA` writer - Serial clock (SCK) phase"] +pub type CPHA_W<'a, const O: u8> = crate::BitWriter<'a, u32, CONFIG_SPEC, CPHA_A, O>; +impl<'a, const O: u8> CPHA_W<'a, O> { + #[doc = "Sample on leading edge of clock, shift serial data on trailing edge"] + #[inline(always)] + pub fn leading(self) -> &'a mut W { + self.variant(CPHA_A::LEADING) + } + #[doc = "Sample on trailing edge of clock, shift serial data on leading edge"] + #[inline(always)] + pub fn trailing(self) -> &'a mut W { + self.variant(CPHA_A::TRAILING) + } +} +#[doc = "Field `CPOL` reader - Serial clock (SCK) polarity"] +pub type CPOL_R = crate::BitReader; +#[doc = "Serial clock (SCK) polarity\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CPOL_A { + #[doc = "0: Active high"] + ACTIVE_HIGH = 0, + #[doc = "1: Active low"] + ACTIVE_LOW = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CPOL_A) -> Self { + variant as u8 != 0 + } +} +impl CPOL_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CPOL_A { + match self.bits { + false => CPOL_A::ACTIVE_HIGH, + true => CPOL_A::ACTIVE_LOW, + } + } + #[doc = "Checks if the value of the field is `ACTIVE_HIGH`"] + #[inline(always)] + pub fn is_active_high(&self) -> bool { + *self == CPOL_A::ACTIVE_HIGH + } + #[doc = "Checks if the value of the field is `ACTIVE_LOW`"] + #[inline(always)] + pub fn is_active_low(&self) -> bool { + *self == CPOL_A::ACTIVE_LOW + } +} +#[doc = "Field `CPOL` writer - Serial clock (SCK) polarity"] +pub type CPOL_W<'a, const O: u8> = crate::BitWriter<'a, u32, CONFIG_SPEC, CPOL_A, O>; +impl<'a, const O: u8> CPOL_W<'a, O> { + #[doc = "Active high"] + #[inline(always)] + pub fn active_high(self) -> &'a mut W { + self.variant(CPOL_A::ACTIVE_HIGH) + } + #[doc = "Active low"] + #[inline(always)] + pub fn active_low(self) -> &'a mut W { + self.variant(CPOL_A::ACTIVE_LOW) + } +} +impl R { + #[doc = "Bit 0 - Bit order"] + #[inline(always)] + pub fn order(&self) -> ORDER_R { + ORDER_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Serial clock (SCK) phase"] + #[inline(always)] + pub fn cpha(&self) -> CPHA_R { + CPHA_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Serial clock (SCK) polarity"] + #[inline(always)] + pub fn cpol(&self) -> CPOL_R { + CPOL_R::new(((self.bits >> 2) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Bit order"] + #[inline(always)] + pub fn order(&mut self) -> ORDER_W<0> { + ORDER_W::new(self) + } + #[doc = "Bit 1 - Serial clock (SCK) phase"] + #[inline(always)] + pub fn cpha(&mut self) -> CPHA_W<1> { + CPHA_W::new(self) + } + #[doc = "Bit 2 - Serial clock (SCK) polarity"] + #[inline(always)] + pub fn cpol(&mut self) -> CPOL_W<2> { + CPOL_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Configuration register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [config](index.html) module"] +pub struct CONFIG_SPEC; +impl crate::RegisterSpec for CONFIG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [config::R](R) reader structure"] +impl crate::Readable for CONFIG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [config::W](W) writer structure"] +impl crate::Writable for CONFIG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CONFIG to value 0"] +impl crate::Resettable for CONFIG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/spis0_ns/def.rs b/pacs/nrf9120-pac/src/spis0_ns/def.rs new file mode 100644 index 00000000..b126a456 --- /dev/null +++ b/pacs/nrf9120-pac/src/spis0_ns/def.rs @@ -0,0 +1,80 @@ +#[doc = "Register `DEF` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DEF` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DEF` reader - Default character. Character clocked out in case of an ignored transaction."] +pub type DEF_R = crate::FieldReader; +#[doc = "Field `DEF` writer - Default character. Character clocked out in case of an ignored transaction."] +pub type DEF_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DEF_SPEC, u8, u8, 8, O>; +impl R { + #[doc = "Bits 0:7 - Default character. Character clocked out in case of an ignored transaction."] + #[inline(always)] + pub fn def(&self) -> DEF_R { + DEF_R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Default character. Character clocked out in case of an ignored transaction."] + #[inline(always)] + pub fn def(&mut self) -> DEF_W<0> { + DEF_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Default character. Character clocked out in case of an ignored transaction.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [def](index.html) module"] +pub struct DEF_SPEC; +impl crate::RegisterSpec for DEF_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [def::R](R) reader structure"] +impl crate::Readable for DEF_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [def::W](W) writer structure"] +impl crate::Writable for DEF_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DEF to value 0"] +impl crate::Resettable for DEF_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/spis0_ns/enable.rs b/pacs/nrf9120-pac/src/spis0_ns/enable.rs new file mode 100644 index 00000000..43e7cda0 --- /dev/null +++ b/pacs/nrf9120-pac/src/spis0_ns/enable.rs @@ -0,0 +1,128 @@ +#[doc = "Register `ENABLE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `ENABLE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ENABLE` reader - Enable or disable SPI slave"] +pub type ENABLE_R = crate::FieldReader; +#[doc = "Enable or disable SPI slave\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum ENABLE_A { + #[doc = "0: Disable SPI slave"] + DISABLED = 0, + #[doc = "2: Enable SPI slave"] + ENABLED = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: ENABLE_A) -> Self { + variant as _ + } +} +impl ENABLE_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(ENABLE_A::DISABLED), + 2 => Some(ENABLE_A::ENABLED), + _ => None, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == ENABLE_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == ENABLE_A::ENABLED + } +} +#[doc = "Field `ENABLE` writer - Enable or disable SPI slave"] +pub type ENABLE_W<'a, const O: u8> = crate::FieldWriter<'a, u32, ENABLE_SPEC, u8, ENABLE_A, 4, O>; +impl<'a, const O: u8> ENABLE_W<'a, O> { + #[doc = "Disable SPI slave"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(ENABLE_A::DISABLED) + } + #[doc = "Enable SPI slave"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(ENABLE_A::ENABLED) + } +} +impl R { + #[doc = "Bits 0:3 - Enable or disable SPI slave"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new((self.bits & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - Enable or disable SPI slave"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W<0> { + ENABLE_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Enable SPI slave\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [enable](index.html) module"] +pub struct ENABLE_SPEC; +impl crate::RegisterSpec for ENABLE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [enable::R](R) reader structure"] +impl crate::Readable for ENABLE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [enable::W](W) writer structure"] +impl crate::Writable for ENABLE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets ENABLE to value 0"] +impl crate::Resettable for ENABLE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/spis0_ns/events_acquired.rs b/pacs/nrf9120-pac/src/spis0_ns/events_acquired.rs new file mode 100644 index 00000000..2db77569 --- /dev/null +++ b/pacs/nrf9120-pac/src/spis0_ns/events_acquired.rs @@ -0,0 +1,127 @@ +#[doc = "Register `EVENTS_ACQUIRED` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVENTS_ACQUIRED` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `EVENTS_ACQUIRED` reader - Semaphore acquired"] +pub type EVENTS_ACQUIRED_R = crate::BitReader; +#[doc = "Semaphore acquired\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum EVENTS_ACQUIRED_A { + #[doc = "0: Event not generated"] + NOT_GENERATED = 0, + #[doc = "1: Event generated"] + GENERATED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: EVENTS_ACQUIRED_A) -> Self { + variant as u8 != 0 + } +} +impl EVENTS_ACQUIRED_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EVENTS_ACQUIRED_A { + match self.bits { + false => EVENTS_ACQUIRED_A::NOT_GENERATED, + true => EVENTS_ACQUIRED_A::GENERATED, + } + } + #[doc = "Checks if the value of the field is `NOT_GENERATED`"] + #[inline(always)] + pub fn is_not_generated(&self) -> bool { + *self == EVENTS_ACQUIRED_A::NOT_GENERATED + } + #[doc = "Checks if the value of the field is `GENERATED`"] + #[inline(always)] + pub fn is_generated(&self) -> bool { + *self == EVENTS_ACQUIRED_A::GENERATED + } +} +#[doc = "Field `EVENTS_ACQUIRED` writer - Semaphore acquired"] +pub type EVENTS_ACQUIRED_W<'a, const O: u8> = + crate::BitWriter<'a, u32, EVENTS_ACQUIRED_SPEC, EVENTS_ACQUIRED_A, O>; +impl<'a, const O: u8> EVENTS_ACQUIRED_W<'a, O> { + #[doc = "Event not generated"] + #[inline(always)] + pub fn not_generated(self) -> &'a mut W { + self.variant(EVENTS_ACQUIRED_A::NOT_GENERATED) + } + #[doc = "Event generated"] + #[inline(always)] + pub fn generated(self) -> &'a mut W { + self.variant(EVENTS_ACQUIRED_A::GENERATED) + } +} +impl R { + #[doc = "Bit 0 - Semaphore acquired"] + #[inline(always)] + pub fn events_acquired(&self) -> EVENTS_ACQUIRED_R { + EVENTS_ACQUIRED_R::new((self.bits & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Semaphore acquired"] + #[inline(always)] + pub fn events_acquired(&mut self) -> EVENTS_ACQUIRED_W<0> { + EVENTS_ACQUIRED_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Semaphore acquired\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [events_acquired](index.html) module"] +pub struct EVENTS_ACQUIRED_SPEC; +impl crate::RegisterSpec for EVENTS_ACQUIRED_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [events_acquired::R](R) reader structure"] +impl crate::Readable for EVENTS_ACQUIRED_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [events_acquired::W](W) writer structure"] +impl crate::Writable for EVENTS_ACQUIRED_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EVENTS_ACQUIRED to value 0"] +impl crate::Resettable for EVENTS_ACQUIRED_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/spis0_ns/events_end.rs b/pacs/nrf9120-pac/src/spis0_ns/events_end.rs new file mode 100644 index 00000000..aee4fb49 --- /dev/null +++ b/pacs/nrf9120-pac/src/spis0_ns/events_end.rs @@ -0,0 +1,127 @@ +#[doc = "Register `EVENTS_END` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVENTS_END` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `EVENTS_END` reader - Granted transaction completed"] +pub type EVENTS_END_R = crate::BitReader; +#[doc = "Granted transaction completed\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum EVENTS_END_A { + #[doc = "0: Event not generated"] + NOT_GENERATED = 0, + #[doc = "1: Event generated"] + GENERATED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: EVENTS_END_A) -> Self { + variant as u8 != 0 + } +} +impl EVENTS_END_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EVENTS_END_A { + match self.bits { + false => EVENTS_END_A::NOT_GENERATED, + true => EVENTS_END_A::GENERATED, + } + } + #[doc = "Checks if the value of the field is `NOT_GENERATED`"] + #[inline(always)] + pub fn is_not_generated(&self) -> bool { + *self == EVENTS_END_A::NOT_GENERATED + } + #[doc = "Checks if the value of the field is `GENERATED`"] + #[inline(always)] + pub fn is_generated(&self) -> bool { + *self == EVENTS_END_A::GENERATED + } +} +#[doc = "Field `EVENTS_END` writer - Granted transaction completed"] +pub type EVENTS_END_W<'a, const O: u8> = + crate::BitWriter<'a, u32, EVENTS_END_SPEC, EVENTS_END_A, O>; +impl<'a, const O: u8> EVENTS_END_W<'a, O> { + #[doc = "Event not generated"] + #[inline(always)] + pub fn not_generated(self) -> &'a mut W { + self.variant(EVENTS_END_A::NOT_GENERATED) + } + #[doc = "Event generated"] + #[inline(always)] + pub fn generated(self) -> &'a mut W { + self.variant(EVENTS_END_A::GENERATED) + } +} +impl R { + #[doc = "Bit 0 - Granted transaction completed"] + #[inline(always)] + pub fn events_end(&self) -> EVENTS_END_R { + EVENTS_END_R::new((self.bits & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Granted transaction completed"] + #[inline(always)] + pub fn events_end(&mut self) -> EVENTS_END_W<0> { + EVENTS_END_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Granted transaction completed\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [events_end](index.html) module"] +pub struct EVENTS_END_SPEC; +impl crate::RegisterSpec for EVENTS_END_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [events_end::R](R) reader structure"] +impl crate::Readable for EVENTS_END_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [events_end::W](W) writer structure"] +impl crate::Writable for EVENTS_END_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EVENTS_END to value 0"] +impl crate::Resettable for EVENTS_END_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/spis0_ns/events_endrx.rs b/pacs/nrf9120-pac/src/spis0_ns/events_endrx.rs new file mode 100644 index 00000000..0963d202 --- /dev/null +++ b/pacs/nrf9120-pac/src/spis0_ns/events_endrx.rs @@ -0,0 +1,127 @@ +#[doc = "Register `EVENTS_ENDRX` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVENTS_ENDRX` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `EVENTS_ENDRX` reader - End of RXD buffer reached"] +pub type EVENTS_ENDRX_R = crate::BitReader; +#[doc = "End of RXD buffer reached\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum EVENTS_ENDRX_A { + #[doc = "0: Event not generated"] + NOT_GENERATED = 0, + #[doc = "1: Event generated"] + GENERATED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: EVENTS_ENDRX_A) -> Self { + variant as u8 != 0 + } +} +impl EVENTS_ENDRX_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EVENTS_ENDRX_A { + match self.bits { + false => EVENTS_ENDRX_A::NOT_GENERATED, + true => EVENTS_ENDRX_A::GENERATED, + } + } + #[doc = "Checks if the value of the field is `NOT_GENERATED`"] + #[inline(always)] + pub fn is_not_generated(&self) -> bool { + *self == EVENTS_ENDRX_A::NOT_GENERATED + } + #[doc = "Checks if the value of the field is `GENERATED`"] + #[inline(always)] + pub fn is_generated(&self) -> bool { + *self == EVENTS_ENDRX_A::GENERATED + } +} +#[doc = "Field `EVENTS_ENDRX` writer - End of RXD buffer reached"] +pub type EVENTS_ENDRX_W<'a, const O: u8> = + crate::BitWriter<'a, u32, EVENTS_ENDRX_SPEC, EVENTS_ENDRX_A, O>; +impl<'a, const O: u8> EVENTS_ENDRX_W<'a, O> { + #[doc = "Event not generated"] + #[inline(always)] + pub fn not_generated(self) -> &'a mut W { + self.variant(EVENTS_ENDRX_A::NOT_GENERATED) + } + #[doc = "Event generated"] + #[inline(always)] + pub fn generated(self) -> &'a mut W { + self.variant(EVENTS_ENDRX_A::GENERATED) + } +} +impl R { + #[doc = "Bit 0 - End of RXD buffer reached"] + #[inline(always)] + pub fn events_endrx(&self) -> EVENTS_ENDRX_R { + EVENTS_ENDRX_R::new((self.bits & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - End of RXD buffer reached"] + #[inline(always)] + pub fn events_endrx(&mut self) -> EVENTS_ENDRX_W<0> { + EVENTS_ENDRX_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "End of RXD buffer reached\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [events_endrx](index.html) module"] +pub struct EVENTS_ENDRX_SPEC; +impl crate::RegisterSpec for EVENTS_ENDRX_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [events_endrx::R](R) reader structure"] +impl crate::Readable for EVENTS_ENDRX_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [events_endrx::W](W) writer structure"] +impl crate::Writable for EVENTS_ENDRX_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EVENTS_ENDRX to value 0"] +impl crate::Resettable for EVENTS_ENDRX_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/spis0_ns/intenclr.rs b/pacs/nrf9120-pac/src/spis0_ns/intenclr.rs new file mode 100644 index 00000000..a06acb1b --- /dev/null +++ b/pacs/nrf9120-pac/src/spis0_ns/intenclr.rs @@ -0,0 +1,267 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `END` reader - Write '1' to disable interrupt for event END"] +pub type END_R = crate::BitReader; +#[doc = "Write '1' to disable interrupt for event END\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum END_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: END_A) -> Self { + variant as u8 != 0 + } +} +impl END_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> END_A { + match self.bits { + false => END_A::DISABLED, + true => END_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == END_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == END_A::ENABLED + } +} +#[doc = "Write '1' to disable interrupt for event END\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum END_AW { + #[doc = "1: Disable"] + CLEAR = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: END_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `END` writer - Write '1' to disable interrupt for event END"] +pub type END_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENCLR_SPEC, END_AW, O>; +impl<'a, const O: u8> END_W<'a, O> { + #[doc = "Disable"] + #[inline(always)] + pub fn clear(self) -> &'a mut W { + self.variant(END_AW::CLEAR) + } +} +#[doc = "Field `ENDRX` reader - Write '1' to disable interrupt for event ENDRX"] +pub type ENDRX_R = crate::BitReader; +#[doc = "Write '1' to disable interrupt for event ENDRX\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum ENDRX_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: ENDRX_A) -> Self { + variant as u8 != 0 + } +} +impl ENDRX_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> ENDRX_A { + match self.bits { + false => ENDRX_A::DISABLED, + true => ENDRX_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == ENDRX_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == ENDRX_A::ENABLED + } +} +#[doc = "Write '1' to disable interrupt for event ENDRX\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum ENDRX_AW { + #[doc = "1: Disable"] + CLEAR = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: ENDRX_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ENDRX` writer - Write '1' to disable interrupt for event ENDRX"] +pub type ENDRX_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENCLR_SPEC, ENDRX_AW, O>; +impl<'a, const O: u8> ENDRX_W<'a, O> { + #[doc = "Disable"] + #[inline(always)] + pub fn clear(self) -> &'a mut W { + self.variant(ENDRX_AW::CLEAR) + } +} +#[doc = "Field `ACQUIRED` reader - Write '1' to disable interrupt for event ACQUIRED"] +pub type ACQUIRED_R = crate::BitReader; +#[doc = "Write '1' to disable interrupt for event ACQUIRED\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum ACQUIRED_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: ACQUIRED_A) -> Self { + variant as u8 != 0 + } +} +impl ACQUIRED_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> ACQUIRED_A { + match self.bits { + false => ACQUIRED_A::DISABLED, + true => ACQUIRED_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == ACQUIRED_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == ACQUIRED_A::ENABLED + } +} +#[doc = "Write '1' to disable interrupt for event ACQUIRED\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum ACQUIRED_AW { + #[doc = "1: Disable"] + CLEAR = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: ACQUIRED_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ACQUIRED` writer - Write '1' to disable interrupt for event ACQUIRED"] +pub type ACQUIRED_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENCLR_SPEC, ACQUIRED_AW, O>; +impl<'a, const O: u8> ACQUIRED_W<'a, O> { + #[doc = "Disable"] + #[inline(always)] + pub fn clear(self) -> &'a mut W { + self.variant(ACQUIRED_AW::CLEAR) + } +} +impl R { + #[doc = "Bit 1 - Write '1' to disable interrupt for event END"] + #[inline(always)] + pub fn end(&self) -> END_R { + END_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 4 - Write '1' to disable interrupt for event ENDRX"] + #[inline(always)] + pub fn endrx(&self) -> ENDRX_R { + ENDRX_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 10 - Write '1' to disable interrupt for event ACQUIRED"] + #[inline(always)] + pub fn acquired(&self) -> ACQUIRED_R { + ACQUIRED_R::new(((self.bits >> 10) & 1) != 0) + } +} +impl W { + #[doc = "Bit 1 - Write '1' to disable interrupt for event END"] + #[inline(always)] + pub fn end(&mut self) -> END_W<1> { + END_W::new(self) + } + #[doc = "Bit 4 - Write '1' to disable interrupt for event ENDRX"] + #[inline(always)] + pub fn endrx(&mut self) -> ENDRX_W<4> { + ENDRX_W::new(self) + } + #[doc = "Bit 10 - Write '1' to disable interrupt for event ACQUIRED"] + #[inline(always)] + pub fn acquired(&mut self) -> ACQUIRED_W<10> { + ACQUIRED_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Disable interrupt\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/spis0_ns/intenset.rs b/pacs/nrf9120-pac/src/spis0_ns/intenset.rs new file mode 100644 index 00000000..7e4bbc05 --- /dev/null +++ b/pacs/nrf9120-pac/src/spis0_ns/intenset.rs @@ -0,0 +1,267 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `END` reader - Write '1' to enable interrupt for event END"] +pub type END_R = crate::BitReader; +#[doc = "Write '1' to enable interrupt for event END\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum END_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: END_A) -> Self { + variant as u8 != 0 + } +} +impl END_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> END_A { + match self.bits { + false => END_A::DISABLED, + true => END_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == END_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == END_A::ENABLED + } +} +#[doc = "Write '1' to enable interrupt for event END\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum END_AW { + #[doc = "1: Enable"] + SET = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: END_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `END` writer - Write '1' to enable interrupt for event END"] +pub type END_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENSET_SPEC, END_AW, O>; +impl<'a, const O: u8> END_W<'a, O> { + #[doc = "Enable"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(END_AW::SET) + } +} +#[doc = "Field `ENDRX` reader - Write '1' to enable interrupt for event ENDRX"] +pub type ENDRX_R = crate::BitReader; +#[doc = "Write '1' to enable interrupt for event ENDRX\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum ENDRX_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: ENDRX_A) -> Self { + variant as u8 != 0 + } +} +impl ENDRX_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> ENDRX_A { + match self.bits { + false => ENDRX_A::DISABLED, + true => ENDRX_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == ENDRX_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == ENDRX_A::ENABLED + } +} +#[doc = "Write '1' to enable interrupt for event ENDRX\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum ENDRX_AW { + #[doc = "1: Enable"] + SET = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: ENDRX_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ENDRX` writer - Write '1' to enable interrupt for event ENDRX"] +pub type ENDRX_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENSET_SPEC, ENDRX_AW, O>; +impl<'a, const O: u8> ENDRX_W<'a, O> { + #[doc = "Enable"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(ENDRX_AW::SET) + } +} +#[doc = "Field `ACQUIRED` reader - Write '1' to enable interrupt for event ACQUIRED"] +pub type ACQUIRED_R = crate::BitReader; +#[doc = "Write '1' to enable interrupt for event ACQUIRED\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum ACQUIRED_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: ACQUIRED_A) -> Self { + variant as u8 != 0 + } +} +impl ACQUIRED_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> ACQUIRED_A { + match self.bits { + false => ACQUIRED_A::DISABLED, + true => ACQUIRED_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == ACQUIRED_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == ACQUIRED_A::ENABLED + } +} +#[doc = "Write '1' to enable interrupt for event ACQUIRED\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum ACQUIRED_AW { + #[doc = "1: Enable"] + SET = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: ACQUIRED_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ACQUIRED` writer - Write '1' to enable interrupt for event ACQUIRED"] +pub type ACQUIRED_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENSET_SPEC, ACQUIRED_AW, O>; +impl<'a, const O: u8> ACQUIRED_W<'a, O> { + #[doc = "Enable"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(ACQUIRED_AW::SET) + } +} +impl R { + #[doc = "Bit 1 - Write '1' to enable interrupt for event END"] + #[inline(always)] + pub fn end(&self) -> END_R { + END_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 4 - Write '1' to enable interrupt for event ENDRX"] + #[inline(always)] + pub fn endrx(&self) -> ENDRX_R { + ENDRX_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 10 - Write '1' to enable interrupt for event ACQUIRED"] + #[inline(always)] + pub fn acquired(&self) -> ACQUIRED_R { + ACQUIRED_R::new(((self.bits >> 10) & 1) != 0) + } +} +impl W { + #[doc = "Bit 1 - Write '1' to enable interrupt for event END"] + #[inline(always)] + pub fn end(&mut self) -> END_W<1> { + END_W::new(self) + } + #[doc = "Bit 4 - Write '1' to enable interrupt for event ENDRX"] + #[inline(always)] + pub fn endrx(&mut self) -> ENDRX_W<4> { + ENDRX_W::new(self) + } + #[doc = "Bit 10 - Write '1' to enable interrupt for event ACQUIRED"] + #[inline(always)] + pub fn acquired(&mut self) -> ACQUIRED_W<10> { + ACQUIRED_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Enable interrupt\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/spis0_ns/orc.rs b/pacs/nrf9120-pac/src/spis0_ns/orc.rs new file mode 100644 index 00000000..505e6ca0 --- /dev/null +++ b/pacs/nrf9120-pac/src/spis0_ns/orc.rs @@ -0,0 +1,80 @@ +#[doc = "Register `ORC` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `ORC` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ORC` reader - Over-read character. Character clocked out after an over-read of the transmit buffer."] +pub type ORC_R = crate::FieldReader; +#[doc = "Field `ORC` writer - Over-read character. Character clocked out after an over-read of the transmit buffer."] +pub type ORC_W<'a, const O: u8> = crate::FieldWriter<'a, u32, ORC_SPEC, u8, u8, 8, O>; +impl R { + #[doc = "Bits 0:7 - Over-read character. Character clocked out after an over-read of the transmit buffer."] + #[inline(always)] + pub fn orc(&self) -> ORC_R { + ORC_R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Over-read character. Character clocked out after an over-read of the transmit buffer."] + #[inline(always)] + pub fn orc(&mut self) -> ORC_W<0> { + ORC_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Over-read character\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [orc](index.html) module"] +pub struct ORC_SPEC; +impl crate::RegisterSpec for ORC_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [orc::R](R) reader structure"] +impl crate::Readable for ORC_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [orc::W](W) writer structure"] +impl crate::Writable for ORC_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets ORC to value 0"] +impl crate::Resettable for ORC_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/spis0_ns/psel.rs b/pacs/nrf9120-pac/src/spis0_ns/psel.rs new file mode 100644 index 00000000..e4b4d4b4 --- /dev/null +++ b/pacs/nrf9120-pac/src/spis0_ns/psel.rs @@ -0,0 +1,28 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct PSEL { + #[doc = "0x00 - Pin select for SCK"] + pub sck: SCK, + #[doc = "0x04 - Pin select for MISO signal"] + pub miso: MISO, + #[doc = "0x08 - Pin select for MOSI signal"] + pub mosi: MOSI, + #[doc = "0x0c - Pin select for CSN signal"] + pub csn: CSN, +} +#[doc = "SCK (rw) register accessor: an alias for `Reg`"] +pub type SCK = crate::Reg; +#[doc = "Pin select for SCK"] +pub mod sck; +#[doc = "MISO (rw) register accessor: an alias for `Reg`"] +pub type MISO = crate::Reg; +#[doc = "Pin select for MISO signal"] +pub mod miso; +#[doc = "MOSI (rw) register accessor: an alias for `Reg`"] +pub type MOSI = crate::Reg; +#[doc = "Pin select for MOSI signal"] +pub mod mosi; +#[doc = "CSN (rw) register accessor: an alias for `Reg`"] +pub type CSN = crate::Reg; +#[doc = "Pin select for CSN signal"] +pub mod csn; diff --git a/pacs/nrf9120-pac/src/spis0_ns/psel/csn.rs b/pacs/nrf9120-pac/src/spis0_ns/psel/csn.rs new file mode 100644 index 00000000..712f957d --- /dev/null +++ b/pacs/nrf9120-pac/src/spis0_ns/psel/csn.rs @@ -0,0 +1,140 @@ +#[doc = "Register `CSN` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CSN` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PIN` reader - Pin number"] +pub type PIN_R = crate::FieldReader; +#[doc = "Field `PIN` writer - Pin number"] +pub type PIN_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CSN_SPEC, u8, u8, 5, O>; +#[doc = "Field `CONNECT` reader - Connection"] +pub type CONNECT_R = crate::BitReader; +#[doc = "Connection\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CONNECT_A { + #[doc = "1: Disconnect"] + DISCONNECTED = 1, + #[doc = "0: Connect"] + CONNECTED = 0, +} +impl From for bool { + #[inline(always)] + fn from(variant: CONNECT_A) -> Self { + variant as u8 != 0 + } +} +impl CONNECT_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CONNECT_A { + match self.bits { + true => CONNECT_A::DISCONNECTED, + false => CONNECT_A::CONNECTED, + } + } + #[doc = "Checks if the value of the field is `DISCONNECTED`"] + #[inline(always)] + pub fn is_disconnected(&self) -> bool { + *self == CONNECT_A::DISCONNECTED + } + #[doc = "Checks if the value of the field is `CONNECTED`"] + #[inline(always)] + pub fn is_connected(&self) -> bool { + *self == CONNECT_A::CONNECTED + } +} +#[doc = "Field `CONNECT` writer - Connection"] +pub type CONNECT_W<'a, const O: u8> = crate::BitWriter<'a, u32, CSN_SPEC, CONNECT_A, O>; +impl<'a, const O: u8> CONNECT_W<'a, O> { + #[doc = "Disconnect"] + #[inline(always)] + pub fn disconnected(self) -> &'a mut W { + self.variant(CONNECT_A::DISCONNECTED) + } + #[doc = "Connect"] + #[inline(always)] + pub fn connected(self) -> &'a mut W { + self.variant(CONNECT_A::CONNECTED) + } +} +impl R { + #[doc = "Bits 0:4 - Pin number"] + #[inline(always)] + pub fn pin(&self) -> PIN_R { + PIN_R::new((self.bits & 0x1f) as u8) + } + #[doc = "Bit 31 - Connection"] + #[inline(always)] + pub fn connect(&self) -> CONNECT_R { + CONNECT_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:4 - Pin number"] + #[inline(always)] + pub fn pin(&mut self) -> PIN_W<0> { + PIN_W::new(self) + } + #[doc = "Bit 31 - Connection"] + #[inline(always)] + pub fn connect(&mut self) -> CONNECT_W<31> { + CONNECT_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Pin select for CSN signal\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [csn](index.html) module"] +pub struct CSN_SPEC; +impl crate::RegisterSpec for CSN_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [csn::R](R) reader structure"] +impl crate::Readable for CSN_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [csn::W](W) writer structure"] +impl crate::Writable for CSN_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CSN to value 0xffff_ffff"] +impl crate::Resettable for CSN_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0xffff_ffff + } +} diff --git a/pacs/nrf9120-pac/src/spis0_ns/psel/miso.rs b/pacs/nrf9120-pac/src/spis0_ns/psel/miso.rs new file mode 100644 index 00000000..23df3916 --- /dev/null +++ b/pacs/nrf9120-pac/src/spis0_ns/psel/miso.rs @@ -0,0 +1,140 @@ +#[doc = "Register `MISO` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `MISO` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PIN` reader - Pin number"] +pub type PIN_R = crate::FieldReader; +#[doc = "Field `PIN` writer - Pin number"] +pub type PIN_W<'a, const O: u8> = crate::FieldWriter<'a, u32, MISO_SPEC, u8, u8, 5, O>; +#[doc = "Field `CONNECT` reader - Connection"] +pub type CONNECT_R = crate::BitReader; +#[doc = "Connection\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CONNECT_A { + #[doc = "1: Disconnect"] + DISCONNECTED = 1, + #[doc = "0: Connect"] + CONNECTED = 0, +} +impl From for bool { + #[inline(always)] + fn from(variant: CONNECT_A) -> Self { + variant as u8 != 0 + } +} +impl CONNECT_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CONNECT_A { + match self.bits { + true => CONNECT_A::DISCONNECTED, + false => CONNECT_A::CONNECTED, + } + } + #[doc = "Checks if the value of the field is `DISCONNECTED`"] + #[inline(always)] + pub fn is_disconnected(&self) -> bool { + *self == CONNECT_A::DISCONNECTED + } + #[doc = "Checks if the value of the field is `CONNECTED`"] + #[inline(always)] + pub fn is_connected(&self) -> bool { + *self == CONNECT_A::CONNECTED + } +} +#[doc = "Field `CONNECT` writer - Connection"] +pub type CONNECT_W<'a, const O: u8> = crate::BitWriter<'a, u32, MISO_SPEC, CONNECT_A, O>; +impl<'a, const O: u8> CONNECT_W<'a, O> { + #[doc = "Disconnect"] + #[inline(always)] + pub fn disconnected(self) -> &'a mut W { + self.variant(CONNECT_A::DISCONNECTED) + } + #[doc = "Connect"] + #[inline(always)] + pub fn connected(self) -> &'a mut W { + self.variant(CONNECT_A::CONNECTED) + } +} +impl R { + #[doc = "Bits 0:4 - Pin number"] + #[inline(always)] + pub fn pin(&self) -> PIN_R { + PIN_R::new((self.bits & 0x1f) as u8) + } + #[doc = "Bit 31 - Connection"] + #[inline(always)] + pub fn connect(&self) -> CONNECT_R { + CONNECT_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:4 - Pin number"] + #[inline(always)] + pub fn pin(&mut self) -> PIN_W<0> { + PIN_W::new(self) + } + #[doc = "Bit 31 - Connection"] + #[inline(always)] + pub fn connect(&mut self) -> CONNECT_W<31> { + CONNECT_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Pin select for MISO signal\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [miso](index.html) module"] +pub struct MISO_SPEC; +impl crate::RegisterSpec for MISO_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [miso::R](R) reader structure"] +impl crate::Readable for MISO_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [miso::W](W) writer structure"] +impl crate::Writable for MISO_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets MISO to value 0xffff_ffff"] +impl crate::Resettable for MISO_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0xffff_ffff + } +} diff --git a/pacs/nrf9120-pac/src/spis0_ns/psel/mosi.rs b/pacs/nrf9120-pac/src/spis0_ns/psel/mosi.rs new file mode 100644 index 00000000..628e39d7 --- /dev/null +++ b/pacs/nrf9120-pac/src/spis0_ns/psel/mosi.rs @@ -0,0 +1,140 @@ +#[doc = "Register `MOSI` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `MOSI` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PIN` reader - Pin number"] +pub type PIN_R = crate::FieldReader; +#[doc = "Field `PIN` writer - Pin number"] +pub type PIN_W<'a, const O: u8> = crate::FieldWriter<'a, u32, MOSI_SPEC, u8, u8, 5, O>; +#[doc = "Field `CONNECT` reader - Connection"] +pub type CONNECT_R = crate::BitReader; +#[doc = "Connection\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CONNECT_A { + #[doc = "1: Disconnect"] + DISCONNECTED = 1, + #[doc = "0: Connect"] + CONNECTED = 0, +} +impl From for bool { + #[inline(always)] + fn from(variant: CONNECT_A) -> Self { + variant as u8 != 0 + } +} +impl CONNECT_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CONNECT_A { + match self.bits { + true => CONNECT_A::DISCONNECTED, + false => CONNECT_A::CONNECTED, + } + } + #[doc = "Checks if the value of the field is `DISCONNECTED`"] + #[inline(always)] + pub fn is_disconnected(&self) -> bool { + *self == CONNECT_A::DISCONNECTED + } + #[doc = "Checks if the value of the field is `CONNECTED`"] + #[inline(always)] + pub fn is_connected(&self) -> bool { + *self == CONNECT_A::CONNECTED + } +} +#[doc = "Field `CONNECT` writer - Connection"] +pub type CONNECT_W<'a, const O: u8> = crate::BitWriter<'a, u32, MOSI_SPEC, CONNECT_A, O>; +impl<'a, const O: u8> CONNECT_W<'a, O> { + #[doc = "Disconnect"] + #[inline(always)] + pub fn disconnected(self) -> &'a mut W { + self.variant(CONNECT_A::DISCONNECTED) + } + #[doc = "Connect"] + #[inline(always)] + pub fn connected(self) -> &'a mut W { + self.variant(CONNECT_A::CONNECTED) + } +} +impl R { + #[doc = "Bits 0:4 - Pin number"] + #[inline(always)] + pub fn pin(&self) -> PIN_R { + PIN_R::new((self.bits & 0x1f) as u8) + } + #[doc = "Bit 31 - Connection"] + #[inline(always)] + pub fn connect(&self) -> CONNECT_R { + CONNECT_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:4 - Pin number"] + #[inline(always)] + pub fn pin(&mut self) -> PIN_W<0> { + PIN_W::new(self) + } + #[doc = "Bit 31 - Connection"] + #[inline(always)] + pub fn connect(&mut self) -> CONNECT_W<31> { + CONNECT_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Pin select for MOSI signal\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [mosi](index.html) module"] +pub struct MOSI_SPEC; +impl crate::RegisterSpec for MOSI_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [mosi::R](R) reader structure"] +impl crate::Readable for MOSI_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [mosi::W](W) writer structure"] +impl crate::Writable for MOSI_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets MOSI to value 0xffff_ffff"] +impl crate::Resettable for MOSI_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0xffff_ffff + } +} diff --git a/pacs/nrf9120-pac/src/spis0_ns/psel/sck.rs b/pacs/nrf9120-pac/src/spis0_ns/psel/sck.rs new file mode 100644 index 00000000..0b259c1c --- /dev/null +++ b/pacs/nrf9120-pac/src/spis0_ns/psel/sck.rs @@ -0,0 +1,140 @@ +#[doc = "Register `SCK` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SCK` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PIN` reader - Pin number"] +pub type PIN_R = crate::FieldReader; +#[doc = "Field `PIN` writer - Pin number"] +pub type PIN_W<'a, const O: u8> = crate::FieldWriter<'a, u32, SCK_SPEC, u8, u8, 5, O>; +#[doc = "Field `CONNECT` reader - Connection"] +pub type CONNECT_R = crate::BitReader; +#[doc = "Connection\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CONNECT_A { + #[doc = "1: Disconnect"] + DISCONNECTED = 1, + #[doc = "0: Connect"] + CONNECTED = 0, +} +impl From for bool { + #[inline(always)] + fn from(variant: CONNECT_A) -> Self { + variant as u8 != 0 + } +} +impl CONNECT_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CONNECT_A { + match self.bits { + true => CONNECT_A::DISCONNECTED, + false => CONNECT_A::CONNECTED, + } + } + #[doc = "Checks if the value of the field is `DISCONNECTED`"] + #[inline(always)] + pub fn is_disconnected(&self) -> bool { + *self == CONNECT_A::DISCONNECTED + } + #[doc = "Checks if the value of the field is `CONNECTED`"] + #[inline(always)] + pub fn is_connected(&self) -> bool { + *self == CONNECT_A::CONNECTED + } +} +#[doc = "Field `CONNECT` writer - Connection"] +pub type CONNECT_W<'a, const O: u8> = crate::BitWriter<'a, u32, SCK_SPEC, CONNECT_A, O>; +impl<'a, const O: u8> CONNECT_W<'a, O> { + #[doc = "Disconnect"] + #[inline(always)] + pub fn disconnected(self) -> &'a mut W { + self.variant(CONNECT_A::DISCONNECTED) + } + #[doc = "Connect"] + #[inline(always)] + pub fn connected(self) -> &'a mut W { + self.variant(CONNECT_A::CONNECTED) + } +} +impl R { + #[doc = "Bits 0:4 - Pin number"] + #[inline(always)] + pub fn pin(&self) -> PIN_R { + PIN_R::new((self.bits & 0x1f) as u8) + } + #[doc = "Bit 31 - Connection"] + #[inline(always)] + pub fn connect(&self) -> CONNECT_R { + CONNECT_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:4 - Pin number"] + #[inline(always)] + pub fn pin(&mut self) -> PIN_W<0> { + PIN_W::new(self) + } + #[doc = "Bit 31 - Connection"] + #[inline(always)] + pub fn connect(&mut self) -> CONNECT_W<31> { + CONNECT_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Pin select for SCK\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sck](index.html) module"] +pub struct SCK_SPEC; +impl crate::RegisterSpec for SCK_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [sck::R](R) reader structure"] +impl crate::Readable for SCK_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [sck::W](W) writer structure"] +impl crate::Writable for SCK_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SCK to value 0xffff_ffff"] +impl crate::Resettable for SCK_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0xffff_ffff + } +} diff --git a/pacs/nrf9120-pac/src/spis0_ns/publish_acquired.rs b/pacs/nrf9120-pac/src/spis0_ns/publish_acquired.rs new file mode 100644 index 00000000..d67ae2aa --- /dev/null +++ b/pacs/nrf9120-pac/src/spis0_ns/publish_acquired.rs @@ -0,0 +1,141 @@ +#[doc = "Register `PUBLISH_ACQUIRED` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PUBLISH_ACQUIRED` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CHIDX` reader - DPPI channel that event ACQUIRED will publish to"] +pub type CHIDX_R = crate::FieldReader; +#[doc = "Field `CHIDX` writer - DPPI channel that event ACQUIRED will publish to"] +pub type CHIDX_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, PUBLISH_ACQUIRED_SPEC, u8, u8, 8, O>; +#[doc = "Field `EN` reader - "] +pub type EN_R = crate::BitReader; +#[doc = "\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum EN_A { + #[doc = "0: Disable publishing"] + DISABLED = 0, + #[doc = "1: Enable publishing"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: EN_A) -> Self { + variant as u8 != 0 + } +} +impl EN_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EN_A { + match self.bits { + false => EN_A::DISABLED, + true => EN_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == EN_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == EN_A::ENABLED + } +} +#[doc = "Field `EN` writer - "] +pub type EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, PUBLISH_ACQUIRED_SPEC, EN_A, O>; +impl<'a, const O: u8> EN_W<'a, O> { + #[doc = "Disable publishing"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(EN_A::DISABLED) + } + #[doc = "Enable publishing"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(EN_A::ENABLED) + } +} +impl R { + #[doc = "Bits 0:7 - DPPI channel that event ACQUIRED will publish to"] + #[inline(always)] + pub fn chidx(&self) -> CHIDX_R { + CHIDX_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&self) -> EN_R { + EN_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:7 - DPPI channel that event ACQUIRED will publish to"] + #[inline(always)] + pub fn chidx(&mut self) -> CHIDX_W<0> { + CHIDX_W::new(self) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&mut self) -> EN_W<31> { + EN_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Publish configuration for event ACQUIRED\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [publish_acquired](index.html) module"] +pub struct PUBLISH_ACQUIRED_SPEC; +impl crate::RegisterSpec for PUBLISH_ACQUIRED_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [publish_acquired::R](R) reader structure"] +impl crate::Readable for PUBLISH_ACQUIRED_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [publish_acquired::W](W) writer structure"] +impl crate::Writable for PUBLISH_ACQUIRED_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PUBLISH_ACQUIRED to value 0"] +impl crate::Resettable for PUBLISH_ACQUIRED_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/spis0_ns/publish_end.rs b/pacs/nrf9120-pac/src/spis0_ns/publish_end.rs new file mode 100644 index 00000000..2006d5cf --- /dev/null +++ b/pacs/nrf9120-pac/src/spis0_ns/publish_end.rs @@ -0,0 +1,140 @@ +#[doc = "Register `PUBLISH_END` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PUBLISH_END` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CHIDX` reader - DPPI channel that event END will publish to"] +pub type CHIDX_R = crate::FieldReader; +#[doc = "Field `CHIDX` writer - DPPI channel that event END will publish to"] +pub type CHIDX_W<'a, const O: u8> = crate::FieldWriter<'a, u32, PUBLISH_END_SPEC, u8, u8, 8, O>; +#[doc = "Field `EN` reader - "] +pub type EN_R = crate::BitReader; +#[doc = "\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum EN_A { + #[doc = "0: Disable publishing"] + DISABLED = 0, + #[doc = "1: Enable publishing"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: EN_A) -> Self { + variant as u8 != 0 + } +} +impl EN_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EN_A { + match self.bits { + false => EN_A::DISABLED, + true => EN_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == EN_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == EN_A::ENABLED + } +} +#[doc = "Field `EN` writer - "] +pub type EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, PUBLISH_END_SPEC, EN_A, O>; +impl<'a, const O: u8> EN_W<'a, O> { + #[doc = "Disable publishing"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(EN_A::DISABLED) + } + #[doc = "Enable publishing"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(EN_A::ENABLED) + } +} +impl R { + #[doc = "Bits 0:7 - DPPI channel that event END will publish to"] + #[inline(always)] + pub fn chidx(&self) -> CHIDX_R { + CHIDX_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&self) -> EN_R { + EN_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:7 - DPPI channel that event END will publish to"] + #[inline(always)] + pub fn chidx(&mut self) -> CHIDX_W<0> { + CHIDX_W::new(self) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&mut self) -> EN_W<31> { + EN_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Publish configuration for event END\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [publish_end](index.html) module"] +pub struct PUBLISH_END_SPEC; +impl crate::RegisterSpec for PUBLISH_END_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [publish_end::R](R) reader structure"] +impl crate::Readable for PUBLISH_END_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [publish_end::W](W) writer structure"] +impl crate::Writable for PUBLISH_END_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PUBLISH_END to value 0"] +impl crate::Resettable for PUBLISH_END_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/spis0_ns/publish_endrx.rs b/pacs/nrf9120-pac/src/spis0_ns/publish_endrx.rs new file mode 100644 index 00000000..1c25570b --- /dev/null +++ b/pacs/nrf9120-pac/src/spis0_ns/publish_endrx.rs @@ -0,0 +1,140 @@ +#[doc = "Register `PUBLISH_ENDRX` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PUBLISH_ENDRX` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CHIDX` reader - DPPI channel that event ENDRX will publish to"] +pub type CHIDX_R = crate::FieldReader; +#[doc = "Field `CHIDX` writer - DPPI channel that event ENDRX will publish to"] +pub type CHIDX_W<'a, const O: u8> = crate::FieldWriter<'a, u32, PUBLISH_ENDRX_SPEC, u8, u8, 8, O>; +#[doc = "Field `EN` reader - "] +pub type EN_R = crate::BitReader; +#[doc = "\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum EN_A { + #[doc = "0: Disable publishing"] + DISABLED = 0, + #[doc = "1: Enable publishing"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: EN_A) -> Self { + variant as u8 != 0 + } +} +impl EN_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EN_A { + match self.bits { + false => EN_A::DISABLED, + true => EN_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == EN_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == EN_A::ENABLED + } +} +#[doc = "Field `EN` writer - "] +pub type EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, PUBLISH_ENDRX_SPEC, EN_A, O>; +impl<'a, const O: u8> EN_W<'a, O> { + #[doc = "Disable publishing"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(EN_A::DISABLED) + } + #[doc = "Enable publishing"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(EN_A::ENABLED) + } +} +impl R { + #[doc = "Bits 0:7 - DPPI channel that event ENDRX will publish to"] + #[inline(always)] + pub fn chidx(&self) -> CHIDX_R { + CHIDX_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&self) -> EN_R { + EN_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:7 - DPPI channel that event ENDRX will publish to"] + #[inline(always)] + pub fn chidx(&mut self) -> CHIDX_W<0> { + CHIDX_W::new(self) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&mut self) -> EN_W<31> { + EN_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Publish configuration for event ENDRX\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [publish_endrx](index.html) module"] +pub struct PUBLISH_ENDRX_SPEC; +impl crate::RegisterSpec for PUBLISH_ENDRX_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [publish_endrx::R](R) reader structure"] +impl crate::Readable for PUBLISH_ENDRX_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [publish_endrx::W](W) writer structure"] +impl crate::Writable for PUBLISH_ENDRX_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PUBLISH_ENDRX to value 0"] +impl crate::Resettable for PUBLISH_ENDRX_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/spis0_ns/rxd.rs b/pacs/nrf9120-pac/src/spis0_ns/rxd.rs new file mode 100644 index 00000000..a0dcd41d --- /dev/null +++ b/pacs/nrf9120-pac/src/spis0_ns/rxd.rs @@ -0,0 +1,28 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RXD { + #[doc = "0x00 - RXD data pointer"] + pub ptr: PTR, + #[doc = "0x04 - Maximum number of bytes in receive buffer"] + pub maxcnt: MAXCNT, + #[doc = "0x08 - Number of bytes received in last granted transaction"] + pub amount: AMOUNT, + #[doc = "0x0c - EasyDMA list type"] + pub list: LIST, +} +#[doc = "PTR (rw) register accessor: an alias for `Reg`"] +pub type PTR = crate::Reg; +#[doc = "RXD data pointer"] +pub mod ptr; +#[doc = "MAXCNT (rw) register accessor: an alias for `Reg`"] +pub type MAXCNT = crate::Reg; +#[doc = "Maximum number of bytes in receive buffer"] +pub mod maxcnt; +#[doc = "AMOUNT (r) register accessor: an alias for `Reg`"] +pub type AMOUNT = crate::Reg; +#[doc = "Number of bytes received in last granted transaction"] +pub mod amount; +#[doc = "LIST (rw) register accessor: an alias for `Reg`"] +pub type LIST = crate::Reg; +#[doc = "EasyDMA list type"] +pub mod list; diff --git a/pacs/nrf9120-pac/src/spis0_ns/rxd/amount.rs b/pacs/nrf9120-pac/src/spis0_ns/rxd/amount.rs new file mode 100644 index 00000000..f5ac730e --- /dev/null +++ b/pacs/nrf9120-pac/src/spis0_ns/rxd/amount.rs @@ -0,0 +1,40 @@ +#[doc = "Register `AMOUNT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `AMOUNT` reader - Number of bytes received in the last granted transaction"] +pub type AMOUNT_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:12 - Number of bytes received in the last granted transaction"] + #[inline(always)] + pub fn amount(&self) -> AMOUNT_R { + AMOUNT_R::new((self.bits & 0x1fff) as u16) + } +} +#[doc = "Number of bytes received in last granted transaction\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [amount](index.html) module"] +pub struct AMOUNT_SPEC; +impl crate::RegisterSpec for AMOUNT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [amount::R](R) reader structure"] +impl crate::Readable for AMOUNT_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets AMOUNT to value 0"] +impl crate::Resettable for AMOUNT_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/spis0_ns/rxd/list.rs b/pacs/nrf9120-pac/src/spis0_ns/rxd/list.rs new file mode 100644 index 00000000..aa379b8c --- /dev/null +++ b/pacs/nrf9120-pac/src/spis0_ns/rxd/list.rs @@ -0,0 +1,128 @@ +#[doc = "Register `LIST` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `LIST` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `LIST` reader - List type"] +pub type LIST_R = crate::FieldReader; +#[doc = "List type\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum LIST_A { + #[doc = "0: Disable EasyDMA list"] + DISABLED = 0, + #[doc = "1: Use array list"] + ARRAY_LIST = 1, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LIST_A) -> Self { + variant as _ + } +} +impl LIST_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(LIST_A::DISABLED), + 1 => Some(LIST_A::ARRAY_LIST), + _ => None, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == LIST_A::DISABLED + } + #[doc = "Checks if the value of the field is `ARRAY_LIST`"] + #[inline(always)] + pub fn is_array_list(&self) -> bool { + *self == LIST_A::ARRAY_LIST + } +} +#[doc = "Field `LIST` writer - List type"] +pub type LIST_W<'a, const O: u8> = crate::FieldWriter<'a, u32, LIST_SPEC, u8, LIST_A, 2, O>; +impl<'a, const O: u8> LIST_W<'a, O> { + #[doc = "Disable EasyDMA list"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(LIST_A::DISABLED) + } + #[doc = "Use array list"] + #[inline(always)] + pub fn array_list(self) -> &'a mut W { + self.variant(LIST_A::ARRAY_LIST) + } +} +impl R { + #[doc = "Bits 0:1 - List type"] + #[inline(always)] + pub fn list(&self) -> LIST_R { + LIST_R::new((self.bits & 3) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - List type"] + #[inline(always)] + pub fn list(&mut self) -> LIST_W<0> { + LIST_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "EasyDMA list type\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [list](index.html) module"] +pub struct LIST_SPEC; +impl crate::RegisterSpec for LIST_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [list::R](R) reader structure"] +impl crate::Readable for LIST_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [list::W](W) writer structure"] +impl crate::Writable for LIST_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets LIST to value 0"] +impl crate::Resettable for LIST_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/spis0_ns/rxd/maxcnt.rs b/pacs/nrf9120-pac/src/spis0_ns/rxd/maxcnt.rs new file mode 100644 index 00000000..0344ca9e --- /dev/null +++ b/pacs/nrf9120-pac/src/spis0_ns/rxd/maxcnt.rs @@ -0,0 +1,80 @@ +#[doc = "Register `MAXCNT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `MAXCNT` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `MAXCNT` reader - Maximum number of bytes in receive buffer"] +pub type MAXCNT_R = crate::FieldReader; +#[doc = "Field `MAXCNT` writer - Maximum number of bytes in receive buffer"] +pub type MAXCNT_W<'a, const O: u8> = crate::FieldWriter<'a, u32, MAXCNT_SPEC, u16, u16, 13, O>; +impl R { + #[doc = "Bits 0:12 - Maximum number of bytes in receive buffer"] + #[inline(always)] + pub fn maxcnt(&self) -> MAXCNT_R { + MAXCNT_R::new((self.bits & 0x1fff) as u16) + } +} +impl W { + #[doc = "Bits 0:12 - Maximum number of bytes in receive buffer"] + #[inline(always)] + pub fn maxcnt(&mut self) -> MAXCNT_W<0> { + MAXCNT_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Maximum number of bytes in receive buffer\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [maxcnt](index.html) module"] +pub struct MAXCNT_SPEC; +impl crate::RegisterSpec for MAXCNT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [maxcnt::R](R) reader structure"] +impl crate::Readable for MAXCNT_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [maxcnt::W](W) writer structure"] +impl crate::Writable for MAXCNT_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets MAXCNT to value 0"] +impl crate::Resettable for MAXCNT_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/spis0_ns/rxd/ptr.rs b/pacs/nrf9120-pac/src/spis0_ns/rxd/ptr.rs new file mode 100644 index 00000000..e7d7d781 --- /dev/null +++ b/pacs/nrf9120-pac/src/spis0_ns/rxd/ptr.rs @@ -0,0 +1,80 @@ +#[doc = "Register `PTR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PTR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PTR` reader - RXD data pointer"] +pub type PTR_R = crate::FieldReader; +#[doc = "Field `PTR` writer - RXD data pointer"] +pub type PTR_W<'a, const O: u8> = crate::FieldWriter<'a, u32, PTR_SPEC, u32, u32, 32, O>; +impl R { + #[doc = "Bits 0:31 - RXD data pointer"] + #[inline(always)] + pub fn ptr(&self) -> PTR_R { + PTR_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - RXD data pointer"] + #[inline(always)] + pub fn ptr(&mut self) -> PTR_W<0> { + PTR_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "RXD data pointer\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ptr](index.html) module"] +pub struct PTR_SPEC; +impl crate::RegisterSpec for PTR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ptr::R](R) reader structure"] +impl crate::Readable for PTR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ptr::W](W) writer structure"] +impl crate::Writable for PTR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PTR to value 0"] +impl crate::Resettable for PTR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/spis0_ns/semstat.rs b/pacs/nrf9120-pac/src/spis0_ns/semstat.rs new file mode 100644 index 00000000..b9b0b8b1 --- /dev/null +++ b/pacs/nrf9120-pac/src/spis0_ns/semstat.rs @@ -0,0 +1,92 @@ +#[doc = "Register `SEMSTAT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SEMSTAT` reader - Semaphore status"] +pub type SEMSTAT_R = crate::FieldReader; +#[doc = "Semaphore status\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SEMSTAT_A { + #[doc = "0: Semaphore is free"] + FREE = 0, + #[doc = "1: Semaphore is assigned to CPU"] + CPU = 1, + #[doc = "2: Semaphore is assigned to SPI slave"] + SPIS = 2, + #[doc = "3: Semaphore is assigned to SPI but a handover to the CPU is pending"] + CPUPENDING = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SEMSTAT_A) -> Self { + variant as _ + } +} +impl SEMSTAT_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> SEMSTAT_A { + match self.bits { + 0 => SEMSTAT_A::FREE, + 1 => SEMSTAT_A::CPU, + 2 => SEMSTAT_A::SPIS, + 3 => SEMSTAT_A::CPUPENDING, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `FREE`"] + #[inline(always)] + pub fn is_free(&self) -> bool { + *self == SEMSTAT_A::FREE + } + #[doc = "Checks if the value of the field is `CPU`"] + #[inline(always)] + pub fn is_cpu(&self) -> bool { + *self == SEMSTAT_A::CPU + } + #[doc = "Checks if the value of the field is `SPIS`"] + #[inline(always)] + pub fn is_spis(&self) -> bool { + *self == SEMSTAT_A::SPIS + } + #[doc = "Checks if the value of the field is `CPUPENDING`"] + #[inline(always)] + pub fn is_cpupending(&self) -> bool { + *self == SEMSTAT_A::CPUPENDING + } +} +impl R { + #[doc = "Bits 0:1 - Semaphore status"] + #[inline(always)] + pub fn semstat(&self) -> SEMSTAT_R { + SEMSTAT_R::new((self.bits & 3) as u8) + } +} +#[doc = "Semaphore status register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [semstat](index.html) module"] +pub struct SEMSTAT_SPEC; +impl crate::RegisterSpec for SEMSTAT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [semstat::R](R) reader structure"] +impl crate::Readable for SEMSTAT_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets SEMSTAT to value 0x01"] +impl crate::Resettable for SEMSTAT_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x01 + } +} diff --git a/pacs/nrf9120-pac/src/spis0_ns/shorts.rs b/pacs/nrf9120-pac/src/spis0_ns/shorts.rs new file mode 100644 index 00000000..7e093e0f --- /dev/null +++ b/pacs/nrf9120-pac/src/spis0_ns/shorts.rs @@ -0,0 +1,126 @@ +#[doc = "Register `SHORTS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SHORTS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `END_ACQUIRE` reader - Shortcut between event END and task ACQUIRE"] +pub type END_ACQUIRE_R = crate::BitReader; +#[doc = "Shortcut between event END and task ACQUIRE\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum END_ACQUIRE_A { + #[doc = "0: Disable shortcut"] + DISABLED = 0, + #[doc = "1: Enable shortcut"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: END_ACQUIRE_A) -> Self { + variant as u8 != 0 + } +} +impl END_ACQUIRE_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> END_ACQUIRE_A { + match self.bits { + false => END_ACQUIRE_A::DISABLED, + true => END_ACQUIRE_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == END_ACQUIRE_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == END_ACQUIRE_A::ENABLED + } +} +#[doc = "Field `END_ACQUIRE` writer - Shortcut between event END and task ACQUIRE"] +pub type END_ACQUIRE_W<'a, const O: u8> = crate::BitWriter<'a, u32, SHORTS_SPEC, END_ACQUIRE_A, O>; +impl<'a, const O: u8> END_ACQUIRE_W<'a, O> { + #[doc = "Disable shortcut"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(END_ACQUIRE_A::DISABLED) + } + #[doc = "Enable shortcut"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(END_ACQUIRE_A::ENABLED) + } +} +impl R { + #[doc = "Bit 2 - Shortcut between event END and task ACQUIRE"] + #[inline(always)] + pub fn end_acquire(&self) -> END_ACQUIRE_R { + END_ACQUIRE_R::new(((self.bits >> 2) & 1) != 0) + } +} +impl W { + #[doc = "Bit 2 - Shortcut between event END and task ACQUIRE"] + #[inline(always)] + pub fn end_acquire(&mut self) -> END_ACQUIRE_W<2> { + END_ACQUIRE_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Shortcuts between local events and tasks\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [shorts](index.html) module"] +pub struct SHORTS_SPEC; +impl crate::RegisterSpec for SHORTS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [shorts::R](R) reader structure"] +impl crate::Readable for SHORTS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [shorts::W](W) writer structure"] +impl crate::Writable for SHORTS_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SHORTS to value 0"] +impl crate::Resettable for SHORTS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/spis0_ns/status.rs b/pacs/nrf9120-pac/src/spis0_ns/status.rs new file mode 100644 index 00000000..028e362b --- /dev/null +++ b/pacs/nrf9120-pac/src/spis0_ns/status.rs @@ -0,0 +1,200 @@ +#[doc = "Register `STATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `STATUS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `OVERREAD` reader - TX buffer over-read detected, and prevented"] +pub type OVERREAD_R = crate::BitReader; +#[doc = "TX buffer over-read detected, and prevented\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum OVERREAD_A { + #[doc = "0: Read: error not present"] + NOT_PRESENT = 0, + #[doc = "1: Read: error present"] + PRESENT = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: OVERREAD_A) -> Self { + variant as u8 != 0 + } +} +impl OVERREAD_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> OVERREAD_A { + match self.bits { + false => OVERREAD_A::NOT_PRESENT, + true => OVERREAD_A::PRESENT, + } + } + #[doc = "Checks if the value of the field is `NOT_PRESENT`"] + #[inline(always)] + pub fn is_not_present(&self) -> bool { + *self == OVERREAD_A::NOT_PRESENT + } + #[doc = "Checks if the value of the field is `PRESENT`"] + #[inline(always)] + pub fn is_present(&self) -> bool { + *self == OVERREAD_A::PRESENT + } +} +#[doc = "TX buffer over-read detected, and prevented\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum OVERREAD_AW { + #[doc = "1: Write: clear error on writing '1'"] + CLEAR = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: OVERREAD_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `OVERREAD` writer - TX buffer over-read detected, and prevented"] +pub type OVERREAD_W<'a, const O: u8> = crate::BitWriter<'a, u32, STATUS_SPEC, OVERREAD_AW, O>; +impl<'a, const O: u8> OVERREAD_W<'a, O> { + #[doc = "Write: clear error on writing '1'"] + #[inline(always)] + pub fn clear(self) -> &'a mut W { + self.variant(OVERREAD_AW::CLEAR) + } +} +#[doc = "Field `OVERFLOW` reader - RX buffer overflow detected, and prevented"] +pub type OVERFLOW_R = crate::BitReader; +#[doc = "RX buffer overflow detected, and prevented\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum OVERFLOW_A { + #[doc = "0: Read: error not present"] + NOT_PRESENT = 0, + #[doc = "1: Read: error present"] + PRESENT = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: OVERFLOW_A) -> Self { + variant as u8 != 0 + } +} +impl OVERFLOW_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> OVERFLOW_A { + match self.bits { + false => OVERFLOW_A::NOT_PRESENT, + true => OVERFLOW_A::PRESENT, + } + } + #[doc = "Checks if the value of the field is `NOT_PRESENT`"] + #[inline(always)] + pub fn is_not_present(&self) -> bool { + *self == OVERFLOW_A::NOT_PRESENT + } + #[doc = "Checks if the value of the field is `PRESENT`"] + #[inline(always)] + pub fn is_present(&self) -> bool { + *self == OVERFLOW_A::PRESENT + } +} +#[doc = "RX buffer overflow detected, and prevented\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum OVERFLOW_AW { + #[doc = "1: Write: clear error on writing '1'"] + CLEAR = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: OVERFLOW_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `OVERFLOW` writer - RX buffer overflow detected, and prevented"] +pub type OVERFLOW_W<'a, const O: u8> = crate::BitWriter<'a, u32, STATUS_SPEC, OVERFLOW_AW, O>; +impl<'a, const O: u8> OVERFLOW_W<'a, O> { + #[doc = "Write: clear error on writing '1'"] + #[inline(always)] + pub fn clear(self) -> &'a mut W { + self.variant(OVERFLOW_AW::CLEAR) + } +} +impl R { + #[doc = "Bit 0 - TX buffer over-read detected, and prevented"] + #[inline(always)] + pub fn overread(&self) -> OVERREAD_R { + OVERREAD_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - RX buffer overflow detected, and prevented"] + #[inline(always)] + pub fn overflow(&self) -> OVERFLOW_R { + OVERFLOW_R::new(((self.bits >> 1) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - TX buffer over-read detected, and prevented"] + #[inline(always)] + pub fn overread(&mut self) -> OVERREAD_W<0> { + OVERREAD_W::new(self) + } + #[doc = "Bit 1 - RX buffer overflow detected, and prevented"] + #[inline(always)] + pub fn overflow(&mut self) -> OVERFLOW_W<1> { + OVERFLOW_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Status from last transaction\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [status::R](R) reader structure"] +impl crate::Readable for STATUS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [status::W](W) writer structure"] +impl crate::Writable for STATUS_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets STATUS to value 0"] +impl crate::Resettable for STATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/spis0_ns/subscribe_acquire.rs b/pacs/nrf9120-pac/src/spis0_ns/subscribe_acquire.rs new file mode 100644 index 00000000..1bf34e16 --- /dev/null +++ b/pacs/nrf9120-pac/src/spis0_ns/subscribe_acquire.rs @@ -0,0 +1,141 @@ +#[doc = "Register `SUBSCRIBE_ACQUIRE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SUBSCRIBE_ACQUIRE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CHIDX` reader - DPPI channel that task ACQUIRE will subscribe to"] +pub type CHIDX_R = crate::FieldReader; +#[doc = "Field `CHIDX` writer - DPPI channel that task ACQUIRE will subscribe to"] +pub type CHIDX_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, SUBSCRIBE_ACQUIRE_SPEC, u8, u8, 8, O>; +#[doc = "Field `EN` reader - "] +pub type EN_R = crate::BitReader; +#[doc = "\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum EN_A { + #[doc = "0: Disable subscription"] + DISABLED = 0, + #[doc = "1: Enable subscription"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: EN_A) -> Self { + variant as u8 != 0 + } +} +impl EN_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EN_A { + match self.bits { + false => EN_A::DISABLED, + true => EN_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == EN_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == EN_A::ENABLED + } +} +#[doc = "Field `EN` writer - "] +pub type EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, SUBSCRIBE_ACQUIRE_SPEC, EN_A, O>; +impl<'a, const O: u8> EN_W<'a, O> { + #[doc = "Disable subscription"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(EN_A::DISABLED) + } + #[doc = "Enable subscription"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(EN_A::ENABLED) + } +} +impl R { + #[doc = "Bits 0:7 - DPPI channel that task ACQUIRE will subscribe to"] + #[inline(always)] + pub fn chidx(&self) -> CHIDX_R { + CHIDX_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&self) -> EN_R { + EN_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:7 - DPPI channel that task ACQUIRE will subscribe to"] + #[inline(always)] + pub fn chidx(&mut self) -> CHIDX_W<0> { + CHIDX_W::new(self) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&mut self) -> EN_W<31> { + EN_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Subscribe configuration for task ACQUIRE\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [subscribe_acquire](index.html) module"] +pub struct SUBSCRIBE_ACQUIRE_SPEC; +impl crate::RegisterSpec for SUBSCRIBE_ACQUIRE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [subscribe_acquire::R](R) reader structure"] +impl crate::Readable for SUBSCRIBE_ACQUIRE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [subscribe_acquire::W](W) writer structure"] +impl crate::Writable for SUBSCRIBE_ACQUIRE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SUBSCRIBE_ACQUIRE to value 0"] +impl crate::Resettable for SUBSCRIBE_ACQUIRE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/spis0_ns/subscribe_release.rs b/pacs/nrf9120-pac/src/spis0_ns/subscribe_release.rs new file mode 100644 index 00000000..85eacc4d --- /dev/null +++ b/pacs/nrf9120-pac/src/spis0_ns/subscribe_release.rs @@ -0,0 +1,141 @@ +#[doc = "Register `SUBSCRIBE_RELEASE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SUBSCRIBE_RELEASE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CHIDX` reader - DPPI channel that task RELEASE will subscribe to"] +pub type CHIDX_R = crate::FieldReader; +#[doc = "Field `CHIDX` writer - DPPI channel that task RELEASE will subscribe to"] +pub type CHIDX_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, SUBSCRIBE_RELEASE_SPEC, u8, u8, 8, O>; +#[doc = "Field `EN` reader - "] +pub type EN_R = crate::BitReader; +#[doc = "\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum EN_A { + #[doc = "0: Disable subscription"] + DISABLED = 0, + #[doc = "1: Enable subscription"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: EN_A) -> Self { + variant as u8 != 0 + } +} +impl EN_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EN_A { + match self.bits { + false => EN_A::DISABLED, + true => EN_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == EN_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == EN_A::ENABLED + } +} +#[doc = "Field `EN` writer - "] +pub type EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, SUBSCRIBE_RELEASE_SPEC, EN_A, O>; +impl<'a, const O: u8> EN_W<'a, O> { + #[doc = "Disable subscription"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(EN_A::DISABLED) + } + #[doc = "Enable subscription"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(EN_A::ENABLED) + } +} +impl R { + #[doc = "Bits 0:7 - DPPI channel that task RELEASE will subscribe to"] + #[inline(always)] + pub fn chidx(&self) -> CHIDX_R { + CHIDX_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&self) -> EN_R { + EN_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:7 - DPPI channel that task RELEASE will subscribe to"] + #[inline(always)] + pub fn chidx(&mut self) -> CHIDX_W<0> { + CHIDX_W::new(self) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&mut self) -> EN_W<31> { + EN_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Subscribe configuration for task RELEASE\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [subscribe_release](index.html) module"] +pub struct SUBSCRIBE_RELEASE_SPEC; +impl crate::RegisterSpec for SUBSCRIBE_RELEASE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [subscribe_release::R](R) reader structure"] +impl crate::Readable for SUBSCRIBE_RELEASE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [subscribe_release::W](W) writer structure"] +impl crate::Writable for SUBSCRIBE_RELEASE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SUBSCRIBE_RELEASE to value 0"] +impl crate::Resettable for SUBSCRIBE_RELEASE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/spis0_ns/tasks_acquire.rs b/pacs/nrf9120-pac/src/spis0_ns/tasks_acquire.rs new file mode 100644 index 00000000..7bdc94c0 --- /dev/null +++ b/pacs/nrf9120-pac/src/spis0_ns/tasks_acquire.rs @@ -0,0 +1,72 @@ +#[doc = "Register `TASKS_ACQUIRE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Acquire SPI semaphore\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum TASKS_ACQUIRE_AW { + #[doc = "1: Trigger task"] + TRIGGER = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TASKS_ACQUIRE_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TASKS_ACQUIRE` writer - Acquire SPI semaphore"] +pub type TASKS_ACQUIRE_W<'a, const O: u8> = + crate::BitWriter<'a, u32, TASKS_ACQUIRE_SPEC, TASKS_ACQUIRE_AW, O>; +impl<'a, const O: u8> TASKS_ACQUIRE_W<'a, O> { + #[doc = "Trigger task"] + #[inline(always)] + pub fn trigger(self) -> &'a mut W { + self.variant(TASKS_ACQUIRE_AW::TRIGGER) + } +} +impl W { + #[doc = "Bit 0 - Acquire SPI semaphore"] + #[inline(always)] + pub fn tasks_acquire(&mut self) -> TASKS_ACQUIRE_W<0> { + TASKS_ACQUIRE_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Acquire SPI semaphore\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tasks_acquire](index.html) module"] +pub struct TASKS_ACQUIRE_SPEC; +impl crate::RegisterSpec for TASKS_ACQUIRE_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [tasks_acquire::W](W) writer structure"] +impl crate::Writable for TASKS_ACQUIRE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets TASKS_ACQUIRE to value 0"] +impl crate::Resettable for TASKS_ACQUIRE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/spis0_ns/tasks_release.rs b/pacs/nrf9120-pac/src/spis0_ns/tasks_release.rs new file mode 100644 index 00000000..e2ab1b72 --- /dev/null +++ b/pacs/nrf9120-pac/src/spis0_ns/tasks_release.rs @@ -0,0 +1,72 @@ +#[doc = "Register `TASKS_RELEASE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Release SPI semaphore, enabling the SPI slave to acquire it\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum TASKS_RELEASE_AW { + #[doc = "1: Trigger task"] + TRIGGER = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TASKS_RELEASE_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TASKS_RELEASE` writer - Release SPI semaphore, enabling the SPI slave to acquire it"] +pub type TASKS_RELEASE_W<'a, const O: u8> = + crate::BitWriter<'a, u32, TASKS_RELEASE_SPEC, TASKS_RELEASE_AW, O>; +impl<'a, const O: u8> TASKS_RELEASE_W<'a, O> { + #[doc = "Trigger task"] + #[inline(always)] + pub fn trigger(self) -> &'a mut W { + self.variant(TASKS_RELEASE_AW::TRIGGER) + } +} +impl W { + #[doc = "Bit 0 - Release SPI semaphore, enabling the SPI slave to acquire it"] + #[inline(always)] + pub fn tasks_release(&mut self) -> TASKS_RELEASE_W<0> { + TASKS_RELEASE_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Release SPI semaphore, enabling the SPI slave to acquire it\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tasks_release](index.html) module"] +pub struct TASKS_RELEASE_SPEC; +impl crate::RegisterSpec for TASKS_RELEASE_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [tasks_release::W](W) writer structure"] +impl crate::Writable for TASKS_RELEASE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets TASKS_RELEASE to value 0"] +impl crate::Resettable for TASKS_RELEASE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/spis0_ns/txd.rs b/pacs/nrf9120-pac/src/spis0_ns/txd.rs new file mode 100644 index 00000000..ac01530f --- /dev/null +++ b/pacs/nrf9120-pac/src/spis0_ns/txd.rs @@ -0,0 +1,28 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct TXD { + #[doc = "0x00 - TXD data pointer"] + pub ptr: PTR, + #[doc = "0x04 - Maximum number of bytes in transmit buffer"] + pub maxcnt: MAXCNT, + #[doc = "0x08 - Number of bytes transmitted in last granted transaction"] + pub amount: AMOUNT, + #[doc = "0x0c - EasyDMA list type"] + pub list: LIST, +} +#[doc = "PTR (rw) register accessor: an alias for `Reg`"] +pub type PTR = crate::Reg; +#[doc = "TXD data pointer"] +pub mod ptr; +#[doc = "MAXCNT (rw) register accessor: an alias for `Reg`"] +pub type MAXCNT = crate::Reg; +#[doc = "Maximum number of bytes in transmit buffer"] +pub mod maxcnt; +#[doc = "AMOUNT (r) register accessor: an alias for `Reg`"] +pub type AMOUNT = crate::Reg; +#[doc = "Number of bytes transmitted in last granted transaction"] +pub mod amount; +#[doc = "LIST (rw) register accessor: an alias for `Reg`"] +pub type LIST = crate::Reg; +#[doc = "EasyDMA list type"] +pub mod list; diff --git a/pacs/nrf9120-pac/src/spis0_ns/txd/amount.rs b/pacs/nrf9120-pac/src/spis0_ns/txd/amount.rs new file mode 100644 index 00000000..0d768a14 --- /dev/null +++ b/pacs/nrf9120-pac/src/spis0_ns/txd/amount.rs @@ -0,0 +1,40 @@ +#[doc = "Register `AMOUNT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `AMOUNT` reader - Number of bytes transmitted in last granted transaction"] +pub type AMOUNT_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:12 - Number of bytes transmitted in last granted transaction"] + #[inline(always)] + pub fn amount(&self) -> AMOUNT_R { + AMOUNT_R::new((self.bits & 0x1fff) as u16) + } +} +#[doc = "Number of bytes transmitted in last granted transaction\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [amount](index.html) module"] +pub struct AMOUNT_SPEC; +impl crate::RegisterSpec for AMOUNT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [amount::R](R) reader structure"] +impl crate::Readable for AMOUNT_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets AMOUNT to value 0"] +impl crate::Resettable for AMOUNT_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/spis0_ns/txd/list.rs b/pacs/nrf9120-pac/src/spis0_ns/txd/list.rs new file mode 100644 index 00000000..aa379b8c --- /dev/null +++ b/pacs/nrf9120-pac/src/spis0_ns/txd/list.rs @@ -0,0 +1,128 @@ +#[doc = "Register `LIST` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `LIST` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `LIST` reader - List type"] +pub type LIST_R = crate::FieldReader; +#[doc = "List type\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum LIST_A { + #[doc = "0: Disable EasyDMA list"] + DISABLED = 0, + #[doc = "1: Use array list"] + ARRAY_LIST = 1, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LIST_A) -> Self { + variant as _ + } +} +impl LIST_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(LIST_A::DISABLED), + 1 => Some(LIST_A::ARRAY_LIST), + _ => None, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == LIST_A::DISABLED + } + #[doc = "Checks if the value of the field is `ARRAY_LIST`"] + #[inline(always)] + pub fn is_array_list(&self) -> bool { + *self == LIST_A::ARRAY_LIST + } +} +#[doc = "Field `LIST` writer - List type"] +pub type LIST_W<'a, const O: u8> = crate::FieldWriter<'a, u32, LIST_SPEC, u8, LIST_A, 2, O>; +impl<'a, const O: u8> LIST_W<'a, O> { + #[doc = "Disable EasyDMA list"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(LIST_A::DISABLED) + } + #[doc = "Use array list"] + #[inline(always)] + pub fn array_list(self) -> &'a mut W { + self.variant(LIST_A::ARRAY_LIST) + } +} +impl R { + #[doc = "Bits 0:1 - List type"] + #[inline(always)] + pub fn list(&self) -> LIST_R { + LIST_R::new((self.bits & 3) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - List type"] + #[inline(always)] + pub fn list(&mut self) -> LIST_W<0> { + LIST_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "EasyDMA list type\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [list](index.html) module"] +pub struct LIST_SPEC; +impl crate::RegisterSpec for LIST_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [list::R](R) reader structure"] +impl crate::Readable for LIST_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [list::W](W) writer structure"] +impl crate::Writable for LIST_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets LIST to value 0"] +impl crate::Resettable for LIST_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/spis0_ns/txd/maxcnt.rs b/pacs/nrf9120-pac/src/spis0_ns/txd/maxcnt.rs new file mode 100644 index 00000000..7ae96778 --- /dev/null +++ b/pacs/nrf9120-pac/src/spis0_ns/txd/maxcnt.rs @@ -0,0 +1,80 @@ +#[doc = "Register `MAXCNT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `MAXCNT` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `MAXCNT` reader - Maximum number of bytes in transmit buffer"] +pub type MAXCNT_R = crate::FieldReader; +#[doc = "Field `MAXCNT` writer - Maximum number of bytes in transmit buffer"] +pub type MAXCNT_W<'a, const O: u8> = crate::FieldWriter<'a, u32, MAXCNT_SPEC, u16, u16, 13, O>; +impl R { + #[doc = "Bits 0:12 - Maximum number of bytes in transmit buffer"] + #[inline(always)] + pub fn maxcnt(&self) -> MAXCNT_R { + MAXCNT_R::new((self.bits & 0x1fff) as u16) + } +} +impl W { + #[doc = "Bits 0:12 - Maximum number of bytes in transmit buffer"] + #[inline(always)] + pub fn maxcnt(&mut self) -> MAXCNT_W<0> { + MAXCNT_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Maximum number of bytes in transmit buffer\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [maxcnt](index.html) module"] +pub struct MAXCNT_SPEC; +impl crate::RegisterSpec for MAXCNT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [maxcnt::R](R) reader structure"] +impl crate::Readable for MAXCNT_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [maxcnt::W](W) writer structure"] +impl crate::Writable for MAXCNT_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets MAXCNT to value 0"] +impl crate::Resettable for MAXCNT_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/spis0_ns/txd/ptr.rs b/pacs/nrf9120-pac/src/spis0_ns/txd/ptr.rs new file mode 100644 index 00000000..f47761dc --- /dev/null +++ b/pacs/nrf9120-pac/src/spis0_ns/txd/ptr.rs @@ -0,0 +1,80 @@ +#[doc = "Register `PTR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PTR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PTR` reader - TXD data pointer"] +pub type PTR_R = crate::FieldReader; +#[doc = "Field `PTR` writer - TXD data pointer"] +pub type PTR_W<'a, const O: u8> = crate::FieldWriter<'a, u32, PTR_SPEC, u32, u32, 32, O>; +impl R { + #[doc = "Bits 0:31 - TXD data pointer"] + #[inline(always)] + pub fn ptr(&self) -> PTR_R { + PTR_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - TXD data pointer"] + #[inline(always)] + pub fn ptr(&mut self) -> PTR_W<0> { + PTR_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "TXD data pointer\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ptr](index.html) module"] +pub struct PTR_SPEC; +impl crate::RegisterSpec for PTR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ptr::R](R) reader structure"] +impl crate::Readable for PTR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ptr::W](W) writer structure"] +impl crate::Writable for PTR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PTR to value 0"] +impl crate::Resettable for PTR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/spu_s.rs b/pacs/nrf9120-pac/src/spu_s.rs new file mode 100644 index 00000000..fcd5818d --- /dev/null +++ b/pacs/nrf9120-pac/src/spu_s.rs @@ -0,0 +1,132 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + _reserved0: [u8; 0x0100], + #[doc = "0x100 - A security violation has been detected for the RAM memory space"] + pub events_ramaccerr: EVENTS_RAMACCERR, + #[doc = "0x104 - A security violation has been detected for the flash memory space"] + pub events_flashaccerr: EVENTS_FLASHACCERR, + #[doc = "0x108 - A security violation has been detected on one or several peripherals"] + pub events_periphaccerr: EVENTS_PERIPHACCERR, + _reserved3: [u8; 0x74], + #[doc = "0x180 - Publish configuration for event RAMACCERR"] + pub publish_ramaccerr: PUBLISH_RAMACCERR, + #[doc = "0x184 - Publish configuration for event FLASHACCERR"] + pub publish_flashaccerr: PUBLISH_FLASHACCERR, + #[doc = "0x188 - Publish configuration for event PERIPHACCERR"] + pub publish_periphaccerr: PUBLISH_PERIPHACCERR, + _reserved6: [u8; 0x0174], + #[doc = "0x300 - Enable or disable interrupt"] + pub inten: INTEN, + #[doc = "0x304 - Enable interrupt"] + pub intenset: INTENSET, + #[doc = "0x308 - Disable interrupt"] + pub intenclr: INTENCLR, + _reserved9: [u8; 0xf4], + #[doc = "0x400 - Show implemented features for the current device"] + pub cap: CAP, + _reserved10: [u8; 0x3c], + #[doc = "0x440 - Unspecified"] + pub extdomain: [EXTDOMAIN; 1], + _reserved11: [u8; 0x3c], + #[doc = "0x480..0x488 - Unspecified"] + pub dppi: [DPPI; 1], + _reserved12: [u8; 0x38], + #[doc = "0x4c0..0x4c8 - Unspecified"] + pub gpioport: [GPIOPORT; 1], + _reserved13: [u8; 0x38], + #[doc = "0x500..0x510 - Unspecified"] + pub flashnsc: [FLASHNSC; 2], + _reserved14: [u8; 0x30], + #[doc = "0x540..0x550 - Unspecified"] + pub ramnsc: [RAMNSC; 2], + _reserved15: [u8; 0xb0], + #[doc = "0x600..0x680 - Unspecified"] + pub flashregion: [FLASHREGION; 32], + _reserved16: [u8; 0x80], + #[doc = "0x700..0x780 - Unspecified"] + pub ramregion: [RAMREGION; 32], + _reserved17: [u8; 0x80], + #[doc = "0x800..0x90c - Unspecified"] + pub periphid: [PERIPHID; 67], +} +#[doc = "EVENTS_RAMACCERR (rw) register accessor: an alias for `Reg`"] +pub type EVENTS_RAMACCERR = crate::Reg; +#[doc = "A security violation has been detected for the RAM memory space"] +pub mod events_ramaccerr; +#[doc = "EVENTS_FLASHACCERR (rw) register accessor: an alias for `Reg`"] +pub type EVENTS_FLASHACCERR = crate::Reg; +#[doc = "A security violation has been detected for the flash memory space"] +pub mod events_flashaccerr; +#[doc = "EVENTS_PERIPHACCERR (rw) register accessor: an alias for `Reg`"] +pub type EVENTS_PERIPHACCERR = crate::Reg; +#[doc = "A security violation has been detected on one or several peripherals"] +pub mod events_periphaccerr; +#[doc = "PUBLISH_RAMACCERR (rw) register accessor: an alias for `Reg`"] +pub type PUBLISH_RAMACCERR = crate::Reg; +#[doc = "Publish configuration for event RAMACCERR"] +pub mod publish_ramaccerr; +#[doc = "PUBLISH_FLASHACCERR (rw) register accessor: an alias for `Reg`"] +pub type PUBLISH_FLASHACCERR = crate::Reg; +#[doc = "Publish configuration for event FLASHACCERR"] +pub mod publish_flashaccerr; +#[doc = "PUBLISH_PERIPHACCERR (rw) register accessor: an alias for `Reg`"] +pub type PUBLISH_PERIPHACCERR = crate::Reg; +#[doc = "Publish configuration for event PERIPHACCERR"] +pub mod publish_periphaccerr; +#[doc = "INTEN (rw) register accessor: an alias for `Reg`"] +pub type INTEN = crate::Reg; +#[doc = "Enable or disable interrupt"] +pub mod inten; +#[doc = "INTENSET (rw) register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "Enable interrupt"] +pub mod intenset; +#[doc = "INTENCLR (rw) register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "Disable interrupt"] +pub mod intenclr; +#[doc = "CAP (r) register accessor: an alias for `Reg`"] +pub type CAP = crate::Reg; +#[doc = "Show implemented features for the current device"] +pub mod cap; +#[doc = "Unspecified"] +pub use extdomain::EXTDOMAIN; +#[doc = r"Cluster"] +#[doc = "Unspecified"] +pub mod extdomain; +#[doc = "Unspecified"] +pub use dppi::DPPI; +#[doc = r"Cluster"] +#[doc = "Unspecified"] +pub mod dppi; +#[doc = "Unspecified"] +pub use gpioport::GPIOPORT; +#[doc = r"Cluster"] +#[doc = "Unspecified"] +pub mod gpioport; +#[doc = "Unspecified"] +pub use flashnsc::FLASHNSC; +#[doc = r"Cluster"] +#[doc = "Unspecified"] +pub mod flashnsc; +#[doc = "Unspecified"] +pub use ramnsc::RAMNSC; +#[doc = r"Cluster"] +#[doc = "Unspecified"] +pub mod ramnsc; +#[doc = "Unspecified"] +pub use flashregion::FLASHREGION; +#[doc = r"Cluster"] +#[doc = "Unspecified"] +pub mod flashregion; +#[doc = "Unspecified"] +pub use ramregion::RAMREGION; +#[doc = r"Cluster"] +#[doc = "Unspecified"] +pub mod ramregion; +#[doc = "Unspecified"] +pub use periphid::PERIPHID; +#[doc = r"Cluster"] +#[doc = "Unspecified"] +pub mod periphid; diff --git a/pacs/nrf9120-pac/src/spu_s/cap.rs b/pacs/nrf9120-pac/src/spu_s/cap.rs new file mode 100644 index 00000000..b046c242 --- /dev/null +++ b/pacs/nrf9120-pac/src/spu_s/cap.rs @@ -0,0 +1,74 @@ +#[doc = "Register `CAP` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `TZM` reader - Show ARM TrustZone status"] +pub type TZM_R = crate::BitReader; +#[doc = "Show ARM TrustZone status\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum TZM_A { + #[doc = "0: ARM TrustZone support not available"] + NOT_AVAILABLE = 0, + #[doc = "1: ARM TrustZone support is available"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TZM_A) -> Self { + variant as u8 != 0 + } +} +impl TZM_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> TZM_A { + match self.bits { + false => TZM_A::NOT_AVAILABLE, + true => TZM_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `NOT_AVAILABLE`"] + #[inline(always)] + pub fn is_not_available(&self) -> bool { + *self == TZM_A::NOT_AVAILABLE + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == TZM_A::ENABLED + } +} +impl R { + #[doc = "Bit 0 - Show ARM TrustZone status"] + #[inline(always)] + pub fn tzm(&self) -> TZM_R { + TZM_R::new((self.bits & 1) != 0) + } +} +#[doc = "Show implemented features for the current device\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cap](index.html) module"] +pub struct CAP_SPEC; +impl crate::RegisterSpec for CAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cap::R](R) reader structure"] +impl crate::Readable for CAP_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets CAP to value 0x01"] +impl crate::Resettable for CAP_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x01 + } +} diff --git a/pacs/nrf9120-pac/src/spu_s/dppi.rs b/pacs/nrf9120-pac/src/spu_s/dppi.rs new file mode 100644 index 00000000..020c2095 --- /dev/null +++ b/pacs/nrf9120-pac/src/spu_s/dppi.rs @@ -0,0 +1,16 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct DPPI { + #[doc = "0x00 - Description cluster: Select between secure and non-secure attribute for the DPPI channels."] + pub perm: PERM, + #[doc = "0x04 - Description cluster: Prevent further modification of the corresponding PERM register"] + pub lock: LOCK, +} +#[doc = "PERM (rw) register accessor: an alias for `Reg`"] +pub type PERM = crate::Reg; +#[doc = "Description cluster: Select between secure and non-secure attribute for the DPPI channels."] +pub mod perm; +#[doc = "LOCK (rw) register accessor: an alias for `Reg`"] +pub type LOCK = crate::Reg; +#[doc = "Description cluster: Prevent further modification of the corresponding PERM register"] +pub mod lock; diff --git a/pacs/nrf9120-pac/src/spu_s/dppi/lock.rs b/pacs/nrf9120-pac/src/spu_s/dppi/lock.rs new file mode 100644 index 00000000..92fcf27e --- /dev/null +++ b/pacs/nrf9120-pac/src/spu_s/dppi/lock.rs @@ -0,0 +1,126 @@ +#[doc = "Register `LOCK` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `LOCK` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `LOCK` reader - "] +pub type LOCK_R = crate::BitReader; +#[doc = "\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum LOCK_A { + #[doc = "1: DPPI\\[n\\].PERM register can't be changed until next reset"] + LOCKED = 1, + #[doc = "0: DPPI\\[n\\].PERM register content can be changed"] + UNLOCKED = 0, +} +impl From for bool { + #[inline(always)] + fn from(variant: LOCK_A) -> Self { + variant as u8 != 0 + } +} +impl LOCK_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> LOCK_A { + match self.bits { + true => LOCK_A::LOCKED, + false => LOCK_A::UNLOCKED, + } + } + #[doc = "Checks if the value of the field is `LOCKED`"] + #[inline(always)] + pub fn is_locked(&self) -> bool { + *self == LOCK_A::LOCKED + } + #[doc = "Checks if the value of the field is `UNLOCKED`"] + #[inline(always)] + pub fn is_unlocked(&self) -> bool { + *self == LOCK_A::UNLOCKED + } +} +#[doc = "Field `LOCK` writer - "] +pub type LOCK_W<'a, const O: u8> = crate::BitWriter<'a, u32, LOCK_SPEC, LOCK_A, O>; +impl<'a, const O: u8> LOCK_W<'a, O> { + #[doc = "DPPI\\[n\\].PERM register can't be changed until next reset"] + #[inline(always)] + pub fn locked(self) -> &'a mut W { + self.variant(LOCK_A::LOCKED) + } + #[doc = "DPPI\\[n\\].PERM register content can be changed"] + #[inline(always)] + pub fn unlocked(self) -> &'a mut W { + self.variant(LOCK_A::UNLOCKED) + } +} +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn lock(&self) -> LOCK_R { + LOCK_R::new((self.bits & 1) != 0) + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn lock(&mut self) -> LOCK_W<0> { + LOCK_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Description cluster: Prevent further modification of the corresponding PERM register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [lock](index.html) module"] +pub struct LOCK_SPEC; +impl crate::RegisterSpec for LOCK_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [lock::R](R) reader structure"] +impl crate::Readable for LOCK_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [lock::W](W) writer structure"] +impl crate::Writable for LOCK_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets LOCK to value 0"] +impl crate::Resettable for LOCK_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/spu_s/dppi/perm.rs b/pacs/nrf9120-pac/src/spu_s/dppi/perm.rs new file mode 100644 index 00000000..aadba28e --- /dev/null +++ b/pacs/nrf9120-pac/src/spu_s/dppi/perm.rs @@ -0,0 +1,1026 @@ +#[doc = "Register `PERM` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PERM` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CHANNEL0` reader - Select secure attribute."] +pub type CHANNEL0_R = crate::BitReader; +#[doc = "Select secure attribute.\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CHANNEL0_A { + #[doc = "1: Channel0 has its secure attribute set"] + SECURE = 1, + #[doc = "0: Channel0 has its non-secure attribute set"] + NON_SECURE = 0, +} +impl From for bool { + #[inline(always)] + fn from(variant: CHANNEL0_A) -> Self { + variant as u8 != 0 + } +} +impl CHANNEL0_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CHANNEL0_A { + match self.bits { + true => CHANNEL0_A::SECURE, + false => CHANNEL0_A::NON_SECURE, + } + } + #[doc = "Checks if the value of the field is `SECURE`"] + #[inline(always)] + pub fn is_secure(&self) -> bool { + *self == CHANNEL0_A::SECURE + } + #[doc = "Checks if the value of the field is `NON_SECURE`"] + #[inline(always)] + pub fn is_non_secure(&self) -> bool { + *self == CHANNEL0_A::NON_SECURE + } +} +#[doc = "Field `CHANNEL0` writer - Select secure attribute."] +pub type CHANNEL0_W<'a, const O: u8> = crate::BitWriter<'a, u32, PERM_SPEC, CHANNEL0_A, O>; +impl<'a, const O: u8> CHANNEL0_W<'a, O> { + #[doc = "Channel0 has its secure attribute set"] + #[inline(always)] + pub fn secure(self) -> &'a mut W { + self.variant(CHANNEL0_A::SECURE) + } + #[doc = "Channel0 has its non-secure attribute set"] + #[inline(always)] + pub fn non_secure(self) -> &'a mut W { + self.variant(CHANNEL0_A::NON_SECURE) + } +} +#[doc = "Field `CHANNEL1` reader - Select secure attribute."] +pub type CHANNEL1_R = crate::BitReader; +#[doc = "Select secure attribute.\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CHANNEL1_A { + #[doc = "1: Channel1 has its secure attribute set"] + SECURE = 1, + #[doc = "0: Channel1 has its non-secure attribute set"] + NON_SECURE = 0, +} +impl From for bool { + #[inline(always)] + fn from(variant: CHANNEL1_A) -> Self { + variant as u8 != 0 + } +} +impl CHANNEL1_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CHANNEL1_A { + match self.bits { + true => CHANNEL1_A::SECURE, + false => CHANNEL1_A::NON_SECURE, + } + } + #[doc = "Checks if the value of the field is `SECURE`"] + #[inline(always)] + pub fn is_secure(&self) -> bool { + *self == CHANNEL1_A::SECURE + } + #[doc = "Checks if the value of the field is `NON_SECURE`"] + #[inline(always)] + pub fn is_non_secure(&self) -> bool { + *self == CHANNEL1_A::NON_SECURE + } +} +#[doc = "Field `CHANNEL1` writer - Select secure attribute."] +pub type CHANNEL1_W<'a, const O: u8> = crate::BitWriter<'a, u32, PERM_SPEC, CHANNEL1_A, O>; +impl<'a, const O: u8> CHANNEL1_W<'a, O> { + #[doc = "Channel1 has its secure attribute set"] + #[inline(always)] + pub fn secure(self) -> &'a mut W { + self.variant(CHANNEL1_A::SECURE) + } + #[doc = "Channel1 has its non-secure attribute set"] + #[inline(always)] + pub fn non_secure(self) -> &'a mut W { + self.variant(CHANNEL1_A::NON_SECURE) + } +} +#[doc = "Field `CHANNEL2` reader - Select secure attribute."] +pub type CHANNEL2_R = crate::BitReader; +#[doc = "Select secure attribute.\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CHANNEL2_A { + #[doc = "1: Channel2 has its secure attribute set"] + SECURE = 1, + #[doc = "0: Channel2 has its non-secure attribute set"] + NON_SECURE = 0, +} +impl From for bool { + #[inline(always)] + fn from(variant: CHANNEL2_A) -> Self { + variant as u8 != 0 + } +} +impl CHANNEL2_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CHANNEL2_A { + match self.bits { + true => CHANNEL2_A::SECURE, + false => CHANNEL2_A::NON_SECURE, + } + } + #[doc = "Checks if the value of the field is `SECURE`"] + #[inline(always)] + pub fn is_secure(&self) -> bool { + *self == CHANNEL2_A::SECURE + } + #[doc = "Checks if the value of the field is `NON_SECURE`"] + #[inline(always)] + pub fn is_non_secure(&self) -> bool { + *self == CHANNEL2_A::NON_SECURE + } +} +#[doc = "Field `CHANNEL2` writer - Select secure attribute."] +pub type CHANNEL2_W<'a, const O: u8> = crate::BitWriter<'a, u32, PERM_SPEC, CHANNEL2_A, O>; +impl<'a, const O: u8> CHANNEL2_W<'a, O> { + #[doc = "Channel2 has its secure attribute set"] + #[inline(always)] + pub fn secure(self) -> &'a mut W { + self.variant(CHANNEL2_A::SECURE) + } + #[doc = "Channel2 has its non-secure attribute set"] + #[inline(always)] + pub fn non_secure(self) -> &'a mut W { + self.variant(CHANNEL2_A::NON_SECURE) + } +} +#[doc = "Field `CHANNEL3` reader - Select secure attribute."] +pub type CHANNEL3_R = crate::BitReader; +#[doc = "Select secure attribute.\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CHANNEL3_A { + #[doc = "1: Channel3 has its secure attribute set"] + SECURE = 1, + #[doc = "0: Channel3 has its non-secure attribute set"] + NON_SECURE = 0, +} +impl From for bool { + #[inline(always)] + fn from(variant: CHANNEL3_A) -> Self { + variant as u8 != 0 + } +} +impl CHANNEL3_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CHANNEL3_A { + match self.bits { + true => CHANNEL3_A::SECURE, + false => CHANNEL3_A::NON_SECURE, + } + } + #[doc = "Checks if the value of the field is `SECURE`"] + #[inline(always)] + pub fn is_secure(&self) -> bool { + *self == CHANNEL3_A::SECURE + } + #[doc = "Checks if the value of the field is `NON_SECURE`"] + #[inline(always)] + pub fn is_non_secure(&self) -> bool { + *self == CHANNEL3_A::NON_SECURE + } +} +#[doc = "Field `CHANNEL3` writer - Select secure attribute."] +pub type CHANNEL3_W<'a, const O: u8> = crate::BitWriter<'a, u32, PERM_SPEC, CHANNEL3_A, O>; +impl<'a, const O: u8> CHANNEL3_W<'a, O> { + #[doc = "Channel3 has its secure attribute set"] + #[inline(always)] + pub fn secure(self) -> &'a mut W { + self.variant(CHANNEL3_A::SECURE) + } + #[doc = "Channel3 has its non-secure attribute set"] + #[inline(always)] + pub fn non_secure(self) -> &'a mut W { + self.variant(CHANNEL3_A::NON_SECURE) + } +} +#[doc = "Field `CHANNEL4` reader - Select secure attribute."] +pub type CHANNEL4_R = crate::BitReader; +#[doc = "Select secure attribute.\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CHANNEL4_A { + #[doc = "1: Channel4 has its secure attribute set"] + SECURE = 1, + #[doc = "0: Channel4 has its non-secure attribute set"] + NON_SECURE = 0, +} +impl From for bool { + #[inline(always)] + fn from(variant: CHANNEL4_A) -> Self { + variant as u8 != 0 + } +} +impl CHANNEL4_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CHANNEL4_A { + match self.bits { + true => CHANNEL4_A::SECURE, + false => CHANNEL4_A::NON_SECURE, + } + } + #[doc = "Checks if the value of the field is `SECURE`"] + #[inline(always)] + pub fn is_secure(&self) -> bool { + *self == CHANNEL4_A::SECURE + } + #[doc = "Checks if the value of the field is `NON_SECURE`"] + #[inline(always)] + pub fn is_non_secure(&self) -> bool { + *self == CHANNEL4_A::NON_SECURE + } +} +#[doc = "Field `CHANNEL4` writer - Select secure attribute."] +pub type CHANNEL4_W<'a, const O: u8> = crate::BitWriter<'a, u32, PERM_SPEC, CHANNEL4_A, O>; +impl<'a, const O: u8> CHANNEL4_W<'a, O> { + #[doc = "Channel4 has its secure attribute set"] + #[inline(always)] + pub fn secure(self) -> &'a mut W { + self.variant(CHANNEL4_A::SECURE) + } + #[doc = "Channel4 has its non-secure attribute set"] + #[inline(always)] + pub fn non_secure(self) -> &'a mut W { + self.variant(CHANNEL4_A::NON_SECURE) + } +} +#[doc = "Field `CHANNEL5` reader - Select secure attribute."] +pub type CHANNEL5_R = crate::BitReader; +#[doc = "Select secure attribute.\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CHANNEL5_A { + #[doc = "1: Channel5 has its secure attribute set"] + SECURE = 1, + #[doc = "0: Channel5 has its non-secure attribute set"] + NON_SECURE = 0, +} +impl From for bool { + #[inline(always)] + fn from(variant: CHANNEL5_A) -> Self { + variant as u8 != 0 + } +} +impl CHANNEL5_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CHANNEL5_A { + match self.bits { + true => CHANNEL5_A::SECURE, + false => CHANNEL5_A::NON_SECURE, + } + } + #[doc = "Checks if the value of the field is `SECURE`"] + #[inline(always)] + pub fn is_secure(&self) -> bool { + *self == CHANNEL5_A::SECURE + } + #[doc = "Checks if the value of the field is `NON_SECURE`"] + #[inline(always)] + pub fn is_non_secure(&self) -> bool { + *self == CHANNEL5_A::NON_SECURE + } +} +#[doc = "Field `CHANNEL5` writer - Select secure attribute."] +pub type CHANNEL5_W<'a, const O: u8> = crate::BitWriter<'a, u32, PERM_SPEC, CHANNEL5_A, O>; +impl<'a, const O: u8> CHANNEL5_W<'a, O> { + #[doc = "Channel5 has its secure attribute set"] + #[inline(always)] + pub fn secure(self) -> &'a mut W { + self.variant(CHANNEL5_A::SECURE) + } + #[doc = "Channel5 has its non-secure attribute set"] + #[inline(always)] + pub fn non_secure(self) -> &'a mut W { + self.variant(CHANNEL5_A::NON_SECURE) + } +} +#[doc = "Field `CHANNEL6` reader - Select secure attribute."] +pub type CHANNEL6_R = crate::BitReader; +#[doc = "Select secure attribute.\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CHANNEL6_A { + #[doc = "1: Channel6 has its secure attribute set"] + SECURE = 1, + #[doc = "0: Channel6 has its non-secure attribute set"] + NON_SECURE = 0, +} +impl From for bool { + #[inline(always)] + fn from(variant: CHANNEL6_A) -> Self { + variant as u8 != 0 + } +} +impl CHANNEL6_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CHANNEL6_A { + match self.bits { + true => CHANNEL6_A::SECURE, + false => CHANNEL6_A::NON_SECURE, + } + } + #[doc = "Checks if the value of the field is `SECURE`"] + #[inline(always)] + pub fn is_secure(&self) -> bool { + *self == CHANNEL6_A::SECURE + } + #[doc = "Checks if the value of the field is `NON_SECURE`"] + #[inline(always)] + pub fn is_non_secure(&self) -> bool { + *self == CHANNEL6_A::NON_SECURE + } +} +#[doc = "Field `CHANNEL6` writer - Select secure attribute."] +pub type CHANNEL6_W<'a, const O: u8> = crate::BitWriter<'a, u32, PERM_SPEC, CHANNEL6_A, O>; +impl<'a, const O: u8> CHANNEL6_W<'a, O> { + #[doc = "Channel6 has its secure attribute set"] + #[inline(always)] + pub fn secure(self) -> &'a mut W { + self.variant(CHANNEL6_A::SECURE) + } + #[doc = "Channel6 has its non-secure attribute set"] + #[inline(always)] + pub fn non_secure(self) -> &'a mut W { + self.variant(CHANNEL6_A::NON_SECURE) + } +} +#[doc = "Field `CHANNEL7` reader - Select secure attribute."] +pub type CHANNEL7_R = crate::BitReader; +#[doc = "Select secure attribute.\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CHANNEL7_A { + #[doc = "1: Channel7 has its secure attribute set"] + SECURE = 1, + #[doc = "0: Channel7 has its non-secure attribute set"] + NON_SECURE = 0, +} +impl From for bool { + #[inline(always)] + fn from(variant: CHANNEL7_A) -> Self { + variant as u8 != 0 + } +} +impl CHANNEL7_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CHANNEL7_A { + match self.bits { + true => CHANNEL7_A::SECURE, + false => CHANNEL7_A::NON_SECURE, + } + } + #[doc = "Checks if the value of the field is `SECURE`"] + #[inline(always)] + pub fn is_secure(&self) -> bool { + *self == CHANNEL7_A::SECURE + } + #[doc = "Checks if the value of the field is `NON_SECURE`"] + #[inline(always)] + pub fn is_non_secure(&self) -> bool { + *self == CHANNEL7_A::NON_SECURE + } +} +#[doc = "Field `CHANNEL7` writer - Select secure attribute."] +pub type CHANNEL7_W<'a, const O: u8> = crate::BitWriter<'a, u32, PERM_SPEC, CHANNEL7_A, O>; +impl<'a, const O: u8> CHANNEL7_W<'a, O> { + #[doc = "Channel7 has its secure attribute set"] + #[inline(always)] + pub fn secure(self) -> &'a mut W { + self.variant(CHANNEL7_A::SECURE) + } + #[doc = "Channel7 has its non-secure attribute set"] + #[inline(always)] + pub fn non_secure(self) -> &'a mut W { + self.variant(CHANNEL7_A::NON_SECURE) + } +} +#[doc = "Field `CHANNEL8` reader - Select secure attribute."] +pub type CHANNEL8_R = crate::BitReader; +#[doc = "Select secure attribute.\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CHANNEL8_A { + #[doc = "1: Channel8 has its secure attribute set"] + SECURE = 1, + #[doc = "0: Channel8 has its non-secure attribute set"] + NON_SECURE = 0, +} +impl From for bool { + #[inline(always)] + fn from(variant: CHANNEL8_A) -> Self { + variant as u8 != 0 + } +} +impl CHANNEL8_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CHANNEL8_A { + match self.bits { + true => CHANNEL8_A::SECURE, + false => CHANNEL8_A::NON_SECURE, + } + } + #[doc = "Checks if the value of the field is `SECURE`"] + #[inline(always)] + pub fn is_secure(&self) -> bool { + *self == CHANNEL8_A::SECURE + } + #[doc = "Checks if the value of the field is `NON_SECURE`"] + #[inline(always)] + pub fn is_non_secure(&self) -> bool { + *self == CHANNEL8_A::NON_SECURE + } +} +#[doc = "Field `CHANNEL8` writer - Select secure attribute."] +pub type CHANNEL8_W<'a, const O: u8> = crate::BitWriter<'a, u32, PERM_SPEC, CHANNEL8_A, O>; +impl<'a, const O: u8> CHANNEL8_W<'a, O> { + #[doc = "Channel8 has its secure attribute set"] + #[inline(always)] + pub fn secure(self) -> &'a mut W { + self.variant(CHANNEL8_A::SECURE) + } + #[doc = "Channel8 has its non-secure attribute set"] + #[inline(always)] + pub fn non_secure(self) -> &'a mut W { + self.variant(CHANNEL8_A::NON_SECURE) + } +} +#[doc = "Field `CHANNEL9` reader - Select secure attribute."] +pub type CHANNEL9_R = crate::BitReader; +#[doc = "Select secure attribute.\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CHANNEL9_A { + #[doc = "1: Channel9 has its secure attribute set"] + SECURE = 1, + #[doc = "0: Channel9 has its non-secure attribute set"] + NON_SECURE = 0, +} +impl From for bool { + #[inline(always)] + fn from(variant: CHANNEL9_A) -> Self { + variant as u8 != 0 + } +} +impl CHANNEL9_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CHANNEL9_A { + match self.bits { + true => CHANNEL9_A::SECURE, + false => CHANNEL9_A::NON_SECURE, + } + } + #[doc = "Checks if the value of the field is `SECURE`"] + #[inline(always)] + pub fn is_secure(&self) -> bool { + *self == CHANNEL9_A::SECURE + } + #[doc = "Checks if the value of the field is `NON_SECURE`"] + #[inline(always)] + pub fn is_non_secure(&self) -> bool { + *self == CHANNEL9_A::NON_SECURE + } +} +#[doc = "Field `CHANNEL9` writer - Select secure attribute."] +pub type CHANNEL9_W<'a, const O: u8> = crate::BitWriter<'a, u32, PERM_SPEC, CHANNEL9_A, O>; +impl<'a, const O: u8> CHANNEL9_W<'a, O> { + #[doc = "Channel9 has its secure attribute set"] + #[inline(always)] + pub fn secure(self) -> &'a mut W { + self.variant(CHANNEL9_A::SECURE) + } + #[doc = "Channel9 has its non-secure attribute set"] + #[inline(always)] + pub fn non_secure(self) -> &'a mut W { + self.variant(CHANNEL9_A::NON_SECURE) + } +} +#[doc = "Field `CHANNEL10` reader - Select secure attribute."] +pub type CHANNEL10_R = crate::BitReader; +#[doc = "Select secure attribute.\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CHANNEL10_A { + #[doc = "1: Channel10 has its secure attribute set"] + SECURE = 1, + #[doc = "0: Channel10 has its non-secure attribute set"] + NON_SECURE = 0, +} +impl From for bool { + #[inline(always)] + fn from(variant: CHANNEL10_A) -> Self { + variant as u8 != 0 + } +} +impl CHANNEL10_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CHANNEL10_A { + match self.bits { + true => CHANNEL10_A::SECURE, + false => CHANNEL10_A::NON_SECURE, + } + } + #[doc = "Checks if the value of the field is `SECURE`"] + #[inline(always)] + pub fn is_secure(&self) -> bool { + *self == CHANNEL10_A::SECURE + } + #[doc = "Checks if the value of the field is `NON_SECURE`"] + #[inline(always)] + pub fn is_non_secure(&self) -> bool { + *self == CHANNEL10_A::NON_SECURE + } +} +#[doc = "Field `CHANNEL10` writer - Select secure attribute."] +pub type CHANNEL10_W<'a, const O: u8> = crate::BitWriter<'a, u32, PERM_SPEC, CHANNEL10_A, O>; +impl<'a, const O: u8> CHANNEL10_W<'a, O> { + #[doc = "Channel10 has its secure attribute set"] + #[inline(always)] + pub fn secure(self) -> &'a mut W { + self.variant(CHANNEL10_A::SECURE) + } + #[doc = "Channel10 has its non-secure attribute set"] + #[inline(always)] + pub fn non_secure(self) -> &'a mut W { + self.variant(CHANNEL10_A::NON_SECURE) + } +} +#[doc = "Field `CHANNEL11` reader - Select secure attribute."] +pub type CHANNEL11_R = crate::BitReader; +#[doc = "Select secure attribute.\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CHANNEL11_A { + #[doc = "1: Channel11 has its secure attribute set"] + SECURE = 1, + #[doc = "0: Channel11 has its non-secure attribute set"] + NON_SECURE = 0, +} +impl From for bool { + #[inline(always)] + fn from(variant: CHANNEL11_A) -> Self { + variant as u8 != 0 + } +} +impl CHANNEL11_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CHANNEL11_A { + match self.bits { + true => CHANNEL11_A::SECURE, + false => CHANNEL11_A::NON_SECURE, + } + } + #[doc = "Checks if the value of the field is `SECURE`"] + #[inline(always)] + pub fn is_secure(&self) -> bool { + *self == CHANNEL11_A::SECURE + } + #[doc = "Checks if the value of the field is `NON_SECURE`"] + #[inline(always)] + pub fn is_non_secure(&self) -> bool { + *self == CHANNEL11_A::NON_SECURE + } +} +#[doc = "Field `CHANNEL11` writer - Select secure attribute."] +pub type CHANNEL11_W<'a, const O: u8> = crate::BitWriter<'a, u32, PERM_SPEC, CHANNEL11_A, O>; +impl<'a, const O: u8> CHANNEL11_W<'a, O> { + #[doc = "Channel11 has its secure attribute set"] + #[inline(always)] + pub fn secure(self) -> &'a mut W { + self.variant(CHANNEL11_A::SECURE) + } + #[doc = "Channel11 has its non-secure attribute set"] + #[inline(always)] + pub fn non_secure(self) -> &'a mut W { + self.variant(CHANNEL11_A::NON_SECURE) + } +} +#[doc = "Field `CHANNEL12` reader - Select secure attribute."] +pub type CHANNEL12_R = crate::BitReader; +#[doc = "Select secure attribute.\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CHANNEL12_A { + #[doc = "1: Channel12 has its secure attribute set"] + SECURE = 1, + #[doc = "0: Channel12 has its non-secure attribute set"] + NON_SECURE = 0, +} +impl From for bool { + #[inline(always)] + fn from(variant: CHANNEL12_A) -> Self { + variant as u8 != 0 + } +} +impl CHANNEL12_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CHANNEL12_A { + match self.bits { + true => CHANNEL12_A::SECURE, + false => CHANNEL12_A::NON_SECURE, + } + } + #[doc = "Checks if the value of the field is `SECURE`"] + #[inline(always)] + pub fn is_secure(&self) -> bool { + *self == CHANNEL12_A::SECURE + } + #[doc = "Checks if the value of the field is `NON_SECURE`"] + #[inline(always)] + pub fn is_non_secure(&self) -> bool { + *self == CHANNEL12_A::NON_SECURE + } +} +#[doc = "Field `CHANNEL12` writer - Select secure attribute."] +pub type CHANNEL12_W<'a, const O: u8> = crate::BitWriter<'a, u32, PERM_SPEC, CHANNEL12_A, O>; +impl<'a, const O: u8> CHANNEL12_W<'a, O> { + #[doc = "Channel12 has its secure attribute set"] + #[inline(always)] + pub fn secure(self) -> &'a mut W { + self.variant(CHANNEL12_A::SECURE) + } + #[doc = "Channel12 has its non-secure attribute set"] + #[inline(always)] + pub fn non_secure(self) -> &'a mut W { + self.variant(CHANNEL12_A::NON_SECURE) + } +} +#[doc = "Field `CHANNEL13` reader - Select secure attribute."] +pub type CHANNEL13_R = crate::BitReader; +#[doc = "Select secure attribute.\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CHANNEL13_A { + #[doc = "1: Channel13 has its secure attribute set"] + SECURE = 1, + #[doc = "0: Channel13 has its non-secure attribute set"] + NON_SECURE = 0, +} +impl From for bool { + #[inline(always)] + fn from(variant: CHANNEL13_A) -> Self { + variant as u8 != 0 + } +} +impl CHANNEL13_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CHANNEL13_A { + match self.bits { + true => CHANNEL13_A::SECURE, + false => CHANNEL13_A::NON_SECURE, + } + } + #[doc = "Checks if the value of the field is `SECURE`"] + #[inline(always)] + pub fn is_secure(&self) -> bool { + *self == CHANNEL13_A::SECURE + } + #[doc = "Checks if the value of the field is `NON_SECURE`"] + #[inline(always)] + pub fn is_non_secure(&self) -> bool { + *self == CHANNEL13_A::NON_SECURE + } +} +#[doc = "Field `CHANNEL13` writer - Select secure attribute."] +pub type CHANNEL13_W<'a, const O: u8> = crate::BitWriter<'a, u32, PERM_SPEC, CHANNEL13_A, O>; +impl<'a, const O: u8> CHANNEL13_W<'a, O> { + #[doc = "Channel13 has its secure attribute set"] + #[inline(always)] + pub fn secure(self) -> &'a mut W { + self.variant(CHANNEL13_A::SECURE) + } + #[doc = "Channel13 has its non-secure attribute set"] + #[inline(always)] + pub fn non_secure(self) -> &'a mut W { + self.variant(CHANNEL13_A::NON_SECURE) + } +} +#[doc = "Field `CHANNEL14` reader - Select secure attribute."] +pub type CHANNEL14_R = crate::BitReader; +#[doc = "Select secure attribute.\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CHANNEL14_A { + #[doc = "1: Channel14 has its secure attribute set"] + SECURE = 1, + #[doc = "0: Channel14 has its non-secure attribute set"] + NON_SECURE = 0, +} +impl From for bool { + #[inline(always)] + fn from(variant: CHANNEL14_A) -> Self { + variant as u8 != 0 + } +} +impl CHANNEL14_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CHANNEL14_A { + match self.bits { + true => CHANNEL14_A::SECURE, + false => CHANNEL14_A::NON_SECURE, + } + } + #[doc = "Checks if the value of the field is `SECURE`"] + #[inline(always)] + pub fn is_secure(&self) -> bool { + *self == CHANNEL14_A::SECURE + } + #[doc = "Checks if the value of the field is `NON_SECURE`"] + #[inline(always)] + pub fn is_non_secure(&self) -> bool { + *self == CHANNEL14_A::NON_SECURE + } +} +#[doc = "Field `CHANNEL14` writer - Select secure attribute."] +pub type CHANNEL14_W<'a, const O: u8> = crate::BitWriter<'a, u32, PERM_SPEC, CHANNEL14_A, O>; +impl<'a, const O: u8> CHANNEL14_W<'a, O> { + #[doc = "Channel14 has its secure attribute set"] + #[inline(always)] + pub fn secure(self) -> &'a mut W { + self.variant(CHANNEL14_A::SECURE) + } + #[doc = "Channel14 has its non-secure attribute set"] + #[inline(always)] + pub fn non_secure(self) -> &'a mut W { + self.variant(CHANNEL14_A::NON_SECURE) + } +} +#[doc = "Field `CHANNEL15` reader - Select secure attribute."] +pub type CHANNEL15_R = crate::BitReader; +#[doc = "Select secure attribute.\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CHANNEL15_A { + #[doc = "1: Channel15 has its secure attribute set"] + SECURE = 1, + #[doc = "0: Channel15 has its non-secure attribute set"] + NON_SECURE = 0, +} +impl From for bool { + #[inline(always)] + fn from(variant: CHANNEL15_A) -> Self { + variant as u8 != 0 + } +} +impl CHANNEL15_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CHANNEL15_A { + match self.bits { + true => CHANNEL15_A::SECURE, + false => CHANNEL15_A::NON_SECURE, + } + } + #[doc = "Checks if the value of the field is `SECURE`"] + #[inline(always)] + pub fn is_secure(&self) -> bool { + *self == CHANNEL15_A::SECURE + } + #[doc = "Checks if the value of the field is `NON_SECURE`"] + #[inline(always)] + pub fn is_non_secure(&self) -> bool { + *self == CHANNEL15_A::NON_SECURE + } +} +#[doc = "Field `CHANNEL15` writer - Select secure attribute."] +pub type CHANNEL15_W<'a, const O: u8> = crate::BitWriter<'a, u32, PERM_SPEC, CHANNEL15_A, O>; +impl<'a, const O: u8> CHANNEL15_W<'a, O> { + #[doc = "Channel15 has its secure attribute set"] + #[inline(always)] + pub fn secure(self) -> &'a mut W { + self.variant(CHANNEL15_A::SECURE) + } + #[doc = "Channel15 has its non-secure attribute set"] + #[inline(always)] + pub fn non_secure(self) -> &'a mut W { + self.variant(CHANNEL15_A::NON_SECURE) + } +} +impl R { + #[doc = "Bit 0 - Select secure attribute."] + #[inline(always)] + pub fn channel0(&self) -> CHANNEL0_R { + CHANNEL0_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Select secure attribute."] + #[inline(always)] + pub fn channel1(&self) -> CHANNEL1_R { + CHANNEL1_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Select secure attribute."] + #[inline(always)] + pub fn channel2(&self) -> CHANNEL2_R { + CHANNEL2_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Select secure attribute."] + #[inline(always)] + pub fn channel3(&self) -> CHANNEL3_R { + CHANNEL3_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Select secure attribute."] + #[inline(always)] + pub fn channel4(&self) -> CHANNEL4_R { + CHANNEL4_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Select secure attribute."] + #[inline(always)] + pub fn channel5(&self) -> CHANNEL5_R { + CHANNEL5_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Select secure attribute."] + #[inline(always)] + pub fn channel6(&self) -> CHANNEL6_R { + CHANNEL6_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Select secure attribute."] + #[inline(always)] + pub fn channel7(&self) -> CHANNEL7_R { + CHANNEL7_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Select secure attribute."] + #[inline(always)] + pub fn channel8(&self) -> CHANNEL8_R { + CHANNEL8_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Select secure attribute."] + #[inline(always)] + pub fn channel9(&self) -> CHANNEL9_R { + CHANNEL9_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Select secure attribute."] + #[inline(always)] + pub fn channel10(&self) -> CHANNEL10_R { + CHANNEL10_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Select secure attribute."] + #[inline(always)] + pub fn channel11(&self) -> CHANNEL11_R { + CHANNEL11_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Select secure attribute."] + #[inline(always)] + pub fn channel12(&self) -> CHANNEL12_R { + CHANNEL12_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Select secure attribute."] + #[inline(always)] + pub fn channel13(&self) -> CHANNEL13_R { + CHANNEL13_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Select secure attribute."] + #[inline(always)] + pub fn channel14(&self) -> CHANNEL14_R { + CHANNEL14_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Select secure attribute."] + #[inline(always)] + pub fn channel15(&self) -> CHANNEL15_R { + CHANNEL15_R::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Select secure attribute."] + #[inline(always)] + pub fn channel0(&mut self) -> CHANNEL0_W<0> { + CHANNEL0_W::new(self) + } + #[doc = "Bit 1 - Select secure attribute."] + #[inline(always)] + pub fn channel1(&mut self) -> CHANNEL1_W<1> { + CHANNEL1_W::new(self) + } + #[doc = "Bit 2 - Select secure attribute."] + #[inline(always)] + pub fn channel2(&mut self) -> CHANNEL2_W<2> { + CHANNEL2_W::new(self) + } + #[doc = "Bit 3 - Select secure attribute."] + #[inline(always)] + pub fn channel3(&mut self) -> CHANNEL3_W<3> { + CHANNEL3_W::new(self) + } + #[doc = "Bit 4 - Select secure attribute."] + #[inline(always)] + pub fn channel4(&mut self) -> CHANNEL4_W<4> { + CHANNEL4_W::new(self) + } + #[doc = "Bit 5 - Select secure attribute."] + #[inline(always)] + pub fn channel5(&mut self) -> CHANNEL5_W<5> { + CHANNEL5_W::new(self) + } + #[doc = "Bit 6 - Select secure attribute."] + #[inline(always)] + pub fn channel6(&mut self) -> CHANNEL6_W<6> { + CHANNEL6_W::new(self) + } + #[doc = "Bit 7 - Select secure attribute."] + #[inline(always)] + pub fn channel7(&mut self) -> CHANNEL7_W<7> { + CHANNEL7_W::new(self) + } + #[doc = "Bit 8 - Select secure attribute."] + #[inline(always)] + pub fn channel8(&mut self) -> CHANNEL8_W<8> { + CHANNEL8_W::new(self) + } + #[doc = "Bit 9 - Select secure attribute."] + #[inline(always)] + pub fn channel9(&mut self) -> CHANNEL9_W<9> { + CHANNEL9_W::new(self) + } + #[doc = "Bit 10 - Select secure attribute."] + #[inline(always)] + pub fn channel10(&mut self) -> CHANNEL10_W<10> { + CHANNEL10_W::new(self) + } + #[doc = "Bit 11 - Select secure attribute."] + #[inline(always)] + pub fn channel11(&mut self) -> CHANNEL11_W<11> { + CHANNEL11_W::new(self) + } + #[doc = "Bit 12 - Select secure attribute."] + #[inline(always)] + pub fn channel12(&mut self) -> CHANNEL12_W<12> { + CHANNEL12_W::new(self) + } + #[doc = "Bit 13 - Select secure attribute."] + #[inline(always)] + pub fn channel13(&mut self) -> CHANNEL13_W<13> { + CHANNEL13_W::new(self) + } + #[doc = "Bit 14 - Select secure attribute."] + #[inline(always)] + pub fn channel14(&mut self) -> CHANNEL14_W<14> { + CHANNEL14_W::new(self) + } + #[doc = "Bit 15 - Select secure attribute."] + #[inline(always)] + pub fn channel15(&mut self) -> CHANNEL15_W<15> { + CHANNEL15_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Description cluster: Select between secure and non-secure attribute for the DPPI channels.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [perm](index.html) module"] +pub struct PERM_SPEC; +impl crate::RegisterSpec for PERM_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [perm::R](R) reader structure"] +impl crate::Readable for PERM_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [perm::W](W) writer structure"] +impl crate::Writable for PERM_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PERM to value 0xffff"] +impl crate::Resettable for PERM_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0xffff + } +} diff --git a/pacs/nrf9120-pac/src/spu_s/events_flashaccerr.rs b/pacs/nrf9120-pac/src/spu_s/events_flashaccerr.rs new file mode 100644 index 00000000..f21051f4 --- /dev/null +++ b/pacs/nrf9120-pac/src/spu_s/events_flashaccerr.rs @@ -0,0 +1,127 @@ +#[doc = "Register `EVENTS_FLASHACCERR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVENTS_FLASHACCERR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `EVENTS_FLASHACCERR` reader - A security violation has been detected for the flash memory space"] +pub type EVENTS_FLASHACCERR_R = crate::BitReader; +#[doc = "A security violation has been detected for the flash memory space\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum EVENTS_FLASHACCERR_A { + #[doc = "0: Event not generated"] + NOT_GENERATED = 0, + #[doc = "1: Event generated"] + GENERATED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: EVENTS_FLASHACCERR_A) -> Self { + variant as u8 != 0 + } +} +impl EVENTS_FLASHACCERR_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EVENTS_FLASHACCERR_A { + match self.bits { + false => EVENTS_FLASHACCERR_A::NOT_GENERATED, + true => EVENTS_FLASHACCERR_A::GENERATED, + } + } + #[doc = "Checks if the value of the field is `NOT_GENERATED`"] + #[inline(always)] + pub fn is_not_generated(&self) -> bool { + *self == EVENTS_FLASHACCERR_A::NOT_GENERATED + } + #[doc = "Checks if the value of the field is `GENERATED`"] + #[inline(always)] + pub fn is_generated(&self) -> bool { + *self == EVENTS_FLASHACCERR_A::GENERATED + } +} +#[doc = "Field `EVENTS_FLASHACCERR` writer - A security violation has been detected for the flash memory space"] +pub type EVENTS_FLASHACCERR_W<'a, const O: u8> = + crate::BitWriter<'a, u32, EVENTS_FLASHACCERR_SPEC, EVENTS_FLASHACCERR_A, O>; +impl<'a, const O: u8> EVENTS_FLASHACCERR_W<'a, O> { + #[doc = "Event not generated"] + #[inline(always)] + pub fn not_generated(self) -> &'a mut W { + self.variant(EVENTS_FLASHACCERR_A::NOT_GENERATED) + } + #[doc = "Event generated"] + #[inline(always)] + pub fn generated(self) -> &'a mut W { + self.variant(EVENTS_FLASHACCERR_A::GENERATED) + } +} +impl R { + #[doc = "Bit 0 - A security violation has been detected for the flash memory space"] + #[inline(always)] + pub fn events_flashaccerr(&self) -> EVENTS_FLASHACCERR_R { + EVENTS_FLASHACCERR_R::new((self.bits & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - A security violation has been detected for the flash memory space"] + #[inline(always)] + pub fn events_flashaccerr(&mut self) -> EVENTS_FLASHACCERR_W<0> { + EVENTS_FLASHACCERR_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "A security violation has been detected for the flash memory space\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [events_flashaccerr](index.html) module"] +pub struct EVENTS_FLASHACCERR_SPEC; +impl crate::RegisterSpec for EVENTS_FLASHACCERR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [events_flashaccerr::R](R) reader structure"] +impl crate::Readable for EVENTS_FLASHACCERR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [events_flashaccerr::W](W) writer structure"] +impl crate::Writable for EVENTS_FLASHACCERR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EVENTS_FLASHACCERR to value 0"] +impl crate::Resettable for EVENTS_FLASHACCERR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/spu_s/events_periphaccerr.rs b/pacs/nrf9120-pac/src/spu_s/events_periphaccerr.rs new file mode 100644 index 00000000..7cf06b4b --- /dev/null +++ b/pacs/nrf9120-pac/src/spu_s/events_periphaccerr.rs @@ -0,0 +1,127 @@ +#[doc = "Register `EVENTS_PERIPHACCERR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVENTS_PERIPHACCERR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `EVENTS_PERIPHACCERR` reader - A security violation has been detected on one or several peripherals"] +pub type EVENTS_PERIPHACCERR_R = crate::BitReader; +#[doc = "A security violation has been detected on one or several peripherals\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum EVENTS_PERIPHACCERR_A { + #[doc = "0: Event not generated"] + NOT_GENERATED = 0, + #[doc = "1: Event generated"] + GENERATED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: EVENTS_PERIPHACCERR_A) -> Self { + variant as u8 != 0 + } +} +impl EVENTS_PERIPHACCERR_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EVENTS_PERIPHACCERR_A { + match self.bits { + false => EVENTS_PERIPHACCERR_A::NOT_GENERATED, + true => EVENTS_PERIPHACCERR_A::GENERATED, + } + } + #[doc = "Checks if the value of the field is `NOT_GENERATED`"] + #[inline(always)] + pub fn is_not_generated(&self) -> bool { + *self == EVENTS_PERIPHACCERR_A::NOT_GENERATED + } + #[doc = "Checks if the value of the field is `GENERATED`"] + #[inline(always)] + pub fn is_generated(&self) -> bool { + *self == EVENTS_PERIPHACCERR_A::GENERATED + } +} +#[doc = "Field `EVENTS_PERIPHACCERR` writer - A security violation has been detected on one or several peripherals"] +pub type EVENTS_PERIPHACCERR_W<'a, const O: u8> = + crate::BitWriter<'a, u32, EVENTS_PERIPHACCERR_SPEC, EVENTS_PERIPHACCERR_A, O>; +impl<'a, const O: u8> EVENTS_PERIPHACCERR_W<'a, O> { + #[doc = "Event not generated"] + #[inline(always)] + pub fn not_generated(self) -> &'a mut W { + self.variant(EVENTS_PERIPHACCERR_A::NOT_GENERATED) + } + #[doc = "Event generated"] + #[inline(always)] + pub fn generated(self) -> &'a mut W { + self.variant(EVENTS_PERIPHACCERR_A::GENERATED) + } +} +impl R { + #[doc = "Bit 0 - A security violation has been detected on one or several peripherals"] + #[inline(always)] + pub fn events_periphaccerr(&self) -> EVENTS_PERIPHACCERR_R { + EVENTS_PERIPHACCERR_R::new((self.bits & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - A security violation has been detected on one or several peripherals"] + #[inline(always)] + pub fn events_periphaccerr(&mut self) -> EVENTS_PERIPHACCERR_W<0> { + EVENTS_PERIPHACCERR_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "A security violation has been detected on one or several peripherals\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [events_periphaccerr](index.html) module"] +pub struct EVENTS_PERIPHACCERR_SPEC; +impl crate::RegisterSpec for EVENTS_PERIPHACCERR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [events_periphaccerr::R](R) reader structure"] +impl crate::Readable for EVENTS_PERIPHACCERR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [events_periphaccerr::W](W) writer structure"] +impl crate::Writable for EVENTS_PERIPHACCERR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EVENTS_PERIPHACCERR to value 0"] +impl crate::Resettable for EVENTS_PERIPHACCERR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/spu_s/events_ramaccerr.rs b/pacs/nrf9120-pac/src/spu_s/events_ramaccerr.rs new file mode 100644 index 00000000..bbff6b25 --- /dev/null +++ b/pacs/nrf9120-pac/src/spu_s/events_ramaccerr.rs @@ -0,0 +1,127 @@ +#[doc = "Register `EVENTS_RAMACCERR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVENTS_RAMACCERR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `EVENTS_RAMACCERR` reader - A security violation has been detected for the RAM memory space"] +pub type EVENTS_RAMACCERR_R = crate::BitReader; +#[doc = "A security violation has been detected for the RAM memory space\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum EVENTS_RAMACCERR_A { + #[doc = "0: Event not generated"] + NOT_GENERATED = 0, + #[doc = "1: Event generated"] + GENERATED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: EVENTS_RAMACCERR_A) -> Self { + variant as u8 != 0 + } +} +impl EVENTS_RAMACCERR_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EVENTS_RAMACCERR_A { + match self.bits { + false => EVENTS_RAMACCERR_A::NOT_GENERATED, + true => EVENTS_RAMACCERR_A::GENERATED, + } + } + #[doc = "Checks if the value of the field is `NOT_GENERATED`"] + #[inline(always)] + pub fn is_not_generated(&self) -> bool { + *self == EVENTS_RAMACCERR_A::NOT_GENERATED + } + #[doc = "Checks if the value of the field is `GENERATED`"] + #[inline(always)] + pub fn is_generated(&self) -> bool { + *self == EVENTS_RAMACCERR_A::GENERATED + } +} +#[doc = "Field `EVENTS_RAMACCERR` writer - A security violation has been detected for the RAM memory space"] +pub type EVENTS_RAMACCERR_W<'a, const O: u8> = + crate::BitWriter<'a, u32, EVENTS_RAMACCERR_SPEC, EVENTS_RAMACCERR_A, O>; +impl<'a, const O: u8> EVENTS_RAMACCERR_W<'a, O> { + #[doc = "Event not generated"] + #[inline(always)] + pub fn not_generated(self) -> &'a mut W { + self.variant(EVENTS_RAMACCERR_A::NOT_GENERATED) + } + #[doc = "Event generated"] + #[inline(always)] + pub fn generated(self) -> &'a mut W { + self.variant(EVENTS_RAMACCERR_A::GENERATED) + } +} +impl R { + #[doc = "Bit 0 - A security violation has been detected for the RAM memory space"] + #[inline(always)] + pub fn events_ramaccerr(&self) -> EVENTS_RAMACCERR_R { + EVENTS_RAMACCERR_R::new((self.bits & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - A security violation has been detected for the RAM memory space"] + #[inline(always)] + pub fn events_ramaccerr(&mut self) -> EVENTS_RAMACCERR_W<0> { + EVENTS_RAMACCERR_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "A security violation has been detected for the RAM memory space\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [events_ramaccerr](index.html) module"] +pub struct EVENTS_RAMACCERR_SPEC; +impl crate::RegisterSpec for EVENTS_RAMACCERR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [events_ramaccerr::R](R) reader structure"] +impl crate::Readable for EVENTS_RAMACCERR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [events_ramaccerr::W](W) writer structure"] +impl crate::Writable for EVENTS_RAMACCERR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EVENTS_RAMACCERR to value 0"] +impl crate::Resettable for EVENTS_RAMACCERR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/spu_s/extdomain.rs b/pacs/nrf9120-pac/src/spu_s/extdomain.rs new file mode 100644 index 00000000..d0463003 --- /dev/null +++ b/pacs/nrf9120-pac/src/spu_s/extdomain.rs @@ -0,0 +1,10 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct EXTDOMAIN { + #[doc = "0x00 - Description cluster: Access for bus access generated from the external domain n List capabilities of the external domain n"] + pub perm: PERM, +} +#[doc = "PERM (rw) register accessor: an alias for `Reg`"] +pub type PERM = crate::Reg; +#[doc = "Description cluster: Access for bus access generated from the external domain n List capabilities of the external domain n"] +pub mod perm; diff --git a/pacs/nrf9120-pac/src/spu_s/extdomain/perm.rs b/pacs/nrf9120-pac/src/spu_s/extdomain/perm.rs new file mode 100644 index 00000000..2fa46d99 --- /dev/null +++ b/pacs/nrf9120-pac/src/spu_s/extdomain/perm.rs @@ -0,0 +1,237 @@ +#[doc = "Register `PERM` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PERM` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SECUREMAPPING` reader - Define configuration capabilities for TrustZone Cortex-M secure attribute"] +pub type SECUREMAPPING_R = crate::FieldReader; +#[doc = "Define configuration capabilities for TrustZone Cortex-M secure attribute\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SECUREMAPPING_A { + #[doc = "0: The bus access from this external domain always have the non-secure attribute set"] + NON_SECURE = 0, + #[doc = "1: The bus access from this external domain always have the secure attribute set"] + SECURE = 1, + #[doc = "2: Non-secure or secure attribute for bus access from this domain is defined by the EXTDOMAIN\\[n\\].PERM register"] + USER_SELECTABLE = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SECUREMAPPING_A) -> Self { + variant as _ + } +} +impl SECUREMAPPING_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SECUREMAPPING_A::NON_SECURE), + 1 => Some(SECUREMAPPING_A::SECURE), + 2 => Some(SECUREMAPPING_A::USER_SELECTABLE), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NON_SECURE`"] + #[inline(always)] + pub fn is_non_secure(&self) -> bool { + *self == SECUREMAPPING_A::NON_SECURE + } + #[doc = "Checks if the value of the field is `SECURE`"] + #[inline(always)] + pub fn is_secure(&self) -> bool { + *self == SECUREMAPPING_A::SECURE + } + #[doc = "Checks if the value of the field is `USER_SELECTABLE`"] + #[inline(always)] + pub fn is_user_selectable(&self) -> bool { + *self == SECUREMAPPING_A::USER_SELECTABLE + } +} +#[doc = "Field `SECATTR` reader - Peripheral security mapping"] +pub type SECATTR_R = crate::BitReader; +#[doc = "Peripheral security mapping\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum SECATTR_A { + #[doc = "0: Bus accesses from this domain have the non-secure attribute set"] + NON_SECURE = 0, + #[doc = "1: Bus accesses from this domain have secure attribute set"] + SECURE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: SECATTR_A) -> Self { + variant as u8 != 0 + } +} +impl SECATTR_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> SECATTR_A { + match self.bits { + false => SECATTR_A::NON_SECURE, + true => SECATTR_A::SECURE, + } + } + #[doc = "Checks if the value of the field is `NON_SECURE`"] + #[inline(always)] + pub fn is_non_secure(&self) -> bool { + *self == SECATTR_A::NON_SECURE + } + #[doc = "Checks if the value of the field is `SECURE`"] + #[inline(always)] + pub fn is_secure(&self) -> bool { + *self == SECATTR_A::SECURE + } +} +#[doc = "Field `SECATTR` writer - Peripheral security mapping"] +pub type SECATTR_W<'a, const O: u8> = crate::BitWriter<'a, u32, PERM_SPEC, SECATTR_A, O>; +impl<'a, const O: u8> SECATTR_W<'a, O> { + #[doc = "Bus accesses from this domain have the non-secure attribute set"] + #[inline(always)] + pub fn non_secure(self) -> &'a mut W { + self.variant(SECATTR_A::NON_SECURE) + } + #[doc = "Bus accesses from this domain have secure attribute set"] + #[inline(always)] + pub fn secure(self) -> &'a mut W { + self.variant(SECATTR_A::SECURE) + } +} +#[doc = "Field `LOCK` reader - "] +pub type LOCK_R = crate::BitReader; +#[doc = "\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum LOCK_A { + #[doc = "0: This register can be updated"] + UNLOCKED = 0, + #[doc = "1: The content of this register can't be changed until the next reset"] + LOCKED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: LOCK_A) -> Self { + variant as u8 != 0 + } +} +impl LOCK_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> LOCK_A { + match self.bits { + false => LOCK_A::UNLOCKED, + true => LOCK_A::LOCKED, + } + } + #[doc = "Checks if the value of the field is `UNLOCKED`"] + #[inline(always)] + pub fn is_unlocked(&self) -> bool { + *self == LOCK_A::UNLOCKED + } + #[doc = "Checks if the value of the field is `LOCKED`"] + #[inline(always)] + pub fn is_locked(&self) -> bool { + *self == LOCK_A::LOCKED + } +} +#[doc = "Field `LOCK` writer - "] +pub type LOCK_W<'a, const O: u8> = crate::BitWriter<'a, u32, PERM_SPEC, LOCK_A, O>; +impl<'a, const O: u8> LOCK_W<'a, O> { + #[doc = "This register can be updated"] + #[inline(always)] + pub fn unlocked(self) -> &'a mut W { + self.variant(LOCK_A::UNLOCKED) + } + #[doc = "The content of this register can't be changed until the next reset"] + #[inline(always)] + pub fn locked(self) -> &'a mut W { + self.variant(LOCK_A::LOCKED) + } +} +impl R { + #[doc = "Bits 0:1 - Define configuration capabilities for TrustZone Cortex-M secure attribute"] + #[inline(always)] + pub fn securemapping(&self) -> SECUREMAPPING_R { + SECUREMAPPING_R::new((self.bits & 3) as u8) + } + #[doc = "Bit 4 - Peripheral security mapping"] + #[inline(always)] + pub fn secattr(&self) -> SECATTR_R { + SECATTR_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 8"] + #[inline(always)] + pub fn lock(&self) -> LOCK_R { + LOCK_R::new(((self.bits >> 8) & 1) != 0) + } +} +impl W { + #[doc = "Bit 4 - Peripheral security mapping"] + #[inline(always)] + pub fn secattr(&mut self) -> SECATTR_W<4> { + SECATTR_W::new(self) + } + #[doc = "Bit 8"] + #[inline(always)] + pub fn lock(&mut self) -> LOCK_W<8> { + LOCK_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Description cluster: Access for bus access generated from the external domain n List capabilities of the external domain n\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [perm](index.html) module"] +pub struct PERM_SPEC; +impl crate::RegisterSpec for PERM_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [perm::R](R) reader structure"] +impl crate::Readable for PERM_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [perm::W](W) writer structure"] +impl crate::Writable for PERM_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PERM to value 0"] +impl crate::Resettable for PERM_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/spu_s/flashnsc.rs b/pacs/nrf9120-pac/src/spu_s/flashnsc.rs new file mode 100644 index 00000000..80a9e548 --- /dev/null +++ b/pacs/nrf9120-pac/src/spu_s/flashnsc.rs @@ -0,0 +1,16 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct FLASHNSC { + #[doc = "0x00 - Description cluster: Define which flash region can contain the non-secure callable (NSC) region n"] + pub region: REGION, + #[doc = "0x04 - Description cluster: Define the size of the non-secure callable (NSC) region n"] + pub size: SIZE, +} +#[doc = "REGION (rw) register accessor: an alias for `Reg`"] +pub type REGION = crate::Reg; +#[doc = "Description cluster: Define which flash region can contain the non-secure callable (NSC) region n"] +pub mod region; +#[doc = "SIZE (rw) register accessor: an alias for `Reg`"] +pub type SIZE = crate::Reg; +#[doc = "Description cluster: Define the size of the non-secure callable (NSC) region n"] +pub mod size; diff --git a/pacs/nrf9120-pac/src/spu_s/flashnsc/region.rs b/pacs/nrf9120-pac/src/spu_s/flashnsc/region.rs new file mode 100644 index 00000000..a81eca63 --- /dev/null +++ b/pacs/nrf9120-pac/src/spu_s/flashnsc/region.rs @@ -0,0 +1,140 @@ +#[doc = "Register `REGION` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `REGION` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `REGION` reader - Region number"] +pub type REGION_R = crate::FieldReader; +#[doc = "Field `REGION` writer - Region number"] +pub type REGION_W<'a, const O: u8> = crate::FieldWriter<'a, u32, REGION_SPEC, u8, u8, 5, O>; +#[doc = "Field `LOCK` reader - "] +pub type LOCK_R = crate::BitReader; +#[doc = "\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum LOCK_A { + #[doc = "0: This register can be updated"] + UNLOCKED = 0, + #[doc = "1: The content of this register can't be changed until the next reset"] + LOCKED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: LOCK_A) -> Self { + variant as u8 != 0 + } +} +impl LOCK_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> LOCK_A { + match self.bits { + false => LOCK_A::UNLOCKED, + true => LOCK_A::LOCKED, + } + } + #[doc = "Checks if the value of the field is `UNLOCKED`"] + #[inline(always)] + pub fn is_unlocked(&self) -> bool { + *self == LOCK_A::UNLOCKED + } + #[doc = "Checks if the value of the field is `LOCKED`"] + #[inline(always)] + pub fn is_locked(&self) -> bool { + *self == LOCK_A::LOCKED + } +} +#[doc = "Field `LOCK` writer - "] +pub type LOCK_W<'a, const O: u8> = crate::BitWriter<'a, u32, REGION_SPEC, LOCK_A, O>; +impl<'a, const O: u8> LOCK_W<'a, O> { + #[doc = "This register can be updated"] + #[inline(always)] + pub fn unlocked(self) -> &'a mut W { + self.variant(LOCK_A::UNLOCKED) + } + #[doc = "The content of this register can't be changed until the next reset"] + #[inline(always)] + pub fn locked(self) -> &'a mut W { + self.variant(LOCK_A::LOCKED) + } +} +impl R { + #[doc = "Bits 0:4 - Region number"] + #[inline(always)] + pub fn region(&self) -> REGION_R { + REGION_R::new((self.bits & 0x1f) as u8) + } + #[doc = "Bit 8"] + #[inline(always)] + pub fn lock(&self) -> LOCK_R { + LOCK_R::new(((self.bits >> 8) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:4 - Region number"] + #[inline(always)] + pub fn region(&mut self) -> REGION_W<0> { + REGION_W::new(self) + } + #[doc = "Bit 8"] + #[inline(always)] + pub fn lock(&mut self) -> LOCK_W<8> { + LOCK_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Description cluster: Define which flash region can contain the non-secure callable (NSC) region n\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [region](index.html) module"] +pub struct REGION_SPEC; +impl crate::RegisterSpec for REGION_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [region::R](R) reader structure"] +impl crate::Readable for REGION_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [region::W](W) writer structure"] +impl crate::Writable for REGION_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets REGION to value 0"] +impl crate::Resettable for REGION_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/spu_s/flashnsc/size.rs b/pacs/nrf9120-pac/src/spu_s/flashnsc/size.rs new file mode 100644 index 00000000..847bc6df --- /dev/null +++ b/pacs/nrf9120-pac/src/spu_s/flashnsc/size.rs @@ -0,0 +1,279 @@ +#[doc = "Register `SIZE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SIZE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SIZE` reader - Size of the non-secure callable (NSC) region n"] +pub type SIZE_R = crate::FieldReader; +#[doc = "Size of the non-secure callable (NSC) region n\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SIZE_A { + #[doc = "0: The region n is not defined as a non-secure callable region. Normal security attributes (secure or non-secure) are enforced."] + DISABLED = 0, + #[doc = "1: The region n is defined as non-secure callable with a 32-byte size"] + _32 = 1, + #[doc = "2: The region n is defined as non-secure callable with a 64-byte size"] + _64 = 2, + #[doc = "3: The region n is defined as non-secure callable with a 128-byte size"] + _128 = 3, + #[doc = "4: The region n is defined as non-secure callable with a 256-byte size"] + _256 = 4, + #[doc = "5: The region n is defined as non-secure callable with a 512-byte size"] + _512 = 5, + #[doc = "6: The region n is defined as non-secure callable with a 1024-byte size"] + _1024 = 6, + #[doc = "7: The region n is defined as non-secure callable with a 2048-byte size"] + _2048 = 7, + #[doc = "8: The region n is defined as non-secure callable with a 4096-byte size"] + _4096 = 8, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SIZE_A) -> Self { + variant as _ + } +} +impl SIZE_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SIZE_A::DISABLED), + 1 => Some(SIZE_A::_32), + 2 => Some(SIZE_A::_64), + 3 => Some(SIZE_A::_128), + 4 => Some(SIZE_A::_256), + 5 => Some(SIZE_A::_512), + 6 => Some(SIZE_A::_1024), + 7 => Some(SIZE_A::_2048), + 8 => Some(SIZE_A::_4096), + _ => None, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == SIZE_A::DISABLED + } + #[doc = "Checks if the value of the field is `_32`"] + #[inline(always)] + pub fn is_32(&self) -> bool { + *self == SIZE_A::_32 + } + #[doc = "Checks if the value of the field is `_64`"] + #[inline(always)] + pub fn is_64(&self) -> bool { + *self == SIZE_A::_64 + } + #[doc = "Checks if the value of the field is `_128`"] + #[inline(always)] + pub fn is_128(&self) -> bool { + *self == SIZE_A::_128 + } + #[doc = "Checks if the value of the field is `_256`"] + #[inline(always)] + pub fn is_256(&self) -> bool { + *self == SIZE_A::_256 + } + #[doc = "Checks if the value of the field is `_512`"] + #[inline(always)] + pub fn is_512(&self) -> bool { + *self == SIZE_A::_512 + } + #[doc = "Checks if the value of the field is `_1024`"] + #[inline(always)] + pub fn is_1024(&self) -> bool { + *self == SIZE_A::_1024 + } + #[doc = "Checks if the value of the field is `_2048`"] + #[inline(always)] + pub fn is_2048(&self) -> bool { + *self == SIZE_A::_2048 + } + #[doc = "Checks if the value of the field is `_4096`"] + #[inline(always)] + pub fn is_4096(&self) -> bool { + *self == SIZE_A::_4096 + } +} +#[doc = "Field `SIZE` writer - Size of the non-secure callable (NSC) region n"] +pub type SIZE_W<'a, const O: u8> = crate::FieldWriter<'a, u32, SIZE_SPEC, u8, SIZE_A, 4, O>; +impl<'a, const O: u8> SIZE_W<'a, O> { + #[doc = "The region n is not defined as a non-secure callable region. Normal security attributes (secure or non-secure) are enforced."] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(SIZE_A::DISABLED) + } + #[doc = "The region n is defined as non-secure callable with a 32-byte size"] + #[inline(always)] + pub fn _32(self) -> &'a mut W { + self.variant(SIZE_A::_32) + } + #[doc = "The region n is defined as non-secure callable with a 64-byte size"] + #[inline(always)] + pub fn _64(self) -> &'a mut W { + self.variant(SIZE_A::_64) + } + #[doc = "The region n is defined as non-secure callable with a 128-byte size"] + #[inline(always)] + pub fn _128(self) -> &'a mut W { + self.variant(SIZE_A::_128) + } + #[doc = "The region n is defined as non-secure callable with a 256-byte size"] + #[inline(always)] + pub fn _256(self) -> &'a mut W { + self.variant(SIZE_A::_256) + } + #[doc = "The region n is defined as non-secure callable with a 512-byte size"] + #[inline(always)] + pub fn _512(self) -> &'a mut W { + self.variant(SIZE_A::_512) + } + #[doc = "The region n is defined as non-secure callable with a 1024-byte size"] + #[inline(always)] + pub fn _1024(self) -> &'a mut W { + self.variant(SIZE_A::_1024) + } + #[doc = "The region n is defined as non-secure callable with a 2048-byte size"] + #[inline(always)] + pub fn _2048(self) -> &'a mut W { + self.variant(SIZE_A::_2048) + } + #[doc = "The region n is defined as non-secure callable with a 4096-byte size"] + #[inline(always)] + pub fn _4096(self) -> &'a mut W { + self.variant(SIZE_A::_4096) + } +} +#[doc = "Field `LOCK` reader - "] +pub type LOCK_R = crate::BitReader; +#[doc = "\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum LOCK_A { + #[doc = "0: This register can be updated"] + UNLOCKED = 0, + #[doc = "1: The content of this register can't be changed until the next reset"] + LOCKED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: LOCK_A) -> Self { + variant as u8 != 0 + } +} +impl LOCK_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> LOCK_A { + match self.bits { + false => LOCK_A::UNLOCKED, + true => LOCK_A::LOCKED, + } + } + #[doc = "Checks if the value of the field is `UNLOCKED`"] + #[inline(always)] + pub fn is_unlocked(&self) -> bool { + *self == LOCK_A::UNLOCKED + } + #[doc = "Checks if the value of the field is `LOCKED`"] + #[inline(always)] + pub fn is_locked(&self) -> bool { + *self == LOCK_A::LOCKED + } +} +#[doc = "Field `LOCK` writer - "] +pub type LOCK_W<'a, const O: u8> = crate::BitWriter<'a, u32, SIZE_SPEC, LOCK_A, O>; +impl<'a, const O: u8> LOCK_W<'a, O> { + #[doc = "This register can be updated"] + #[inline(always)] + pub fn unlocked(self) -> &'a mut W { + self.variant(LOCK_A::UNLOCKED) + } + #[doc = "The content of this register can't be changed until the next reset"] + #[inline(always)] + pub fn locked(self) -> &'a mut W { + self.variant(LOCK_A::LOCKED) + } +} +impl R { + #[doc = "Bits 0:3 - Size of the non-secure callable (NSC) region n"] + #[inline(always)] + pub fn size(&self) -> SIZE_R { + SIZE_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bit 8"] + #[inline(always)] + pub fn lock(&self) -> LOCK_R { + LOCK_R::new(((self.bits >> 8) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:3 - Size of the non-secure callable (NSC) region n"] + #[inline(always)] + pub fn size(&mut self) -> SIZE_W<0> { + SIZE_W::new(self) + } + #[doc = "Bit 8"] + #[inline(always)] + pub fn lock(&mut self) -> LOCK_W<8> { + LOCK_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Description cluster: Define the size of the non-secure callable (NSC) region n\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [size](index.html) module"] +pub struct SIZE_SPEC; +impl crate::RegisterSpec for SIZE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [size::R](R) reader structure"] +impl crate::Readable for SIZE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [size::W](W) writer structure"] +impl crate::Writable for SIZE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SIZE to value 0"] +impl crate::Resettable for SIZE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/spu_s/flashregion.rs b/pacs/nrf9120-pac/src/spu_s/flashregion.rs new file mode 100644 index 00000000..88fba7bf --- /dev/null +++ b/pacs/nrf9120-pac/src/spu_s/flashregion.rs @@ -0,0 +1,10 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct FLASHREGION { + #[doc = "0x00 - Description cluster: Access permissions for flash region n"] + pub perm: PERM, +} +#[doc = "PERM (rw) register accessor: an alias for `Reg`"] +pub type PERM = crate::Reg; +#[doc = "Description cluster: Access permissions for flash region n"] +pub mod perm; diff --git a/pacs/nrf9120-pac/src/spu_s/flashregion/perm.rs b/pacs/nrf9120-pac/src/spu_s/flashregion/perm.rs new file mode 100644 index 00000000..78ae76da --- /dev/null +++ b/pacs/nrf9120-pac/src/spu_s/flashregion/perm.rs @@ -0,0 +1,366 @@ +#[doc = "Register `PERM` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PERM` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `EXECUTE` reader - Configure instruction fetch permissions from flash region n"] +pub type EXECUTE_R = crate::BitReader; +#[doc = "Configure instruction fetch permissions from flash region n\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum EXECUTE_A { + #[doc = "1: Allow instruction fetches from flash region n"] + ENABLE = 1, + #[doc = "0: Block instruction fetches from flash region n"] + DISABLE = 0, +} +impl From for bool { + #[inline(always)] + fn from(variant: EXECUTE_A) -> Self { + variant as u8 != 0 + } +} +impl EXECUTE_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EXECUTE_A { + match self.bits { + true => EXECUTE_A::ENABLE, + false => EXECUTE_A::DISABLE, + } + } + #[doc = "Checks if the value of the field is `ENABLE`"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == EXECUTE_A::ENABLE + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == EXECUTE_A::DISABLE + } +} +#[doc = "Field `EXECUTE` writer - Configure instruction fetch permissions from flash region n"] +pub type EXECUTE_W<'a, const O: u8> = crate::BitWriter<'a, u32, PERM_SPEC, EXECUTE_A, O>; +impl<'a, const O: u8> EXECUTE_W<'a, O> { + #[doc = "Allow instruction fetches from flash region n"] + #[inline(always)] + pub fn enable(self) -> &'a mut W { + self.variant(EXECUTE_A::ENABLE) + } + #[doc = "Block instruction fetches from flash region n"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(EXECUTE_A::DISABLE) + } +} +#[doc = "Field `WRITE` reader - Configure write permission for flash region n"] +pub type WRITE_R = crate::BitReader; +#[doc = "Configure write permission for flash region n\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum WRITE_A { + #[doc = "1: Allow write operation to region n"] + ENABLE = 1, + #[doc = "0: Block write operation to region n"] + DISABLE = 0, +} +impl From for bool { + #[inline(always)] + fn from(variant: WRITE_A) -> Self { + variant as u8 != 0 + } +} +impl WRITE_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> WRITE_A { + match self.bits { + true => WRITE_A::ENABLE, + false => WRITE_A::DISABLE, + } + } + #[doc = "Checks if the value of the field is `ENABLE`"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == WRITE_A::ENABLE + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == WRITE_A::DISABLE + } +} +#[doc = "Field `WRITE` writer - Configure write permission for flash region n"] +pub type WRITE_W<'a, const O: u8> = crate::BitWriter<'a, u32, PERM_SPEC, WRITE_A, O>; +impl<'a, const O: u8> WRITE_W<'a, O> { + #[doc = "Allow write operation to region n"] + #[inline(always)] + pub fn enable(self) -> &'a mut W { + self.variant(WRITE_A::ENABLE) + } + #[doc = "Block write operation to region n"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(WRITE_A::DISABLE) + } +} +#[doc = "Field `READ` reader - Configure read permissions for flash region n"] +pub type READ_R = crate::BitReader; +#[doc = "Configure read permissions for flash region n\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum READ_A { + #[doc = "1: Allow read operation from flash region n"] + ENABLE = 1, + #[doc = "0: Block read operation from flash region n"] + DISABLE = 0, +} +impl From for bool { + #[inline(always)] + fn from(variant: READ_A) -> Self { + variant as u8 != 0 + } +} +impl READ_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> READ_A { + match self.bits { + true => READ_A::ENABLE, + false => READ_A::DISABLE, + } + } + #[doc = "Checks if the value of the field is `ENABLE`"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == READ_A::ENABLE + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == READ_A::DISABLE + } +} +#[doc = "Field `READ` writer - Configure read permissions for flash region n"] +pub type READ_W<'a, const O: u8> = crate::BitWriter<'a, u32, PERM_SPEC, READ_A, O>; +impl<'a, const O: u8> READ_W<'a, O> { + #[doc = "Allow read operation from flash region n"] + #[inline(always)] + pub fn enable(self) -> &'a mut W { + self.variant(READ_A::ENABLE) + } + #[doc = "Block read operation from flash region n"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(READ_A::DISABLE) + } +} +#[doc = "Field `SECATTR` reader - Security attribute for flash region n"] +pub type SECATTR_R = crate::BitReader; +#[doc = "Security attribute for flash region n\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum SECATTR_A { + #[doc = "0: Flash region n security attribute is non-secure"] + NON_SECURE = 0, + #[doc = "1: Flash region n security attribute is secure"] + SECURE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: SECATTR_A) -> Self { + variant as u8 != 0 + } +} +impl SECATTR_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> SECATTR_A { + match self.bits { + false => SECATTR_A::NON_SECURE, + true => SECATTR_A::SECURE, + } + } + #[doc = "Checks if the value of the field is `NON_SECURE`"] + #[inline(always)] + pub fn is_non_secure(&self) -> bool { + *self == SECATTR_A::NON_SECURE + } + #[doc = "Checks if the value of the field is `SECURE`"] + #[inline(always)] + pub fn is_secure(&self) -> bool { + *self == SECATTR_A::SECURE + } +} +#[doc = "Field `SECATTR` writer - Security attribute for flash region n"] +pub type SECATTR_W<'a, const O: u8> = crate::BitWriter<'a, u32, PERM_SPEC, SECATTR_A, O>; +impl<'a, const O: u8> SECATTR_W<'a, O> { + #[doc = "Flash region n security attribute is non-secure"] + #[inline(always)] + pub fn non_secure(self) -> &'a mut W { + self.variant(SECATTR_A::NON_SECURE) + } + #[doc = "Flash region n security attribute is secure"] + #[inline(always)] + pub fn secure(self) -> &'a mut W { + self.variant(SECATTR_A::SECURE) + } +} +#[doc = "Field `LOCK` reader - "] +pub type LOCK_R = crate::BitReader; +#[doc = "\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum LOCK_A { + #[doc = "0: This register can be updated"] + UNLOCKED = 0, + #[doc = "1: The content of this register can't be changed until the next reset"] + LOCKED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: LOCK_A) -> Self { + variant as u8 != 0 + } +} +impl LOCK_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> LOCK_A { + match self.bits { + false => LOCK_A::UNLOCKED, + true => LOCK_A::LOCKED, + } + } + #[doc = "Checks if the value of the field is `UNLOCKED`"] + #[inline(always)] + pub fn is_unlocked(&self) -> bool { + *self == LOCK_A::UNLOCKED + } + #[doc = "Checks if the value of the field is `LOCKED`"] + #[inline(always)] + pub fn is_locked(&self) -> bool { + *self == LOCK_A::LOCKED + } +} +#[doc = "Field `LOCK` writer - "] +pub type LOCK_W<'a, const O: u8> = crate::BitWriter<'a, u32, PERM_SPEC, LOCK_A, O>; +impl<'a, const O: u8> LOCK_W<'a, O> { + #[doc = "This register can be updated"] + #[inline(always)] + pub fn unlocked(self) -> &'a mut W { + self.variant(LOCK_A::UNLOCKED) + } + #[doc = "The content of this register can't be changed until the next reset"] + #[inline(always)] + pub fn locked(self) -> &'a mut W { + self.variant(LOCK_A::LOCKED) + } +} +impl R { + #[doc = "Bit 0 - Configure instruction fetch permissions from flash region n"] + #[inline(always)] + pub fn execute(&self) -> EXECUTE_R { + EXECUTE_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Configure write permission for flash region n"] + #[inline(always)] + pub fn write(&self) -> WRITE_R { + WRITE_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Configure read permissions for flash region n"] + #[inline(always)] + pub fn read(&self) -> READ_R { + READ_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 4 - Security attribute for flash region n"] + #[inline(always)] + pub fn secattr(&self) -> SECATTR_R { + SECATTR_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 8"] + #[inline(always)] + pub fn lock(&self) -> LOCK_R { + LOCK_R::new(((self.bits >> 8) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Configure instruction fetch permissions from flash region n"] + #[inline(always)] + pub fn execute(&mut self) -> EXECUTE_W<0> { + EXECUTE_W::new(self) + } + #[doc = "Bit 1 - Configure write permission for flash region n"] + #[inline(always)] + pub fn write(&mut self) -> WRITE_W<1> { + WRITE_W::new(self) + } + #[doc = "Bit 2 - Configure read permissions for flash region n"] + #[inline(always)] + pub fn read(&mut self) -> READ_W<2> { + READ_W::new(self) + } + #[doc = "Bit 4 - Security attribute for flash region n"] + #[inline(always)] + pub fn secattr(&mut self) -> SECATTR_W<4> { + SECATTR_W::new(self) + } + #[doc = "Bit 8"] + #[inline(always)] + pub fn lock(&mut self) -> LOCK_W<8> { + LOCK_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Description cluster: Access permissions for flash region n\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [perm](index.html) module"] +pub struct PERM_SPEC; +impl crate::RegisterSpec for PERM_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [perm::R](R) reader structure"] +impl crate::Readable for PERM_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [perm::W](W) writer structure"] +impl crate::Writable for PERM_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PERM to value 0x17"] +impl crate::Resettable for PERM_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x17 + } +} diff --git a/pacs/nrf9120-pac/src/spu_s/gpioport.rs b/pacs/nrf9120-pac/src/spu_s/gpioport.rs new file mode 100644 index 00000000..5f3af919 --- /dev/null +++ b/pacs/nrf9120-pac/src/spu_s/gpioport.rs @@ -0,0 +1,16 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct GPIOPORT { + #[doc = "0x00 - Description cluster: Select between secure and non-secure attribute for pins 0 to 31 of port n."] + pub perm: PERM, + #[doc = "0x04 - Description cluster: Prevent further modification of the corresponding PERM register"] + pub lock: LOCK, +} +#[doc = "PERM (rw) register accessor: an alias for `Reg`"] +pub type PERM = crate::Reg; +#[doc = "Description cluster: Select between secure and non-secure attribute for pins 0 to 31 of port n."] +pub mod perm; +#[doc = "LOCK (rw) register accessor: an alias for `Reg`"] +pub type LOCK = crate::Reg; +#[doc = "Description cluster: Prevent further modification of the corresponding PERM register"] +pub mod lock; diff --git a/pacs/nrf9120-pac/src/spu_s/gpioport/lock.rs b/pacs/nrf9120-pac/src/spu_s/gpioport/lock.rs new file mode 100644 index 00000000..361217d1 --- /dev/null +++ b/pacs/nrf9120-pac/src/spu_s/gpioport/lock.rs @@ -0,0 +1,126 @@ +#[doc = "Register `LOCK` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `LOCK` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `LOCK` reader - "] +pub type LOCK_R = crate::BitReader; +#[doc = "\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum LOCK_A { + #[doc = "1: GPIOPORT\\[n\\].PERM register can't be changed until next reset"] + LOCKED = 1, + #[doc = "0: GPIOPORT\\[n\\].PERM register content can be changed"] + UNLOCKED = 0, +} +impl From for bool { + #[inline(always)] + fn from(variant: LOCK_A) -> Self { + variant as u8 != 0 + } +} +impl LOCK_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> LOCK_A { + match self.bits { + true => LOCK_A::LOCKED, + false => LOCK_A::UNLOCKED, + } + } + #[doc = "Checks if the value of the field is `LOCKED`"] + #[inline(always)] + pub fn is_locked(&self) -> bool { + *self == LOCK_A::LOCKED + } + #[doc = "Checks if the value of the field is `UNLOCKED`"] + #[inline(always)] + pub fn is_unlocked(&self) -> bool { + *self == LOCK_A::UNLOCKED + } +} +#[doc = "Field `LOCK` writer - "] +pub type LOCK_W<'a, const O: u8> = crate::BitWriter<'a, u32, LOCK_SPEC, LOCK_A, O>; +impl<'a, const O: u8> LOCK_W<'a, O> { + #[doc = "GPIOPORT\\[n\\].PERM register can't be changed until next reset"] + #[inline(always)] + pub fn locked(self) -> &'a mut W { + self.variant(LOCK_A::LOCKED) + } + #[doc = "GPIOPORT\\[n\\].PERM register content can be changed"] + #[inline(always)] + pub fn unlocked(self) -> &'a mut W { + self.variant(LOCK_A::UNLOCKED) + } +} +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn lock(&self) -> LOCK_R { + LOCK_R::new((self.bits & 1) != 0) + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn lock(&mut self) -> LOCK_W<0> { + LOCK_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Description cluster: Prevent further modification of the corresponding PERM register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [lock](index.html) module"] +pub struct LOCK_SPEC; +impl crate::RegisterSpec for LOCK_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [lock::R](R) reader structure"] +impl crate::Readable for LOCK_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [lock::W](W) writer structure"] +impl crate::Writable for LOCK_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets LOCK to value 0"] +impl crate::Resettable for LOCK_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/spu_s/gpioport/perm.rs b/pacs/nrf9120-pac/src/spu_s/gpioport/perm.rs new file mode 100644 index 00000000..fc21d817 --- /dev/null +++ b/pacs/nrf9120-pac/src/spu_s/gpioport/perm.rs @@ -0,0 +1,1986 @@ +#[doc = "Register `PERM` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PERM` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PIN0` reader - Select secure attribute attribute for PIN 0."] +pub type PIN0_R = crate::BitReader; +#[doc = "Select secure attribute attribute for PIN 0.\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN0_A { + #[doc = "1: Pin 0 has its secure attribute set"] + SECURE = 1, + #[doc = "0: Pin 0 has its non-secure attribute set"] + NON_SECURE = 0, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN0_A) -> Self { + variant as u8 != 0 + } +} +impl PIN0_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN0_A { + match self.bits { + true => PIN0_A::SECURE, + false => PIN0_A::NON_SECURE, + } + } + #[doc = "Checks if the value of the field is `SECURE`"] + #[inline(always)] + pub fn is_secure(&self) -> bool { + *self == PIN0_A::SECURE + } + #[doc = "Checks if the value of the field is `NON_SECURE`"] + #[inline(always)] + pub fn is_non_secure(&self) -> bool { + *self == PIN0_A::NON_SECURE + } +} +#[doc = "Field `PIN0` writer - Select secure attribute attribute for PIN 0."] +pub type PIN0_W<'a, const O: u8> = crate::BitWriter<'a, u32, PERM_SPEC, PIN0_A, O>; +impl<'a, const O: u8> PIN0_W<'a, O> { + #[doc = "Pin 0 has its secure attribute set"] + #[inline(always)] + pub fn secure(self) -> &'a mut W { + self.variant(PIN0_A::SECURE) + } + #[doc = "Pin 0 has its non-secure attribute set"] + #[inline(always)] + pub fn non_secure(self) -> &'a mut W { + self.variant(PIN0_A::NON_SECURE) + } +} +#[doc = "Field `PIN1` reader - Select secure attribute attribute for PIN 1."] +pub type PIN1_R = crate::BitReader; +#[doc = "Select secure attribute attribute for PIN 1.\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN1_A { + #[doc = "1: Pin 1 has its secure attribute set"] + SECURE = 1, + #[doc = "0: Pin 1 has its non-secure attribute set"] + NON_SECURE = 0, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN1_A) -> Self { + variant as u8 != 0 + } +} +impl PIN1_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN1_A { + match self.bits { + true => PIN1_A::SECURE, + false => PIN1_A::NON_SECURE, + } + } + #[doc = "Checks if the value of the field is `SECURE`"] + #[inline(always)] + pub fn is_secure(&self) -> bool { + *self == PIN1_A::SECURE + } + #[doc = "Checks if the value of the field is `NON_SECURE`"] + #[inline(always)] + pub fn is_non_secure(&self) -> bool { + *self == PIN1_A::NON_SECURE + } +} +#[doc = "Field `PIN1` writer - Select secure attribute attribute for PIN 1."] +pub type PIN1_W<'a, const O: u8> = crate::BitWriter<'a, u32, PERM_SPEC, PIN1_A, O>; +impl<'a, const O: u8> PIN1_W<'a, O> { + #[doc = "Pin 1 has its secure attribute set"] + #[inline(always)] + pub fn secure(self) -> &'a mut W { + self.variant(PIN1_A::SECURE) + } + #[doc = "Pin 1 has its non-secure attribute set"] + #[inline(always)] + pub fn non_secure(self) -> &'a mut W { + self.variant(PIN1_A::NON_SECURE) + } +} +#[doc = "Field `PIN2` reader - Select secure attribute attribute for PIN 2."] +pub type PIN2_R = crate::BitReader; +#[doc = "Select secure attribute attribute for PIN 2.\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN2_A { + #[doc = "1: Pin 2 has its secure attribute set"] + SECURE = 1, + #[doc = "0: Pin 2 has its non-secure attribute set"] + NON_SECURE = 0, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN2_A) -> Self { + variant as u8 != 0 + } +} +impl PIN2_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN2_A { + match self.bits { + true => PIN2_A::SECURE, + false => PIN2_A::NON_SECURE, + } + } + #[doc = "Checks if the value of the field is `SECURE`"] + #[inline(always)] + pub fn is_secure(&self) -> bool { + *self == PIN2_A::SECURE + } + #[doc = "Checks if the value of the field is `NON_SECURE`"] + #[inline(always)] + pub fn is_non_secure(&self) -> bool { + *self == PIN2_A::NON_SECURE + } +} +#[doc = "Field `PIN2` writer - Select secure attribute attribute for PIN 2."] +pub type PIN2_W<'a, const O: u8> = crate::BitWriter<'a, u32, PERM_SPEC, PIN2_A, O>; +impl<'a, const O: u8> PIN2_W<'a, O> { + #[doc = "Pin 2 has its secure attribute set"] + #[inline(always)] + pub fn secure(self) -> &'a mut W { + self.variant(PIN2_A::SECURE) + } + #[doc = "Pin 2 has its non-secure attribute set"] + #[inline(always)] + pub fn non_secure(self) -> &'a mut W { + self.variant(PIN2_A::NON_SECURE) + } +} +#[doc = "Field `PIN3` reader - Select secure attribute attribute for PIN 3."] +pub type PIN3_R = crate::BitReader; +#[doc = "Select secure attribute attribute for PIN 3.\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN3_A { + #[doc = "1: Pin 3 has its secure attribute set"] + SECURE = 1, + #[doc = "0: Pin 3 has its non-secure attribute set"] + NON_SECURE = 0, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN3_A) -> Self { + variant as u8 != 0 + } +} +impl PIN3_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN3_A { + match self.bits { + true => PIN3_A::SECURE, + false => PIN3_A::NON_SECURE, + } + } + #[doc = "Checks if the value of the field is `SECURE`"] + #[inline(always)] + pub fn is_secure(&self) -> bool { + *self == PIN3_A::SECURE + } + #[doc = "Checks if the value of the field is `NON_SECURE`"] + #[inline(always)] + pub fn is_non_secure(&self) -> bool { + *self == PIN3_A::NON_SECURE + } +} +#[doc = "Field `PIN3` writer - Select secure attribute attribute for PIN 3."] +pub type PIN3_W<'a, const O: u8> = crate::BitWriter<'a, u32, PERM_SPEC, PIN3_A, O>; +impl<'a, const O: u8> PIN3_W<'a, O> { + #[doc = "Pin 3 has its secure attribute set"] + #[inline(always)] + pub fn secure(self) -> &'a mut W { + self.variant(PIN3_A::SECURE) + } + #[doc = "Pin 3 has its non-secure attribute set"] + #[inline(always)] + pub fn non_secure(self) -> &'a mut W { + self.variant(PIN3_A::NON_SECURE) + } +} +#[doc = "Field `PIN4` reader - Select secure attribute attribute for PIN 4."] +pub type PIN4_R = crate::BitReader; +#[doc = "Select secure attribute attribute for PIN 4.\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN4_A { + #[doc = "1: Pin 4 has its secure attribute set"] + SECURE = 1, + #[doc = "0: Pin 4 has its non-secure attribute set"] + NON_SECURE = 0, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN4_A) -> Self { + variant as u8 != 0 + } +} +impl PIN4_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN4_A { + match self.bits { + true => PIN4_A::SECURE, + false => PIN4_A::NON_SECURE, + } + } + #[doc = "Checks if the value of the field is `SECURE`"] + #[inline(always)] + pub fn is_secure(&self) -> bool { + *self == PIN4_A::SECURE + } + #[doc = "Checks if the value of the field is `NON_SECURE`"] + #[inline(always)] + pub fn is_non_secure(&self) -> bool { + *self == PIN4_A::NON_SECURE + } +} +#[doc = "Field `PIN4` writer - Select secure attribute attribute for PIN 4."] +pub type PIN4_W<'a, const O: u8> = crate::BitWriter<'a, u32, PERM_SPEC, PIN4_A, O>; +impl<'a, const O: u8> PIN4_W<'a, O> { + #[doc = "Pin 4 has its secure attribute set"] + #[inline(always)] + pub fn secure(self) -> &'a mut W { + self.variant(PIN4_A::SECURE) + } + #[doc = "Pin 4 has its non-secure attribute set"] + #[inline(always)] + pub fn non_secure(self) -> &'a mut W { + self.variant(PIN4_A::NON_SECURE) + } +} +#[doc = "Field `PIN5` reader - Select secure attribute attribute for PIN 5."] +pub type PIN5_R = crate::BitReader; +#[doc = "Select secure attribute attribute for PIN 5.\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN5_A { + #[doc = "1: Pin 5 has its secure attribute set"] + SECURE = 1, + #[doc = "0: Pin 5 has its non-secure attribute set"] + NON_SECURE = 0, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN5_A) -> Self { + variant as u8 != 0 + } +} +impl PIN5_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN5_A { + match self.bits { + true => PIN5_A::SECURE, + false => PIN5_A::NON_SECURE, + } + } + #[doc = "Checks if the value of the field is `SECURE`"] + #[inline(always)] + pub fn is_secure(&self) -> bool { + *self == PIN5_A::SECURE + } + #[doc = "Checks if the value of the field is `NON_SECURE`"] + #[inline(always)] + pub fn is_non_secure(&self) -> bool { + *self == PIN5_A::NON_SECURE + } +} +#[doc = "Field `PIN5` writer - Select secure attribute attribute for PIN 5."] +pub type PIN5_W<'a, const O: u8> = crate::BitWriter<'a, u32, PERM_SPEC, PIN5_A, O>; +impl<'a, const O: u8> PIN5_W<'a, O> { + #[doc = "Pin 5 has its secure attribute set"] + #[inline(always)] + pub fn secure(self) -> &'a mut W { + self.variant(PIN5_A::SECURE) + } + #[doc = "Pin 5 has its non-secure attribute set"] + #[inline(always)] + pub fn non_secure(self) -> &'a mut W { + self.variant(PIN5_A::NON_SECURE) + } +} +#[doc = "Field `PIN6` reader - Select secure attribute attribute for PIN 6."] +pub type PIN6_R = crate::BitReader; +#[doc = "Select secure attribute attribute for PIN 6.\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN6_A { + #[doc = "1: Pin 6 has its secure attribute set"] + SECURE = 1, + #[doc = "0: Pin 6 has its non-secure attribute set"] + NON_SECURE = 0, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN6_A) -> Self { + variant as u8 != 0 + } +} +impl PIN6_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN6_A { + match self.bits { + true => PIN6_A::SECURE, + false => PIN6_A::NON_SECURE, + } + } + #[doc = "Checks if the value of the field is `SECURE`"] + #[inline(always)] + pub fn is_secure(&self) -> bool { + *self == PIN6_A::SECURE + } + #[doc = "Checks if the value of the field is `NON_SECURE`"] + #[inline(always)] + pub fn is_non_secure(&self) -> bool { + *self == PIN6_A::NON_SECURE + } +} +#[doc = "Field `PIN6` writer - Select secure attribute attribute for PIN 6."] +pub type PIN6_W<'a, const O: u8> = crate::BitWriter<'a, u32, PERM_SPEC, PIN6_A, O>; +impl<'a, const O: u8> PIN6_W<'a, O> { + #[doc = "Pin 6 has its secure attribute set"] + #[inline(always)] + pub fn secure(self) -> &'a mut W { + self.variant(PIN6_A::SECURE) + } + #[doc = "Pin 6 has its non-secure attribute set"] + #[inline(always)] + pub fn non_secure(self) -> &'a mut W { + self.variant(PIN6_A::NON_SECURE) + } +} +#[doc = "Field `PIN7` reader - Select secure attribute attribute for PIN 7."] +pub type PIN7_R = crate::BitReader; +#[doc = "Select secure attribute attribute for PIN 7.\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN7_A { + #[doc = "1: Pin 7 has its secure attribute set"] + SECURE = 1, + #[doc = "0: Pin 7 has its non-secure attribute set"] + NON_SECURE = 0, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN7_A) -> Self { + variant as u8 != 0 + } +} +impl PIN7_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN7_A { + match self.bits { + true => PIN7_A::SECURE, + false => PIN7_A::NON_SECURE, + } + } + #[doc = "Checks if the value of the field is `SECURE`"] + #[inline(always)] + pub fn is_secure(&self) -> bool { + *self == PIN7_A::SECURE + } + #[doc = "Checks if the value of the field is `NON_SECURE`"] + #[inline(always)] + pub fn is_non_secure(&self) -> bool { + *self == PIN7_A::NON_SECURE + } +} +#[doc = "Field `PIN7` writer - Select secure attribute attribute for PIN 7."] +pub type PIN7_W<'a, const O: u8> = crate::BitWriter<'a, u32, PERM_SPEC, PIN7_A, O>; +impl<'a, const O: u8> PIN7_W<'a, O> { + #[doc = "Pin 7 has its secure attribute set"] + #[inline(always)] + pub fn secure(self) -> &'a mut W { + self.variant(PIN7_A::SECURE) + } + #[doc = "Pin 7 has its non-secure attribute set"] + #[inline(always)] + pub fn non_secure(self) -> &'a mut W { + self.variant(PIN7_A::NON_SECURE) + } +} +#[doc = "Field `PIN8` reader - Select secure attribute attribute for PIN 8."] +pub type PIN8_R = crate::BitReader; +#[doc = "Select secure attribute attribute for PIN 8.\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN8_A { + #[doc = "1: Pin 8 has its secure attribute set"] + SECURE = 1, + #[doc = "0: Pin 8 has its non-secure attribute set"] + NON_SECURE = 0, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN8_A) -> Self { + variant as u8 != 0 + } +} +impl PIN8_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN8_A { + match self.bits { + true => PIN8_A::SECURE, + false => PIN8_A::NON_SECURE, + } + } + #[doc = "Checks if the value of the field is `SECURE`"] + #[inline(always)] + pub fn is_secure(&self) -> bool { + *self == PIN8_A::SECURE + } + #[doc = "Checks if the value of the field is `NON_SECURE`"] + #[inline(always)] + pub fn is_non_secure(&self) -> bool { + *self == PIN8_A::NON_SECURE + } +} +#[doc = "Field `PIN8` writer - Select secure attribute attribute for PIN 8."] +pub type PIN8_W<'a, const O: u8> = crate::BitWriter<'a, u32, PERM_SPEC, PIN8_A, O>; +impl<'a, const O: u8> PIN8_W<'a, O> { + #[doc = "Pin 8 has its secure attribute set"] + #[inline(always)] + pub fn secure(self) -> &'a mut W { + self.variant(PIN8_A::SECURE) + } + #[doc = "Pin 8 has its non-secure attribute set"] + #[inline(always)] + pub fn non_secure(self) -> &'a mut W { + self.variant(PIN8_A::NON_SECURE) + } +} +#[doc = "Field `PIN9` reader - Select secure attribute attribute for PIN 9."] +pub type PIN9_R = crate::BitReader; +#[doc = "Select secure attribute attribute for PIN 9.\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN9_A { + #[doc = "1: Pin 9 has its secure attribute set"] + SECURE = 1, + #[doc = "0: Pin 9 has its non-secure attribute set"] + NON_SECURE = 0, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN9_A) -> Self { + variant as u8 != 0 + } +} +impl PIN9_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN9_A { + match self.bits { + true => PIN9_A::SECURE, + false => PIN9_A::NON_SECURE, + } + } + #[doc = "Checks if the value of the field is `SECURE`"] + #[inline(always)] + pub fn is_secure(&self) -> bool { + *self == PIN9_A::SECURE + } + #[doc = "Checks if the value of the field is `NON_SECURE`"] + #[inline(always)] + pub fn is_non_secure(&self) -> bool { + *self == PIN9_A::NON_SECURE + } +} +#[doc = "Field `PIN9` writer - Select secure attribute attribute for PIN 9."] +pub type PIN9_W<'a, const O: u8> = crate::BitWriter<'a, u32, PERM_SPEC, PIN9_A, O>; +impl<'a, const O: u8> PIN9_W<'a, O> { + #[doc = "Pin 9 has its secure attribute set"] + #[inline(always)] + pub fn secure(self) -> &'a mut W { + self.variant(PIN9_A::SECURE) + } + #[doc = "Pin 9 has its non-secure attribute set"] + #[inline(always)] + pub fn non_secure(self) -> &'a mut W { + self.variant(PIN9_A::NON_SECURE) + } +} +#[doc = "Field `PIN10` reader - Select secure attribute attribute for PIN 10."] +pub type PIN10_R = crate::BitReader; +#[doc = "Select secure attribute attribute for PIN 10.\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN10_A { + #[doc = "1: Pin 10 has its secure attribute set"] + SECURE = 1, + #[doc = "0: Pin 10 has its non-secure attribute set"] + NON_SECURE = 0, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN10_A) -> Self { + variant as u8 != 0 + } +} +impl PIN10_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN10_A { + match self.bits { + true => PIN10_A::SECURE, + false => PIN10_A::NON_SECURE, + } + } + #[doc = "Checks if the value of the field is `SECURE`"] + #[inline(always)] + pub fn is_secure(&self) -> bool { + *self == PIN10_A::SECURE + } + #[doc = "Checks if the value of the field is `NON_SECURE`"] + #[inline(always)] + pub fn is_non_secure(&self) -> bool { + *self == PIN10_A::NON_SECURE + } +} +#[doc = "Field `PIN10` writer - Select secure attribute attribute for PIN 10."] +pub type PIN10_W<'a, const O: u8> = crate::BitWriter<'a, u32, PERM_SPEC, PIN10_A, O>; +impl<'a, const O: u8> PIN10_W<'a, O> { + #[doc = "Pin 10 has its secure attribute set"] + #[inline(always)] + pub fn secure(self) -> &'a mut W { + self.variant(PIN10_A::SECURE) + } + #[doc = "Pin 10 has its non-secure attribute set"] + #[inline(always)] + pub fn non_secure(self) -> &'a mut W { + self.variant(PIN10_A::NON_SECURE) + } +} +#[doc = "Field `PIN11` reader - Select secure attribute attribute for PIN 11."] +pub type PIN11_R = crate::BitReader; +#[doc = "Select secure attribute attribute for PIN 11.\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN11_A { + #[doc = "1: Pin 11 has its secure attribute set"] + SECURE = 1, + #[doc = "0: Pin 11 has its non-secure attribute set"] + NON_SECURE = 0, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN11_A) -> Self { + variant as u8 != 0 + } +} +impl PIN11_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN11_A { + match self.bits { + true => PIN11_A::SECURE, + false => PIN11_A::NON_SECURE, + } + } + #[doc = "Checks if the value of the field is `SECURE`"] + #[inline(always)] + pub fn is_secure(&self) -> bool { + *self == PIN11_A::SECURE + } + #[doc = "Checks if the value of the field is `NON_SECURE`"] + #[inline(always)] + pub fn is_non_secure(&self) -> bool { + *self == PIN11_A::NON_SECURE + } +} +#[doc = "Field `PIN11` writer - Select secure attribute attribute for PIN 11."] +pub type PIN11_W<'a, const O: u8> = crate::BitWriter<'a, u32, PERM_SPEC, PIN11_A, O>; +impl<'a, const O: u8> PIN11_W<'a, O> { + #[doc = "Pin 11 has its secure attribute set"] + #[inline(always)] + pub fn secure(self) -> &'a mut W { + self.variant(PIN11_A::SECURE) + } + #[doc = "Pin 11 has its non-secure attribute set"] + #[inline(always)] + pub fn non_secure(self) -> &'a mut W { + self.variant(PIN11_A::NON_SECURE) + } +} +#[doc = "Field `PIN12` reader - Select secure attribute attribute for PIN 12."] +pub type PIN12_R = crate::BitReader; +#[doc = "Select secure attribute attribute for PIN 12.\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN12_A { + #[doc = "1: Pin 12 has its secure attribute set"] + SECURE = 1, + #[doc = "0: Pin 12 has its non-secure attribute set"] + NON_SECURE = 0, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN12_A) -> Self { + variant as u8 != 0 + } +} +impl PIN12_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN12_A { + match self.bits { + true => PIN12_A::SECURE, + false => PIN12_A::NON_SECURE, + } + } + #[doc = "Checks if the value of the field is `SECURE`"] + #[inline(always)] + pub fn is_secure(&self) -> bool { + *self == PIN12_A::SECURE + } + #[doc = "Checks if the value of the field is `NON_SECURE`"] + #[inline(always)] + pub fn is_non_secure(&self) -> bool { + *self == PIN12_A::NON_SECURE + } +} +#[doc = "Field `PIN12` writer - Select secure attribute attribute for PIN 12."] +pub type PIN12_W<'a, const O: u8> = crate::BitWriter<'a, u32, PERM_SPEC, PIN12_A, O>; +impl<'a, const O: u8> PIN12_W<'a, O> { + #[doc = "Pin 12 has its secure attribute set"] + #[inline(always)] + pub fn secure(self) -> &'a mut W { + self.variant(PIN12_A::SECURE) + } + #[doc = "Pin 12 has its non-secure attribute set"] + #[inline(always)] + pub fn non_secure(self) -> &'a mut W { + self.variant(PIN12_A::NON_SECURE) + } +} +#[doc = "Field `PIN13` reader - Select secure attribute attribute for PIN 13."] +pub type PIN13_R = crate::BitReader; +#[doc = "Select secure attribute attribute for PIN 13.\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN13_A { + #[doc = "1: Pin 13 has its secure attribute set"] + SECURE = 1, + #[doc = "0: Pin 13 has its non-secure attribute set"] + NON_SECURE = 0, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN13_A) -> Self { + variant as u8 != 0 + } +} +impl PIN13_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN13_A { + match self.bits { + true => PIN13_A::SECURE, + false => PIN13_A::NON_SECURE, + } + } + #[doc = "Checks if the value of the field is `SECURE`"] + #[inline(always)] + pub fn is_secure(&self) -> bool { + *self == PIN13_A::SECURE + } + #[doc = "Checks if the value of the field is `NON_SECURE`"] + #[inline(always)] + pub fn is_non_secure(&self) -> bool { + *self == PIN13_A::NON_SECURE + } +} +#[doc = "Field `PIN13` writer - Select secure attribute attribute for PIN 13."] +pub type PIN13_W<'a, const O: u8> = crate::BitWriter<'a, u32, PERM_SPEC, PIN13_A, O>; +impl<'a, const O: u8> PIN13_W<'a, O> { + #[doc = "Pin 13 has its secure attribute set"] + #[inline(always)] + pub fn secure(self) -> &'a mut W { + self.variant(PIN13_A::SECURE) + } + #[doc = "Pin 13 has its non-secure attribute set"] + #[inline(always)] + pub fn non_secure(self) -> &'a mut W { + self.variant(PIN13_A::NON_SECURE) + } +} +#[doc = "Field `PIN14` reader - Select secure attribute attribute for PIN 14."] +pub type PIN14_R = crate::BitReader; +#[doc = "Select secure attribute attribute for PIN 14.\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN14_A { + #[doc = "1: Pin 14 has its secure attribute set"] + SECURE = 1, + #[doc = "0: Pin 14 has its non-secure attribute set"] + NON_SECURE = 0, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN14_A) -> Self { + variant as u8 != 0 + } +} +impl PIN14_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN14_A { + match self.bits { + true => PIN14_A::SECURE, + false => PIN14_A::NON_SECURE, + } + } + #[doc = "Checks if the value of the field is `SECURE`"] + #[inline(always)] + pub fn is_secure(&self) -> bool { + *self == PIN14_A::SECURE + } + #[doc = "Checks if the value of the field is `NON_SECURE`"] + #[inline(always)] + pub fn is_non_secure(&self) -> bool { + *self == PIN14_A::NON_SECURE + } +} +#[doc = "Field `PIN14` writer - Select secure attribute attribute for PIN 14."] +pub type PIN14_W<'a, const O: u8> = crate::BitWriter<'a, u32, PERM_SPEC, PIN14_A, O>; +impl<'a, const O: u8> PIN14_W<'a, O> { + #[doc = "Pin 14 has its secure attribute set"] + #[inline(always)] + pub fn secure(self) -> &'a mut W { + self.variant(PIN14_A::SECURE) + } + #[doc = "Pin 14 has its non-secure attribute set"] + #[inline(always)] + pub fn non_secure(self) -> &'a mut W { + self.variant(PIN14_A::NON_SECURE) + } +} +#[doc = "Field `PIN15` reader - Select secure attribute attribute for PIN 15."] +pub type PIN15_R = crate::BitReader; +#[doc = "Select secure attribute attribute for PIN 15.\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN15_A { + #[doc = "1: Pin 15 has its secure attribute set"] + SECURE = 1, + #[doc = "0: Pin 15 has its non-secure attribute set"] + NON_SECURE = 0, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN15_A) -> Self { + variant as u8 != 0 + } +} +impl PIN15_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN15_A { + match self.bits { + true => PIN15_A::SECURE, + false => PIN15_A::NON_SECURE, + } + } + #[doc = "Checks if the value of the field is `SECURE`"] + #[inline(always)] + pub fn is_secure(&self) -> bool { + *self == PIN15_A::SECURE + } + #[doc = "Checks if the value of the field is `NON_SECURE`"] + #[inline(always)] + pub fn is_non_secure(&self) -> bool { + *self == PIN15_A::NON_SECURE + } +} +#[doc = "Field `PIN15` writer - Select secure attribute attribute for PIN 15."] +pub type PIN15_W<'a, const O: u8> = crate::BitWriter<'a, u32, PERM_SPEC, PIN15_A, O>; +impl<'a, const O: u8> PIN15_W<'a, O> { + #[doc = "Pin 15 has its secure attribute set"] + #[inline(always)] + pub fn secure(self) -> &'a mut W { + self.variant(PIN15_A::SECURE) + } + #[doc = "Pin 15 has its non-secure attribute set"] + #[inline(always)] + pub fn non_secure(self) -> &'a mut W { + self.variant(PIN15_A::NON_SECURE) + } +} +#[doc = "Field `PIN16` reader - Select secure attribute attribute for PIN 16."] +pub type PIN16_R = crate::BitReader; +#[doc = "Select secure attribute attribute for PIN 16.\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN16_A { + #[doc = "1: Pin 16 has its secure attribute set"] + SECURE = 1, + #[doc = "0: Pin 16 has its non-secure attribute set"] + NON_SECURE = 0, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN16_A) -> Self { + variant as u8 != 0 + } +} +impl PIN16_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN16_A { + match self.bits { + true => PIN16_A::SECURE, + false => PIN16_A::NON_SECURE, + } + } + #[doc = "Checks if the value of the field is `SECURE`"] + #[inline(always)] + pub fn is_secure(&self) -> bool { + *self == PIN16_A::SECURE + } + #[doc = "Checks if the value of the field is `NON_SECURE`"] + #[inline(always)] + pub fn is_non_secure(&self) -> bool { + *self == PIN16_A::NON_SECURE + } +} +#[doc = "Field `PIN16` writer - Select secure attribute attribute for PIN 16."] +pub type PIN16_W<'a, const O: u8> = crate::BitWriter<'a, u32, PERM_SPEC, PIN16_A, O>; +impl<'a, const O: u8> PIN16_W<'a, O> { + #[doc = "Pin 16 has its secure attribute set"] + #[inline(always)] + pub fn secure(self) -> &'a mut W { + self.variant(PIN16_A::SECURE) + } + #[doc = "Pin 16 has its non-secure attribute set"] + #[inline(always)] + pub fn non_secure(self) -> &'a mut W { + self.variant(PIN16_A::NON_SECURE) + } +} +#[doc = "Field `PIN17` reader - Select secure attribute attribute for PIN 17."] +pub type PIN17_R = crate::BitReader; +#[doc = "Select secure attribute attribute for PIN 17.\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN17_A { + #[doc = "1: Pin 17 has its secure attribute set"] + SECURE = 1, + #[doc = "0: Pin 17 has its non-secure attribute set"] + NON_SECURE = 0, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN17_A) -> Self { + variant as u8 != 0 + } +} +impl PIN17_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN17_A { + match self.bits { + true => PIN17_A::SECURE, + false => PIN17_A::NON_SECURE, + } + } + #[doc = "Checks if the value of the field is `SECURE`"] + #[inline(always)] + pub fn is_secure(&self) -> bool { + *self == PIN17_A::SECURE + } + #[doc = "Checks if the value of the field is `NON_SECURE`"] + #[inline(always)] + pub fn is_non_secure(&self) -> bool { + *self == PIN17_A::NON_SECURE + } +} +#[doc = "Field `PIN17` writer - Select secure attribute attribute for PIN 17."] +pub type PIN17_W<'a, const O: u8> = crate::BitWriter<'a, u32, PERM_SPEC, PIN17_A, O>; +impl<'a, const O: u8> PIN17_W<'a, O> { + #[doc = "Pin 17 has its secure attribute set"] + #[inline(always)] + pub fn secure(self) -> &'a mut W { + self.variant(PIN17_A::SECURE) + } + #[doc = "Pin 17 has its non-secure attribute set"] + #[inline(always)] + pub fn non_secure(self) -> &'a mut W { + self.variant(PIN17_A::NON_SECURE) + } +} +#[doc = "Field `PIN18` reader - Select secure attribute attribute for PIN 18."] +pub type PIN18_R = crate::BitReader; +#[doc = "Select secure attribute attribute for PIN 18.\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN18_A { + #[doc = "1: Pin 18 has its secure attribute set"] + SECURE = 1, + #[doc = "0: Pin 18 has its non-secure attribute set"] + NON_SECURE = 0, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN18_A) -> Self { + variant as u8 != 0 + } +} +impl PIN18_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN18_A { + match self.bits { + true => PIN18_A::SECURE, + false => PIN18_A::NON_SECURE, + } + } + #[doc = "Checks if the value of the field is `SECURE`"] + #[inline(always)] + pub fn is_secure(&self) -> bool { + *self == PIN18_A::SECURE + } + #[doc = "Checks if the value of the field is `NON_SECURE`"] + #[inline(always)] + pub fn is_non_secure(&self) -> bool { + *self == PIN18_A::NON_SECURE + } +} +#[doc = "Field `PIN18` writer - Select secure attribute attribute for PIN 18."] +pub type PIN18_W<'a, const O: u8> = crate::BitWriter<'a, u32, PERM_SPEC, PIN18_A, O>; +impl<'a, const O: u8> PIN18_W<'a, O> { + #[doc = "Pin 18 has its secure attribute set"] + #[inline(always)] + pub fn secure(self) -> &'a mut W { + self.variant(PIN18_A::SECURE) + } + #[doc = "Pin 18 has its non-secure attribute set"] + #[inline(always)] + pub fn non_secure(self) -> &'a mut W { + self.variant(PIN18_A::NON_SECURE) + } +} +#[doc = "Field `PIN19` reader - Select secure attribute attribute for PIN 19."] +pub type PIN19_R = crate::BitReader; +#[doc = "Select secure attribute attribute for PIN 19.\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN19_A { + #[doc = "1: Pin 19 has its secure attribute set"] + SECURE = 1, + #[doc = "0: Pin 19 has its non-secure attribute set"] + NON_SECURE = 0, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN19_A) -> Self { + variant as u8 != 0 + } +} +impl PIN19_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN19_A { + match self.bits { + true => PIN19_A::SECURE, + false => PIN19_A::NON_SECURE, + } + } + #[doc = "Checks if the value of the field is `SECURE`"] + #[inline(always)] + pub fn is_secure(&self) -> bool { + *self == PIN19_A::SECURE + } + #[doc = "Checks if the value of the field is `NON_SECURE`"] + #[inline(always)] + pub fn is_non_secure(&self) -> bool { + *self == PIN19_A::NON_SECURE + } +} +#[doc = "Field `PIN19` writer - Select secure attribute attribute for PIN 19."] +pub type PIN19_W<'a, const O: u8> = crate::BitWriter<'a, u32, PERM_SPEC, PIN19_A, O>; +impl<'a, const O: u8> PIN19_W<'a, O> { + #[doc = "Pin 19 has its secure attribute set"] + #[inline(always)] + pub fn secure(self) -> &'a mut W { + self.variant(PIN19_A::SECURE) + } + #[doc = "Pin 19 has its non-secure attribute set"] + #[inline(always)] + pub fn non_secure(self) -> &'a mut W { + self.variant(PIN19_A::NON_SECURE) + } +} +#[doc = "Field `PIN20` reader - Select secure attribute attribute for PIN 20."] +pub type PIN20_R = crate::BitReader; +#[doc = "Select secure attribute attribute for PIN 20.\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN20_A { + #[doc = "1: Pin 20 has its secure attribute set"] + SECURE = 1, + #[doc = "0: Pin 20 has its non-secure attribute set"] + NON_SECURE = 0, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN20_A) -> Self { + variant as u8 != 0 + } +} +impl PIN20_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN20_A { + match self.bits { + true => PIN20_A::SECURE, + false => PIN20_A::NON_SECURE, + } + } + #[doc = "Checks if the value of the field is `SECURE`"] + #[inline(always)] + pub fn is_secure(&self) -> bool { + *self == PIN20_A::SECURE + } + #[doc = "Checks if the value of the field is `NON_SECURE`"] + #[inline(always)] + pub fn is_non_secure(&self) -> bool { + *self == PIN20_A::NON_SECURE + } +} +#[doc = "Field `PIN20` writer - Select secure attribute attribute for PIN 20."] +pub type PIN20_W<'a, const O: u8> = crate::BitWriter<'a, u32, PERM_SPEC, PIN20_A, O>; +impl<'a, const O: u8> PIN20_W<'a, O> { + #[doc = "Pin 20 has its secure attribute set"] + #[inline(always)] + pub fn secure(self) -> &'a mut W { + self.variant(PIN20_A::SECURE) + } + #[doc = "Pin 20 has its non-secure attribute set"] + #[inline(always)] + pub fn non_secure(self) -> &'a mut W { + self.variant(PIN20_A::NON_SECURE) + } +} +#[doc = "Field `PIN21` reader - Select secure attribute attribute for PIN 21."] +pub type PIN21_R = crate::BitReader; +#[doc = "Select secure attribute attribute for PIN 21.\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN21_A { + #[doc = "1: Pin 21 has its secure attribute set"] + SECURE = 1, + #[doc = "0: Pin 21 has its non-secure attribute set"] + NON_SECURE = 0, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN21_A) -> Self { + variant as u8 != 0 + } +} +impl PIN21_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN21_A { + match self.bits { + true => PIN21_A::SECURE, + false => PIN21_A::NON_SECURE, + } + } + #[doc = "Checks if the value of the field is `SECURE`"] + #[inline(always)] + pub fn is_secure(&self) -> bool { + *self == PIN21_A::SECURE + } + #[doc = "Checks if the value of the field is `NON_SECURE`"] + #[inline(always)] + pub fn is_non_secure(&self) -> bool { + *self == PIN21_A::NON_SECURE + } +} +#[doc = "Field `PIN21` writer - Select secure attribute attribute for PIN 21."] +pub type PIN21_W<'a, const O: u8> = crate::BitWriter<'a, u32, PERM_SPEC, PIN21_A, O>; +impl<'a, const O: u8> PIN21_W<'a, O> { + #[doc = "Pin 21 has its secure attribute set"] + #[inline(always)] + pub fn secure(self) -> &'a mut W { + self.variant(PIN21_A::SECURE) + } + #[doc = "Pin 21 has its non-secure attribute set"] + #[inline(always)] + pub fn non_secure(self) -> &'a mut W { + self.variant(PIN21_A::NON_SECURE) + } +} +#[doc = "Field `PIN22` reader - Select secure attribute attribute for PIN 22."] +pub type PIN22_R = crate::BitReader; +#[doc = "Select secure attribute attribute for PIN 22.\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN22_A { + #[doc = "1: Pin 22 has its secure attribute set"] + SECURE = 1, + #[doc = "0: Pin 22 has its non-secure attribute set"] + NON_SECURE = 0, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN22_A) -> Self { + variant as u8 != 0 + } +} +impl PIN22_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN22_A { + match self.bits { + true => PIN22_A::SECURE, + false => PIN22_A::NON_SECURE, + } + } + #[doc = "Checks if the value of the field is `SECURE`"] + #[inline(always)] + pub fn is_secure(&self) -> bool { + *self == PIN22_A::SECURE + } + #[doc = "Checks if the value of the field is `NON_SECURE`"] + #[inline(always)] + pub fn is_non_secure(&self) -> bool { + *self == PIN22_A::NON_SECURE + } +} +#[doc = "Field `PIN22` writer - Select secure attribute attribute for PIN 22."] +pub type PIN22_W<'a, const O: u8> = crate::BitWriter<'a, u32, PERM_SPEC, PIN22_A, O>; +impl<'a, const O: u8> PIN22_W<'a, O> { + #[doc = "Pin 22 has its secure attribute set"] + #[inline(always)] + pub fn secure(self) -> &'a mut W { + self.variant(PIN22_A::SECURE) + } + #[doc = "Pin 22 has its non-secure attribute set"] + #[inline(always)] + pub fn non_secure(self) -> &'a mut W { + self.variant(PIN22_A::NON_SECURE) + } +} +#[doc = "Field `PIN23` reader - Select secure attribute attribute for PIN 23."] +pub type PIN23_R = crate::BitReader; +#[doc = "Select secure attribute attribute for PIN 23.\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN23_A { + #[doc = "1: Pin 23 has its secure attribute set"] + SECURE = 1, + #[doc = "0: Pin 23 has its non-secure attribute set"] + NON_SECURE = 0, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN23_A) -> Self { + variant as u8 != 0 + } +} +impl PIN23_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN23_A { + match self.bits { + true => PIN23_A::SECURE, + false => PIN23_A::NON_SECURE, + } + } + #[doc = "Checks if the value of the field is `SECURE`"] + #[inline(always)] + pub fn is_secure(&self) -> bool { + *self == PIN23_A::SECURE + } + #[doc = "Checks if the value of the field is `NON_SECURE`"] + #[inline(always)] + pub fn is_non_secure(&self) -> bool { + *self == PIN23_A::NON_SECURE + } +} +#[doc = "Field `PIN23` writer - Select secure attribute attribute for PIN 23."] +pub type PIN23_W<'a, const O: u8> = crate::BitWriter<'a, u32, PERM_SPEC, PIN23_A, O>; +impl<'a, const O: u8> PIN23_W<'a, O> { + #[doc = "Pin 23 has its secure attribute set"] + #[inline(always)] + pub fn secure(self) -> &'a mut W { + self.variant(PIN23_A::SECURE) + } + #[doc = "Pin 23 has its non-secure attribute set"] + #[inline(always)] + pub fn non_secure(self) -> &'a mut W { + self.variant(PIN23_A::NON_SECURE) + } +} +#[doc = "Field `PIN24` reader - Select secure attribute attribute for PIN 24."] +pub type PIN24_R = crate::BitReader; +#[doc = "Select secure attribute attribute for PIN 24.\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN24_A { + #[doc = "1: Pin 24 has its secure attribute set"] + SECURE = 1, + #[doc = "0: Pin 24 has its non-secure attribute set"] + NON_SECURE = 0, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN24_A) -> Self { + variant as u8 != 0 + } +} +impl PIN24_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN24_A { + match self.bits { + true => PIN24_A::SECURE, + false => PIN24_A::NON_SECURE, + } + } + #[doc = "Checks if the value of the field is `SECURE`"] + #[inline(always)] + pub fn is_secure(&self) -> bool { + *self == PIN24_A::SECURE + } + #[doc = "Checks if the value of the field is `NON_SECURE`"] + #[inline(always)] + pub fn is_non_secure(&self) -> bool { + *self == PIN24_A::NON_SECURE + } +} +#[doc = "Field `PIN24` writer - Select secure attribute attribute for PIN 24."] +pub type PIN24_W<'a, const O: u8> = crate::BitWriter<'a, u32, PERM_SPEC, PIN24_A, O>; +impl<'a, const O: u8> PIN24_W<'a, O> { + #[doc = "Pin 24 has its secure attribute set"] + #[inline(always)] + pub fn secure(self) -> &'a mut W { + self.variant(PIN24_A::SECURE) + } + #[doc = "Pin 24 has its non-secure attribute set"] + #[inline(always)] + pub fn non_secure(self) -> &'a mut W { + self.variant(PIN24_A::NON_SECURE) + } +} +#[doc = "Field `PIN25` reader - Select secure attribute attribute for PIN 25."] +pub type PIN25_R = crate::BitReader; +#[doc = "Select secure attribute attribute for PIN 25.\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN25_A { + #[doc = "1: Pin 25 has its secure attribute set"] + SECURE = 1, + #[doc = "0: Pin 25 has its non-secure attribute set"] + NON_SECURE = 0, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN25_A) -> Self { + variant as u8 != 0 + } +} +impl PIN25_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN25_A { + match self.bits { + true => PIN25_A::SECURE, + false => PIN25_A::NON_SECURE, + } + } + #[doc = "Checks if the value of the field is `SECURE`"] + #[inline(always)] + pub fn is_secure(&self) -> bool { + *self == PIN25_A::SECURE + } + #[doc = "Checks if the value of the field is `NON_SECURE`"] + #[inline(always)] + pub fn is_non_secure(&self) -> bool { + *self == PIN25_A::NON_SECURE + } +} +#[doc = "Field `PIN25` writer - Select secure attribute attribute for PIN 25."] +pub type PIN25_W<'a, const O: u8> = crate::BitWriter<'a, u32, PERM_SPEC, PIN25_A, O>; +impl<'a, const O: u8> PIN25_W<'a, O> { + #[doc = "Pin 25 has its secure attribute set"] + #[inline(always)] + pub fn secure(self) -> &'a mut W { + self.variant(PIN25_A::SECURE) + } + #[doc = "Pin 25 has its non-secure attribute set"] + #[inline(always)] + pub fn non_secure(self) -> &'a mut W { + self.variant(PIN25_A::NON_SECURE) + } +} +#[doc = "Field `PIN26` reader - Select secure attribute attribute for PIN 26."] +pub type PIN26_R = crate::BitReader; +#[doc = "Select secure attribute attribute for PIN 26.\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN26_A { + #[doc = "1: Pin 26 has its secure attribute set"] + SECURE = 1, + #[doc = "0: Pin 26 has its non-secure attribute set"] + NON_SECURE = 0, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN26_A) -> Self { + variant as u8 != 0 + } +} +impl PIN26_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN26_A { + match self.bits { + true => PIN26_A::SECURE, + false => PIN26_A::NON_SECURE, + } + } + #[doc = "Checks if the value of the field is `SECURE`"] + #[inline(always)] + pub fn is_secure(&self) -> bool { + *self == PIN26_A::SECURE + } + #[doc = "Checks if the value of the field is `NON_SECURE`"] + #[inline(always)] + pub fn is_non_secure(&self) -> bool { + *self == PIN26_A::NON_SECURE + } +} +#[doc = "Field `PIN26` writer - Select secure attribute attribute for PIN 26."] +pub type PIN26_W<'a, const O: u8> = crate::BitWriter<'a, u32, PERM_SPEC, PIN26_A, O>; +impl<'a, const O: u8> PIN26_W<'a, O> { + #[doc = "Pin 26 has its secure attribute set"] + #[inline(always)] + pub fn secure(self) -> &'a mut W { + self.variant(PIN26_A::SECURE) + } + #[doc = "Pin 26 has its non-secure attribute set"] + #[inline(always)] + pub fn non_secure(self) -> &'a mut W { + self.variant(PIN26_A::NON_SECURE) + } +} +#[doc = "Field `PIN27` reader - Select secure attribute attribute for PIN 27."] +pub type PIN27_R = crate::BitReader; +#[doc = "Select secure attribute attribute for PIN 27.\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN27_A { + #[doc = "1: Pin 27 has its secure attribute set"] + SECURE = 1, + #[doc = "0: Pin 27 has its non-secure attribute set"] + NON_SECURE = 0, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN27_A) -> Self { + variant as u8 != 0 + } +} +impl PIN27_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN27_A { + match self.bits { + true => PIN27_A::SECURE, + false => PIN27_A::NON_SECURE, + } + } + #[doc = "Checks if the value of the field is `SECURE`"] + #[inline(always)] + pub fn is_secure(&self) -> bool { + *self == PIN27_A::SECURE + } + #[doc = "Checks if the value of the field is `NON_SECURE`"] + #[inline(always)] + pub fn is_non_secure(&self) -> bool { + *self == PIN27_A::NON_SECURE + } +} +#[doc = "Field `PIN27` writer - Select secure attribute attribute for PIN 27."] +pub type PIN27_W<'a, const O: u8> = crate::BitWriter<'a, u32, PERM_SPEC, PIN27_A, O>; +impl<'a, const O: u8> PIN27_W<'a, O> { + #[doc = "Pin 27 has its secure attribute set"] + #[inline(always)] + pub fn secure(self) -> &'a mut W { + self.variant(PIN27_A::SECURE) + } + #[doc = "Pin 27 has its non-secure attribute set"] + #[inline(always)] + pub fn non_secure(self) -> &'a mut W { + self.variant(PIN27_A::NON_SECURE) + } +} +#[doc = "Field `PIN28` reader - Select secure attribute attribute for PIN 28."] +pub type PIN28_R = crate::BitReader; +#[doc = "Select secure attribute attribute for PIN 28.\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN28_A { + #[doc = "1: Pin 28 has its secure attribute set"] + SECURE = 1, + #[doc = "0: Pin 28 has its non-secure attribute set"] + NON_SECURE = 0, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN28_A) -> Self { + variant as u8 != 0 + } +} +impl PIN28_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN28_A { + match self.bits { + true => PIN28_A::SECURE, + false => PIN28_A::NON_SECURE, + } + } + #[doc = "Checks if the value of the field is `SECURE`"] + #[inline(always)] + pub fn is_secure(&self) -> bool { + *self == PIN28_A::SECURE + } + #[doc = "Checks if the value of the field is `NON_SECURE`"] + #[inline(always)] + pub fn is_non_secure(&self) -> bool { + *self == PIN28_A::NON_SECURE + } +} +#[doc = "Field `PIN28` writer - Select secure attribute attribute for PIN 28."] +pub type PIN28_W<'a, const O: u8> = crate::BitWriter<'a, u32, PERM_SPEC, PIN28_A, O>; +impl<'a, const O: u8> PIN28_W<'a, O> { + #[doc = "Pin 28 has its secure attribute set"] + #[inline(always)] + pub fn secure(self) -> &'a mut W { + self.variant(PIN28_A::SECURE) + } + #[doc = "Pin 28 has its non-secure attribute set"] + #[inline(always)] + pub fn non_secure(self) -> &'a mut W { + self.variant(PIN28_A::NON_SECURE) + } +} +#[doc = "Field `PIN29` reader - Select secure attribute attribute for PIN 29."] +pub type PIN29_R = crate::BitReader; +#[doc = "Select secure attribute attribute for PIN 29.\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN29_A { + #[doc = "1: Pin 29 has its secure attribute set"] + SECURE = 1, + #[doc = "0: Pin 29 has its non-secure attribute set"] + NON_SECURE = 0, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN29_A) -> Self { + variant as u8 != 0 + } +} +impl PIN29_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN29_A { + match self.bits { + true => PIN29_A::SECURE, + false => PIN29_A::NON_SECURE, + } + } + #[doc = "Checks if the value of the field is `SECURE`"] + #[inline(always)] + pub fn is_secure(&self) -> bool { + *self == PIN29_A::SECURE + } + #[doc = "Checks if the value of the field is `NON_SECURE`"] + #[inline(always)] + pub fn is_non_secure(&self) -> bool { + *self == PIN29_A::NON_SECURE + } +} +#[doc = "Field `PIN29` writer - Select secure attribute attribute for PIN 29."] +pub type PIN29_W<'a, const O: u8> = crate::BitWriter<'a, u32, PERM_SPEC, PIN29_A, O>; +impl<'a, const O: u8> PIN29_W<'a, O> { + #[doc = "Pin 29 has its secure attribute set"] + #[inline(always)] + pub fn secure(self) -> &'a mut W { + self.variant(PIN29_A::SECURE) + } + #[doc = "Pin 29 has its non-secure attribute set"] + #[inline(always)] + pub fn non_secure(self) -> &'a mut W { + self.variant(PIN29_A::NON_SECURE) + } +} +#[doc = "Field `PIN30` reader - Select secure attribute attribute for PIN 30."] +pub type PIN30_R = crate::BitReader; +#[doc = "Select secure attribute attribute for PIN 30.\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN30_A { + #[doc = "1: Pin 30 has its secure attribute set"] + SECURE = 1, + #[doc = "0: Pin 30 has its non-secure attribute set"] + NON_SECURE = 0, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN30_A) -> Self { + variant as u8 != 0 + } +} +impl PIN30_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN30_A { + match self.bits { + true => PIN30_A::SECURE, + false => PIN30_A::NON_SECURE, + } + } + #[doc = "Checks if the value of the field is `SECURE`"] + #[inline(always)] + pub fn is_secure(&self) -> bool { + *self == PIN30_A::SECURE + } + #[doc = "Checks if the value of the field is `NON_SECURE`"] + #[inline(always)] + pub fn is_non_secure(&self) -> bool { + *self == PIN30_A::NON_SECURE + } +} +#[doc = "Field `PIN30` writer - Select secure attribute attribute for PIN 30."] +pub type PIN30_W<'a, const O: u8> = crate::BitWriter<'a, u32, PERM_SPEC, PIN30_A, O>; +impl<'a, const O: u8> PIN30_W<'a, O> { + #[doc = "Pin 30 has its secure attribute set"] + #[inline(always)] + pub fn secure(self) -> &'a mut W { + self.variant(PIN30_A::SECURE) + } + #[doc = "Pin 30 has its non-secure attribute set"] + #[inline(always)] + pub fn non_secure(self) -> &'a mut W { + self.variant(PIN30_A::NON_SECURE) + } +} +#[doc = "Field `PIN31` reader - Select secure attribute attribute for PIN 31."] +pub type PIN31_R = crate::BitReader; +#[doc = "Select secure attribute attribute for PIN 31.\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PIN31_A { + #[doc = "1: Pin 31 has its secure attribute set"] + SECURE = 1, + #[doc = "0: Pin 31 has its non-secure attribute set"] + NON_SECURE = 0, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIN31_A) -> Self { + variant as u8 != 0 + } +} +impl PIN31_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN31_A { + match self.bits { + true => PIN31_A::SECURE, + false => PIN31_A::NON_SECURE, + } + } + #[doc = "Checks if the value of the field is `SECURE`"] + #[inline(always)] + pub fn is_secure(&self) -> bool { + *self == PIN31_A::SECURE + } + #[doc = "Checks if the value of the field is `NON_SECURE`"] + #[inline(always)] + pub fn is_non_secure(&self) -> bool { + *self == PIN31_A::NON_SECURE + } +} +#[doc = "Field `PIN31` writer - Select secure attribute attribute for PIN 31."] +pub type PIN31_W<'a, const O: u8> = crate::BitWriter<'a, u32, PERM_SPEC, PIN31_A, O>; +impl<'a, const O: u8> PIN31_W<'a, O> { + #[doc = "Pin 31 has its secure attribute set"] + #[inline(always)] + pub fn secure(self) -> &'a mut W { + self.variant(PIN31_A::SECURE) + } + #[doc = "Pin 31 has its non-secure attribute set"] + #[inline(always)] + pub fn non_secure(self) -> &'a mut W { + self.variant(PIN31_A::NON_SECURE) + } +} +impl R { + #[doc = "Bit 0 - Select secure attribute attribute for PIN 0."] + #[inline(always)] + pub fn pin0(&self) -> PIN0_R { + PIN0_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Select secure attribute attribute for PIN 1."] + #[inline(always)] + pub fn pin1(&self) -> PIN1_R { + PIN1_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Select secure attribute attribute for PIN 2."] + #[inline(always)] + pub fn pin2(&self) -> PIN2_R { + PIN2_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Select secure attribute attribute for PIN 3."] + #[inline(always)] + pub fn pin3(&self) -> PIN3_R { + PIN3_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Select secure attribute attribute for PIN 4."] + #[inline(always)] + pub fn pin4(&self) -> PIN4_R { + PIN4_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Select secure attribute attribute for PIN 5."] + #[inline(always)] + pub fn pin5(&self) -> PIN5_R { + PIN5_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Select secure attribute attribute for PIN 6."] + #[inline(always)] + pub fn pin6(&self) -> PIN6_R { + PIN6_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Select secure attribute attribute for PIN 7."] + #[inline(always)] + pub fn pin7(&self) -> PIN7_R { + PIN7_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Select secure attribute attribute for PIN 8."] + #[inline(always)] + pub fn pin8(&self) -> PIN8_R { + PIN8_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Select secure attribute attribute for PIN 9."] + #[inline(always)] + pub fn pin9(&self) -> PIN9_R { + PIN9_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Select secure attribute attribute for PIN 10."] + #[inline(always)] + pub fn pin10(&self) -> PIN10_R { + PIN10_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Select secure attribute attribute for PIN 11."] + #[inline(always)] + pub fn pin11(&self) -> PIN11_R { + PIN11_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Select secure attribute attribute for PIN 12."] + #[inline(always)] + pub fn pin12(&self) -> PIN12_R { + PIN12_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Select secure attribute attribute for PIN 13."] + #[inline(always)] + pub fn pin13(&self) -> PIN13_R { + PIN13_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Select secure attribute attribute for PIN 14."] + #[inline(always)] + pub fn pin14(&self) -> PIN14_R { + PIN14_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Select secure attribute attribute for PIN 15."] + #[inline(always)] + pub fn pin15(&self) -> PIN15_R { + PIN15_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - Select secure attribute attribute for PIN 16."] + #[inline(always)] + pub fn pin16(&self) -> PIN16_R { + PIN16_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Select secure attribute attribute for PIN 17."] + #[inline(always)] + pub fn pin17(&self) -> PIN17_R { + PIN17_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Select secure attribute attribute for PIN 18."] + #[inline(always)] + pub fn pin18(&self) -> PIN18_R { + PIN18_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Select secure attribute attribute for PIN 19."] + #[inline(always)] + pub fn pin19(&self) -> PIN19_R { + PIN19_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Select secure attribute attribute for PIN 20."] + #[inline(always)] + pub fn pin20(&self) -> PIN20_R { + PIN20_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Select secure attribute attribute for PIN 21."] + #[inline(always)] + pub fn pin21(&self) -> PIN21_R { + PIN21_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Select secure attribute attribute for PIN 22."] + #[inline(always)] + pub fn pin22(&self) -> PIN22_R { + PIN22_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - Select secure attribute attribute for PIN 23."] + #[inline(always)] + pub fn pin23(&self) -> PIN23_R { + PIN23_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - Select secure attribute attribute for PIN 24."] + #[inline(always)] + pub fn pin24(&self) -> PIN24_R { + PIN24_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - Select secure attribute attribute for PIN 25."] + #[inline(always)] + pub fn pin25(&self) -> PIN25_R { + PIN25_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - Select secure attribute attribute for PIN 26."] + #[inline(always)] + pub fn pin26(&self) -> PIN26_R { + PIN26_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - Select secure attribute attribute for PIN 27."] + #[inline(always)] + pub fn pin27(&self) -> PIN27_R { + PIN27_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - Select secure attribute attribute for PIN 28."] + #[inline(always)] + pub fn pin28(&self) -> PIN28_R { + PIN28_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - Select secure attribute attribute for PIN 29."] + #[inline(always)] + pub fn pin29(&self) -> PIN29_R { + PIN29_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Select secure attribute attribute for PIN 30."] + #[inline(always)] + pub fn pin30(&self) -> PIN30_R { + PIN30_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Select secure attribute attribute for PIN 31."] + #[inline(always)] + pub fn pin31(&self) -> PIN31_R { + PIN31_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Select secure attribute attribute for PIN 0."] + #[inline(always)] + pub fn pin0(&mut self) -> PIN0_W<0> { + PIN0_W::new(self) + } + #[doc = "Bit 1 - Select secure attribute attribute for PIN 1."] + #[inline(always)] + pub fn pin1(&mut self) -> PIN1_W<1> { + PIN1_W::new(self) + } + #[doc = "Bit 2 - Select secure attribute attribute for PIN 2."] + #[inline(always)] + pub fn pin2(&mut self) -> PIN2_W<2> { + PIN2_W::new(self) + } + #[doc = "Bit 3 - Select secure attribute attribute for PIN 3."] + #[inline(always)] + pub fn pin3(&mut self) -> PIN3_W<3> { + PIN3_W::new(self) + } + #[doc = "Bit 4 - Select secure attribute attribute for PIN 4."] + #[inline(always)] + pub fn pin4(&mut self) -> PIN4_W<4> { + PIN4_W::new(self) + } + #[doc = "Bit 5 - Select secure attribute attribute for PIN 5."] + #[inline(always)] + pub fn pin5(&mut self) -> PIN5_W<5> { + PIN5_W::new(self) + } + #[doc = "Bit 6 - Select secure attribute attribute for PIN 6."] + #[inline(always)] + pub fn pin6(&mut self) -> PIN6_W<6> { + PIN6_W::new(self) + } + #[doc = "Bit 7 - Select secure attribute attribute for PIN 7."] + #[inline(always)] + pub fn pin7(&mut self) -> PIN7_W<7> { + PIN7_W::new(self) + } + #[doc = "Bit 8 - Select secure attribute attribute for PIN 8."] + #[inline(always)] + pub fn pin8(&mut self) -> PIN8_W<8> { + PIN8_W::new(self) + } + #[doc = "Bit 9 - Select secure attribute attribute for PIN 9."] + #[inline(always)] + pub fn pin9(&mut self) -> PIN9_W<9> { + PIN9_W::new(self) + } + #[doc = "Bit 10 - Select secure attribute attribute for PIN 10."] + #[inline(always)] + pub fn pin10(&mut self) -> PIN10_W<10> { + PIN10_W::new(self) + } + #[doc = "Bit 11 - Select secure attribute attribute for PIN 11."] + #[inline(always)] + pub fn pin11(&mut self) -> PIN11_W<11> { + PIN11_W::new(self) + } + #[doc = "Bit 12 - Select secure attribute attribute for PIN 12."] + #[inline(always)] + pub fn pin12(&mut self) -> PIN12_W<12> { + PIN12_W::new(self) + } + #[doc = "Bit 13 - Select secure attribute attribute for PIN 13."] + #[inline(always)] + pub fn pin13(&mut self) -> PIN13_W<13> { + PIN13_W::new(self) + } + #[doc = "Bit 14 - Select secure attribute attribute for PIN 14."] + #[inline(always)] + pub fn pin14(&mut self) -> PIN14_W<14> { + PIN14_W::new(self) + } + #[doc = "Bit 15 - Select secure attribute attribute for PIN 15."] + #[inline(always)] + pub fn pin15(&mut self) -> PIN15_W<15> { + PIN15_W::new(self) + } + #[doc = "Bit 16 - Select secure attribute attribute for PIN 16."] + #[inline(always)] + pub fn pin16(&mut self) -> PIN16_W<16> { + PIN16_W::new(self) + } + #[doc = "Bit 17 - Select secure attribute attribute for PIN 17."] + #[inline(always)] + pub fn pin17(&mut self) -> PIN17_W<17> { + PIN17_W::new(self) + } + #[doc = "Bit 18 - Select secure attribute attribute for PIN 18."] + #[inline(always)] + pub fn pin18(&mut self) -> PIN18_W<18> { + PIN18_W::new(self) + } + #[doc = "Bit 19 - Select secure attribute attribute for PIN 19."] + #[inline(always)] + pub fn pin19(&mut self) -> PIN19_W<19> { + PIN19_W::new(self) + } + #[doc = "Bit 20 - Select secure attribute attribute for PIN 20."] + #[inline(always)] + pub fn pin20(&mut self) -> PIN20_W<20> { + PIN20_W::new(self) + } + #[doc = "Bit 21 - Select secure attribute attribute for PIN 21."] + #[inline(always)] + pub fn pin21(&mut self) -> PIN21_W<21> { + PIN21_W::new(self) + } + #[doc = "Bit 22 - Select secure attribute attribute for PIN 22."] + #[inline(always)] + pub fn pin22(&mut self) -> PIN22_W<22> { + PIN22_W::new(self) + } + #[doc = "Bit 23 - Select secure attribute attribute for PIN 23."] + #[inline(always)] + pub fn pin23(&mut self) -> PIN23_W<23> { + PIN23_W::new(self) + } + #[doc = "Bit 24 - Select secure attribute attribute for PIN 24."] + #[inline(always)] + pub fn pin24(&mut self) -> PIN24_W<24> { + PIN24_W::new(self) + } + #[doc = "Bit 25 - Select secure attribute attribute for PIN 25."] + #[inline(always)] + pub fn pin25(&mut self) -> PIN25_W<25> { + PIN25_W::new(self) + } + #[doc = "Bit 26 - Select secure attribute attribute for PIN 26."] + #[inline(always)] + pub fn pin26(&mut self) -> PIN26_W<26> { + PIN26_W::new(self) + } + #[doc = "Bit 27 - Select secure attribute attribute for PIN 27."] + #[inline(always)] + pub fn pin27(&mut self) -> PIN27_W<27> { + PIN27_W::new(self) + } + #[doc = "Bit 28 - Select secure attribute attribute for PIN 28."] + #[inline(always)] + pub fn pin28(&mut self) -> PIN28_W<28> { + PIN28_W::new(self) + } + #[doc = "Bit 29 - Select secure attribute attribute for PIN 29."] + #[inline(always)] + pub fn pin29(&mut self) -> PIN29_W<29> { + PIN29_W::new(self) + } + #[doc = "Bit 30 - Select secure attribute attribute for PIN 30."] + #[inline(always)] + pub fn pin30(&mut self) -> PIN30_W<30> { + PIN30_W::new(self) + } + #[doc = "Bit 31 - Select secure attribute attribute for PIN 31."] + #[inline(always)] + pub fn pin31(&mut self) -> PIN31_W<31> { + PIN31_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Description cluster: Select between secure and non-secure attribute for pins 0 to 31 of port n.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [perm](index.html) module"] +pub struct PERM_SPEC; +impl crate::RegisterSpec for PERM_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [perm::R](R) reader structure"] +impl crate::Readable for PERM_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [perm::W](W) writer structure"] +impl crate::Writable for PERM_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PERM to value 0xffff_ffff"] +impl crate::Resettable for PERM_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0xffff_ffff + } +} diff --git a/pacs/nrf9120-pac/src/spu_s/inten.rs b/pacs/nrf9120-pac/src/spu_s/inten.rs new file mode 100644 index 00000000..fc4734c0 --- /dev/null +++ b/pacs/nrf9120-pac/src/spu_s/inten.rs @@ -0,0 +1,246 @@ +#[doc = "Register `INTEN` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTEN` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `RAMACCERR` reader - Enable or disable interrupt for event RAMACCERR"] +pub type RAMACCERR_R = crate::BitReader; +#[doc = "Enable or disable interrupt for event RAMACCERR\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RAMACCERR_A { + #[doc = "0: Disable"] + DISABLED = 0, + #[doc = "1: Enable"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RAMACCERR_A) -> Self { + variant as u8 != 0 + } +} +impl RAMACCERR_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RAMACCERR_A { + match self.bits { + false => RAMACCERR_A::DISABLED, + true => RAMACCERR_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == RAMACCERR_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == RAMACCERR_A::ENABLED + } +} +#[doc = "Field `RAMACCERR` writer - Enable or disable interrupt for event RAMACCERR"] +pub type RAMACCERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTEN_SPEC, RAMACCERR_A, O>; +impl<'a, const O: u8> RAMACCERR_W<'a, O> { + #[doc = "Disable"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(RAMACCERR_A::DISABLED) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(RAMACCERR_A::ENABLED) + } +} +#[doc = "Field `FLASHACCERR` reader - Enable or disable interrupt for event FLASHACCERR"] +pub type FLASHACCERR_R = crate::BitReader; +#[doc = "Enable or disable interrupt for event FLASHACCERR\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum FLASHACCERR_A { + #[doc = "0: Disable"] + DISABLED = 0, + #[doc = "1: Enable"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: FLASHACCERR_A) -> Self { + variant as u8 != 0 + } +} +impl FLASHACCERR_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> FLASHACCERR_A { + match self.bits { + false => FLASHACCERR_A::DISABLED, + true => FLASHACCERR_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == FLASHACCERR_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == FLASHACCERR_A::ENABLED + } +} +#[doc = "Field `FLASHACCERR` writer - Enable or disable interrupt for event FLASHACCERR"] +pub type FLASHACCERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTEN_SPEC, FLASHACCERR_A, O>; +impl<'a, const O: u8> FLASHACCERR_W<'a, O> { + #[doc = "Disable"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(FLASHACCERR_A::DISABLED) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(FLASHACCERR_A::ENABLED) + } +} +#[doc = "Field `PERIPHACCERR` reader - Enable or disable interrupt for event PERIPHACCERR"] +pub type PERIPHACCERR_R = crate::BitReader; +#[doc = "Enable or disable interrupt for event PERIPHACCERR\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PERIPHACCERR_A { + #[doc = "0: Disable"] + DISABLED = 0, + #[doc = "1: Enable"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PERIPHACCERR_A) -> Self { + variant as u8 != 0 + } +} +impl PERIPHACCERR_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PERIPHACCERR_A { + match self.bits { + false => PERIPHACCERR_A::DISABLED, + true => PERIPHACCERR_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == PERIPHACCERR_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == PERIPHACCERR_A::ENABLED + } +} +#[doc = "Field `PERIPHACCERR` writer - Enable or disable interrupt for event PERIPHACCERR"] +pub type PERIPHACCERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTEN_SPEC, PERIPHACCERR_A, O>; +impl<'a, const O: u8> PERIPHACCERR_W<'a, O> { + #[doc = "Disable"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(PERIPHACCERR_A::DISABLED) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(PERIPHACCERR_A::ENABLED) + } +} +impl R { + #[doc = "Bit 0 - Enable or disable interrupt for event RAMACCERR"] + #[inline(always)] + pub fn ramaccerr(&self) -> RAMACCERR_R { + RAMACCERR_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Enable or disable interrupt for event FLASHACCERR"] + #[inline(always)] + pub fn flashaccerr(&self) -> FLASHACCERR_R { + FLASHACCERR_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Enable or disable interrupt for event PERIPHACCERR"] + #[inline(always)] + pub fn periphaccerr(&self) -> PERIPHACCERR_R { + PERIPHACCERR_R::new(((self.bits >> 2) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Enable or disable interrupt for event RAMACCERR"] + #[inline(always)] + pub fn ramaccerr(&mut self) -> RAMACCERR_W<0> { + RAMACCERR_W::new(self) + } + #[doc = "Bit 1 - Enable or disable interrupt for event FLASHACCERR"] + #[inline(always)] + pub fn flashaccerr(&mut self) -> FLASHACCERR_W<1> { + FLASHACCERR_W::new(self) + } + #[doc = "Bit 2 - Enable or disable interrupt for event PERIPHACCERR"] + #[inline(always)] + pub fn periphaccerr(&mut self) -> PERIPHACCERR_W<2> { + PERIPHACCERR_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Enable or disable interrupt\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [inten](index.html) module"] +pub struct INTEN_SPEC; +impl crate::RegisterSpec for INTEN_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [inten::R](R) reader structure"] +impl crate::Readable for INTEN_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [inten::W](W) writer structure"] +impl crate::Writable for INTEN_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTEN to value 0"] +impl crate::Resettable for INTEN_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/spu_s/intenclr.rs b/pacs/nrf9120-pac/src/spu_s/intenclr.rs new file mode 100644 index 00000000..4a7b1b98 --- /dev/null +++ b/pacs/nrf9120-pac/src/spu_s/intenclr.rs @@ -0,0 +1,269 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `RAMACCERR` reader - Write '1' to disable interrupt for event RAMACCERR"] +pub type RAMACCERR_R = crate::BitReader; +#[doc = "Write '1' to disable interrupt for event RAMACCERR\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RAMACCERR_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RAMACCERR_A) -> Self { + variant as u8 != 0 + } +} +impl RAMACCERR_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RAMACCERR_A { + match self.bits { + false => RAMACCERR_A::DISABLED, + true => RAMACCERR_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == RAMACCERR_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == RAMACCERR_A::ENABLED + } +} +#[doc = "Write '1' to disable interrupt for event RAMACCERR\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RAMACCERR_AW { + #[doc = "1: Disable"] + CLEAR = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RAMACCERR_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RAMACCERR` writer - Write '1' to disable interrupt for event RAMACCERR"] +pub type RAMACCERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENCLR_SPEC, RAMACCERR_AW, O>; +impl<'a, const O: u8> RAMACCERR_W<'a, O> { + #[doc = "Disable"] + #[inline(always)] + pub fn clear(self) -> &'a mut W { + self.variant(RAMACCERR_AW::CLEAR) + } +} +#[doc = "Field `FLASHACCERR` reader - Write '1' to disable interrupt for event FLASHACCERR"] +pub type FLASHACCERR_R = crate::BitReader; +#[doc = "Write '1' to disable interrupt for event FLASHACCERR\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum FLASHACCERR_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: FLASHACCERR_A) -> Self { + variant as u8 != 0 + } +} +impl FLASHACCERR_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> FLASHACCERR_A { + match self.bits { + false => FLASHACCERR_A::DISABLED, + true => FLASHACCERR_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == FLASHACCERR_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == FLASHACCERR_A::ENABLED + } +} +#[doc = "Write '1' to disable interrupt for event FLASHACCERR\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum FLASHACCERR_AW { + #[doc = "1: Disable"] + CLEAR = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: FLASHACCERR_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `FLASHACCERR` writer - Write '1' to disable interrupt for event FLASHACCERR"] +pub type FLASHACCERR_W<'a, const O: u8> = + crate::BitWriter<'a, u32, INTENCLR_SPEC, FLASHACCERR_AW, O>; +impl<'a, const O: u8> FLASHACCERR_W<'a, O> { + #[doc = "Disable"] + #[inline(always)] + pub fn clear(self) -> &'a mut W { + self.variant(FLASHACCERR_AW::CLEAR) + } +} +#[doc = "Field `PERIPHACCERR` reader - Write '1' to disable interrupt for event PERIPHACCERR"] +pub type PERIPHACCERR_R = crate::BitReader; +#[doc = "Write '1' to disable interrupt for event PERIPHACCERR\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PERIPHACCERR_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PERIPHACCERR_A) -> Self { + variant as u8 != 0 + } +} +impl PERIPHACCERR_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PERIPHACCERR_A { + match self.bits { + false => PERIPHACCERR_A::DISABLED, + true => PERIPHACCERR_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == PERIPHACCERR_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == PERIPHACCERR_A::ENABLED + } +} +#[doc = "Write '1' to disable interrupt for event PERIPHACCERR\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PERIPHACCERR_AW { + #[doc = "1: Disable"] + CLEAR = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PERIPHACCERR_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PERIPHACCERR` writer - Write '1' to disable interrupt for event PERIPHACCERR"] +pub type PERIPHACCERR_W<'a, const O: u8> = + crate::BitWriter<'a, u32, INTENCLR_SPEC, PERIPHACCERR_AW, O>; +impl<'a, const O: u8> PERIPHACCERR_W<'a, O> { + #[doc = "Disable"] + #[inline(always)] + pub fn clear(self) -> &'a mut W { + self.variant(PERIPHACCERR_AW::CLEAR) + } +} +impl R { + #[doc = "Bit 0 - Write '1' to disable interrupt for event RAMACCERR"] + #[inline(always)] + pub fn ramaccerr(&self) -> RAMACCERR_R { + RAMACCERR_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Write '1' to disable interrupt for event FLASHACCERR"] + #[inline(always)] + pub fn flashaccerr(&self) -> FLASHACCERR_R { + FLASHACCERR_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Write '1' to disable interrupt for event PERIPHACCERR"] + #[inline(always)] + pub fn periphaccerr(&self) -> PERIPHACCERR_R { + PERIPHACCERR_R::new(((self.bits >> 2) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Write '1' to disable interrupt for event RAMACCERR"] + #[inline(always)] + pub fn ramaccerr(&mut self) -> RAMACCERR_W<0> { + RAMACCERR_W::new(self) + } + #[doc = "Bit 1 - Write '1' to disable interrupt for event FLASHACCERR"] + #[inline(always)] + pub fn flashaccerr(&mut self) -> FLASHACCERR_W<1> { + FLASHACCERR_W::new(self) + } + #[doc = "Bit 2 - Write '1' to disable interrupt for event PERIPHACCERR"] + #[inline(always)] + pub fn periphaccerr(&mut self) -> PERIPHACCERR_W<2> { + PERIPHACCERR_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Disable interrupt\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/spu_s/intenset.rs b/pacs/nrf9120-pac/src/spu_s/intenset.rs new file mode 100644 index 00000000..521ab92c --- /dev/null +++ b/pacs/nrf9120-pac/src/spu_s/intenset.rs @@ -0,0 +1,269 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `RAMACCERR` reader - Write '1' to enable interrupt for event RAMACCERR"] +pub type RAMACCERR_R = crate::BitReader; +#[doc = "Write '1' to enable interrupt for event RAMACCERR\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RAMACCERR_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RAMACCERR_A) -> Self { + variant as u8 != 0 + } +} +impl RAMACCERR_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RAMACCERR_A { + match self.bits { + false => RAMACCERR_A::DISABLED, + true => RAMACCERR_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == RAMACCERR_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == RAMACCERR_A::ENABLED + } +} +#[doc = "Write '1' to enable interrupt for event RAMACCERR\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RAMACCERR_AW { + #[doc = "1: Enable"] + SET = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RAMACCERR_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RAMACCERR` writer - Write '1' to enable interrupt for event RAMACCERR"] +pub type RAMACCERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENSET_SPEC, RAMACCERR_AW, O>; +impl<'a, const O: u8> RAMACCERR_W<'a, O> { + #[doc = "Enable"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(RAMACCERR_AW::SET) + } +} +#[doc = "Field `FLASHACCERR` reader - Write '1' to enable interrupt for event FLASHACCERR"] +pub type FLASHACCERR_R = crate::BitReader; +#[doc = "Write '1' to enable interrupt for event FLASHACCERR\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum FLASHACCERR_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: FLASHACCERR_A) -> Self { + variant as u8 != 0 + } +} +impl FLASHACCERR_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> FLASHACCERR_A { + match self.bits { + false => FLASHACCERR_A::DISABLED, + true => FLASHACCERR_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == FLASHACCERR_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == FLASHACCERR_A::ENABLED + } +} +#[doc = "Write '1' to enable interrupt for event FLASHACCERR\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum FLASHACCERR_AW { + #[doc = "1: Enable"] + SET = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: FLASHACCERR_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `FLASHACCERR` writer - Write '1' to enable interrupt for event FLASHACCERR"] +pub type FLASHACCERR_W<'a, const O: u8> = + crate::BitWriter<'a, u32, INTENSET_SPEC, FLASHACCERR_AW, O>; +impl<'a, const O: u8> FLASHACCERR_W<'a, O> { + #[doc = "Enable"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(FLASHACCERR_AW::SET) + } +} +#[doc = "Field `PERIPHACCERR` reader - Write '1' to enable interrupt for event PERIPHACCERR"] +pub type PERIPHACCERR_R = crate::BitReader; +#[doc = "Write '1' to enable interrupt for event PERIPHACCERR\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PERIPHACCERR_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PERIPHACCERR_A) -> Self { + variant as u8 != 0 + } +} +impl PERIPHACCERR_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PERIPHACCERR_A { + match self.bits { + false => PERIPHACCERR_A::DISABLED, + true => PERIPHACCERR_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == PERIPHACCERR_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == PERIPHACCERR_A::ENABLED + } +} +#[doc = "Write '1' to enable interrupt for event PERIPHACCERR\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PERIPHACCERR_AW { + #[doc = "1: Enable"] + SET = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PERIPHACCERR_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PERIPHACCERR` writer - Write '1' to enable interrupt for event PERIPHACCERR"] +pub type PERIPHACCERR_W<'a, const O: u8> = + crate::BitWriter<'a, u32, INTENSET_SPEC, PERIPHACCERR_AW, O>; +impl<'a, const O: u8> PERIPHACCERR_W<'a, O> { + #[doc = "Enable"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(PERIPHACCERR_AW::SET) + } +} +impl R { + #[doc = "Bit 0 - Write '1' to enable interrupt for event RAMACCERR"] + #[inline(always)] + pub fn ramaccerr(&self) -> RAMACCERR_R { + RAMACCERR_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Write '1' to enable interrupt for event FLASHACCERR"] + #[inline(always)] + pub fn flashaccerr(&self) -> FLASHACCERR_R { + FLASHACCERR_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Write '1' to enable interrupt for event PERIPHACCERR"] + #[inline(always)] + pub fn periphaccerr(&self) -> PERIPHACCERR_R { + PERIPHACCERR_R::new(((self.bits >> 2) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Write '1' to enable interrupt for event RAMACCERR"] + #[inline(always)] + pub fn ramaccerr(&mut self) -> RAMACCERR_W<0> { + RAMACCERR_W::new(self) + } + #[doc = "Bit 1 - Write '1' to enable interrupt for event FLASHACCERR"] + #[inline(always)] + pub fn flashaccerr(&mut self) -> FLASHACCERR_W<1> { + FLASHACCERR_W::new(self) + } + #[doc = "Bit 2 - Write '1' to enable interrupt for event PERIPHACCERR"] + #[inline(always)] + pub fn periphaccerr(&mut self) -> PERIPHACCERR_W<2> { + PERIPHACCERR_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Enable interrupt\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/spu_s/periphid.rs b/pacs/nrf9120-pac/src/spu_s/periphid.rs new file mode 100644 index 00000000..30aa257a --- /dev/null +++ b/pacs/nrf9120-pac/src/spu_s/periphid.rs @@ -0,0 +1,10 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct PERIPHID { + #[doc = "0x00 - Description cluster: List capabilities and access permissions for the peripheral with ID n"] + pub perm: PERM, +} +#[doc = "PERM (rw) register accessor: an alias for `Reg`"] +pub type PERM = crate::Reg; +#[doc = "Description cluster: List capabilities and access permissions for the peripheral with ID n"] +pub mod perm; diff --git a/pacs/nrf9120-pac/src/spu_s/periphid/perm.rs b/pacs/nrf9120-pac/src/spu_s/periphid/perm.rs new file mode 100644 index 00000000..a594d0d5 --- /dev/null +++ b/pacs/nrf9120-pac/src/spu_s/periphid/perm.rs @@ -0,0 +1,397 @@ +#[doc = "Register `PERM` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PERM` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SECUREMAPPING` reader - Define configuration capabilities for TrustZone Cortex-M secure attribute"] +pub type SECUREMAPPING_R = crate::FieldReader; +#[doc = "Define configuration capabilities for TrustZone Cortex-M secure attribute\n\nValue on reset: 2"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SECUREMAPPING_A { + #[doc = "0: This peripheral is always accessible as a non-secure peripheral"] + NON_SECURE = 0, + #[doc = "1: This peripheral is always accessible as a secure peripheral"] + SECURE = 1, + #[doc = "2: Non-secure or secure attribute for this peripheral is defined by the PERIPHID\\[n\\].PERM register"] + USER_SELECTABLE = 2, + #[doc = "3: This peripheral implements the split security mechanism. Non-secure or secure attribute for this peripheral is defined by the PERIPHID\\[n\\].PERM register."] + SPLIT = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SECUREMAPPING_A) -> Self { + variant as _ + } +} +impl SECUREMAPPING_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> SECUREMAPPING_A { + match self.bits { + 0 => SECUREMAPPING_A::NON_SECURE, + 1 => SECUREMAPPING_A::SECURE, + 2 => SECUREMAPPING_A::USER_SELECTABLE, + 3 => SECUREMAPPING_A::SPLIT, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `NON_SECURE`"] + #[inline(always)] + pub fn is_non_secure(&self) -> bool { + *self == SECUREMAPPING_A::NON_SECURE + } + #[doc = "Checks if the value of the field is `SECURE`"] + #[inline(always)] + pub fn is_secure(&self) -> bool { + *self == SECUREMAPPING_A::SECURE + } + #[doc = "Checks if the value of the field is `USER_SELECTABLE`"] + #[inline(always)] + pub fn is_user_selectable(&self) -> bool { + *self == SECUREMAPPING_A::USER_SELECTABLE + } + #[doc = "Checks if the value of the field is `SPLIT`"] + #[inline(always)] + pub fn is_split(&self) -> bool { + *self == SECUREMAPPING_A::SPLIT + } +} +#[doc = "Field `DMA` reader - Indicate if the peripheral has DMA capabilities and if DMA transfer can be assigned to a different security attribute than the peripheral itself"] +pub type DMA_R = crate::FieldReader; +#[doc = "Indicate if the peripheral has DMA capabilities and if DMA transfer can be assigned to a different security attribute than the peripheral itself\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum DMA_A { + #[doc = "0: Peripheral has no DMA capability"] + NO_DMA = 0, + #[doc = "1: Peripheral has DMA and DMA transfers always have the same security attribute as assigned to the peripheral"] + NO_SEPARATE_ATTRIBUTE = 1, + #[doc = "2: Peripheral has DMA and DMA transfers can have a different security attribute than the one assigned to the peripheral"] + SEPARATE_ATTRIBUTE = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: DMA_A) -> Self { + variant as _ + } +} +impl DMA_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(DMA_A::NO_DMA), + 1 => Some(DMA_A::NO_SEPARATE_ATTRIBUTE), + 2 => Some(DMA_A::SEPARATE_ATTRIBUTE), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NO_DMA`"] + #[inline(always)] + pub fn is_no_dma(&self) -> bool { + *self == DMA_A::NO_DMA + } + #[doc = "Checks if the value of the field is `NO_SEPARATE_ATTRIBUTE`"] + #[inline(always)] + pub fn is_no_separate_attribute(&self) -> bool { + *self == DMA_A::NO_SEPARATE_ATTRIBUTE + } + #[doc = "Checks if the value of the field is `SEPARATE_ATTRIBUTE`"] + #[inline(always)] + pub fn is_separate_attribute(&self) -> bool { + *self == DMA_A::SEPARATE_ATTRIBUTE + } +} +#[doc = "Field `SECATTR` reader - Peripheral security mapping"] +pub type SECATTR_R = crate::BitReader; +#[doc = "Peripheral security mapping\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum SECATTR_A { + #[doc = "1: Peripheral is mapped in secure peripheral address space"] + SECURE = 1, + #[doc = "0: If SECUREMAPPING == UserSelectable: Peripheral is mapped in non-secure peripheral address space. If SECUREMAPPING == Split: Peripheral is mapped in non-secure and secure peripheral address space."] + NON_SECURE = 0, +} +impl From for bool { + #[inline(always)] + fn from(variant: SECATTR_A) -> Self { + variant as u8 != 0 + } +} +impl SECATTR_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> SECATTR_A { + match self.bits { + true => SECATTR_A::SECURE, + false => SECATTR_A::NON_SECURE, + } + } + #[doc = "Checks if the value of the field is `SECURE`"] + #[inline(always)] + pub fn is_secure(&self) -> bool { + *self == SECATTR_A::SECURE + } + #[doc = "Checks if the value of the field is `NON_SECURE`"] + #[inline(always)] + pub fn is_non_secure(&self) -> bool { + *self == SECATTR_A::NON_SECURE + } +} +#[doc = "Field `SECATTR` writer - Peripheral security mapping"] +pub type SECATTR_W<'a, const O: u8> = crate::BitWriter<'a, u32, PERM_SPEC, SECATTR_A, O>; +impl<'a, const O: u8> SECATTR_W<'a, O> { + #[doc = "Peripheral is mapped in secure peripheral address space"] + #[inline(always)] + pub fn secure(self) -> &'a mut W { + self.variant(SECATTR_A::SECURE) + } + #[doc = "If SECUREMAPPING == UserSelectable: Peripheral is mapped in non-secure peripheral address space. If SECUREMAPPING == Split: Peripheral is mapped in non-secure and secure peripheral address space."] + #[inline(always)] + pub fn non_secure(self) -> &'a mut W { + self.variant(SECATTR_A::NON_SECURE) + } +} +#[doc = "Field `DMASEC` reader - Security attribution for the DMA transfer"] +pub type DMASEC_R = crate::BitReader; +#[doc = "Security attribution for the DMA transfer\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum DMASEC_A { + #[doc = "1: DMA transfers initiated by this peripheral have the secure attribute set"] + SECURE = 1, + #[doc = "0: DMA transfers initiated by this peripheral have the non-secure attribute set"] + NON_SECURE = 0, +} +impl From for bool { + #[inline(always)] + fn from(variant: DMASEC_A) -> Self { + variant as u8 != 0 + } +} +impl DMASEC_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> DMASEC_A { + match self.bits { + true => DMASEC_A::SECURE, + false => DMASEC_A::NON_SECURE, + } + } + #[doc = "Checks if the value of the field is `SECURE`"] + #[inline(always)] + pub fn is_secure(&self) -> bool { + *self == DMASEC_A::SECURE + } + #[doc = "Checks if the value of the field is `NON_SECURE`"] + #[inline(always)] + pub fn is_non_secure(&self) -> bool { + *self == DMASEC_A::NON_SECURE + } +} +#[doc = "Field `DMASEC` writer - Security attribution for the DMA transfer"] +pub type DMASEC_W<'a, const O: u8> = crate::BitWriter<'a, u32, PERM_SPEC, DMASEC_A, O>; +impl<'a, const O: u8> DMASEC_W<'a, O> { + #[doc = "DMA transfers initiated by this peripheral have the secure attribute set"] + #[inline(always)] + pub fn secure(self) -> &'a mut W { + self.variant(DMASEC_A::SECURE) + } + #[doc = "DMA transfers initiated by this peripheral have the non-secure attribute set"] + #[inline(always)] + pub fn non_secure(self) -> &'a mut W { + self.variant(DMASEC_A::NON_SECURE) + } +} +#[doc = "Field `LOCK` reader - "] +pub type LOCK_R = crate::BitReader; +#[doc = "\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum LOCK_A { + #[doc = "0: This register can be updated"] + UNLOCKED = 0, + #[doc = "1: The content of this register can't be changed until the next reset"] + LOCKED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: LOCK_A) -> Self { + variant as u8 != 0 + } +} +impl LOCK_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> LOCK_A { + match self.bits { + false => LOCK_A::UNLOCKED, + true => LOCK_A::LOCKED, + } + } + #[doc = "Checks if the value of the field is `UNLOCKED`"] + #[inline(always)] + pub fn is_unlocked(&self) -> bool { + *self == LOCK_A::UNLOCKED + } + #[doc = "Checks if the value of the field is `LOCKED`"] + #[inline(always)] + pub fn is_locked(&self) -> bool { + *self == LOCK_A::LOCKED + } +} +#[doc = "Field `LOCK` writer - "] +pub type LOCK_W<'a, const O: u8> = crate::BitWriter<'a, u32, PERM_SPEC, LOCK_A, O>; +impl<'a, const O: u8> LOCK_W<'a, O> { + #[doc = "This register can be updated"] + #[inline(always)] + pub fn unlocked(self) -> &'a mut W { + self.variant(LOCK_A::UNLOCKED) + } + #[doc = "The content of this register can't be changed until the next reset"] + #[inline(always)] + pub fn locked(self) -> &'a mut W { + self.variant(LOCK_A::LOCKED) + } +} +#[doc = "Field `PRESENT` reader - Indicate if a peripheral is present with ID n"] +pub type PRESENT_R = crate::BitReader; +#[doc = "Indicate if a peripheral is present with ID n\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PRESENT_A { + #[doc = "0: Peripheral is not present"] + NOT_PRESENT = 0, + #[doc = "1: Peripheral is present"] + IS_PRESENT = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PRESENT_A) -> Self { + variant as u8 != 0 + } +} +impl PRESENT_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PRESENT_A { + match self.bits { + false => PRESENT_A::NOT_PRESENT, + true => PRESENT_A::IS_PRESENT, + } + } + #[doc = "Checks if the value of the field is `NOT_PRESENT`"] + #[inline(always)] + pub fn is_not_present(&self) -> bool { + *self == PRESENT_A::NOT_PRESENT + } + #[doc = "Checks if the value of the field is `IS_PRESENT`"] + #[inline(always)] + pub fn is_is_present(&self) -> bool { + *self == PRESENT_A::IS_PRESENT + } +} +impl R { + #[doc = "Bits 0:1 - Define configuration capabilities for TrustZone Cortex-M secure attribute"] + #[inline(always)] + pub fn securemapping(&self) -> SECUREMAPPING_R { + SECUREMAPPING_R::new((self.bits & 3) as u8) + } + #[doc = "Bits 2:3 - Indicate if the peripheral has DMA capabilities and if DMA transfer can be assigned to a different security attribute than the peripheral itself"] + #[inline(always)] + pub fn dma(&self) -> DMA_R { + DMA_R::new(((self.bits >> 2) & 3) as u8) + } + #[doc = "Bit 4 - Peripheral security mapping"] + #[inline(always)] + pub fn secattr(&self) -> SECATTR_R { + SECATTR_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Security attribution for the DMA transfer"] + #[inline(always)] + pub fn dmasec(&self) -> DMASEC_R { + DMASEC_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 8"] + #[inline(always)] + pub fn lock(&self) -> LOCK_R { + LOCK_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 31 - Indicate if a peripheral is present with ID n"] + #[inline(always)] + pub fn present(&self) -> PRESENT_R { + PRESENT_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bit 4 - Peripheral security mapping"] + #[inline(always)] + pub fn secattr(&mut self) -> SECATTR_W<4> { + SECATTR_W::new(self) + } + #[doc = "Bit 5 - Security attribution for the DMA transfer"] + #[inline(always)] + pub fn dmasec(&mut self) -> DMASEC_W<5> { + DMASEC_W::new(self) + } + #[doc = "Bit 8"] + #[inline(always)] + pub fn lock(&mut self) -> LOCK_W<8> { + LOCK_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Description cluster: List capabilities and access permissions for the peripheral with ID n\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [perm](index.html) module"] +pub struct PERM_SPEC; +impl crate::RegisterSpec for PERM_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [perm::R](R) reader structure"] +impl crate::Readable for PERM_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [perm::W](W) writer structure"] +impl crate::Writable for PERM_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PERM to value 0x12"] +impl crate::Resettable for PERM_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x12 + } +} diff --git a/pacs/nrf9120-pac/src/spu_s/publish_flashaccerr.rs b/pacs/nrf9120-pac/src/spu_s/publish_flashaccerr.rs new file mode 100644 index 00000000..4700c31c --- /dev/null +++ b/pacs/nrf9120-pac/src/spu_s/publish_flashaccerr.rs @@ -0,0 +1,141 @@ +#[doc = "Register `PUBLISH_FLASHACCERR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PUBLISH_FLASHACCERR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CHIDX` reader - DPPI channel that event FLASHACCERR will publish to"] +pub type CHIDX_R = crate::FieldReader; +#[doc = "Field `CHIDX` writer - DPPI channel that event FLASHACCERR will publish to"] +pub type CHIDX_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, PUBLISH_FLASHACCERR_SPEC, u8, u8, 8, O>; +#[doc = "Field `EN` reader - "] +pub type EN_R = crate::BitReader; +#[doc = "\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum EN_A { + #[doc = "0: Disable publishing"] + DISABLED = 0, + #[doc = "1: Enable publishing"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: EN_A) -> Self { + variant as u8 != 0 + } +} +impl EN_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EN_A { + match self.bits { + false => EN_A::DISABLED, + true => EN_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == EN_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == EN_A::ENABLED + } +} +#[doc = "Field `EN` writer - "] +pub type EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, PUBLISH_FLASHACCERR_SPEC, EN_A, O>; +impl<'a, const O: u8> EN_W<'a, O> { + #[doc = "Disable publishing"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(EN_A::DISABLED) + } + #[doc = "Enable publishing"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(EN_A::ENABLED) + } +} +impl R { + #[doc = "Bits 0:7 - DPPI channel that event FLASHACCERR will publish to"] + #[inline(always)] + pub fn chidx(&self) -> CHIDX_R { + CHIDX_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&self) -> EN_R { + EN_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:7 - DPPI channel that event FLASHACCERR will publish to"] + #[inline(always)] + pub fn chidx(&mut self) -> CHIDX_W<0> { + CHIDX_W::new(self) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&mut self) -> EN_W<31> { + EN_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Publish configuration for event FLASHACCERR\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [publish_flashaccerr](index.html) module"] +pub struct PUBLISH_FLASHACCERR_SPEC; +impl crate::RegisterSpec for PUBLISH_FLASHACCERR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [publish_flashaccerr::R](R) reader structure"] +impl crate::Readable for PUBLISH_FLASHACCERR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [publish_flashaccerr::W](W) writer structure"] +impl crate::Writable for PUBLISH_FLASHACCERR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PUBLISH_FLASHACCERR to value 0"] +impl crate::Resettable for PUBLISH_FLASHACCERR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/spu_s/publish_periphaccerr.rs b/pacs/nrf9120-pac/src/spu_s/publish_periphaccerr.rs new file mode 100644 index 00000000..1b74e5ab --- /dev/null +++ b/pacs/nrf9120-pac/src/spu_s/publish_periphaccerr.rs @@ -0,0 +1,141 @@ +#[doc = "Register `PUBLISH_PERIPHACCERR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PUBLISH_PERIPHACCERR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CHIDX` reader - DPPI channel that event PERIPHACCERR will publish to"] +pub type CHIDX_R = crate::FieldReader; +#[doc = "Field `CHIDX` writer - DPPI channel that event PERIPHACCERR will publish to"] +pub type CHIDX_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, PUBLISH_PERIPHACCERR_SPEC, u8, u8, 8, O>; +#[doc = "Field `EN` reader - "] +pub type EN_R = crate::BitReader; +#[doc = "\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum EN_A { + #[doc = "0: Disable publishing"] + DISABLED = 0, + #[doc = "1: Enable publishing"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: EN_A) -> Self { + variant as u8 != 0 + } +} +impl EN_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EN_A { + match self.bits { + false => EN_A::DISABLED, + true => EN_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == EN_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == EN_A::ENABLED + } +} +#[doc = "Field `EN` writer - "] +pub type EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, PUBLISH_PERIPHACCERR_SPEC, EN_A, O>; +impl<'a, const O: u8> EN_W<'a, O> { + #[doc = "Disable publishing"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(EN_A::DISABLED) + } + #[doc = "Enable publishing"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(EN_A::ENABLED) + } +} +impl R { + #[doc = "Bits 0:7 - DPPI channel that event PERIPHACCERR will publish to"] + #[inline(always)] + pub fn chidx(&self) -> CHIDX_R { + CHIDX_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&self) -> EN_R { + EN_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:7 - DPPI channel that event PERIPHACCERR will publish to"] + #[inline(always)] + pub fn chidx(&mut self) -> CHIDX_W<0> { + CHIDX_W::new(self) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&mut self) -> EN_W<31> { + EN_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Publish configuration for event PERIPHACCERR\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [publish_periphaccerr](index.html) module"] +pub struct PUBLISH_PERIPHACCERR_SPEC; +impl crate::RegisterSpec for PUBLISH_PERIPHACCERR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [publish_periphaccerr::R](R) reader structure"] +impl crate::Readable for PUBLISH_PERIPHACCERR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [publish_periphaccerr::W](W) writer structure"] +impl crate::Writable for PUBLISH_PERIPHACCERR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PUBLISH_PERIPHACCERR to value 0"] +impl crate::Resettable for PUBLISH_PERIPHACCERR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/spu_s/publish_ramaccerr.rs b/pacs/nrf9120-pac/src/spu_s/publish_ramaccerr.rs new file mode 100644 index 00000000..93c50e75 --- /dev/null +++ b/pacs/nrf9120-pac/src/spu_s/publish_ramaccerr.rs @@ -0,0 +1,141 @@ +#[doc = "Register `PUBLISH_RAMACCERR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PUBLISH_RAMACCERR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CHIDX` reader - DPPI channel that event RAMACCERR will publish to"] +pub type CHIDX_R = crate::FieldReader; +#[doc = "Field `CHIDX` writer - DPPI channel that event RAMACCERR will publish to"] +pub type CHIDX_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, PUBLISH_RAMACCERR_SPEC, u8, u8, 8, O>; +#[doc = "Field `EN` reader - "] +pub type EN_R = crate::BitReader; +#[doc = "\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum EN_A { + #[doc = "0: Disable publishing"] + DISABLED = 0, + #[doc = "1: Enable publishing"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: EN_A) -> Self { + variant as u8 != 0 + } +} +impl EN_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EN_A { + match self.bits { + false => EN_A::DISABLED, + true => EN_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == EN_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == EN_A::ENABLED + } +} +#[doc = "Field `EN` writer - "] +pub type EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, PUBLISH_RAMACCERR_SPEC, EN_A, O>; +impl<'a, const O: u8> EN_W<'a, O> { + #[doc = "Disable publishing"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(EN_A::DISABLED) + } + #[doc = "Enable publishing"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(EN_A::ENABLED) + } +} +impl R { + #[doc = "Bits 0:7 - DPPI channel that event RAMACCERR will publish to"] + #[inline(always)] + pub fn chidx(&self) -> CHIDX_R { + CHIDX_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&self) -> EN_R { + EN_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:7 - DPPI channel that event RAMACCERR will publish to"] + #[inline(always)] + pub fn chidx(&mut self) -> CHIDX_W<0> { + CHIDX_W::new(self) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&mut self) -> EN_W<31> { + EN_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Publish configuration for event RAMACCERR\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [publish_ramaccerr](index.html) module"] +pub struct PUBLISH_RAMACCERR_SPEC; +impl crate::RegisterSpec for PUBLISH_RAMACCERR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [publish_ramaccerr::R](R) reader structure"] +impl crate::Readable for PUBLISH_RAMACCERR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [publish_ramaccerr::W](W) writer structure"] +impl crate::Writable for PUBLISH_RAMACCERR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PUBLISH_RAMACCERR to value 0"] +impl crate::Resettable for PUBLISH_RAMACCERR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/spu_s/ramnsc.rs b/pacs/nrf9120-pac/src/spu_s/ramnsc.rs new file mode 100644 index 00000000..7c04da97 --- /dev/null +++ b/pacs/nrf9120-pac/src/spu_s/ramnsc.rs @@ -0,0 +1,16 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RAMNSC { + #[doc = "0x00 - Description cluster: Define which RAM region can contain the non-secure callable (NSC) region n"] + pub region: REGION, + #[doc = "0x04 - Description cluster: Define the size of the non-secure callable (NSC) region n"] + pub size: SIZE, +} +#[doc = "REGION (rw) register accessor: an alias for `Reg`"] +pub type REGION = crate::Reg; +#[doc = "Description cluster: Define which RAM region can contain the non-secure callable (NSC) region n"] +pub mod region; +#[doc = "SIZE (rw) register accessor: an alias for `Reg`"] +pub type SIZE = crate::Reg; +#[doc = "Description cluster: Define the size of the non-secure callable (NSC) region n"] +pub mod size; diff --git a/pacs/nrf9120-pac/src/spu_s/ramnsc/region.rs b/pacs/nrf9120-pac/src/spu_s/ramnsc/region.rs new file mode 100644 index 00000000..3950ec5f --- /dev/null +++ b/pacs/nrf9120-pac/src/spu_s/ramnsc/region.rs @@ -0,0 +1,140 @@ +#[doc = "Register `REGION` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `REGION` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `REGION` reader - Region number"] +pub type REGION_R = crate::FieldReader; +#[doc = "Field `REGION` writer - Region number"] +pub type REGION_W<'a, const O: u8> = crate::FieldWriter<'a, u32, REGION_SPEC, u8, u8, 5, O>; +#[doc = "Field `LOCK` reader - "] +pub type LOCK_R = crate::BitReader; +#[doc = "\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum LOCK_A { + #[doc = "0: This register can be updated"] + UNLOCKED = 0, + #[doc = "1: The content of this register can't be changed until the next reset"] + LOCKED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: LOCK_A) -> Self { + variant as u8 != 0 + } +} +impl LOCK_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> LOCK_A { + match self.bits { + false => LOCK_A::UNLOCKED, + true => LOCK_A::LOCKED, + } + } + #[doc = "Checks if the value of the field is `UNLOCKED`"] + #[inline(always)] + pub fn is_unlocked(&self) -> bool { + *self == LOCK_A::UNLOCKED + } + #[doc = "Checks if the value of the field is `LOCKED`"] + #[inline(always)] + pub fn is_locked(&self) -> bool { + *self == LOCK_A::LOCKED + } +} +#[doc = "Field `LOCK` writer - "] +pub type LOCK_W<'a, const O: u8> = crate::BitWriter<'a, u32, REGION_SPEC, LOCK_A, O>; +impl<'a, const O: u8> LOCK_W<'a, O> { + #[doc = "This register can be updated"] + #[inline(always)] + pub fn unlocked(self) -> &'a mut W { + self.variant(LOCK_A::UNLOCKED) + } + #[doc = "The content of this register can't be changed until the next reset"] + #[inline(always)] + pub fn locked(self) -> &'a mut W { + self.variant(LOCK_A::LOCKED) + } +} +impl R { + #[doc = "Bits 0:4 - Region number"] + #[inline(always)] + pub fn region(&self) -> REGION_R { + REGION_R::new((self.bits & 0x1f) as u8) + } + #[doc = "Bit 8"] + #[inline(always)] + pub fn lock(&self) -> LOCK_R { + LOCK_R::new(((self.bits >> 8) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:4 - Region number"] + #[inline(always)] + pub fn region(&mut self) -> REGION_W<0> { + REGION_W::new(self) + } + #[doc = "Bit 8"] + #[inline(always)] + pub fn lock(&mut self) -> LOCK_W<8> { + LOCK_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Description cluster: Define which RAM region can contain the non-secure callable (NSC) region n\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [region](index.html) module"] +pub struct REGION_SPEC; +impl crate::RegisterSpec for REGION_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [region::R](R) reader structure"] +impl crate::Readable for REGION_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [region::W](W) writer structure"] +impl crate::Writable for REGION_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets REGION to value 0"] +impl crate::Resettable for REGION_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/spu_s/ramnsc/size.rs b/pacs/nrf9120-pac/src/spu_s/ramnsc/size.rs new file mode 100644 index 00000000..847bc6df --- /dev/null +++ b/pacs/nrf9120-pac/src/spu_s/ramnsc/size.rs @@ -0,0 +1,279 @@ +#[doc = "Register `SIZE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SIZE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SIZE` reader - Size of the non-secure callable (NSC) region n"] +pub type SIZE_R = crate::FieldReader; +#[doc = "Size of the non-secure callable (NSC) region n\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SIZE_A { + #[doc = "0: The region n is not defined as a non-secure callable region. Normal security attributes (secure or non-secure) are enforced."] + DISABLED = 0, + #[doc = "1: The region n is defined as non-secure callable with a 32-byte size"] + _32 = 1, + #[doc = "2: The region n is defined as non-secure callable with a 64-byte size"] + _64 = 2, + #[doc = "3: The region n is defined as non-secure callable with a 128-byte size"] + _128 = 3, + #[doc = "4: The region n is defined as non-secure callable with a 256-byte size"] + _256 = 4, + #[doc = "5: The region n is defined as non-secure callable with a 512-byte size"] + _512 = 5, + #[doc = "6: The region n is defined as non-secure callable with a 1024-byte size"] + _1024 = 6, + #[doc = "7: The region n is defined as non-secure callable with a 2048-byte size"] + _2048 = 7, + #[doc = "8: The region n is defined as non-secure callable with a 4096-byte size"] + _4096 = 8, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SIZE_A) -> Self { + variant as _ + } +} +impl SIZE_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SIZE_A::DISABLED), + 1 => Some(SIZE_A::_32), + 2 => Some(SIZE_A::_64), + 3 => Some(SIZE_A::_128), + 4 => Some(SIZE_A::_256), + 5 => Some(SIZE_A::_512), + 6 => Some(SIZE_A::_1024), + 7 => Some(SIZE_A::_2048), + 8 => Some(SIZE_A::_4096), + _ => None, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == SIZE_A::DISABLED + } + #[doc = "Checks if the value of the field is `_32`"] + #[inline(always)] + pub fn is_32(&self) -> bool { + *self == SIZE_A::_32 + } + #[doc = "Checks if the value of the field is `_64`"] + #[inline(always)] + pub fn is_64(&self) -> bool { + *self == SIZE_A::_64 + } + #[doc = "Checks if the value of the field is `_128`"] + #[inline(always)] + pub fn is_128(&self) -> bool { + *self == SIZE_A::_128 + } + #[doc = "Checks if the value of the field is `_256`"] + #[inline(always)] + pub fn is_256(&self) -> bool { + *self == SIZE_A::_256 + } + #[doc = "Checks if the value of the field is `_512`"] + #[inline(always)] + pub fn is_512(&self) -> bool { + *self == SIZE_A::_512 + } + #[doc = "Checks if the value of the field is `_1024`"] + #[inline(always)] + pub fn is_1024(&self) -> bool { + *self == SIZE_A::_1024 + } + #[doc = "Checks if the value of the field is `_2048`"] + #[inline(always)] + pub fn is_2048(&self) -> bool { + *self == SIZE_A::_2048 + } + #[doc = "Checks if the value of the field is `_4096`"] + #[inline(always)] + pub fn is_4096(&self) -> bool { + *self == SIZE_A::_4096 + } +} +#[doc = "Field `SIZE` writer - Size of the non-secure callable (NSC) region n"] +pub type SIZE_W<'a, const O: u8> = crate::FieldWriter<'a, u32, SIZE_SPEC, u8, SIZE_A, 4, O>; +impl<'a, const O: u8> SIZE_W<'a, O> { + #[doc = "The region n is not defined as a non-secure callable region. Normal security attributes (secure or non-secure) are enforced."] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(SIZE_A::DISABLED) + } + #[doc = "The region n is defined as non-secure callable with a 32-byte size"] + #[inline(always)] + pub fn _32(self) -> &'a mut W { + self.variant(SIZE_A::_32) + } + #[doc = "The region n is defined as non-secure callable with a 64-byte size"] + #[inline(always)] + pub fn _64(self) -> &'a mut W { + self.variant(SIZE_A::_64) + } + #[doc = "The region n is defined as non-secure callable with a 128-byte size"] + #[inline(always)] + pub fn _128(self) -> &'a mut W { + self.variant(SIZE_A::_128) + } + #[doc = "The region n is defined as non-secure callable with a 256-byte size"] + #[inline(always)] + pub fn _256(self) -> &'a mut W { + self.variant(SIZE_A::_256) + } + #[doc = "The region n is defined as non-secure callable with a 512-byte size"] + #[inline(always)] + pub fn _512(self) -> &'a mut W { + self.variant(SIZE_A::_512) + } + #[doc = "The region n is defined as non-secure callable with a 1024-byte size"] + #[inline(always)] + pub fn _1024(self) -> &'a mut W { + self.variant(SIZE_A::_1024) + } + #[doc = "The region n is defined as non-secure callable with a 2048-byte size"] + #[inline(always)] + pub fn _2048(self) -> &'a mut W { + self.variant(SIZE_A::_2048) + } + #[doc = "The region n is defined as non-secure callable with a 4096-byte size"] + #[inline(always)] + pub fn _4096(self) -> &'a mut W { + self.variant(SIZE_A::_4096) + } +} +#[doc = "Field `LOCK` reader - "] +pub type LOCK_R = crate::BitReader; +#[doc = "\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum LOCK_A { + #[doc = "0: This register can be updated"] + UNLOCKED = 0, + #[doc = "1: The content of this register can't be changed until the next reset"] + LOCKED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: LOCK_A) -> Self { + variant as u8 != 0 + } +} +impl LOCK_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> LOCK_A { + match self.bits { + false => LOCK_A::UNLOCKED, + true => LOCK_A::LOCKED, + } + } + #[doc = "Checks if the value of the field is `UNLOCKED`"] + #[inline(always)] + pub fn is_unlocked(&self) -> bool { + *self == LOCK_A::UNLOCKED + } + #[doc = "Checks if the value of the field is `LOCKED`"] + #[inline(always)] + pub fn is_locked(&self) -> bool { + *self == LOCK_A::LOCKED + } +} +#[doc = "Field `LOCK` writer - "] +pub type LOCK_W<'a, const O: u8> = crate::BitWriter<'a, u32, SIZE_SPEC, LOCK_A, O>; +impl<'a, const O: u8> LOCK_W<'a, O> { + #[doc = "This register can be updated"] + #[inline(always)] + pub fn unlocked(self) -> &'a mut W { + self.variant(LOCK_A::UNLOCKED) + } + #[doc = "The content of this register can't be changed until the next reset"] + #[inline(always)] + pub fn locked(self) -> &'a mut W { + self.variant(LOCK_A::LOCKED) + } +} +impl R { + #[doc = "Bits 0:3 - Size of the non-secure callable (NSC) region n"] + #[inline(always)] + pub fn size(&self) -> SIZE_R { + SIZE_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bit 8"] + #[inline(always)] + pub fn lock(&self) -> LOCK_R { + LOCK_R::new(((self.bits >> 8) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:3 - Size of the non-secure callable (NSC) region n"] + #[inline(always)] + pub fn size(&mut self) -> SIZE_W<0> { + SIZE_W::new(self) + } + #[doc = "Bit 8"] + #[inline(always)] + pub fn lock(&mut self) -> LOCK_W<8> { + LOCK_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Description cluster: Define the size of the non-secure callable (NSC) region n\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [size](index.html) module"] +pub struct SIZE_SPEC; +impl crate::RegisterSpec for SIZE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [size::R](R) reader structure"] +impl crate::Readable for SIZE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [size::W](W) writer structure"] +impl crate::Writable for SIZE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SIZE to value 0"] +impl crate::Resettable for SIZE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/spu_s/ramregion.rs b/pacs/nrf9120-pac/src/spu_s/ramregion.rs new file mode 100644 index 00000000..f7ba556d --- /dev/null +++ b/pacs/nrf9120-pac/src/spu_s/ramregion.rs @@ -0,0 +1,10 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RAMREGION { + #[doc = "0x00 - Description cluster: Access permissions for RAM region n"] + pub perm: PERM, +} +#[doc = "PERM (rw) register accessor: an alias for `Reg`"] +pub type PERM = crate::Reg; +#[doc = "Description cluster: Access permissions for RAM region n"] +pub mod perm; diff --git a/pacs/nrf9120-pac/src/spu_s/ramregion/perm.rs b/pacs/nrf9120-pac/src/spu_s/ramregion/perm.rs new file mode 100644 index 00000000..d2b25ebb --- /dev/null +++ b/pacs/nrf9120-pac/src/spu_s/ramregion/perm.rs @@ -0,0 +1,366 @@ +#[doc = "Register `PERM` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PERM` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `EXECUTE` reader - Configure instruction fetch permissions from RAM region n"] +pub type EXECUTE_R = crate::BitReader; +#[doc = "Configure instruction fetch permissions from RAM region n\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum EXECUTE_A { + #[doc = "1: Allow instruction fetches from RAM region n"] + ENABLE = 1, + #[doc = "0: Block instruction fetches from RAM region n"] + DISABLE = 0, +} +impl From for bool { + #[inline(always)] + fn from(variant: EXECUTE_A) -> Self { + variant as u8 != 0 + } +} +impl EXECUTE_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EXECUTE_A { + match self.bits { + true => EXECUTE_A::ENABLE, + false => EXECUTE_A::DISABLE, + } + } + #[doc = "Checks if the value of the field is `ENABLE`"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == EXECUTE_A::ENABLE + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == EXECUTE_A::DISABLE + } +} +#[doc = "Field `EXECUTE` writer - Configure instruction fetch permissions from RAM region n"] +pub type EXECUTE_W<'a, const O: u8> = crate::BitWriter<'a, u32, PERM_SPEC, EXECUTE_A, O>; +impl<'a, const O: u8> EXECUTE_W<'a, O> { + #[doc = "Allow instruction fetches from RAM region n"] + #[inline(always)] + pub fn enable(self) -> &'a mut W { + self.variant(EXECUTE_A::ENABLE) + } + #[doc = "Block instruction fetches from RAM region n"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(EXECUTE_A::DISABLE) + } +} +#[doc = "Field `WRITE` reader - Configure write permission for RAM region n"] +pub type WRITE_R = crate::BitReader; +#[doc = "Configure write permission for RAM region n\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum WRITE_A { + #[doc = "1: Allow write operation to RAM region n"] + ENABLE = 1, + #[doc = "0: Block write operation to RAM region n"] + DISABLE = 0, +} +impl From for bool { + #[inline(always)] + fn from(variant: WRITE_A) -> Self { + variant as u8 != 0 + } +} +impl WRITE_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> WRITE_A { + match self.bits { + true => WRITE_A::ENABLE, + false => WRITE_A::DISABLE, + } + } + #[doc = "Checks if the value of the field is `ENABLE`"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == WRITE_A::ENABLE + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == WRITE_A::DISABLE + } +} +#[doc = "Field `WRITE` writer - Configure write permission for RAM region n"] +pub type WRITE_W<'a, const O: u8> = crate::BitWriter<'a, u32, PERM_SPEC, WRITE_A, O>; +impl<'a, const O: u8> WRITE_W<'a, O> { + #[doc = "Allow write operation to RAM region n"] + #[inline(always)] + pub fn enable(self) -> &'a mut W { + self.variant(WRITE_A::ENABLE) + } + #[doc = "Block write operation to RAM region n"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(WRITE_A::DISABLE) + } +} +#[doc = "Field `READ` reader - Configure read permissions for RAM region n"] +pub type READ_R = crate::BitReader; +#[doc = "Configure read permissions for RAM region n\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum READ_A { + #[doc = "1: Allow read operation from RAM region n"] + ENABLE = 1, + #[doc = "0: Block read operation from RAM region n"] + DISABLE = 0, +} +impl From for bool { + #[inline(always)] + fn from(variant: READ_A) -> Self { + variant as u8 != 0 + } +} +impl READ_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> READ_A { + match self.bits { + true => READ_A::ENABLE, + false => READ_A::DISABLE, + } + } + #[doc = "Checks if the value of the field is `ENABLE`"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == READ_A::ENABLE + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == READ_A::DISABLE + } +} +#[doc = "Field `READ` writer - Configure read permissions for RAM region n"] +pub type READ_W<'a, const O: u8> = crate::BitWriter<'a, u32, PERM_SPEC, READ_A, O>; +impl<'a, const O: u8> READ_W<'a, O> { + #[doc = "Allow read operation from RAM region n"] + #[inline(always)] + pub fn enable(self) -> &'a mut W { + self.variant(READ_A::ENABLE) + } + #[doc = "Block read operation from RAM region n"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(READ_A::DISABLE) + } +} +#[doc = "Field `SECATTR` reader - Security attribute for RAM region n"] +pub type SECATTR_R = crate::BitReader; +#[doc = "Security attribute for RAM region n\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum SECATTR_A { + #[doc = "0: RAM region n security attribute is non-secure"] + NON_SECURE = 0, + #[doc = "1: RAM region n security attribute is secure"] + SECURE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: SECATTR_A) -> Self { + variant as u8 != 0 + } +} +impl SECATTR_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> SECATTR_A { + match self.bits { + false => SECATTR_A::NON_SECURE, + true => SECATTR_A::SECURE, + } + } + #[doc = "Checks if the value of the field is `NON_SECURE`"] + #[inline(always)] + pub fn is_non_secure(&self) -> bool { + *self == SECATTR_A::NON_SECURE + } + #[doc = "Checks if the value of the field is `SECURE`"] + #[inline(always)] + pub fn is_secure(&self) -> bool { + *self == SECATTR_A::SECURE + } +} +#[doc = "Field `SECATTR` writer - Security attribute for RAM region n"] +pub type SECATTR_W<'a, const O: u8> = crate::BitWriter<'a, u32, PERM_SPEC, SECATTR_A, O>; +impl<'a, const O: u8> SECATTR_W<'a, O> { + #[doc = "RAM region n security attribute is non-secure"] + #[inline(always)] + pub fn non_secure(self) -> &'a mut W { + self.variant(SECATTR_A::NON_SECURE) + } + #[doc = "RAM region n security attribute is secure"] + #[inline(always)] + pub fn secure(self) -> &'a mut W { + self.variant(SECATTR_A::SECURE) + } +} +#[doc = "Field `LOCK` reader - "] +pub type LOCK_R = crate::BitReader; +#[doc = "\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum LOCK_A { + #[doc = "0: This register can be updated"] + UNLOCKED = 0, + #[doc = "1: The content of this register can't be changed until the next reset"] + LOCKED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: LOCK_A) -> Self { + variant as u8 != 0 + } +} +impl LOCK_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> LOCK_A { + match self.bits { + false => LOCK_A::UNLOCKED, + true => LOCK_A::LOCKED, + } + } + #[doc = "Checks if the value of the field is `UNLOCKED`"] + #[inline(always)] + pub fn is_unlocked(&self) -> bool { + *self == LOCK_A::UNLOCKED + } + #[doc = "Checks if the value of the field is `LOCKED`"] + #[inline(always)] + pub fn is_locked(&self) -> bool { + *self == LOCK_A::LOCKED + } +} +#[doc = "Field `LOCK` writer - "] +pub type LOCK_W<'a, const O: u8> = crate::BitWriter<'a, u32, PERM_SPEC, LOCK_A, O>; +impl<'a, const O: u8> LOCK_W<'a, O> { + #[doc = "This register can be updated"] + #[inline(always)] + pub fn unlocked(self) -> &'a mut W { + self.variant(LOCK_A::UNLOCKED) + } + #[doc = "The content of this register can't be changed until the next reset"] + #[inline(always)] + pub fn locked(self) -> &'a mut W { + self.variant(LOCK_A::LOCKED) + } +} +impl R { + #[doc = "Bit 0 - Configure instruction fetch permissions from RAM region n"] + #[inline(always)] + pub fn execute(&self) -> EXECUTE_R { + EXECUTE_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Configure write permission for RAM region n"] + #[inline(always)] + pub fn write(&self) -> WRITE_R { + WRITE_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Configure read permissions for RAM region n"] + #[inline(always)] + pub fn read(&self) -> READ_R { + READ_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 4 - Security attribute for RAM region n"] + #[inline(always)] + pub fn secattr(&self) -> SECATTR_R { + SECATTR_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 8"] + #[inline(always)] + pub fn lock(&self) -> LOCK_R { + LOCK_R::new(((self.bits >> 8) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Configure instruction fetch permissions from RAM region n"] + #[inline(always)] + pub fn execute(&mut self) -> EXECUTE_W<0> { + EXECUTE_W::new(self) + } + #[doc = "Bit 1 - Configure write permission for RAM region n"] + #[inline(always)] + pub fn write(&mut self) -> WRITE_W<1> { + WRITE_W::new(self) + } + #[doc = "Bit 2 - Configure read permissions for RAM region n"] + #[inline(always)] + pub fn read(&mut self) -> READ_W<2> { + READ_W::new(self) + } + #[doc = "Bit 4 - Security attribute for RAM region n"] + #[inline(always)] + pub fn secattr(&mut self) -> SECATTR_W<4> { + SECATTR_W::new(self) + } + #[doc = "Bit 8"] + #[inline(always)] + pub fn lock(&mut self) -> LOCK_W<8> { + LOCK_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Description cluster: Access permissions for RAM region n\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [perm](index.html) module"] +pub struct PERM_SPEC; +impl crate::RegisterSpec for PERM_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [perm::R](R) reader structure"] +impl crate::Readable for PERM_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [perm::W](W) writer structure"] +impl crate::Writable for PERM_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PERM to value 0x17"] +impl crate::Resettable for PERM_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x17 + } +} diff --git a/pacs/nrf9120-pac/src/tad_s.rs b/pacs/nrf9120-pac/src/tad_s.rs new file mode 100644 index 00000000..a8169b3f --- /dev/null +++ b/pacs/nrf9120-pac/src/tad_s.rs @@ -0,0 +1,36 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Start all trace and debug clocks."] + pub tasks_clockstart: TASKS_CLOCKSTART, + #[doc = "0x04 - Stop all trace and debug clocks."] + pub tasks_clockstop: TASKS_CLOCKSTOP, + _reserved2: [u8; 0x04f8], + #[doc = "0x500 - Enable debug domain and aquire selected GPIOs"] + pub enable: ENABLE, + #[doc = "0x504..0x518 - Unspecified"] + pub psel: PSEL, + #[doc = "0x518 - Clocking options for the Trace Port debug interface Reset behavior is the same as debug components"] + pub traceportspeed: TRACEPORTSPEED, +} +#[doc = "TASKS_CLOCKSTART (w) register accessor: an alias for `Reg`"] +pub type TASKS_CLOCKSTART = crate::Reg; +#[doc = "Start all trace and debug clocks."] +pub mod tasks_clockstart; +#[doc = "TASKS_CLOCKSTOP (w) register accessor: an alias for `Reg`"] +pub type TASKS_CLOCKSTOP = crate::Reg; +#[doc = "Stop all trace and debug clocks."] +pub mod tasks_clockstop; +#[doc = "ENABLE (rw) register accessor: an alias for `Reg`"] +pub type ENABLE = crate::Reg; +#[doc = "Enable debug domain and aquire selected GPIOs"] +pub mod enable; +#[doc = "Unspecified"] +pub use psel::PSEL; +#[doc = r"Cluster"] +#[doc = "Unspecified"] +pub mod psel; +#[doc = "TRACEPORTSPEED (rw) register accessor: an alias for `Reg`"] +pub type TRACEPORTSPEED = crate::Reg; +#[doc = "Clocking options for the Trace Port debug interface Reset behavior is the same as debug components"] +pub mod traceportspeed; diff --git a/pacs/nrf9120-pac/src/tad_s/enable.rs b/pacs/nrf9120-pac/src/tad_s/enable.rs new file mode 100644 index 00000000..79111223 --- /dev/null +++ b/pacs/nrf9120-pac/src/tad_s/enable.rs @@ -0,0 +1,126 @@ +#[doc = "Register `ENABLE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `ENABLE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ENABLE` reader - "] +pub type ENABLE_R = crate::BitReader; +#[doc = "\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum ENABLE_A { + #[doc = "0: Disable debug domain and release selected GPIOs"] + DISABLED = 0, + #[doc = "1: Enable debug domain and aquire selected GPIOs"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: ENABLE_A) -> Self { + variant as u8 != 0 + } +} +impl ENABLE_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> ENABLE_A { + match self.bits { + false => ENABLE_A::DISABLED, + true => ENABLE_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == ENABLE_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == ENABLE_A::ENABLED + } +} +#[doc = "Field `ENABLE` writer - "] +pub type ENABLE_W<'a, const O: u8> = crate::BitWriter<'a, u32, ENABLE_SPEC, ENABLE_A, O>; +impl<'a, const O: u8> ENABLE_W<'a, O> { + #[doc = "Disable debug domain and release selected GPIOs"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(ENABLE_A::DISABLED) + } + #[doc = "Enable debug domain and aquire selected GPIOs"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(ENABLE_A::ENABLED) + } +} +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new((self.bits & 1) != 0) + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W<0> { + ENABLE_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Enable debug domain and aquire selected GPIOs\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [enable](index.html) module"] +pub struct ENABLE_SPEC; +impl crate::RegisterSpec for ENABLE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [enable::R](R) reader structure"] +impl crate::Readable for ENABLE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [enable::W](W) writer structure"] +impl crate::Writable for ENABLE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets ENABLE to value 0"] +impl crate::Resettable for ENABLE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/tad_s/psel.rs b/pacs/nrf9120-pac/src/tad_s/psel.rs new file mode 100644 index 00000000..44c4cbc5 --- /dev/null +++ b/pacs/nrf9120-pac/src/tad_s/psel.rs @@ -0,0 +1,34 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct PSEL { + #[doc = "0x00 - Pin configuration for TRACECLK"] + pub traceclk: TRACECLK, + #[doc = "0x04 - Pin configuration for TRACEDATA\\[0\\]"] + pub tracedata0: TRACEDATA0, + #[doc = "0x08 - Pin configuration for TRACEDATA\\[1\\]"] + pub tracedata1: TRACEDATA1, + #[doc = "0x0c - Pin configuration for TRACEDATA\\[2\\]"] + pub tracedata2: TRACEDATA2, + #[doc = "0x10 - Pin configuration for TRACEDATA\\[3\\]"] + pub tracedata3: TRACEDATA3, +} +#[doc = "TRACECLK (rw) register accessor: an alias for `Reg`"] +pub type TRACECLK = crate::Reg; +#[doc = "Pin configuration for TRACECLK"] +pub mod traceclk; +#[doc = "TRACEDATA0 (rw) register accessor: an alias for `Reg`"] +pub type TRACEDATA0 = crate::Reg; +#[doc = "Pin configuration for TRACEDATA\\[0\\]"] +pub mod tracedata0; +#[doc = "TRACEDATA1 (rw) register accessor: an alias for `Reg`"] +pub type TRACEDATA1 = crate::Reg; +#[doc = "Pin configuration for TRACEDATA\\[1\\]"] +pub mod tracedata1; +#[doc = "TRACEDATA2 (rw) register accessor: an alias for `Reg`"] +pub type TRACEDATA2 = crate::Reg; +#[doc = "Pin configuration for TRACEDATA\\[2\\]"] +pub mod tracedata2; +#[doc = "TRACEDATA3 (rw) register accessor: an alias for `Reg`"] +pub type TRACEDATA3 = crate::Reg; +#[doc = "Pin configuration for TRACEDATA\\[3\\]"] +pub mod tracedata3; diff --git a/pacs/nrf9120-pac/src/tad_s/psel/traceclk.rs b/pacs/nrf9120-pac/src/tad_s/psel/traceclk.rs new file mode 100644 index 00000000..3c2e21f2 --- /dev/null +++ b/pacs/nrf9120-pac/src/tad_s/psel/traceclk.rs @@ -0,0 +1,175 @@ +#[doc = "Register `TRACECLK` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `TRACECLK` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PIN` reader - Pin number"] +pub type PIN_R = crate::FieldReader; +#[doc = "Pin number\n\nValue on reset: 31"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum PIN_A { + #[doc = "21: TRACECLK pin"] + TRACECLK = 21, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PIN_A) -> Self { + variant as _ + } +} +impl PIN_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 21 => Some(PIN_A::TRACECLK), + _ => None, + } + } + #[doc = "Checks if the value of the field is `TRACECLK`"] + #[inline(always)] + pub fn is_traceclk(&self) -> bool { + *self == PIN_A::TRACECLK + } +} +#[doc = "Field `PIN` writer - Pin number"] +pub type PIN_W<'a, const O: u8> = crate::FieldWriter<'a, u32, TRACECLK_SPEC, u8, PIN_A, 5, O>; +impl<'a, const O: u8> PIN_W<'a, O> { + #[doc = "TRACECLK pin"] + #[inline(always)] + pub fn traceclk(self) -> &'a mut W { + self.variant(PIN_A::TRACECLK) + } +} +#[doc = "Field `CONNECT` reader - Connection"] +pub type CONNECT_R = crate::BitReader; +#[doc = "Connection\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CONNECT_A { + #[doc = "1: Disconnect"] + DISCONNECTED = 1, + #[doc = "0: Connect"] + CONNECTED = 0, +} +impl From for bool { + #[inline(always)] + fn from(variant: CONNECT_A) -> Self { + variant as u8 != 0 + } +} +impl CONNECT_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CONNECT_A { + match self.bits { + true => CONNECT_A::DISCONNECTED, + false => CONNECT_A::CONNECTED, + } + } + #[doc = "Checks if the value of the field is `DISCONNECTED`"] + #[inline(always)] + pub fn is_disconnected(&self) -> bool { + *self == CONNECT_A::DISCONNECTED + } + #[doc = "Checks if the value of the field is `CONNECTED`"] + #[inline(always)] + pub fn is_connected(&self) -> bool { + *self == CONNECT_A::CONNECTED + } +} +#[doc = "Field `CONNECT` writer - Connection"] +pub type CONNECT_W<'a, const O: u8> = crate::BitWriter<'a, u32, TRACECLK_SPEC, CONNECT_A, O>; +impl<'a, const O: u8> CONNECT_W<'a, O> { + #[doc = "Disconnect"] + #[inline(always)] + pub fn disconnected(self) -> &'a mut W { + self.variant(CONNECT_A::DISCONNECTED) + } + #[doc = "Connect"] + #[inline(always)] + pub fn connected(self) -> &'a mut W { + self.variant(CONNECT_A::CONNECTED) + } +} +impl R { + #[doc = "Bits 0:4 - Pin number"] + #[inline(always)] + pub fn pin(&self) -> PIN_R { + PIN_R::new((self.bits & 0x1f) as u8) + } + #[doc = "Bit 31 - Connection"] + #[inline(always)] + pub fn connect(&self) -> CONNECT_R { + CONNECT_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:4 - Pin number"] + #[inline(always)] + pub fn pin(&mut self) -> PIN_W<0> { + PIN_W::new(self) + } + #[doc = "Bit 31 - Connection"] + #[inline(always)] + pub fn connect(&mut self) -> CONNECT_W<31> { + CONNECT_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Pin configuration for TRACECLK\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [traceclk](index.html) module"] +pub struct TRACECLK_SPEC; +impl crate::RegisterSpec for TRACECLK_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [traceclk::R](R) reader structure"] +impl crate::Readable for TRACECLK_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [traceclk::W](W) writer structure"] +impl crate::Writable for TRACECLK_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets TRACECLK to value 0xffff_ffff"] +impl crate::Resettable for TRACECLK_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0xffff_ffff + } +} diff --git a/pacs/nrf9120-pac/src/tad_s/psel/tracedata0.rs b/pacs/nrf9120-pac/src/tad_s/psel/tracedata0.rs new file mode 100644 index 00000000..1734ffae --- /dev/null +++ b/pacs/nrf9120-pac/src/tad_s/psel/tracedata0.rs @@ -0,0 +1,175 @@ +#[doc = "Register `TRACEDATA0` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `TRACEDATA0` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PIN` reader - Pin number"] +pub type PIN_R = crate::FieldReader; +#[doc = "Pin number\n\nValue on reset: 31"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum PIN_A { + #[doc = "22: TRACEDATA0 pin"] + TRACEDATA0 = 22, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PIN_A) -> Self { + variant as _ + } +} +impl PIN_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 22 => Some(PIN_A::TRACEDATA0), + _ => None, + } + } + #[doc = "Checks if the value of the field is `TRACEDATA0`"] + #[inline(always)] + pub fn is_tracedata0(&self) -> bool { + *self == PIN_A::TRACEDATA0 + } +} +#[doc = "Field `PIN` writer - Pin number"] +pub type PIN_W<'a, const O: u8> = crate::FieldWriter<'a, u32, TRACEDATA0_SPEC, u8, PIN_A, 5, O>; +impl<'a, const O: u8> PIN_W<'a, O> { + #[doc = "TRACEDATA0 pin"] + #[inline(always)] + pub fn tracedata0(self) -> &'a mut W { + self.variant(PIN_A::TRACEDATA0) + } +} +#[doc = "Field `CONNECT` reader - Connection"] +pub type CONNECT_R = crate::BitReader; +#[doc = "Connection\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CONNECT_A { + #[doc = "1: Disconnect"] + DISCONNECTED = 1, + #[doc = "0: Connect"] + CONNECTED = 0, +} +impl From for bool { + #[inline(always)] + fn from(variant: CONNECT_A) -> Self { + variant as u8 != 0 + } +} +impl CONNECT_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CONNECT_A { + match self.bits { + true => CONNECT_A::DISCONNECTED, + false => CONNECT_A::CONNECTED, + } + } + #[doc = "Checks if the value of the field is `DISCONNECTED`"] + #[inline(always)] + pub fn is_disconnected(&self) -> bool { + *self == CONNECT_A::DISCONNECTED + } + #[doc = "Checks if the value of the field is `CONNECTED`"] + #[inline(always)] + pub fn is_connected(&self) -> bool { + *self == CONNECT_A::CONNECTED + } +} +#[doc = "Field `CONNECT` writer - Connection"] +pub type CONNECT_W<'a, const O: u8> = crate::BitWriter<'a, u32, TRACEDATA0_SPEC, CONNECT_A, O>; +impl<'a, const O: u8> CONNECT_W<'a, O> { + #[doc = "Disconnect"] + #[inline(always)] + pub fn disconnected(self) -> &'a mut W { + self.variant(CONNECT_A::DISCONNECTED) + } + #[doc = "Connect"] + #[inline(always)] + pub fn connected(self) -> &'a mut W { + self.variant(CONNECT_A::CONNECTED) + } +} +impl R { + #[doc = "Bits 0:4 - Pin number"] + #[inline(always)] + pub fn pin(&self) -> PIN_R { + PIN_R::new((self.bits & 0x1f) as u8) + } + #[doc = "Bit 31 - Connection"] + #[inline(always)] + pub fn connect(&self) -> CONNECT_R { + CONNECT_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:4 - Pin number"] + #[inline(always)] + pub fn pin(&mut self) -> PIN_W<0> { + PIN_W::new(self) + } + #[doc = "Bit 31 - Connection"] + #[inline(always)] + pub fn connect(&mut self) -> CONNECT_W<31> { + CONNECT_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Pin configuration for TRACEDATA\\[0\\]\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tracedata0](index.html) module"] +pub struct TRACEDATA0_SPEC; +impl crate::RegisterSpec for TRACEDATA0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [tracedata0::R](R) reader structure"] +impl crate::Readable for TRACEDATA0_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [tracedata0::W](W) writer structure"] +impl crate::Writable for TRACEDATA0_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets TRACEDATA0 to value 0xffff_ffff"] +impl crate::Resettable for TRACEDATA0_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0xffff_ffff + } +} diff --git a/pacs/nrf9120-pac/src/tad_s/psel/tracedata1.rs b/pacs/nrf9120-pac/src/tad_s/psel/tracedata1.rs new file mode 100644 index 00000000..10b81d6f --- /dev/null +++ b/pacs/nrf9120-pac/src/tad_s/psel/tracedata1.rs @@ -0,0 +1,175 @@ +#[doc = "Register `TRACEDATA1` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `TRACEDATA1` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PIN` reader - Pin number"] +pub type PIN_R = crate::FieldReader; +#[doc = "Pin number\n\nValue on reset: 31"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum PIN_A { + #[doc = "23: TRACEDATA1 pin"] + TRACEDATA1 = 23, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PIN_A) -> Self { + variant as _ + } +} +impl PIN_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 23 => Some(PIN_A::TRACEDATA1), + _ => None, + } + } + #[doc = "Checks if the value of the field is `TRACEDATA1`"] + #[inline(always)] + pub fn is_tracedata1(&self) -> bool { + *self == PIN_A::TRACEDATA1 + } +} +#[doc = "Field `PIN` writer - Pin number"] +pub type PIN_W<'a, const O: u8> = crate::FieldWriter<'a, u32, TRACEDATA1_SPEC, u8, PIN_A, 5, O>; +impl<'a, const O: u8> PIN_W<'a, O> { + #[doc = "TRACEDATA1 pin"] + #[inline(always)] + pub fn tracedata1(self) -> &'a mut W { + self.variant(PIN_A::TRACEDATA1) + } +} +#[doc = "Field `CONNECT` reader - Connection"] +pub type CONNECT_R = crate::BitReader; +#[doc = "Connection\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CONNECT_A { + #[doc = "1: Disconnect"] + DISCONNECTED = 1, + #[doc = "0: Connect"] + CONNECTED = 0, +} +impl From for bool { + #[inline(always)] + fn from(variant: CONNECT_A) -> Self { + variant as u8 != 0 + } +} +impl CONNECT_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CONNECT_A { + match self.bits { + true => CONNECT_A::DISCONNECTED, + false => CONNECT_A::CONNECTED, + } + } + #[doc = "Checks if the value of the field is `DISCONNECTED`"] + #[inline(always)] + pub fn is_disconnected(&self) -> bool { + *self == CONNECT_A::DISCONNECTED + } + #[doc = "Checks if the value of the field is `CONNECTED`"] + #[inline(always)] + pub fn is_connected(&self) -> bool { + *self == CONNECT_A::CONNECTED + } +} +#[doc = "Field `CONNECT` writer - Connection"] +pub type CONNECT_W<'a, const O: u8> = crate::BitWriter<'a, u32, TRACEDATA1_SPEC, CONNECT_A, O>; +impl<'a, const O: u8> CONNECT_W<'a, O> { + #[doc = "Disconnect"] + #[inline(always)] + pub fn disconnected(self) -> &'a mut W { + self.variant(CONNECT_A::DISCONNECTED) + } + #[doc = "Connect"] + #[inline(always)] + pub fn connected(self) -> &'a mut W { + self.variant(CONNECT_A::CONNECTED) + } +} +impl R { + #[doc = "Bits 0:4 - Pin number"] + #[inline(always)] + pub fn pin(&self) -> PIN_R { + PIN_R::new((self.bits & 0x1f) as u8) + } + #[doc = "Bit 31 - Connection"] + #[inline(always)] + pub fn connect(&self) -> CONNECT_R { + CONNECT_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:4 - Pin number"] + #[inline(always)] + pub fn pin(&mut self) -> PIN_W<0> { + PIN_W::new(self) + } + #[doc = "Bit 31 - Connection"] + #[inline(always)] + pub fn connect(&mut self) -> CONNECT_W<31> { + CONNECT_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Pin configuration for TRACEDATA\\[1\\]\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tracedata1](index.html) module"] +pub struct TRACEDATA1_SPEC; +impl crate::RegisterSpec for TRACEDATA1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [tracedata1::R](R) reader structure"] +impl crate::Readable for TRACEDATA1_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [tracedata1::W](W) writer structure"] +impl crate::Writable for TRACEDATA1_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets TRACEDATA1 to value 0xffff_ffff"] +impl crate::Resettable for TRACEDATA1_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0xffff_ffff + } +} diff --git a/pacs/nrf9120-pac/src/tad_s/psel/tracedata2.rs b/pacs/nrf9120-pac/src/tad_s/psel/tracedata2.rs new file mode 100644 index 00000000..8f04f9ca --- /dev/null +++ b/pacs/nrf9120-pac/src/tad_s/psel/tracedata2.rs @@ -0,0 +1,175 @@ +#[doc = "Register `TRACEDATA2` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `TRACEDATA2` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PIN` reader - Pin number"] +pub type PIN_R = crate::FieldReader; +#[doc = "Pin number\n\nValue on reset: 31"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum PIN_A { + #[doc = "24: TRACEDATA2 pin"] + TRACEDATA2 = 24, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PIN_A) -> Self { + variant as _ + } +} +impl PIN_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 24 => Some(PIN_A::TRACEDATA2), + _ => None, + } + } + #[doc = "Checks if the value of the field is `TRACEDATA2`"] + #[inline(always)] + pub fn is_tracedata2(&self) -> bool { + *self == PIN_A::TRACEDATA2 + } +} +#[doc = "Field `PIN` writer - Pin number"] +pub type PIN_W<'a, const O: u8> = crate::FieldWriter<'a, u32, TRACEDATA2_SPEC, u8, PIN_A, 5, O>; +impl<'a, const O: u8> PIN_W<'a, O> { + #[doc = "TRACEDATA2 pin"] + #[inline(always)] + pub fn tracedata2(self) -> &'a mut W { + self.variant(PIN_A::TRACEDATA2) + } +} +#[doc = "Field `CONNECT` reader - Connection"] +pub type CONNECT_R = crate::BitReader; +#[doc = "Connection\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CONNECT_A { + #[doc = "1: Disconnect"] + DISCONNECTED = 1, + #[doc = "0: Connect"] + CONNECTED = 0, +} +impl From for bool { + #[inline(always)] + fn from(variant: CONNECT_A) -> Self { + variant as u8 != 0 + } +} +impl CONNECT_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CONNECT_A { + match self.bits { + true => CONNECT_A::DISCONNECTED, + false => CONNECT_A::CONNECTED, + } + } + #[doc = "Checks if the value of the field is `DISCONNECTED`"] + #[inline(always)] + pub fn is_disconnected(&self) -> bool { + *self == CONNECT_A::DISCONNECTED + } + #[doc = "Checks if the value of the field is `CONNECTED`"] + #[inline(always)] + pub fn is_connected(&self) -> bool { + *self == CONNECT_A::CONNECTED + } +} +#[doc = "Field `CONNECT` writer - Connection"] +pub type CONNECT_W<'a, const O: u8> = crate::BitWriter<'a, u32, TRACEDATA2_SPEC, CONNECT_A, O>; +impl<'a, const O: u8> CONNECT_W<'a, O> { + #[doc = "Disconnect"] + #[inline(always)] + pub fn disconnected(self) -> &'a mut W { + self.variant(CONNECT_A::DISCONNECTED) + } + #[doc = "Connect"] + #[inline(always)] + pub fn connected(self) -> &'a mut W { + self.variant(CONNECT_A::CONNECTED) + } +} +impl R { + #[doc = "Bits 0:4 - Pin number"] + #[inline(always)] + pub fn pin(&self) -> PIN_R { + PIN_R::new((self.bits & 0x1f) as u8) + } + #[doc = "Bit 31 - Connection"] + #[inline(always)] + pub fn connect(&self) -> CONNECT_R { + CONNECT_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:4 - Pin number"] + #[inline(always)] + pub fn pin(&mut self) -> PIN_W<0> { + PIN_W::new(self) + } + #[doc = "Bit 31 - Connection"] + #[inline(always)] + pub fn connect(&mut self) -> CONNECT_W<31> { + CONNECT_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Pin configuration for TRACEDATA\\[2\\]\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tracedata2](index.html) module"] +pub struct TRACEDATA2_SPEC; +impl crate::RegisterSpec for TRACEDATA2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [tracedata2::R](R) reader structure"] +impl crate::Readable for TRACEDATA2_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [tracedata2::W](W) writer structure"] +impl crate::Writable for TRACEDATA2_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets TRACEDATA2 to value 0xffff_ffff"] +impl crate::Resettable for TRACEDATA2_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0xffff_ffff + } +} diff --git a/pacs/nrf9120-pac/src/tad_s/psel/tracedata3.rs b/pacs/nrf9120-pac/src/tad_s/psel/tracedata3.rs new file mode 100644 index 00000000..73792c49 --- /dev/null +++ b/pacs/nrf9120-pac/src/tad_s/psel/tracedata3.rs @@ -0,0 +1,175 @@ +#[doc = "Register `TRACEDATA3` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `TRACEDATA3` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PIN` reader - Pin number"] +pub type PIN_R = crate::FieldReader; +#[doc = "Pin number\n\nValue on reset: 31"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum PIN_A { + #[doc = "25: TRACEDATA3 pin"] + TRACEDATA3 = 25, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PIN_A) -> Self { + variant as _ + } +} +impl PIN_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 25 => Some(PIN_A::TRACEDATA3), + _ => None, + } + } + #[doc = "Checks if the value of the field is `TRACEDATA3`"] + #[inline(always)] + pub fn is_tracedata3(&self) -> bool { + *self == PIN_A::TRACEDATA3 + } +} +#[doc = "Field `PIN` writer - Pin number"] +pub type PIN_W<'a, const O: u8> = crate::FieldWriter<'a, u32, TRACEDATA3_SPEC, u8, PIN_A, 5, O>; +impl<'a, const O: u8> PIN_W<'a, O> { + #[doc = "TRACEDATA3 pin"] + #[inline(always)] + pub fn tracedata3(self) -> &'a mut W { + self.variant(PIN_A::TRACEDATA3) + } +} +#[doc = "Field `CONNECT` reader - Connection"] +pub type CONNECT_R = crate::BitReader; +#[doc = "Connection\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CONNECT_A { + #[doc = "1: Disconnect"] + DISCONNECTED = 1, + #[doc = "0: Connect"] + CONNECTED = 0, +} +impl From for bool { + #[inline(always)] + fn from(variant: CONNECT_A) -> Self { + variant as u8 != 0 + } +} +impl CONNECT_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CONNECT_A { + match self.bits { + true => CONNECT_A::DISCONNECTED, + false => CONNECT_A::CONNECTED, + } + } + #[doc = "Checks if the value of the field is `DISCONNECTED`"] + #[inline(always)] + pub fn is_disconnected(&self) -> bool { + *self == CONNECT_A::DISCONNECTED + } + #[doc = "Checks if the value of the field is `CONNECTED`"] + #[inline(always)] + pub fn is_connected(&self) -> bool { + *self == CONNECT_A::CONNECTED + } +} +#[doc = "Field `CONNECT` writer - Connection"] +pub type CONNECT_W<'a, const O: u8> = crate::BitWriter<'a, u32, TRACEDATA3_SPEC, CONNECT_A, O>; +impl<'a, const O: u8> CONNECT_W<'a, O> { + #[doc = "Disconnect"] + #[inline(always)] + pub fn disconnected(self) -> &'a mut W { + self.variant(CONNECT_A::DISCONNECTED) + } + #[doc = "Connect"] + #[inline(always)] + pub fn connected(self) -> &'a mut W { + self.variant(CONNECT_A::CONNECTED) + } +} +impl R { + #[doc = "Bits 0:4 - Pin number"] + #[inline(always)] + pub fn pin(&self) -> PIN_R { + PIN_R::new((self.bits & 0x1f) as u8) + } + #[doc = "Bit 31 - Connection"] + #[inline(always)] + pub fn connect(&self) -> CONNECT_R { + CONNECT_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:4 - Pin number"] + #[inline(always)] + pub fn pin(&mut self) -> PIN_W<0> { + PIN_W::new(self) + } + #[doc = "Bit 31 - Connection"] + #[inline(always)] + pub fn connect(&mut self) -> CONNECT_W<31> { + CONNECT_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Pin configuration for TRACEDATA\\[3\\]\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tracedata3](index.html) module"] +pub struct TRACEDATA3_SPEC; +impl crate::RegisterSpec for TRACEDATA3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [tracedata3::R](R) reader structure"] +impl crate::Readable for TRACEDATA3_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [tracedata3::W](W) writer structure"] +impl crate::Writable for TRACEDATA3_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets TRACEDATA3 to value 0xffff_ffff"] +impl crate::Resettable for TRACEDATA3_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0xffff_ffff + } +} diff --git a/pacs/nrf9120-pac/src/tad_s/tasks_clockstart.rs b/pacs/nrf9120-pac/src/tad_s/tasks_clockstart.rs new file mode 100644 index 00000000..b900d6f7 --- /dev/null +++ b/pacs/nrf9120-pac/src/tad_s/tasks_clockstart.rs @@ -0,0 +1,72 @@ +#[doc = "Register `TASKS_CLOCKSTART` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Start all trace and debug clocks.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum TASKS_CLOCKSTART_AW { + #[doc = "1: Trigger task"] + TRIGGER = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TASKS_CLOCKSTART_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TASKS_CLOCKSTART` writer - Start all trace and debug clocks."] +pub type TASKS_CLOCKSTART_W<'a, const O: u8> = + crate::BitWriter<'a, u32, TASKS_CLOCKSTART_SPEC, TASKS_CLOCKSTART_AW, O>; +impl<'a, const O: u8> TASKS_CLOCKSTART_W<'a, O> { + #[doc = "Trigger task"] + #[inline(always)] + pub fn trigger(self) -> &'a mut W { + self.variant(TASKS_CLOCKSTART_AW::TRIGGER) + } +} +impl W { + #[doc = "Bit 0 - Start all trace and debug clocks."] + #[inline(always)] + pub fn tasks_clockstart(&mut self) -> TASKS_CLOCKSTART_W<0> { + TASKS_CLOCKSTART_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Start all trace and debug clocks.\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tasks_clockstart](index.html) module"] +pub struct TASKS_CLOCKSTART_SPEC; +impl crate::RegisterSpec for TASKS_CLOCKSTART_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [tasks_clockstart::W](W) writer structure"] +impl crate::Writable for TASKS_CLOCKSTART_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets TASKS_CLOCKSTART to value 0"] +impl crate::Resettable for TASKS_CLOCKSTART_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/tad_s/tasks_clockstop.rs b/pacs/nrf9120-pac/src/tad_s/tasks_clockstop.rs new file mode 100644 index 00000000..e854a58a --- /dev/null +++ b/pacs/nrf9120-pac/src/tad_s/tasks_clockstop.rs @@ -0,0 +1,72 @@ +#[doc = "Register `TASKS_CLOCKSTOP` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Stop all trace and debug clocks.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum TASKS_CLOCKSTOP_AW { + #[doc = "1: Trigger task"] + TRIGGER = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TASKS_CLOCKSTOP_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TASKS_CLOCKSTOP` writer - Stop all trace and debug clocks."] +pub type TASKS_CLOCKSTOP_W<'a, const O: u8> = + crate::BitWriter<'a, u32, TASKS_CLOCKSTOP_SPEC, TASKS_CLOCKSTOP_AW, O>; +impl<'a, const O: u8> TASKS_CLOCKSTOP_W<'a, O> { + #[doc = "Trigger task"] + #[inline(always)] + pub fn trigger(self) -> &'a mut W { + self.variant(TASKS_CLOCKSTOP_AW::TRIGGER) + } +} +impl W { + #[doc = "Bit 0 - Stop all trace and debug clocks."] + #[inline(always)] + pub fn tasks_clockstop(&mut self) -> TASKS_CLOCKSTOP_W<0> { + TASKS_CLOCKSTOP_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Stop all trace and debug clocks.\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tasks_clockstop](index.html) module"] +pub struct TASKS_CLOCKSTOP_SPEC; +impl crate::RegisterSpec for TASKS_CLOCKSTOP_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [tasks_clockstop::W](W) writer structure"] +impl crate::Writable for TASKS_CLOCKSTOP_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets TASKS_CLOCKSTOP to value 0"] +impl crate::Resettable for TASKS_CLOCKSTOP_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/tad_s/traceportspeed.rs b/pacs/nrf9120-pac/src/tad_s/traceportspeed.rs new file mode 100644 index 00000000..d219faf0 --- /dev/null +++ b/pacs/nrf9120-pac/src/tad_s/traceportspeed.rs @@ -0,0 +1,155 @@ +#[doc = "Register `TRACEPORTSPEED` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `TRACEPORTSPEED` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `TRACEPORTSPEED` reader - Speed of Trace Port clock. Note that the TRACECLK pin output will be divided again by two from the Trace Port clock."] +pub type TRACEPORTSPEED_R = crate::FieldReader; +#[doc = "Speed of Trace Port clock. Note that the TRACECLK pin output will be divided again by two from the Trace Port clock.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum TRACEPORTSPEED_A { + #[doc = "0: Trace Port clock is: 32MHz"] + _32MHZ = 0, + #[doc = "1: Trace Port clock is: 16MHz"] + _16MHZ = 1, + #[doc = "2: Trace Port clock is: 8MHz"] + _8MHZ = 2, + #[doc = "3: Trace Port clock is: 4MHz"] + _4MHZ = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: TRACEPORTSPEED_A) -> Self { + variant as _ + } +} +impl TRACEPORTSPEED_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> TRACEPORTSPEED_A { + match self.bits { + 0 => TRACEPORTSPEED_A::_32MHZ, + 1 => TRACEPORTSPEED_A::_16MHZ, + 2 => TRACEPORTSPEED_A::_8MHZ, + 3 => TRACEPORTSPEED_A::_4MHZ, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `_32MHZ`"] + #[inline(always)] + pub fn is_32mhz(&self) -> bool { + *self == TRACEPORTSPEED_A::_32MHZ + } + #[doc = "Checks if the value of the field is `_16MHZ`"] + #[inline(always)] + pub fn is_16mhz(&self) -> bool { + *self == TRACEPORTSPEED_A::_16MHZ + } + #[doc = "Checks if the value of the field is `_8MHZ`"] + #[inline(always)] + pub fn is_8mhz(&self) -> bool { + *self == TRACEPORTSPEED_A::_8MHZ + } + #[doc = "Checks if the value of the field is `_4MHZ`"] + #[inline(always)] + pub fn is_4mhz(&self) -> bool { + *self == TRACEPORTSPEED_A::_4MHZ + } +} +#[doc = "Field `TRACEPORTSPEED` writer - Speed of Trace Port clock. Note that the TRACECLK pin output will be divided again by two from the Trace Port clock."] +pub type TRACEPORTSPEED_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u32, TRACEPORTSPEED_SPEC, u8, TRACEPORTSPEED_A, 2, O>; +impl<'a, const O: u8> TRACEPORTSPEED_W<'a, O> { + #[doc = "Trace Port clock is: 32MHz"] + #[inline(always)] + pub fn _32mhz(self) -> &'a mut W { + self.variant(TRACEPORTSPEED_A::_32MHZ) + } + #[doc = "Trace Port clock is: 16MHz"] + #[inline(always)] + pub fn _16mhz(self) -> &'a mut W { + self.variant(TRACEPORTSPEED_A::_16MHZ) + } + #[doc = "Trace Port clock is: 8MHz"] + #[inline(always)] + pub fn _8mhz(self) -> &'a mut W { + self.variant(TRACEPORTSPEED_A::_8MHZ) + } + #[doc = "Trace Port clock is: 4MHz"] + #[inline(always)] + pub fn _4mhz(self) -> &'a mut W { + self.variant(TRACEPORTSPEED_A::_4MHZ) + } +} +impl R { + #[doc = "Bits 0:1 - Speed of Trace Port clock. Note that the TRACECLK pin output will be divided again by two from the Trace Port clock."] + #[inline(always)] + pub fn traceportspeed(&self) -> TRACEPORTSPEED_R { + TRACEPORTSPEED_R::new((self.bits & 3) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Speed of Trace Port clock. Note that the TRACECLK pin output will be divided again by two from the Trace Port clock."] + #[inline(always)] + pub fn traceportspeed(&mut self) -> TRACEPORTSPEED_W<0> { + TRACEPORTSPEED_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Clocking options for the Trace Port debug interface Reset behavior is the same as debug components\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [traceportspeed](index.html) module"] +pub struct TRACEPORTSPEED_SPEC; +impl crate::RegisterSpec for TRACEPORTSPEED_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [traceportspeed::R](R) reader structure"] +impl crate::Readable for TRACEPORTSPEED_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [traceportspeed::W](W) writer structure"] +impl crate::Writable for TRACEPORTSPEED_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets TRACEPORTSPEED to value 0"] +impl crate::Resettable for TRACEPORTSPEED_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/timer0_ns.rs b/pacs/nrf9120-pac/src/timer0_ns.rs new file mode 100644 index 00000000..4dea4b48 --- /dev/null +++ b/pacs/nrf9120-pac/src/timer0_ns.rs @@ -0,0 +1,150 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Start Timer"] + pub tasks_start: TASKS_START, + #[doc = "0x04 - Stop Timer"] + pub tasks_stop: TASKS_STOP, + #[doc = "0x08 - Increment Timer (Counter mode only)"] + pub tasks_count: TASKS_COUNT, + #[doc = "0x0c - Clear time"] + pub tasks_clear: TASKS_CLEAR, + #[doc = "0x10 - Deprecated register - Shut down timer"] + pub tasks_shutdown: TASKS_SHUTDOWN, + _reserved5: [u8; 0x2c], + #[doc = "0x40..0x58 - Description collection: Capture Timer value to CC\\[n\\] +register"] + pub tasks_capture: [TASKS_CAPTURE; 6], + _reserved6: [u8; 0x28], + #[doc = "0x80 - Subscribe configuration for task START"] + pub subscribe_start: SUBSCRIBE_START, + #[doc = "0x84 - Subscribe configuration for task STOP"] + pub subscribe_stop: SUBSCRIBE_STOP, + #[doc = "0x88 - Subscribe configuration for task COUNT"] + pub subscribe_count: SUBSCRIBE_COUNT, + #[doc = "0x8c - Subscribe configuration for task CLEAR"] + pub subscribe_clear: SUBSCRIBE_CLEAR, + #[doc = "0x90 - Deprecated register - Subscribe configuration for task SHUTDOWN"] + pub subscribe_shutdown: SUBSCRIBE_SHUTDOWN, + _reserved11: [u8; 0x2c], + #[doc = "0xc0..0xd8 - Description collection: Subscribe configuration for task CAPTURE\\[n\\]"] + pub subscribe_capture: [SUBSCRIBE_CAPTURE; 6], + _reserved12: [u8; 0x68], + #[doc = "0x140..0x158 - Description collection: Compare event on CC\\[n\\] +match"] + pub events_compare: [EVENTS_COMPARE; 6], + _reserved13: [u8; 0x68], + #[doc = "0x1c0..0x1d8 - Description collection: Publish configuration for event COMPARE\\[n\\]"] + pub publish_compare: [PUBLISH_COMPARE; 6], + _reserved14: [u8; 0x28], + #[doc = "0x200 - Shortcuts between local events and tasks"] + pub shorts: SHORTS, + _reserved15: [u8; 0x0100], + #[doc = "0x304 - Enable interrupt"] + pub intenset: INTENSET, + #[doc = "0x308 - Disable interrupt"] + pub intenclr: INTENCLR, + _reserved17: [u8; 0x01f8], + #[doc = "0x504 - Timer mode selection"] + pub mode: MODE, + #[doc = "0x508 - Configure the number of bits used by the TIMER"] + pub bitmode: BITMODE, + _reserved19: [u8; 0x04], + #[doc = "0x510 - Timer prescaler register"] + pub prescaler: PRESCALER, + #[doc = "0x514..0x52c - Description collection: Enable one-shot operation for Capture/Compare channel n"] + pub oneshoten: [ONESHOTEN; 6], + _reserved21: [u8; 0x14], + #[doc = "0x540..0x558 - Description collection: Capture/Compare register n"] + pub cc: [CC; 6], +} +#[doc = "TASKS_START (w) register accessor: an alias for `Reg`"] +pub type TASKS_START = crate::Reg; +#[doc = "Start Timer"] +pub mod tasks_start; +#[doc = "TASKS_STOP (w) register accessor: an alias for `Reg`"] +pub type TASKS_STOP = crate::Reg; +#[doc = "Stop Timer"] +pub mod tasks_stop; +#[doc = "TASKS_COUNT (w) register accessor: an alias for `Reg`"] +pub type TASKS_COUNT = crate::Reg; +#[doc = "Increment Timer (Counter mode only)"] +pub mod tasks_count; +#[doc = "TASKS_CLEAR (w) register accessor: an alias for `Reg`"] +pub type TASKS_CLEAR = crate::Reg; +#[doc = "Clear time"] +pub mod tasks_clear; +#[doc = "TASKS_SHUTDOWN (w) register accessor: an alias for `Reg`"] +pub type TASKS_SHUTDOWN = crate::Reg; +#[doc = "Deprecated register - Shut down timer"] +pub mod tasks_shutdown; +#[doc = "TASKS_CAPTURE (w) register accessor: an alias for `Reg`"] +pub type TASKS_CAPTURE = crate::Reg; +#[doc = "Description collection: Capture Timer value to CC\\[n\\] +register"] +pub mod tasks_capture; +#[doc = "SUBSCRIBE_START (rw) register accessor: an alias for `Reg`"] +pub type SUBSCRIBE_START = crate::Reg; +#[doc = "Subscribe configuration for task START"] +pub mod subscribe_start; +#[doc = "SUBSCRIBE_STOP (rw) register accessor: an alias for `Reg`"] +pub type SUBSCRIBE_STOP = crate::Reg; +#[doc = "Subscribe configuration for task STOP"] +pub mod subscribe_stop; +#[doc = "SUBSCRIBE_COUNT (rw) register accessor: an alias for `Reg`"] +pub type SUBSCRIBE_COUNT = crate::Reg; +#[doc = "Subscribe configuration for task COUNT"] +pub mod subscribe_count; +#[doc = "SUBSCRIBE_CLEAR (rw) register accessor: an alias for `Reg`"] +pub type SUBSCRIBE_CLEAR = crate::Reg; +#[doc = "Subscribe configuration for task CLEAR"] +pub mod subscribe_clear; +#[doc = "SUBSCRIBE_SHUTDOWN (rw) register accessor: an alias for `Reg`"] +pub type SUBSCRIBE_SHUTDOWN = crate::Reg; +#[doc = "Deprecated register - Subscribe configuration for task SHUTDOWN"] +pub mod subscribe_shutdown; +#[doc = "SUBSCRIBE_CAPTURE (rw) register accessor: an alias for `Reg`"] +pub type SUBSCRIBE_CAPTURE = crate::Reg; +#[doc = "Description collection: Subscribe configuration for task CAPTURE\\[n\\]"] +pub mod subscribe_capture; +#[doc = "EVENTS_COMPARE (rw) register accessor: an alias for `Reg`"] +pub type EVENTS_COMPARE = crate::Reg; +#[doc = "Description collection: Compare event on CC\\[n\\] +match"] +pub mod events_compare; +#[doc = "PUBLISH_COMPARE (rw) register accessor: an alias for `Reg`"] +pub type PUBLISH_COMPARE = crate::Reg; +#[doc = "Description collection: Publish configuration for event COMPARE\\[n\\]"] +pub mod publish_compare; +#[doc = "SHORTS (rw) register accessor: an alias for `Reg`"] +pub type SHORTS = crate::Reg; +#[doc = "Shortcuts between local events and tasks"] +pub mod shorts; +#[doc = "INTENSET (rw) register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "Enable interrupt"] +pub mod intenset; +#[doc = "INTENCLR (rw) register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "Disable interrupt"] +pub mod intenclr; +#[doc = "MODE (rw) register accessor: an alias for `Reg`"] +pub type MODE = crate::Reg; +#[doc = "Timer mode selection"] +pub mod mode; +#[doc = "BITMODE (rw) register accessor: an alias for `Reg`"] +pub type BITMODE = crate::Reg; +#[doc = "Configure the number of bits used by the TIMER"] +pub mod bitmode; +#[doc = "PRESCALER (rw) register accessor: an alias for `Reg`"] +pub type PRESCALER = crate::Reg; +#[doc = "Timer prescaler register"] +pub mod prescaler; +#[doc = "ONESHOTEN (rw) register accessor: an alias for `Reg`"] +pub type ONESHOTEN = crate::Reg; +#[doc = "Description collection: Enable one-shot operation for Capture/Compare channel n"] +pub mod oneshoten; +#[doc = "CC (rw) register accessor: an alias for `Reg`"] +pub type CC = crate::Reg; +#[doc = "Description collection: Capture/Compare register n"] +pub mod cc; diff --git a/pacs/nrf9120-pac/src/timer0_ns/bitmode.rs b/pacs/nrf9120-pac/src/timer0_ns/bitmode.rs new file mode 100644 index 00000000..bad4446e --- /dev/null +++ b/pacs/nrf9120-pac/src/timer0_ns/bitmode.rs @@ -0,0 +1,155 @@ +#[doc = "Register `BITMODE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `BITMODE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BITMODE` reader - Timer bit width"] +pub type BITMODE_R = crate::FieldReader; +#[doc = "Timer bit width\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum BITMODE_A { + #[doc = "0: 16 bit timer bit width"] + _16BIT = 0, + #[doc = "1: 8 bit timer bit width"] + _08BIT = 1, + #[doc = "2: 24 bit timer bit width"] + _24BIT = 2, + #[doc = "3: 32 bit timer bit width"] + _32BIT = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: BITMODE_A) -> Self { + variant as _ + } +} +impl BITMODE_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> BITMODE_A { + match self.bits { + 0 => BITMODE_A::_16BIT, + 1 => BITMODE_A::_08BIT, + 2 => BITMODE_A::_24BIT, + 3 => BITMODE_A::_32BIT, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `_16BIT`"] + #[inline(always)] + pub fn is_16bit(&self) -> bool { + *self == BITMODE_A::_16BIT + } + #[doc = "Checks if the value of the field is `_08BIT`"] + #[inline(always)] + pub fn is_08bit(&self) -> bool { + *self == BITMODE_A::_08BIT + } + #[doc = "Checks if the value of the field is `_24BIT`"] + #[inline(always)] + pub fn is_24bit(&self) -> bool { + *self == BITMODE_A::_24BIT + } + #[doc = "Checks if the value of the field is `_32BIT`"] + #[inline(always)] + pub fn is_32bit(&self) -> bool { + *self == BITMODE_A::_32BIT + } +} +#[doc = "Field `BITMODE` writer - Timer bit width"] +pub type BITMODE_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u32, BITMODE_SPEC, u8, BITMODE_A, 2, O>; +impl<'a, const O: u8> BITMODE_W<'a, O> { + #[doc = "16 bit timer bit width"] + #[inline(always)] + pub fn _16bit(self) -> &'a mut W { + self.variant(BITMODE_A::_16BIT) + } + #[doc = "8 bit timer bit width"] + #[inline(always)] + pub fn _08bit(self) -> &'a mut W { + self.variant(BITMODE_A::_08BIT) + } + #[doc = "24 bit timer bit width"] + #[inline(always)] + pub fn _24bit(self) -> &'a mut W { + self.variant(BITMODE_A::_24BIT) + } + #[doc = "32 bit timer bit width"] + #[inline(always)] + pub fn _32bit(self) -> &'a mut W { + self.variant(BITMODE_A::_32BIT) + } +} +impl R { + #[doc = "Bits 0:1 - Timer bit width"] + #[inline(always)] + pub fn bitmode(&self) -> BITMODE_R { + BITMODE_R::new((self.bits & 3) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Timer bit width"] + #[inline(always)] + pub fn bitmode(&mut self) -> BITMODE_W<0> { + BITMODE_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Configure the number of bits used by the TIMER\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [bitmode](index.html) module"] +pub struct BITMODE_SPEC; +impl crate::RegisterSpec for BITMODE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [bitmode::R](R) reader structure"] +impl crate::Readable for BITMODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [bitmode::W](W) writer structure"] +impl crate::Writable for BITMODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets BITMODE to value 0"] +impl crate::Resettable for BITMODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/timer0_ns/cc.rs b/pacs/nrf9120-pac/src/timer0_ns/cc.rs new file mode 100644 index 00000000..8ca97538 --- /dev/null +++ b/pacs/nrf9120-pac/src/timer0_ns/cc.rs @@ -0,0 +1,81 @@ +#[doc = "Register `CC[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CC[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CC` reader - Capture/Compare value"] +pub type CC_R = crate::FieldReader; +#[doc = "Field `CC` writer - Capture/Compare value"] +pub type CC_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CC_SPEC, u32, u32, 32, O>; +impl R { + #[doc = "Bits 0:31 - Capture/Compare value"] + #[inline(always)] + pub fn cc(&self) -> CC_R { + CC_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Capture/Compare value"] + #[inline(always)] + pub fn cc(&mut self) -> CC_W<0> { + CC_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Description collection: Capture/Compare register n\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cc](index.html) module"] +pub struct CC_SPEC; +impl crate::RegisterSpec for CC_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cc::R](R) reader structure"] +impl crate::Readable for CC_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [cc::W](W) writer structure"] +impl crate::Writable for CC_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CC[%s] +to value 0"] +impl crate::Resettable for CC_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/timer0_ns/events_compare.rs b/pacs/nrf9120-pac/src/timer0_ns/events_compare.rs new file mode 100644 index 00000000..07f8b944 --- /dev/null +++ b/pacs/nrf9120-pac/src/timer0_ns/events_compare.rs @@ -0,0 +1,134 @@ +#[doc = "Register `EVENTS_COMPARE[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVENTS_COMPARE[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `EVENTS_COMPARE` reader - Compare event on CC\\[n\\] +match"] +pub type EVENTS_COMPARE_R = crate::BitReader; +#[doc = "Compare event on CC\\[n\\] +match\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum EVENTS_COMPARE_A { + #[doc = "0: Event not generated"] + NOT_GENERATED = 0, + #[doc = "1: Event generated"] + GENERATED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: EVENTS_COMPARE_A) -> Self { + variant as u8 != 0 + } +} +impl EVENTS_COMPARE_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EVENTS_COMPARE_A { + match self.bits { + false => EVENTS_COMPARE_A::NOT_GENERATED, + true => EVENTS_COMPARE_A::GENERATED, + } + } + #[doc = "Checks if the value of the field is `NOT_GENERATED`"] + #[inline(always)] + pub fn is_not_generated(&self) -> bool { + *self == EVENTS_COMPARE_A::NOT_GENERATED + } + #[doc = "Checks if the value of the field is `GENERATED`"] + #[inline(always)] + pub fn is_generated(&self) -> bool { + *self == EVENTS_COMPARE_A::GENERATED + } +} +#[doc = "Field `EVENTS_COMPARE` writer - Compare event on CC\\[n\\] +match"] +pub type EVENTS_COMPARE_W<'a, const O: u8> = + crate::BitWriter<'a, u32, EVENTS_COMPARE_SPEC, EVENTS_COMPARE_A, O>; +impl<'a, const O: u8> EVENTS_COMPARE_W<'a, O> { + #[doc = "Event not generated"] + #[inline(always)] + pub fn not_generated(self) -> &'a mut W { + self.variant(EVENTS_COMPARE_A::NOT_GENERATED) + } + #[doc = "Event generated"] + #[inline(always)] + pub fn generated(self) -> &'a mut W { + self.variant(EVENTS_COMPARE_A::GENERATED) + } +} +impl R { + #[doc = "Bit 0 - Compare event on CC\\[n\\] +match"] + #[inline(always)] + pub fn events_compare(&self) -> EVENTS_COMPARE_R { + EVENTS_COMPARE_R::new((self.bits & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Compare event on CC\\[n\\] +match"] + #[inline(always)] + pub fn events_compare(&mut self) -> EVENTS_COMPARE_W<0> { + EVENTS_COMPARE_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Description collection: Compare event on CC\\[n\\] +match\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [events_compare](index.html) module"] +pub struct EVENTS_COMPARE_SPEC; +impl crate::RegisterSpec for EVENTS_COMPARE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [events_compare::R](R) reader structure"] +impl crate::Readable for EVENTS_COMPARE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [events_compare::W](W) writer structure"] +impl crate::Writable for EVENTS_COMPARE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EVENTS_COMPARE[%s] +to value 0"] +impl crate::Resettable for EVENTS_COMPARE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/timer0_ns/intenclr.rs b/pacs/nrf9120-pac/src/timer0_ns/intenclr.rs new file mode 100644 index 00000000..4dfc08da --- /dev/null +++ b/pacs/nrf9120-pac/src/timer0_ns/intenclr.rs @@ -0,0 +1,468 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `COMPARE0` reader - Write '1' to disable interrupt for event COMPARE\\[0\\]"] +pub type COMPARE0_R = crate::BitReader; +#[doc = "Write '1' to disable interrupt for event COMPARE\\[0\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum COMPARE0_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: COMPARE0_A) -> Self { + variant as u8 != 0 + } +} +impl COMPARE0_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> COMPARE0_A { + match self.bits { + false => COMPARE0_A::DISABLED, + true => COMPARE0_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == COMPARE0_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == COMPARE0_A::ENABLED + } +} +#[doc = "Write '1' to disable interrupt for event COMPARE\\[0\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum COMPARE0_AW { + #[doc = "1: Disable"] + CLEAR = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: COMPARE0_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `COMPARE0` writer - Write '1' to disable interrupt for event COMPARE\\[0\\]"] +pub type COMPARE0_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENCLR_SPEC, COMPARE0_AW, O>; +impl<'a, const O: u8> COMPARE0_W<'a, O> { + #[doc = "Disable"] + #[inline(always)] + pub fn clear(self) -> &'a mut W { + self.variant(COMPARE0_AW::CLEAR) + } +} +#[doc = "Field `COMPARE1` reader - Write '1' to disable interrupt for event COMPARE\\[1\\]"] +pub type COMPARE1_R = crate::BitReader; +#[doc = "Write '1' to disable interrupt for event COMPARE\\[1\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum COMPARE1_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: COMPARE1_A) -> Self { + variant as u8 != 0 + } +} +impl COMPARE1_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> COMPARE1_A { + match self.bits { + false => COMPARE1_A::DISABLED, + true => COMPARE1_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == COMPARE1_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == COMPARE1_A::ENABLED + } +} +#[doc = "Write '1' to disable interrupt for event COMPARE\\[1\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum COMPARE1_AW { + #[doc = "1: Disable"] + CLEAR = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: COMPARE1_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `COMPARE1` writer - Write '1' to disable interrupt for event COMPARE\\[1\\]"] +pub type COMPARE1_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENCLR_SPEC, COMPARE1_AW, O>; +impl<'a, const O: u8> COMPARE1_W<'a, O> { + #[doc = "Disable"] + #[inline(always)] + pub fn clear(self) -> &'a mut W { + self.variant(COMPARE1_AW::CLEAR) + } +} +#[doc = "Field `COMPARE2` reader - Write '1' to disable interrupt for event COMPARE\\[2\\]"] +pub type COMPARE2_R = crate::BitReader; +#[doc = "Write '1' to disable interrupt for event COMPARE\\[2\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum COMPARE2_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: COMPARE2_A) -> Self { + variant as u8 != 0 + } +} +impl COMPARE2_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> COMPARE2_A { + match self.bits { + false => COMPARE2_A::DISABLED, + true => COMPARE2_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == COMPARE2_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == COMPARE2_A::ENABLED + } +} +#[doc = "Write '1' to disable interrupt for event COMPARE\\[2\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum COMPARE2_AW { + #[doc = "1: Disable"] + CLEAR = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: COMPARE2_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `COMPARE2` writer - Write '1' to disable interrupt for event COMPARE\\[2\\]"] +pub type COMPARE2_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENCLR_SPEC, COMPARE2_AW, O>; +impl<'a, const O: u8> COMPARE2_W<'a, O> { + #[doc = "Disable"] + #[inline(always)] + pub fn clear(self) -> &'a mut W { + self.variant(COMPARE2_AW::CLEAR) + } +} +#[doc = "Field `COMPARE3` reader - Write '1' to disable interrupt for event COMPARE\\[3\\]"] +pub type COMPARE3_R = crate::BitReader; +#[doc = "Write '1' to disable interrupt for event COMPARE\\[3\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum COMPARE3_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: COMPARE3_A) -> Self { + variant as u8 != 0 + } +} +impl COMPARE3_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> COMPARE3_A { + match self.bits { + false => COMPARE3_A::DISABLED, + true => COMPARE3_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == COMPARE3_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == COMPARE3_A::ENABLED + } +} +#[doc = "Write '1' to disable interrupt for event COMPARE\\[3\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum COMPARE3_AW { + #[doc = "1: Disable"] + CLEAR = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: COMPARE3_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `COMPARE3` writer - Write '1' to disable interrupt for event COMPARE\\[3\\]"] +pub type COMPARE3_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENCLR_SPEC, COMPARE3_AW, O>; +impl<'a, const O: u8> COMPARE3_W<'a, O> { + #[doc = "Disable"] + #[inline(always)] + pub fn clear(self) -> &'a mut W { + self.variant(COMPARE3_AW::CLEAR) + } +} +#[doc = "Field `COMPARE4` reader - Write '1' to disable interrupt for event COMPARE\\[4\\]"] +pub type COMPARE4_R = crate::BitReader; +#[doc = "Write '1' to disable interrupt for event COMPARE\\[4\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum COMPARE4_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: COMPARE4_A) -> Self { + variant as u8 != 0 + } +} +impl COMPARE4_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> COMPARE4_A { + match self.bits { + false => COMPARE4_A::DISABLED, + true => COMPARE4_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == COMPARE4_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == COMPARE4_A::ENABLED + } +} +#[doc = "Write '1' to disable interrupt for event COMPARE\\[4\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum COMPARE4_AW { + #[doc = "1: Disable"] + CLEAR = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: COMPARE4_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `COMPARE4` writer - Write '1' to disable interrupt for event COMPARE\\[4\\]"] +pub type COMPARE4_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENCLR_SPEC, COMPARE4_AW, O>; +impl<'a, const O: u8> COMPARE4_W<'a, O> { + #[doc = "Disable"] + #[inline(always)] + pub fn clear(self) -> &'a mut W { + self.variant(COMPARE4_AW::CLEAR) + } +} +#[doc = "Field `COMPARE5` reader - Write '1' to disable interrupt for event COMPARE\\[5\\]"] +pub type COMPARE5_R = crate::BitReader; +#[doc = "Write '1' to disable interrupt for event COMPARE\\[5\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum COMPARE5_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: COMPARE5_A) -> Self { + variant as u8 != 0 + } +} +impl COMPARE5_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> COMPARE5_A { + match self.bits { + false => COMPARE5_A::DISABLED, + true => COMPARE5_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == COMPARE5_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == COMPARE5_A::ENABLED + } +} +#[doc = "Write '1' to disable interrupt for event COMPARE\\[5\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum COMPARE5_AW { + #[doc = "1: Disable"] + CLEAR = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: COMPARE5_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `COMPARE5` writer - Write '1' to disable interrupt for event COMPARE\\[5\\]"] +pub type COMPARE5_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENCLR_SPEC, COMPARE5_AW, O>; +impl<'a, const O: u8> COMPARE5_W<'a, O> { + #[doc = "Disable"] + #[inline(always)] + pub fn clear(self) -> &'a mut W { + self.variant(COMPARE5_AW::CLEAR) + } +} +impl R { + #[doc = "Bit 16 - Write '1' to disable interrupt for event COMPARE\\[0\\]"] + #[inline(always)] + pub fn compare0(&self) -> COMPARE0_R { + COMPARE0_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Write '1' to disable interrupt for event COMPARE\\[1\\]"] + #[inline(always)] + pub fn compare1(&self) -> COMPARE1_R { + COMPARE1_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Write '1' to disable interrupt for event COMPARE\\[2\\]"] + #[inline(always)] + pub fn compare2(&self) -> COMPARE2_R { + COMPARE2_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Write '1' to disable interrupt for event COMPARE\\[3\\]"] + #[inline(always)] + pub fn compare3(&self) -> COMPARE3_R { + COMPARE3_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Write '1' to disable interrupt for event COMPARE\\[4\\]"] + #[inline(always)] + pub fn compare4(&self) -> COMPARE4_R { + COMPARE4_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Write '1' to disable interrupt for event COMPARE\\[5\\]"] + #[inline(always)] + pub fn compare5(&self) -> COMPARE5_R { + COMPARE5_R::new(((self.bits >> 21) & 1) != 0) + } +} +impl W { + #[doc = "Bit 16 - Write '1' to disable interrupt for event COMPARE\\[0\\]"] + #[inline(always)] + pub fn compare0(&mut self) -> COMPARE0_W<16> { + COMPARE0_W::new(self) + } + #[doc = "Bit 17 - Write '1' to disable interrupt for event COMPARE\\[1\\]"] + #[inline(always)] + pub fn compare1(&mut self) -> COMPARE1_W<17> { + COMPARE1_W::new(self) + } + #[doc = "Bit 18 - Write '1' to disable interrupt for event COMPARE\\[2\\]"] + #[inline(always)] + pub fn compare2(&mut self) -> COMPARE2_W<18> { + COMPARE2_W::new(self) + } + #[doc = "Bit 19 - Write '1' to disable interrupt for event COMPARE\\[3\\]"] + #[inline(always)] + pub fn compare3(&mut self) -> COMPARE3_W<19> { + COMPARE3_W::new(self) + } + #[doc = "Bit 20 - Write '1' to disable interrupt for event COMPARE\\[4\\]"] + #[inline(always)] + pub fn compare4(&mut self) -> COMPARE4_W<20> { + COMPARE4_W::new(self) + } + #[doc = "Bit 21 - Write '1' to disable interrupt for event COMPARE\\[5\\]"] + #[inline(always)] + pub fn compare5(&mut self) -> COMPARE5_W<21> { + COMPARE5_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Disable interrupt\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/timer0_ns/intenset.rs b/pacs/nrf9120-pac/src/timer0_ns/intenset.rs new file mode 100644 index 00000000..8e154471 --- /dev/null +++ b/pacs/nrf9120-pac/src/timer0_ns/intenset.rs @@ -0,0 +1,468 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `COMPARE0` reader - Write '1' to enable interrupt for event COMPARE\\[0\\]"] +pub type COMPARE0_R = crate::BitReader; +#[doc = "Write '1' to enable interrupt for event COMPARE\\[0\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum COMPARE0_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: COMPARE0_A) -> Self { + variant as u8 != 0 + } +} +impl COMPARE0_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> COMPARE0_A { + match self.bits { + false => COMPARE0_A::DISABLED, + true => COMPARE0_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == COMPARE0_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == COMPARE0_A::ENABLED + } +} +#[doc = "Write '1' to enable interrupt for event COMPARE\\[0\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum COMPARE0_AW { + #[doc = "1: Enable"] + SET = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: COMPARE0_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `COMPARE0` writer - Write '1' to enable interrupt for event COMPARE\\[0\\]"] +pub type COMPARE0_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENSET_SPEC, COMPARE0_AW, O>; +impl<'a, const O: u8> COMPARE0_W<'a, O> { + #[doc = "Enable"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(COMPARE0_AW::SET) + } +} +#[doc = "Field `COMPARE1` reader - Write '1' to enable interrupt for event COMPARE\\[1\\]"] +pub type COMPARE1_R = crate::BitReader; +#[doc = "Write '1' to enable interrupt for event COMPARE\\[1\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum COMPARE1_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: COMPARE1_A) -> Self { + variant as u8 != 0 + } +} +impl COMPARE1_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> COMPARE1_A { + match self.bits { + false => COMPARE1_A::DISABLED, + true => COMPARE1_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == COMPARE1_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == COMPARE1_A::ENABLED + } +} +#[doc = "Write '1' to enable interrupt for event COMPARE\\[1\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum COMPARE1_AW { + #[doc = "1: Enable"] + SET = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: COMPARE1_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `COMPARE1` writer - Write '1' to enable interrupt for event COMPARE\\[1\\]"] +pub type COMPARE1_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENSET_SPEC, COMPARE1_AW, O>; +impl<'a, const O: u8> COMPARE1_W<'a, O> { + #[doc = "Enable"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(COMPARE1_AW::SET) + } +} +#[doc = "Field `COMPARE2` reader - Write '1' to enable interrupt for event COMPARE\\[2\\]"] +pub type COMPARE2_R = crate::BitReader; +#[doc = "Write '1' to enable interrupt for event COMPARE\\[2\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum COMPARE2_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: COMPARE2_A) -> Self { + variant as u8 != 0 + } +} +impl COMPARE2_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> COMPARE2_A { + match self.bits { + false => COMPARE2_A::DISABLED, + true => COMPARE2_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == COMPARE2_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == COMPARE2_A::ENABLED + } +} +#[doc = "Write '1' to enable interrupt for event COMPARE\\[2\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum COMPARE2_AW { + #[doc = "1: Enable"] + SET = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: COMPARE2_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `COMPARE2` writer - Write '1' to enable interrupt for event COMPARE\\[2\\]"] +pub type COMPARE2_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENSET_SPEC, COMPARE2_AW, O>; +impl<'a, const O: u8> COMPARE2_W<'a, O> { + #[doc = "Enable"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(COMPARE2_AW::SET) + } +} +#[doc = "Field `COMPARE3` reader - Write '1' to enable interrupt for event COMPARE\\[3\\]"] +pub type COMPARE3_R = crate::BitReader; +#[doc = "Write '1' to enable interrupt for event COMPARE\\[3\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum COMPARE3_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: COMPARE3_A) -> Self { + variant as u8 != 0 + } +} +impl COMPARE3_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> COMPARE3_A { + match self.bits { + false => COMPARE3_A::DISABLED, + true => COMPARE3_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == COMPARE3_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == COMPARE3_A::ENABLED + } +} +#[doc = "Write '1' to enable interrupt for event COMPARE\\[3\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum COMPARE3_AW { + #[doc = "1: Enable"] + SET = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: COMPARE3_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `COMPARE3` writer - Write '1' to enable interrupt for event COMPARE\\[3\\]"] +pub type COMPARE3_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENSET_SPEC, COMPARE3_AW, O>; +impl<'a, const O: u8> COMPARE3_W<'a, O> { + #[doc = "Enable"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(COMPARE3_AW::SET) + } +} +#[doc = "Field `COMPARE4` reader - Write '1' to enable interrupt for event COMPARE\\[4\\]"] +pub type COMPARE4_R = crate::BitReader; +#[doc = "Write '1' to enable interrupt for event COMPARE\\[4\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum COMPARE4_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: COMPARE4_A) -> Self { + variant as u8 != 0 + } +} +impl COMPARE4_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> COMPARE4_A { + match self.bits { + false => COMPARE4_A::DISABLED, + true => COMPARE4_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == COMPARE4_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == COMPARE4_A::ENABLED + } +} +#[doc = "Write '1' to enable interrupt for event COMPARE\\[4\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum COMPARE4_AW { + #[doc = "1: Enable"] + SET = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: COMPARE4_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `COMPARE4` writer - Write '1' to enable interrupt for event COMPARE\\[4\\]"] +pub type COMPARE4_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENSET_SPEC, COMPARE4_AW, O>; +impl<'a, const O: u8> COMPARE4_W<'a, O> { + #[doc = "Enable"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(COMPARE4_AW::SET) + } +} +#[doc = "Field `COMPARE5` reader - Write '1' to enable interrupt for event COMPARE\\[5\\]"] +pub type COMPARE5_R = crate::BitReader; +#[doc = "Write '1' to enable interrupt for event COMPARE\\[5\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum COMPARE5_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: COMPARE5_A) -> Self { + variant as u8 != 0 + } +} +impl COMPARE5_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> COMPARE5_A { + match self.bits { + false => COMPARE5_A::DISABLED, + true => COMPARE5_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == COMPARE5_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == COMPARE5_A::ENABLED + } +} +#[doc = "Write '1' to enable interrupt for event COMPARE\\[5\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum COMPARE5_AW { + #[doc = "1: Enable"] + SET = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: COMPARE5_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `COMPARE5` writer - Write '1' to enable interrupt for event COMPARE\\[5\\]"] +pub type COMPARE5_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENSET_SPEC, COMPARE5_AW, O>; +impl<'a, const O: u8> COMPARE5_W<'a, O> { + #[doc = "Enable"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(COMPARE5_AW::SET) + } +} +impl R { + #[doc = "Bit 16 - Write '1' to enable interrupt for event COMPARE\\[0\\]"] + #[inline(always)] + pub fn compare0(&self) -> COMPARE0_R { + COMPARE0_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Write '1' to enable interrupt for event COMPARE\\[1\\]"] + #[inline(always)] + pub fn compare1(&self) -> COMPARE1_R { + COMPARE1_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Write '1' to enable interrupt for event COMPARE\\[2\\]"] + #[inline(always)] + pub fn compare2(&self) -> COMPARE2_R { + COMPARE2_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Write '1' to enable interrupt for event COMPARE\\[3\\]"] + #[inline(always)] + pub fn compare3(&self) -> COMPARE3_R { + COMPARE3_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Write '1' to enable interrupt for event COMPARE\\[4\\]"] + #[inline(always)] + pub fn compare4(&self) -> COMPARE4_R { + COMPARE4_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Write '1' to enable interrupt for event COMPARE\\[5\\]"] + #[inline(always)] + pub fn compare5(&self) -> COMPARE5_R { + COMPARE5_R::new(((self.bits >> 21) & 1) != 0) + } +} +impl W { + #[doc = "Bit 16 - Write '1' to enable interrupt for event COMPARE\\[0\\]"] + #[inline(always)] + pub fn compare0(&mut self) -> COMPARE0_W<16> { + COMPARE0_W::new(self) + } + #[doc = "Bit 17 - Write '1' to enable interrupt for event COMPARE\\[1\\]"] + #[inline(always)] + pub fn compare1(&mut self) -> COMPARE1_W<17> { + COMPARE1_W::new(self) + } + #[doc = "Bit 18 - Write '1' to enable interrupt for event COMPARE\\[2\\]"] + #[inline(always)] + pub fn compare2(&mut self) -> COMPARE2_W<18> { + COMPARE2_W::new(self) + } + #[doc = "Bit 19 - Write '1' to enable interrupt for event COMPARE\\[3\\]"] + #[inline(always)] + pub fn compare3(&mut self) -> COMPARE3_W<19> { + COMPARE3_W::new(self) + } + #[doc = "Bit 20 - Write '1' to enable interrupt for event COMPARE\\[4\\]"] + #[inline(always)] + pub fn compare4(&mut self) -> COMPARE4_W<20> { + COMPARE4_W::new(self) + } + #[doc = "Bit 21 - Write '1' to enable interrupt for event COMPARE\\[5\\]"] + #[inline(always)] + pub fn compare5(&mut self) -> COMPARE5_W<21> { + COMPARE5_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Enable interrupt\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/timer0_ns/mode.rs b/pacs/nrf9120-pac/src/timer0_ns/mode.rs new file mode 100644 index 00000000..33c307d3 --- /dev/null +++ b/pacs/nrf9120-pac/src/timer0_ns/mode.rs @@ -0,0 +1,141 @@ +#[doc = "Register `MODE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `MODE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `MODE` reader - Timer mode"] +pub type MODE_R = crate::FieldReader; +#[doc = "Timer mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum MODE_A { + #[doc = "0: Select Timer mode"] + TIMER = 0, + #[doc = "1: Deprecated enumerator - Select Counter mode"] + COUNTER = 1, + #[doc = "2: Select Low Power Counter mode"] + LOW_POWER_COUNTER = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: MODE_A) -> Self { + variant as _ + } +} +impl MODE_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(MODE_A::TIMER), + 1 => Some(MODE_A::COUNTER), + 2 => Some(MODE_A::LOW_POWER_COUNTER), + _ => None, + } + } + #[doc = "Checks if the value of the field is `TIMER`"] + #[inline(always)] + pub fn is_timer(&self) -> bool { + *self == MODE_A::TIMER + } + #[doc = "Checks if the value of the field is `COUNTER`"] + #[inline(always)] + pub fn is_counter(&self) -> bool { + *self == MODE_A::COUNTER + } + #[doc = "Checks if the value of the field is `LOW_POWER_COUNTER`"] + #[inline(always)] + pub fn is_low_power_counter(&self) -> bool { + *self == MODE_A::LOW_POWER_COUNTER + } +} +#[doc = "Field `MODE` writer - Timer mode"] +pub type MODE_W<'a, const O: u8> = crate::FieldWriter<'a, u32, MODE_SPEC, u8, MODE_A, 2, O>; +impl<'a, const O: u8> MODE_W<'a, O> { + #[doc = "Select Timer mode"] + #[inline(always)] + pub fn timer(self) -> &'a mut W { + self.variant(MODE_A::TIMER) + } + #[doc = "Deprecated enumerator - Select Counter mode"] + #[inline(always)] + pub fn counter(self) -> &'a mut W { + self.variant(MODE_A::COUNTER) + } + #[doc = "Select Low Power Counter mode"] + #[inline(always)] + pub fn low_power_counter(self) -> &'a mut W { + self.variant(MODE_A::LOW_POWER_COUNTER) + } +} +impl R { + #[doc = "Bits 0:1 - Timer mode"] + #[inline(always)] + pub fn mode(&self) -> MODE_R { + MODE_R::new((self.bits & 3) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Timer mode"] + #[inline(always)] + pub fn mode(&mut self) -> MODE_W<0> { + MODE_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Timer mode selection\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [mode](index.html) module"] +pub struct MODE_SPEC; +impl crate::RegisterSpec for MODE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [mode::R](R) reader structure"] +impl crate::Readable for MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [mode::W](W) writer structure"] +impl crate::Writable for MODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets MODE to value 0"] +impl crate::Resettable for MODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/timer0_ns/oneshoten.rs b/pacs/nrf9120-pac/src/timer0_ns/oneshoten.rs new file mode 100644 index 00000000..4f472969 --- /dev/null +++ b/pacs/nrf9120-pac/src/timer0_ns/oneshoten.rs @@ -0,0 +1,127 @@ +#[doc = "Register `ONESHOTEN[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `ONESHOTEN[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ONESHOTEN` reader - Enable one-shot operation"] +pub type ONESHOTEN_R = crate::BitReader; +#[doc = "Enable one-shot operation\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum ONESHOTEN_A { + #[doc = "0: Disable one-shot operation"] + DISABLE = 0, + #[doc = "1: Enable one-shot operation"] + ENABLE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: ONESHOTEN_A) -> Self { + variant as u8 != 0 + } +} +impl ONESHOTEN_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> ONESHOTEN_A { + match self.bits { + false => ONESHOTEN_A::DISABLE, + true => ONESHOTEN_A::ENABLE, + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == ONESHOTEN_A::DISABLE + } + #[doc = "Checks if the value of the field is `ENABLE`"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == ONESHOTEN_A::ENABLE + } +} +#[doc = "Field `ONESHOTEN` writer - Enable one-shot operation"] +pub type ONESHOTEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, ONESHOTEN_SPEC, ONESHOTEN_A, O>; +impl<'a, const O: u8> ONESHOTEN_W<'a, O> { + #[doc = "Disable one-shot operation"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(ONESHOTEN_A::DISABLE) + } + #[doc = "Enable one-shot operation"] + #[inline(always)] + pub fn enable(self) -> &'a mut W { + self.variant(ONESHOTEN_A::ENABLE) + } +} +impl R { + #[doc = "Bit 0 - Enable one-shot operation"] + #[inline(always)] + pub fn oneshoten(&self) -> ONESHOTEN_R { + ONESHOTEN_R::new((self.bits & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Enable one-shot operation"] + #[inline(always)] + pub fn oneshoten(&mut self) -> ONESHOTEN_W<0> { + ONESHOTEN_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Description collection: Enable one-shot operation for Capture/Compare channel n\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [oneshoten](index.html) module"] +pub struct ONESHOTEN_SPEC; +impl crate::RegisterSpec for ONESHOTEN_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [oneshoten::R](R) reader structure"] +impl crate::Readable for ONESHOTEN_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [oneshoten::W](W) writer structure"] +impl crate::Writable for ONESHOTEN_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets ONESHOTEN[%s] +to value 0"] +impl crate::Resettable for ONESHOTEN_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/timer0_ns/prescaler.rs b/pacs/nrf9120-pac/src/timer0_ns/prescaler.rs new file mode 100644 index 00000000..6d3f97db --- /dev/null +++ b/pacs/nrf9120-pac/src/timer0_ns/prescaler.rs @@ -0,0 +1,80 @@ +#[doc = "Register `PRESCALER` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PRESCALER` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PRESCALER` reader - Prescaler value"] +pub type PRESCALER_R = crate::FieldReader; +#[doc = "Field `PRESCALER` writer - Prescaler value"] +pub type PRESCALER_W<'a, const O: u8> = crate::FieldWriter<'a, u32, PRESCALER_SPEC, u8, u8, 4, O>; +impl R { + #[doc = "Bits 0:3 - Prescaler value"] + #[inline(always)] + pub fn prescaler(&self) -> PRESCALER_R { + PRESCALER_R::new((self.bits & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - Prescaler value"] + #[inline(always)] + pub fn prescaler(&mut self) -> PRESCALER_W<0> { + PRESCALER_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Timer prescaler register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [prescaler](index.html) module"] +pub struct PRESCALER_SPEC; +impl crate::RegisterSpec for PRESCALER_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [prescaler::R](R) reader structure"] +impl crate::Readable for PRESCALER_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [prescaler::W](W) writer structure"] +impl crate::Writable for PRESCALER_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PRESCALER to value 0x04"] +impl crate::Resettable for PRESCALER_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x04 + } +} diff --git a/pacs/nrf9120-pac/src/timer0_ns/publish_compare.rs b/pacs/nrf9120-pac/src/timer0_ns/publish_compare.rs new file mode 100644 index 00000000..0de6a146 --- /dev/null +++ b/pacs/nrf9120-pac/src/timer0_ns/publish_compare.rs @@ -0,0 +1,145 @@ +#[doc = "Register `PUBLISH_COMPARE[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PUBLISH_COMPARE[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CHIDX` reader - DPPI channel that event COMPARE\\[n\\] +will publish to"] +pub type CHIDX_R = crate::FieldReader; +#[doc = "Field `CHIDX` writer - DPPI channel that event COMPARE\\[n\\] +will publish to"] +pub type CHIDX_W<'a, const O: u8> = crate::FieldWriter<'a, u32, PUBLISH_COMPARE_SPEC, u8, u8, 8, O>; +#[doc = "Field `EN` reader - "] +pub type EN_R = crate::BitReader; +#[doc = "\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum EN_A { + #[doc = "0: Disable publishing"] + DISABLED = 0, + #[doc = "1: Enable publishing"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: EN_A) -> Self { + variant as u8 != 0 + } +} +impl EN_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EN_A { + match self.bits { + false => EN_A::DISABLED, + true => EN_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == EN_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == EN_A::ENABLED + } +} +#[doc = "Field `EN` writer - "] +pub type EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, PUBLISH_COMPARE_SPEC, EN_A, O>; +impl<'a, const O: u8> EN_W<'a, O> { + #[doc = "Disable publishing"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(EN_A::DISABLED) + } + #[doc = "Enable publishing"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(EN_A::ENABLED) + } +} +impl R { + #[doc = "Bits 0:7 - DPPI channel that event COMPARE\\[n\\] +will publish to"] + #[inline(always)] + pub fn chidx(&self) -> CHIDX_R { + CHIDX_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&self) -> EN_R { + EN_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:7 - DPPI channel that event COMPARE\\[n\\] +will publish to"] + #[inline(always)] + pub fn chidx(&mut self) -> CHIDX_W<0> { + CHIDX_W::new(self) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&mut self) -> EN_W<31> { + EN_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Description collection: Publish configuration for event COMPARE\\[n\\]\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [publish_compare](index.html) module"] +pub struct PUBLISH_COMPARE_SPEC; +impl crate::RegisterSpec for PUBLISH_COMPARE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [publish_compare::R](R) reader structure"] +impl crate::Readable for PUBLISH_COMPARE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [publish_compare::W](W) writer structure"] +impl crate::Writable for PUBLISH_COMPARE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PUBLISH_COMPARE[%s] +to value 0"] +impl crate::Resettable for PUBLISH_COMPARE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/timer0_ns/shorts.rs b/pacs/nrf9120-pac/src/timer0_ns/shorts.rs new file mode 100644 index 00000000..a571e334 --- /dev/null +++ b/pacs/nrf9120-pac/src/timer0_ns/shorts.rs @@ -0,0 +1,858 @@ +#[doc = "Register `SHORTS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SHORTS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `COMPARE0_CLEAR` reader - Shortcut between event COMPARE\\[0\\] +and task CLEAR"] +pub type COMPARE0_CLEAR_R = crate::BitReader; +#[doc = "Shortcut between event COMPARE\\[0\\] +and task CLEAR\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum COMPARE0_CLEAR_A { + #[doc = "0: Disable shortcut"] + DISABLED = 0, + #[doc = "1: Enable shortcut"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: COMPARE0_CLEAR_A) -> Self { + variant as u8 != 0 + } +} +impl COMPARE0_CLEAR_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> COMPARE0_CLEAR_A { + match self.bits { + false => COMPARE0_CLEAR_A::DISABLED, + true => COMPARE0_CLEAR_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == COMPARE0_CLEAR_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == COMPARE0_CLEAR_A::ENABLED + } +} +#[doc = "Field `COMPARE0_CLEAR` writer - Shortcut between event COMPARE\\[0\\] +and task CLEAR"] +pub type COMPARE0_CLEAR_W<'a, const O: u8> = + crate::BitWriter<'a, u32, SHORTS_SPEC, COMPARE0_CLEAR_A, O>; +impl<'a, const O: u8> COMPARE0_CLEAR_W<'a, O> { + #[doc = "Disable shortcut"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(COMPARE0_CLEAR_A::DISABLED) + } + #[doc = "Enable shortcut"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(COMPARE0_CLEAR_A::ENABLED) + } +} +#[doc = "Field `COMPARE1_CLEAR` reader - Shortcut between event COMPARE\\[1\\] +and task CLEAR"] +pub type COMPARE1_CLEAR_R = crate::BitReader; +#[doc = "Shortcut between event COMPARE\\[1\\] +and task CLEAR\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum COMPARE1_CLEAR_A { + #[doc = "0: Disable shortcut"] + DISABLED = 0, + #[doc = "1: Enable shortcut"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: COMPARE1_CLEAR_A) -> Self { + variant as u8 != 0 + } +} +impl COMPARE1_CLEAR_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> COMPARE1_CLEAR_A { + match self.bits { + false => COMPARE1_CLEAR_A::DISABLED, + true => COMPARE1_CLEAR_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == COMPARE1_CLEAR_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == COMPARE1_CLEAR_A::ENABLED + } +} +#[doc = "Field `COMPARE1_CLEAR` writer - Shortcut between event COMPARE\\[1\\] +and task CLEAR"] +pub type COMPARE1_CLEAR_W<'a, const O: u8> = + crate::BitWriter<'a, u32, SHORTS_SPEC, COMPARE1_CLEAR_A, O>; +impl<'a, const O: u8> COMPARE1_CLEAR_W<'a, O> { + #[doc = "Disable shortcut"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(COMPARE1_CLEAR_A::DISABLED) + } + #[doc = "Enable shortcut"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(COMPARE1_CLEAR_A::ENABLED) + } +} +#[doc = "Field `COMPARE2_CLEAR` reader - Shortcut between event COMPARE\\[2\\] +and task CLEAR"] +pub type COMPARE2_CLEAR_R = crate::BitReader; +#[doc = "Shortcut between event COMPARE\\[2\\] +and task CLEAR\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum COMPARE2_CLEAR_A { + #[doc = "0: Disable shortcut"] + DISABLED = 0, + #[doc = "1: Enable shortcut"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: COMPARE2_CLEAR_A) -> Self { + variant as u8 != 0 + } +} +impl COMPARE2_CLEAR_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> COMPARE2_CLEAR_A { + match self.bits { + false => COMPARE2_CLEAR_A::DISABLED, + true => COMPARE2_CLEAR_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == COMPARE2_CLEAR_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == COMPARE2_CLEAR_A::ENABLED + } +} +#[doc = "Field `COMPARE2_CLEAR` writer - Shortcut between event COMPARE\\[2\\] +and task CLEAR"] +pub type COMPARE2_CLEAR_W<'a, const O: u8> = + crate::BitWriter<'a, u32, SHORTS_SPEC, COMPARE2_CLEAR_A, O>; +impl<'a, const O: u8> COMPARE2_CLEAR_W<'a, O> { + #[doc = "Disable shortcut"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(COMPARE2_CLEAR_A::DISABLED) + } + #[doc = "Enable shortcut"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(COMPARE2_CLEAR_A::ENABLED) + } +} +#[doc = "Field `COMPARE3_CLEAR` reader - Shortcut between event COMPARE\\[3\\] +and task CLEAR"] +pub type COMPARE3_CLEAR_R = crate::BitReader; +#[doc = "Shortcut between event COMPARE\\[3\\] +and task CLEAR\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum COMPARE3_CLEAR_A { + #[doc = "0: Disable shortcut"] + DISABLED = 0, + #[doc = "1: Enable shortcut"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: COMPARE3_CLEAR_A) -> Self { + variant as u8 != 0 + } +} +impl COMPARE3_CLEAR_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> COMPARE3_CLEAR_A { + match self.bits { + false => COMPARE3_CLEAR_A::DISABLED, + true => COMPARE3_CLEAR_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == COMPARE3_CLEAR_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == COMPARE3_CLEAR_A::ENABLED + } +} +#[doc = "Field `COMPARE3_CLEAR` writer - Shortcut between event COMPARE\\[3\\] +and task CLEAR"] +pub type COMPARE3_CLEAR_W<'a, const O: u8> = + crate::BitWriter<'a, u32, SHORTS_SPEC, COMPARE3_CLEAR_A, O>; +impl<'a, const O: u8> COMPARE3_CLEAR_W<'a, O> { + #[doc = "Disable shortcut"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(COMPARE3_CLEAR_A::DISABLED) + } + #[doc = "Enable shortcut"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(COMPARE3_CLEAR_A::ENABLED) + } +} +#[doc = "Field `COMPARE4_CLEAR` reader - Shortcut between event COMPARE\\[4\\] +and task CLEAR"] +pub type COMPARE4_CLEAR_R = crate::BitReader; +#[doc = "Shortcut between event COMPARE\\[4\\] +and task CLEAR\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum COMPARE4_CLEAR_A { + #[doc = "0: Disable shortcut"] + DISABLED = 0, + #[doc = "1: Enable shortcut"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: COMPARE4_CLEAR_A) -> Self { + variant as u8 != 0 + } +} +impl COMPARE4_CLEAR_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> COMPARE4_CLEAR_A { + match self.bits { + false => COMPARE4_CLEAR_A::DISABLED, + true => COMPARE4_CLEAR_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == COMPARE4_CLEAR_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == COMPARE4_CLEAR_A::ENABLED + } +} +#[doc = "Field `COMPARE4_CLEAR` writer - Shortcut between event COMPARE\\[4\\] +and task CLEAR"] +pub type COMPARE4_CLEAR_W<'a, const O: u8> = + crate::BitWriter<'a, u32, SHORTS_SPEC, COMPARE4_CLEAR_A, O>; +impl<'a, const O: u8> COMPARE4_CLEAR_W<'a, O> { + #[doc = "Disable shortcut"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(COMPARE4_CLEAR_A::DISABLED) + } + #[doc = "Enable shortcut"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(COMPARE4_CLEAR_A::ENABLED) + } +} +#[doc = "Field `COMPARE5_CLEAR` reader - Shortcut between event COMPARE\\[5\\] +and task CLEAR"] +pub type COMPARE5_CLEAR_R = crate::BitReader; +#[doc = "Shortcut between event COMPARE\\[5\\] +and task CLEAR\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum COMPARE5_CLEAR_A { + #[doc = "0: Disable shortcut"] + DISABLED = 0, + #[doc = "1: Enable shortcut"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: COMPARE5_CLEAR_A) -> Self { + variant as u8 != 0 + } +} +impl COMPARE5_CLEAR_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> COMPARE5_CLEAR_A { + match self.bits { + false => COMPARE5_CLEAR_A::DISABLED, + true => COMPARE5_CLEAR_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == COMPARE5_CLEAR_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == COMPARE5_CLEAR_A::ENABLED + } +} +#[doc = "Field `COMPARE5_CLEAR` writer - Shortcut between event COMPARE\\[5\\] +and task CLEAR"] +pub type COMPARE5_CLEAR_W<'a, const O: u8> = + crate::BitWriter<'a, u32, SHORTS_SPEC, COMPARE5_CLEAR_A, O>; +impl<'a, const O: u8> COMPARE5_CLEAR_W<'a, O> { + #[doc = "Disable shortcut"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(COMPARE5_CLEAR_A::DISABLED) + } + #[doc = "Enable shortcut"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(COMPARE5_CLEAR_A::ENABLED) + } +} +#[doc = "Field `COMPARE0_STOP` reader - Shortcut between event COMPARE\\[0\\] +and task STOP"] +pub type COMPARE0_STOP_R = crate::BitReader; +#[doc = "Shortcut between event COMPARE\\[0\\] +and task STOP\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum COMPARE0_STOP_A { + #[doc = "0: Disable shortcut"] + DISABLED = 0, + #[doc = "1: Enable shortcut"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: COMPARE0_STOP_A) -> Self { + variant as u8 != 0 + } +} +impl COMPARE0_STOP_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> COMPARE0_STOP_A { + match self.bits { + false => COMPARE0_STOP_A::DISABLED, + true => COMPARE0_STOP_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == COMPARE0_STOP_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == COMPARE0_STOP_A::ENABLED + } +} +#[doc = "Field `COMPARE0_STOP` writer - Shortcut between event COMPARE\\[0\\] +and task STOP"] +pub type COMPARE0_STOP_W<'a, const O: u8> = + crate::BitWriter<'a, u32, SHORTS_SPEC, COMPARE0_STOP_A, O>; +impl<'a, const O: u8> COMPARE0_STOP_W<'a, O> { + #[doc = "Disable shortcut"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(COMPARE0_STOP_A::DISABLED) + } + #[doc = "Enable shortcut"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(COMPARE0_STOP_A::ENABLED) + } +} +#[doc = "Field `COMPARE1_STOP` reader - Shortcut between event COMPARE\\[1\\] +and task STOP"] +pub type COMPARE1_STOP_R = crate::BitReader; +#[doc = "Shortcut between event COMPARE\\[1\\] +and task STOP\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum COMPARE1_STOP_A { + #[doc = "0: Disable shortcut"] + DISABLED = 0, + #[doc = "1: Enable shortcut"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: COMPARE1_STOP_A) -> Self { + variant as u8 != 0 + } +} +impl COMPARE1_STOP_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> COMPARE1_STOP_A { + match self.bits { + false => COMPARE1_STOP_A::DISABLED, + true => COMPARE1_STOP_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == COMPARE1_STOP_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == COMPARE1_STOP_A::ENABLED + } +} +#[doc = "Field `COMPARE1_STOP` writer - Shortcut between event COMPARE\\[1\\] +and task STOP"] +pub type COMPARE1_STOP_W<'a, const O: u8> = + crate::BitWriter<'a, u32, SHORTS_SPEC, COMPARE1_STOP_A, O>; +impl<'a, const O: u8> COMPARE1_STOP_W<'a, O> { + #[doc = "Disable shortcut"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(COMPARE1_STOP_A::DISABLED) + } + #[doc = "Enable shortcut"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(COMPARE1_STOP_A::ENABLED) + } +} +#[doc = "Field `COMPARE2_STOP` reader - Shortcut between event COMPARE\\[2\\] +and task STOP"] +pub type COMPARE2_STOP_R = crate::BitReader; +#[doc = "Shortcut between event COMPARE\\[2\\] +and task STOP\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum COMPARE2_STOP_A { + #[doc = "0: Disable shortcut"] + DISABLED = 0, + #[doc = "1: Enable shortcut"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: COMPARE2_STOP_A) -> Self { + variant as u8 != 0 + } +} +impl COMPARE2_STOP_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> COMPARE2_STOP_A { + match self.bits { + false => COMPARE2_STOP_A::DISABLED, + true => COMPARE2_STOP_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == COMPARE2_STOP_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == COMPARE2_STOP_A::ENABLED + } +} +#[doc = "Field `COMPARE2_STOP` writer - Shortcut between event COMPARE\\[2\\] +and task STOP"] +pub type COMPARE2_STOP_W<'a, const O: u8> = + crate::BitWriter<'a, u32, SHORTS_SPEC, COMPARE2_STOP_A, O>; +impl<'a, const O: u8> COMPARE2_STOP_W<'a, O> { + #[doc = "Disable shortcut"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(COMPARE2_STOP_A::DISABLED) + } + #[doc = "Enable shortcut"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(COMPARE2_STOP_A::ENABLED) + } +} +#[doc = "Field `COMPARE3_STOP` reader - Shortcut between event COMPARE\\[3\\] +and task STOP"] +pub type COMPARE3_STOP_R = crate::BitReader; +#[doc = "Shortcut between event COMPARE\\[3\\] +and task STOP\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum COMPARE3_STOP_A { + #[doc = "0: Disable shortcut"] + DISABLED = 0, + #[doc = "1: Enable shortcut"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: COMPARE3_STOP_A) -> Self { + variant as u8 != 0 + } +} +impl COMPARE3_STOP_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> COMPARE3_STOP_A { + match self.bits { + false => COMPARE3_STOP_A::DISABLED, + true => COMPARE3_STOP_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == COMPARE3_STOP_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == COMPARE3_STOP_A::ENABLED + } +} +#[doc = "Field `COMPARE3_STOP` writer - Shortcut between event COMPARE\\[3\\] +and task STOP"] +pub type COMPARE3_STOP_W<'a, const O: u8> = + crate::BitWriter<'a, u32, SHORTS_SPEC, COMPARE3_STOP_A, O>; +impl<'a, const O: u8> COMPARE3_STOP_W<'a, O> { + #[doc = "Disable shortcut"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(COMPARE3_STOP_A::DISABLED) + } + #[doc = "Enable shortcut"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(COMPARE3_STOP_A::ENABLED) + } +} +#[doc = "Field `COMPARE4_STOP` reader - Shortcut between event COMPARE\\[4\\] +and task STOP"] +pub type COMPARE4_STOP_R = crate::BitReader; +#[doc = "Shortcut between event COMPARE\\[4\\] +and task STOP\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum COMPARE4_STOP_A { + #[doc = "0: Disable shortcut"] + DISABLED = 0, + #[doc = "1: Enable shortcut"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: COMPARE4_STOP_A) -> Self { + variant as u8 != 0 + } +} +impl COMPARE4_STOP_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> COMPARE4_STOP_A { + match self.bits { + false => COMPARE4_STOP_A::DISABLED, + true => COMPARE4_STOP_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == COMPARE4_STOP_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == COMPARE4_STOP_A::ENABLED + } +} +#[doc = "Field `COMPARE4_STOP` writer - Shortcut between event COMPARE\\[4\\] +and task STOP"] +pub type COMPARE4_STOP_W<'a, const O: u8> = + crate::BitWriter<'a, u32, SHORTS_SPEC, COMPARE4_STOP_A, O>; +impl<'a, const O: u8> COMPARE4_STOP_W<'a, O> { + #[doc = "Disable shortcut"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(COMPARE4_STOP_A::DISABLED) + } + #[doc = "Enable shortcut"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(COMPARE4_STOP_A::ENABLED) + } +} +#[doc = "Field `COMPARE5_STOP` reader - Shortcut between event COMPARE\\[5\\] +and task STOP"] +pub type COMPARE5_STOP_R = crate::BitReader; +#[doc = "Shortcut between event COMPARE\\[5\\] +and task STOP\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum COMPARE5_STOP_A { + #[doc = "0: Disable shortcut"] + DISABLED = 0, + #[doc = "1: Enable shortcut"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: COMPARE5_STOP_A) -> Self { + variant as u8 != 0 + } +} +impl COMPARE5_STOP_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> COMPARE5_STOP_A { + match self.bits { + false => COMPARE5_STOP_A::DISABLED, + true => COMPARE5_STOP_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == COMPARE5_STOP_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == COMPARE5_STOP_A::ENABLED + } +} +#[doc = "Field `COMPARE5_STOP` writer - Shortcut between event COMPARE\\[5\\] +and task STOP"] +pub type COMPARE5_STOP_W<'a, const O: u8> = + crate::BitWriter<'a, u32, SHORTS_SPEC, COMPARE5_STOP_A, O>; +impl<'a, const O: u8> COMPARE5_STOP_W<'a, O> { + #[doc = "Disable shortcut"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(COMPARE5_STOP_A::DISABLED) + } + #[doc = "Enable shortcut"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(COMPARE5_STOP_A::ENABLED) + } +} +impl R { + #[doc = "Bit 0 - Shortcut between event COMPARE\\[0\\] +and task CLEAR"] + #[inline(always)] + pub fn compare0_clear(&self) -> COMPARE0_CLEAR_R { + COMPARE0_CLEAR_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Shortcut between event COMPARE\\[1\\] +and task CLEAR"] + #[inline(always)] + pub fn compare1_clear(&self) -> COMPARE1_CLEAR_R { + COMPARE1_CLEAR_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Shortcut between event COMPARE\\[2\\] +and task CLEAR"] + #[inline(always)] + pub fn compare2_clear(&self) -> COMPARE2_CLEAR_R { + COMPARE2_CLEAR_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Shortcut between event COMPARE\\[3\\] +and task CLEAR"] + #[inline(always)] + pub fn compare3_clear(&self) -> COMPARE3_CLEAR_R { + COMPARE3_CLEAR_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Shortcut between event COMPARE\\[4\\] +and task CLEAR"] + #[inline(always)] + pub fn compare4_clear(&self) -> COMPARE4_CLEAR_R { + COMPARE4_CLEAR_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Shortcut between event COMPARE\\[5\\] +and task CLEAR"] + #[inline(always)] + pub fn compare5_clear(&self) -> COMPARE5_CLEAR_R { + COMPARE5_CLEAR_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 8 - Shortcut between event COMPARE\\[0\\] +and task STOP"] + #[inline(always)] + pub fn compare0_stop(&self) -> COMPARE0_STOP_R { + COMPARE0_STOP_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Shortcut between event COMPARE\\[1\\] +and task STOP"] + #[inline(always)] + pub fn compare1_stop(&self) -> COMPARE1_STOP_R { + COMPARE1_STOP_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Shortcut between event COMPARE\\[2\\] +and task STOP"] + #[inline(always)] + pub fn compare2_stop(&self) -> COMPARE2_STOP_R { + COMPARE2_STOP_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Shortcut between event COMPARE\\[3\\] +and task STOP"] + #[inline(always)] + pub fn compare3_stop(&self) -> COMPARE3_STOP_R { + COMPARE3_STOP_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Shortcut between event COMPARE\\[4\\] +and task STOP"] + #[inline(always)] + pub fn compare4_stop(&self) -> COMPARE4_STOP_R { + COMPARE4_STOP_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Shortcut between event COMPARE\\[5\\] +and task STOP"] + #[inline(always)] + pub fn compare5_stop(&self) -> COMPARE5_STOP_R { + COMPARE5_STOP_R::new(((self.bits >> 13) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Shortcut between event COMPARE\\[0\\] +and task CLEAR"] + #[inline(always)] + pub fn compare0_clear(&mut self) -> COMPARE0_CLEAR_W<0> { + COMPARE0_CLEAR_W::new(self) + } + #[doc = "Bit 1 - Shortcut between event COMPARE\\[1\\] +and task CLEAR"] + #[inline(always)] + pub fn compare1_clear(&mut self) -> COMPARE1_CLEAR_W<1> { + COMPARE1_CLEAR_W::new(self) + } + #[doc = "Bit 2 - Shortcut between event COMPARE\\[2\\] +and task CLEAR"] + #[inline(always)] + pub fn compare2_clear(&mut self) -> COMPARE2_CLEAR_W<2> { + COMPARE2_CLEAR_W::new(self) + } + #[doc = "Bit 3 - Shortcut between event COMPARE\\[3\\] +and task CLEAR"] + #[inline(always)] + pub fn compare3_clear(&mut self) -> COMPARE3_CLEAR_W<3> { + COMPARE3_CLEAR_W::new(self) + } + #[doc = "Bit 4 - Shortcut between event COMPARE\\[4\\] +and task CLEAR"] + #[inline(always)] + pub fn compare4_clear(&mut self) -> COMPARE4_CLEAR_W<4> { + COMPARE4_CLEAR_W::new(self) + } + #[doc = "Bit 5 - Shortcut between event COMPARE\\[5\\] +and task CLEAR"] + #[inline(always)] + pub fn compare5_clear(&mut self) -> COMPARE5_CLEAR_W<5> { + COMPARE5_CLEAR_W::new(self) + } + #[doc = "Bit 8 - Shortcut between event COMPARE\\[0\\] +and task STOP"] + #[inline(always)] + pub fn compare0_stop(&mut self) -> COMPARE0_STOP_W<8> { + COMPARE0_STOP_W::new(self) + } + #[doc = "Bit 9 - Shortcut between event COMPARE\\[1\\] +and task STOP"] + #[inline(always)] + pub fn compare1_stop(&mut self) -> COMPARE1_STOP_W<9> { + COMPARE1_STOP_W::new(self) + } + #[doc = "Bit 10 - Shortcut between event COMPARE\\[2\\] +and task STOP"] + #[inline(always)] + pub fn compare2_stop(&mut self) -> COMPARE2_STOP_W<10> { + COMPARE2_STOP_W::new(self) + } + #[doc = "Bit 11 - Shortcut between event COMPARE\\[3\\] +and task STOP"] + #[inline(always)] + pub fn compare3_stop(&mut self) -> COMPARE3_STOP_W<11> { + COMPARE3_STOP_W::new(self) + } + #[doc = "Bit 12 - Shortcut between event COMPARE\\[4\\] +and task STOP"] + #[inline(always)] + pub fn compare4_stop(&mut self) -> COMPARE4_STOP_W<12> { + COMPARE4_STOP_W::new(self) + } + #[doc = "Bit 13 - Shortcut between event COMPARE\\[5\\] +and task STOP"] + #[inline(always)] + pub fn compare5_stop(&mut self) -> COMPARE5_STOP_W<13> { + COMPARE5_STOP_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Shortcuts between local events and tasks\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [shorts](index.html) module"] +pub struct SHORTS_SPEC; +impl crate::RegisterSpec for SHORTS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [shorts::R](R) reader structure"] +impl crate::Readable for SHORTS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [shorts::W](W) writer structure"] +impl crate::Writable for SHORTS_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SHORTS to value 0"] +impl crate::Resettable for SHORTS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/timer0_ns/subscribe_capture.rs b/pacs/nrf9120-pac/src/timer0_ns/subscribe_capture.rs new file mode 100644 index 00000000..92c1e441 --- /dev/null +++ b/pacs/nrf9120-pac/src/timer0_ns/subscribe_capture.rs @@ -0,0 +1,146 @@ +#[doc = "Register `SUBSCRIBE_CAPTURE[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SUBSCRIBE_CAPTURE[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CHIDX` reader - DPPI channel that task CAPTURE\\[n\\] +will subscribe to"] +pub type CHIDX_R = crate::FieldReader; +#[doc = "Field `CHIDX` writer - DPPI channel that task CAPTURE\\[n\\] +will subscribe to"] +pub type CHIDX_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, SUBSCRIBE_CAPTURE_SPEC, u8, u8, 8, O>; +#[doc = "Field `EN` reader - "] +pub type EN_R = crate::BitReader; +#[doc = "\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum EN_A { + #[doc = "0: Disable subscription"] + DISABLED = 0, + #[doc = "1: Enable subscription"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: EN_A) -> Self { + variant as u8 != 0 + } +} +impl EN_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EN_A { + match self.bits { + false => EN_A::DISABLED, + true => EN_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == EN_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == EN_A::ENABLED + } +} +#[doc = "Field `EN` writer - "] +pub type EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, SUBSCRIBE_CAPTURE_SPEC, EN_A, O>; +impl<'a, const O: u8> EN_W<'a, O> { + #[doc = "Disable subscription"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(EN_A::DISABLED) + } + #[doc = "Enable subscription"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(EN_A::ENABLED) + } +} +impl R { + #[doc = "Bits 0:7 - DPPI channel that task CAPTURE\\[n\\] +will subscribe to"] + #[inline(always)] + pub fn chidx(&self) -> CHIDX_R { + CHIDX_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&self) -> EN_R { + EN_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:7 - DPPI channel that task CAPTURE\\[n\\] +will subscribe to"] + #[inline(always)] + pub fn chidx(&mut self) -> CHIDX_W<0> { + CHIDX_W::new(self) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&mut self) -> EN_W<31> { + EN_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Description collection: Subscribe configuration for task CAPTURE\\[n\\]\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [subscribe_capture](index.html) module"] +pub struct SUBSCRIBE_CAPTURE_SPEC; +impl crate::RegisterSpec for SUBSCRIBE_CAPTURE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [subscribe_capture::R](R) reader structure"] +impl crate::Readable for SUBSCRIBE_CAPTURE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [subscribe_capture::W](W) writer structure"] +impl crate::Writable for SUBSCRIBE_CAPTURE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SUBSCRIBE_CAPTURE[%s] +to value 0"] +impl crate::Resettable for SUBSCRIBE_CAPTURE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/timer0_ns/subscribe_clear.rs b/pacs/nrf9120-pac/src/timer0_ns/subscribe_clear.rs new file mode 100644 index 00000000..0930663f --- /dev/null +++ b/pacs/nrf9120-pac/src/timer0_ns/subscribe_clear.rs @@ -0,0 +1,140 @@ +#[doc = "Register `SUBSCRIBE_CLEAR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SUBSCRIBE_CLEAR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CHIDX` reader - DPPI channel that task CLEAR will subscribe to"] +pub type CHIDX_R = crate::FieldReader; +#[doc = "Field `CHIDX` writer - DPPI channel that task CLEAR will subscribe to"] +pub type CHIDX_W<'a, const O: u8> = crate::FieldWriter<'a, u32, SUBSCRIBE_CLEAR_SPEC, u8, u8, 8, O>; +#[doc = "Field `EN` reader - "] +pub type EN_R = crate::BitReader; +#[doc = "\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum EN_A { + #[doc = "0: Disable subscription"] + DISABLED = 0, + #[doc = "1: Enable subscription"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: EN_A) -> Self { + variant as u8 != 0 + } +} +impl EN_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EN_A { + match self.bits { + false => EN_A::DISABLED, + true => EN_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == EN_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == EN_A::ENABLED + } +} +#[doc = "Field `EN` writer - "] +pub type EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, SUBSCRIBE_CLEAR_SPEC, EN_A, O>; +impl<'a, const O: u8> EN_W<'a, O> { + #[doc = "Disable subscription"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(EN_A::DISABLED) + } + #[doc = "Enable subscription"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(EN_A::ENABLED) + } +} +impl R { + #[doc = "Bits 0:7 - DPPI channel that task CLEAR will subscribe to"] + #[inline(always)] + pub fn chidx(&self) -> CHIDX_R { + CHIDX_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&self) -> EN_R { + EN_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:7 - DPPI channel that task CLEAR will subscribe to"] + #[inline(always)] + pub fn chidx(&mut self) -> CHIDX_W<0> { + CHIDX_W::new(self) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&mut self) -> EN_W<31> { + EN_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Subscribe configuration for task CLEAR\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [subscribe_clear](index.html) module"] +pub struct SUBSCRIBE_CLEAR_SPEC; +impl crate::RegisterSpec for SUBSCRIBE_CLEAR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [subscribe_clear::R](R) reader structure"] +impl crate::Readable for SUBSCRIBE_CLEAR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [subscribe_clear::W](W) writer structure"] +impl crate::Writable for SUBSCRIBE_CLEAR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SUBSCRIBE_CLEAR to value 0"] +impl crate::Resettable for SUBSCRIBE_CLEAR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/timer0_ns/subscribe_count.rs b/pacs/nrf9120-pac/src/timer0_ns/subscribe_count.rs new file mode 100644 index 00000000..48d95fa3 --- /dev/null +++ b/pacs/nrf9120-pac/src/timer0_ns/subscribe_count.rs @@ -0,0 +1,140 @@ +#[doc = "Register `SUBSCRIBE_COUNT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SUBSCRIBE_COUNT` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CHIDX` reader - DPPI channel that task COUNT will subscribe to"] +pub type CHIDX_R = crate::FieldReader; +#[doc = "Field `CHIDX` writer - DPPI channel that task COUNT will subscribe to"] +pub type CHIDX_W<'a, const O: u8> = crate::FieldWriter<'a, u32, SUBSCRIBE_COUNT_SPEC, u8, u8, 8, O>; +#[doc = "Field `EN` reader - "] +pub type EN_R = crate::BitReader; +#[doc = "\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum EN_A { + #[doc = "0: Disable subscription"] + DISABLED = 0, + #[doc = "1: Enable subscription"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: EN_A) -> Self { + variant as u8 != 0 + } +} +impl EN_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EN_A { + match self.bits { + false => EN_A::DISABLED, + true => EN_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == EN_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == EN_A::ENABLED + } +} +#[doc = "Field `EN` writer - "] +pub type EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, SUBSCRIBE_COUNT_SPEC, EN_A, O>; +impl<'a, const O: u8> EN_W<'a, O> { + #[doc = "Disable subscription"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(EN_A::DISABLED) + } + #[doc = "Enable subscription"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(EN_A::ENABLED) + } +} +impl R { + #[doc = "Bits 0:7 - DPPI channel that task COUNT will subscribe to"] + #[inline(always)] + pub fn chidx(&self) -> CHIDX_R { + CHIDX_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&self) -> EN_R { + EN_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:7 - DPPI channel that task COUNT will subscribe to"] + #[inline(always)] + pub fn chidx(&mut self) -> CHIDX_W<0> { + CHIDX_W::new(self) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&mut self) -> EN_W<31> { + EN_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Subscribe configuration for task COUNT\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [subscribe_count](index.html) module"] +pub struct SUBSCRIBE_COUNT_SPEC; +impl crate::RegisterSpec for SUBSCRIBE_COUNT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [subscribe_count::R](R) reader structure"] +impl crate::Readable for SUBSCRIBE_COUNT_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [subscribe_count::W](W) writer structure"] +impl crate::Writable for SUBSCRIBE_COUNT_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SUBSCRIBE_COUNT to value 0"] +impl crate::Resettable for SUBSCRIBE_COUNT_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/timer0_ns/subscribe_shutdown.rs b/pacs/nrf9120-pac/src/timer0_ns/subscribe_shutdown.rs new file mode 100644 index 00000000..9b3bbe9a --- /dev/null +++ b/pacs/nrf9120-pac/src/timer0_ns/subscribe_shutdown.rs @@ -0,0 +1,141 @@ +#[doc = "Register `SUBSCRIBE_SHUTDOWN` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SUBSCRIBE_SHUTDOWN` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CHIDX` reader - DPPI channel that task SHUTDOWN will subscribe to"] +pub type CHIDX_R = crate::FieldReader; +#[doc = "Field `CHIDX` writer - DPPI channel that task SHUTDOWN will subscribe to"] +pub type CHIDX_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, SUBSCRIBE_SHUTDOWN_SPEC, u8, u8, 8, O>; +#[doc = "Field `EN` reader - "] +pub type EN_R = crate::BitReader; +#[doc = "\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum EN_A { + #[doc = "0: Disable subscription"] + DISABLED = 0, + #[doc = "1: Enable subscription"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: EN_A) -> Self { + variant as u8 != 0 + } +} +impl EN_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EN_A { + match self.bits { + false => EN_A::DISABLED, + true => EN_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == EN_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == EN_A::ENABLED + } +} +#[doc = "Field `EN` writer - "] +pub type EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, SUBSCRIBE_SHUTDOWN_SPEC, EN_A, O>; +impl<'a, const O: u8> EN_W<'a, O> { + #[doc = "Disable subscription"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(EN_A::DISABLED) + } + #[doc = "Enable subscription"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(EN_A::ENABLED) + } +} +impl R { + #[doc = "Bits 0:7 - DPPI channel that task SHUTDOWN will subscribe to"] + #[inline(always)] + pub fn chidx(&self) -> CHIDX_R { + CHIDX_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&self) -> EN_R { + EN_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:7 - DPPI channel that task SHUTDOWN will subscribe to"] + #[inline(always)] + pub fn chidx(&mut self) -> CHIDX_W<0> { + CHIDX_W::new(self) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&mut self) -> EN_W<31> { + EN_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Deprecated register - Subscribe configuration for task SHUTDOWN\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [subscribe_shutdown](index.html) module"] +pub struct SUBSCRIBE_SHUTDOWN_SPEC; +impl crate::RegisterSpec for SUBSCRIBE_SHUTDOWN_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [subscribe_shutdown::R](R) reader structure"] +impl crate::Readable for SUBSCRIBE_SHUTDOWN_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [subscribe_shutdown::W](W) writer structure"] +impl crate::Writable for SUBSCRIBE_SHUTDOWN_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SUBSCRIBE_SHUTDOWN to value 0"] +impl crate::Resettable for SUBSCRIBE_SHUTDOWN_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/timer0_ns/subscribe_start.rs b/pacs/nrf9120-pac/src/timer0_ns/subscribe_start.rs new file mode 100644 index 00000000..fb9deced --- /dev/null +++ b/pacs/nrf9120-pac/src/timer0_ns/subscribe_start.rs @@ -0,0 +1,140 @@ +#[doc = "Register `SUBSCRIBE_START` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SUBSCRIBE_START` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CHIDX` reader - DPPI channel that task START will subscribe to"] +pub type CHIDX_R = crate::FieldReader; +#[doc = "Field `CHIDX` writer - DPPI channel that task START will subscribe to"] +pub type CHIDX_W<'a, const O: u8> = crate::FieldWriter<'a, u32, SUBSCRIBE_START_SPEC, u8, u8, 8, O>; +#[doc = "Field `EN` reader - "] +pub type EN_R = crate::BitReader; +#[doc = "\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum EN_A { + #[doc = "0: Disable subscription"] + DISABLED = 0, + #[doc = "1: Enable subscription"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: EN_A) -> Self { + variant as u8 != 0 + } +} +impl EN_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EN_A { + match self.bits { + false => EN_A::DISABLED, + true => EN_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == EN_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == EN_A::ENABLED + } +} +#[doc = "Field `EN` writer - "] +pub type EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, SUBSCRIBE_START_SPEC, EN_A, O>; +impl<'a, const O: u8> EN_W<'a, O> { + #[doc = "Disable subscription"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(EN_A::DISABLED) + } + #[doc = "Enable subscription"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(EN_A::ENABLED) + } +} +impl R { + #[doc = "Bits 0:7 - DPPI channel that task START will subscribe to"] + #[inline(always)] + pub fn chidx(&self) -> CHIDX_R { + CHIDX_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&self) -> EN_R { + EN_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:7 - DPPI channel that task START will subscribe to"] + #[inline(always)] + pub fn chidx(&mut self) -> CHIDX_W<0> { + CHIDX_W::new(self) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&mut self) -> EN_W<31> { + EN_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Subscribe configuration for task START\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [subscribe_start](index.html) module"] +pub struct SUBSCRIBE_START_SPEC; +impl crate::RegisterSpec for SUBSCRIBE_START_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [subscribe_start::R](R) reader structure"] +impl crate::Readable for SUBSCRIBE_START_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [subscribe_start::W](W) writer structure"] +impl crate::Writable for SUBSCRIBE_START_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SUBSCRIBE_START to value 0"] +impl crate::Resettable for SUBSCRIBE_START_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/timer0_ns/subscribe_stop.rs b/pacs/nrf9120-pac/src/timer0_ns/subscribe_stop.rs new file mode 100644 index 00000000..2fe3af58 --- /dev/null +++ b/pacs/nrf9120-pac/src/timer0_ns/subscribe_stop.rs @@ -0,0 +1,140 @@ +#[doc = "Register `SUBSCRIBE_STOP` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SUBSCRIBE_STOP` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CHIDX` reader - DPPI channel that task STOP will subscribe to"] +pub type CHIDX_R = crate::FieldReader; +#[doc = "Field `CHIDX` writer - DPPI channel that task STOP will subscribe to"] +pub type CHIDX_W<'a, const O: u8> = crate::FieldWriter<'a, u32, SUBSCRIBE_STOP_SPEC, u8, u8, 8, O>; +#[doc = "Field `EN` reader - "] +pub type EN_R = crate::BitReader; +#[doc = "\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum EN_A { + #[doc = "0: Disable subscription"] + DISABLED = 0, + #[doc = "1: Enable subscription"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: EN_A) -> Self { + variant as u8 != 0 + } +} +impl EN_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EN_A { + match self.bits { + false => EN_A::DISABLED, + true => EN_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == EN_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == EN_A::ENABLED + } +} +#[doc = "Field `EN` writer - "] +pub type EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, SUBSCRIBE_STOP_SPEC, EN_A, O>; +impl<'a, const O: u8> EN_W<'a, O> { + #[doc = "Disable subscription"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(EN_A::DISABLED) + } + #[doc = "Enable subscription"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(EN_A::ENABLED) + } +} +impl R { + #[doc = "Bits 0:7 - DPPI channel that task STOP will subscribe to"] + #[inline(always)] + pub fn chidx(&self) -> CHIDX_R { + CHIDX_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&self) -> EN_R { + EN_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:7 - DPPI channel that task STOP will subscribe to"] + #[inline(always)] + pub fn chidx(&mut self) -> CHIDX_W<0> { + CHIDX_W::new(self) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&mut self) -> EN_W<31> { + EN_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Subscribe configuration for task STOP\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [subscribe_stop](index.html) module"] +pub struct SUBSCRIBE_STOP_SPEC; +impl crate::RegisterSpec for SUBSCRIBE_STOP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [subscribe_stop::R](R) reader structure"] +impl crate::Readable for SUBSCRIBE_STOP_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [subscribe_stop::W](W) writer structure"] +impl crate::Writable for SUBSCRIBE_STOP_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SUBSCRIBE_STOP to value 0"] +impl crate::Resettable for SUBSCRIBE_STOP_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/timer0_ns/tasks_capture.rs b/pacs/nrf9120-pac/src/timer0_ns/tasks_capture.rs new file mode 100644 index 00000000..98477691 --- /dev/null +++ b/pacs/nrf9120-pac/src/timer0_ns/tasks_capture.rs @@ -0,0 +1,77 @@ +#[doc = "Register `TASKS_CAPTURE[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Capture Timer value to CC\\[n\\] +register\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum TASKS_CAPTURE_AW { + #[doc = "1: Trigger task"] + TRIGGER = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TASKS_CAPTURE_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TASKS_CAPTURE` writer - Capture Timer value to CC\\[n\\] +register"] +pub type TASKS_CAPTURE_W<'a, const O: u8> = + crate::BitWriter<'a, u32, TASKS_CAPTURE_SPEC, TASKS_CAPTURE_AW, O>; +impl<'a, const O: u8> TASKS_CAPTURE_W<'a, O> { + #[doc = "Trigger task"] + #[inline(always)] + pub fn trigger(self) -> &'a mut W { + self.variant(TASKS_CAPTURE_AW::TRIGGER) + } +} +impl W { + #[doc = "Bit 0 - Capture Timer value to CC\\[n\\] +register"] + #[inline(always)] + pub fn tasks_capture(&mut self) -> TASKS_CAPTURE_W<0> { + TASKS_CAPTURE_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Description collection: Capture Timer value to CC\\[n\\] +register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tasks_capture](index.html) module"] +pub struct TASKS_CAPTURE_SPEC; +impl crate::RegisterSpec for TASKS_CAPTURE_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [tasks_capture::W](W) writer structure"] +impl crate::Writable for TASKS_CAPTURE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets TASKS_CAPTURE[%s] +to value 0"] +impl crate::Resettable for TASKS_CAPTURE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/timer0_ns/tasks_clear.rs b/pacs/nrf9120-pac/src/timer0_ns/tasks_clear.rs new file mode 100644 index 00000000..0e39565a --- /dev/null +++ b/pacs/nrf9120-pac/src/timer0_ns/tasks_clear.rs @@ -0,0 +1,72 @@ +#[doc = "Register `TASKS_CLEAR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Clear time\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum TASKS_CLEAR_AW { + #[doc = "1: Trigger task"] + TRIGGER = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TASKS_CLEAR_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TASKS_CLEAR` writer - Clear time"] +pub type TASKS_CLEAR_W<'a, const O: u8> = + crate::BitWriter<'a, u32, TASKS_CLEAR_SPEC, TASKS_CLEAR_AW, O>; +impl<'a, const O: u8> TASKS_CLEAR_W<'a, O> { + #[doc = "Trigger task"] + #[inline(always)] + pub fn trigger(self) -> &'a mut W { + self.variant(TASKS_CLEAR_AW::TRIGGER) + } +} +impl W { + #[doc = "Bit 0 - Clear time"] + #[inline(always)] + pub fn tasks_clear(&mut self) -> TASKS_CLEAR_W<0> { + TASKS_CLEAR_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Clear time\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tasks_clear](index.html) module"] +pub struct TASKS_CLEAR_SPEC; +impl crate::RegisterSpec for TASKS_CLEAR_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [tasks_clear::W](W) writer structure"] +impl crate::Writable for TASKS_CLEAR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets TASKS_CLEAR to value 0"] +impl crate::Resettable for TASKS_CLEAR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/timer0_ns/tasks_count.rs b/pacs/nrf9120-pac/src/timer0_ns/tasks_count.rs new file mode 100644 index 00000000..d0836d73 --- /dev/null +++ b/pacs/nrf9120-pac/src/timer0_ns/tasks_count.rs @@ -0,0 +1,72 @@ +#[doc = "Register `TASKS_COUNT` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Increment Timer (Counter mode only)\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum TASKS_COUNT_AW { + #[doc = "1: Trigger task"] + TRIGGER = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TASKS_COUNT_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TASKS_COUNT` writer - Increment Timer (Counter mode only)"] +pub type TASKS_COUNT_W<'a, const O: u8> = + crate::BitWriter<'a, u32, TASKS_COUNT_SPEC, TASKS_COUNT_AW, O>; +impl<'a, const O: u8> TASKS_COUNT_W<'a, O> { + #[doc = "Trigger task"] + #[inline(always)] + pub fn trigger(self) -> &'a mut W { + self.variant(TASKS_COUNT_AW::TRIGGER) + } +} +impl W { + #[doc = "Bit 0 - Increment Timer (Counter mode only)"] + #[inline(always)] + pub fn tasks_count(&mut self) -> TASKS_COUNT_W<0> { + TASKS_COUNT_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Increment Timer (Counter mode only)\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tasks_count](index.html) module"] +pub struct TASKS_COUNT_SPEC; +impl crate::RegisterSpec for TASKS_COUNT_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [tasks_count::W](W) writer structure"] +impl crate::Writable for TASKS_COUNT_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets TASKS_COUNT to value 0"] +impl crate::Resettable for TASKS_COUNT_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/timer0_ns/tasks_shutdown.rs b/pacs/nrf9120-pac/src/timer0_ns/tasks_shutdown.rs new file mode 100644 index 00000000..d889cf4b --- /dev/null +++ b/pacs/nrf9120-pac/src/timer0_ns/tasks_shutdown.rs @@ -0,0 +1,72 @@ +#[doc = "Register `TASKS_SHUTDOWN` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Deprecated field - Shut down timer\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum TASKS_SHUTDOWN_AW { + #[doc = "1: Trigger task"] + TRIGGER = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TASKS_SHUTDOWN_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TASKS_SHUTDOWN` writer - Deprecated field - Shut down timer"] +pub type TASKS_SHUTDOWN_W<'a, const O: u8> = + crate::BitWriter<'a, u32, TASKS_SHUTDOWN_SPEC, TASKS_SHUTDOWN_AW, O>; +impl<'a, const O: u8> TASKS_SHUTDOWN_W<'a, O> { + #[doc = "Trigger task"] + #[inline(always)] + pub fn trigger(self) -> &'a mut W { + self.variant(TASKS_SHUTDOWN_AW::TRIGGER) + } +} +impl W { + #[doc = "Bit 0 - Deprecated field - Shut down timer"] + #[inline(always)] + pub fn tasks_shutdown(&mut self) -> TASKS_SHUTDOWN_W<0> { + TASKS_SHUTDOWN_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Deprecated register - Shut down timer\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tasks_shutdown](index.html) module"] +pub struct TASKS_SHUTDOWN_SPEC; +impl crate::RegisterSpec for TASKS_SHUTDOWN_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [tasks_shutdown::W](W) writer structure"] +impl crate::Writable for TASKS_SHUTDOWN_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets TASKS_SHUTDOWN to value 0"] +impl crate::Resettable for TASKS_SHUTDOWN_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/timer0_ns/tasks_start.rs b/pacs/nrf9120-pac/src/timer0_ns/tasks_start.rs new file mode 100644 index 00000000..d7c11b0d --- /dev/null +++ b/pacs/nrf9120-pac/src/timer0_ns/tasks_start.rs @@ -0,0 +1,72 @@ +#[doc = "Register `TASKS_START` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Start Timer\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum TASKS_START_AW { + #[doc = "1: Trigger task"] + TRIGGER = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TASKS_START_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TASKS_START` writer - Start Timer"] +pub type TASKS_START_W<'a, const O: u8> = + crate::BitWriter<'a, u32, TASKS_START_SPEC, TASKS_START_AW, O>; +impl<'a, const O: u8> TASKS_START_W<'a, O> { + #[doc = "Trigger task"] + #[inline(always)] + pub fn trigger(self) -> &'a mut W { + self.variant(TASKS_START_AW::TRIGGER) + } +} +impl W { + #[doc = "Bit 0 - Start Timer"] + #[inline(always)] + pub fn tasks_start(&mut self) -> TASKS_START_W<0> { + TASKS_START_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Start Timer\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tasks_start](index.html) module"] +pub struct TASKS_START_SPEC; +impl crate::RegisterSpec for TASKS_START_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [tasks_start::W](W) writer structure"] +impl crate::Writable for TASKS_START_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets TASKS_START to value 0"] +impl crate::Resettable for TASKS_START_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/timer0_ns/tasks_stop.rs b/pacs/nrf9120-pac/src/timer0_ns/tasks_stop.rs new file mode 100644 index 00000000..05b7ee27 --- /dev/null +++ b/pacs/nrf9120-pac/src/timer0_ns/tasks_stop.rs @@ -0,0 +1,72 @@ +#[doc = "Register `TASKS_STOP` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Stop Timer\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum TASKS_STOP_AW { + #[doc = "1: Trigger task"] + TRIGGER = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TASKS_STOP_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TASKS_STOP` writer - Stop Timer"] +pub type TASKS_STOP_W<'a, const O: u8> = + crate::BitWriter<'a, u32, TASKS_STOP_SPEC, TASKS_STOP_AW, O>; +impl<'a, const O: u8> TASKS_STOP_W<'a, O> { + #[doc = "Trigger task"] + #[inline(always)] + pub fn trigger(self) -> &'a mut W { + self.variant(TASKS_STOP_AW::TRIGGER) + } +} +impl W { + #[doc = "Bit 0 - Stop Timer"] + #[inline(always)] + pub fn tasks_stop(&mut self) -> TASKS_STOP_W<0> { + TASKS_STOP_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Stop Timer\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tasks_stop](index.html) module"] +pub struct TASKS_STOP_SPEC; +impl crate::RegisterSpec for TASKS_STOP_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [tasks_stop::W](W) writer structure"] +impl crate::Writable for TASKS_STOP_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets TASKS_STOP to value 0"] +impl crate::Resettable for TASKS_STOP_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/twim0_ns.rs b/pacs/nrf9120-pac/src/twim0_ns.rs new file mode 100644 index 00000000..66d4d747 --- /dev/null +++ b/pacs/nrf9120-pac/src/twim0_ns.rs @@ -0,0 +1,240 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Start TWI receive sequence"] + pub tasks_startrx: TASKS_STARTRX, + _reserved1: [u8; 0x04], + #[doc = "0x08 - Start TWI transmit sequence"] + pub tasks_starttx: TASKS_STARTTX, + _reserved2: [u8; 0x08], + #[doc = "0x14 - Stop TWI transaction. Must be issued while the TWI master is not suspended."] + pub tasks_stop: TASKS_STOP, + _reserved3: [u8; 0x04], + #[doc = "0x1c - Suspend TWI transaction"] + pub tasks_suspend: TASKS_SUSPEND, + #[doc = "0x20 - Resume TWI transaction"] + pub tasks_resume: TASKS_RESUME, + _reserved5: [u8; 0x5c], + #[doc = "0x80 - Subscribe configuration for task STARTRX"] + pub subscribe_startrx: SUBSCRIBE_STARTRX, + _reserved6: [u8; 0x04], + #[doc = "0x88 - Subscribe configuration for task STARTTX"] + pub subscribe_starttx: SUBSCRIBE_STARTTX, + _reserved7: [u8; 0x08], + #[doc = "0x94 - Subscribe configuration for task STOP"] + pub subscribe_stop: SUBSCRIBE_STOP, + _reserved8: [u8; 0x04], + #[doc = "0x9c - Subscribe configuration for task SUSPEND"] + pub subscribe_suspend: SUBSCRIBE_SUSPEND, + #[doc = "0xa0 - Subscribe configuration for task RESUME"] + pub subscribe_resume: SUBSCRIBE_RESUME, + _reserved10: [u8; 0x60], + #[doc = "0x104 - TWI stopped"] + pub events_stopped: EVENTS_STOPPED, + _reserved11: [u8; 0x1c], + #[doc = "0x124 - TWI error"] + pub events_error: EVENTS_ERROR, + _reserved12: [u8; 0x20], + #[doc = "0x148 - SUSPEND task has been issued, TWI traffic is now suspended."] + pub events_suspended: EVENTS_SUSPENDED, + #[doc = "0x14c - Receive sequence started"] + pub events_rxstarted: EVENTS_RXSTARTED, + #[doc = "0x150 - Transmit sequence started"] + pub events_txstarted: EVENTS_TXSTARTED, + _reserved15: [u8; 0x08], + #[doc = "0x15c - Byte boundary, starting to receive the last byte"] + pub events_lastrx: EVENTS_LASTRX, + #[doc = "0x160 - Byte boundary, starting to transmit the last byte"] + pub events_lasttx: EVENTS_LASTTX, + _reserved17: [u8; 0x20], + #[doc = "0x184 - Publish configuration for event STOPPED"] + pub publish_stopped: PUBLISH_STOPPED, + _reserved18: [u8; 0x1c], + #[doc = "0x1a4 - Publish configuration for event ERROR"] + pub publish_error: PUBLISH_ERROR, + _reserved19: [u8; 0x20], + #[doc = "0x1c8 - Publish configuration for event SUSPENDED"] + pub publish_suspended: PUBLISH_SUSPENDED, + #[doc = "0x1cc - Publish configuration for event RXSTARTED"] + pub publish_rxstarted: PUBLISH_RXSTARTED, + #[doc = "0x1d0 - Publish configuration for event TXSTARTED"] + pub publish_txstarted: PUBLISH_TXSTARTED, + _reserved22: [u8; 0x08], + #[doc = "0x1dc - Publish configuration for event LASTRX"] + pub publish_lastrx: PUBLISH_LASTRX, + #[doc = "0x1e0 - Publish configuration for event LASTTX"] + pub publish_lasttx: PUBLISH_LASTTX, + _reserved24: [u8; 0x1c], + #[doc = "0x200 - Shortcuts between local events and tasks"] + pub shorts: SHORTS, + _reserved25: [u8; 0xfc], + #[doc = "0x300 - Enable or disable interrupt"] + pub inten: INTEN, + #[doc = "0x304 - Enable interrupt"] + pub intenset: INTENSET, + #[doc = "0x308 - Disable interrupt"] + pub intenclr: INTENCLR, + _reserved28: [u8; 0x01b8], + #[doc = "0x4c4 - Error source"] + pub errorsrc: ERRORSRC, + _reserved29: [u8; 0x38], + #[doc = "0x500 - Enable TWIM"] + pub enable: ENABLE, + _reserved30: [u8; 0x04], + #[doc = "0x508..0x510 - Unspecified"] + pub psel: PSEL, + _reserved31: [u8; 0x14], + #[doc = "0x524 - TWI frequency. Accuracy depends on the HFCLK source selected."] + pub frequency: FREQUENCY, + _reserved32: [u8; 0x0c], + #[doc = "0x534..0x544 - RXD EasyDMA channel"] + pub rxd: RXD, + #[doc = "0x544..0x554 - TXD EasyDMA channel"] + pub txd: TXD, + _reserved34: [u8; 0x34], + #[doc = "0x588 - Address used in the TWI transfer"] + pub address: ADDRESS, +} +#[doc = "TASKS_STARTRX (w) register accessor: an alias for `Reg`"] +pub type TASKS_STARTRX = crate::Reg; +#[doc = "Start TWI receive sequence"] +pub mod tasks_startrx; +#[doc = "TASKS_STARTTX (w) register accessor: an alias for `Reg`"] +pub type TASKS_STARTTX = crate::Reg; +#[doc = "Start TWI transmit sequence"] +pub mod tasks_starttx; +#[doc = "TASKS_STOP (w) register accessor: an alias for `Reg`"] +pub type TASKS_STOP = crate::Reg; +#[doc = "Stop TWI transaction. Must be issued while the TWI master is not suspended."] +pub mod tasks_stop; +#[doc = "TASKS_SUSPEND (w) register accessor: an alias for `Reg`"] +pub type TASKS_SUSPEND = crate::Reg; +#[doc = "Suspend TWI transaction"] +pub mod tasks_suspend; +#[doc = "TASKS_RESUME (w) register accessor: an alias for `Reg`"] +pub type TASKS_RESUME = crate::Reg; +#[doc = "Resume TWI transaction"] +pub mod tasks_resume; +#[doc = "SUBSCRIBE_STARTRX (rw) register accessor: an alias for `Reg`"] +pub type SUBSCRIBE_STARTRX = crate::Reg; +#[doc = "Subscribe configuration for task STARTRX"] +pub mod subscribe_startrx; +#[doc = "SUBSCRIBE_STARTTX (rw) register accessor: an alias for `Reg`"] +pub type SUBSCRIBE_STARTTX = crate::Reg; +#[doc = "Subscribe configuration for task STARTTX"] +pub mod subscribe_starttx; +#[doc = "SUBSCRIBE_STOP (rw) register accessor: an alias for `Reg`"] +pub type SUBSCRIBE_STOP = crate::Reg; +#[doc = "Subscribe configuration for task STOP"] +pub mod subscribe_stop; +#[doc = "SUBSCRIBE_SUSPEND (rw) register accessor: an alias for `Reg`"] +pub type SUBSCRIBE_SUSPEND = crate::Reg; +#[doc = "Subscribe configuration for task SUSPEND"] +pub mod subscribe_suspend; +#[doc = "SUBSCRIBE_RESUME (rw) register accessor: an alias for `Reg`"] +pub type SUBSCRIBE_RESUME = crate::Reg; +#[doc = "Subscribe configuration for task RESUME"] +pub mod subscribe_resume; +#[doc = "EVENTS_STOPPED (rw) register accessor: an alias for `Reg`"] +pub type EVENTS_STOPPED = crate::Reg; +#[doc = "TWI stopped"] +pub mod events_stopped; +#[doc = "EVENTS_ERROR (rw) register accessor: an alias for `Reg`"] +pub type EVENTS_ERROR = crate::Reg; +#[doc = "TWI error"] +pub mod events_error; +#[doc = "EVENTS_SUSPENDED (rw) register accessor: an alias for `Reg`"] +pub type EVENTS_SUSPENDED = crate::Reg; +#[doc = "SUSPEND task has been issued, TWI traffic is now suspended."] +pub mod events_suspended; +#[doc = "EVENTS_RXSTARTED (rw) register accessor: an alias for `Reg`"] +pub type EVENTS_RXSTARTED = crate::Reg; +#[doc = "Receive sequence started"] +pub mod events_rxstarted; +#[doc = "EVENTS_TXSTARTED (rw) register accessor: an alias for `Reg`"] +pub type EVENTS_TXSTARTED = crate::Reg; +#[doc = "Transmit sequence started"] +pub mod events_txstarted; +#[doc = "EVENTS_LASTRX (rw) register accessor: an alias for `Reg`"] +pub type EVENTS_LASTRX = crate::Reg; +#[doc = "Byte boundary, starting to receive the last byte"] +pub mod events_lastrx; +#[doc = "EVENTS_LASTTX (rw) register accessor: an alias for `Reg`"] +pub type EVENTS_LASTTX = crate::Reg; +#[doc = "Byte boundary, starting to transmit the last byte"] +pub mod events_lasttx; +#[doc = "PUBLISH_STOPPED (rw) register accessor: an alias for `Reg`"] +pub type PUBLISH_STOPPED = crate::Reg; +#[doc = "Publish configuration for event STOPPED"] +pub mod publish_stopped; +#[doc = "PUBLISH_ERROR (rw) register accessor: an alias for `Reg`"] +pub type PUBLISH_ERROR = crate::Reg; +#[doc = "Publish configuration for event ERROR"] +pub mod publish_error; +#[doc = "PUBLISH_SUSPENDED (rw) register accessor: an alias for `Reg`"] +pub type PUBLISH_SUSPENDED = crate::Reg; +#[doc = "Publish configuration for event SUSPENDED"] +pub mod publish_suspended; +#[doc = "PUBLISH_RXSTARTED (rw) register accessor: an alias for `Reg`"] +pub type PUBLISH_RXSTARTED = crate::Reg; +#[doc = "Publish configuration for event RXSTARTED"] +pub mod publish_rxstarted; +#[doc = "PUBLISH_TXSTARTED (rw) register accessor: an alias for `Reg`"] +pub type PUBLISH_TXSTARTED = crate::Reg; +#[doc = "Publish configuration for event TXSTARTED"] +pub mod publish_txstarted; +#[doc = "PUBLISH_LASTRX (rw) register accessor: an alias for `Reg`"] +pub type PUBLISH_LASTRX = crate::Reg; +#[doc = "Publish configuration for event LASTRX"] +pub mod publish_lastrx; +#[doc = "PUBLISH_LASTTX (rw) register accessor: an alias for `Reg`"] +pub type PUBLISH_LASTTX = crate::Reg; +#[doc = "Publish configuration for event LASTTX"] +pub mod publish_lasttx; +#[doc = "SHORTS (rw) register accessor: an alias for `Reg`"] +pub type SHORTS = crate::Reg; +#[doc = "Shortcuts between local events and tasks"] +pub mod shorts; +#[doc = "INTEN (rw) register accessor: an alias for `Reg`"] +pub type INTEN = crate::Reg; +#[doc = "Enable or disable interrupt"] +pub mod inten; +#[doc = "INTENSET (rw) register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "Enable interrupt"] +pub mod intenset; +#[doc = "INTENCLR (rw) register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "Disable interrupt"] +pub mod intenclr; +#[doc = "ERRORSRC (rw) register accessor: an alias for `Reg`"] +pub type ERRORSRC = crate::Reg; +#[doc = "Error source"] +pub mod errorsrc; +#[doc = "ENABLE (rw) register accessor: an alias for `Reg`"] +pub type ENABLE = crate::Reg; +#[doc = "Enable TWIM"] +pub mod enable; +#[doc = "Unspecified"] +pub use psel::PSEL; +#[doc = r"Cluster"] +#[doc = "Unspecified"] +pub mod psel; +#[doc = "FREQUENCY (rw) register accessor: an alias for `Reg`"] +pub type FREQUENCY = crate::Reg; +#[doc = "TWI frequency. Accuracy depends on the HFCLK source selected."] +pub mod frequency; +#[doc = "RXD EasyDMA channel"] +pub use rxd::RXD; +#[doc = r"Cluster"] +#[doc = "RXD EasyDMA channel"] +pub mod rxd; +#[doc = "TXD EasyDMA channel"] +pub use txd::TXD; +#[doc = r"Cluster"] +#[doc = "TXD EasyDMA channel"] +pub mod txd; +#[doc = "ADDRESS (rw) register accessor: an alias for `Reg`"] +pub type ADDRESS = crate::Reg; +#[doc = "Address used in the TWI transfer"] +pub mod address; diff --git a/pacs/nrf9120-pac/src/twim0_ns/address.rs b/pacs/nrf9120-pac/src/twim0_ns/address.rs new file mode 100644 index 00000000..147a4c76 --- /dev/null +++ b/pacs/nrf9120-pac/src/twim0_ns/address.rs @@ -0,0 +1,80 @@ +#[doc = "Register `ADDRESS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `ADDRESS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ADDRESS` reader - Address used in the TWI transfer"] +pub type ADDRESS_R = crate::FieldReader; +#[doc = "Field `ADDRESS` writer - Address used in the TWI transfer"] +pub type ADDRESS_W<'a, const O: u8> = crate::FieldWriter<'a, u32, ADDRESS_SPEC, u8, u8, 7, O>; +impl R { + #[doc = "Bits 0:6 - Address used in the TWI transfer"] + #[inline(always)] + pub fn address(&self) -> ADDRESS_R { + ADDRESS_R::new((self.bits & 0x7f) as u8) + } +} +impl W { + #[doc = "Bits 0:6 - Address used in the TWI transfer"] + #[inline(always)] + pub fn address(&mut self) -> ADDRESS_W<0> { + ADDRESS_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Address used in the TWI transfer\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [address](index.html) module"] +pub struct ADDRESS_SPEC; +impl crate::RegisterSpec for ADDRESS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [address::R](R) reader structure"] +impl crate::Readable for ADDRESS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [address::W](W) writer structure"] +impl crate::Writable for ADDRESS_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets ADDRESS to value 0"] +impl crate::Resettable for ADDRESS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/twim0_ns/enable.rs b/pacs/nrf9120-pac/src/twim0_ns/enable.rs new file mode 100644 index 00000000..a293e9c5 --- /dev/null +++ b/pacs/nrf9120-pac/src/twim0_ns/enable.rs @@ -0,0 +1,128 @@ +#[doc = "Register `ENABLE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `ENABLE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ENABLE` reader - Enable or disable TWIM"] +pub type ENABLE_R = crate::FieldReader; +#[doc = "Enable or disable TWIM\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum ENABLE_A { + #[doc = "0: Disable TWIM"] + DISABLED = 0, + #[doc = "6: Enable TWIM"] + ENABLED = 6, +} +impl From for u8 { + #[inline(always)] + fn from(variant: ENABLE_A) -> Self { + variant as _ + } +} +impl ENABLE_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(ENABLE_A::DISABLED), + 6 => Some(ENABLE_A::ENABLED), + _ => None, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == ENABLE_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == ENABLE_A::ENABLED + } +} +#[doc = "Field `ENABLE` writer - Enable or disable TWIM"] +pub type ENABLE_W<'a, const O: u8> = crate::FieldWriter<'a, u32, ENABLE_SPEC, u8, ENABLE_A, 4, O>; +impl<'a, const O: u8> ENABLE_W<'a, O> { + #[doc = "Disable TWIM"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(ENABLE_A::DISABLED) + } + #[doc = "Enable TWIM"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(ENABLE_A::ENABLED) + } +} +impl R { + #[doc = "Bits 0:3 - Enable or disable TWIM"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new((self.bits & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - Enable or disable TWIM"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W<0> { + ENABLE_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Enable TWIM\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [enable](index.html) module"] +pub struct ENABLE_SPEC; +impl crate::RegisterSpec for ENABLE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [enable::R](R) reader structure"] +impl crate::Readable for ENABLE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [enable::W](W) writer structure"] +impl crate::Writable for ENABLE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets ENABLE to value 0"] +impl crate::Resettable for ENABLE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/twim0_ns/errorsrc.rs b/pacs/nrf9120-pac/src/twim0_ns/errorsrc.rs new file mode 100644 index 00000000..53e1c064 --- /dev/null +++ b/pacs/nrf9120-pac/src/twim0_ns/errorsrc.rs @@ -0,0 +1,246 @@ +#[doc = "Register `ERRORSRC` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `ERRORSRC` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `OVERRUN` reader - Overrun error"] +pub type OVERRUN_R = crate::BitReader; +#[doc = "Overrun error\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum OVERRUN_A { + #[doc = "0: Error did not occur"] + NOT_RECEIVED = 0, + #[doc = "1: Error occurred"] + RECEIVED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: OVERRUN_A) -> Self { + variant as u8 != 0 + } +} +impl OVERRUN_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> OVERRUN_A { + match self.bits { + false => OVERRUN_A::NOT_RECEIVED, + true => OVERRUN_A::RECEIVED, + } + } + #[doc = "Checks if the value of the field is `NOT_RECEIVED`"] + #[inline(always)] + pub fn is_not_received(&self) -> bool { + *self == OVERRUN_A::NOT_RECEIVED + } + #[doc = "Checks if the value of the field is `RECEIVED`"] + #[inline(always)] + pub fn is_received(&self) -> bool { + *self == OVERRUN_A::RECEIVED + } +} +#[doc = "Field `OVERRUN` writer - Overrun error"] +pub type OVERRUN_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, ERRORSRC_SPEC, OVERRUN_A, O>; +impl<'a, const O: u8> OVERRUN_W<'a, O> { + #[doc = "Error did not occur"] + #[inline(always)] + pub fn not_received(self) -> &'a mut W { + self.variant(OVERRUN_A::NOT_RECEIVED) + } + #[doc = "Error occurred"] + #[inline(always)] + pub fn received(self) -> &'a mut W { + self.variant(OVERRUN_A::RECEIVED) + } +} +#[doc = "Field `ANACK` reader - NACK received after sending the address (write '1' to clear)"] +pub type ANACK_R = crate::BitReader; +#[doc = "NACK received after sending the address (write '1' to clear)\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum ANACK_A { + #[doc = "0: Error did not occur"] + NOT_RECEIVED = 0, + #[doc = "1: Error occurred"] + RECEIVED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: ANACK_A) -> Self { + variant as u8 != 0 + } +} +impl ANACK_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> ANACK_A { + match self.bits { + false => ANACK_A::NOT_RECEIVED, + true => ANACK_A::RECEIVED, + } + } + #[doc = "Checks if the value of the field is `NOT_RECEIVED`"] + #[inline(always)] + pub fn is_not_received(&self) -> bool { + *self == ANACK_A::NOT_RECEIVED + } + #[doc = "Checks if the value of the field is `RECEIVED`"] + #[inline(always)] + pub fn is_received(&self) -> bool { + *self == ANACK_A::RECEIVED + } +} +#[doc = "Field `ANACK` writer - NACK received after sending the address (write '1' to clear)"] +pub type ANACK_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, ERRORSRC_SPEC, ANACK_A, O>; +impl<'a, const O: u8> ANACK_W<'a, O> { + #[doc = "Error did not occur"] + #[inline(always)] + pub fn not_received(self) -> &'a mut W { + self.variant(ANACK_A::NOT_RECEIVED) + } + #[doc = "Error occurred"] + #[inline(always)] + pub fn received(self) -> &'a mut W { + self.variant(ANACK_A::RECEIVED) + } +} +#[doc = "Field `DNACK` reader - NACK received after sending a data byte (write '1' to clear)"] +pub type DNACK_R = crate::BitReader; +#[doc = "NACK received after sending a data byte (write '1' to clear)\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum DNACK_A { + #[doc = "0: Error did not occur"] + NOT_RECEIVED = 0, + #[doc = "1: Error occurred"] + RECEIVED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: DNACK_A) -> Self { + variant as u8 != 0 + } +} +impl DNACK_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> DNACK_A { + match self.bits { + false => DNACK_A::NOT_RECEIVED, + true => DNACK_A::RECEIVED, + } + } + #[doc = "Checks if the value of the field is `NOT_RECEIVED`"] + #[inline(always)] + pub fn is_not_received(&self) -> bool { + *self == DNACK_A::NOT_RECEIVED + } + #[doc = "Checks if the value of the field is `RECEIVED`"] + #[inline(always)] + pub fn is_received(&self) -> bool { + *self == DNACK_A::RECEIVED + } +} +#[doc = "Field `DNACK` writer - NACK received after sending a data byte (write '1' to clear)"] +pub type DNACK_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, ERRORSRC_SPEC, DNACK_A, O>; +impl<'a, const O: u8> DNACK_W<'a, O> { + #[doc = "Error did not occur"] + #[inline(always)] + pub fn not_received(self) -> &'a mut W { + self.variant(DNACK_A::NOT_RECEIVED) + } + #[doc = "Error occurred"] + #[inline(always)] + pub fn received(self) -> &'a mut W { + self.variant(DNACK_A::RECEIVED) + } +} +impl R { + #[doc = "Bit 0 - Overrun error"] + #[inline(always)] + pub fn overrun(&self) -> OVERRUN_R { + OVERRUN_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - NACK received after sending the address (write '1' to clear)"] + #[inline(always)] + pub fn anack(&self) -> ANACK_R { + ANACK_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - NACK received after sending a data byte (write '1' to clear)"] + #[inline(always)] + pub fn dnack(&self) -> DNACK_R { + DNACK_R::new(((self.bits >> 2) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Overrun error"] + #[inline(always)] + pub fn overrun(&mut self) -> OVERRUN_W<0> { + OVERRUN_W::new(self) + } + #[doc = "Bit 1 - NACK received after sending the address (write '1' to clear)"] + #[inline(always)] + pub fn anack(&mut self) -> ANACK_W<1> { + ANACK_W::new(self) + } + #[doc = "Bit 2 - NACK received after sending a data byte (write '1' to clear)"] + #[inline(always)] + pub fn dnack(&mut self) -> DNACK_W<2> { + DNACK_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Error source\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [errorsrc](index.html) module"] +pub struct ERRORSRC_SPEC; +impl crate::RegisterSpec for ERRORSRC_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [errorsrc::R](R) reader structure"] +impl crate::Readable for ERRORSRC_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [errorsrc::W](W) writer structure"] +impl crate::Writable for ERRORSRC_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets ERRORSRC to value 0"] +impl crate::Resettable for ERRORSRC_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/twim0_ns/events_error.rs b/pacs/nrf9120-pac/src/twim0_ns/events_error.rs new file mode 100644 index 00000000..975b6d4b --- /dev/null +++ b/pacs/nrf9120-pac/src/twim0_ns/events_error.rs @@ -0,0 +1,127 @@ +#[doc = "Register `EVENTS_ERROR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVENTS_ERROR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `EVENTS_ERROR` reader - TWI error"] +pub type EVENTS_ERROR_R = crate::BitReader; +#[doc = "TWI error\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum EVENTS_ERROR_A { + #[doc = "0: Event not generated"] + NOT_GENERATED = 0, + #[doc = "1: Event generated"] + GENERATED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: EVENTS_ERROR_A) -> Self { + variant as u8 != 0 + } +} +impl EVENTS_ERROR_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EVENTS_ERROR_A { + match self.bits { + false => EVENTS_ERROR_A::NOT_GENERATED, + true => EVENTS_ERROR_A::GENERATED, + } + } + #[doc = "Checks if the value of the field is `NOT_GENERATED`"] + #[inline(always)] + pub fn is_not_generated(&self) -> bool { + *self == EVENTS_ERROR_A::NOT_GENERATED + } + #[doc = "Checks if the value of the field is `GENERATED`"] + #[inline(always)] + pub fn is_generated(&self) -> bool { + *self == EVENTS_ERROR_A::GENERATED + } +} +#[doc = "Field `EVENTS_ERROR` writer - TWI error"] +pub type EVENTS_ERROR_W<'a, const O: u8> = + crate::BitWriter<'a, u32, EVENTS_ERROR_SPEC, EVENTS_ERROR_A, O>; +impl<'a, const O: u8> EVENTS_ERROR_W<'a, O> { + #[doc = "Event not generated"] + #[inline(always)] + pub fn not_generated(self) -> &'a mut W { + self.variant(EVENTS_ERROR_A::NOT_GENERATED) + } + #[doc = "Event generated"] + #[inline(always)] + pub fn generated(self) -> &'a mut W { + self.variant(EVENTS_ERROR_A::GENERATED) + } +} +impl R { + #[doc = "Bit 0 - TWI error"] + #[inline(always)] + pub fn events_error(&self) -> EVENTS_ERROR_R { + EVENTS_ERROR_R::new((self.bits & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - TWI error"] + #[inline(always)] + pub fn events_error(&mut self) -> EVENTS_ERROR_W<0> { + EVENTS_ERROR_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "TWI error\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [events_error](index.html) module"] +pub struct EVENTS_ERROR_SPEC; +impl crate::RegisterSpec for EVENTS_ERROR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [events_error::R](R) reader structure"] +impl crate::Readable for EVENTS_ERROR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [events_error::W](W) writer structure"] +impl crate::Writable for EVENTS_ERROR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EVENTS_ERROR to value 0"] +impl crate::Resettable for EVENTS_ERROR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/twim0_ns/events_lastrx.rs b/pacs/nrf9120-pac/src/twim0_ns/events_lastrx.rs new file mode 100644 index 00000000..c01f4764 --- /dev/null +++ b/pacs/nrf9120-pac/src/twim0_ns/events_lastrx.rs @@ -0,0 +1,127 @@ +#[doc = "Register `EVENTS_LASTRX` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVENTS_LASTRX` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `EVENTS_LASTRX` reader - Byte boundary, starting to receive the last byte"] +pub type EVENTS_LASTRX_R = crate::BitReader; +#[doc = "Byte boundary, starting to receive the last byte\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum EVENTS_LASTRX_A { + #[doc = "0: Event not generated"] + NOT_GENERATED = 0, + #[doc = "1: Event generated"] + GENERATED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: EVENTS_LASTRX_A) -> Self { + variant as u8 != 0 + } +} +impl EVENTS_LASTRX_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EVENTS_LASTRX_A { + match self.bits { + false => EVENTS_LASTRX_A::NOT_GENERATED, + true => EVENTS_LASTRX_A::GENERATED, + } + } + #[doc = "Checks if the value of the field is `NOT_GENERATED`"] + #[inline(always)] + pub fn is_not_generated(&self) -> bool { + *self == EVENTS_LASTRX_A::NOT_GENERATED + } + #[doc = "Checks if the value of the field is `GENERATED`"] + #[inline(always)] + pub fn is_generated(&self) -> bool { + *self == EVENTS_LASTRX_A::GENERATED + } +} +#[doc = "Field `EVENTS_LASTRX` writer - Byte boundary, starting to receive the last byte"] +pub type EVENTS_LASTRX_W<'a, const O: u8> = + crate::BitWriter<'a, u32, EVENTS_LASTRX_SPEC, EVENTS_LASTRX_A, O>; +impl<'a, const O: u8> EVENTS_LASTRX_W<'a, O> { + #[doc = "Event not generated"] + #[inline(always)] + pub fn not_generated(self) -> &'a mut W { + self.variant(EVENTS_LASTRX_A::NOT_GENERATED) + } + #[doc = "Event generated"] + #[inline(always)] + pub fn generated(self) -> &'a mut W { + self.variant(EVENTS_LASTRX_A::GENERATED) + } +} +impl R { + #[doc = "Bit 0 - Byte boundary, starting to receive the last byte"] + #[inline(always)] + pub fn events_lastrx(&self) -> EVENTS_LASTRX_R { + EVENTS_LASTRX_R::new((self.bits & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Byte boundary, starting to receive the last byte"] + #[inline(always)] + pub fn events_lastrx(&mut self) -> EVENTS_LASTRX_W<0> { + EVENTS_LASTRX_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Byte boundary, starting to receive the last byte\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [events_lastrx](index.html) module"] +pub struct EVENTS_LASTRX_SPEC; +impl crate::RegisterSpec for EVENTS_LASTRX_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [events_lastrx::R](R) reader structure"] +impl crate::Readable for EVENTS_LASTRX_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [events_lastrx::W](W) writer structure"] +impl crate::Writable for EVENTS_LASTRX_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EVENTS_LASTRX to value 0"] +impl crate::Resettable for EVENTS_LASTRX_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/twim0_ns/events_lasttx.rs b/pacs/nrf9120-pac/src/twim0_ns/events_lasttx.rs new file mode 100644 index 00000000..f66b102e --- /dev/null +++ b/pacs/nrf9120-pac/src/twim0_ns/events_lasttx.rs @@ -0,0 +1,127 @@ +#[doc = "Register `EVENTS_LASTTX` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVENTS_LASTTX` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `EVENTS_LASTTX` reader - Byte boundary, starting to transmit the last byte"] +pub type EVENTS_LASTTX_R = crate::BitReader; +#[doc = "Byte boundary, starting to transmit the last byte\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum EVENTS_LASTTX_A { + #[doc = "0: Event not generated"] + NOT_GENERATED = 0, + #[doc = "1: Event generated"] + GENERATED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: EVENTS_LASTTX_A) -> Self { + variant as u8 != 0 + } +} +impl EVENTS_LASTTX_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EVENTS_LASTTX_A { + match self.bits { + false => EVENTS_LASTTX_A::NOT_GENERATED, + true => EVENTS_LASTTX_A::GENERATED, + } + } + #[doc = "Checks if the value of the field is `NOT_GENERATED`"] + #[inline(always)] + pub fn is_not_generated(&self) -> bool { + *self == EVENTS_LASTTX_A::NOT_GENERATED + } + #[doc = "Checks if the value of the field is `GENERATED`"] + #[inline(always)] + pub fn is_generated(&self) -> bool { + *self == EVENTS_LASTTX_A::GENERATED + } +} +#[doc = "Field `EVENTS_LASTTX` writer - Byte boundary, starting to transmit the last byte"] +pub type EVENTS_LASTTX_W<'a, const O: u8> = + crate::BitWriter<'a, u32, EVENTS_LASTTX_SPEC, EVENTS_LASTTX_A, O>; +impl<'a, const O: u8> EVENTS_LASTTX_W<'a, O> { + #[doc = "Event not generated"] + #[inline(always)] + pub fn not_generated(self) -> &'a mut W { + self.variant(EVENTS_LASTTX_A::NOT_GENERATED) + } + #[doc = "Event generated"] + #[inline(always)] + pub fn generated(self) -> &'a mut W { + self.variant(EVENTS_LASTTX_A::GENERATED) + } +} +impl R { + #[doc = "Bit 0 - Byte boundary, starting to transmit the last byte"] + #[inline(always)] + pub fn events_lasttx(&self) -> EVENTS_LASTTX_R { + EVENTS_LASTTX_R::new((self.bits & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Byte boundary, starting to transmit the last byte"] + #[inline(always)] + pub fn events_lasttx(&mut self) -> EVENTS_LASTTX_W<0> { + EVENTS_LASTTX_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Byte boundary, starting to transmit the last byte\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [events_lasttx](index.html) module"] +pub struct EVENTS_LASTTX_SPEC; +impl crate::RegisterSpec for EVENTS_LASTTX_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [events_lasttx::R](R) reader structure"] +impl crate::Readable for EVENTS_LASTTX_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [events_lasttx::W](W) writer structure"] +impl crate::Writable for EVENTS_LASTTX_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EVENTS_LASTTX to value 0"] +impl crate::Resettable for EVENTS_LASTTX_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/twim0_ns/events_rxstarted.rs b/pacs/nrf9120-pac/src/twim0_ns/events_rxstarted.rs new file mode 100644 index 00000000..a4d0bb22 --- /dev/null +++ b/pacs/nrf9120-pac/src/twim0_ns/events_rxstarted.rs @@ -0,0 +1,127 @@ +#[doc = "Register `EVENTS_RXSTARTED` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVENTS_RXSTARTED` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `EVENTS_RXSTARTED` reader - Receive sequence started"] +pub type EVENTS_RXSTARTED_R = crate::BitReader; +#[doc = "Receive sequence started\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum EVENTS_RXSTARTED_A { + #[doc = "0: Event not generated"] + NOT_GENERATED = 0, + #[doc = "1: Event generated"] + GENERATED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: EVENTS_RXSTARTED_A) -> Self { + variant as u8 != 0 + } +} +impl EVENTS_RXSTARTED_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EVENTS_RXSTARTED_A { + match self.bits { + false => EVENTS_RXSTARTED_A::NOT_GENERATED, + true => EVENTS_RXSTARTED_A::GENERATED, + } + } + #[doc = "Checks if the value of the field is `NOT_GENERATED`"] + #[inline(always)] + pub fn is_not_generated(&self) -> bool { + *self == EVENTS_RXSTARTED_A::NOT_GENERATED + } + #[doc = "Checks if the value of the field is `GENERATED`"] + #[inline(always)] + pub fn is_generated(&self) -> bool { + *self == EVENTS_RXSTARTED_A::GENERATED + } +} +#[doc = "Field `EVENTS_RXSTARTED` writer - Receive sequence started"] +pub type EVENTS_RXSTARTED_W<'a, const O: u8> = + crate::BitWriter<'a, u32, EVENTS_RXSTARTED_SPEC, EVENTS_RXSTARTED_A, O>; +impl<'a, const O: u8> EVENTS_RXSTARTED_W<'a, O> { + #[doc = "Event not generated"] + #[inline(always)] + pub fn not_generated(self) -> &'a mut W { + self.variant(EVENTS_RXSTARTED_A::NOT_GENERATED) + } + #[doc = "Event generated"] + #[inline(always)] + pub fn generated(self) -> &'a mut W { + self.variant(EVENTS_RXSTARTED_A::GENERATED) + } +} +impl R { + #[doc = "Bit 0 - Receive sequence started"] + #[inline(always)] + pub fn events_rxstarted(&self) -> EVENTS_RXSTARTED_R { + EVENTS_RXSTARTED_R::new((self.bits & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Receive sequence started"] + #[inline(always)] + pub fn events_rxstarted(&mut self) -> EVENTS_RXSTARTED_W<0> { + EVENTS_RXSTARTED_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Receive sequence started\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [events_rxstarted](index.html) module"] +pub struct EVENTS_RXSTARTED_SPEC; +impl crate::RegisterSpec for EVENTS_RXSTARTED_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [events_rxstarted::R](R) reader structure"] +impl crate::Readable for EVENTS_RXSTARTED_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [events_rxstarted::W](W) writer structure"] +impl crate::Writable for EVENTS_RXSTARTED_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EVENTS_RXSTARTED to value 0"] +impl crate::Resettable for EVENTS_RXSTARTED_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/twim0_ns/events_stopped.rs b/pacs/nrf9120-pac/src/twim0_ns/events_stopped.rs new file mode 100644 index 00000000..25da5392 --- /dev/null +++ b/pacs/nrf9120-pac/src/twim0_ns/events_stopped.rs @@ -0,0 +1,127 @@ +#[doc = "Register `EVENTS_STOPPED` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVENTS_STOPPED` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `EVENTS_STOPPED` reader - TWI stopped"] +pub type EVENTS_STOPPED_R = crate::BitReader; +#[doc = "TWI stopped\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum EVENTS_STOPPED_A { + #[doc = "0: Event not generated"] + NOT_GENERATED = 0, + #[doc = "1: Event generated"] + GENERATED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: EVENTS_STOPPED_A) -> Self { + variant as u8 != 0 + } +} +impl EVENTS_STOPPED_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EVENTS_STOPPED_A { + match self.bits { + false => EVENTS_STOPPED_A::NOT_GENERATED, + true => EVENTS_STOPPED_A::GENERATED, + } + } + #[doc = "Checks if the value of the field is `NOT_GENERATED`"] + #[inline(always)] + pub fn is_not_generated(&self) -> bool { + *self == EVENTS_STOPPED_A::NOT_GENERATED + } + #[doc = "Checks if the value of the field is `GENERATED`"] + #[inline(always)] + pub fn is_generated(&self) -> bool { + *self == EVENTS_STOPPED_A::GENERATED + } +} +#[doc = "Field `EVENTS_STOPPED` writer - TWI stopped"] +pub type EVENTS_STOPPED_W<'a, const O: u8> = + crate::BitWriter<'a, u32, EVENTS_STOPPED_SPEC, EVENTS_STOPPED_A, O>; +impl<'a, const O: u8> EVENTS_STOPPED_W<'a, O> { + #[doc = "Event not generated"] + #[inline(always)] + pub fn not_generated(self) -> &'a mut W { + self.variant(EVENTS_STOPPED_A::NOT_GENERATED) + } + #[doc = "Event generated"] + #[inline(always)] + pub fn generated(self) -> &'a mut W { + self.variant(EVENTS_STOPPED_A::GENERATED) + } +} +impl R { + #[doc = "Bit 0 - TWI stopped"] + #[inline(always)] + pub fn events_stopped(&self) -> EVENTS_STOPPED_R { + EVENTS_STOPPED_R::new((self.bits & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - TWI stopped"] + #[inline(always)] + pub fn events_stopped(&mut self) -> EVENTS_STOPPED_W<0> { + EVENTS_STOPPED_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "TWI stopped\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [events_stopped](index.html) module"] +pub struct EVENTS_STOPPED_SPEC; +impl crate::RegisterSpec for EVENTS_STOPPED_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [events_stopped::R](R) reader structure"] +impl crate::Readable for EVENTS_STOPPED_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [events_stopped::W](W) writer structure"] +impl crate::Writable for EVENTS_STOPPED_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EVENTS_STOPPED to value 0"] +impl crate::Resettable for EVENTS_STOPPED_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/twim0_ns/events_suspended.rs b/pacs/nrf9120-pac/src/twim0_ns/events_suspended.rs new file mode 100644 index 00000000..25e9f704 --- /dev/null +++ b/pacs/nrf9120-pac/src/twim0_ns/events_suspended.rs @@ -0,0 +1,127 @@ +#[doc = "Register `EVENTS_SUSPENDED` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVENTS_SUSPENDED` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `EVENTS_SUSPENDED` reader - SUSPEND task has been issued, TWI traffic is now suspended."] +pub type EVENTS_SUSPENDED_R = crate::BitReader; +#[doc = "SUSPEND task has been issued, TWI traffic is now suspended.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum EVENTS_SUSPENDED_A { + #[doc = "0: Event not generated"] + NOT_GENERATED = 0, + #[doc = "1: Event generated"] + GENERATED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: EVENTS_SUSPENDED_A) -> Self { + variant as u8 != 0 + } +} +impl EVENTS_SUSPENDED_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EVENTS_SUSPENDED_A { + match self.bits { + false => EVENTS_SUSPENDED_A::NOT_GENERATED, + true => EVENTS_SUSPENDED_A::GENERATED, + } + } + #[doc = "Checks if the value of the field is `NOT_GENERATED`"] + #[inline(always)] + pub fn is_not_generated(&self) -> bool { + *self == EVENTS_SUSPENDED_A::NOT_GENERATED + } + #[doc = "Checks if the value of the field is `GENERATED`"] + #[inline(always)] + pub fn is_generated(&self) -> bool { + *self == EVENTS_SUSPENDED_A::GENERATED + } +} +#[doc = "Field `EVENTS_SUSPENDED` writer - SUSPEND task has been issued, TWI traffic is now suspended."] +pub type EVENTS_SUSPENDED_W<'a, const O: u8> = + crate::BitWriter<'a, u32, EVENTS_SUSPENDED_SPEC, EVENTS_SUSPENDED_A, O>; +impl<'a, const O: u8> EVENTS_SUSPENDED_W<'a, O> { + #[doc = "Event not generated"] + #[inline(always)] + pub fn not_generated(self) -> &'a mut W { + self.variant(EVENTS_SUSPENDED_A::NOT_GENERATED) + } + #[doc = "Event generated"] + #[inline(always)] + pub fn generated(self) -> &'a mut W { + self.variant(EVENTS_SUSPENDED_A::GENERATED) + } +} +impl R { + #[doc = "Bit 0 - SUSPEND task has been issued, TWI traffic is now suspended."] + #[inline(always)] + pub fn events_suspended(&self) -> EVENTS_SUSPENDED_R { + EVENTS_SUSPENDED_R::new((self.bits & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - SUSPEND task has been issued, TWI traffic is now suspended."] + #[inline(always)] + pub fn events_suspended(&mut self) -> EVENTS_SUSPENDED_W<0> { + EVENTS_SUSPENDED_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SUSPEND task has been issued, TWI traffic is now suspended.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [events_suspended](index.html) module"] +pub struct EVENTS_SUSPENDED_SPEC; +impl crate::RegisterSpec for EVENTS_SUSPENDED_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [events_suspended::R](R) reader structure"] +impl crate::Readable for EVENTS_SUSPENDED_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [events_suspended::W](W) writer structure"] +impl crate::Writable for EVENTS_SUSPENDED_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EVENTS_SUSPENDED to value 0"] +impl crate::Resettable for EVENTS_SUSPENDED_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/twim0_ns/events_txstarted.rs b/pacs/nrf9120-pac/src/twim0_ns/events_txstarted.rs new file mode 100644 index 00000000..35be4204 --- /dev/null +++ b/pacs/nrf9120-pac/src/twim0_ns/events_txstarted.rs @@ -0,0 +1,127 @@ +#[doc = "Register `EVENTS_TXSTARTED` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVENTS_TXSTARTED` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `EVENTS_TXSTARTED` reader - Transmit sequence started"] +pub type EVENTS_TXSTARTED_R = crate::BitReader; +#[doc = "Transmit sequence started\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum EVENTS_TXSTARTED_A { + #[doc = "0: Event not generated"] + NOT_GENERATED = 0, + #[doc = "1: Event generated"] + GENERATED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: EVENTS_TXSTARTED_A) -> Self { + variant as u8 != 0 + } +} +impl EVENTS_TXSTARTED_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EVENTS_TXSTARTED_A { + match self.bits { + false => EVENTS_TXSTARTED_A::NOT_GENERATED, + true => EVENTS_TXSTARTED_A::GENERATED, + } + } + #[doc = "Checks if the value of the field is `NOT_GENERATED`"] + #[inline(always)] + pub fn is_not_generated(&self) -> bool { + *self == EVENTS_TXSTARTED_A::NOT_GENERATED + } + #[doc = "Checks if the value of the field is `GENERATED`"] + #[inline(always)] + pub fn is_generated(&self) -> bool { + *self == EVENTS_TXSTARTED_A::GENERATED + } +} +#[doc = "Field `EVENTS_TXSTARTED` writer - Transmit sequence started"] +pub type EVENTS_TXSTARTED_W<'a, const O: u8> = + crate::BitWriter<'a, u32, EVENTS_TXSTARTED_SPEC, EVENTS_TXSTARTED_A, O>; +impl<'a, const O: u8> EVENTS_TXSTARTED_W<'a, O> { + #[doc = "Event not generated"] + #[inline(always)] + pub fn not_generated(self) -> &'a mut W { + self.variant(EVENTS_TXSTARTED_A::NOT_GENERATED) + } + #[doc = "Event generated"] + #[inline(always)] + pub fn generated(self) -> &'a mut W { + self.variant(EVENTS_TXSTARTED_A::GENERATED) + } +} +impl R { + #[doc = "Bit 0 - Transmit sequence started"] + #[inline(always)] + pub fn events_txstarted(&self) -> EVENTS_TXSTARTED_R { + EVENTS_TXSTARTED_R::new((self.bits & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Transmit sequence started"] + #[inline(always)] + pub fn events_txstarted(&mut self) -> EVENTS_TXSTARTED_W<0> { + EVENTS_TXSTARTED_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Transmit sequence started\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [events_txstarted](index.html) module"] +pub struct EVENTS_TXSTARTED_SPEC; +impl crate::RegisterSpec for EVENTS_TXSTARTED_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [events_txstarted::R](R) reader structure"] +impl crate::Readable for EVENTS_TXSTARTED_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [events_txstarted::W](W) writer structure"] +impl crate::Writable for EVENTS_TXSTARTED_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EVENTS_TXSTARTED to value 0"] +impl crate::Resettable for EVENTS_TXSTARTED_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/twim0_ns/frequency.rs b/pacs/nrf9120-pac/src/twim0_ns/frequency.rs new file mode 100644 index 00000000..91234309 --- /dev/null +++ b/pacs/nrf9120-pac/src/twim0_ns/frequency.rs @@ -0,0 +1,142 @@ +#[doc = "Register `FREQUENCY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `FREQUENCY` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `FREQUENCY` reader - TWI master clock frequency"] +pub type FREQUENCY_R = crate::FieldReader; +#[doc = "TWI master clock frequency\n\nValue on reset: 67108864"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u32)] +pub enum FREQUENCY_A { + #[doc = "26738688: 100 kbps"] + K100 = 26738688, + #[doc = "67108864: 250 kbps"] + K250 = 67108864, + #[doc = "104857600: 400 kbps"] + K400 = 104857600, +} +impl From for u32 { + #[inline(always)] + fn from(variant: FREQUENCY_A) -> Self { + variant as _ + } +} +impl FREQUENCY_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 26738688 => Some(FREQUENCY_A::K100), + 67108864 => Some(FREQUENCY_A::K250), + 104857600 => Some(FREQUENCY_A::K400), + _ => None, + } + } + #[doc = "Checks if the value of the field is `K100`"] + #[inline(always)] + pub fn is_k100(&self) -> bool { + *self == FREQUENCY_A::K100 + } + #[doc = "Checks if the value of the field is `K250`"] + #[inline(always)] + pub fn is_k250(&self) -> bool { + *self == FREQUENCY_A::K250 + } + #[doc = "Checks if the value of the field is `K400`"] + #[inline(always)] + pub fn is_k400(&self) -> bool { + *self == FREQUENCY_A::K400 + } +} +#[doc = "Field `FREQUENCY` writer - TWI master clock frequency"] +pub type FREQUENCY_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, FREQUENCY_SPEC, u32, FREQUENCY_A, 32, O>; +impl<'a, const O: u8> FREQUENCY_W<'a, O> { + #[doc = "100 kbps"] + #[inline(always)] + pub fn k100(self) -> &'a mut W { + self.variant(FREQUENCY_A::K100) + } + #[doc = "250 kbps"] + #[inline(always)] + pub fn k250(self) -> &'a mut W { + self.variant(FREQUENCY_A::K250) + } + #[doc = "400 kbps"] + #[inline(always)] + pub fn k400(self) -> &'a mut W { + self.variant(FREQUENCY_A::K400) + } +} +impl R { + #[doc = "Bits 0:31 - TWI master clock frequency"] + #[inline(always)] + pub fn frequency(&self) -> FREQUENCY_R { + FREQUENCY_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - TWI master clock frequency"] + #[inline(always)] + pub fn frequency(&mut self) -> FREQUENCY_W<0> { + FREQUENCY_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "TWI frequency. Accuracy depends on the HFCLK source selected.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [frequency](index.html) module"] +pub struct FREQUENCY_SPEC; +impl crate::RegisterSpec for FREQUENCY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [frequency::R](R) reader structure"] +impl crate::Readable for FREQUENCY_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [frequency::W](W) writer structure"] +impl crate::Writable for FREQUENCY_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets FREQUENCY to value 0x0400_0000"] +impl crate::Resettable for FREQUENCY_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x0400_0000 + } +} diff --git a/pacs/nrf9120-pac/src/twim0_ns/inten.rs b/pacs/nrf9120-pac/src/twim0_ns/inten.rs new file mode 100644 index 00000000..21c9fb75 --- /dev/null +++ b/pacs/nrf9120-pac/src/twim0_ns/inten.rs @@ -0,0 +1,486 @@ +#[doc = "Register `INTEN` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTEN` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `STOPPED` reader - Enable or disable interrupt for event STOPPED"] +pub type STOPPED_R = crate::BitReader; +#[doc = "Enable or disable interrupt for event STOPPED\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum STOPPED_A { + #[doc = "0: Disable"] + DISABLED = 0, + #[doc = "1: Enable"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: STOPPED_A) -> Self { + variant as u8 != 0 + } +} +impl STOPPED_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> STOPPED_A { + match self.bits { + false => STOPPED_A::DISABLED, + true => STOPPED_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == STOPPED_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == STOPPED_A::ENABLED + } +} +#[doc = "Field `STOPPED` writer - Enable or disable interrupt for event STOPPED"] +pub type STOPPED_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTEN_SPEC, STOPPED_A, O>; +impl<'a, const O: u8> STOPPED_W<'a, O> { + #[doc = "Disable"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(STOPPED_A::DISABLED) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(STOPPED_A::ENABLED) + } +} +#[doc = "Field `ERROR` reader - Enable or disable interrupt for event ERROR"] +pub type ERROR_R = crate::BitReader; +#[doc = "Enable or disable interrupt for event ERROR\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum ERROR_A { + #[doc = "0: Disable"] + DISABLED = 0, + #[doc = "1: Enable"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: ERROR_A) -> Self { + variant as u8 != 0 + } +} +impl ERROR_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> ERROR_A { + match self.bits { + false => ERROR_A::DISABLED, + true => ERROR_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == ERROR_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == ERROR_A::ENABLED + } +} +#[doc = "Field `ERROR` writer - Enable or disable interrupt for event ERROR"] +pub type ERROR_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTEN_SPEC, ERROR_A, O>; +impl<'a, const O: u8> ERROR_W<'a, O> { + #[doc = "Disable"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(ERROR_A::DISABLED) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(ERROR_A::ENABLED) + } +} +#[doc = "Field `SUSPENDED` reader - Enable or disable interrupt for event SUSPENDED"] +pub type SUSPENDED_R = crate::BitReader; +#[doc = "Enable or disable interrupt for event SUSPENDED\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum SUSPENDED_A { + #[doc = "0: Disable"] + DISABLED = 0, + #[doc = "1: Enable"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: SUSPENDED_A) -> Self { + variant as u8 != 0 + } +} +impl SUSPENDED_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> SUSPENDED_A { + match self.bits { + false => SUSPENDED_A::DISABLED, + true => SUSPENDED_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == SUSPENDED_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == SUSPENDED_A::ENABLED + } +} +#[doc = "Field `SUSPENDED` writer - Enable or disable interrupt for event SUSPENDED"] +pub type SUSPENDED_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTEN_SPEC, SUSPENDED_A, O>; +impl<'a, const O: u8> SUSPENDED_W<'a, O> { + #[doc = "Disable"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(SUSPENDED_A::DISABLED) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(SUSPENDED_A::ENABLED) + } +} +#[doc = "Field `RXSTARTED` reader - Enable or disable interrupt for event RXSTARTED"] +pub type RXSTARTED_R = crate::BitReader; +#[doc = "Enable or disable interrupt for event RXSTARTED\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RXSTARTED_A { + #[doc = "0: Disable"] + DISABLED = 0, + #[doc = "1: Enable"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RXSTARTED_A) -> Self { + variant as u8 != 0 + } +} +impl RXSTARTED_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RXSTARTED_A { + match self.bits { + false => RXSTARTED_A::DISABLED, + true => RXSTARTED_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == RXSTARTED_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == RXSTARTED_A::ENABLED + } +} +#[doc = "Field `RXSTARTED` writer - Enable or disable interrupt for event RXSTARTED"] +pub type RXSTARTED_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTEN_SPEC, RXSTARTED_A, O>; +impl<'a, const O: u8> RXSTARTED_W<'a, O> { + #[doc = "Disable"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(RXSTARTED_A::DISABLED) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(RXSTARTED_A::ENABLED) + } +} +#[doc = "Field `TXSTARTED` reader - Enable or disable interrupt for event TXSTARTED"] +pub type TXSTARTED_R = crate::BitReader; +#[doc = "Enable or disable interrupt for event TXSTARTED\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum TXSTARTED_A { + #[doc = "0: Disable"] + DISABLED = 0, + #[doc = "1: Enable"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TXSTARTED_A) -> Self { + variant as u8 != 0 + } +} +impl TXSTARTED_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> TXSTARTED_A { + match self.bits { + false => TXSTARTED_A::DISABLED, + true => TXSTARTED_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == TXSTARTED_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == TXSTARTED_A::ENABLED + } +} +#[doc = "Field `TXSTARTED` writer - Enable or disable interrupt for event TXSTARTED"] +pub type TXSTARTED_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTEN_SPEC, TXSTARTED_A, O>; +impl<'a, const O: u8> TXSTARTED_W<'a, O> { + #[doc = "Disable"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(TXSTARTED_A::DISABLED) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(TXSTARTED_A::ENABLED) + } +} +#[doc = "Field `LASTRX` reader - Enable or disable interrupt for event LASTRX"] +pub type LASTRX_R = crate::BitReader; +#[doc = "Enable or disable interrupt for event LASTRX\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum LASTRX_A { + #[doc = "0: Disable"] + DISABLED = 0, + #[doc = "1: Enable"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: LASTRX_A) -> Self { + variant as u8 != 0 + } +} +impl LASTRX_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> LASTRX_A { + match self.bits { + false => LASTRX_A::DISABLED, + true => LASTRX_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == LASTRX_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == LASTRX_A::ENABLED + } +} +#[doc = "Field `LASTRX` writer - Enable or disable interrupt for event LASTRX"] +pub type LASTRX_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTEN_SPEC, LASTRX_A, O>; +impl<'a, const O: u8> LASTRX_W<'a, O> { + #[doc = "Disable"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(LASTRX_A::DISABLED) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(LASTRX_A::ENABLED) + } +} +#[doc = "Field `LASTTX` reader - Enable or disable interrupt for event LASTTX"] +pub type LASTTX_R = crate::BitReader; +#[doc = "Enable or disable interrupt for event LASTTX\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum LASTTX_A { + #[doc = "0: Disable"] + DISABLED = 0, + #[doc = "1: Enable"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: LASTTX_A) -> Self { + variant as u8 != 0 + } +} +impl LASTTX_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> LASTTX_A { + match self.bits { + false => LASTTX_A::DISABLED, + true => LASTTX_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == LASTTX_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == LASTTX_A::ENABLED + } +} +#[doc = "Field `LASTTX` writer - Enable or disable interrupt for event LASTTX"] +pub type LASTTX_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTEN_SPEC, LASTTX_A, O>; +impl<'a, const O: u8> LASTTX_W<'a, O> { + #[doc = "Disable"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(LASTTX_A::DISABLED) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(LASTTX_A::ENABLED) + } +} +impl R { + #[doc = "Bit 1 - Enable or disable interrupt for event STOPPED"] + #[inline(always)] + pub fn stopped(&self) -> STOPPED_R { + STOPPED_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 9 - Enable or disable interrupt for event ERROR"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 18 - Enable or disable interrupt for event SUSPENDED"] + #[inline(always)] + pub fn suspended(&self) -> SUSPENDED_R { + SUSPENDED_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Enable or disable interrupt for event RXSTARTED"] + #[inline(always)] + pub fn rxstarted(&self) -> RXSTARTED_R { + RXSTARTED_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Enable or disable interrupt for event TXSTARTED"] + #[inline(always)] + pub fn txstarted(&self) -> TXSTARTED_R { + TXSTARTED_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 23 - Enable or disable interrupt for event LASTRX"] + #[inline(always)] + pub fn lastrx(&self) -> LASTRX_R { + LASTRX_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - Enable or disable interrupt for event LASTTX"] + #[inline(always)] + pub fn lasttx(&self) -> LASTTX_R { + LASTTX_R::new(((self.bits >> 24) & 1) != 0) + } +} +impl W { + #[doc = "Bit 1 - Enable or disable interrupt for event STOPPED"] + #[inline(always)] + pub fn stopped(&mut self) -> STOPPED_W<1> { + STOPPED_W::new(self) + } + #[doc = "Bit 9 - Enable or disable interrupt for event ERROR"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W<9> { + ERROR_W::new(self) + } + #[doc = "Bit 18 - Enable or disable interrupt for event SUSPENDED"] + #[inline(always)] + pub fn suspended(&mut self) -> SUSPENDED_W<18> { + SUSPENDED_W::new(self) + } + #[doc = "Bit 19 - Enable or disable interrupt for event RXSTARTED"] + #[inline(always)] + pub fn rxstarted(&mut self) -> RXSTARTED_W<19> { + RXSTARTED_W::new(self) + } + #[doc = "Bit 20 - Enable or disable interrupt for event TXSTARTED"] + #[inline(always)] + pub fn txstarted(&mut self) -> TXSTARTED_W<20> { + TXSTARTED_W::new(self) + } + #[doc = "Bit 23 - Enable or disable interrupt for event LASTRX"] + #[inline(always)] + pub fn lastrx(&mut self) -> LASTRX_W<23> { + LASTRX_W::new(self) + } + #[doc = "Bit 24 - Enable or disable interrupt for event LASTTX"] + #[inline(always)] + pub fn lasttx(&mut self) -> LASTTX_W<24> { + LASTTX_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Enable or disable interrupt\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [inten](index.html) module"] +pub struct INTEN_SPEC; +impl crate::RegisterSpec for INTEN_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [inten::R](R) reader structure"] +impl crate::Readable for INTEN_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [inten::W](W) writer structure"] +impl crate::Writable for INTEN_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTEN to value 0"] +impl crate::Resettable for INTEN_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/twim0_ns/intenclr.rs b/pacs/nrf9120-pac/src/twim0_ns/intenclr.rs new file mode 100644 index 00000000..52f4f926 --- /dev/null +++ b/pacs/nrf9120-pac/src/twim0_ns/intenclr.rs @@ -0,0 +1,535 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `STOPPED` reader - Write '1' to disable interrupt for event STOPPED"] +pub type STOPPED_R = crate::BitReader; +#[doc = "Write '1' to disable interrupt for event STOPPED\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum STOPPED_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: STOPPED_A) -> Self { + variant as u8 != 0 + } +} +impl STOPPED_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> STOPPED_A { + match self.bits { + false => STOPPED_A::DISABLED, + true => STOPPED_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == STOPPED_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == STOPPED_A::ENABLED + } +} +#[doc = "Write '1' to disable interrupt for event STOPPED\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum STOPPED_AW { + #[doc = "1: Disable"] + CLEAR = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: STOPPED_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `STOPPED` writer - Write '1' to disable interrupt for event STOPPED"] +pub type STOPPED_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENCLR_SPEC, STOPPED_AW, O>; +impl<'a, const O: u8> STOPPED_W<'a, O> { + #[doc = "Disable"] + #[inline(always)] + pub fn clear(self) -> &'a mut W { + self.variant(STOPPED_AW::CLEAR) + } +} +#[doc = "Field `ERROR` reader - Write '1' to disable interrupt for event ERROR"] +pub type ERROR_R = crate::BitReader; +#[doc = "Write '1' to disable interrupt for event ERROR\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum ERROR_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: ERROR_A) -> Self { + variant as u8 != 0 + } +} +impl ERROR_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> ERROR_A { + match self.bits { + false => ERROR_A::DISABLED, + true => ERROR_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == ERROR_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == ERROR_A::ENABLED + } +} +#[doc = "Write '1' to disable interrupt for event ERROR\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum ERROR_AW { + #[doc = "1: Disable"] + CLEAR = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: ERROR_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ERROR` writer - Write '1' to disable interrupt for event ERROR"] +pub type ERROR_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENCLR_SPEC, ERROR_AW, O>; +impl<'a, const O: u8> ERROR_W<'a, O> { + #[doc = "Disable"] + #[inline(always)] + pub fn clear(self) -> &'a mut W { + self.variant(ERROR_AW::CLEAR) + } +} +#[doc = "Field `SUSPENDED` reader - Write '1' to disable interrupt for event SUSPENDED"] +pub type SUSPENDED_R = crate::BitReader; +#[doc = "Write '1' to disable interrupt for event SUSPENDED\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum SUSPENDED_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: SUSPENDED_A) -> Self { + variant as u8 != 0 + } +} +impl SUSPENDED_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> SUSPENDED_A { + match self.bits { + false => SUSPENDED_A::DISABLED, + true => SUSPENDED_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == SUSPENDED_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == SUSPENDED_A::ENABLED + } +} +#[doc = "Write '1' to disable interrupt for event SUSPENDED\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum SUSPENDED_AW { + #[doc = "1: Disable"] + CLEAR = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: SUSPENDED_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SUSPENDED` writer - Write '1' to disable interrupt for event SUSPENDED"] +pub type SUSPENDED_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENCLR_SPEC, SUSPENDED_AW, O>; +impl<'a, const O: u8> SUSPENDED_W<'a, O> { + #[doc = "Disable"] + #[inline(always)] + pub fn clear(self) -> &'a mut W { + self.variant(SUSPENDED_AW::CLEAR) + } +} +#[doc = "Field `RXSTARTED` reader - Write '1' to disable interrupt for event RXSTARTED"] +pub type RXSTARTED_R = crate::BitReader; +#[doc = "Write '1' to disable interrupt for event RXSTARTED\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RXSTARTED_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RXSTARTED_A) -> Self { + variant as u8 != 0 + } +} +impl RXSTARTED_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RXSTARTED_A { + match self.bits { + false => RXSTARTED_A::DISABLED, + true => RXSTARTED_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == RXSTARTED_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == RXSTARTED_A::ENABLED + } +} +#[doc = "Write '1' to disable interrupt for event RXSTARTED\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RXSTARTED_AW { + #[doc = "1: Disable"] + CLEAR = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RXSTARTED_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RXSTARTED` writer - Write '1' to disable interrupt for event RXSTARTED"] +pub type RXSTARTED_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENCLR_SPEC, RXSTARTED_AW, O>; +impl<'a, const O: u8> RXSTARTED_W<'a, O> { + #[doc = "Disable"] + #[inline(always)] + pub fn clear(self) -> &'a mut W { + self.variant(RXSTARTED_AW::CLEAR) + } +} +#[doc = "Field `TXSTARTED` reader - Write '1' to disable interrupt for event TXSTARTED"] +pub type TXSTARTED_R = crate::BitReader; +#[doc = "Write '1' to disable interrupt for event TXSTARTED\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum TXSTARTED_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TXSTARTED_A) -> Self { + variant as u8 != 0 + } +} +impl TXSTARTED_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> TXSTARTED_A { + match self.bits { + false => TXSTARTED_A::DISABLED, + true => TXSTARTED_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == TXSTARTED_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == TXSTARTED_A::ENABLED + } +} +#[doc = "Write '1' to disable interrupt for event TXSTARTED\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum TXSTARTED_AW { + #[doc = "1: Disable"] + CLEAR = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TXSTARTED_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TXSTARTED` writer - Write '1' to disable interrupt for event TXSTARTED"] +pub type TXSTARTED_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENCLR_SPEC, TXSTARTED_AW, O>; +impl<'a, const O: u8> TXSTARTED_W<'a, O> { + #[doc = "Disable"] + #[inline(always)] + pub fn clear(self) -> &'a mut W { + self.variant(TXSTARTED_AW::CLEAR) + } +} +#[doc = "Field `LASTRX` reader - Write '1' to disable interrupt for event LASTRX"] +pub type LASTRX_R = crate::BitReader; +#[doc = "Write '1' to disable interrupt for event LASTRX\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum LASTRX_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: LASTRX_A) -> Self { + variant as u8 != 0 + } +} +impl LASTRX_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> LASTRX_A { + match self.bits { + false => LASTRX_A::DISABLED, + true => LASTRX_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == LASTRX_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == LASTRX_A::ENABLED + } +} +#[doc = "Write '1' to disable interrupt for event LASTRX\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum LASTRX_AW { + #[doc = "1: Disable"] + CLEAR = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: LASTRX_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LASTRX` writer - Write '1' to disable interrupt for event LASTRX"] +pub type LASTRX_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENCLR_SPEC, LASTRX_AW, O>; +impl<'a, const O: u8> LASTRX_W<'a, O> { + #[doc = "Disable"] + #[inline(always)] + pub fn clear(self) -> &'a mut W { + self.variant(LASTRX_AW::CLEAR) + } +} +#[doc = "Field `LASTTX` reader - Write '1' to disable interrupt for event LASTTX"] +pub type LASTTX_R = crate::BitReader; +#[doc = "Write '1' to disable interrupt for event LASTTX\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum LASTTX_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: LASTTX_A) -> Self { + variant as u8 != 0 + } +} +impl LASTTX_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> LASTTX_A { + match self.bits { + false => LASTTX_A::DISABLED, + true => LASTTX_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == LASTTX_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == LASTTX_A::ENABLED + } +} +#[doc = "Write '1' to disable interrupt for event LASTTX\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum LASTTX_AW { + #[doc = "1: Disable"] + CLEAR = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: LASTTX_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LASTTX` writer - Write '1' to disable interrupt for event LASTTX"] +pub type LASTTX_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENCLR_SPEC, LASTTX_AW, O>; +impl<'a, const O: u8> LASTTX_W<'a, O> { + #[doc = "Disable"] + #[inline(always)] + pub fn clear(self) -> &'a mut W { + self.variant(LASTTX_AW::CLEAR) + } +} +impl R { + #[doc = "Bit 1 - Write '1' to disable interrupt for event STOPPED"] + #[inline(always)] + pub fn stopped(&self) -> STOPPED_R { + STOPPED_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 9 - Write '1' to disable interrupt for event ERROR"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 18 - Write '1' to disable interrupt for event SUSPENDED"] + #[inline(always)] + pub fn suspended(&self) -> SUSPENDED_R { + SUSPENDED_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Write '1' to disable interrupt for event RXSTARTED"] + #[inline(always)] + pub fn rxstarted(&self) -> RXSTARTED_R { + RXSTARTED_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Write '1' to disable interrupt for event TXSTARTED"] + #[inline(always)] + pub fn txstarted(&self) -> TXSTARTED_R { + TXSTARTED_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 23 - Write '1' to disable interrupt for event LASTRX"] + #[inline(always)] + pub fn lastrx(&self) -> LASTRX_R { + LASTRX_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - Write '1' to disable interrupt for event LASTTX"] + #[inline(always)] + pub fn lasttx(&self) -> LASTTX_R { + LASTTX_R::new(((self.bits >> 24) & 1) != 0) + } +} +impl W { + #[doc = "Bit 1 - Write '1' to disable interrupt for event STOPPED"] + #[inline(always)] + pub fn stopped(&mut self) -> STOPPED_W<1> { + STOPPED_W::new(self) + } + #[doc = "Bit 9 - Write '1' to disable interrupt for event ERROR"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W<9> { + ERROR_W::new(self) + } + #[doc = "Bit 18 - Write '1' to disable interrupt for event SUSPENDED"] + #[inline(always)] + pub fn suspended(&mut self) -> SUSPENDED_W<18> { + SUSPENDED_W::new(self) + } + #[doc = "Bit 19 - Write '1' to disable interrupt for event RXSTARTED"] + #[inline(always)] + pub fn rxstarted(&mut self) -> RXSTARTED_W<19> { + RXSTARTED_W::new(self) + } + #[doc = "Bit 20 - Write '1' to disable interrupt for event TXSTARTED"] + #[inline(always)] + pub fn txstarted(&mut self) -> TXSTARTED_W<20> { + TXSTARTED_W::new(self) + } + #[doc = "Bit 23 - Write '1' to disable interrupt for event LASTRX"] + #[inline(always)] + pub fn lastrx(&mut self) -> LASTRX_W<23> { + LASTRX_W::new(self) + } + #[doc = "Bit 24 - Write '1' to disable interrupt for event LASTTX"] + #[inline(always)] + pub fn lasttx(&mut self) -> LASTTX_W<24> { + LASTTX_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Disable interrupt\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/twim0_ns/intenset.rs b/pacs/nrf9120-pac/src/twim0_ns/intenset.rs new file mode 100644 index 00000000..057868a4 --- /dev/null +++ b/pacs/nrf9120-pac/src/twim0_ns/intenset.rs @@ -0,0 +1,535 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `STOPPED` reader - Write '1' to enable interrupt for event STOPPED"] +pub type STOPPED_R = crate::BitReader; +#[doc = "Write '1' to enable interrupt for event STOPPED\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum STOPPED_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: STOPPED_A) -> Self { + variant as u8 != 0 + } +} +impl STOPPED_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> STOPPED_A { + match self.bits { + false => STOPPED_A::DISABLED, + true => STOPPED_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == STOPPED_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == STOPPED_A::ENABLED + } +} +#[doc = "Write '1' to enable interrupt for event STOPPED\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum STOPPED_AW { + #[doc = "1: Enable"] + SET = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: STOPPED_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `STOPPED` writer - Write '1' to enable interrupt for event STOPPED"] +pub type STOPPED_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENSET_SPEC, STOPPED_AW, O>; +impl<'a, const O: u8> STOPPED_W<'a, O> { + #[doc = "Enable"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(STOPPED_AW::SET) + } +} +#[doc = "Field `ERROR` reader - Write '1' to enable interrupt for event ERROR"] +pub type ERROR_R = crate::BitReader; +#[doc = "Write '1' to enable interrupt for event ERROR\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum ERROR_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: ERROR_A) -> Self { + variant as u8 != 0 + } +} +impl ERROR_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> ERROR_A { + match self.bits { + false => ERROR_A::DISABLED, + true => ERROR_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == ERROR_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == ERROR_A::ENABLED + } +} +#[doc = "Write '1' to enable interrupt for event ERROR\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum ERROR_AW { + #[doc = "1: Enable"] + SET = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: ERROR_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ERROR` writer - Write '1' to enable interrupt for event ERROR"] +pub type ERROR_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENSET_SPEC, ERROR_AW, O>; +impl<'a, const O: u8> ERROR_W<'a, O> { + #[doc = "Enable"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(ERROR_AW::SET) + } +} +#[doc = "Field `SUSPENDED` reader - Write '1' to enable interrupt for event SUSPENDED"] +pub type SUSPENDED_R = crate::BitReader; +#[doc = "Write '1' to enable interrupt for event SUSPENDED\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum SUSPENDED_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: SUSPENDED_A) -> Self { + variant as u8 != 0 + } +} +impl SUSPENDED_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> SUSPENDED_A { + match self.bits { + false => SUSPENDED_A::DISABLED, + true => SUSPENDED_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == SUSPENDED_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == SUSPENDED_A::ENABLED + } +} +#[doc = "Write '1' to enable interrupt for event SUSPENDED\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum SUSPENDED_AW { + #[doc = "1: Enable"] + SET = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: SUSPENDED_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SUSPENDED` writer - Write '1' to enable interrupt for event SUSPENDED"] +pub type SUSPENDED_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENSET_SPEC, SUSPENDED_AW, O>; +impl<'a, const O: u8> SUSPENDED_W<'a, O> { + #[doc = "Enable"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(SUSPENDED_AW::SET) + } +} +#[doc = "Field `RXSTARTED` reader - Write '1' to enable interrupt for event RXSTARTED"] +pub type RXSTARTED_R = crate::BitReader; +#[doc = "Write '1' to enable interrupt for event RXSTARTED\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RXSTARTED_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RXSTARTED_A) -> Self { + variant as u8 != 0 + } +} +impl RXSTARTED_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RXSTARTED_A { + match self.bits { + false => RXSTARTED_A::DISABLED, + true => RXSTARTED_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == RXSTARTED_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == RXSTARTED_A::ENABLED + } +} +#[doc = "Write '1' to enable interrupt for event RXSTARTED\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RXSTARTED_AW { + #[doc = "1: Enable"] + SET = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RXSTARTED_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RXSTARTED` writer - Write '1' to enable interrupt for event RXSTARTED"] +pub type RXSTARTED_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENSET_SPEC, RXSTARTED_AW, O>; +impl<'a, const O: u8> RXSTARTED_W<'a, O> { + #[doc = "Enable"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(RXSTARTED_AW::SET) + } +} +#[doc = "Field `TXSTARTED` reader - Write '1' to enable interrupt for event TXSTARTED"] +pub type TXSTARTED_R = crate::BitReader; +#[doc = "Write '1' to enable interrupt for event TXSTARTED\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum TXSTARTED_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TXSTARTED_A) -> Self { + variant as u8 != 0 + } +} +impl TXSTARTED_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> TXSTARTED_A { + match self.bits { + false => TXSTARTED_A::DISABLED, + true => TXSTARTED_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == TXSTARTED_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == TXSTARTED_A::ENABLED + } +} +#[doc = "Write '1' to enable interrupt for event TXSTARTED\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum TXSTARTED_AW { + #[doc = "1: Enable"] + SET = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TXSTARTED_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TXSTARTED` writer - Write '1' to enable interrupt for event TXSTARTED"] +pub type TXSTARTED_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENSET_SPEC, TXSTARTED_AW, O>; +impl<'a, const O: u8> TXSTARTED_W<'a, O> { + #[doc = "Enable"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(TXSTARTED_AW::SET) + } +} +#[doc = "Field `LASTRX` reader - Write '1' to enable interrupt for event LASTRX"] +pub type LASTRX_R = crate::BitReader; +#[doc = "Write '1' to enable interrupt for event LASTRX\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum LASTRX_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: LASTRX_A) -> Self { + variant as u8 != 0 + } +} +impl LASTRX_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> LASTRX_A { + match self.bits { + false => LASTRX_A::DISABLED, + true => LASTRX_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == LASTRX_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == LASTRX_A::ENABLED + } +} +#[doc = "Write '1' to enable interrupt for event LASTRX\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum LASTRX_AW { + #[doc = "1: Enable"] + SET = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: LASTRX_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LASTRX` writer - Write '1' to enable interrupt for event LASTRX"] +pub type LASTRX_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENSET_SPEC, LASTRX_AW, O>; +impl<'a, const O: u8> LASTRX_W<'a, O> { + #[doc = "Enable"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(LASTRX_AW::SET) + } +} +#[doc = "Field `LASTTX` reader - Write '1' to enable interrupt for event LASTTX"] +pub type LASTTX_R = crate::BitReader; +#[doc = "Write '1' to enable interrupt for event LASTTX\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum LASTTX_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: LASTTX_A) -> Self { + variant as u8 != 0 + } +} +impl LASTTX_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> LASTTX_A { + match self.bits { + false => LASTTX_A::DISABLED, + true => LASTTX_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == LASTTX_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == LASTTX_A::ENABLED + } +} +#[doc = "Write '1' to enable interrupt for event LASTTX\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum LASTTX_AW { + #[doc = "1: Enable"] + SET = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: LASTTX_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LASTTX` writer - Write '1' to enable interrupt for event LASTTX"] +pub type LASTTX_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENSET_SPEC, LASTTX_AW, O>; +impl<'a, const O: u8> LASTTX_W<'a, O> { + #[doc = "Enable"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(LASTTX_AW::SET) + } +} +impl R { + #[doc = "Bit 1 - Write '1' to enable interrupt for event STOPPED"] + #[inline(always)] + pub fn stopped(&self) -> STOPPED_R { + STOPPED_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 9 - Write '1' to enable interrupt for event ERROR"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 18 - Write '1' to enable interrupt for event SUSPENDED"] + #[inline(always)] + pub fn suspended(&self) -> SUSPENDED_R { + SUSPENDED_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Write '1' to enable interrupt for event RXSTARTED"] + #[inline(always)] + pub fn rxstarted(&self) -> RXSTARTED_R { + RXSTARTED_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Write '1' to enable interrupt for event TXSTARTED"] + #[inline(always)] + pub fn txstarted(&self) -> TXSTARTED_R { + TXSTARTED_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 23 - Write '1' to enable interrupt for event LASTRX"] + #[inline(always)] + pub fn lastrx(&self) -> LASTRX_R { + LASTRX_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - Write '1' to enable interrupt for event LASTTX"] + #[inline(always)] + pub fn lasttx(&self) -> LASTTX_R { + LASTTX_R::new(((self.bits >> 24) & 1) != 0) + } +} +impl W { + #[doc = "Bit 1 - Write '1' to enable interrupt for event STOPPED"] + #[inline(always)] + pub fn stopped(&mut self) -> STOPPED_W<1> { + STOPPED_W::new(self) + } + #[doc = "Bit 9 - Write '1' to enable interrupt for event ERROR"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W<9> { + ERROR_W::new(self) + } + #[doc = "Bit 18 - Write '1' to enable interrupt for event SUSPENDED"] + #[inline(always)] + pub fn suspended(&mut self) -> SUSPENDED_W<18> { + SUSPENDED_W::new(self) + } + #[doc = "Bit 19 - Write '1' to enable interrupt for event RXSTARTED"] + #[inline(always)] + pub fn rxstarted(&mut self) -> RXSTARTED_W<19> { + RXSTARTED_W::new(self) + } + #[doc = "Bit 20 - Write '1' to enable interrupt for event TXSTARTED"] + #[inline(always)] + pub fn txstarted(&mut self) -> TXSTARTED_W<20> { + TXSTARTED_W::new(self) + } + #[doc = "Bit 23 - Write '1' to enable interrupt for event LASTRX"] + #[inline(always)] + pub fn lastrx(&mut self) -> LASTRX_W<23> { + LASTRX_W::new(self) + } + #[doc = "Bit 24 - Write '1' to enable interrupt for event LASTTX"] + #[inline(always)] + pub fn lasttx(&mut self) -> LASTTX_W<24> { + LASTTX_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Enable interrupt\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/twim0_ns/psel.rs b/pacs/nrf9120-pac/src/twim0_ns/psel.rs new file mode 100644 index 00000000..6d71cdf1 --- /dev/null +++ b/pacs/nrf9120-pac/src/twim0_ns/psel.rs @@ -0,0 +1,16 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct PSEL { + #[doc = "0x00 - Pin select for SCL signal"] + pub scl: SCL, + #[doc = "0x04 - Pin select for SDA signal"] + pub sda: SDA, +} +#[doc = "SCL (rw) register accessor: an alias for `Reg`"] +pub type SCL = crate::Reg; +#[doc = "Pin select for SCL signal"] +pub mod scl; +#[doc = "SDA (rw) register accessor: an alias for `Reg`"] +pub type SDA = crate::Reg; +#[doc = "Pin select for SDA signal"] +pub mod sda; diff --git a/pacs/nrf9120-pac/src/twim0_ns/psel/scl.rs b/pacs/nrf9120-pac/src/twim0_ns/psel/scl.rs new file mode 100644 index 00000000..75273ced --- /dev/null +++ b/pacs/nrf9120-pac/src/twim0_ns/psel/scl.rs @@ -0,0 +1,140 @@ +#[doc = "Register `SCL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SCL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PIN` reader - Pin number"] +pub type PIN_R = crate::FieldReader; +#[doc = "Field `PIN` writer - Pin number"] +pub type PIN_W<'a, const O: u8> = crate::FieldWriter<'a, u32, SCL_SPEC, u8, u8, 5, O>; +#[doc = "Field `CONNECT` reader - Connection"] +pub type CONNECT_R = crate::BitReader; +#[doc = "Connection\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CONNECT_A { + #[doc = "1: Disconnect"] + DISCONNECTED = 1, + #[doc = "0: Connect"] + CONNECTED = 0, +} +impl From for bool { + #[inline(always)] + fn from(variant: CONNECT_A) -> Self { + variant as u8 != 0 + } +} +impl CONNECT_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CONNECT_A { + match self.bits { + true => CONNECT_A::DISCONNECTED, + false => CONNECT_A::CONNECTED, + } + } + #[doc = "Checks if the value of the field is `DISCONNECTED`"] + #[inline(always)] + pub fn is_disconnected(&self) -> bool { + *self == CONNECT_A::DISCONNECTED + } + #[doc = "Checks if the value of the field is `CONNECTED`"] + #[inline(always)] + pub fn is_connected(&self) -> bool { + *self == CONNECT_A::CONNECTED + } +} +#[doc = "Field `CONNECT` writer - Connection"] +pub type CONNECT_W<'a, const O: u8> = crate::BitWriter<'a, u32, SCL_SPEC, CONNECT_A, O>; +impl<'a, const O: u8> CONNECT_W<'a, O> { + #[doc = "Disconnect"] + #[inline(always)] + pub fn disconnected(self) -> &'a mut W { + self.variant(CONNECT_A::DISCONNECTED) + } + #[doc = "Connect"] + #[inline(always)] + pub fn connected(self) -> &'a mut W { + self.variant(CONNECT_A::CONNECTED) + } +} +impl R { + #[doc = "Bits 0:4 - Pin number"] + #[inline(always)] + pub fn pin(&self) -> PIN_R { + PIN_R::new((self.bits & 0x1f) as u8) + } + #[doc = "Bit 31 - Connection"] + #[inline(always)] + pub fn connect(&self) -> CONNECT_R { + CONNECT_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:4 - Pin number"] + #[inline(always)] + pub fn pin(&mut self) -> PIN_W<0> { + PIN_W::new(self) + } + #[doc = "Bit 31 - Connection"] + #[inline(always)] + pub fn connect(&mut self) -> CONNECT_W<31> { + CONNECT_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Pin select for SCL signal\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [scl](index.html) module"] +pub struct SCL_SPEC; +impl crate::RegisterSpec for SCL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [scl::R](R) reader structure"] +impl crate::Readable for SCL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [scl::W](W) writer structure"] +impl crate::Writable for SCL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SCL to value 0xffff_ffff"] +impl crate::Resettable for SCL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0xffff_ffff + } +} diff --git a/pacs/nrf9120-pac/src/twim0_ns/psel/sda.rs b/pacs/nrf9120-pac/src/twim0_ns/psel/sda.rs new file mode 100644 index 00000000..4063508e --- /dev/null +++ b/pacs/nrf9120-pac/src/twim0_ns/psel/sda.rs @@ -0,0 +1,140 @@ +#[doc = "Register `SDA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SDA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PIN` reader - Pin number"] +pub type PIN_R = crate::FieldReader; +#[doc = "Field `PIN` writer - Pin number"] +pub type PIN_W<'a, const O: u8> = crate::FieldWriter<'a, u32, SDA_SPEC, u8, u8, 5, O>; +#[doc = "Field `CONNECT` reader - Connection"] +pub type CONNECT_R = crate::BitReader; +#[doc = "Connection\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CONNECT_A { + #[doc = "1: Disconnect"] + DISCONNECTED = 1, + #[doc = "0: Connect"] + CONNECTED = 0, +} +impl From for bool { + #[inline(always)] + fn from(variant: CONNECT_A) -> Self { + variant as u8 != 0 + } +} +impl CONNECT_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CONNECT_A { + match self.bits { + true => CONNECT_A::DISCONNECTED, + false => CONNECT_A::CONNECTED, + } + } + #[doc = "Checks if the value of the field is `DISCONNECTED`"] + #[inline(always)] + pub fn is_disconnected(&self) -> bool { + *self == CONNECT_A::DISCONNECTED + } + #[doc = "Checks if the value of the field is `CONNECTED`"] + #[inline(always)] + pub fn is_connected(&self) -> bool { + *self == CONNECT_A::CONNECTED + } +} +#[doc = "Field `CONNECT` writer - Connection"] +pub type CONNECT_W<'a, const O: u8> = crate::BitWriter<'a, u32, SDA_SPEC, CONNECT_A, O>; +impl<'a, const O: u8> CONNECT_W<'a, O> { + #[doc = "Disconnect"] + #[inline(always)] + pub fn disconnected(self) -> &'a mut W { + self.variant(CONNECT_A::DISCONNECTED) + } + #[doc = "Connect"] + #[inline(always)] + pub fn connected(self) -> &'a mut W { + self.variant(CONNECT_A::CONNECTED) + } +} +impl R { + #[doc = "Bits 0:4 - Pin number"] + #[inline(always)] + pub fn pin(&self) -> PIN_R { + PIN_R::new((self.bits & 0x1f) as u8) + } + #[doc = "Bit 31 - Connection"] + #[inline(always)] + pub fn connect(&self) -> CONNECT_R { + CONNECT_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:4 - Pin number"] + #[inline(always)] + pub fn pin(&mut self) -> PIN_W<0> { + PIN_W::new(self) + } + #[doc = "Bit 31 - Connection"] + #[inline(always)] + pub fn connect(&mut self) -> CONNECT_W<31> { + CONNECT_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Pin select for SDA signal\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sda](index.html) module"] +pub struct SDA_SPEC; +impl crate::RegisterSpec for SDA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [sda::R](R) reader structure"] +impl crate::Readable for SDA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [sda::W](W) writer structure"] +impl crate::Writable for SDA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SDA to value 0xffff_ffff"] +impl crate::Resettable for SDA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0xffff_ffff + } +} diff --git a/pacs/nrf9120-pac/src/twim0_ns/publish_error.rs b/pacs/nrf9120-pac/src/twim0_ns/publish_error.rs new file mode 100644 index 00000000..b8934693 --- /dev/null +++ b/pacs/nrf9120-pac/src/twim0_ns/publish_error.rs @@ -0,0 +1,140 @@ +#[doc = "Register `PUBLISH_ERROR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PUBLISH_ERROR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CHIDX` reader - DPPI channel that event ERROR will publish to"] +pub type CHIDX_R = crate::FieldReader; +#[doc = "Field `CHIDX` writer - DPPI channel that event ERROR will publish to"] +pub type CHIDX_W<'a, const O: u8> = crate::FieldWriter<'a, u32, PUBLISH_ERROR_SPEC, u8, u8, 8, O>; +#[doc = "Field `EN` reader - "] +pub type EN_R = crate::BitReader; +#[doc = "\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum EN_A { + #[doc = "0: Disable publishing"] + DISABLED = 0, + #[doc = "1: Enable publishing"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: EN_A) -> Self { + variant as u8 != 0 + } +} +impl EN_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EN_A { + match self.bits { + false => EN_A::DISABLED, + true => EN_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == EN_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == EN_A::ENABLED + } +} +#[doc = "Field `EN` writer - "] +pub type EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, PUBLISH_ERROR_SPEC, EN_A, O>; +impl<'a, const O: u8> EN_W<'a, O> { + #[doc = "Disable publishing"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(EN_A::DISABLED) + } + #[doc = "Enable publishing"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(EN_A::ENABLED) + } +} +impl R { + #[doc = "Bits 0:7 - DPPI channel that event ERROR will publish to"] + #[inline(always)] + pub fn chidx(&self) -> CHIDX_R { + CHIDX_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&self) -> EN_R { + EN_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:7 - DPPI channel that event ERROR will publish to"] + #[inline(always)] + pub fn chidx(&mut self) -> CHIDX_W<0> { + CHIDX_W::new(self) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&mut self) -> EN_W<31> { + EN_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Publish configuration for event ERROR\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [publish_error](index.html) module"] +pub struct PUBLISH_ERROR_SPEC; +impl crate::RegisterSpec for PUBLISH_ERROR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [publish_error::R](R) reader structure"] +impl crate::Readable for PUBLISH_ERROR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [publish_error::W](W) writer structure"] +impl crate::Writable for PUBLISH_ERROR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PUBLISH_ERROR to value 0"] +impl crate::Resettable for PUBLISH_ERROR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/twim0_ns/publish_lastrx.rs b/pacs/nrf9120-pac/src/twim0_ns/publish_lastrx.rs new file mode 100644 index 00000000..b1a83096 --- /dev/null +++ b/pacs/nrf9120-pac/src/twim0_ns/publish_lastrx.rs @@ -0,0 +1,140 @@ +#[doc = "Register `PUBLISH_LASTRX` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PUBLISH_LASTRX` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CHIDX` reader - DPPI channel that event LASTRX will publish to"] +pub type CHIDX_R = crate::FieldReader; +#[doc = "Field `CHIDX` writer - DPPI channel that event LASTRX will publish to"] +pub type CHIDX_W<'a, const O: u8> = crate::FieldWriter<'a, u32, PUBLISH_LASTRX_SPEC, u8, u8, 8, O>; +#[doc = "Field `EN` reader - "] +pub type EN_R = crate::BitReader; +#[doc = "\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum EN_A { + #[doc = "0: Disable publishing"] + DISABLED = 0, + #[doc = "1: Enable publishing"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: EN_A) -> Self { + variant as u8 != 0 + } +} +impl EN_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EN_A { + match self.bits { + false => EN_A::DISABLED, + true => EN_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == EN_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == EN_A::ENABLED + } +} +#[doc = "Field `EN` writer - "] +pub type EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, PUBLISH_LASTRX_SPEC, EN_A, O>; +impl<'a, const O: u8> EN_W<'a, O> { + #[doc = "Disable publishing"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(EN_A::DISABLED) + } + #[doc = "Enable publishing"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(EN_A::ENABLED) + } +} +impl R { + #[doc = "Bits 0:7 - DPPI channel that event LASTRX will publish to"] + #[inline(always)] + pub fn chidx(&self) -> CHIDX_R { + CHIDX_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&self) -> EN_R { + EN_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:7 - DPPI channel that event LASTRX will publish to"] + #[inline(always)] + pub fn chidx(&mut self) -> CHIDX_W<0> { + CHIDX_W::new(self) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&mut self) -> EN_W<31> { + EN_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Publish configuration for event LASTRX\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [publish_lastrx](index.html) module"] +pub struct PUBLISH_LASTRX_SPEC; +impl crate::RegisterSpec for PUBLISH_LASTRX_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [publish_lastrx::R](R) reader structure"] +impl crate::Readable for PUBLISH_LASTRX_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [publish_lastrx::W](W) writer structure"] +impl crate::Writable for PUBLISH_LASTRX_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PUBLISH_LASTRX to value 0"] +impl crate::Resettable for PUBLISH_LASTRX_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/twim0_ns/publish_lasttx.rs b/pacs/nrf9120-pac/src/twim0_ns/publish_lasttx.rs new file mode 100644 index 00000000..00c916de --- /dev/null +++ b/pacs/nrf9120-pac/src/twim0_ns/publish_lasttx.rs @@ -0,0 +1,140 @@ +#[doc = "Register `PUBLISH_LASTTX` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PUBLISH_LASTTX` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CHIDX` reader - DPPI channel that event LASTTX will publish to"] +pub type CHIDX_R = crate::FieldReader; +#[doc = "Field `CHIDX` writer - DPPI channel that event LASTTX will publish to"] +pub type CHIDX_W<'a, const O: u8> = crate::FieldWriter<'a, u32, PUBLISH_LASTTX_SPEC, u8, u8, 8, O>; +#[doc = "Field `EN` reader - "] +pub type EN_R = crate::BitReader; +#[doc = "\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum EN_A { + #[doc = "0: Disable publishing"] + DISABLED = 0, + #[doc = "1: Enable publishing"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: EN_A) -> Self { + variant as u8 != 0 + } +} +impl EN_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EN_A { + match self.bits { + false => EN_A::DISABLED, + true => EN_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == EN_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == EN_A::ENABLED + } +} +#[doc = "Field `EN` writer - "] +pub type EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, PUBLISH_LASTTX_SPEC, EN_A, O>; +impl<'a, const O: u8> EN_W<'a, O> { + #[doc = "Disable publishing"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(EN_A::DISABLED) + } + #[doc = "Enable publishing"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(EN_A::ENABLED) + } +} +impl R { + #[doc = "Bits 0:7 - DPPI channel that event LASTTX will publish to"] + #[inline(always)] + pub fn chidx(&self) -> CHIDX_R { + CHIDX_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&self) -> EN_R { + EN_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:7 - DPPI channel that event LASTTX will publish to"] + #[inline(always)] + pub fn chidx(&mut self) -> CHIDX_W<0> { + CHIDX_W::new(self) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&mut self) -> EN_W<31> { + EN_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Publish configuration for event LASTTX\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [publish_lasttx](index.html) module"] +pub struct PUBLISH_LASTTX_SPEC; +impl crate::RegisterSpec for PUBLISH_LASTTX_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [publish_lasttx::R](R) reader structure"] +impl crate::Readable for PUBLISH_LASTTX_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [publish_lasttx::W](W) writer structure"] +impl crate::Writable for PUBLISH_LASTTX_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PUBLISH_LASTTX to value 0"] +impl crate::Resettable for PUBLISH_LASTTX_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/twim0_ns/publish_rxstarted.rs b/pacs/nrf9120-pac/src/twim0_ns/publish_rxstarted.rs new file mode 100644 index 00000000..c0328382 --- /dev/null +++ b/pacs/nrf9120-pac/src/twim0_ns/publish_rxstarted.rs @@ -0,0 +1,141 @@ +#[doc = "Register `PUBLISH_RXSTARTED` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PUBLISH_RXSTARTED` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CHIDX` reader - DPPI channel that event RXSTARTED will publish to"] +pub type CHIDX_R = crate::FieldReader; +#[doc = "Field `CHIDX` writer - DPPI channel that event RXSTARTED will publish to"] +pub type CHIDX_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, PUBLISH_RXSTARTED_SPEC, u8, u8, 8, O>; +#[doc = "Field `EN` reader - "] +pub type EN_R = crate::BitReader; +#[doc = "\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum EN_A { + #[doc = "0: Disable publishing"] + DISABLED = 0, + #[doc = "1: Enable publishing"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: EN_A) -> Self { + variant as u8 != 0 + } +} +impl EN_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EN_A { + match self.bits { + false => EN_A::DISABLED, + true => EN_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == EN_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == EN_A::ENABLED + } +} +#[doc = "Field `EN` writer - "] +pub type EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, PUBLISH_RXSTARTED_SPEC, EN_A, O>; +impl<'a, const O: u8> EN_W<'a, O> { + #[doc = "Disable publishing"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(EN_A::DISABLED) + } + #[doc = "Enable publishing"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(EN_A::ENABLED) + } +} +impl R { + #[doc = "Bits 0:7 - DPPI channel that event RXSTARTED will publish to"] + #[inline(always)] + pub fn chidx(&self) -> CHIDX_R { + CHIDX_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&self) -> EN_R { + EN_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:7 - DPPI channel that event RXSTARTED will publish to"] + #[inline(always)] + pub fn chidx(&mut self) -> CHIDX_W<0> { + CHIDX_W::new(self) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&mut self) -> EN_W<31> { + EN_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Publish configuration for event RXSTARTED\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [publish_rxstarted](index.html) module"] +pub struct PUBLISH_RXSTARTED_SPEC; +impl crate::RegisterSpec for PUBLISH_RXSTARTED_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [publish_rxstarted::R](R) reader structure"] +impl crate::Readable for PUBLISH_RXSTARTED_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [publish_rxstarted::W](W) writer structure"] +impl crate::Writable for PUBLISH_RXSTARTED_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PUBLISH_RXSTARTED to value 0"] +impl crate::Resettable for PUBLISH_RXSTARTED_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/twim0_ns/publish_stopped.rs b/pacs/nrf9120-pac/src/twim0_ns/publish_stopped.rs new file mode 100644 index 00000000..247f50bf --- /dev/null +++ b/pacs/nrf9120-pac/src/twim0_ns/publish_stopped.rs @@ -0,0 +1,140 @@ +#[doc = "Register `PUBLISH_STOPPED` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PUBLISH_STOPPED` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CHIDX` reader - DPPI channel that event STOPPED will publish to"] +pub type CHIDX_R = crate::FieldReader; +#[doc = "Field `CHIDX` writer - DPPI channel that event STOPPED will publish to"] +pub type CHIDX_W<'a, const O: u8> = crate::FieldWriter<'a, u32, PUBLISH_STOPPED_SPEC, u8, u8, 8, O>; +#[doc = "Field `EN` reader - "] +pub type EN_R = crate::BitReader; +#[doc = "\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum EN_A { + #[doc = "0: Disable publishing"] + DISABLED = 0, + #[doc = "1: Enable publishing"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: EN_A) -> Self { + variant as u8 != 0 + } +} +impl EN_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EN_A { + match self.bits { + false => EN_A::DISABLED, + true => EN_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == EN_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == EN_A::ENABLED + } +} +#[doc = "Field `EN` writer - "] +pub type EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, PUBLISH_STOPPED_SPEC, EN_A, O>; +impl<'a, const O: u8> EN_W<'a, O> { + #[doc = "Disable publishing"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(EN_A::DISABLED) + } + #[doc = "Enable publishing"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(EN_A::ENABLED) + } +} +impl R { + #[doc = "Bits 0:7 - DPPI channel that event STOPPED will publish to"] + #[inline(always)] + pub fn chidx(&self) -> CHIDX_R { + CHIDX_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&self) -> EN_R { + EN_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:7 - DPPI channel that event STOPPED will publish to"] + #[inline(always)] + pub fn chidx(&mut self) -> CHIDX_W<0> { + CHIDX_W::new(self) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&mut self) -> EN_W<31> { + EN_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Publish configuration for event STOPPED\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [publish_stopped](index.html) module"] +pub struct PUBLISH_STOPPED_SPEC; +impl crate::RegisterSpec for PUBLISH_STOPPED_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [publish_stopped::R](R) reader structure"] +impl crate::Readable for PUBLISH_STOPPED_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [publish_stopped::W](W) writer structure"] +impl crate::Writable for PUBLISH_STOPPED_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PUBLISH_STOPPED to value 0"] +impl crate::Resettable for PUBLISH_STOPPED_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/twim0_ns/publish_suspended.rs b/pacs/nrf9120-pac/src/twim0_ns/publish_suspended.rs new file mode 100644 index 00000000..976d734e --- /dev/null +++ b/pacs/nrf9120-pac/src/twim0_ns/publish_suspended.rs @@ -0,0 +1,141 @@ +#[doc = "Register `PUBLISH_SUSPENDED` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PUBLISH_SUSPENDED` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CHIDX` reader - DPPI channel that event SUSPENDED will publish to"] +pub type CHIDX_R = crate::FieldReader; +#[doc = "Field `CHIDX` writer - DPPI channel that event SUSPENDED will publish to"] +pub type CHIDX_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, PUBLISH_SUSPENDED_SPEC, u8, u8, 8, O>; +#[doc = "Field `EN` reader - "] +pub type EN_R = crate::BitReader; +#[doc = "\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum EN_A { + #[doc = "0: Disable publishing"] + DISABLED = 0, + #[doc = "1: Enable publishing"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: EN_A) -> Self { + variant as u8 != 0 + } +} +impl EN_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EN_A { + match self.bits { + false => EN_A::DISABLED, + true => EN_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == EN_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == EN_A::ENABLED + } +} +#[doc = "Field `EN` writer - "] +pub type EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, PUBLISH_SUSPENDED_SPEC, EN_A, O>; +impl<'a, const O: u8> EN_W<'a, O> { + #[doc = "Disable publishing"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(EN_A::DISABLED) + } + #[doc = "Enable publishing"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(EN_A::ENABLED) + } +} +impl R { + #[doc = "Bits 0:7 - DPPI channel that event SUSPENDED will publish to"] + #[inline(always)] + pub fn chidx(&self) -> CHIDX_R { + CHIDX_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&self) -> EN_R { + EN_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:7 - DPPI channel that event SUSPENDED will publish to"] + #[inline(always)] + pub fn chidx(&mut self) -> CHIDX_W<0> { + CHIDX_W::new(self) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&mut self) -> EN_W<31> { + EN_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Publish configuration for event SUSPENDED\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [publish_suspended](index.html) module"] +pub struct PUBLISH_SUSPENDED_SPEC; +impl crate::RegisterSpec for PUBLISH_SUSPENDED_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [publish_suspended::R](R) reader structure"] +impl crate::Readable for PUBLISH_SUSPENDED_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [publish_suspended::W](W) writer structure"] +impl crate::Writable for PUBLISH_SUSPENDED_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PUBLISH_SUSPENDED to value 0"] +impl crate::Resettable for PUBLISH_SUSPENDED_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/twim0_ns/publish_txstarted.rs b/pacs/nrf9120-pac/src/twim0_ns/publish_txstarted.rs new file mode 100644 index 00000000..2d049893 --- /dev/null +++ b/pacs/nrf9120-pac/src/twim0_ns/publish_txstarted.rs @@ -0,0 +1,141 @@ +#[doc = "Register `PUBLISH_TXSTARTED` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PUBLISH_TXSTARTED` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CHIDX` reader - DPPI channel that event TXSTARTED will publish to"] +pub type CHIDX_R = crate::FieldReader; +#[doc = "Field `CHIDX` writer - DPPI channel that event TXSTARTED will publish to"] +pub type CHIDX_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, PUBLISH_TXSTARTED_SPEC, u8, u8, 8, O>; +#[doc = "Field `EN` reader - "] +pub type EN_R = crate::BitReader; +#[doc = "\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum EN_A { + #[doc = "0: Disable publishing"] + DISABLED = 0, + #[doc = "1: Enable publishing"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: EN_A) -> Self { + variant as u8 != 0 + } +} +impl EN_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EN_A { + match self.bits { + false => EN_A::DISABLED, + true => EN_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == EN_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == EN_A::ENABLED + } +} +#[doc = "Field `EN` writer - "] +pub type EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, PUBLISH_TXSTARTED_SPEC, EN_A, O>; +impl<'a, const O: u8> EN_W<'a, O> { + #[doc = "Disable publishing"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(EN_A::DISABLED) + } + #[doc = "Enable publishing"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(EN_A::ENABLED) + } +} +impl R { + #[doc = "Bits 0:7 - DPPI channel that event TXSTARTED will publish to"] + #[inline(always)] + pub fn chidx(&self) -> CHIDX_R { + CHIDX_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&self) -> EN_R { + EN_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:7 - DPPI channel that event TXSTARTED will publish to"] + #[inline(always)] + pub fn chidx(&mut self) -> CHIDX_W<0> { + CHIDX_W::new(self) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&mut self) -> EN_W<31> { + EN_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Publish configuration for event TXSTARTED\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [publish_txstarted](index.html) module"] +pub struct PUBLISH_TXSTARTED_SPEC; +impl crate::RegisterSpec for PUBLISH_TXSTARTED_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [publish_txstarted::R](R) reader structure"] +impl crate::Readable for PUBLISH_TXSTARTED_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [publish_txstarted::W](W) writer structure"] +impl crate::Writable for PUBLISH_TXSTARTED_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PUBLISH_TXSTARTED to value 0"] +impl crate::Resettable for PUBLISH_TXSTARTED_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/twim0_ns/rxd.rs b/pacs/nrf9120-pac/src/twim0_ns/rxd.rs new file mode 100644 index 00000000..6a264182 --- /dev/null +++ b/pacs/nrf9120-pac/src/twim0_ns/rxd.rs @@ -0,0 +1,28 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RXD { + #[doc = "0x00 - Data pointer"] + pub ptr: PTR, + #[doc = "0x04 - Maximum number of bytes in receive buffer"] + pub maxcnt: MAXCNT, + #[doc = "0x08 - Number of bytes transferred in the last transaction"] + pub amount: AMOUNT, + #[doc = "0x0c - EasyDMA list type"] + pub list: LIST, +} +#[doc = "PTR (rw) register accessor: an alias for `Reg`"] +pub type PTR = crate::Reg; +#[doc = "Data pointer"] +pub mod ptr; +#[doc = "MAXCNT (rw) register accessor: an alias for `Reg`"] +pub type MAXCNT = crate::Reg; +#[doc = "Maximum number of bytes in receive buffer"] +pub mod maxcnt; +#[doc = "AMOUNT (r) register accessor: an alias for `Reg`"] +pub type AMOUNT = crate::Reg; +#[doc = "Number of bytes transferred in the last transaction"] +pub mod amount; +#[doc = "LIST (rw) register accessor: an alias for `Reg`"] +pub type LIST = crate::Reg; +#[doc = "EasyDMA list type"] +pub mod list; diff --git a/pacs/nrf9120-pac/src/twim0_ns/rxd/amount.rs b/pacs/nrf9120-pac/src/twim0_ns/rxd/amount.rs new file mode 100644 index 00000000..70bb5e68 --- /dev/null +++ b/pacs/nrf9120-pac/src/twim0_ns/rxd/amount.rs @@ -0,0 +1,40 @@ +#[doc = "Register `AMOUNT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `AMOUNT` reader - Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte."] +pub type AMOUNT_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:12 - Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte."] + #[inline(always)] + pub fn amount(&self) -> AMOUNT_R { + AMOUNT_R::new((self.bits & 0x1fff) as u16) + } +} +#[doc = "Number of bytes transferred in the last transaction\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [amount](index.html) module"] +pub struct AMOUNT_SPEC; +impl crate::RegisterSpec for AMOUNT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [amount::R](R) reader structure"] +impl crate::Readable for AMOUNT_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets AMOUNT to value 0"] +impl crate::Resettable for AMOUNT_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/twim0_ns/rxd/list.rs b/pacs/nrf9120-pac/src/twim0_ns/rxd/list.rs new file mode 100644 index 00000000..aa379b8c --- /dev/null +++ b/pacs/nrf9120-pac/src/twim0_ns/rxd/list.rs @@ -0,0 +1,128 @@ +#[doc = "Register `LIST` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `LIST` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `LIST` reader - List type"] +pub type LIST_R = crate::FieldReader; +#[doc = "List type\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum LIST_A { + #[doc = "0: Disable EasyDMA list"] + DISABLED = 0, + #[doc = "1: Use array list"] + ARRAY_LIST = 1, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LIST_A) -> Self { + variant as _ + } +} +impl LIST_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(LIST_A::DISABLED), + 1 => Some(LIST_A::ARRAY_LIST), + _ => None, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == LIST_A::DISABLED + } + #[doc = "Checks if the value of the field is `ARRAY_LIST`"] + #[inline(always)] + pub fn is_array_list(&self) -> bool { + *self == LIST_A::ARRAY_LIST + } +} +#[doc = "Field `LIST` writer - List type"] +pub type LIST_W<'a, const O: u8> = crate::FieldWriter<'a, u32, LIST_SPEC, u8, LIST_A, 2, O>; +impl<'a, const O: u8> LIST_W<'a, O> { + #[doc = "Disable EasyDMA list"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(LIST_A::DISABLED) + } + #[doc = "Use array list"] + #[inline(always)] + pub fn array_list(self) -> &'a mut W { + self.variant(LIST_A::ARRAY_LIST) + } +} +impl R { + #[doc = "Bits 0:1 - List type"] + #[inline(always)] + pub fn list(&self) -> LIST_R { + LIST_R::new((self.bits & 3) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - List type"] + #[inline(always)] + pub fn list(&mut self) -> LIST_W<0> { + LIST_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "EasyDMA list type\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [list](index.html) module"] +pub struct LIST_SPEC; +impl crate::RegisterSpec for LIST_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [list::R](R) reader structure"] +impl crate::Readable for LIST_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [list::W](W) writer structure"] +impl crate::Writable for LIST_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets LIST to value 0"] +impl crate::Resettable for LIST_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/twim0_ns/rxd/maxcnt.rs b/pacs/nrf9120-pac/src/twim0_ns/rxd/maxcnt.rs new file mode 100644 index 00000000..0344ca9e --- /dev/null +++ b/pacs/nrf9120-pac/src/twim0_ns/rxd/maxcnt.rs @@ -0,0 +1,80 @@ +#[doc = "Register `MAXCNT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `MAXCNT` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `MAXCNT` reader - Maximum number of bytes in receive buffer"] +pub type MAXCNT_R = crate::FieldReader; +#[doc = "Field `MAXCNT` writer - Maximum number of bytes in receive buffer"] +pub type MAXCNT_W<'a, const O: u8> = crate::FieldWriter<'a, u32, MAXCNT_SPEC, u16, u16, 13, O>; +impl R { + #[doc = "Bits 0:12 - Maximum number of bytes in receive buffer"] + #[inline(always)] + pub fn maxcnt(&self) -> MAXCNT_R { + MAXCNT_R::new((self.bits & 0x1fff) as u16) + } +} +impl W { + #[doc = "Bits 0:12 - Maximum number of bytes in receive buffer"] + #[inline(always)] + pub fn maxcnt(&mut self) -> MAXCNT_W<0> { + MAXCNT_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Maximum number of bytes in receive buffer\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [maxcnt](index.html) module"] +pub struct MAXCNT_SPEC; +impl crate::RegisterSpec for MAXCNT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [maxcnt::R](R) reader structure"] +impl crate::Readable for MAXCNT_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [maxcnt::W](W) writer structure"] +impl crate::Writable for MAXCNT_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets MAXCNT to value 0"] +impl crate::Resettable for MAXCNT_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/twim0_ns/rxd/ptr.rs b/pacs/nrf9120-pac/src/twim0_ns/rxd/ptr.rs new file mode 100644 index 00000000..d5f98439 --- /dev/null +++ b/pacs/nrf9120-pac/src/twim0_ns/rxd/ptr.rs @@ -0,0 +1,80 @@ +#[doc = "Register `PTR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PTR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PTR` reader - Data pointer"] +pub type PTR_R = crate::FieldReader; +#[doc = "Field `PTR` writer - Data pointer"] +pub type PTR_W<'a, const O: u8> = crate::FieldWriter<'a, u32, PTR_SPEC, u32, u32, 32, O>; +impl R { + #[doc = "Bits 0:31 - Data pointer"] + #[inline(always)] + pub fn ptr(&self) -> PTR_R { + PTR_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Data pointer"] + #[inline(always)] + pub fn ptr(&mut self) -> PTR_W<0> { + PTR_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Data pointer\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ptr](index.html) module"] +pub struct PTR_SPEC; +impl crate::RegisterSpec for PTR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ptr::R](R) reader structure"] +impl crate::Readable for PTR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ptr::W](W) writer structure"] +impl crate::Writable for PTR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PTR to value 0"] +impl crate::Resettable for PTR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/twim0_ns/shorts.rs b/pacs/nrf9120-pac/src/twim0_ns/shorts.rs new file mode 100644 index 00000000..5349370d --- /dev/null +++ b/pacs/nrf9120-pac/src/twim0_ns/shorts.rs @@ -0,0 +1,369 @@ +#[doc = "Register `SHORTS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SHORTS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `LASTTX_STARTRX` reader - Shortcut between event LASTTX and task STARTRX"] +pub type LASTTX_STARTRX_R = crate::BitReader; +#[doc = "Shortcut between event LASTTX and task STARTRX\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum LASTTX_STARTRX_A { + #[doc = "0: Disable shortcut"] + DISABLED = 0, + #[doc = "1: Enable shortcut"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: LASTTX_STARTRX_A) -> Self { + variant as u8 != 0 + } +} +impl LASTTX_STARTRX_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> LASTTX_STARTRX_A { + match self.bits { + false => LASTTX_STARTRX_A::DISABLED, + true => LASTTX_STARTRX_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == LASTTX_STARTRX_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == LASTTX_STARTRX_A::ENABLED + } +} +#[doc = "Field `LASTTX_STARTRX` writer - Shortcut between event LASTTX and task STARTRX"] +pub type LASTTX_STARTRX_W<'a, const O: u8> = + crate::BitWriter<'a, u32, SHORTS_SPEC, LASTTX_STARTRX_A, O>; +impl<'a, const O: u8> LASTTX_STARTRX_W<'a, O> { + #[doc = "Disable shortcut"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(LASTTX_STARTRX_A::DISABLED) + } + #[doc = "Enable shortcut"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(LASTTX_STARTRX_A::ENABLED) + } +} +#[doc = "Field `LASTTX_SUSPEND` reader - Shortcut between event LASTTX and task SUSPEND"] +pub type LASTTX_SUSPEND_R = crate::BitReader; +#[doc = "Shortcut between event LASTTX and task SUSPEND\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum LASTTX_SUSPEND_A { + #[doc = "0: Disable shortcut"] + DISABLED = 0, + #[doc = "1: Enable shortcut"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: LASTTX_SUSPEND_A) -> Self { + variant as u8 != 0 + } +} +impl LASTTX_SUSPEND_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> LASTTX_SUSPEND_A { + match self.bits { + false => LASTTX_SUSPEND_A::DISABLED, + true => LASTTX_SUSPEND_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == LASTTX_SUSPEND_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == LASTTX_SUSPEND_A::ENABLED + } +} +#[doc = "Field `LASTTX_SUSPEND` writer - Shortcut between event LASTTX and task SUSPEND"] +pub type LASTTX_SUSPEND_W<'a, const O: u8> = + crate::BitWriter<'a, u32, SHORTS_SPEC, LASTTX_SUSPEND_A, O>; +impl<'a, const O: u8> LASTTX_SUSPEND_W<'a, O> { + #[doc = "Disable shortcut"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(LASTTX_SUSPEND_A::DISABLED) + } + #[doc = "Enable shortcut"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(LASTTX_SUSPEND_A::ENABLED) + } +} +#[doc = "Field `LASTTX_STOP` reader - Shortcut between event LASTTX and task STOP"] +pub type LASTTX_STOP_R = crate::BitReader; +#[doc = "Shortcut between event LASTTX and task STOP\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum LASTTX_STOP_A { + #[doc = "0: Disable shortcut"] + DISABLED = 0, + #[doc = "1: Enable shortcut"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: LASTTX_STOP_A) -> Self { + variant as u8 != 0 + } +} +impl LASTTX_STOP_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> LASTTX_STOP_A { + match self.bits { + false => LASTTX_STOP_A::DISABLED, + true => LASTTX_STOP_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == LASTTX_STOP_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == LASTTX_STOP_A::ENABLED + } +} +#[doc = "Field `LASTTX_STOP` writer - Shortcut between event LASTTX and task STOP"] +pub type LASTTX_STOP_W<'a, const O: u8> = crate::BitWriter<'a, u32, SHORTS_SPEC, LASTTX_STOP_A, O>; +impl<'a, const O: u8> LASTTX_STOP_W<'a, O> { + #[doc = "Disable shortcut"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(LASTTX_STOP_A::DISABLED) + } + #[doc = "Enable shortcut"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(LASTTX_STOP_A::ENABLED) + } +} +#[doc = "Field `LASTRX_STARTTX` reader - Shortcut between event LASTRX and task STARTTX"] +pub type LASTRX_STARTTX_R = crate::BitReader; +#[doc = "Shortcut between event LASTRX and task STARTTX\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum LASTRX_STARTTX_A { + #[doc = "0: Disable shortcut"] + DISABLED = 0, + #[doc = "1: Enable shortcut"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: LASTRX_STARTTX_A) -> Self { + variant as u8 != 0 + } +} +impl LASTRX_STARTTX_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> LASTRX_STARTTX_A { + match self.bits { + false => LASTRX_STARTTX_A::DISABLED, + true => LASTRX_STARTTX_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == LASTRX_STARTTX_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == LASTRX_STARTTX_A::ENABLED + } +} +#[doc = "Field `LASTRX_STARTTX` writer - Shortcut between event LASTRX and task STARTTX"] +pub type LASTRX_STARTTX_W<'a, const O: u8> = + crate::BitWriter<'a, u32, SHORTS_SPEC, LASTRX_STARTTX_A, O>; +impl<'a, const O: u8> LASTRX_STARTTX_W<'a, O> { + #[doc = "Disable shortcut"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(LASTRX_STARTTX_A::DISABLED) + } + #[doc = "Enable shortcut"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(LASTRX_STARTTX_A::ENABLED) + } +} +#[doc = "Field `LASTRX_STOP` reader - Shortcut between event LASTRX and task STOP"] +pub type LASTRX_STOP_R = crate::BitReader; +#[doc = "Shortcut between event LASTRX and task STOP\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum LASTRX_STOP_A { + #[doc = "0: Disable shortcut"] + DISABLED = 0, + #[doc = "1: Enable shortcut"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: LASTRX_STOP_A) -> Self { + variant as u8 != 0 + } +} +impl LASTRX_STOP_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> LASTRX_STOP_A { + match self.bits { + false => LASTRX_STOP_A::DISABLED, + true => LASTRX_STOP_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == LASTRX_STOP_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == LASTRX_STOP_A::ENABLED + } +} +#[doc = "Field `LASTRX_STOP` writer - Shortcut between event LASTRX and task STOP"] +pub type LASTRX_STOP_W<'a, const O: u8> = crate::BitWriter<'a, u32, SHORTS_SPEC, LASTRX_STOP_A, O>; +impl<'a, const O: u8> LASTRX_STOP_W<'a, O> { + #[doc = "Disable shortcut"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(LASTRX_STOP_A::DISABLED) + } + #[doc = "Enable shortcut"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(LASTRX_STOP_A::ENABLED) + } +} +impl R { + #[doc = "Bit 7 - Shortcut between event LASTTX and task STARTRX"] + #[inline(always)] + pub fn lasttx_startrx(&self) -> LASTTX_STARTRX_R { + LASTTX_STARTRX_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Shortcut between event LASTTX and task SUSPEND"] + #[inline(always)] + pub fn lasttx_suspend(&self) -> LASTTX_SUSPEND_R { + LASTTX_SUSPEND_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Shortcut between event LASTTX and task STOP"] + #[inline(always)] + pub fn lasttx_stop(&self) -> LASTTX_STOP_R { + LASTTX_STOP_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Shortcut between event LASTRX and task STARTTX"] + #[inline(always)] + pub fn lastrx_starttx(&self) -> LASTRX_STARTTX_R { + LASTRX_STARTTX_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 12 - Shortcut between event LASTRX and task STOP"] + #[inline(always)] + pub fn lastrx_stop(&self) -> LASTRX_STOP_R { + LASTRX_STOP_R::new(((self.bits >> 12) & 1) != 0) + } +} +impl W { + #[doc = "Bit 7 - Shortcut between event LASTTX and task STARTRX"] + #[inline(always)] + pub fn lasttx_startrx(&mut self) -> LASTTX_STARTRX_W<7> { + LASTTX_STARTRX_W::new(self) + } + #[doc = "Bit 8 - Shortcut between event LASTTX and task SUSPEND"] + #[inline(always)] + pub fn lasttx_suspend(&mut self) -> LASTTX_SUSPEND_W<8> { + LASTTX_SUSPEND_W::new(self) + } + #[doc = "Bit 9 - Shortcut between event LASTTX and task STOP"] + #[inline(always)] + pub fn lasttx_stop(&mut self) -> LASTTX_STOP_W<9> { + LASTTX_STOP_W::new(self) + } + #[doc = "Bit 10 - Shortcut between event LASTRX and task STARTTX"] + #[inline(always)] + pub fn lastrx_starttx(&mut self) -> LASTRX_STARTTX_W<10> { + LASTRX_STARTTX_W::new(self) + } + #[doc = "Bit 12 - Shortcut between event LASTRX and task STOP"] + #[inline(always)] + pub fn lastrx_stop(&mut self) -> LASTRX_STOP_W<12> { + LASTRX_STOP_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Shortcuts between local events and tasks\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [shorts](index.html) module"] +pub struct SHORTS_SPEC; +impl crate::RegisterSpec for SHORTS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [shorts::R](R) reader structure"] +impl crate::Readable for SHORTS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [shorts::W](W) writer structure"] +impl crate::Writable for SHORTS_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SHORTS to value 0"] +impl crate::Resettable for SHORTS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/twim0_ns/subscribe_resume.rs b/pacs/nrf9120-pac/src/twim0_ns/subscribe_resume.rs new file mode 100644 index 00000000..cef10f00 --- /dev/null +++ b/pacs/nrf9120-pac/src/twim0_ns/subscribe_resume.rs @@ -0,0 +1,141 @@ +#[doc = "Register `SUBSCRIBE_RESUME` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SUBSCRIBE_RESUME` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CHIDX` reader - DPPI channel that task RESUME will subscribe to"] +pub type CHIDX_R = crate::FieldReader; +#[doc = "Field `CHIDX` writer - DPPI channel that task RESUME will subscribe to"] +pub type CHIDX_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, SUBSCRIBE_RESUME_SPEC, u8, u8, 8, O>; +#[doc = "Field `EN` reader - "] +pub type EN_R = crate::BitReader; +#[doc = "\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum EN_A { + #[doc = "0: Disable subscription"] + DISABLED = 0, + #[doc = "1: Enable subscription"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: EN_A) -> Self { + variant as u8 != 0 + } +} +impl EN_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EN_A { + match self.bits { + false => EN_A::DISABLED, + true => EN_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == EN_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == EN_A::ENABLED + } +} +#[doc = "Field `EN` writer - "] +pub type EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, SUBSCRIBE_RESUME_SPEC, EN_A, O>; +impl<'a, const O: u8> EN_W<'a, O> { + #[doc = "Disable subscription"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(EN_A::DISABLED) + } + #[doc = "Enable subscription"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(EN_A::ENABLED) + } +} +impl R { + #[doc = "Bits 0:7 - DPPI channel that task RESUME will subscribe to"] + #[inline(always)] + pub fn chidx(&self) -> CHIDX_R { + CHIDX_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&self) -> EN_R { + EN_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:7 - DPPI channel that task RESUME will subscribe to"] + #[inline(always)] + pub fn chidx(&mut self) -> CHIDX_W<0> { + CHIDX_W::new(self) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&mut self) -> EN_W<31> { + EN_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Subscribe configuration for task RESUME\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [subscribe_resume](index.html) module"] +pub struct SUBSCRIBE_RESUME_SPEC; +impl crate::RegisterSpec for SUBSCRIBE_RESUME_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [subscribe_resume::R](R) reader structure"] +impl crate::Readable for SUBSCRIBE_RESUME_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [subscribe_resume::W](W) writer structure"] +impl crate::Writable for SUBSCRIBE_RESUME_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SUBSCRIBE_RESUME to value 0"] +impl crate::Resettable for SUBSCRIBE_RESUME_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/twim0_ns/subscribe_startrx.rs b/pacs/nrf9120-pac/src/twim0_ns/subscribe_startrx.rs new file mode 100644 index 00000000..83be54e3 --- /dev/null +++ b/pacs/nrf9120-pac/src/twim0_ns/subscribe_startrx.rs @@ -0,0 +1,141 @@ +#[doc = "Register `SUBSCRIBE_STARTRX` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SUBSCRIBE_STARTRX` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CHIDX` reader - DPPI channel that task STARTRX will subscribe to"] +pub type CHIDX_R = crate::FieldReader; +#[doc = "Field `CHIDX` writer - DPPI channel that task STARTRX will subscribe to"] +pub type CHIDX_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, SUBSCRIBE_STARTRX_SPEC, u8, u8, 8, O>; +#[doc = "Field `EN` reader - "] +pub type EN_R = crate::BitReader; +#[doc = "\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum EN_A { + #[doc = "0: Disable subscription"] + DISABLED = 0, + #[doc = "1: Enable subscription"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: EN_A) -> Self { + variant as u8 != 0 + } +} +impl EN_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EN_A { + match self.bits { + false => EN_A::DISABLED, + true => EN_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == EN_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == EN_A::ENABLED + } +} +#[doc = "Field `EN` writer - "] +pub type EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, SUBSCRIBE_STARTRX_SPEC, EN_A, O>; +impl<'a, const O: u8> EN_W<'a, O> { + #[doc = "Disable subscription"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(EN_A::DISABLED) + } + #[doc = "Enable subscription"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(EN_A::ENABLED) + } +} +impl R { + #[doc = "Bits 0:7 - DPPI channel that task STARTRX will subscribe to"] + #[inline(always)] + pub fn chidx(&self) -> CHIDX_R { + CHIDX_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&self) -> EN_R { + EN_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:7 - DPPI channel that task STARTRX will subscribe to"] + #[inline(always)] + pub fn chidx(&mut self) -> CHIDX_W<0> { + CHIDX_W::new(self) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&mut self) -> EN_W<31> { + EN_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Subscribe configuration for task STARTRX\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [subscribe_startrx](index.html) module"] +pub struct SUBSCRIBE_STARTRX_SPEC; +impl crate::RegisterSpec for SUBSCRIBE_STARTRX_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [subscribe_startrx::R](R) reader structure"] +impl crate::Readable for SUBSCRIBE_STARTRX_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [subscribe_startrx::W](W) writer structure"] +impl crate::Writable for SUBSCRIBE_STARTRX_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SUBSCRIBE_STARTRX to value 0"] +impl crate::Resettable for SUBSCRIBE_STARTRX_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/twim0_ns/subscribe_starttx.rs b/pacs/nrf9120-pac/src/twim0_ns/subscribe_starttx.rs new file mode 100644 index 00000000..fca12315 --- /dev/null +++ b/pacs/nrf9120-pac/src/twim0_ns/subscribe_starttx.rs @@ -0,0 +1,141 @@ +#[doc = "Register `SUBSCRIBE_STARTTX` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SUBSCRIBE_STARTTX` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CHIDX` reader - DPPI channel that task STARTTX will subscribe to"] +pub type CHIDX_R = crate::FieldReader; +#[doc = "Field `CHIDX` writer - DPPI channel that task STARTTX will subscribe to"] +pub type CHIDX_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, SUBSCRIBE_STARTTX_SPEC, u8, u8, 8, O>; +#[doc = "Field `EN` reader - "] +pub type EN_R = crate::BitReader; +#[doc = "\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum EN_A { + #[doc = "0: Disable subscription"] + DISABLED = 0, + #[doc = "1: Enable subscription"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: EN_A) -> Self { + variant as u8 != 0 + } +} +impl EN_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EN_A { + match self.bits { + false => EN_A::DISABLED, + true => EN_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == EN_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == EN_A::ENABLED + } +} +#[doc = "Field `EN` writer - "] +pub type EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, SUBSCRIBE_STARTTX_SPEC, EN_A, O>; +impl<'a, const O: u8> EN_W<'a, O> { + #[doc = "Disable subscription"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(EN_A::DISABLED) + } + #[doc = "Enable subscription"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(EN_A::ENABLED) + } +} +impl R { + #[doc = "Bits 0:7 - DPPI channel that task STARTTX will subscribe to"] + #[inline(always)] + pub fn chidx(&self) -> CHIDX_R { + CHIDX_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&self) -> EN_R { + EN_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:7 - DPPI channel that task STARTTX will subscribe to"] + #[inline(always)] + pub fn chidx(&mut self) -> CHIDX_W<0> { + CHIDX_W::new(self) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&mut self) -> EN_W<31> { + EN_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Subscribe configuration for task STARTTX\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [subscribe_starttx](index.html) module"] +pub struct SUBSCRIBE_STARTTX_SPEC; +impl crate::RegisterSpec for SUBSCRIBE_STARTTX_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [subscribe_starttx::R](R) reader structure"] +impl crate::Readable for SUBSCRIBE_STARTTX_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [subscribe_starttx::W](W) writer structure"] +impl crate::Writable for SUBSCRIBE_STARTTX_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SUBSCRIBE_STARTTX to value 0"] +impl crate::Resettable for SUBSCRIBE_STARTTX_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/twim0_ns/subscribe_stop.rs b/pacs/nrf9120-pac/src/twim0_ns/subscribe_stop.rs new file mode 100644 index 00000000..2fe3af58 --- /dev/null +++ b/pacs/nrf9120-pac/src/twim0_ns/subscribe_stop.rs @@ -0,0 +1,140 @@ +#[doc = "Register `SUBSCRIBE_STOP` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SUBSCRIBE_STOP` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CHIDX` reader - DPPI channel that task STOP will subscribe to"] +pub type CHIDX_R = crate::FieldReader; +#[doc = "Field `CHIDX` writer - DPPI channel that task STOP will subscribe to"] +pub type CHIDX_W<'a, const O: u8> = crate::FieldWriter<'a, u32, SUBSCRIBE_STOP_SPEC, u8, u8, 8, O>; +#[doc = "Field `EN` reader - "] +pub type EN_R = crate::BitReader; +#[doc = "\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum EN_A { + #[doc = "0: Disable subscription"] + DISABLED = 0, + #[doc = "1: Enable subscription"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: EN_A) -> Self { + variant as u8 != 0 + } +} +impl EN_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EN_A { + match self.bits { + false => EN_A::DISABLED, + true => EN_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == EN_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == EN_A::ENABLED + } +} +#[doc = "Field `EN` writer - "] +pub type EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, SUBSCRIBE_STOP_SPEC, EN_A, O>; +impl<'a, const O: u8> EN_W<'a, O> { + #[doc = "Disable subscription"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(EN_A::DISABLED) + } + #[doc = "Enable subscription"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(EN_A::ENABLED) + } +} +impl R { + #[doc = "Bits 0:7 - DPPI channel that task STOP will subscribe to"] + #[inline(always)] + pub fn chidx(&self) -> CHIDX_R { + CHIDX_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&self) -> EN_R { + EN_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:7 - DPPI channel that task STOP will subscribe to"] + #[inline(always)] + pub fn chidx(&mut self) -> CHIDX_W<0> { + CHIDX_W::new(self) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&mut self) -> EN_W<31> { + EN_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Subscribe configuration for task STOP\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [subscribe_stop](index.html) module"] +pub struct SUBSCRIBE_STOP_SPEC; +impl crate::RegisterSpec for SUBSCRIBE_STOP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [subscribe_stop::R](R) reader structure"] +impl crate::Readable for SUBSCRIBE_STOP_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [subscribe_stop::W](W) writer structure"] +impl crate::Writable for SUBSCRIBE_STOP_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SUBSCRIBE_STOP to value 0"] +impl crate::Resettable for SUBSCRIBE_STOP_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/twim0_ns/subscribe_suspend.rs b/pacs/nrf9120-pac/src/twim0_ns/subscribe_suspend.rs new file mode 100644 index 00000000..b3fe4912 --- /dev/null +++ b/pacs/nrf9120-pac/src/twim0_ns/subscribe_suspend.rs @@ -0,0 +1,141 @@ +#[doc = "Register `SUBSCRIBE_SUSPEND` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SUBSCRIBE_SUSPEND` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CHIDX` reader - DPPI channel that task SUSPEND will subscribe to"] +pub type CHIDX_R = crate::FieldReader; +#[doc = "Field `CHIDX` writer - DPPI channel that task SUSPEND will subscribe to"] +pub type CHIDX_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, SUBSCRIBE_SUSPEND_SPEC, u8, u8, 8, O>; +#[doc = "Field `EN` reader - "] +pub type EN_R = crate::BitReader; +#[doc = "\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum EN_A { + #[doc = "0: Disable subscription"] + DISABLED = 0, + #[doc = "1: Enable subscription"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: EN_A) -> Self { + variant as u8 != 0 + } +} +impl EN_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EN_A { + match self.bits { + false => EN_A::DISABLED, + true => EN_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == EN_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == EN_A::ENABLED + } +} +#[doc = "Field `EN` writer - "] +pub type EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, SUBSCRIBE_SUSPEND_SPEC, EN_A, O>; +impl<'a, const O: u8> EN_W<'a, O> { + #[doc = "Disable subscription"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(EN_A::DISABLED) + } + #[doc = "Enable subscription"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(EN_A::ENABLED) + } +} +impl R { + #[doc = "Bits 0:7 - DPPI channel that task SUSPEND will subscribe to"] + #[inline(always)] + pub fn chidx(&self) -> CHIDX_R { + CHIDX_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&self) -> EN_R { + EN_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:7 - DPPI channel that task SUSPEND will subscribe to"] + #[inline(always)] + pub fn chidx(&mut self) -> CHIDX_W<0> { + CHIDX_W::new(self) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&mut self) -> EN_W<31> { + EN_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Subscribe configuration for task SUSPEND\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [subscribe_suspend](index.html) module"] +pub struct SUBSCRIBE_SUSPEND_SPEC; +impl crate::RegisterSpec for SUBSCRIBE_SUSPEND_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [subscribe_suspend::R](R) reader structure"] +impl crate::Readable for SUBSCRIBE_SUSPEND_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [subscribe_suspend::W](W) writer structure"] +impl crate::Writable for SUBSCRIBE_SUSPEND_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SUBSCRIBE_SUSPEND to value 0"] +impl crate::Resettable for SUBSCRIBE_SUSPEND_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/twim0_ns/tasks_resume.rs b/pacs/nrf9120-pac/src/twim0_ns/tasks_resume.rs new file mode 100644 index 00000000..f246e04d --- /dev/null +++ b/pacs/nrf9120-pac/src/twim0_ns/tasks_resume.rs @@ -0,0 +1,72 @@ +#[doc = "Register `TASKS_RESUME` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Resume TWI transaction\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum TASKS_RESUME_AW { + #[doc = "1: Trigger task"] + TRIGGER = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TASKS_RESUME_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TASKS_RESUME` writer - Resume TWI transaction"] +pub type TASKS_RESUME_W<'a, const O: u8> = + crate::BitWriter<'a, u32, TASKS_RESUME_SPEC, TASKS_RESUME_AW, O>; +impl<'a, const O: u8> TASKS_RESUME_W<'a, O> { + #[doc = "Trigger task"] + #[inline(always)] + pub fn trigger(self) -> &'a mut W { + self.variant(TASKS_RESUME_AW::TRIGGER) + } +} +impl W { + #[doc = "Bit 0 - Resume TWI transaction"] + #[inline(always)] + pub fn tasks_resume(&mut self) -> TASKS_RESUME_W<0> { + TASKS_RESUME_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Resume TWI transaction\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tasks_resume](index.html) module"] +pub struct TASKS_RESUME_SPEC; +impl crate::RegisterSpec for TASKS_RESUME_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [tasks_resume::W](W) writer structure"] +impl crate::Writable for TASKS_RESUME_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets TASKS_RESUME to value 0"] +impl crate::Resettable for TASKS_RESUME_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/twim0_ns/tasks_startrx.rs b/pacs/nrf9120-pac/src/twim0_ns/tasks_startrx.rs new file mode 100644 index 00000000..984ede6b --- /dev/null +++ b/pacs/nrf9120-pac/src/twim0_ns/tasks_startrx.rs @@ -0,0 +1,72 @@ +#[doc = "Register `TASKS_STARTRX` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Start TWI receive sequence\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum TASKS_STARTRX_AW { + #[doc = "1: Trigger task"] + TRIGGER = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TASKS_STARTRX_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TASKS_STARTRX` writer - Start TWI receive sequence"] +pub type TASKS_STARTRX_W<'a, const O: u8> = + crate::BitWriter<'a, u32, TASKS_STARTRX_SPEC, TASKS_STARTRX_AW, O>; +impl<'a, const O: u8> TASKS_STARTRX_W<'a, O> { + #[doc = "Trigger task"] + #[inline(always)] + pub fn trigger(self) -> &'a mut W { + self.variant(TASKS_STARTRX_AW::TRIGGER) + } +} +impl W { + #[doc = "Bit 0 - Start TWI receive sequence"] + #[inline(always)] + pub fn tasks_startrx(&mut self) -> TASKS_STARTRX_W<0> { + TASKS_STARTRX_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Start TWI receive sequence\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tasks_startrx](index.html) module"] +pub struct TASKS_STARTRX_SPEC; +impl crate::RegisterSpec for TASKS_STARTRX_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [tasks_startrx::W](W) writer structure"] +impl crate::Writable for TASKS_STARTRX_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets TASKS_STARTRX to value 0"] +impl crate::Resettable for TASKS_STARTRX_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/twim0_ns/tasks_starttx.rs b/pacs/nrf9120-pac/src/twim0_ns/tasks_starttx.rs new file mode 100644 index 00000000..58b6ec38 --- /dev/null +++ b/pacs/nrf9120-pac/src/twim0_ns/tasks_starttx.rs @@ -0,0 +1,72 @@ +#[doc = "Register `TASKS_STARTTX` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Start TWI transmit sequence\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum TASKS_STARTTX_AW { + #[doc = "1: Trigger task"] + TRIGGER = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TASKS_STARTTX_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TASKS_STARTTX` writer - Start TWI transmit sequence"] +pub type TASKS_STARTTX_W<'a, const O: u8> = + crate::BitWriter<'a, u32, TASKS_STARTTX_SPEC, TASKS_STARTTX_AW, O>; +impl<'a, const O: u8> TASKS_STARTTX_W<'a, O> { + #[doc = "Trigger task"] + #[inline(always)] + pub fn trigger(self) -> &'a mut W { + self.variant(TASKS_STARTTX_AW::TRIGGER) + } +} +impl W { + #[doc = "Bit 0 - Start TWI transmit sequence"] + #[inline(always)] + pub fn tasks_starttx(&mut self) -> TASKS_STARTTX_W<0> { + TASKS_STARTTX_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Start TWI transmit sequence\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tasks_starttx](index.html) module"] +pub struct TASKS_STARTTX_SPEC; +impl crate::RegisterSpec for TASKS_STARTTX_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [tasks_starttx::W](W) writer structure"] +impl crate::Writable for TASKS_STARTTX_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets TASKS_STARTTX to value 0"] +impl crate::Resettable for TASKS_STARTTX_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/twim0_ns/tasks_stop.rs b/pacs/nrf9120-pac/src/twim0_ns/tasks_stop.rs new file mode 100644 index 00000000..903d6f78 --- /dev/null +++ b/pacs/nrf9120-pac/src/twim0_ns/tasks_stop.rs @@ -0,0 +1,72 @@ +#[doc = "Register `TASKS_STOP` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Stop TWI transaction. Must be issued while the TWI master is not suspended.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum TASKS_STOP_AW { + #[doc = "1: Trigger task"] + TRIGGER = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TASKS_STOP_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TASKS_STOP` writer - Stop TWI transaction. Must be issued while the TWI master is not suspended."] +pub type TASKS_STOP_W<'a, const O: u8> = + crate::BitWriter<'a, u32, TASKS_STOP_SPEC, TASKS_STOP_AW, O>; +impl<'a, const O: u8> TASKS_STOP_W<'a, O> { + #[doc = "Trigger task"] + #[inline(always)] + pub fn trigger(self) -> &'a mut W { + self.variant(TASKS_STOP_AW::TRIGGER) + } +} +impl W { + #[doc = "Bit 0 - Stop TWI transaction. Must be issued while the TWI master is not suspended."] + #[inline(always)] + pub fn tasks_stop(&mut self) -> TASKS_STOP_W<0> { + TASKS_STOP_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Stop TWI transaction. Must be issued while the TWI master is not suspended.\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tasks_stop](index.html) module"] +pub struct TASKS_STOP_SPEC; +impl crate::RegisterSpec for TASKS_STOP_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [tasks_stop::W](W) writer structure"] +impl crate::Writable for TASKS_STOP_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets TASKS_STOP to value 0"] +impl crate::Resettable for TASKS_STOP_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/twim0_ns/tasks_suspend.rs b/pacs/nrf9120-pac/src/twim0_ns/tasks_suspend.rs new file mode 100644 index 00000000..37884f26 --- /dev/null +++ b/pacs/nrf9120-pac/src/twim0_ns/tasks_suspend.rs @@ -0,0 +1,72 @@ +#[doc = "Register `TASKS_SUSPEND` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Suspend TWI transaction\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum TASKS_SUSPEND_AW { + #[doc = "1: Trigger task"] + TRIGGER = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TASKS_SUSPEND_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TASKS_SUSPEND` writer - Suspend TWI transaction"] +pub type TASKS_SUSPEND_W<'a, const O: u8> = + crate::BitWriter<'a, u32, TASKS_SUSPEND_SPEC, TASKS_SUSPEND_AW, O>; +impl<'a, const O: u8> TASKS_SUSPEND_W<'a, O> { + #[doc = "Trigger task"] + #[inline(always)] + pub fn trigger(self) -> &'a mut W { + self.variant(TASKS_SUSPEND_AW::TRIGGER) + } +} +impl W { + #[doc = "Bit 0 - Suspend TWI transaction"] + #[inline(always)] + pub fn tasks_suspend(&mut self) -> TASKS_SUSPEND_W<0> { + TASKS_SUSPEND_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Suspend TWI transaction\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tasks_suspend](index.html) module"] +pub struct TASKS_SUSPEND_SPEC; +impl crate::RegisterSpec for TASKS_SUSPEND_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [tasks_suspend::W](W) writer structure"] +impl crate::Writable for TASKS_SUSPEND_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets TASKS_SUSPEND to value 0"] +impl crate::Resettable for TASKS_SUSPEND_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/twim0_ns/txd.rs b/pacs/nrf9120-pac/src/twim0_ns/txd.rs new file mode 100644 index 00000000..19ea101d --- /dev/null +++ b/pacs/nrf9120-pac/src/twim0_ns/txd.rs @@ -0,0 +1,28 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct TXD { + #[doc = "0x00 - Data pointer"] + pub ptr: PTR, + #[doc = "0x04 - Maximum number of bytes in transmit buffer"] + pub maxcnt: MAXCNT, + #[doc = "0x08 - Number of bytes transferred in the last transaction"] + pub amount: AMOUNT, + #[doc = "0x0c - EasyDMA list type"] + pub list: LIST, +} +#[doc = "PTR (rw) register accessor: an alias for `Reg`"] +pub type PTR = crate::Reg; +#[doc = "Data pointer"] +pub mod ptr; +#[doc = "MAXCNT (rw) register accessor: an alias for `Reg`"] +pub type MAXCNT = crate::Reg; +#[doc = "Maximum number of bytes in transmit buffer"] +pub mod maxcnt; +#[doc = "AMOUNT (r) register accessor: an alias for `Reg`"] +pub type AMOUNT = crate::Reg; +#[doc = "Number of bytes transferred in the last transaction"] +pub mod amount; +#[doc = "LIST (rw) register accessor: an alias for `Reg`"] +pub type LIST = crate::Reg; +#[doc = "EasyDMA list type"] +pub mod list; diff --git a/pacs/nrf9120-pac/src/twim0_ns/txd/amount.rs b/pacs/nrf9120-pac/src/twim0_ns/txd/amount.rs new file mode 100644 index 00000000..70bb5e68 --- /dev/null +++ b/pacs/nrf9120-pac/src/twim0_ns/txd/amount.rs @@ -0,0 +1,40 @@ +#[doc = "Register `AMOUNT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `AMOUNT` reader - Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte."] +pub type AMOUNT_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:12 - Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte."] + #[inline(always)] + pub fn amount(&self) -> AMOUNT_R { + AMOUNT_R::new((self.bits & 0x1fff) as u16) + } +} +#[doc = "Number of bytes transferred in the last transaction\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [amount](index.html) module"] +pub struct AMOUNT_SPEC; +impl crate::RegisterSpec for AMOUNT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [amount::R](R) reader structure"] +impl crate::Readable for AMOUNT_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets AMOUNT to value 0"] +impl crate::Resettable for AMOUNT_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/twim0_ns/txd/list.rs b/pacs/nrf9120-pac/src/twim0_ns/txd/list.rs new file mode 100644 index 00000000..aa379b8c --- /dev/null +++ b/pacs/nrf9120-pac/src/twim0_ns/txd/list.rs @@ -0,0 +1,128 @@ +#[doc = "Register `LIST` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `LIST` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `LIST` reader - List type"] +pub type LIST_R = crate::FieldReader; +#[doc = "List type\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum LIST_A { + #[doc = "0: Disable EasyDMA list"] + DISABLED = 0, + #[doc = "1: Use array list"] + ARRAY_LIST = 1, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LIST_A) -> Self { + variant as _ + } +} +impl LIST_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(LIST_A::DISABLED), + 1 => Some(LIST_A::ARRAY_LIST), + _ => None, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == LIST_A::DISABLED + } + #[doc = "Checks if the value of the field is `ARRAY_LIST`"] + #[inline(always)] + pub fn is_array_list(&self) -> bool { + *self == LIST_A::ARRAY_LIST + } +} +#[doc = "Field `LIST` writer - List type"] +pub type LIST_W<'a, const O: u8> = crate::FieldWriter<'a, u32, LIST_SPEC, u8, LIST_A, 2, O>; +impl<'a, const O: u8> LIST_W<'a, O> { + #[doc = "Disable EasyDMA list"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(LIST_A::DISABLED) + } + #[doc = "Use array list"] + #[inline(always)] + pub fn array_list(self) -> &'a mut W { + self.variant(LIST_A::ARRAY_LIST) + } +} +impl R { + #[doc = "Bits 0:1 - List type"] + #[inline(always)] + pub fn list(&self) -> LIST_R { + LIST_R::new((self.bits & 3) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - List type"] + #[inline(always)] + pub fn list(&mut self) -> LIST_W<0> { + LIST_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "EasyDMA list type\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [list](index.html) module"] +pub struct LIST_SPEC; +impl crate::RegisterSpec for LIST_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [list::R](R) reader structure"] +impl crate::Readable for LIST_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [list::W](W) writer structure"] +impl crate::Writable for LIST_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets LIST to value 0"] +impl crate::Resettable for LIST_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/twim0_ns/txd/maxcnt.rs b/pacs/nrf9120-pac/src/twim0_ns/txd/maxcnt.rs new file mode 100644 index 00000000..7ae96778 --- /dev/null +++ b/pacs/nrf9120-pac/src/twim0_ns/txd/maxcnt.rs @@ -0,0 +1,80 @@ +#[doc = "Register `MAXCNT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `MAXCNT` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `MAXCNT` reader - Maximum number of bytes in transmit buffer"] +pub type MAXCNT_R = crate::FieldReader; +#[doc = "Field `MAXCNT` writer - Maximum number of bytes in transmit buffer"] +pub type MAXCNT_W<'a, const O: u8> = crate::FieldWriter<'a, u32, MAXCNT_SPEC, u16, u16, 13, O>; +impl R { + #[doc = "Bits 0:12 - Maximum number of bytes in transmit buffer"] + #[inline(always)] + pub fn maxcnt(&self) -> MAXCNT_R { + MAXCNT_R::new((self.bits & 0x1fff) as u16) + } +} +impl W { + #[doc = "Bits 0:12 - Maximum number of bytes in transmit buffer"] + #[inline(always)] + pub fn maxcnt(&mut self) -> MAXCNT_W<0> { + MAXCNT_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Maximum number of bytes in transmit buffer\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [maxcnt](index.html) module"] +pub struct MAXCNT_SPEC; +impl crate::RegisterSpec for MAXCNT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [maxcnt::R](R) reader structure"] +impl crate::Readable for MAXCNT_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [maxcnt::W](W) writer structure"] +impl crate::Writable for MAXCNT_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets MAXCNT to value 0"] +impl crate::Resettable for MAXCNT_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/twim0_ns/txd/ptr.rs b/pacs/nrf9120-pac/src/twim0_ns/txd/ptr.rs new file mode 100644 index 00000000..d5f98439 --- /dev/null +++ b/pacs/nrf9120-pac/src/twim0_ns/txd/ptr.rs @@ -0,0 +1,80 @@ +#[doc = "Register `PTR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PTR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PTR` reader - Data pointer"] +pub type PTR_R = crate::FieldReader; +#[doc = "Field `PTR` writer - Data pointer"] +pub type PTR_W<'a, const O: u8> = crate::FieldWriter<'a, u32, PTR_SPEC, u32, u32, 32, O>; +impl R { + #[doc = "Bits 0:31 - Data pointer"] + #[inline(always)] + pub fn ptr(&self) -> PTR_R { + PTR_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Data pointer"] + #[inline(always)] + pub fn ptr(&mut self) -> PTR_W<0> { + PTR_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Data pointer\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ptr](index.html) module"] +pub struct PTR_SPEC; +impl crate::RegisterSpec for PTR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ptr::R](R) reader structure"] +impl crate::Readable for PTR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ptr::W](W) writer structure"] +impl crate::Writable for PTR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PTR to value 0"] +impl crate::Resettable for PTR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/twis0_ns.rs b/pacs/nrf9120-pac/src/twis0_ns.rs new file mode 100644 index 00000000..469ee8e8 --- /dev/null +++ b/pacs/nrf9120-pac/src/twis0_ns.rs @@ -0,0 +1,240 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + _reserved0: [u8; 0x14], + #[doc = "0x14 - Stop TWI transaction"] + pub tasks_stop: TASKS_STOP, + _reserved1: [u8; 0x04], + #[doc = "0x1c - Suspend TWI transaction"] + pub tasks_suspend: TASKS_SUSPEND, + #[doc = "0x20 - Resume TWI transaction"] + pub tasks_resume: TASKS_RESUME, + _reserved3: [u8; 0x0c], + #[doc = "0x30 - Prepare the TWI slave to respond to a write command"] + pub tasks_preparerx: TASKS_PREPARERX, + #[doc = "0x34 - Prepare the TWI slave to respond to a read command"] + pub tasks_preparetx: TASKS_PREPARETX, + _reserved5: [u8; 0x5c], + #[doc = "0x94 - Subscribe configuration for task STOP"] + pub subscribe_stop: SUBSCRIBE_STOP, + _reserved6: [u8; 0x04], + #[doc = "0x9c - Subscribe configuration for task SUSPEND"] + pub subscribe_suspend: SUBSCRIBE_SUSPEND, + #[doc = "0xa0 - Subscribe configuration for task RESUME"] + pub subscribe_resume: SUBSCRIBE_RESUME, + _reserved8: [u8; 0x0c], + #[doc = "0xb0 - Subscribe configuration for task PREPARERX"] + pub subscribe_preparerx: SUBSCRIBE_PREPARERX, + #[doc = "0xb4 - Subscribe configuration for task PREPARETX"] + pub subscribe_preparetx: SUBSCRIBE_PREPARETX, + _reserved10: [u8; 0x4c], + #[doc = "0x104 - TWI stopped"] + pub events_stopped: EVENTS_STOPPED, + _reserved11: [u8; 0x1c], + #[doc = "0x124 - TWI error"] + pub events_error: EVENTS_ERROR, + _reserved12: [u8; 0x24], + #[doc = "0x14c - Receive sequence started"] + pub events_rxstarted: EVENTS_RXSTARTED, + #[doc = "0x150 - Transmit sequence started"] + pub events_txstarted: EVENTS_TXSTARTED, + _reserved14: [u8; 0x10], + #[doc = "0x164 - Write command received"] + pub events_write: EVENTS_WRITE, + #[doc = "0x168 - Read command received"] + pub events_read: EVENTS_READ, + _reserved16: [u8; 0x18], + #[doc = "0x184 - Publish configuration for event STOPPED"] + pub publish_stopped: PUBLISH_STOPPED, + _reserved17: [u8; 0x1c], + #[doc = "0x1a4 - Publish configuration for event ERROR"] + pub publish_error: PUBLISH_ERROR, + _reserved18: [u8; 0x24], + #[doc = "0x1cc - Publish configuration for event RXSTARTED"] + pub publish_rxstarted: PUBLISH_RXSTARTED, + #[doc = "0x1d0 - Publish configuration for event TXSTARTED"] + pub publish_txstarted: PUBLISH_TXSTARTED, + _reserved20: [u8; 0x10], + #[doc = "0x1e4 - Publish configuration for event WRITE"] + pub publish_write: PUBLISH_WRITE, + #[doc = "0x1e8 - Publish configuration for event READ"] + pub publish_read: PUBLISH_READ, + _reserved22: [u8; 0x14], + #[doc = "0x200 - Shortcuts between local events and tasks"] + pub shorts: SHORTS, + _reserved23: [u8; 0xfc], + #[doc = "0x300 - Enable or disable interrupt"] + pub inten: INTEN, + #[doc = "0x304 - Enable interrupt"] + pub intenset: INTENSET, + #[doc = "0x308 - Disable interrupt"] + pub intenclr: INTENCLR, + _reserved26: [u8; 0x01c4], + #[doc = "0x4d0 - Error source"] + pub errorsrc: ERRORSRC, + #[doc = "0x4d4 - Status register indicating which address had a match"] + pub match_: MATCH, + _reserved28: [u8; 0x28], + #[doc = "0x500 - Enable TWIS"] + pub enable: ENABLE, + _reserved29: [u8; 0x04], + #[doc = "0x508..0x510 - Unspecified"] + pub psel: PSEL, + _reserved30: [u8; 0x24], + #[doc = "0x534..0x544 - RXD EasyDMA channel"] + pub rxd: RXD, + #[doc = "0x544..0x554 - TXD EasyDMA channel"] + pub txd: TXD, + _reserved32: [u8; 0x34], + #[doc = "0x588..0x590 - Description collection: TWI slave address n"] + pub address: [ADDRESS; 2], + _reserved33: [u8; 0x04], + #[doc = "0x594 - Configuration register for the address match mechanism"] + pub config: CONFIG, + _reserved34: [u8; 0x28], + #[doc = "0x5c0 - Over-read character. Character sent out in case of an over-read of the transmit buffer."] + pub orc: ORC, +} +#[doc = "TASKS_STOP (w) register accessor: an alias for `Reg`"] +pub type TASKS_STOP = crate::Reg; +#[doc = "Stop TWI transaction"] +pub mod tasks_stop; +#[doc = "TASKS_SUSPEND (w) register accessor: an alias for `Reg`"] +pub type TASKS_SUSPEND = crate::Reg; +#[doc = "Suspend TWI transaction"] +pub mod tasks_suspend; +#[doc = "TASKS_RESUME (w) register accessor: an alias for `Reg`"] +pub type TASKS_RESUME = crate::Reg; +#[doc = "Resume TWI transaction"] +pub mod tasks_resume; +#[doc = "TASKS_PREPARERX (w) register accessor: an alias for `Reg`"] +pub type TASKS_PREPARERX = crate::Reg; +#[doc = "Prepare the TWI slave to respond to a write command"] +pub mod tasks_preparerx; +#[doc = "TASKS_PREPARETX (w) register accessor: an alias for `Reg`"] +pub type TASKS_PREPARETX = crate::Reg; +#[doc = "Prepare the TWI slave to respond to a read command"] +pub mod tasks_preparetx; +#[doc = "SUBSCRIBE_STOP (rw) register accessor: an alias for `Reg`"] +pub type SUBSCRIBE_STOP = crate::Reg; +#[doc = "Subscribe configuration for task STOP"] +pub mod subscribe_stop; +#[doc = "SUBSCRIBE_SUSPEND (rw) register accessor: an alias for `Reg`"] +pub type SUBSCRIBE_SUSPEND = crate::Reg; +#[doc = "Subscribe configuration for task SUSPEND"] +pub mod subscribe_suspend; +#[doc = "SUBSCRIBE_RESUME (rw) register accessor: an alias for `Reg`"] +pub type SUBSCRIBE_RESUME = crate::Reg; +#[doc = "Subscribe configuration for task RESUME"] +pub mod subscribe_resume; +#[doc = "SUBSCRIBE_PREPARERX (rw) register accessor: an alias for `Reg`"] +pub type SUBSCRIBE_PREPARERX = crate::Reg; +#[doc = "Subscribe configuration for task PREPARERX"] +pub mod subscribe_preparerx; +#[doc = "SUBSCRIBE_PREPARETX (rw) register accessor: an alias for `Reg`"] +pub type SUBSCRIBE_PREPARETX = crate::Reg; +#[doc = "Subscribe configuration for task PREPARETX"] +pub mod subscribe_preparetx; +#[doc = "EVENTS_STOPPED (rw) register accessor: an alias for `Reg`"] +pub type EVENTS_STOPPED = crate::Reg; +#[doc = "TWI stopped"] +pub mod events_stopped; +#[doc = "EVENTS_ERROR (rw) register accessor: an alias for `Reg`"] +pub type EVENTS_ERROR = crate::Reg; +#[doc = "TWI error"] +pub mod events_error; +#[doc = "EVENTS_RXSTARTED (rw) register accessor: an alias for `Reg`"] +pub type EVENTS_RXSTARTED = crate::Reg; +#[doc = "Receive sequence started"] +pub mod events_rxstarted; +#[doc = "EVENTS_TXSTARTED (rw) register accessor: an alias for `Reg`"] +pub type EVENTS_TXSTARTED = crate::Reg; +#[doc = "Transmit sequence started"] +pub mod events_txstarted; +#[doc = "EVENTS_WRITE (rw) register accessor: an alias for `Reg`"] +pub type EVENTS_WRITE = crate::Reg; +#[doc = "Write command received"] +pub mod events_write; +#[doc = "EVENTS_READ (rw) register accessor: an alias for `Reg`"] +pub type EVENTS_READ = crate::Reg; +#[doc = "Read command received"] +pub mod events_read; +#[doc = "PUBLISH_STOPPED (rw) register accessor: an alias for `Reg`"] +pub type PUBLISH_STOPPED = crate::Reg; +#[doc = "Publish configuration for event STOPPED"] +pub mod publish_stopped; +#[doc = "PUBLISH_ERROR (rw) register accessor: an alias for `Reg`"] +pub type PUBLISH_ERROR = crate::Reg; +#[doc = "Publish configuration for event ERROR"] +pub mod publish_error; +#[doc = "PUBLISH_RXSTARTED (rw) register accessor: an alias for `Reg`"] +pub type PUBLISH_RXSTARTED = crate::Reg; +#[doc = "Publish configuration for event RXSTARTED"] +pub mod publish_rxstarted; +#[doc = "PUBLISH_TXSTARTED (rw) register accessor: an alias for `Reg`"] +pub type PUBLISH_TXSTARTED = crate::Reg; +#[doc = "Publish configuration for event TXSTARTED"] +pub mod publish_txstarted; +#[doc = "PUBLISH_WRITE (rw) register accessor: an alias for `Reg`"] +pub type PUBLISH_WRITE = crate::Reg; +#[doc = "Publish configuration for event WRITE"] +pub mod publish_write; +#[doc = "PUBLISH_READ (rw) register accessor: an alias for `Reg`"] +pub type PUBLISH_READ = crate::Reg; +#[doc = "Publish configuration for event READ"] +pub mod publish_read; +#[doc = "SHORTS (rw) register accessor: an alias for `Reg`"] +pub type SHORTS = crate::Reg; +#[doc = "Shortcuts between local events and tasks"] +pub mod shorts; +#[doc = "INTEN (rw) register accessor: an alias for `Reg`"] +pub type INTEN = crate::Reg; +#[doc = "Enable or disable interrupt"] +pub mod inten; +#[doc = "INTENSET (rw) register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "Enable interrupt"] +pub mod intenset; +#[doc = "INTENCLR (rw) register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "Disable interrupt"] +pub mod intenclr; +#[doc = "ERRORSRC (rw) register accessor: an alias for `Reg`"] +pub type ERRORSRC = crate::Reg; +#[doc = "Error source"] +pub mod errorsrc; +#[doc = "MATCH (r) register accessor: an alias for `Reg`"] +pub type MATCH = crate::Reg; +#[doc = "Status register indicating which address had a match"] +pub mod match_; +#[doc = "ENABLE (rw) register accessor: an alias for `Reg`"] +pub type ENABLE = crate::Reg; +#[doc = "Enable TWIS"] +pub mod enable; +#[doc = "Unspecified"] +pub use psel::PSEL; +#[doc = r"Cluster"] +#[doc = "Unspecified"] +pub mod psel; +#[doc = "RXD EasyDMA channel"] +pub use rxd::RXD; +#[doc = r"Cluster"] +#[doc = "RXD EasyDMA channel"] +pub mod rxd; +#[doc = "TXD EasyDMA channel"] +pub use txd::TXD; +#[doc = r"Cluster"] +#[doc = "TXD EasyDMA channel"] +pub mod txd; +#[doc = "ADDRESS (rw) register accessor: an alias for `Reg`"] +pub type ADDRESS = crate::Reg; +#[doc = "Description collection: TWI slave address n"] +pub mod address; +#[doc = "CONFIG (rw) register accessor: an alias for `Reg`"] +pub type CONFIG = crate::Reg; +#[doc = "Configuration register for the address match mechanism"] +pub mod config; +#[doc = "ORC (rw) register accessor: an alias for `Reg`"] +pub type ORC = crate::Reg; +#[doc = "Over-read character. Character sent out in case of an over-read of the transmit buffer."] +pub mod orc; diff --git a/pacs/nrf9120-pac/src/twis0_ns/address.rs b/pacs/nrf9120-pac/src/twis0_ns/address.rs new file mode 100644 index 00000000..92c689ed --- /dev/null +++ b/pacs/nrf9120-pac/src/twis0_ns/address.rs @@ -0,0 +1,81 @@ +#[doc = "Register `ADDRESS[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `ADDRESS[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ADDRESS` reader - TWI slave address"] +pub type ADDRESS_R = crate::FieldReader; +#[doc = "Field `ADDRESS` writer - TWI slave address"] +pub type ADDRESS_W<'a, const O: u8> = crate::FieldWriter<'a, u32, ADDRESS_SPEC, u8, u8, 7, O>; +impl R { + #[doc = "Bits 0:6 - TWI slave address"] + #[inline(always)] + pub fn address(&self) -> ADDRESS_R { + ADDRESS_R::new((self.bits & 0x7f) as u8) + } +} +impl W { + #[doc = "Bits 0:6 - TWI slave address"] + #[inline(always)] + pub fn address(&mut self) -> ADDRESS_W<0> { + ADDRESS_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Description collection: TWI slave address n\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [address](index.html) module"] +pub struct ADDRESS_SPEC; +impl crate::RegisterSpec for ADDRESS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [address::R](R) reader structure"] +impl crate::Readable for ADDRESS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [address::W](W) writer structure"] +impl crate::Writable for ADDRESS_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets ADDRESS[%s] +to value 0"] +impl crate::Resettable for ADDRESS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/twis0_ns/config.rs b/pacs/nrf9120-pac/src/twis0_ns/config.rs new file mode 100644 index 00000000..92179d1d --- /dev/null +++ b/pacs/nrf9120-pac/src/twis0_ns/config.rs @@ -0,0 +1,186 @@ +#[doc = "Register `CONFIG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CONFIG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ADDRESS0` reader - Enable or disable address matching on ADDRESS\\[0\\]"] +pub type ADDRESS0_R = crate::BitReader; +#[doc = "Enable or disable address matching on ADDRESS\\[0\\]\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum ADDRESS0_A { + #[doc = "0: Disabled"] + DISABLED = 0, + #[doc = "1: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: ADDRESS0_A) -> Self { + variant as u8 != 0 + } +} +impl ADDRESS0_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> ADDRESS0_A { + match self.bits { + false => ADDRESS0_A::DISABLED, + true => ADDRESS0_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == ADDRESS0_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == ADDRESS0_A::ENABLED + } +} +#[doc = "Field `ADDRESS0` writer - Enable or disable address matching on ADDRESS\\[0\\]"] +pub type ADDRESS0_W<'a, const O: u8> = crate::BitWriter<'a, u32, CONFIG_SPEC, ADDRESS0_A, O>; +impl<'a, const O: u8> ADDRESS0_W<'a, O> { + #[doc = "Disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(ADDRESS0_A::DISABLED) + } + #[doc = "Enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(ADDRESS0_A::ENABLED) + } +} +#[doc = "Field `ADDRESS1` reader - Enable or disable address matching on ADDRESS\\[1\\]"] +pub type ADDRESS1_R = crate::BitReader; +#[doc = "Enable or disable address matching on ADDRESS\\[1\\]\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum ADDRESS1_A { + #[doc = "0: Disabled"] + DISABLED = 0, + #[doc = "1: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: ADDRESS1_A) -> Self { + variant as u8 != 0 + } +} +impl ADDRESS1_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> ADDRESS1_A { + match self.bits { + false => ADDRESS1_A::DISABLED, + true => ADDRESS1_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == ADDRESS1_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == ADDRESS1_A::ENABLED + } +} +#[doc = "Field `ADDRESS1` writer - Enable or disable address matching on ADDRESS\\[1\\]"] +pub type ADDRESS1_W<'a, const O: u8> = crate::BitWriter<'a, u32, CONFIG_SPEC, ADDRESS1_A, O>; +impl<'a, const O: u8> ADDRESS1_W<'a, O> { + #[doc = "Disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(ADDRESS1_A::DISABLED) + } + #[doc = "Enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(ADDRESS1_A::ENABLED) + } +} +impl R { + #[doc = "Bit 0 - Enable or disable address matching on ADDRESS\\[0\\]"] + #[inline(always)] + pub fn address0(&self) -> ADDRESS0_R { + ADDRESS0_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Enable or disable address matching on ADDRESS\\[1\\]"] + #[inline(always)] + pub fn address1(&self) -> ADDRESS1_R { + ADDRESS1_R::new(((self.bits >> 1) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Enable or disable address matching on ADDRESS\\[0\\]"] + #[inline(always)] + pub fn address0(&mut self) -> ADDRESS0_W<0> { + ADDRESS0_W::new(self) + } + #[doc = "Bit 1 - Enable or disable address matching on ADDRESS\\[1\\]"] + #[inline(always)] + pub fn address1(&mut self) -> ADDRESS1_W<1> { + ADDRESS1_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Configuration register for the address match mechanism\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [config](index.html) module"] +pub struct CONFIG_SPEC; +impl crate::RegisterSpec for CONFIG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [config::R](R) reader structure"] +impl crate::Readable for CONFIG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [config::W](W) writer structure"] +impl crate::Writable for CONFIG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CONFIG to value 0x01"] +impl crate::Resettable for CONFIG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x01 + } +} diff --git a/pacs/nrf9120-pac/src/twis0_ns/enable.rs b/pacs/nrf9120-pac/src/twis0_ns/enable.rs new file mode 100644 index 00000000..51969d89 --- /dev/null +++ b/pacs/nrf9120-pac/src/twis0_ns/enable.rs @@ -0,0 +1,128 @@ +#[doc = "Register `ENABLE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `ENABLE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ENABLE` reader - Enable or disable TWIS"] +pub type ENABLE_R = crate::FieldReader; +#[doc = "Enable or disable TWIS\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum ENABLE_A { + #[doc = "0: Disable TWIS"] + DISABLED = 0, + #[doc = "9: Enable TWIS"] + ENABLED = 9, +} +impl From for u8 { + #[inline(always)] + fn from(variant: ENABLE_A) -> Self { + variant as _ + } +} +impl ENABLE_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(ENABLE_A::DISABLED), + 9 => Some(ENABLE_A::ENABLED), + _ => None, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == ENABLE_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == ENABLE_A::ENABLED + } +} +#[doc = "Field `ENABLE` writer - Enable or disable TWIS"] +pub type ENABLE_W<'a, const O: u8> = crate::FieldWriter<'a, u32, ENABLE_SPEC, u8, ENABLE_A, 4, O>; +impl<'a, const O: u8> ENABLE_W<'a, O> { + #[doc = "Disable TWIS"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(ENABLE_A::DISABLED) + } + #[doc = "Enable TWIS"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(ENABLE_A::ENABLED) + } +} +impl R { + #[doc = "Bits 0:3 - Enable or disable TWIS"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new((self.bits & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - Enable or disable TWIS"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W<0> { + ENABLE_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Enable TWIS\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [enable](index.html) module"] +pub struct ENABLE_SPEC; +impl crate::RegisterSpec for ENABLE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [enable::R](R) reader structure"] +impl crate::Readable for ENABLE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [enable::W](W) writer structure"] +impl crate::Writable for ENABLE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets ENABLE to value 0"] +impl crate::Resettable for ENABLE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/twis0_ns/errorsrc.rs b/pacs/nrf9120-pac/src/twis0_ns/errorsrc.rs new file mode 100644 index 00000000..4e622082 --- /dev/null +++ b/pacs/nrf9120-pac/src/twis0_ns/errorsrc.rs @@ -0,0 +1,246 @@ +#[doc = "Register `ERRORSRC` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `ERRORSRC` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `OVERFLOW` reader - RX buffer overflow detected, and prevented"] +pub type OVERFLOW_R = crate::BitReader; +#[doc = "RX buffer overflow detected, and prevented\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum OVERFLOW_A { + #[doc = "0: Error did not occur"] + NOT_DETECTED = 0, + #[doc = "1: Error occurred"] + DETECTED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: OVERFLOW_A) -> Self { + variant as u8 != 0 + } +} +impl OVERFLOW_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> OVERFLOW_A { + match self.bits { + false => OVERFLOW_A::NOT_DETECTED, + true => OVERFLOW_A::DETECTED, + } + } + #[doc = "Checks if the value of the field is `NOT_DETECTED`"] + #[inline(always)] + pub fn is_not_detected(&self) -> bool { + *self == OVERFLOW_A::NOT_DETECTED + } + #[doc = "Checks if the value of the field is `DETECTED`"] + #[inline(always)] + pub fn is_detected(&self) -> bool { + *self == OVERFLOW_A::DETECTED + } +} +#[doc = "Field `OVERFLOW` writer - RX buffer overflow detected, and prevented"] +pub type OVERFLOW_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, ERRORSRC_SPEC, OVERFLOW_A, O>; +impl<'a, const O: u8> OVERFLOW_W<'a, O> { + #[doc = "Error did not occur"] + #[inline(always)] + pub fn not_detected(self) -> &'a mut W { + self.variant(OVERFLOW_A::NOT_DETECTED) + } + #[doc = "Error occurred"] + #[inline(always)] + pub fn detected(self) -> &'a mut W { + self.variant(OVERFLOW_A::DETECTED) + } +} +#[doc = "Field `DNACK` reader - NACK sent after receiving a data byte"] +pub type DNACK_R = crate::BitReader; +#[doc = "NACK sent after receiving a data byte\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum DNACK_A { + #[doc = "0: Error did not occur"] + NOT_RECEIVED = 0, + #[doc = "1: Error occurred"] + RECEIVED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: DNACK_A) -> Self { + variant as u8 != 0 + } +} +impl DNACK_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> DNACK_A { + match self.bits { + false => DNACK_A::NOT_RECEIVED, + true => DNACK_A::RECEIVED, + } + } + #[doc = "Checks if the value of the field is `NOT_RECEIVED`"] + #[inline(always)] + pub fn is_not_received(&self) -> bool { + *self == DNACK_A::NOT_RECEIVED + } + #[doc = "Checks if the value of the field is `RECEIVED`"] + #[inline(always)] + pub fn is_received(&self) -> bool { + *self == DNACK_A::RECEIVED + } +} +#[doc = "Field `DNACK` writer - NACK sent after receiving a data byte"] +pub type DNACK_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, ERRORSRC_SPEC, DNACK_A, O>; +impl<'a, const O: u8> DNACK_W<'a, O> { + #[doc = "Error did not occur"] + #[inline(always)] + pub fn not_received(self) -> &'a mut W { + self.variant(DNACK_A::NOT_RECEIVED) + } + #[doc = "Error occurred"] + #[inline(always)] + pub fn received(self) -> &'a mut W { + self.variant(DNACK_A::RECEIVED) + } +} +#[doc = "Field `OVERREAD` reader - TX buffer over-read detected, and prevented"] +pub type OVERREAD_R = crate::BitReader; +#[doc = "TX buffer over-read detected, and prevented\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum OVERREAD_A { + #[doc = "0: Error did not occur"] + NOT_DETECTED = 0, + #[doc = "1: Error occurred"] + DETECTED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: OVERREAD_A) -> Self { + variant as u8 != 0 + } +} +impl OVERREAD_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> OVERREAD_A { + match self.bits { + false => OVERREAD_A::NOT_DETECTED, + true => OVERREAD_A::DETECTED, + } + } + #[doc = "Checks if the value of the field is `NOT_DETECTED`"] + #[inline(always)] + pub fn is_not_detected(&self) -> bool { + *self == OVERREAD_A::NOT_DETECTED + } + #[doc = "Checks if the value of the field is `DETECTED`"] + #[inline(always)] + pub fn is_detected(&self) -> bool { + *self == OVERREAD_A::DETECTED + } +} +#[doc = "Field `OVERREAD` writer - TX buffer over-read detected, and prevented"] +pub type OVERREAD_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, ERRORSRC_SPEC, OVERREAD_A, O>; +impl<'a, const O: u8> OVERREAD_W<'a, O> { + #[doc = "Error did not occur"] + #[inline(always)] + pub fn not_detected(self) -> &'a mut W { + self.variant(OVERREAD_A::NOT_DETECTED) + } + #[doc = "Error occurred"] + #[inline(always)] + pub fn detected(self) -> &'a mut W { + self.variant(OVERREAD_A::DETECTED) + } +} +impl R { + #[doc = "Bit 0 - RX buffer overflow detected, and prevented"] + #[inline(always)] + pub fn overflow(&self) -> OVERFLOW_R { + OVERFLOW_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 2 - NACK sent after receiving a data byte"] + #[inline(always)] + pub fn dnack(&self) -> DNACK_R { + DNACK_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - TX buffer over-read detected, and prevented"] + #[inline(always)] + pub fn overread(&self) -> OVERREAD_R { + OVERREAD_R::new(((self.bits >> 3) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - RX buffer overflow detected, and prevented"] + #[inline(always)] + pub fn overflow(&mut self) -> OVERFLOW_W<0> { + OVERFLOW_W::new(self) + } + #[doc = "Bit 2 - NACK sent after receiving a data byte"] + #[inline(always)] + pub fn dnack(&mut self) -> DNACK_W<2> { + DNACK_W::new(self) + } + #[doc = "Bit 3 - TX buffer over-read detected, and prevented"] + #[inline(always)] + pub fn overread(&mut self) -> OVERREAD_W<3> { + OVERREAD_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Error source\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [errorsrc](index.html) module"] +pub struct ERRORSRC_SPEC; +impl crate::RegisterSpec for ERRORSRC_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [errorsrc::R](R) reader structure"] +impl crate::Readable for ERRORSRC_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [errorsrc::W](W) writer structure"] +impl crate::Writable for ERRORSRC_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets ERRORSRC to value 0"] +impl crate::Resettable for ERRORSRC_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/twis0_ns/events_error.rs b/pacs/nrf9120-pac/src/twis0_ns/events_error.rs new file mode 100644 index 00000000..975b6d4b --- /dev/null +++ b/pacs/nrf9120-pac/src/twis0_ns/events_error.rs @@ -0,0 +1,127 @@ +#[doc = "Register `EVENTS_ERROR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVENTS_ERROR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `EVENTS_ERROR` reader - TWI error"] +pub type EVENTS_ERROR_R = crate::BitReader; +#[doc = "TWI error\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum EVENTS_ERROR_A { + #[doc = "0: Event not generated"] + NOT_GENERATED = 0, + #[doc = "1: Event generated"] + GENERATED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: EVENTS_ERROR_A) -> Self { + variant as u8 != 0 + } +} +impl EVENTS_ERROR_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EVENTS_ERROR_A { + match self.bits { + false => EVENTS_ERROR_A::NOT_GENERATED, + true => EVENTS_ERROR_A::GENERATED, + } + } + #[doc = "Checks if the value of the field is `NOT_GENERATED`"] + #[inline(always)] + pub fn is_not_generated(&self) -> bool { + *self == EVENTS_ERROR_A::NOT_GENERATED + } + #[doc = "Checks if the value of the field is `GENERATED`"] + #[inline(always)] + pub fn is_generated(&self) -> bool { + *self == EVENTS_ERROR_A::GENERATED + } +} +#[doc = "Field `EVENTS_ERROR` writer - TWI error"] +pub type EVENTS_ERROR_W<'a, const O: u8> = + crate::BitWriter<'a, u32, EVENTS_ERROR_SPEC, EVENTS_ERROR_A, O>; +impl<'a, const O: u8> EVENTS_ERROR_W<'a, O> { + #[doc = "Event not generated"] + #[inline(always)] + pub fn not_generated(self) -> &'a mut W { + self.variant(EVENTS_ERROR_A::NOT_GENERATED) + } + #[doc = "Event generated"] + #[inline(always)] + pub fn generated(self) -> &'a mut W { + self.variant(EVENTS_ERROR_A::GENERATED) + } +} +impl R { + #[doc = "Bit 0 - TWI error"] + #[inline(always)] + pub fn events_error(&self) -> EVENTS_ERROR_R { + EVENTS_ERROR_R::new((self.bits & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - TWI error"] + #[inline(always)] + pub fn events_error(&mut self) -> EVENTS_ERROR_W<0> { + EVENTS_ERROR_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "TWI error\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [events_error](index.html) module"] +pub struct EVENTS_ERROR_SPEC; +impl crate::RegisterSpec for EVENTS_ERROR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [events_error::R](R) reader structure"] +impl crate::Readable for EVENTS_ERROR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [events_error::W](W) writer structure"] +impl crate::Writable for EVENTS_ERROR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EVENTS_ERROR to value 0"] +impl crate::Resettable for EVENTS_ERROR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/twis0_ns/events_read.rs b/pacs/nrf9120-pac/src/twis0_ns/events_read.rs new file mode 100644 index 00000000..c6c78f1c --- /dev/null +++ b/pacs/nrf9120-pac/src/twis0_ns/events_read.rs @@ -0,0 +1,127 @@ +#[doc = "Register `EVENTS_READ` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVENTS_READ` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `EVENTS_READ` reader - Read command received"] +pub type EVENTS_READ_R = crate::BitReader; +#[doc = "Read command received\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum EVENTS_READ_A { + #[doc = "0: Event not generated"] + NOT_GENERATED = 0, + #[doc = "1: Event generated"] + GENERATED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: EVENTS_READ_A) -> Self { + variant as u8 != 0 + } +} +impl EVENTS_READ_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EVENTS_READ_A { + match self.bits { + false => EVENTS_READ_A::NOT_GENERATED, + true => EVENTS_READ_A::GENERATED, + } + } + #[doc = "Checks if the value of the field is `NOT_GENERATED`"] + #[inline(always)] + pub fn is_not_generated(&self) -> bool { + *self == EVENTS_READ_A::NOT_GENERATED + } + #[doc = "Checks if the value of the field is `GENERATED`"] + #[inline(always)] + pub fn is_generated(&self) -> bool { + *self == EVENTS_READ_A::GENERATED + } +} +#[doc = "Field `EVENTS_READ` writer - Read command received"] +pub type EVENTS_READ_W<'a, const O: u8> = + crate::BitWriter<'a, u32, EVENTS_READ_SPEC, EVENTS_READ_A, O>; +impl<'a, const O: u8> EVENTS_READ_W<'a, O> { + #[doc = "Event not generated"] + #[inline(always)] + pub fn not_generated(self) -> &'a mut W { + self.variant(EVENTS_READ_A::NOT_GENERATED) + } + #[doc = "Event generated"] + #[inline(always)] + pub fn generated(self) -> &'a mut W { + self.variant(EVENTS_READ_A::GENERATED) + } +} +impl R { + #[doc = "Bit 0 - Read command received"] + #[inline(always)] + pub fn events_read(&self) -> EVENTS_READ_R { + EVENTS_READ_R::new((self.bits & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Read command received"] + #[inline(always)] + pub fn events_read(&mut self) -> EVENTS_READ_W<0> { + EVENTS_READ_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Read command received\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [events_read](index.html) module"] +pub struct EVENTS_READ_SPEC; +impl crate::RegisterSpec for EVENTS_READ_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [events_read::R](R) reader structure"] +impl crate::Readable for EVENTS_READ_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [events_read::W](W) writer structure"] +impl crate::Writable for EVENTS_READ_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EVENTS_READ to value 0"] +impl crate::Resettable for EVENTS_READ_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/twis0_ns/events_rxstarted.rs b/pacs/nrf9120-pac/src/twis0_ns/events_rxstarted.rs new file mode 100644 index 00000000..a4d0bb22 --- /dev/null +++ b/pacs/nrf9120-pac/src/twis0_ns/events_rxstarted.rs @@ -0,0 +1,127 @@ +#[doc = "Register `EVENTS_RXSTARTED` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVENTS_RXSTARTED` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `EVENTS_RXSTARTED` reader - Receive sequence started"] +pub type EVENTS_RXSTARTED_R = crate::BitReader; +#[doc = "Receive sequence started\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum EVENTS_RXSTARTED_A { + #[doc = "0: Event not generated"] + NOT_GENERATED = 0, + #[doc = "1: Event generated"] + GENERATED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: EVENTS_RXSTARTED_A) -> Self { + variant as u8 != 0 + } +} +impl EVENTS_RXSTARTED_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EVENTS_RXSTARTED_A { + match self.bits { + false => EVENTS_RXSTARTED_A::NOT_GENERATED, + true => EVENTS_RXSTARTED_A::GENERATED, + } + } + #[doc = "Checks if the value of the field is `NOT_GENERATED`"] + #[inline(always)] + pub fn is_not_generated(&self) -> bool { + *self == EVENTS_RXSTARTED_A::NOT_GENERATED + } + #[doc = "Checks if the value of the field is `GENERATED`"] + #[inline(always)] + pub fn is_generated(&self) -> bool { + *self == EVENTS_RXSTARTED_A::GENERATED + } +} +#[doc = "Field `EVENTS_RXSTARTED` writer - Receive sequence started"] +pub type EVENTS_RXSTARTED_W<'a, const O: u8> = + crate::BitWriter<'a, u32, EVENTS_RXSTARTED_SPEC, EVENTS_RXSTARTED_A, O>; +impl<'a, const O: u8> EVENTS_RXSTARTED_W<'a, O> { + #[doc = "Event not generated"] + #[inline(always)] + pub fn not_generated(self) -> &'a mut W { + self.variant(EVENTS_RXSTARTED_A::NOT_GENERATED) + } + #[doc = "Event generated"] + #[inline(always)] + pub fn generated(self) -> &'a mut W { + self.variant(EVENTS_RXSTARTED_A::GENERATED) + } +} +impl R { + #[doc = "Bit 0 - Receive sequence started"] + #[inline(always)] + pub fn events_rxstarted(&self) -> EVENTS_RXSTARTED_R { + EVENTS_RXSTARTED_R::new((self.bits & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Receive sequence started"] + #[inline(always)] + pub fn events_rxstarted(&mut self) -> EVENTS_RXSTARTED_W<0> { + EVENTS_RXSTARTED_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Receive sequence started\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [events_rxstarted](index.html) module"] +pub struct EVENTS_RXSTARTED_SPEC; +impl crate::RegisterSpec for EVENTS_RXSTARTED_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [events_rxstarted::R](R) reader structure"] +impl crate::Readable for EVENTS_RXSTARTED_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [events_rxstarted::W](W) writer structure"] +impl crate::Writable for EVENTS_RXSTARTED_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EVENTS_RXSTARTED to value 0"] +impl crate::Resettable for EVENTS_RXSTARTED_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/twis0_ns/events_stopped.rs b/pacs/nrf9120-pac/src/twis0_ns/events_stopped.rs new file mode 100644 index 00000000..25da5392 --- /dev/null +++ b/pacs/nrf9120-pac/src/twis0_ns/events_stopped.rs @@ -0,0 +1,127 @@ +#[doc = "Register `EVENTS_STOPPED` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVENTS_STOPPED` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `EVENTS_STOPPED` reader - TWI stopped"] +pub type EVENTS_STOPPED_R = crate::BitReader; +#[doc = "TWI stopped\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum EVENTS_STOPPED_A { + #[doc = "0: Event not generated"] + NOT_GENERATED = 0, + #[doc = "1: Event generated"] + GENERATED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: EVENTS_STOPPED_A) -> Self { + variant as u8 != 0 + } +} +impl EVENTS_STOPPED_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EVENTS_STOPPED_A { + match self.bits { + false => EVENTS_STOPPED_A::NOT_GENERATED, + true => EVENTS_STOPPED_A::GENERATED, + } + } + #[doc = "Checks if the value of the field is `NOT_GENERATED`"] + #[inline(always)] + pub fn is_not_generated(&self) -> bool { + *self == EVENTS_STOPPED_A::NOT_GENERATED + } + #[doc = "Checks if the value of the field is `GENERATED`"] + #[inline(always)] + pub fn is_generated(&self) -> bool { + *self == EVENTS_STOPPED_A::GENERATED + } +} +#[doc = "Field `EVENTS_STOPPED` writer - TWI stopped"] +pub type EVENTS_STOPPED_W<'a, const O: u8> = + crate::BitWriter<'a, u32, EVENTS_STOPPED_SPEC, EVENTS_STOPPED_A, O>; +impl<'a, const O: u8> EVENTS_STOPPED_W<'a, O> { + #[doc = "Event not generated"] + #[inline(always)] + pub fn not_generated(self) -> &'a mut W { + self.variant(EVENTS_STOPPED_A::NOT_GENERATED) + } + #[doc = "Event generated"] + #[inline(always)] + pub fn generated(self) -> &'a mut W { + self.variant(EVENTS_STOPPED_A::GENERATED) + } +} +impl R { + #[doc = "Bit 0 - TWI stopped"] + #[inline(always)] + pub fn events_stopped(&self) -> EVENTS_STOPPED_R { + EVENTS_STOPPED_R::new((self.bits & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - TWI stopped"] + #[inline(always)] + pub fn events_stopped(&mut self) -> EVENTS_STOPPED_W<0> { + EVENTS_STOPPED_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "TWI stopped\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [events_stopped](index.html) module"] +pub struct EVENTS_STOPPED_SPEC; +impl crate::RegisterSpec for EVENTS_STOPPED_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [events_stopped::R](R) reader structure"] +impl crate::Readable for EVENTS_STOPPED_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [events_stopped::W](W) writer structure"] +impl crate::Writable for EVENTS_STOPPED_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EVENTS_STOPPED to value 0"] +impl crate::Resettable for EVENTS_STOPPED_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/twis0_ns/events_txstarted.rs b/pacs/nrf9120-pac/src/twis0_ns/events_txstarted.rs new file mode 100644 index 00000000..35be4204 --- /dev/null +++ b/pacs/nrf9120-pac/src/twis0_ns/events_txstarted.rs @@ -0,0 +1,127 @@ +#[doc = "Register `EVENTS_TXSTARTED` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVENTS_TXSTARTED` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `EVENTS_TXSTARTED` reader - Transmit sequence started"] +pub type EVENTS_TXSTARTED_R = crate::BitReader; +#[doc = "Transmit sequence started\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum EVENTS_TXSTARTED_A { + #[doc = "0: Event not generated"] + NOT_GENERATED = 0, + #[doc = "1: Event generated"] + GENERATED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: EVENTS_TXSTARTED_A) -> Self { + variant as u8 != 0 + } +} +impl EVENTS_TXSTARTED_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EVENTS_TXSTARTED_A { + match self.bits { + false => EVENTS_TXSTARTED_A::NOT_GENERATED, + true => EVENTS_TXSTARTED_A::GENERATED, + } + } + #[doc = "Checks if the value of the field is `NOT_GENERATED`"] + #[inline(always)] + pub fn is_not_generated(&self) -> bool { + *self == EVENTS_TXSTARTED_A::NOT_GENERATED + } + #[doc = "Checks if the value of the field is `GENERATED`"] + #[inline(always)] + pub fn is_generated(&self) -> bool { + *self == EVENTS_TXSTARTED_A::GENERATED + } +} +#[doc = "Field `EVENTS_TXSTARTED` writer - Transmit sequence started"] +pub type EVENTS_TXSTARTED_W<'a, const O: u8> = + crate::BitWriter<'a, u32, EVENTS_TXSTARTED_SPEC, EVENTS_TXSTARTED_A, O>; +impl<'a, const O: u8> EVENTS_TXSTARTED_W<'a, O> { + #[doc = "Event not generated"] + #[inline(always)] + pub fn not_generated(self) -> &'a mut W { + self.variant(EVENTS_TXSTARTED_A::NOT_GENERATED) + } + #[doc = "Event generated"] + #[inline(always)] + pub fn generated(self) -> &'a mut W { + self.variant(EVENTS_TXSTARTED_A::GENERATED) + } +} +impl R { + #[doc = "Bit 0 - Transmit sequence started"] + #[inline(always)] + pub fn events_txstarted(&self) -> EVENTS_TXSTARTED_R { + EVENTS_TXSTARTED_R::new((self.bits & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Transmit sequence started"] + #[inline(always)] + pub fn events_txstarted(&mut self) -> EVENTS_TXSTARTED_W<0> { + EVENTS_TXSTARTED_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Transmit sequence started\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [events_txstarted](index.html) module"] +pub struct EVENTS_TXSTARTED_SPEC; +impl crate::RegisterSpec for EVENTS_TXSTARTED_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [events_txstarted::R](R) reader structure"] +impl crate::Readable for EVENTS_TXSTARTED_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [events_txstarted::W](W) writer structure"] +impl crate::Writable for EVENTS_TXSTARTED_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EVENTS_TXSTARTED to value 0"] +impl crate::Resettable for EVENTS_TXSTARTED_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/twis0_ns/events_write.rs b/pacs/nrf9120-pac/src/twis0_ns/events_write.rs new file mode 100644 index 00000000..ec519d08 --- /dev/null +++ b/pacs/nrf9120-pac/src/twis0_ns/events_write.rs @@ -0,0 +1,127 @@ +#[doc = "Register `EVENTS_WRITE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVENTS_WRITE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `EVENTS_WRITE` reader - Write command received"] +pub type EVENTS_WRITE_R = crate::BitReader; +#[doc = "Write command received\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum EVENTS_WRITE_A { + #[doc = "0: Event not generated"] + NOT_GENERATED = 0, + #[doc = "1: Event generated"] + GENERATED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: EVENTS_WRITE_A) -> Self { + variant as u8 != 0 + } +} +impl EVENTS_WRITE_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EVENTS_WRITE_A { + match self.bits { + false => EVENTS_WRITE_A::NOT_GENERATED, + true => EVENTS_WRITE_A::GENERATED, + } + } + #[doc = "Checks if the value of the field is `NOT_GENERATED`"] + #[inline(always)] + pub fn is_not_generated(&self) -> bool { + *self == EVENTS_WRITE_A::NOT_GENERATED + } + #[doc = "Checks if the value of the field is `GENERATED`"] + #[inline(always)] + pub fn is_generated(&self) -> bool { + *self == EVENTS_WRITE_A::GENERATED + } +} +#[doc = "Field `EVENTS_WRITE` writer - Write command received"] +pub type EVENTS_WRITE_W<'a, const O: u8> = + crate::BitWriter<'a, u32, EVENTS_WRITE_SPEC, EVENTS_WRITE_A, O>; +impl<'a, const O: u8> EVENTS_WRITE_W<'a, O> { + #[doc = "Event not generated"] + #[inline(always)] + pub fn not_generated(self) -> &'a mut W { + self.variant(EVENTS_WRITE_A::NOT_GENERATED) + } + #[doc = "Event generated"] + #[inline(always)] + pub fn generated(self) -> &'a mut W { + self.variant(EVENTS_WRITE_A::GENERATED) + } +} +impl R { + #[doc = "Bit 0 - Write command received"] + #[inline(always)] + pub fn events_write(&self) -> EVENTS_WRITE_R { + EVENTS_WRITE_R::new((self.bits & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Write command received"] + #[inline(always)] + pub fn events_write(&mut self) -> EVENTS_WRITE_W<0> { + EVENTS_WRITE_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Write command received\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [events_write](index.html) module"] +pub struct EVENTS_WRITE_SPEC; +impl crate::RegisterSpec for EVENTS_WRITE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [events_write::R](R) reader structure"] +impl crate::Readable for EVENTS_WRITE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [events_write::W](W) writer structure"] +impl crate::Writable for EVENTS_WRITE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EVENTS_WRITE to value 0"] +impl crate::Resettable for EVENTS_WRITE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/twis0_ns/inten.rs b/pacs/nrf9120-pac/src/twis0_ns/inten.rs new file mode 100644 index 00000000..c1581c73 --- /dev/null +++ b/pacs/nrf9120-pac/src/twis0_ns/inten.rs @@ -0,0 +1,426 @@ +#[doc = "Register `INTEN` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTEN` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `STOPPED` reader - Enable or disable interrupt for event STOPPED"] +pub type STOPPED_R = crate::BitReader; +#[doc = "Enable or disable interrupt for event STOPPED\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum STOPPED_A { + #[doc = "0: Disable"] + DISABLED = 0, + #[doc = "1: Enable"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: STOPPED_A) -> Self { + variant as u8 != 0 + } +} +impl STOPPED_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> STOPPED_A { + match self.bits { + false => STOPPED_A::DISABLED, + true => STOPPED_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == STOPPED_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == STOPPED_A::ENABLED + } +} +#[doc = "Field `STOPPED` writer - Enable or disable interrupt for event STOPPED"] +pub type STOPPED_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTEN_SPEC, STOPPED_A, O>; +impl<'a, const O: u8> STOPPED_W<'a, O> { + #[doc = "Disable"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(STOPPED_A::DISABLED) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(STOPPED_A::ENABLED) + } +} +#[doc = "Field `ERROR` reader - Enable or disable interrupt for event ERROR"] +pub type ERROR_R = crate::BitReader; +#[doc = "Enable or disable interrupt for event ERROR\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum ERROR_A { + #[doc = "0: Disable"] + DISABLED = 0, + #[doc = "1: Enable"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: ERROR_A) -> Self { + variant as u8 != 0 + } +} +impl ERROR_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> ERROR_A { + match self.bits { + false => ERROR_A::DISABLED, + true => ERROR_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == ERROR_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == ERROR_A::ENABLED + } +} +#[doc = "Field `ERROR` writer - Enable or disable interrupt for event ERROR"] +pub type ERROR_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTEN_SPEC, ERROR_A, O>; +impl<'a, const O: u8> ERROR_W<'a, O> { + #[doc = "Disable"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(ERROR_A::DISABLED) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(ERROR_A::ENABLED) + } +} +#[doc = "Field `RXSTARTED` reader - Enable or disable interrupt for event RXSTARTED"] +pub type RXSTARTED_R = crate::BitReader; +#[doc = "Enable or disable interrupt for event RXSTARTED\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RXSTARTED_A { + #[doc = "0: Disable"] + DISABLED = 0, + #[doc = "1: Enable"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RXSTARTED_A) -> Self { + variant as u8 != 0 + } +} +impl RXSTARTED_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RXSTARTED_A { + match self.bits { + false => RXSTARTED_A::DISABLED, + true => RXSTARTED_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == RXSTARTED_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == RXSTARTED_A::ENABLED + } +} +#[doc = "Field `RXSTARTED` writer - Enable or disable interrupt for event RXSTARTED"] +pub type RXSTARTED_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTEN_SPEC, RXSTARTED_A, O>; +impl<'a, const O: u8> RXSTARTED_W<'a, O> { + #[doc = "Disable"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(RXSTARTED_A::DISABLED) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(RXSTARTED_A::ENABLED) + } +} +#[doc = "Field `TXSTARTED` reader - Enable or disable interrupt for event TXSTARTED"] +pub type TXSTARTED_R = crate::BitReader; +#[doc = "Enable or disable interrupt for event TXSTARTED\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum TXSTARTED_A { + #[doc = "0: Disable"] + DISABLED = 0, + #[doc = "1: Enable"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TXSTARTED_A) -> Self { + variant as u8 != 0 + } +} +impl TXSTARTED_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> TXSTARTED_A { + match self.bits { + false => TXSTARTED_A::DISABLED, + true => TXSTARTED_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == TXSTARTED_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == TXSTARTED_A::ENABLED + } +} +#[doc = "Field `TXSTARTED` writer - Enable or disable interrupt for event TXSTARTED"] +pub type TXSTARTED_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTEN_SPEC, TXSTARTED_A, O>; +impl<'a, const O: u8> TXSTARTED_W<'a, O> { + #[doc = "Disable"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(TXSTARTED_A::DISABLED) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(TXSTARTED_A::ENABLED) + } +} +#[doc = "Field `WRITE` reader - Enable or disable interrupt for event WRITE"] +pub type WRITE_R = crate::BitReader; +#[doc = "Enable or disable interrupt for event WRITE\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum WRITE_A { + #[doc = "0: Disable"] + DISABLED = 0, + #[doc = "1: Enable"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: WRITE_A) -> Self { + variant as u8 != 0 + } +} +impl WRITE_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> WRITE_A { + match self.bits { + false => WRITE_A::DISABLED, + true => WRITE_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == WRITE_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == WRITE_A::ENABLED + } +} +#[doc = "Field `WRITE` writer - Enable or disable interrupt for event WRITE"] +pub type WRITE_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTEN_SPEC, WRITE_A, O>; +impl<'a, const O: u8> WRITE_W<'a, O> { + #[doc = "Disable"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(WRITE_A::DISABLED) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(WRITE_A::ENABLED) + } +} +#[doc = "Field `READ` reader - Enable or disable interrupt for event READ"] +pub type READ_R = crate::BitReader; +#[doc = "Enable or disable interrupt for event READ\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum READ_A { + #[doc = "0: Disable"] + DISABLED = 0, + #[doc = "1: Enable"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: READ_A) -> Self { + variant as u8 != 0 + } +} +impl READ_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> READ_A { + match self.bits { + false => READ_A::DISABLED, + true => READ_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == READ_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == READ_A::ENABLED + } +} +#[doc = "Field `READ` writer - Enable or disable interrupt for event READ"] +pub type READ_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTEN_SPEC, READ_A, O>; +impl<'a, const O: u8> READ_W<'a, O> { + #[doc = "Disable"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(READ_A::DISABLED) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(READ_A::ENABLED) + } +} +impl R { + #[doc = "Bit 1 - Enable or disable interrupt for event STOPPED"] + #[inline(always)] + pub fn stopped(&self) -> STOPPED_R { + STOPPED_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 9 - Enable or disable interrupt for event ERROR"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 19 - Enable or disable interrupt for event RXSTARTED"] + #[inline(always)] + pub fn rxstarted(&self) -> RXSTARTED_R { + RXSTARTED_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Enable or disable interrupt for event TXSTARTED"] + #[inline(always)] + pub fn txstarted(&self) -> TXSTARTED_R { + TXSTARTED_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 25 - Enable or disable interrupt for event WRITE"] + #[inline(always)] + pub fn write(&self) -> WRITE_R { + WRITE_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - Enable or disable interrupt for event READ"] + #[inline(always)] + pub fn read(&self) -> READ_R { + READ_R::new(((self.bits >> 26) & 1) != 0) + } +} +impl W { + #[doc = "Bit 1 - Enable or disable interrupt for event STOPPED"] + #[inline(always)] + pub fn stopped(&mut self) -> STOPPED_W<1> { + STOPPED_W::new(self) + } + #[doc = "Bit 9 - Enable or disable interrupt for event ERROR"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W<9> { + ERROR_W::new(self) + } + #[doc = "Bit 19 - Enable or disable interrupt for event RXSTARTED"] + #[inline(always)] + pub fn rxstarted(&mut self) -> RXSTARTED_W<19> { + RXSTARTED_W::new(self) + } + #[doc = "Bit 20 - Enable or disable interrupt for event TXSTARTED"] + #[inline(always)] + pub fn txstarted(&mut self) -> TXSTARTED_W<20> { + TXSTARTED_W::new(self) + } + #[doc = "Bit 25 - Enable or disable interrupt for event WRITE"] + #[inline(always)] + pub fn write(&mut self) -> WRITE_W<25> { + WRITE_W::new(self) + } + #[doc = "Bit 26 - Enable or disable interrupt for event READ"] + #[inline(always)] + pub fn read(&mut self) -> READ_W<26> { + READ_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Enable or disable interrupt\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [inten](index.html) module"] +pub struct INTEN_SPEC; +impl crate::RegisterSpec for INTEN_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [inten::R](R) reader structure"] +impl crate::Readable for INTEN_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [inten::W](W) writer structure"] +impl crate::Writable for INTEN_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTEN to value 0"] +impl crate::Resettable for INTEN_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/twis0_ns/intenclr.rs b/pacs/nrf9120-pac/src/twis0_ns/intenclr.rs new file mode 100644 index 00000000..c2b49d6a --- /dev/null +++ b/pacs/nrf9120-pac/src/twis0_ns/intenclr.rs @@ -0,0 +1,468 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `STOPPED` reader - Write '1' to disable interrupt for event STOPPED"] +pub type STOPPED_R = crate::BitReader; +#[doc = "Write '1' to disable interrupt for event STOPPED\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum STOPPED_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: STOPPED_A) -> Self { + variant as u8 != 0 + } +} +impl STOPPED_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> STOPPED_A { + match self.bits { + false => STOPPED_A::DISABLED, + true => STOPPED_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == STOPPED_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == STOPPED_A::ENABLED + } +} +#[doc = "Write '1' to disable interrupt for event STOPPED\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum STOPPED_AW { + #[doc = "1: Disable"] + CLEAR = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: STOPPED_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `STOPPED` writer - Write '1' to disable interrupt for event STOPPED"] +pub type STOPPED_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENCLR_SPEC, STOPPED_AW, O>; +impl<'a, const O: u8> STOPPED_W<'a, O> { + #[doc = "Disable"] + #[inline(always)] + pub fn clear(self) -> &'a mut W { + self.variant(STOPPED_AW::CLEAR) + } +} +#[doc = "Field `ERROR` reader - Write '1' to disable interrupt for event ERROR"] +pub type ERROR_R = crate::BitReader; +#[doc = "Write '1' to disable interrupt for event ERROR\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum ERROR_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: ERROR_A) -> Self { + variant as u8 != 0 + } +} +impl ERROR_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> ERROR_A { + match self.bits { + false => ERROR_A::DISABLED, + true => ERROR_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == ERROR_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == ERROR_A::ENABLED + } +} +#[doc = "Write '1' to disable interrupt for event ERROR\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum ERROR_AW { + #[doc = "1: Disable"] + CLEAR = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: ERROR_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ERROR` writer - Write '1' to disable interrupt for event ERROR"] +pub type ERROR_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENCLR_SPEC, ERROR_AW, O>; +impl<'a, const O: u8> ERROR_W<'a, O> { + #[doc = "Disable"] + #[inline(always)] + pub fn clear(self) -> &'a mut W { + self.variant(ERROR_AW::CLEAR) + } +} +#[doc = "Field `RXSTARTED` reader - Write '1' to disable interrupt for event RXSTARTED"] +pub type RXSTARTED_R = crate::BitReader; +#[doc = "Write '1' to disable interrupt for event RXSTARTED\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RXSTARTED_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RXSTARTED_A) -> Self { + variant as u8 != 0 + } +} +impl RXSTARTED_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RXSTARTED_A { + match self.bits { + false => RXSTARTED_A::DISABLED, + true => RXSTARTED_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == RXSTARTED_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == RXSTARTED_A::ENABLED + } +} +#[doc = "Write '1' to disable interrupt for event RXSTARTED\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RXSTARTED_AW { + #[doc = "1: Disable"] + CLEAR = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RXSTARTED_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RXSTARTED` writer - Write '1' to disable interrupt for event RXSTARTED"] +pub type RXSTARTED_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENCLR_SPEC, RXSTARTED_AW, O>; +impl<'a, const O: u8> RXSTARTED_W<'a, O> { + #[doc = "Disable"] + #[inline(always)] + pub fn clear(self) -> &'a mut W { + self.variant(RXSTARTED_AW::CLEAR) + } +} +#[doc = "Field `TXSTARTED` reader - Write '1' to disable interrupt for event TXSTARTED"] +pub type TXSTARTED_R = crate::BitReader; +#[doc = "Write '1' to disable interrupt for event TXSTARTED\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum TXSTARTED_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TXSTARTED_A) -> Self { + variant as u8 != 0 + } +} +impl TXSTARTED_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> TXSTARTED_A { + match self.bits { + false => TXSTARTED_A::DISABLED, + true => TXSTARTED_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == TXSTARTED_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == TXSTARTED_A::ENABLED + } +} +#[doc = "Write '1' to disable interrupt for event TXSTARTED\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum TXSTARTED_AW { + #[doc = "1: Disable"] + CLEAR = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TXSTARTED_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TXSTARTED` writer - Write '1' to disable interrupt for event TXSTARTED"] +pub type TXSTARTED_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENCLR_SPEC, TXSTARTED_AW, O>; +impl<'a, const O: u8> TXSTARTED_W<'a, O> { + #[doc = "Disable"] + #[inline(always)] + pub fn clear(self) -> &'a mut W { + self.variant(TXSTARTED_AW::CLEAR) + } +} +#[doc = "Field `WRITE` reader - Write '1' to disable interrupt for event WRITE"] +pub type WRITE_R = crate::BitReader; +#[doc = "Write '1' to disable interrupt for event WRITE\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum WRITE_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: WRITE_A) -> Self { + variant as u8 != 0 + } +} +impl WRITE_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> WRITE_A { + match self.bits { + false => WRITE_A::DISABLED, + true => WRITE_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == WRITE_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == WRITE_A::ENABLED + } +} +#[doc = "Write '1' to disable interrupt for event WRITE\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum WRITE_AW { + #[doc = "1: Disable"] + CLEAR = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: WRITE_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `WRITE` writer - Write '1' to disable interrupt for event WRITE"] +pub type WRITE_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENCLR_SPEC, WRITE_AW, O>; +impl<'a, const O: u8> WRITE_W<'a, O> { + #[doc = "Disable"] + #[inline(always)] + pub fn clear(self) -> &'a mut W { + self.variant(WRITE_AW::CLEAR) + } +} +#[doc = "Field `READ` reader - Write '1' to disable interrupt for event READ"] +pub type READ_R = crate::BitReader; +#[doc = "Write '1' to disable interrupt for event READ\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum READ_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: READ_A) -> Self { + variant as u8 != 0 + } +} +impl READ_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> READ_A { + match self.bits { + false => READ_A::DISABLED, + true => READ_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == READ_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == READ_A::ENABLED + } +} +#[doc = "Write '1' to disable interrupt for event READ\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum READ_AW { + #[doc = "1: Disable"] + CLEAR = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: READ_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `READ` writer - Write '1' to disable interrupt for event READ"] +pub type READ_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENCLR_SPEC, READ_AW, O>; +impl<'a, const O: u8> READ_W<'a, O> { + #[doc = "Disable"] + #[inline(always)] + pub fn clear(self) -> &'a mut W { + self.variant(READ_AW::CLEAR) + } +} +impl R { + #[doc = "Bit 1 - Write '1' to disable interrupt for event STOPPED"] + #[inline(always)] + pub fn stopped(&self) -> STOPPED_R { + STOPPED_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 9 - Write '1' to disable interrupt for event ERROR"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 19 - Write '1' to disable interrupt for event RXSTARTED"] + #[inline(always)] + pub fn rxstarted(&self) -> RXSTARTED_R { + RXSTARTED_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Write '1' to disable interrupt for event TXSTARTED"] + #[inline(always)] + pub fn txstarted(&self) -> TXSTARTED_R { + TXSTARTED_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 25 - Write '1' to disable interrupt for event WRITE"] + #[inline(always)] + pub fn write(&self) -> WRITE_R { + WRITE_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - Write '1' to disable interrupt for event READ"] + #[inline(always)] + pub fn read(&self) -> READ_R { + READ_R::new(((self.bits >> 26) & 1) != 0) + } +} +impl W { + #[doc = "Bit 1 - Write '1' to disable interrupt for event STOPPED"] + #[inline(always)] + pub fn stopped(&mut self) -> STOPPED_W<1> { + STOPPED_W::new(self) + } + #[doc = "Bit 9 - Write '1' to disable interrupt for event ERROR"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W<9> { + ERROR_W::new(self) + } + #[doc = "Bit 19 - Write '1' to disable interrupt for event RXSTARTED"] + #[inline(always)] + pub fn rxstarted(&mut self) -> RXSTARTED_W<19> { + RXSTARTED_W::new(self) + } + #[doc = "Bit 20 - Write '1' to disable interrupt for event TXSTARTED"] + #[inline(always)] + pub fn txstarted(&mut self) -> TXSTARTED_W<20> { + TXSTARTED_W::new(self) + } + #[doc = "Bit 25 - Write '1' to disable interrupt for event WRITE"] + #[inline(always)] + pub fn write(&mut self) -> WRITE_W<25> { + WRITE_W::new(self) + } + #[doc = "Bit 26 - Write '1' to disable interrupt for event READ"] + #[inline(always)] + pub fn read(&mut self) -> READ_W<26> { + READ_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Disable interrupt\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/twis0_ns/intenset.rs b/pacs/nrf9120-pac/src/twis0_ns/intenset.rs new file mode 100644 index 00000000..e835f3ee --- /dev/null +++ b/pacs/nrf9120-pac/src/twis0_ns/intenset.rs @@ -0,0 +1,468 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `STOPPED` reader - Write '1' to enable interrupt for event STOPPED"] +pub type STOPPED_R = crate::BitReader; +#[doc = "Write '1' to enable interrupt for event STOPPED\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum STOPPED_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: STOPPED_A) -> Self { + variant as u8 != 0 + } +} +impl STOPPED_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> STOPPED_A { + match self.bits { + false => STOPPED_A::DISABLED, + true => STOPPED_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == STOPPED_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == STOPPED_A::ENABLED + } +} +#[doc = "Write '1' to enable interrupt for event STOPPED\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum STOPPED_AW { + #[doc = "1: Enable"] + SET = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: STOPPED_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `STOPPED` writer - Write '1' to enable interrupt for event STOPPED"] +pub type STOPPED_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENSET_SPEC, STOPPED_AW, O>; +impl<'a, const O: u8> STOPPED_W<'a, O> { + #[doc = "Enable"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(STOPPED_AW::SET) + } +} +#[doc = "Field `ERROR` reader - Write '1' to enable interrupt for event ERROR"] +pub type ERROR_R = crate::BitReader; +#[doc = "Write '1' to enable interrupt for event ERROR\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum ERROR_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: ERROR_A) -> Self { + variant as u8 != 0 + } +} +impl ERROR_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> ERROR_A { + match self.bits { + false => ERROR_A::DISABLED, + true => ERROR_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == ERROR_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == ERROR_A::ENABLED + } +} +#[doc = "Write '1' to enable interrupt for event ERROR\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum ERROR_AW { + #[doc = "1: Enable"] + SET = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: ERROR_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ERROR` writer - Write '1' to enable interrupt for event ERROR"] +pub type ERROR_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENSET_SPEC, ERROR_AW, O>; +impl<'a, const O: u8> ERROR_W<'a, O> { + #[doc = "Enable"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(ERROR_AW::SET) + } +} +#[doc = "Field `RXSTARTED` reader - Write '1' to enable interrupt for event RXSTARTED"] +pub type RXSTARTED_R = crate::BitReader; +#[doc = "Write '1' to enable interrupt for event RXSTARTED\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RXSTARTED_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RXSTARTED_A) -> Self { + variant as u8 != 0 + } +} +impl RXSTARTED_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RXSTARTED_A { + match self.bits { + false => RXSTARTED_A::DISABLED, + true => RXSTARTED_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == RXSTARTED_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == RXSTARTED_A::ENABLED + } +} +#[doc = "Write '1' to enable interrupt for event RXSTARTED\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RXSTARTED_AW { + #[doc = "1: Enable"] + SET = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RXSTARTED_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RXSTARTED` writer - Write '1' to enable interrupt for event RXSTARTED"] +pub type RXSTARTED_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENSET_SPEC, RXSTARTED_AW, O>; +impl<'a, const O: u8> RXSTARTED_W<'a, O> { + #[doc = "Enable"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(RXSTARTED_AW::SET) + } +} +#[doc = "Field `TXSTARTED` reader - Write '1' to enable interrupt for event TXSTARTED"] +pub type TXSTARTED_R = crate::BitReader; +#[doc = "Write '1' to enable interrupt for event TXSTARTED\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum TXSTARTED_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TXSTARTED_A) -> Self { + variant as u8 != 0 + } +} +impl TXSTARTED_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> TXSTARTED_A { + match self.bits { + false => TXSTARTED_A::DISABLED, + true => TXSTARTED_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == TXSTARTED_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == TXSTARTED_A::ENABLED + } +} +#[doc = "Write '1' to enable interrupt for event TXSTARTED\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum TXSTARTED_AW { + #[doc = "1: Enable"] + SET = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TXSTARTED_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TXSTARTED` writer - Write '1' to enable interrupt for event TXSTARTED"] +pub type TXSTARTED_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENSET_SPEC, TXSTARTED_AW, O>; +impl<'a, const O: u8> TXSTARTED_W<'a, O> { + #[doc = "Enable"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(TXSTARTED_AW::SET) + } +} +#[doc = "Field `WRITE` reader - Write '1' to enable interrupt for event WRITE"] +pub type WRITE_R = crate::BitReader; +#[doc = "Write '1' to enable interrupt for event WRITE\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum WRITE_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: WRITE_A) -> Self { + variant as u8 != 0 + } +} +impl WRITE_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> WRITE_A { + match self.bits { + false => WRITE_A::DISABLED, + true => WRITE_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == WRITE_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == WRITE_A::ENABLED + } +} +#[doc = "Write '1' to enable interrupt for event WRITE\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum WRITE_AW { + #[doc = "1: Enable"] + SET = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: WRITE_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `WRITE` writer - Write '1' to enable interrupt for event WRITE"] +pub type WRITE_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENSET_SPEC, WRITE_AW, O>; +impl<'a, const O: u8> WRITE_W<'a, O> { + #[doc = "Enable"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(WRITE_AW::SET) + } +} +#[doc = "Field `READ` reader - Write '1' to enable interrupt for event READ"] +pub type READ_R = crate::BitReader; +#[doc = "Write '1' to enable interrupt for event READ\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum READ_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: READ_A) -> Self { + variant as u8 != 0 + } +} +impl READ_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> READ_A { + match self.bits { + false => READ_A::DISABLED, + true => READ_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == READ_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == READ_A::ENABLED + } +} +#[doc = "Write '1' to enable interrupt for event READ\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum READ_AW { + #[doc = "1: Enable"] + SET = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: READ_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `READ` writer - Write '1' to enable interrupt for event READ"] +pub type READ_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENSET_SPEC, READ_AW, O>; +impl<'a, const O: u8> READ_W<'a, O> { + #[doc = "Enable"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(READ_AW::SET) + } +} +impl R { + #[doc = "Bit 1 - Write '1' to enable interrupt for event STOPPED"] + #[inline(always)] + pub fn stopped(&self) -> STOPPED_R { + STOPPED_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 9 - Write '1' to enable interrupt for event ERROR"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 19 - Write '1' to enable interrupt for event RXSTARTED"] + #[inline(always)] + pub fn rxstarted(&self) -> RXSTARTED_R { + RXSTARTED_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Write '1' to enable interrupt for event TXSTARTED"] + #[inline(always)] + pub fn txstarted(&self) -> TXSTARTED_R { + TXSTARTED_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 25 - Write '1' to enable interrupt for event WRITE"] + #[inline(always)] + pub fn write(&self) -> WRITE_R { + WRITE_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - Write '1' to enable interrupt for event READ"] + #[inline(always)] + pub fn read(&self) -> READ_R { + READ_R::new(((self.bits >> 26) & 1) != 0) + } +} +impl W { + #[doc = "Bit 1 - Write '1' to enable interrupt for event STOPPED"] + #[inline(always)] + pub fn stopped(&mut self) -> STOPPED_W<1> { + STOPPED_W::new(self) + } + #[doc = "Bit 9 - Write '1' to enable interrupt for event ERROR"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W<9> { + ERROR_W::new(self) + } + #[doc = "Bit 19 - Write '1' to enable interrupt for event RXSTARTED"] + #[inline(always)] + pub fn rxstarted(&mut self) -> RXSTARTED_W<19> { + RXSTARTED_W::new(self) + } + #[doc = "Bit 20 - Write '1' to enable interrupt for event TXSTARTED"] + #[inline(always)] + pub fn txstarted(&mut self) -> TXSTARTED_W<20> { + TXSTARTED_W::new(self) + } + #[doc = "Bit 25 - Write '1' to enable interrupt for event WRITE"] + #[inline(always)] + pub fn write(&mut self) -> WRITE_W<25> { + WRITE_W::new(self) + } + #[doc = "Bit 26 - Write '1' to enable interrupt for event READ"] + #[inline(always)] + pub fn read(&mut self) -> READ_W<26> { + READ_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Enable interrupt\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/twis0_ns/match_.rs b/pacs/nrf9120-pac/src/twis0_ns/match_.rs new file mode 100644 index 00000000..2f8d5503 --- /dev/null +++ b/pacs/nrf9120-pac/src/twis0_ns/match_.rs @@ -0,0 +1,40 @@ +#[doc = "Register `MATCH` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `MATCH` reader - Indication of which address in ADDRESS that matched the incoming address"] +pub type MATCH_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - Indication of which address in ADDRESS that matched the incoming address"] + #[inline(always)] + pub fn match_(&self) -> MATCH_R { + MATCH_R::new((self.bits & 1) != 0) + } +} +#[doc = "Status register indicating which address had a match\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [match_](index.html) module"] +pub struct MATCH_SPEC; +impl crate::RegisterSpec for MATCH_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [match_::R](R) reader structure"] +impl crate::Readable for MATCH_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets MATCH to value 0"] +impl crate::Resettable for MATCH_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/twis0_ns/orc.rs b/pacs/nrf9120-pac/src/twis0_ns/orc.rs new file mode 100644 index 00000000..1dafba42 --- /dev/null +++ b/pacs/nrf9120-pac/src/twis0_ns/orc.rs @@ -0,0 +1,80 @@ +#[doc = "Register `ORC` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `ORC` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ORC` reader - Over-read character. Character sent out in case of an over-read of the transmit buffer."] +pub type ORC_R = crate::FieldReader; +#[doc = "Field `ORC` writer - Over-read character. Character sent out in case of an over-read of the transmit buffer."] +pub type ORC_W<'a, const O: u8> = crate::FieldWriter<'a, u32, ORC_SPEC, u8, u8, 8, O>; +impl R { + #[doc = "Bits 0:7 - Over-read character. Character sent out in case of an over-read of the transmit buffer."] + #[inline(always)] + pub fn orc(&self) -> ORC_R { + ORC_R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Over-read character. Character sent out in case of an over-read of the transmit buffer."] + #[inline(always)] + pub fn orc(&mut self) -> ORC_W<0> { + ORC_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Over-read character. Character sent out in case of an over-read of the transmit buffer.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [orc](index.html) module"] +pub struct ORC_SPEC; +impl crate::RegisterSpec for ORC_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [orc::R](R) reader structure"] +impl crate::Readable for ORC_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [orc::W](W) writer structure"] +impl crate::Writable for ORC_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets ORC to value 0"] +impl crate::Resettable for ORC_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/twis0_ns/psel.rs b/pacs/nrf9120-pac/src/twis0_ns/psel.rs new file mode 100644 index 00000000..6d71cdf1 --- /dev/null +++ b/pacs/nrf9120-pac/src/twis0_ns/psel.rs @@ -0,0 +1,16 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct PSEL { + #[doc = "0x00 - Pin select for SCL signal"] + pub scl: SCL, + #[doc = "0x04 - Pin select for SDA signal"] + pub sda: SDA, +} +#[doc = "SCL (rw) register accessor: an alias for `Reg`"] +pub type SCL = crate::Reg; +#[doc = "Pin select for SCL signal"] +pub mod scl; +#[doc = "SDA (rw) register accessor: an alias for `Reg`"] +pub type SDA = crate::Reg; +#[doc = "Pin select for SDA signal"] +pub mod sda; diff --git a/pacs/nrf9120-pac/src/twis0_ns/psel/scl.rs b/pacs/nrf9120-pac/src/twis0_ns/psel/scl.rs new file mode 100644 index 00000000..75273ced --- /dev/null +++ b/pacs/nrf9120-pac/src/twis0_ns/psel/scl.rs @@ -0,0 +1,140 @@ +#[doc = "Register `SCL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SCL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PIN` reader - Pin number"] +pub type PIN_R = crate::FieldReader; +#[doc = "Field `PIN` writer - Pin number"] +pub type PIN_W<'a, const O: u8> = crate::FieldWriter<'a, u32, SCL_SPEC, u8, u8, 5, O>; +#[doc = "Field `CONNECT` reader - Connection"] +pub type CONNECT_R = crate::BitReader; +#[doc = "Connection\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CONNECT_A { + #[doc = "1: Disconnect"] + DISCONNECTED = 1, + #[doc = "0: Connect"] + CONNECTED = 0, +} +impl From for bool { + #[inline(always)] + fn from(variant: CONNECT_A) -> Self { + variant as u8 != 0 + } +} +impl CONNECT_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CONNECT_A { + match self.bits { + true => CONNECT_A::DISCONNECTED, + false => CONNECT_A::CONNECTED, + } + } + #[doc = "Checks if the value of the field is `DISCONNECTED`"] + #[inline(always)] + pub fn is_disconnected(&self) -> bool { + *self == CONNECT_A::DISCONNECTED + } + #[doc = "Checks if the value of the field is `CONNECTED`"] + #[inline(always)] + pub fn is_connected(&self) -> bool { + *self == CONNECT_A::CONNECTED + } +} +#[doc = "Field `CONNECT` writer - Connection"] +pub type CONNECT_W<'a, const O: u8> = crate::BitWriter<'a, u32, SCL_SPEC, CONNECT_A, O>; +impl<'a, const O: u8> CONNECT_W<'a, O> { + #[doc = "Disconnect"] + #[inline(always)] + pub fn disconnected(self) -> &'a mut W { + self.variant(CONNECT_A::DISCONNECTED) + } + #[doc = "Connect"] + #[inline(always)] + pub fn connected(self) -> &'a mut W { + self.variant(CONNECT_A::CONNECTED) + } +} +impl R { + #[doc = "Bits 0:4 - Pin number"] + #[inline(always)] + pub fn pin(&self) -> PIN_R { + PIN_R::new((self.bits & 0x1f) as u8) + } + #[doc = "Bit 31 - Connection"] + #[inline(always)] + pub fn connect(&self) -> CONNECT_R { + CONNECT_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:4 - Pin number"] + #[inline(always)] + pub fn pin(&mut self) -> PIN_W<0> { + PIN_W::new(self) + } + #[doc = "Bit 31 - Connection"] + #[inline(always)] + pub fn connect(&mut self) -> CONNECT_W<31> { + CONNECT_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Pin select for SCL signal\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [scl](index.html) module"] +pub struct SCL_SPEC; +impl crate::RegisterSpec for SCL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [scl::R](R) reader structure"] +impl crate::Readable for SCL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [scl::W](W) writer structure"] +impl crate::Writable for SCL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SCL to value 0xffff_ffff"] +impl crate::Resettable for SCL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0xffff_ffff + } +} diff --git a/pacs/nrf9120-pac/src/twis0_ns/psel/sda.rs b/pacs/nrf9120-pac/src/twis0_ns/psel/sda.rs new file mode 100644 index 00000000..4063508e --- /dev/null +++ b/pacs/nrf9120-pac/src/twis0_ns/psel/sda.rs @@ -0,0 +1,140 @@ +#[doc = "Register `SDA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SDA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PIN` reader - Pin number"] +pub type PIN_R = crate::FieldReader; +#[doc = "Field `PIN` writer - Pin number"] +pub type PIN_W<'a, const O: u8> = crate::FieldWriter<'a, u32, SDA_SPEC, u8, u8, 5, O>; +#[doc = "Field `CONNECT` reader - Connection"] +pub type CONNECT_R = crate::BitReader; +#[doc = "Connection\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CONNECT_A { + #[doc = "1: Disconnect"] + DISCONNECTED = 1, + #[doc = "0: Connect"] + CONNECTED = 0, +} +impl From for bool { + #[inline(always)] + fn from(variant: CONNECT_A) -> Self { + variant as u8 != 0 + } +} +impl CONNECT_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CONNECT_A { + match self.bits { + true => CONNECT_A::DISCONNECTED, + false => CONNECT_A::CONNECTED, + } + } + #[doc = "Checks if the value of the field is `DISCONNECTED`"] + #[inline(always)] + pub fn is_disconnected(&self) -> bool { + *self == CONNECT_A::DISCONNECTED + } + #[doc = "Checks if the value of the field is `CONNECTED`"] + #[inline(always)] + pub fn is_connected(&self) -> bool { + *self == CONNECT_A::CONNECTED + } +} +#[doc = "Field `CONNECT` writer - Connection"] +pub type CONNECT_W<'a, const O: u8> = crate::BitWriter<'a, u32, SDA_SPEC, CONNECT_A, O>; +impl<'a, const O: u8> CONNECT_W<'a, O> { + #[doc = "Disconnect"] + #[inline(always)] + pub fn disconnected(self) -> &'a mut W { + self.variant(CONNECT_A::DISCONNECTED) + } + #[doc = "Connect"] + #[inline(always)] + pub fn connected(self) -> &'a mut W { + self.variant(CONNECT_A::CONNECTED) + } +} +impl R { + #[doc = "Bits 0:4 - Pin number"] + #[inline(always)] + pub fn pin(&self) -> PIN_R { + PIN_R::new((self.bits & 0x1f) as u8) + } + #[doc = "Bit 31 - Connection"] + #[inline(always)] + pub fn connect(&self) -> CONNECT_R { + CONNECT_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:4 - Pin number"] + #[inline(always)] + pub fn pin(&mut self) -> PIN_W<0> { + PIN_W::new(self) + } + #[doc = "Bit 31 - Connection"] + #[inline(always)] + pub fn connect(&mut self) -> CONNECT_W<31> { + CONNECT_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Pin select for SDA signal\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sda](index.html) module"] +pub struct SDA_SPEC; +impl crate::RegisterSpec for SDA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [sda::R](R) reader structure"] +impl crate::Readable for SDA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [sda::W](W) writer structure"] +impl crate::Writable for SDA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SDA to value 0xffff_ffff"] +impl crate::Resettable for SDA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0xffff_ffff + } +} diff --git a/pacs/nrf9120-pac/src/twis0_ns/publish_error.rs b/pacs/nrf9120-pac/src/twis0_ns/publish_error.rs new file mode 100644 index 00000000..b8934693 --- /dev/null +++ b/pacs/nrf9120-pac/src/twis0_ns/publish_error.rs @@ -0,0 +1,140 @@ +#[doc = "Register `PUBLISH_ERROR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PUBLISH_ERROR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CHIDX` reader - DPPI channel that event ERROR will publish to"] +pub type CHIDX_R = crate::FieldReader; +#[doc = "Field `CHIDX` writer - DPPI channel that event ERROR will publish to"] +pub type CHIDX_W<'a, const O: u8> = crate::FieldWriter<'a, u32, PUBLISH_ERROR_SPEC, u8, u8, 8, O>; +#[doc = "Field `EN` reader - "] +pub type EN_R = crate::BitReader; +#[doc = "\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum EN_A { + #[doc = "0: Disable publishing"] + DISABLED = 0, + #[doc = "1: Enable publishing"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: EN_A) -> Self { + variant as u8 != 0 + } +} +impl EN_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EN_A { + match self.bits { + false => EN_A::DISABLED, + true => EN_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == EN_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == EN_A::ENABLED + } +} +#[doc = "Field `EN` writer - "] +pub type EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, PUBLISH_ERROR_SPEC, EN_A, O>; +impl<'a, const O: u8> EN_W<'a, O> { + #[doc = "Disable publishing"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(EN_A::DISABLED) + } + #[doc = "Enable publishing"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(EN_A::ENABLED) + } +} +impl R { + #[doc = "Bits 0:7 - DPPI channel that event ERROR will publish to"] + #[inline(always)] + pub fn chidx(&self) -> CHIDX_R { + CHIDX_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&self) -> EN_R { + EN_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:7 - DPPI channel that event ERROR will publish to"] + #[inline(always)] + pub fn chidx(&mut self) -> CHIDX_W<0> { + CHIDX_W::new(self) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&mut self) -> EN_W<31> { + EN_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Publish configuration for event ERROR\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [publish_error](index.html) module"] +pub struct PUBLISH_ERROR_SPEC; +impl crate::RegisterSpec for PUBLISH_ERROR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [publish_error::R](R) reader structure"] +impl crate::Readable for PUBLISH_ERROR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [publish_error::W](W) writer structure"] +impl crate::Writable for PUBLISH_ERROR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PUBLISH_ERROR to value 0"] +impl crate::Resettable for PUBLISH_ERROR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/twis0_ns/publish_read.rs b/pacs/nrf9120-pac/src/twis0_ns/publish_read.rs new file mode 100644 index 00000000..7a30cfc5 --- /dev/null +++ b/pacs/nrf9120-pac/src/twis0_ns/publish_read.rs @@ -0,0 +1,140 @@ +#[doc = "Register `PUBLISH_READ` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PUBLISH_READ` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CHIDX` reader - DPPI channel that event READ will publish to"] +pub type CHIDX_R = crate::FieldReader; +#[doc = "Field `CHIDX` writer - DPPI channel that event READ will publish to"] +pub type CHIDX_W<'a, const O: u8> = crate::FieldWriter<'a, u32, PUBLISH_READ_SPEC, u8, u8, 8, O>; +#[doc = "Field `EN` reader - "] +pub type EN_R = crate::BitReader; +#[doc = "\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum EN_A { + #[doc = "0: Disable publishing"] + DISABLED = 0, + #[doc = "1: Enable publishing"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: EN_A) -> Self { + variant as u8 != 0 + } +} +impl EN_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EN_A { + match self.bits { + false => EN_A::DISABLED, + true => EN_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == EN_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == EN_A::ENABLED + } +} +#[doc = "Field `EN` writer - "] +pub type EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, PUBLISH_READ_SPEC, EN_A, O>; +impl<'a, const O: u8> EN_W<'a, O> { + #[doc = "Disable publishing"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(EN_A::DISABLED) + } + #[doc = "Enable publishing"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(EN_A::ENABLED) + } +} +impl R { + #[doc = "Bits 0:7 - DPPI channel that event READ will publish to"] + #[inline(always)] + pub fn chidx(&self) -> CHIDX_R { + CHIDX_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&self) -> EN_R { + EN_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:7 - DPPI channel that event READ will publish to"] + #[inline(always)] + pub fn chidx(&mut self) -> CHIDX_W<0> { + CHIDX_W::new(self) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&mut self) -> EN_W<31> { + EN_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Publish configuration for event READ\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [publish_read](index.html) module"] +pub struct PUBLISH_READ_SPEC; +impl crate::RegisterSpec for PUBLISH_READ_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [publish_read::R](R) reader structure"] +impl crate::Readable for PUBLISH_READ_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [publish_read::W](W) writer structure"] +impl crate::Writable for PUBLISH_READ_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PUBLISH_READ to value 0"] +impl crate::Resettable for PUBLISH_READ_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/twis0_ns/publish_rxstarted.rs b/pacs/nrf9120-pac/src/twis0_ns/publish_rxstarted.rs new file mode 100644 index 00000000..c0328382 --- /dev/null +++ b/pacs/nrf9120-pac/src/twis0_ns/publish_rxstarted.rs @@ -0,0 +1,141 @@ +#[doc = "Register `PUBLISH_RXSTARTED` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PUBLISH_RXSTARTED` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CHIDX` reader - DPPI channel that event RXSTARTED will publish to"] +pub type CHIDX_R = crate::FieldReader; +#[doc = "Field `CHIDX` writer - DPPI channel that event RXSTARTED will publish to"] +pub type CHIDX_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, PUBLISH_RXSTARTED_SPEC, u8, u8, 8, O>; +#[doc = "Field `EN` reader - "] +pub type EN_R = crate::BitReader; +#[doc = "\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum EN_A { + #[doc = "0: Disable publishing"] + DISABLED = 0, + #[doc = "1: Enable publishing"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: EN_A) -> Self { + variant as u8 != 0 + } +} +impl EN_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EN_A { + match self.bits { + false => EN_A::DISABLED, + true => EN_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == EN_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == EN_A::ENABLED + } +} +#[doc = "Field `EN` writer - "] +pub type EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, PUBLISH_RXSTARTED_SPEC, EN_A, O>; +impl<'a, const O: u8> EN_W<'a, O> { + #[doc = "Disable publishing"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(EN_A::DISABLED) + } + #[doc = "Enable publishing"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(EN_A::ENABLED) + } +} +impl R { + #[doc = "Bits 0:7 - DPPI channel that event RXSTARTED will publish to"] + #[inline(always)] + pub fn chidx(&self) -> CHIDX_R { + CHIDX_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&self) -> EN_R { + EN_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:7 - DPPI channel that event RXSTARTED will publish to"] + #[inline(always)] + pub fn chidx(&mut self) -> CHIDX_W<0> { + CHIDX_W::new(self) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&mut self) -> EN_W<31> { + EN_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Publish configuration for event RXSTARTED\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [publish_rxstarted](index.html) module"] +pub struct PUBLISH_RXSTARTED_SPEC; +impl crate::RegisterSpec for PUBLISH_RXSTARTED_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [publish_rxstarted::R](R) reader structure"] +impl crate::Readable for PUBLISH_RXSTARTED_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [publish_rxstarted::W](W) writer structure"] +impl crate::Writable for PUBLISH_RXSTARTED_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PUBLISH_RXSTARTED to value 0"] +impl crate::Resettable for PUBLISH_RXSTARTED_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/twis0_ns/publish_stopped.rs b/pacs/nrf9120-pac/src/twis0_ns/publish_stopped.rs new file mode 100644 index 00000000..247f50bf --- /dev/null +++ b/pacs/nrf9120-pac/src/twis0_ns/publish_stopped.rs @@ -0,0 +1,140 @@ +#[doc = "Register `PUBLISH_STOPPED` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PUBLISH_STOPPED` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CHIDX` reader - DPPI channel that event STOPPED will publish to"] +pub type CHIDX_R = crate::FieldReader; +#[doc = "Field `CHIDX` writer - DPPI channel that event STOPPED will publish to"] +pub type CHIDX_W<'a, const O: u8> = crate::FieldWriter<'a, u32, PUBLISH_STOPPED_SPEC, u8, u8, 8, O>; +#[doc = "Field `EN` reader - "] +pub type EN_R = crate::BitReader; +#[doc = "\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum EN_A { + #[doc = "0: Disable publishing"] + DISABLED = 0, + #[doc = "1: Enable publishing"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: EN_A) -> Self { + variant as u8 != 0 + } +} +impl EN_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EN_A { + match self.bits { + false => EN_A::DISABLED, + true => EN_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == EN_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == EN_A::ENABLED + } +} +#[doc = "Field `EN` writer - "] +pub type EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, PUBLISH_STOPPED_SPEC, EN_A, O>; +impl<'a, const O: u8> EN_W<'a, O> { + #[doc = "Disable publishing"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(EN_A::DISABLED) + } + #[doc = "Enable publishing"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(EN_A::ENABLED) + } +} +impl R { + #[doc = "Bits 0:7 - DPPI channel that event STOPPED will publish to"] + #[inline(always)] + pub fn chidx(&self) -> CHIDX_R { + CHIDX_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&self) -> EN_R { + EN_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:7 - DPPI channel that event STOPPED will publish to"] + #[inline(always)] + pub fn chidx(&mut self) -> CHIDX_W<0> { + CHIDX_W::new(self) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&mut self) -> EN_W<31> { + EN_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Publish configuration for event STOPPED\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [publish_stopped](index.html) module"] +pub struct PUBLISH_STOPPED_SPEC; +impl crate::RegisterSpec for PUBLISH_STOPPED_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [publish_stopped::R](R) reader structure"] +impl crate::Readable for PUBLISH_STOPPED_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [publish_stopped::W](W) writer structure"] +impl crate::Writable for PUBLISH_STOPPED_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PUBLISH_STOPPED to value 0"] +impl crate::Resettable for PUBLISH_STOPPED_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/twis0_ns/publish_txstarted.rs b/pacs/nrf9120-pac/src/twis0_ns/publish_txstarted.rs new file mode 100644 index 00000000..2d049893 --- /dev/null +++ b/pacs/nrf9120-pac/src/twis0_ns/publish_txstarted.rs @@ -0,0 +1,141 @@ +#[doc = "Register `PUBLISH_TXSTARTED` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PUBLISH_TXSTARTED` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CHIDX` reader - DPPI channel that event TXSTARTED will publish to"] +pub type CHIDX_R = crate::FieldReader; +#[doc = "Field `CHIDX` writer - DPPI channel that event TXSTARTED will publish to"] +pub type CHIDX_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, PUBLISH_TXSTARTED_SPEC, u8, u8, 8, O>; +#[doc = "Field `EN` reader - "] +pub type EN_R = crate::BitReader; +#[doc = "\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum EN_A { + #[doc = "0: Disable publishing"] + DISABLED = 0, + #[doc = "1: Enable publishing"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: EN_A) -> Self { + variant as u8 != 0 + } +} +impl EN_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EN_A { + match self.bits { + false => EN_A::DISABLED, + true => EN_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == EN_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == EN_A::ENABLED + } +} +#[doc = "Field `EN` writer - "] +pub type EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, PUBLISH_TXSTARTED_SPEC, EN_A, O>; +impl<'a, const O: u8> EN_W<'a, O> { + #[doc = "Disable publishing"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(EN_A::DISABLED) + } + #[doc = "Enable publishing"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(EN_A::ENABLED) + } +} +impl R { + #[doc = "Bits 0:7 - DPPI channel that event TXSTARTED will publish to"] + #[inline(always)] + pub fn chidx(&self) -> CHIDX_R { + CHIDX_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&self) -> EN_R { + EN_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:7 - DPPI channel that event TXSTARTED will publish to"] + #[inline(always)] + pub fn chidx(&mut self) -> CHIDX_W<0> { + CHIDX_W::new(self) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&mut self) -> EN_W<31> { + EN_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Publish configuration for event TXSTARTED\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [publish_txstarted](index.html) module"] +pub struct PUBLISH_TXSTARTED_SPEC; +impl crate::RegisterSpec for PUBLISH_TXSTARTED_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [publish_txstarted::R](R) reader structure"] +impl crate::Readable for PUBLISH_TXSTARTED_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [publish_txstarted::W](W) writer structure"] +impl crate::Writable for PUBLISH_TXSTARTED_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PUBLISH_TXSTARTED to value 0"] +impl crate::Resettable for PUBLISH_TXSTARTED_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/twis0_ns/publish_write.rs b/pacs/nrf9120-pac/src/twis0_ns/publish_write.rs new file mode 100644 index 00000000..b9ae22a7 --- /dev/null +++ b/pacs/nrf9120-pac/src/twis0_ns/publish_write.rs @@ -0,0 +1,140 @@ +#[doc = "Register `PUBLISH_WRITE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PUBLISH_WRITE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CHIDX` reader - DPPI channel that event WRITE will publish to"] +pub type CHIDX_R = crate::FieldReader; +#[doc = "Field `CHIDX` writer - DPPI channel that event WRITE will publish to"] +pub type CHIDX_W<'a, const O: u8> = crate::FieldWriter<'a, u32, PUBLISH_WRITE_SPEC, u8, u8, 8, O>; +#[doc = "Field `EN` reader - "] +pub type EN_R = crate::BitReader; +#[doc = "\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum EN_A { + #[doc = "0: Disable publishing"] + DISABLED = 0, + #[doc = "1: Enable publishing"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: EN_A) -> Self { + variant as u8 != 0 + } +} +impl EN_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EN_A { + match self.bits { + false => EN_A::DISABLED, + true => EN_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == EN_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == EN_A::ENABLED + } +} +#[doc = "Field `EN` writer - "] +pub type EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, PUBLISH_WRITE_SPEC, EN_A, O>; +impl<'a, const O: u8> EN_W<'a, O> { + #[doc = "Disable publishing"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(EN_A::DISABLED) + } + #[doc = "Enable publishing"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(EN_A::ENABLED) + } +} +impl R { + #[doc = "Bits 0:7 - DPPI channel that event WRITE will publish to"] + #[inline(always)] + pub fn chidx(&self) -> CHIDX_R { + CHIDX_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&self) -> EN_R { + EN_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:7 - DPPI channel that event WRITE will publish to"] + #[inline(always)] + pub fn chidx(&mut self) -> CHIDX_W<0> { + CHIDX_W::new(self) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&mut self) -> EN_W<31> { + EN_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Publish configuration for event WRITE\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [publish_write](index.html) module"] +pub struct PUBLISH_WRITE_SPEC; +impl crate::RegisterSpec for PUBLISH_WRITE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [publish_write::R](R) reader structure"] +impl crate::Readable for PUBLISH_WRITE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [publish_write::W](W) writer structure"] +impl crate::Writable for PUBLISH_WRITE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PUBLISH_WRITE to value 0"] +impl crate::Resettable for PUBLISH_WRITE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/twis0_ns/rxd.rs b/pacs/nrf9120-pac/src/twis0_ns/rxd.rs new file mode 100644 index 00000000..b306b63d --- /dev/null +++ b/pacs/nrf9120-pac/src/twis0_ns/rxd.rs @@ -0,0 +1,28 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RXD { + #[doc = "0x00 - RXD Data pointer"] + pub ptr: PTR, + #[doc = "0x04 - Maximum number of bytes in RXD buffer"] + pub maxcnt: MAXCNT, + #[doc = "0x08 - Number of bytes transferred in the last RXD transaction"] + pub amount: AMOUNT, + #[doc = "0x0c - EasyDMA list type"] + pub list: LIST, +} +#[doc = "PTR (rw) register accessor: an alias for `Reg`"] +pub type PTR = crate::Reg; +#[doc = "RXD Data pointer"] +pub mod ptr; +#[doc = "MAXCNT (rw) register accessor: an alias for `Reg`"] +pub type MAXCNT = crate::Reg; +#[doc = "Maximum number of bytes in RXD buffer"] +pub mod maxcnt; +#[doc = "AMOUNT (r) register accessor: an alias for `Reg`"] +pub type AMOUNT = crate::Reg; +#[doc = "Number of bytes transferred in the last RXD transaction"] +pub mod amount; +#[doc = "LIST (rw) register accessor: an alias for `Reg`"] +pub type LIST = crate::Reg; +#[doc = "EasyDMA list type"] +pub mod list; diff --git a/pacs/nrf9120-pac/src/twis0_ns/rxd/amount.rs b/pacs/nrf9120-pac/src/twis0_ns/rxd/amount.rs new file mode 100644 index 00000000..23ee0ad2 --- /dev/null +++ b/pacs/nrf9120-pac/src/twis0_ns/rxd/amount.rs @@ -0,0 +1,40 @@ +#[doc = "Register `AMOUNT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `AMOUNT` reader - Number of bytes transferred in the last RXD transaction"] +pub type AMOUNT_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:12 - Number of bytes transferred in the last RXD transaction"] + #[inline(always)] + pub fn amount(&self) -> AMOUNT_R { + AMOUNT_R::new((self.bits & 0x1fff) as u16) + } +} +#[doc = "Number of bytes transferred in the last RXD transaction\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [amount](index.html) module"] +pub struct AMOUNT_SPEC; +impl crate::RegisterSpec for AMOUNT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [amount::R](R) reader structure"] +impl crate::Readable for AMOUNT_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets AMOUNT to value 0"] +impl crate::Resettable for AMOUNT_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/twis0_ns/rxd/list.rs b/pacs/nrf9120-pac/src/twis0_ns/rxd/list.rs new file mode 100644 index 00000000..aa379b8c --- /dev/null +++ b/pacs/nrf9120-pac/src/twis0_ns/rxd/list.rs @@ -0,0 +1,128 @@ +#[doc = "Register `LIST` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `LIST` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `LIST` reader - List type"] +pub type LIST_R = crate::FieldReader; +#[doc = "List type\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum LIST_A { + #[doc = "0: Disable EasyDMA list"] + DISABLED = 0, + #[doc = "1: Use array list"] + ARRAY_LIST = 1, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LIST_A) -> Self { + variant as _ + } +} +impl LIST_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(LIST_A::DISABLED), + 1 => Some(LIST_A::ARRAY_LIST), + _ => None, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == LIST_A::DISABLED + } + #[doc = "Checks if the value of the field is `ARRAY_LIST`"] + #[inline(always)] + pub fn is_array_list(&self) -> bool { + *self == LIST_A::ARRAY_LIST + } +} +#[doc = "Field `LIST` writer - List type"] +pub type LIST_W<'a, const O: u8> = crate::FieldWriter<'a, u32, LIST_SPEC, u8, LIST_A, 2, O>; +impl<'a, const O: u8> LIST_W<'a, O> { + #[doc = "Disable EasyDMA list"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(LIST_A::DISABLED) + } + #[doc = "Use array list"] + #[inline(always)] + pub fn array_list(self) -> &'a mut W { + self.variant(LIST_A::ARRAY_LIST) + } +} +impl R { + #[doc = "Bits 0:1 - List type"] + #[inline(always)] + pub fn list(&self) -> LIST_R { + LIST_R::new((self.bits & 3) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - List type"] + #[inline(always)] + pub fn list(&mut self) -> LIST_W<0> { + LIST_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "EasyDMA list type\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [list](index.html) module"] +pub struct LIST_SPEC; +impl crate::RegisterSpec for LIST_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [list::R](R) reader structure"] +impl crate::Readable for LIST_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [list::W](W) writer structure"] +impl crate::Writable for LIST_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets LIST to value 0"] +impl crate::Resettable for LIST_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/twis0_ns/rxd/maxcnt.rs b/pacs/nrf9120-pac/src/twis0_ns/rxd/maxcnt.rs new file mode 100644 index 00000000..171e19ec --- /dev/null +++ b/pacs/nrf9120-pac/src/twis0_ns/rxd/maxcnt.rs @@ -0,0 +1,80 @@ +#[doc = "Register `MAXCNT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `MAXCNT` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `MAXCNT` reader - Maximum number of bytes in RXD buffer"] +pub type MAXCNT_R = crate::FieldReader; +#[doc = "Field `MAXCNT` writer - Maximum number of bytes in RXD buffer"] +pub type MAXCNT_W<'a, const O: u8> = crate::FieldWriter<'a, u32, MAXCNT_SPEC, u16, u16, 13, O>; +impl R { + #[doc = "Bits 0:12 - Maximum number of bytes in RXD buffer"] + #[inline(always)] + pub fn maxcnt(&self) -> MAXCNT_R { + MAXCNT_R::new((self.bits & 0x1fff) as u16) + } +} +impl W { + #[doc = "Bits 0:12 - Maximum number of bytes in RXD buffer"] + #[inline(always)] + pub fn maxcnt(&mut self) -> MAXCNT_W<0> { + MAXCNT_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Maximum number of bytes in RXD buffer\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [maxcnt](index.html) module"] +pub struct MAXCNT_SPEC; +impl crate::RegisterSpec for MAXCNT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [maxcnt::R](R) reader structure"] +impl crate::Readable for MAXCNT_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [maxcnt::W](W) writer structure"] +impl crate::Writable for MAXCNT_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets MAXCNT to value 0"] +impl crate::Resettable for MAXCNT_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/twis0_ns/rxd/ptr.rs b/pacs/nrf9120-pac/src/twis0_ns/rxd/ptr.rs new file mode 100644 index 00000000..535066d0 --- /dev/null +++ b/pacs/nrf9120-pac/src/twis0_ns/rxd/ptr.rs @@ -0,0 +1,80 @@ +#[doc = "Register `PTR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PTR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PTR` reader - RXD Data pointer"] +pub type PTR_R = crate::FieldReader; +#[doc = "Field `PTR` writer - RXD Data pointer"] +pub type PTR_W<'a, const O: u8> = crate::FieldWriter<'a, u32, PTR_SPEC, u32, u32, 32, O>; +impl R { + #[doc = "Bits 0:31 - RXD Data pointer"] + #[inline(always)] + pub fn ptr(&self) -> PTR_R { + PTR_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - RXD Data pointer"] + #[inline(always)] + pub fn ptr(&mut self) -> PTR_W<0> { + PTR_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "RXD Data pointer\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ptr](index.html) module"] +pub struct PTR_SPEC; +impl crate::RegisterSpec for PTR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ptr::R](R) reader structure"] +impl crate::Readable for PTR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ptr::W](W) writer structure"] +impl crate::Writable for PTR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PTR to value 0"] +impl crate::Resettable for PTR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/twis0_ns/shorts.rs b/pacs/nrf9120-pac/src/twis0_ns/shorts.rs new file mode 100644 index 00000000..74033e67 --- /dev/null +++ b/pacs/nrf9120-pac/src/twis0_ns/shorts.rs @@ -0,0 +1,188 @@ +#[doc = "Register `SHORTS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SHORTS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `WRITE_SUSPEND` reader - Shortcut between event WRITE and task SUSPEND"] +pub type WRITE_SUSPEND_R = crate::BitReader; +#[doc = "Shortcut between event WRITE and task SUSPEND\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum WRITE_SUSPEND_A { + #[doc = "0: Disable shortcut"] + DISABLED = 0, + #[doc = "1: Enable shortcut"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: WRITE_SUSPEND_A) -> Self { + variant as u8 != 0 + } +} +impl WRITE_SUSPEND_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> WRITE_SUSPEND_A { + match self.bits { + false => WRITE_SUSPEND_A::DISABLED, + true => WRITE_SUSPEND_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == WRITE_SUSPEND_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == WRITE_SUSPEND_A::ENABLED + } +} +#[doc = "Field `WRITE_SUSPEND` writer - Shortcut between event WRITE and task SUSPEND"] +pub type WRITE_SUSPEND_W<'a, const O: u8> = + crate::BitWriter<'a, u32, SHORTS_SPEC, WRITE_SUSPEND_A, O>; +impl<'a, const O: u8> WRITE_SUSPEND_W<'a, O> { + #[doc = "Disable shortcut"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(WRITE_SUSPEND_A::DISABLED) + } + #[doc = "Enable shortcut"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(WRITE_SUSPEND_A::ENABLED) + } +} +#[doc = "Field `READ_SUSPEND` reader - Shortcut between event READ and task SUSPEND"] +pub type READ_SUSPEND_R = crate::BitReader; +#[doc = "Shortcut between event READ and task SUSPEND\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum READ_SUSPEND_A { + #[doc = "0: Disable shortcut"] + DISABLED = 0, + #[doc = "1: Enable shortcut"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: READ_SUSPEND_A) -> Self { + variant as u8 != 0 + } +} +impl READ_SUSPEND_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> READ_SUSPEND_A { + match self.bits { + false => READ_SUSPEND_A::DISABLED, + true => READ_SUSPEND_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == READ_SUSPEND_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == READ_SUSPEND_A::ENABLED + } +} +#[doc = "Field `READ_SUSPEND` writer - Shortcut between event READ and task SUSPEND"] +pub type READ_SUSPEND_W<'a, const O: u8> = + crate::BitWriter<'a, u32, SHORTS_SPEC, READ_SUSPEND_A, O>; +impl<'a, const O: u8> READ_SUSPEND_W<'a, O> { + #[doc = "Disable shortcut"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(READ_SUSPEND_A::DISABLED) + } + #[doc = "Enable shortcut"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(READ_SUSPEND_A::ENABLED) + } +} +impl R { + #[doc = "Bit 13 - Shortcut between event WRITE and task SUSPEND"] + #[inline(always)] + pub fn write_suspend(&self) -> WRITE_SUSPEND_R { + WRITE_SUSPEND_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Shortcut between event READ and task SUSPEND"] + #[inline(always)] + pub fn read_suspend(&self) -> READ_SUSPEND_R { + READ_SUSPEND_R::new(((self.bits >> 14) & 1) != 0) + } +} +impl W { + #[doc = "Bit 13 - Shortcut between event WRITE and task SUSPEND"] + #[inline(always)] + pub fn write_suspend(&mut self) -> WRITE_SUSPEND_W<13> { + WRITE_SUSPEND_W::new(self) + } + #[doc = "Bit 14 - Shortcut between event READ and task SUSPEND"] + #[inline(always)] + pub fn read_suspend(&mut self) -> READ_SUSPEND_W<14> { + READ_SUSPEND_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Shortcuts between local events and tasks\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [shorts](index.html) module"] +pub struct SHORTS_SPEC; +impl crate::RegisterSpec for SHORTS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [shorts::R](R) reader structure"] +impl crate::Readable for SHORTS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [shorts::W](W) writer structure"] +impl crate::Writable for SHORTS_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SHORTS to value 0"] +impl crate::Resettable for SHORTS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/twis0_ns/subscribe_preparerx.rs b/pacs/nrf9120-pac/src/twis0_ns/subscribe_preparerx.rs new file mode 100644 index 00000000..dac9044d --- /dev/null +++ b/pacs/nrf9120-pac/src/twis0_ns/subscribe_preparerx.rs @@ -0,0 +1,141 @@ +#[doc = "Register `SUBSCRIBE_PREPARERX` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SUBSCRIBE_PREPARERX` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CHIDX` reader - DPPI channel that task PREPARERX will subscribe to"] +pub type CHIDX_R = crate::FieldReader; +#[doc = "Field `CHIDX` writer - DPPI channel that task PREPARERX will subscribe to"] +pub type CHIDX_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, SUBSCRIBE_PREPARERX_SPEC, u8, u8, 8, O>; +#[doc = "Field `EN` reader - "] +pub type EN_R = crate::BitReader; +#[doc = "\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum EN_A { + #[doc = "0: Disable subscription"] + DISABLED = 0, + #[doc = "1: Enable subscription"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: EN_A) -> Self { + variant as u8 != 0 + } +} +impl EN_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EN_A { + match self.bits { + false => EN_A::DISABLED, + true => EN_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == EN_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == EN_A::ENABLED + } +} +#[doc = "Field `EN` writer - "] +pub type EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, SUBSCRIBE_PREPARERX_SPEC, EN_A, O>; +impl<'a, const O: u8> EN_W<'a, O> { + #[doc = "Disable subscription"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(EN_A::DISABLED) + } + #[doc = "Enable subscription"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(EN_A::ENABLED) + } +} +impl R { + #[doc = "Bits 0:7 - DPPI channel that task PREPARERX will subscribe to"] + #[inline(always)] + pub fn chidx(&self) -> CHIDX_R { + CHIDX_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&self) -> EN_R { + EN_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:7 - DPPI channel that task PREPARERX will subscribe to"] + #[inline(always)] + pub fn chidx(&mut self) -> CHIDX_W<0> { + CHIDX_W::new(self) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&mut self) -> EN_W<31> { + EN_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Subscribe configuration for task PREPARERX\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [subscribe_preparerx](index.html) module"] +pub struct SUBSCRIBE_PREPARERX_SPEC; +impl crate::RegisterSpec for SUBSCRIBE_PREPARERX_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [subscribe_preparerx::R](R) reader structure"] +impl crate::Readable for SUBSCRIBE_PREPARERX_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [subscribe_preparerx::W](W) writer structure"] +impl crate::Writable for SUBSCRIBE_PREPARERX_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SUBSCRIBE_PREPARERX to value 0"] +impl crate::Resettable for SUBSCRIBE_PREPARERX_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/twis0_ns/subscribe_preparetx.rs b/pacs/nrf9120-pac/src/twis0_ns/subscribe_preparetx.rs new file mode 100644 index 00000000..506a6193 --- /dev/null +++ b/pacs/nrf9120-pac/src/twis0_ns/subscribe_preparetx.rs @@ -0,0 +1,141 @@ +#[doc = "Register `SUBSCRIBE_PREPARETX` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SUBSCRIBE_PREPARETX` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CHIDX` reader - DPPI channel that task PREPARETX will subscribe to"] +pub type CHIDX_R = crate::FieldReader; +#[doc = "Field `CHIDX` writer - DPPI channel that task PREPARETX will subscribe to"] +pub type CHIDX_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, SUBSCRIBE_PREPARETX_SPEC, u8, u8, 8, O>; +#[doc = "Field `EN` reader - "] +pub type EN_R = crate::BitReader; +#[doc = "\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum EN_A { + #[doc = "0: Disable subscription"] + DISABLED = 0, + #[doc = "1: Enable subscription"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: EN_A) -> Self { + variant as u8 != 0 + } +} +impl EN_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EN_A { + match self.bits { + false => EN_A::DISABLED, + true => EN_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == EN_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == EN_A::ENABLED + } +} +#[doc = "Field `EN` writer - "] +pub type EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, SUBSCRIBE_PREPARETX_SPEC, EN_A, O>; +impl<'a, const O: u8> EN_W<'a, O> { + #[doc = "Disable subscription"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(EN_A::DISABLED) + } + #[doc = "Enable subscription"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(EN_A::ENABLED) + } +} +impl R { + #[doc = "Bits 0:7 - DPPI channel that task PREPARETX will subscribe to"] + #[inline(always)] + pub fn chidx(&self) -> CHIDX_R { + CHIDX_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&self) -> EN_R { + EN_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:7 - DPPI channel that task PREPARETX will subscribe to"] + #[inline(always)] + pub fn chidx(&mut self) -> CHIDX_W<0> { + CHIDX_W::new(self) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&mut self) -> EN_W<31> { + EN_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Subscribe configuration for task PREPARETX\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [subscribe_preparetx](index.html) module"] +pub struct SUBSCRIBE_PREPARETX_SPEC; +impl crate::RegisterSpec for SUBSCRIBE_PREPARETX_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [subscribe_preparetx::R](R) reader structure"] +impl crate::Readable for SUBSCRIBE_PREPARETX_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [subscribe_preparetx::W](W) writer structure"] +impl crate::Writable for SUBSCRIBE_PREPARETX_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SUBSCRIBE_PREPARETX to value 0"] +impl crate::Resettable for SUBSCRIBE_PREPARETX_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/twis0_ns/subscribe_resume.rs b/pacs/nrf9120-pac/src/twis0_ns/subscribe_resume.rs new file mode 100644 index 00000000..cef10f00 --- /dev/null +++ b/pacs/nrf9120-pac/src/twis0_ns/subscribe_resume.rs @@ -0,0 +1,141 @@ +#[doc = "Register `SUBSCRIBE_RESUME` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SUBSCRIBE_RESUME` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CHIDX` reader - DPPI channel that task RESUME will subscribe to"] +pub type CHIDX_R = crate::FieldReader; +#[doc = "Field `CHIDX` writer - DPPI channel that task RESUME will subscribe to"] +pub type CHIDX_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, SUBSCRIBE_RESUME_SPEC, u8, u8, 8, O>; +#[doc = "Field `EN` reader - "] +pub type EN_R = crate::BitReader; +#[doc = "\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum EN_A { + #[doc = "0: Disable subscription"] + DISABLED = 0, + #[doc = "1: Enable subscription"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: EN_A) -> Self { + variant as u8 != 0 + } +} +impl EN_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EN_A { + match self.bits { + false => EN_A::DISABLED, + true => EN_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == EN_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == EN_A::ENABLED + } +} +#[doc = "Field `EN` writer - "] +pub type EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, SUBSCRIBE_RESUME_SPEC, EN_A, O>; +impl<'a, const O: u8> EN_W<'a, O> { + #[doc = "Disable subscription"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(EN_A::DISABLED) + } + #[doc = "Enable subscription"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(EN_A::ENABLED) + } +} +impl R { + #[doc = "Bits 0:7 - DPPI channel that task RESUME will subscribe to"] + #[inline(always)] + pub fn chidx(&self) -> CHIDX_R { + CHIDX_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&self) -> EN_R { + EN_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:7 - DPPI channel that task RESUME will subscribe to"] + #[inline(always)] + pub fn chidx(&mut self) -> CHIDX_W<0> { + CHIDX_W::new(self) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&mut self) -> EN_W<31> { + EN_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Subscribe configuration for task RESUME\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [subscribe_resume](index.html) module"] +pub struct SUBSCRIBE_RESUME_SPEC; +impl crate::RegisterSpec for SUBSCRIBE_RESUME_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [subscribe_resume::R](R) reader structure"] +impl crate::Readable for SUBSCRIBE_RESUME_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [subscribe_resume::W](W) writer structure"] +impl crate::Writable for SUBSCRIBE_RESUME_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SUBSCRIBE_RESUME to value 0"] +impl crate::Resettable for SUBSCRIBE_RESUME_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/twis0_ns/subscribe_stop.rs b/pacs/nrf9120-pac/src/twis0_ns/subscribe_stop.rs new file mode 100644 index 00000000..2fe3af58 --- /dev/null +++ b/pacs/nrf9120-pac/src/twis0_ns/subscribe_stop.rs @@ -0,0 +1,140 @@ +#[doc = "Register `SUBSCRIBE_STOP` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SUBSCRIBE_STOP` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CHIDX` reader - DPPI channel that task STOP will subscribe to"] +pub type CHIDX_R = crate::FieldReader; +#[doc = "Field `CHIDX` writer - DPPI channel that task STOP will subscribe to"] +pub type CHIDX_W<'a, const O: u8> = crate::FieldWriter<'a, u32, SUBSCRIBE_STOP_SPEC, u8, u8, 8, O>; +#[doc = "Field `EN` reader - "] +pub type EN_R = crate::BitReader; +#[doc = "\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum EN_A { + #[doc = "0: Disable subscription"] + DISABLED = 0, + #[doc = "1: Enable subscription"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: EN_A) -> Self { + variant as u8 != 0 + } +} +impl EN_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EN_A { + match self.bits { + false => EN_A::DISABLED, + true => EN_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == EN_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == EN_A::ENABLED + } +} +#[doc = "Field `EN` writer - "] +pub type EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, SUBSCRIBE_STOP_SPEC, EN_A, O>; +impl<'a, const O: u8> EN_W<'a, O> { + #[doc = "Disable subscription"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(EN_A::DISABLED) + } + #[doc = "Enable subscription"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(EN_A::ENABLED) + } +} +impl R { + #[doc = "Bits 0:7 - DPPI channel that task STOP will subscribe to"] + #[inline(always)] + pub fn chidx(&self) -> CHIDX_R { + CHIDX_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&self) -> EN_R { + EN_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:7 - DPPI channel that task STOP will subscribe to"] + #[inline(always)] + pub fn chidx(&mut self) -> CHIDX_W<0> { + CHIDX_W::new(self) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&mut self) -> EN_W<31> { + EN_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Subscribe configuration for task STOP\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [subscribe_stop](index.html) module"] +pub struct SUBSCRIBE_STOP_SPEC; +impl crate::RegisterSpec for SUBSCRIBE_STOP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [subscribe_stop::R](R) reader structure"] +impl crate::Readable for SUBSCRIBE_STOP_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [subscribe_stop::W](W) writer structure"] +impl crate::Writable for SUBSCRIBE_STOP_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SUBSCRIBE_STOP to value 0"] +impl crate::Resettable for SUBSCRIBE_STOP_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/twis0_ns/subscribe_suspend.rs b/pacs/nrf9120-pac/src/twis0_ns/subscribe_suspend.rs new file mode 100644 index 00000000..b3fe4912 --- /dev/null +++ b/pacs/nrf9120-pac/src/twis0_ns/subscribe_suspend.rs @@ -0,0 +1,141 @@ +#[doc = "Register `SUBSCRIBE_SUSPEND` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SUBSCRIBE_SUSPEND` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CHIDX` reader - DPPI channel that task SUSPEND will subscribe to"] +pub type CHIDX_R = crate::FieldReader; +#[doc = "Field `CHIDX` writer - DPPI channel that task SUSPEND will subscribe to"] +pub type CHIDX_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, SUBSCRIBE_SUSPEND_SPEC, u8, u8, 8, O>; +#[doc = "Field `EN` reader - "] +pub type EN_R = crate::BitReader; +#[doc = "\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum EN_A { + #[doc = "0: Disable subscription"] + DISABLED = 0, + #[doc = "1: Enable subscription"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: EN_A) -> Self { + variant as u8 != 0 + } +} +impl EN_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EN_A { + match self.bits { + false => EN_A::DISABLED, + true => EN_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == EN_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == EN_A::ENABLED + } +} +#[doc = "Field `EN` writer - "] +pub type EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, SUBSCRIBE_SUSPEND_SPEC, EN_A, O>; +impl<'a, const O: u8> EN_W<'a, O> { + #[doc = "Disable subscription"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(EN_A::DISABLED) + } + #[doc = "Enable subscription"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(EN_A::ENABLED) + } +} +impl R { + #[doc = "Bits 0:7 - DPPI channel that task SUSPEND will subscribe to"] + #[inline(always)] + pub fn chidx(&self) -> CHIDX_R { + CHIDX_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&self) -> EN_R { + EN_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:7 - DPPI channel that task SUSPEND will subscribe to"] + #[inline(always)] + pub fn chidx(&mut self) -> CHIDX_W<0> { + CHIDX_W::new(self) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&mut self) -> EN_W<31> { + EN_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Subscribe configuration for task SUSPEND\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [subscribe_suspend](index.html) module"] +pub struct SUBSCRIBE_SUSPEND_SPEC; +impl crate::RegisterSpec for SUBSCRIBE_SUSPEND_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [subscribe_suspend::R](R) reader structure"] +impl crate::Readable for SUBSCRIBE_SUSPEND_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [subscribe_suspend::W](W) writer structure"] +impl crate::Writable for SUBSCRIBE_SUSPEND_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SUBSCRIBE_SUSPEND to value 0"] +impl crate::Resettable for SUBSCRIBE_SUSPEND_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/twis0_ns/tasks_preparerx.rs b/pacs/nrf9120-pac/src/twis0_ns/tasks_preparerx.rs new file mode 100644 index 00000000..6133ebd3 --- /dev/null +++ b/pacs/nrf9120-pac/src/twis0_ns/tasks_preparerx.rs @@ -0,0 +1,72 @@ +#[doc = "Register `TASKS_PREPARERX` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Prepare the TWI slave to respond to a write command\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum TASKS_PREPARERX_AW { + #[doc = "1: Trigger task"] + TRIGGER = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TASKS_PREPARERX_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TASKS_PREPARERX` writer - Prepare the TWI slave to respond to a write command"] +pub type TASKS_PREPARERX_W<'a, const O: u8> = + crate::BitWriter<'a, u32, TASKS_PREPARERX_SPEC, TASKS_PREPARERX_AW, O>; +impl<'a, const O: u8> TASKS_PREPARERX_W<'a, O> { + #[doc = "Trigger task"] + #[inline(always)] + pub fn trigger(self) -> &'a mut W { + self.variant(TASKS_PREPARERX_AW::TRIGGER) + } +} +impl W { + #[doc = "Bit 0 - Prepare the TWI slave to respond to a write command"] + #[inline(always)] + pub fn tasks_preparerx(&mut self) -> TASKS_PREPARERX_W<0> { + TASKS_PREPARERX_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Prepare the TWI slave to respond to a write command\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tasks_preparerx](index.html) module"] +pub struct TASKS_PREPARERX_SPEC; +impl crate::RegisterSpec for TASKS_PREPARERX_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [tasks_preparerx::W](W) writer structure"] +impl crate::Writable for TASKS_PREPARERX_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets TASKS_PREPARERX to value 0"] +impl crate::Resettable for TASKS_PREPARERX_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/twis0_ns/tasks_preparetx.rs b/pacs/nrf9120-pac/src/twis0_ns/tasks_preparetx.rs new file mode 100644 index 00000000..a95c555c --- /dev/null +++ b/pacs/nrf9120-pac/src/twis0_ns/tasks_preparetx.rs @@ -0,0 +1,72 @@ +#[doc = "Register `TASKS_PREPARETX` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Prepare the TWI slave to respond to a read command\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum TASKS_PREPARETX_AW { + #[doc = "1: Trigger task"] + TRIGGER = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TASKS_PREPARETX_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TASKS_PREPARETX` writer - Prepare the TWI slave to respond to a read command"] +pub type TASKS_PREPARETX_W<'a, const O: u8> = + crate::BitWriter<'a, u32, TASKS_PREPARETX_SPEC, TASKS_PREPARETX_AW, O>; +impl<'a, const O: u8> TASKS_PREPARETX_W<'a, O> { + #[doc = "Trigger task"] + #[inline(always)] + pub fn trigger(self) -> &'a mut W { + self.variant(TASKS_PREPARETX_AW::TRIGGER) + } +} +impl W { + #[doc = "Bit 0 - Prepare the TWI slave to respond to a read command"] + #[inline(always)] + pub fn tasks_preparetx(&mut self) -> TASKS_PREPARETX_W<0> { + TASKS_PREPARETX_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Prepare the TWI slave to respond to a read command\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tasks_preparetx](index.html) module"] +pub struct TASKS_PREPARETX_SPEC; +impl crate::RegisterSpec for TASKS_PREPARETX_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [tasks_preparetx::W](W) writer structure"] +impl crate::Writable for TASKS_PREPARETX_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets TASKS_PREPARETX to value 0"] +impl crate::Resettable for TASKS_PREPARETX_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/twis0_ns/tasks_resume.rs b/pacs/nrf9120-pac/src/twis0_ns/tasks_resume.rs new file mode 100644 index 00000000..f246e04d --- /dev/null +++ b/pacs/nrf9120-pac/src/twis0_ns/tasks_resume.rs @@ -0,0 +1,72 @@ +#[doc = "Register `TASKS_RESUME` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Resume TWI transaction\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum TASKS_RESUME_AW { + #[doc = "1: Trigger task"] + TRIGGER = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TASKS_RESUME_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TASKS_RESUME` writer - Resume TWI transaction"] +pub type TASKS_RESUME_W<'a, const O: u8> = + crate::BitWriter<'a, u32, TASKS_RESUME_SPEC, TASKS_RESUME_AW, O>; +impl<'a, const O: u8> TASKS_RESUME_W<'a, O> { + #[doc = "Trigger task"] + #[inline(always)] + pub fn trigger(self) -> &'a mut W { + self.variant(TASKS_RESUME_AW::TRIGGER) + } +} +impl W { + #[doc = "Bit 0 - Resume TWI transaction"] + #[inline(always)] + pub fn tasks_resume(&mut self) -> TASKS_RESUME_W<0> { + TASKS_RESUME_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Resume TWI transaction\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tasks_resume](index.html) module"] +pub struct TASKS_RESUME_SPEC; +impl crate::RegisterSpec for TASKS_RESUME_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [tasks_resume::W](W) writer structure"] +impl crate::Writable for TASKS_RESUME_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets TASKS_RESUME to value 0"] +impl crate::Resettable for TASKS_RESUME_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/twis0_ns/tasks_stop.rs b/pacs/nrf9120-pac/src/twis0_ns/tasks_stop.rs new file mode 100644 index 00000000..66eb6cad --- /dev/null +++ b/pacs/nrf9120-pac/src/twis0_ns/tasks_stop.rs @@ -0,0 +1,72 @@ +#[doc = "Register `TASKS_STOP` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Stop TWI transaction\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum TASKS_STOP_AW { + #[doc = "1: Trigger task"] + TRIGGER = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TASKS_STOP_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TASKS_STOP` writer - Stop TWI transaction"] +pub type TASKS_STOP_W<'a, const O: u8> = + crate::BitWriter<'a, u32, TASKS_STOP_SPEC, TASKS_STOP_AW, O>; +impl<'a, const O: u8> TASKS_STOP_W<'a, O> { + #[doc = "Trigger task"] + #[inline(always)] + pub fn trigger(self) -> &'a mut W { + self.variant(TASKS_STOP_AW::TRIGGER) + } +} +impl W { + #[doc = "Bit 0 - Stop TWI transaction"] + #[inline(always)] + pub fn tasks_stop(&mut self) -> TASKS_STOP_W<0> { + TASKS_STOP_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Stop TWI transaction\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tasks_stop](index.html) module"] +pub struct TASKS_STOP_SPEC; +impl crate::RegisterSpec for TASKS_STOP_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [tasks_stop::W](W) writer structure"] +impl crate::Writable for TASKS_STOP_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets TASKS_STOP to value 0"] +impl crate::Resettable for TASKS_STOP_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/twis0_ns/tasks_suspend.rs b/pacs/nrf9120-pac/src/twis0_ns/tasks_suspend.rs new file mode 100644 index 00000000..37884f26 --- /dev/null +++ b/pacs/nrf9120-pac/src/twis0_ns/tasks_suspend.rs @@ -0,0 +1,72 @@ +#[doc = "Register `TASKS_SUSPEND` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Suspend TWI transaction\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum TASKS_SUSPEND_AW { + #[doc = "1: Trigger task"] + TRIGGER = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TASKS_SUSPEND_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TASKS_SUSPEND` writer - Suspend TWI transaction"] +pub type TASKS_SUSPEND_W<'a, const O: u8> = + crate::BitWriter<'a, u32, TASKS_SUSPEND_SPEC, TASKS_SUSPEND_AW, O>; +impl<'a, const O: u8> TASKS_SUSPEND_W<'a, O> { + #[doc = "Trigger task"] + #[inline(always)] + pub fn trigger(self) -> &'a mut W { + self.variant(TASKS_SUSPEND_AW::TRIGGER) + } +} +impl W { + #[doc = "Bit 0 - Suspend TWI transaction"] + #[inline(always)] + pub fn tasks_suspend(&mut self) -> TASKS_SUSPEND_W<0> { + TASKS_SUSPEND_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Suspend TWI transaction\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tasks_suspend](index.html) module"] +pub struct TASKS_SUSPEND_SPEC; +impl crate::RegisterSpec for TASKS_SUSPEND_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [tasks_suspend::W](W) writer structure"] +impl crate::Writable for TASKS_SUSPEND_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets TASKS_SUSPEND to value 0"] +impl crate::Resettable for TASKS_SUSPEND_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/twis0_ns/txd.rs b/pacs/nrf9120-pac/src/twis0_ns/txd.rs new file mode 100644 index 00000000..66032c3b --- /dev/null +++ b/pacs/nrf9120-pac/src/twis0_ns/txd.rs @@ -0,0 +1,28 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct TXD { + #[doc = "0x00 - TXD Data pointer"] + pub ptr: PTR, + #[doc = "0x04 - Maximum number of bytes in TXD buffer"] + pub maxcnt: MAXCNT, + #[doc = "0x08 - Number of bytes transferred in the last TXD transaction"] + pub amount: AMOUNT, + #[doc = "0x0c - EasyDMA list type"] + pub list: LIST, +} +#[doc = "PTR (rw) register accessor: an alias for `Reg`"] +pub type PTR = crate::Reg; +#[doc = "TXD Data pointer"] +pub mod ptr; +#[doc = "MAXCNT (rw) register accessor: an alias for `Reg`"] +pub type MAXCNT = crate::Reg; +#[doc = "Maximum number of bytes in TXD buffer"] +pub mod maxcnt; +#[doc = "AMOUNT (r) register accessor: an alias for `Reg`"] +pub type AMOUNT = crate::Reg; +#[doc = "Number of bytes transferred in the last TXD transaction"] +pub mod amount; +#[doc = "LIST (rw) register accessor: an alias for `Reg`"] +pub type LIST = crate::Reg; +#[doc = "EasyDMA list type"] +pub mod list; diff --git a/pacs/nrf9120-pac/src/twis0_ns/txd/amount.rs b/pacs/nrf9120-pac/src/twis0_ns/txd/amount.rs new file mode 100644 index 00000000..bc15c252 --- /dev/null +++ b/pacs/nrf9120-pac/src/twis0_ns/txd/amount.rs @@ -0,0 +1,40 @@ +#[doc = "Register `AMOUNT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `AMOUNT` reader - Number of bytes transferred in the last TXD transaction"] +pub type AMOUNT_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:12 - Number of bytes transferred in the last TXD transaction"] + #[inline(always)] + pub fn amount(&self) -> AMOUNT_R { + AMOUNT_R::new((self.bits & 0x1fff) as u16) + } +} +#[doc = "Number of bytes transferred in the last TXD transaction\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [amount](index.html) module"] +pub struct AMOUNT_SPEC; +impl crate::RegisterSpec for AMOUNT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [amount::R](R) reader structure"] +impl crate::Readable for AMOUNT_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets AMOUNT to value 0"] +impl crate::Resettable for AMOUNT_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/twis0_ns/txd/list.rs b/pacs/nrf9120-pac/src/twis0_ns/txd/list.rs new file mode 100644 index 00000000..aa379b8c --- /dev/null +++ b/pacs/nrf9120-pac/src/twis0_ns/txd/list.rs @@ -0,0 +1,128 @@ +#[doc = "Register `LIST` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `LIST` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `LIST` reader - List type"] +pub type LIST_R = crate::FieldReader; +#[doc = "List type\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum LIST_A { + #[doc = "0: Disable EasyDMA list"] + DISABLED = 0, + #[doc = "1: Use array list"] + ARRAY_LIST = 1, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LIST_A) -> Self { + variant as _ + } +} +impl LIST_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(LIST_A::DISABLED), + 1 => Some(LIST_A::ARRAY_LIST), + _ => None, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == LIST_A::DISABLED + } + #[doc = "Checks if the value of the field is `ARRAY_LIST`"] + #[inline(always)] + pub fn is_array_list(&self) -> bool { + *self == LIST_A::ARRAY_LIST + } +} +#[doc = "Field `LIST` writer - List type"] +pub type LIST_W<'a, const O: u8> = crate::FieldWriter<'a, u32, LIST_SPEC, u8, LIST_A, 2, O>; +impl<'a, const O: u8> LIST_W<'a, O> { + #[doc = "Disable EasyDMA list"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(LIST_A::DISABLED) + } + #[doc = "Use array list"] + #[inline(always)] + pub fn array_list(self) -> &'a mut W { + self.variant(LIST_A::ARRAY_LIST) + } +} +impl R { + #[doc = "Bits 0:1 - List type"] + #[inline(always)] + pub fn list(&self) -> LIST_R { + LIST_R::new((self.bits & 3) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - List type"] + #[inline(always)] + pub fn list(&mut self) -> LIST_W<0> { + LIST_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "EasyDMA list type\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [list](index.html) module"] +pub struct LIST_SPEC; +impl crate::RegisterSpec for LIST_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [list::R](R) reader structure"] +impl crate::Readable for LIST_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [list::W](W) writer structure"] +impl crate::Writable for LIST_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets LIST to value 0"] +impl crate::Resettable for LIST_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/twis0_ns/txd/maxcnt.rs b/pacs/nrf9120-pac/src/twis0_ns/txd/maxcnt.rs new file mode 100644 index 00000000..92ef37c3 --- /dev/null +++ b/pacs/nrf9120-pac/src/twis0_ns/txd/maxcnt.rs @@ -0,0 +1,80 @@ +#[doc = "Register `MAXCNT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `MAXCNT` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `MAXCNT` reader - Maximum number of bytes in TXD buffer"] +pub type MAXCNT_R = crate::FieldReader; +#[doc = "Field `MAXCNT` writer - Maximum number of bytes in TXD buffer"] +pub type MAXCNT_W<'a, const O: u8> = crate::FieldWriter<'a, u32, MAXCNT_SPEC, u16, u16, 13, O>; +impl R { + #[doc = "Bits 0:12 - Maximum number of bytes in TXD buffer"] + #[inline(always)] + pub fn maxcnt(&self) -> MAXCNT_R { + MAXCNT_R::new((self.bits & 0x1fff) as u16) + } +} +impl W { + #[doc = "Bits 0:12 - Maximum number of bytes in TXD buffer"] + #[inline(always)] + pub fn maxcnt(&mut self) -> MAXCNT_W<0> { + MAXCNT_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Maximum number of bytes in TXD buffer\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [maxcnt](index.html) module"] +pub struct MAXCNT_SPEC; +impl crate::RegisterSpec for MAXCNT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [maxcnt::R](R) reader structure"] +impl crate::Readable for MAXCNT_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [maxcnt::W](W) writer structure"] +impl crate::Writable for MAXCNT_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets MAXCNT to value 0"] +impl crate::Resettable for MAXCNT_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/twis0_ns/txd/ptr.rs b/pacs/nrf9120-pac/src/twis0_ns/txd/ptr.rs new file mode 100644 index 00000000..38de2db6 --- /dev/null +++ b/pacs/nrf9120-pac/src/twis0_ns/txd/ptr.rs @@ -0,0 +1,80 @@ +#[doc = "Register `PTR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PTR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PTR` reader - TXD Data pointer"] +pub type PTR_R = crate::FieldReader; +#[doc = "Field `PTR` writer - TXD Data pointer"] +pub type PTR_W<'a, const O: u8> = crate::FieldWriter<'a, u32, PTR_SPEC, u32, u32, 32, O>; +impl R { + #[doc = "Bits 0:31 - TXD Data pointer"] + #[inline(always)] + pub fn ptr(&self) -> PTR_R { + PTR_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - TXD Data pointer"] + #[inline(always)] + pub fn ptr(&mut self) -> PTR_W<0> { + PTR_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "TXD Data pointer\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ptr](index.html) module"] +pub struct PTR_SPEC; +impl crate::RegisterSpec for PTR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ptr::R](R) reader structure"] +impl crate::Readable for PTR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ptr::W](W) writer structure"] +impl crate::Writable for PTR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PTR to value 0"] +impl crate::Resettable for PTR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/uarte0_ns.rs b/pacs/nrf9120-pac/src/uarte0_ns.rs new file mode 100644 index 00000000..4f07bbca --- /dev/null +++ b/pacs/nrf9120-pac/src/uarte0_ns.rs @@ -0,0 +1,289 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Start UART receiver"] + pub tasks_startrx: TASKS_STARTRX, + #[doc = "0x04 - Stop UART receiver"] + pub tasks_stoprx: TASKS_STOPRX, + #[doc = "0x08 - Start UART transmitter"] + pub tasks_starttx: TASKS_STARTTX, + #[doc = "0x0c - Stop UART transmitter"] + pub tasks_stoptx: TASKS_STOPTX, + _reserved4: [u8; 0x1c], + #[doc = "0x2c - Flush RX FIFO into RX buffer"] + pub tasks_flushrx: TASKS_FLUSHRX, + _reserved5: [u8; 0x50], + #[doc = "0x80 - Subscribe configuration for task STARTRX"] + pub subscribe_startrx: SUBSCRIBE_STARTRX, + #[doc = "0x84 - Subscribe configuration for task STOPRX"] + pub subscribe_stoprx: SUBSCRIBE_STOPRX, + #[doc = "0x88 - Subscribe configuration for task STARTTX"] + pub subscribe_starttx: SUBSCRIBE_STARTTX, + #[doc = "0x8c - Subscribe configuration for task STOPTX"] + pub subscribe_stoptx: SUBSCRIBE_STOPTX, + _reserved9: [u8; 0x1c], + #[doc = "0xac - Subscribe configuration for task FLUSHRX"] + pub subscribe_flushrx: SUBSCRIBE_FLUSHRX, + _reserved10: [u8; 0x50], + #[doc = "0x100 - CTS is activated (set low). Clear To Send."] + pub events_cts: EVENTS_CTS, + #[doc = "0x104 - CTS is deactivated (set high). Not Clear To Send."] + pub events_ncts: EVENTS_NCTS, + #[doc = "0x108 - Data received in RXD (but potentially not yet transferred to Data RAM)"] + pub events_rxdrdy: EVENTS_RXDRDY, + _reserved13: [u8; 0x04], + #[doc = "0x110 - Receive buffer is filled up"] + pub events_endrx: EVENTS_ENDRX, + _reserved14: [u8; 0x08], + #[doc = "0x11c - Data sent from TXD"] + pub events_txdrdy: EVENTS_TXDRDY, + #[doc = "0x120 - Last TX byte transmitted"] + pub events_endtx: EVENTS_ENDTX, + #[doc = "0x124 - Error detected"] + pub events_error: EVENTS_ERROR, + _reserved17: [u8; 0x1c], + #[doc = "0x144 - Receiver timeout"] + pub events_rxto: EVENTS_RXTO, + _reserved18: [u8; 0x04], + #[doc = "0x14c - UART receiver has started"] + pub events_rxstarted: EVENTS_RXSTARTED, + #[doc = "0x150 - UART transmitter has started"] + pub events_txstarted: EVENTS_TXSTARTED, + _reserved20: [u8; 0x04], + #[doc = "0x158 - Transmitter stopped"] + pub events_txstopped: EVENTS_TXSTOPPED, + _reserved21: [u8; 0x24], + #[doc = "0x180 - Publish configuration for event CTS"] + pub publish_cts: PUBLISH_CTS, + #[doc = "0x184 - Publish configuration for event NCTS"] + pub publish_ncts: PUBLISH_NCTS, + #[doc = "0x188 - Publish configuration for event RXDRDY"] + pub publish_rxdrdy: PUBLISH_RXDRDY, + _reserved24: [u8; 0x04], + #[doc = "0x190 - Publish configuration for event ENDRX"] + pub publish_endrx: PUBLISH_ENDRX, + _reserved25: [u8; 0x08], + #[doc = "0x19c - Publish configuration for event TXDRDY"] + pub publish_txdrdy: PUBLISH_TXDRDY, + #[doc = "0x1a0 - Publish configuration for event ENDTX"] + pub publish_endtx: PUBLISH_ENDTX, + #[doc = "0x1a4 - Publish configuration for event ERROR"] + pub publish_error: PUBLISH_ERROR, + _reserved28: [u8; 0x1c], + #[doc = "0x1c4 - Publish configuration for event RXTO"] + pub publish_rxto: PUBLISH_RXTO, + _reserved29: [u8; 0x04], + #[doc = "0x1cc - Publish configuration for event RXSTARTED"] + pub publish_rxstarted: PUBLISH_RXSTARTED, + #[doc = "0x1d0 - Publish configuration for event TXSTARTED"] + pub publish_txstarted: PUBLISH_TXSTARTED, + _reserved31: [u8; 0x04], + #[doc = "0x1d8 - Publish configuration for event TXSTOPPED"] + pub publish_txstopped: PUBLISH_TXSTOPPED, + _reserved32: [u8; 0x24], + #[doc = "0x200 - Shortcuts between local events and tasks"] + pub shorts: SHORTS, + _reserved33: [u8; 0xfc], + #[doc = "0x300 - Enable or disable interrupt"] + pub inten: INTEN, + #[doc = "0x304 - Enable interrupt"] + pub intenset: INTENSET, + #[doc = "0x308 - Disable interrupt"] + pub intenclr: INTENCLR, + _reserved36: [u8; 0x0174], + #[doc = "0x480 - Error source This register is read/write one to clear."] + pub errorsrc: ERRORSRC, + _reserved37: [u8; 0x7c], + #[doc = "0x500 - Enable UART"] + pub enable: ENABLE, + _reserved38: [u8; 0x04], + #[doc = "0x508..0x518 - Unspecified"] + pub psel: PSEL, + _reserved39: [u8; 0x0c], + #[doc = "0x524 - Baud rate. Accuracy depends on the HFCLK source selected."] + pub baudrate: BAUDRATE, + _reserved40: [u8; 0x0c], + #[doc = "0x534..0x540 - RXD EasyDMA channel"] + pub rxd: RXD, + _reserved41: [u8; 0x04], + #[doc = "0x544..0x550 - TXD EasyDMA channel"] + pub txd: TXD, + _reserved42: [u8; 0x1c], + #[doc = "0x56c - Configuration of parity and hardware flow control"] + pub config: CONFIG, +} +#[doc = "TASKS_STARTRX (w) register accessor: an alias for `Reg`"] +pub type TASKS_STARTRX = crate::Reg; +#[doc = "Start UART receiver"] +pub mod tasks_startrx; +#[doc = "TASKS_STOPRX (w) register accessor: an alias for `Reg`"] +pub type TASKS_STOPRX = crate::Reg; +#[doc = "Stop UART receiver"] +pub mod tasks_stoprx; +#[doc = "TASKS_STARTTX (w) register accessor: an alias for `Reg`"] +pub type TASKS_STARTTX = crate::Reg; +#[doc = "Start UART transmitter"] +pub mod tasks_starttx; +#[doc = "TASKS_STOPTX (w) register accessor: an alias for `Reg`"] +pub type TASKS_STOPTX = crate::Reg; +#[doc = "Stop UART transmitter"] +pub mod tasks_stoptx; +#[doc = "TASKS_FLUSHRX (w) register accessor: an alias for `Reg`"] +pub type TASKS_FLUSHRX = crate::Reg; +#[doc = "Flush RX FIFO into RX buffer"] +pub mod tasks_flushrx; +#[doc = "SUBSCRIBE_STARTRX (rw) register accessor: an alias for `Reg`"] +pub type SUBSCRIBE_STARTRX = crate::Reg; +#[doc = "Subscribe configuration for task STARTRX"] +pub mod subscribe_startrx; +#[doc = "SUBSCRIBE_STOPRX (rw) register accessor: an alias for `Reg`"] +pub type SUBSCRIBE_STOPRX = crate::Reg; +#[doc = "Subscribe configuration for task STOPRX"] +pub mod subscribe_stoprx; +#[doc = "SUBSCRIBE_STARTTX (rw) register accessor: an alias for `Reg`"] +pub type SUBSCRIBE_STARTTX = crate::Reg; +#[doc = "Subscribe configuration for task STARTTX"] +pub mod subscribe_starttx; +#[doc = "SUBSCRIBE_STOPTX (rw) register accessor: an alias for `Reg`"] +pub type SUBSCRIBE_STOPTX = crate::Reg; +#[doc = "Subscribe configuration for task STOPTX"] +pub mod subscribe_stoptx; +#[doc = "SUBSCRIBE_FLUSHRX (rw) register accessor: an alias for `Reg`"] +pub type SUBSCRIBE_FLUSHRX = crate::Reg; +#[doc = "Subscribe configuration for task FLUSHRX"] +pub mod subscribe_flushrx; +#[doc = "EVENTS_CTS (rw) register accessor: an alias for `Reg`"] +pub type EVENTS_CTS = crate::Reg; +#[doc = "CTS is activated (set low). Clear To Send."] +pub mod events_cts; +#[doc = "EVENTS_NCTS (rw) register accessor: an alias for `Reg`"] +pub type EVENTS_NCTS = crate::Reg; +#[doc = "CTS is deactivated (set high). Not Clear To Send."] +pub mod events_ncts; +#[doc = "EVENTS_RXDRDY (rw) register accessor: an alias for `Reg`"] +pub type EVENTS_RXDRDY = crate::Reg; +#[doc = "Data received in RXD (but potentially not yet transferred to Data RAM)"] +pub mod events_rxdrdy; +#[doc = "EVENTS_ENDRX (rw) register accessor: an alias for `Reg`"] +pub type EVENTS_ENDRX = crate::Reg; +#[doc = "Receive buffer is filled up"] +pub mod events_endrx; +#[doc = "EVENTS_TXDRDY (rw) register accessor: an alias for `Reg`"] +pub type EVENTS_TXDRDY = crate::Reg; +#[doc = "Data sent from TXD"] +pub mod events_txdrdy; +#[doc = "EVENTS_ENDTX (rw) register accessor: an alias for `Reg`"] +pub type EVENTS_ENDTX = crate::Reg; +#[doc = "Last TX byte transmitted"] +pub mod events_endtx; +#[doc = "EVENTS_ERROR (rw) register accessor: an alias for `Reg`"] +pub type EVENTS_ERROR = crate::Reg; +#[doc = "Error detected"] +pub mod events_error; +#[doc = "EVENTS_RXTO (rw) register accessor: an alias for `Reg`"] +pub type EVENTS_RXTO = crate::Reg; +#[doc = "Receiver timeout"] +pub mod events_rxto; +#[doc = "EVENTS_RXSTARTED (rw) register accessor: an alias for `Reg`"] +pub type EVENTS_RXSTARTED = crate::Reg; +#[doc = "UART receiver has started"] +pub mod events_rxstarted; +#[doc = "EVENTS_TXSTARTED (rw) register accessor: an alias for `Reg`"] +pub type EVENTS_TXSTARTED = crate::Reg; +#[doc = "UART transmitter has started"] +pub mod events_txstarted; +#[doc = "EVENTS_TXSTOPPED (rw) register accessor: an alias for `Reg`"] +pub type EVENTS_TXSTOPPED = crate::Reg; +#[doc = "Transmitter stopped"] +pub mod events_txstopped; +#[doc = "PUBLISH_CTS (rw) register accessor: an alias for `Reg`"] +pub type PUBLISH_CTS = crate::Reg; +#[doc = "Publish configuration for event CTS"] +pub mod publish_cts; +#[doc = "PUBLISH_NCTS (rw) register accessor: an alias for `Reg`"] +pub type PUBLISH_NCTS = crate::Reg; +#[doc = "Publish configuration for event NCTS"] +pub mod publish_ncts; +#[doc = "PUBLISH_RXDRDY (rw) register accessor: an alias for `Reg`"] +pub type PUBLISH_RXDRDY = crate::Reg; +#[doc = "Publish configuration for event RXDRDY"] +pub mod publish_rxdrdy; +#[doc = "PUBLISH_ENDRX (rw) register accessor: an alias for `Reg`"] +pub type PUBLISH_ENDRX = crate::Reg; +#[doc = "Publish configuration for event ENDRX"] +pub mod publish_endrx; +#[doc = "PUBLISH_TXDRDY (rw) register accessor: an alias for `Reg`"] +pub type PUBLISH_TXDRDY = crate::Reg; +#[doc = "Publish configuration for event TXDRDY"] +pub mod publish_txdrdy; +#[doc = "PUBLISH_ENDTX (rw) register accessor: an alias for `Reg`"] +pub type PUBLISH_ENDTX = crate::Reg; +#[doc = "Publish configuration for event ENDTX"] +pub mod publish_endtx; +#[doc = "PUBLISH_ERROR (rw) register accessor: an alias for `Reg`"] +pub type PUBLISH_ERROR = crate::Reg; +#[doc = "Publish configuration for event ERROR"] +pub mod publish_error; +#[doc = "PUBLISH_RXTO (rw) register accessor: an alias for `Reg`"] +pub type PUBLISH_RXTO = crate::Reg; +#[doc = "Publish configuration for event RXTO"] +pub mod publish_rxto; +#[doc = "PUBLISH_RXSTARTED (rw) register accessor: an alias for `Reg`"] +pub type PUBLISH_RXSTARTED = crate::Reg; +#[doc = "Publish configuration for event RXSTARTED"] +pub mod publish_rxstarted; +#[doc = "PUBLISH_TXSTARTED (rw) register accessor: an alias for `Reg`"] +pub type PUBLISH_TXSTARTED = crate::Reg; +#[doc = "Publish configuration for event TXSTARTED"] +pub mod publish_txstarted; +#[doc = "PUBLISH_TXSTOPPED (rw) register accessor: an alias for `Reg`"] +pub type PUBLISH_TXSTOPPED = crate::Reg; +#[doc = "Publish configuration for event TXSTOPPED"] +pub mod publish_txstopped; +#[doc = "SHORTS (rw) register accessor: an alias for `Reg`"] +pub type SHORTS = crate::Reg; +#[doc = "Shortcuts between local events and tasks"] +pub mod shorts; +#[doc = "INTEN (rw) register accessor: an alias for `Reg`"] +pub type INTEN = crate::Reg; +#[doc = "Enable or disable interrupt"] +pub mod inten; +#[doc = "INTENSET (rw) register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "Enable interrupt"] +pub mod intenset; +#[doc = "INTENCLR (rw) register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "Disable interrupt"] +pub mod intenclr; +#[doc = "ERRORSRC (rw) register accessor: an alias for `Reg`"] +pub type ERRORSRC = crate::Reg; +#[doc = "Error source This register is read/write one to clear."] +pub mod errorsrc; +#[doc = "ENABLE (rw) register accessor: an alias for `Reg`"] +pub type ENABLE = crate::Reg; +#[doc = "Enable UART"] +pub mod enable; +#[doc = "Unspecified"] +pub use psel::PSEL; +#[doc = r"Cluster"] +#[doc = "Unspecified"] +pub mod psel; +#[doc = "BAUDRATE (rw) register accessor: an alias for `Reg`"] +pub type BAUDRATE = crate::Reg; +#[doc = "Baud rate. Accuracy depends on the HFCLK source selected."] +pub mod baudrate; +#[doc = "RXD EasyDMA channel"] +pub use rxd::RXD; +#[doc = r"Cluster"] +#[doc = "RXD EasyDMA channel"] +pub mod rxd; +#[doc = "TXD EasyDMA channel"] +pub use txd::TXD; +#[doc = r"Cluster"] +#[doc = "TXD EasyDMA channel"] +pub mod txd; +#[doc = "CONFIG (rw) register accessor: an alias for `Reg`"] +pub type CONFIG = crate::Reg; +#[doc = "Configuration of parity and hardware flow control"] +pub mod config; diff --git a/pacs/nrf9120-pac/src/uarte0_ns/baudrate.rs b/pacs/nrf9120-pac/src/uarte0_ns/baudrate.rs new file mode 100644 index 00000000..95dbceb7 --- /dev/null +++ b/pacs/nrf9120-pac/src/uarte0_ns/baudrate.rs @@ -0,0 +1,337 @@ +#[doc = "Register `BAUDRATE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `BAUDRATE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BAUDRATE` reader - Baud rate"] +pub type BAUDRATE_R = crate::FieldReader; +#[doc = "Baud rate\n\nValue on reset: 67108864"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u32)] +pub enum BAUDRATE_A { + #[doc = "323584: 1200 baud (actual rate: 1205)"] + BAUD1200 = 323584, + #[doc = "643072: 2400 baud (actual rate: 2396)"] + BAUD2400 = 643072, + #[doc = "1290240: 4800 baud (actual rate: 4808)"] + BAUD4800 = 1290240, + #[doc = "2576384: 9600 baud (actual rate: 9598)"] + BAUD9600 = 2576384, + #[doc = "3862528: 14400 baud (actual rate: 14401)"] + BAUD14400 = 3862528, + #[doc = "5152768: 19200 baud (actual rate: 19208)"] + BAUD19200 = 5152768, + #[doc = "7716864: 28800 baud (actual rate: 28777)"] + BAUD28800 = 7716864, + #[doc = "8388608: 31250 baud"] + BAUD31250 = 8388608, + #[doc = "10289152: 38400 baud (actual rate: 38369)"] + BAUD38400 = 10289152, + #[doc = "15007744: 56000 baud (actual rate: 55944)"] + BAUD56000 = 15007744, + #[doc = "15400960: 57600 baud (actual rate: 57554)"] + BAUD57600 = 15400960, + #[doc = "20615168: 76800 baud (actual rate: 76923)"] + BAUD76800 = 20615168, + #[doc = "30801920: 115200 baud (actual rate: 115108)"] + BAUD115200 = 30801920, + #[doc = "61865984: 230400 baud (actual rate: 231884)"] + BAUD230400 = 61865984, + #[doc = "67108864: 250000 baud"] + BAUD250000 = 67108864, + #[doc = "121634816: 460800 baud (actual rate: 457143)"] + BAUD460800 = 121634816, + #[doc = "251658240: 921600 baud (actual rate: 941176)"] + BAUD921600 = 251658240, + #[doc = "268435456: 1 megabaud"] + BAUD1M = 268435456, +} +impl From for u32 { + #[inline(always)] + fn from(variant: BAUDRATE_A) -> Self { + variant as _ + } +} +impl BAUDRATE_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 323584 => Some(BAUDRATE_A::BAUD1200), + 643072 => Some(BAUDRATE_A::BAUD2400), + 1290240 => Some(BAUDRATE_A::BAUD4800), + 2576384 => Some(BAUDRATE_A::BAUD9600), + 3862528 => Some(BAUDRATE_A::BAUD14400), + 5152768 => Some(BAUDRATE_A::BAUD19200), + 7716864 => Some(BAUDRATE_A::BAUD28800), + 8388608 => Some(BAUDRATE_A::BAUD31250), + 10289152 => Some(BAUDRATE_A::BAUD38400), + 15007744 => Some(BAUDRATE_A::BAUD56000), + 15400960 => Some(BAUDRATE_A::BAUD57600), + 20615168 => Some(BAUDRATE_A::BAUD76800), + 30801920 => Some(BAUDRATE_A::BAUD115200), + 61865984 => Some(BAUDRATE_A::BAUD230400), + 67108864 => Some(BAUDRATE_A::BAUD250000), + 121634816 => Some(BAUDRATE_A::BAUD460800), + 251658240 => Some(BAUDRATE_A::BAUD921600), + 268435456 => Some(BAUDRATE_A::BAUD1M), + _ => None, + } + } + #[doc = "Checks if the value of the field is `BAUD1200`"] + #[inline(always)] + pub fn is_baud1200(&self) -> bool { + *self == BAUDRATE_A::BAUD1200 + } + #[doc = "Checks if the value of the field is `BAUD2400`"] + #[inline(always)] + pub fn is_baud2400(&self) -> bool { + *self == BAUDRATE_A::BAUD2400 + } + #[doc = "Checks if the value of the field is `BAUD4800`"] + #[inline(always)] + pub fn is_baud4800(&self) -> bool { + *self == BAUDRATE_A::BAUD4800 + } + #[doc = "Checks if the value of the field is `BAUD9600`"] + #[inline(always)] + pub fn is_baud9600(&self) -> bool { + *self == BAUDRATE_A::BAUD9600 + } + #[doc = "Checks if the value of the field is `BAUD14400`"] + #[inline(always)] + pub fn is_baud14400(&self) -> bool { + *self == BAUDRATE_A::BAUD14400 + } + #[doc = "Checks if the value of the field is `BAUD19200`"] + #[inline(always)] + pub fn is_baud19200(&self) -> bool { + *self == BAUDRATE_A::BAUD19200 + } + #[doc = "Checks if the value of the field is `BAUD28800`"] + #[inline(always)] + pub fn is_baud28800(&self) -> bool { + *self == BAUDRATE_A::BAUD28800 + } + #[doc = "Checks if the value of the field is `BAUD31250`"] + #[inline(always)] + pub fn is_baud31250(&self) -> bool { + *self == BAUDRATE_A::BAUD31250 + } + #[doc = "Checks if the value of the field is `BAUD38400`"] + #[inline(always)] + pub fn is_baud38400(&self) -> bool { + *self == BAUDRATE_A::BAUD38400 + } + #[doc = "Checks if the value of the field is `BAUD56000`"] + #[inline(always)] + pub fn is_baud56000(&self) -> bool { + *self == BAUDRATE_A::BAUD56000 + } + #[doc = "Checks if the value of the field is `BAUD57600`"] + #[inline(always)] + pub fn is_baud57600(&self) -> bool { + *self == BAUDRATE_A::BAUD57600 + } + #[doc = "Checks if the value of the field is `BAUD76800`"] + #[inline(always)] + pub fn is_baud76800(&self) -> bool { + *self == BAUDRATE_A::BAUD76800 + } + #[doc = "Checks if the value of the field is `BAUD115200`"] + #[inline(always)] + pub fn is_baud115200(&self) -> bool { + *self == BAUDRATE_A::BAUD115200 + } + #[doc = "Checks if the value of the field is `BAUD230400`"] + #[inline(always)] + pub fn is_baud230400(&self) -> bool { + *self == BAUDRATE_A::BAUD230400 + } + #[doc = "Checks if the value of the field is `BAUD250000`"] + #[inline(always)] + pub fn is_baud250000(&self) -> bool { + *self == BAUDRATE_A::BAUD250000 + } + #[doc = "Checks if the value of the field is `BAUD460800`"] + #[inline(always)] + pub fn is_baud460800(&self) -> bool { + *self == BAUDRATE_A::BAUD460800 + } + #[doc = "Checks if the value of the field is `BAUD921600`"] + #[inline(always)] + pub fn is_baud921600(&self) -> bool { + *self == BAUDRATE_A::BAUD921600 + } + #[doc = "Checks if the value of the field is `BAUD1M`"] + #[inline(always)] + pub fn is_baud1m(&self) -> bool { + *self == BAUDRATE_A::BAUD1M + } +} +#[doc = "Field `BAUDRATE` writer - Baud rate"] +pub type BAUDRATE_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, BAUDRATE_SPEC, u32, BAUDRATE_A, 32, O>; +impl<'a, const O: u8> BAUDRATE_W<'a, O> { + #[doc = "1200 baud (actual rate: 1205)"] + #[inline(always)] + pub fn baud1200(self) -> &'a mut W { + self.variant(BAUDRATE_A::BAUD1200) + } + #[doc = "2400 baud (actual rate: 2396)"] + #[inline(always)] + pub fn baud2400(self) -> &'a mut W { + self.variant(BAUDRATE_A::BAUD2400) + } + #[doc = "4800 baud (actual rate: 4808)"] + #[inline(always)] + pub fn baud4800(self) -> &'a mut W { + self.variant(BAUDRATE_A::BAUD4800) + } + #[doc = "9600 baud (actual rate: 9598)"] + #[inline(always)] + pub fn baud9600(self) -> &'a mut W { + self.variant(BAUDRATE_A::BAUD9600) + } + #[doc = "14400 baud (actual rate: 14401)"] + #[inline(always)] + pub fn baud14400(self) -> &'a mut W { + self.variant(BAUDRATE_A::BAUD14400) + } + #[doc = "19200 baud (actual rate: 19208)"] + #[inline(always)] + pub fn baud19200(self) -> &'a mut W { + self.variant(BAUDRATE_A::BAUD19200) + } + #[doc = "28800 baud (actual rate: 28777)"] + #[inline(always)] + pub fn baud28800(self) -> &'a mut W { + self.variant(BAUDRATE_A::BAUD28800) + } + #[doc = "31250 baud"] + #[inline(always)] + pub fn baud31250(self) -> &'a mut W { + self.variant(BAUDRATE_A::BAUD31250) + } + #[doc = "38400 baud (actual rate: 38369)"] + #[inline(always)] + pub fn baud38400(self) -> &'a mut W { + self.variant(BAUDRATE_A::BAUD38400) + } + #[doc = "56000 baud (actual rate: 55944)"] + #[inline(always)] + pub fn baud56000(self) -> &'a mut W { + self.variant(BAUDRATE_A::BAUD56000) + } + #[doc = "57600 baud (actual rate: 57554)"] + #[inline(always)] + pub fn baud57600(self) -> &'a mut W { + self.variant(BAUDRATE_A::BAUD57600) + } + #[doc = "76800 baud (actual rate: 76923)"] + #[inline(always)] + pub fn baud76800(self) -> &'a mut W { + self.variant(BAUDRATE_A::BAUD76800) + } + #[doc = "115200 baud (actual rate: 115108)"] + #[inline(always)] + pub fn baud115200(self) -> &'a mut W { + self.variant(BAUDRATE_A::BAUD115200) + } + #[doc = "230400 baud (actual rate: 231884)"] + #[inline(always)] + pub fn baud230400(self) -> &'a mut W { + self.variant(BAUDRATE_A::BAUD230400) + } + #[doc = "250000 baud"] + #[inline(always)] + pub fn baud250000(self) -> &'a mut W { + self.variant(BAUDRATE_A::BAUD250000) + } + #[doc = "460800 baud (actual rate: 457143)"] + #[inline(always)] + pub fn baud460800(self) -> &'a mut W { + self.variant(BAUDRATE_A::BAUD460800) + } + #[doc = "921600 baud (actual rate: 941176)"] + #[inline(always)] + pub fn baud921600(self) -> &'a mut W { + self.variant(BAUDRATE_A::BAUD921600) + } + #[doc = "1 megabaud"] + #[inline(always)] + pub fn baud1m(self) -> &'a mut W { + self.variant(BAUDRATE_A::BAUD1M) + } +} +impl R { + #[doc = "Bits 0:31 - Baud rate"] + #[inline(always)] + pub fn baudrate(&self) -> BAUDRATE_R { + BAUDRATE_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Baud rate"] + #[inline(always)] + pub fn baudrate(&mut self) -> BAUDRATE_W<0> { + BAUDRATE_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Baud rate. Accuracy depends on the HFCLK source selected.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [baudrate](index.html) module"] +pub struct BAUDRATE_SPEC; +impl crate::RegisterSpec for BAUDRATE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [baudrate::R](R) reader structure"] +impl crate::Readable for BAUDRATE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [baudrate::W](W) writer structure"] +impl crate::Writable for BAUDRATE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets BAUDRATE to value 0x0400_0000"] +impl crate::Resettable for BAUDRATE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x0400_0000 + } +} diff --git a/pacs/nrf9120-pac/src/uarte0_ns/config.rs b/pacs/nrf9120-pac/src/uarte0_ns/config.rs new file mode 100644 index 00000000..23908352 --- /dev/null +++ b/pacs/nrf9120-pac/src/uarte0_ns/config.rs @@ -0,0 +1,248 @@ +#[doc = "Register `CONFIG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CONFIG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `HWFC` reader - Hardware flow control"] +pub type HWFC_R = crate::BitReader; +#[doc = "Hardware flow control\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum HWFC_A { + #[doc = "0: Disabled"] + DISABLED = 0, + #[doc = "1: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: HWFC_A) -> Self { + variant as u8 != 0 + } +} +impl HWFC_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> HWFC_A { + match self.bits { + false => HWFC_A::DISABLED, + true => HWFC_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == HWFC_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == HWFC_A::ENABLED + } +} +#[doc = "Field `HWFC` writer - Hardware flow control"] +pub type HWFC_W<'a, const O: u8> = crate::BitWriter<'a, u32, CONFIG_SPEC, HWFC_A, O>; +impl<'a, const O: u8> HWFC_W<'a, O> { + #[doc = "Disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(HWFC_A::DISABLED) + } + #[doc = "Enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(HWFC_A::ENABLED) + } +} +#[doc = "Field `PARITY` reader - Parity"] +pub type PARITY_R = crate::FieldReader; +#[doc = "Parity\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum PARITY_A { + #[doc = "0: Exclude parity bit"] + EXCLUDED = 0, + #[doc = "7: Include even parity bit"] + INCLUDED = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PARITY_A) -> Self { + variant as _ + } +} +impl PARITY_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(PARITY_A::EXCLUDED), + 7 => Some(PARITY_A::INCLUDED), + _ => None, + } + } + #[doc = "Checks if the value of the field is `EXCLUDED`"] + #[inline(always)] + pub fn is_excluded(&self) -> bool { + *self == PARITY_A::EXCLUDED + } + #[doc = "Checks if the value of the field is `INCLUDED`"] + #[inline(always)] + pub fn is_included(&self) -> bool { + *self == PARITY_A::INCLUDED + } +} +#[doc = "Field `PARITY` writer - Parity"] +pub type PARITY_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CONFIG_SPEC, u8, PARITY_A, 3, O>; +impl<'a, const O: u8> PARITY_W<'a, O> { + #[doc = "Exclude parity bit"] + #[inline(always)] + pub fn excluded(self) -> &'a mut W { + self.variant(PARITY_A::EXCLUDED) + } + #[doc = "Include even parity bit"] + #[inline(always)] + pub fn included(self) -> &'a mut W { + self.variant(PARITY_A::INCLUDED) + } +} +#[doc = "Field `STOP` reader - Stop bits"] +pub type STOP_R = crate::BitReader; +#[doc = "Stop bits\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum STOP_A { + #[doc = "0: One stop bit"] + ONE = 0, + #[doc = "1: Two stop bits"] + TWO = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: STOP_A) -> Self { + variant as u8 != 0 + } +} +impl STOP_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> STOP_A { + match self.bits { + false => STOP_A::ONE, + true => STOP_A::TWO, + } + } + #[doc = "Checks if the value of the field is `ONE`"] + #[inline(always)] + pub fn is_one(&self) -> bool { + *self == STOP_A::ONE + } + #[doc = "Checks if the value of the field is `TWO`"] + #[inline(always)] + pub fn is_two(&self) -> bool { + *self == STOP_A::TWO + } +} +#[doc = "Field `STOP` writer - Stop bits"] +pub type STOP_W<'a, const O: u8> = crate::BitWriter<'a, u32, CONFIG_SPEC, STOP_A, O>; +impl<'a, const O: u8> STOP_W<'a, O> { + #[doc = "One stop bit"] + #[inline(always)] + pub fn one(self) -> &'a mut W { + self.variant(STOP_A::ONE) + } + #[doc = "Two stop bits"] + #[inline(always)] + pub fn two(self) -> &'a mut W { + self.variant(STOP_A::TWO) + } +} +impl R { + #[doc = "Bit 0 - Hardware flow control"] + #[inline(always)] + pub fn hwfc(&self) -> HWFC_R { + HWFC_R::new((self.bits & 1) != 0) + } + #[doc = "Bits 1:3 - Parity"] + #[inline(always)] + pub fn parity(&self) -> PARITY_R { + PARITY_R::new(((self.bits >> 1) & 7) as u8) + } + #[doc = "Bit 4 - Stop bits"] + #[inline(always)] + pub fn stop(&self) -> STOP_R { + STOP_R::new(((self.bits >> 4) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Hardware flow control"] + #[inline(always)] + pub fn hwfc(&mut self) -> HWFC_W<0> { + HWFC_W::new(self) + } + #[doc = "Bits 1:3 - Parity"] + #[inline(always)] + pub fn parity(&mut self) -> PARITY_W<1> { + PARITY_W::new(self) + } + #[doc = "Bit 4 - Stop bits"] + #[inline(always)] + pub fn stop(&mut self) -> STOP_W<4> { + STOP_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Configuration of parity and hardware flow control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [config](index.html) module"] +pub struct CONFIG_SPEC; +impl crate::RegisterSpec for CONFIG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [config::R](R) reader structure"] +impl crate::Readable for CONFIG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [config::W](W) writer structure"] +impl crate::Writable for CONFIG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CONFIG to value 0"] +impl crate::Resettable for CONFIG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/uarte0_ns/enable.rs b/pacs/nrf9120-pac/src/uarte0_ns/enable.rs new file mode 100644 index 00000000..0a8c5a91 --- /dev/null +++ b/pacs/nrf9120-pac/src/uarte0_ns/enable.rs @@ -0,0 +1,128 @@ +#[doc = "Register `ENABLE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `ENABLE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ENABLE` reader - Enable or disable UARTE"] +pub type ENABLE_R = crate::FieldReader; +#[doc = "Enable or disable UARTE\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum ENABLE_A { + #[doc = "0: Disable UARTE"] + DISABLED = 0, + #[doc = "8: Enable UARTE"] + ENABLED = 8, +} +impl From for u8 { + #[inline(always)] + fn from(variant: ENABLE_A) -> Self { + variant as _ + } +} +impl ENABLE_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(ENABLE_A::DISABLED), + 8 => Some(ENABLE_A::ENABLED), + _ => None, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == ENABLE_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == ENABLE_A::ENABLED + } +} +#[doc = "Field `ENABLE` writer - Enable or disable UARTE"] +pub type ENABLE_W<'a, const O: u8> = crate::FieldWriter<'a, u32, ENABLE_SPEC, u8, ENABLE_A, 4, O>; +impl<'a, const O: u8> ENABLE_W<'a, O> { + #[doc = "Disable UARTE"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(ENABLE_A::DISABLED) + } + #[doc = "Enable UARTE"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(ENABLE_A::ENABLED) + } +} +impl R { + #[doc = "Bits 0:3 - Enable or disable UARTE"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new((self.bits & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - Enable or disable UARTE"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W<0> { + ENABLE_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Enable UART\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [enable](index.html) module"] +pub struct ENABLE_SPEC; +impl crate::RegisterSpec for ENABLE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [enable::R](R) reader structure"] +impl crate::Readable for ENABLE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [enable::W](W) writer structure"] +impl crate::Writable for ENABLE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets ENABLE to value 0"] +impl crate::Resettable for ENABLE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/uarte0_ns/errorsrc.rs b/pacs/nrf9120-pac/src/uarte0_ns/errorsrc.rs new file mode 100644 index 00000000..7314b4c8 --- /dev/null +++ b/pacs/nrf9120-pac/src/uarte0_ns/errorsrc.rs @@ -0,0 +1,306 @@ +#[doc = "Register `ERRORSRC` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `ERRORSRC` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `OVERRUN` reader - Overrun error"] +pub type OVERRUN_R = crate::BitReader; +#[doc = "Overrun error\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum OVERRUN_A { + #[doc = "0: Read: error not present"] + NOT_PRESENT = 0, + #[doc = "1: Read: error present"] + PRESENT = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: OVERRUN_A) -> Self { + variant as u8 != 0 + } +} +impl OVERRUN_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> OVERRUN_A { + match self.bits { + false => OVERRUN_A::NOT_PRESENT, + true => OVERRUN_A::PRESENT, + } + } + #[doc = "Checks if the value of the field is `NOT_PRESENT`"] + #[inline(always)] + pub fn is_not_present(&self) -> bool { + *self == OVERRUN_A::NOT_PRESENT + } + #[doc = "Checks if the value of the field is `PRESENT`"] + #[inline(always)] + pub fn is_present(&self) -> bool { + *self == OVERRUN_A::PRESENT + } +} +#[doc = "Field `OVERRUN` writer - Overrun error"] +pub type OVERRUN_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, ERRORSRC_SPEC, OVERRUN_A, O>; +impl<'a, const O: u8> OVERRUN_W<'a, O> { + #[doc = "Read: error not present"] + #[inline(always)] + pub fn not_present(self) -> &'a mut W { + self.variant(OVERRUN_A::NOT_PRESENT) + } + #[doc = "Read: error present"] + #[inline(always)] + pub fn present(self) -> &'a mut W { + self.variant(OVERRUN_A::PRESENT) + } +} +#[doc = "Field `PARITY` reader - Parity error"] +pub type PARITY_R = crate::BitReader; +#[doc = "Parity error\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PARITY_A { + #[doc = "0: Read: error not present"] + NOT_PRESENT = 0, + #[doc = "1: Read: error present"] + PRESENT = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PARITY_A) -> Self { + variant as u8 != 0 + } +} +impl PARITY_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PARITY_A { + match self.bits { + false => PARITY_A::NOT_PRESENT, + true => PARITY_A::PRESENT, + } + } + #[doc = "Checks if the value of the field is `NOT_PRESENT`"] + #[inline(always)] + pub fn is_not_present(&self) -> bool { + *self == PARITY_A::NOT_PRESENT + } + #[doc = "Checks if the value of the field is `PRESENT`"] + #[inline(always)] + pub fn is_present(&self) -> bool { + *self == PARITY_A::PRESENT + } +} +#[doc = "Field `PARITY` writer - Parity error"] +pub type PARITY_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, ERRORSRC_SPEC, PARITY_A, O>; +impl<'a, const O: u8> PARITY_W<'a, O> { + #[doc = "Read: error not present"] + #[inline(always)] + pub fn not_present(self) -> &'a mut W { + self.variant(PARITY_A::NOT_PRESENT) + } + #[doc = "Read: error present"] + #[inline(always)] + pub fn present(self) -> &'a mut W { + self.variant(PARITY_A::PRESENT) + } +} +#[doc = "Field `FRAMING` reader - Framing error occurred"] +pub type FRAMING_R = crate::BitReader; +#[doc = "Framing error occurred\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum FRAMING_A { + #[doc = "0: Read: error not present"] + NOT_PRESENT = 0, + #[doc = "1: Read: error present"] + PRESENT = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: FRAMING_A) -> Self { + variant as u8 != 0 + } +} +impl FRAMING_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> FRAMING_A { + match self.bits { + false => FRAMING_A::NOT_PRESENT, + true => FRAMING_A::PRESENT, + } + } + #[doc = "Checks if the value of the field is `NOT_PRESENT`"] + #[inline(always)] + pub fn is_not_present(&self) -> bool { + *self == FRAMING_A::NOT_PRESENT + } + #[doc = "Checks if the value of the field is `PRESENT`"] + #[inline(always)] + pub fn is_present(&self) -> bool { + *self == FRAMING_A::PRESENT + } +} +#[doc = "Field `FRAMING` writer - Framing error occurred"] +pub type FRAMING_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, ERRORSRC_SPEC, FRAMING_A, O>; +impl<'a, const O: u8> FRAMING_W<'a, O> { + #[doc = "Read: error not present"] + #[inline(always)] + pub fn not_present(self) -> &'a mut W { + self.variant(FRAMING_A::NOT_PRESENT) + } + #[doc = "Read: error present"] + #[inline(always)] + pub fn present(self) -> &'a mut W { + self.variant(FRAMING_A::PRESENT) + } +} +#[doc = "Field `BREAK` reader - Break condition"] +pub type BREAK_R = crate::BitReader; +#[doc = "Break condition\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum BREAK_A { + #[doc = "0: Read: error not present"] + NOT_PRESENT = 0, + #[doc = "1: Read: error present"] + PRESENT = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: BREAK_A) -> Self { + variant as u8 != 0 + } +} +impl BREAK_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> BREAK_A { + match self.bits { + false => BREAK_A::NOT_PRESENT, + true => BREAK_A::PRESENT, + } + } + #[doc = "Checks if the value of the field is `NOT_PRESENT`"] + #[inline(always)] + pub fn is_not_present(&self) -> bool { + *self == BREAK_A::NOT_PRESENT + } + #[doc = "Checks if the value of the field is `PRESENT`"] + #[inline(always)] + pub fn is_present(&self) -> bool { + *self == BREAK_A::PRESENT + } +} +#[doc = "Field `BREAK` writer - Break condition"] +pub type BREAK_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, ERRORSRC_SPEC, BREAK_A, O>; +impl<'a, const O: u8> BREAK_W<'a, O> { + #[doc = "Read: error not present"] + #[inline(always)] + pub fn not_present(self) -> &'a mut W { + self.variant(BREAK_A::NOT_PRESENT) + } + #[doc = "Read: error present"] + #[inline(always)] + pub fn present(self) -> &'a mut W { + self.variant(BREAK_A::PRESENT) + } +} +impl R { + #[doc = "Bit 0 - Overrun error"] + #[inline(always)] + pub fn overrun(&self) -> OVERRUN_R { + OVERRUN_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Parity error"] + #[inline(always)] + pub fn parity(&self) -> PARITY_R { + PARITY_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Framing error occurred"] + #[inline(always)] + pub fn framing(&self) -> FRAMING_R { + FRAMING_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Break condition"] + #[inline(always)] + pub fn break_(&self) -> BREAK_R { + BREAK_R::new(((self.bits >> 3) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Overrun error"] + #[inline(always)] + pub fn overrun(&mut self) -> OVERRUN_W<0> { + OVERRUN_W::new(self) + } + #[doc = "Bit 1 - Parity error"] + #[inline(always)] + pub fn parity(&mut self) -> PARITY_W<1> { + PARITY_W::new(self) + } + #[doc = "Bit 2 - Framing error occurred"] + #[inline(always)] + pub fn framing(&mut self) -> FRAMING_W<2> { + FRAMING_W::new(self) + } + #[doc = "Bit 3 - Break condition"] + #[inline(always)] + pub fn break_(&mut self) -> BREAK_W<3> { + BREAK_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Error source This register is read/write one to clear.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [errorsrc](index.html) module"] +pub struct ERRORSRC_SPEC; +impl crate::RegisterSpec for ERRORSRC_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [errorsrc::R](R) reader structure"] +impl crate::Readable for ERRORSRC_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [errorsrc::W](W) writer structure"] +impl crate::Writable for ERRORSRC_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets ERRORSRC to value 0"] +impl crate::Resettable for ERRORSRC_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/uarte0_ns/events_cts.rs b/pacs/nrf9120-pac/src/uarte0_ns/events_cts.rs new file mode 100644 index 00000000..acfdfe86 --- /dev/null +++ b/pacs/nrf9120-pac/src/uarte0_ns/events_cts.rs @@ -0,0 +1,127 @@ +#[doc = "Register `EVENTS_CTS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVENTS_CTS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `EVENTS_CTS` reader - CTS is activated (set low). Clear To Send."] +pub type EVENTS_CTS_R = crate::BitReader; +#[doc = "CTS is activated (set low). Clear To Send.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum EVENTS_CTS_A { + #[doc = "0: Event not generated"] + NOT_GENERATED = 0, + #[doc = "1: Event generated"] + GENERATED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: EVENTS_CTS_A) -> Self { + variant as u8 != 0 + } +} +impl EVENTS_CTS_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EVENTS_CTS_A { + match self.bits { + false => EVENTS_CTS_A::NOT_GENERATED, + true => EVENTS_CTS_A::GENERATED, + } + } + #[doc = "Checks if the value of the field is `NOT_GENERATED`"] + #[inline(always)] + pub fn is_not_generated(&self) -> bool { + *self == EVENTS_CTS_A::NOT_GENERATED + } + #[doc = "Checks if the value of the field is `GENERATED`"] + #[inline(always)] + pub fn is_generated(&self) -> bool { + *self == EVENTS_CTS_A::GENERATED + } +} +#[doc = "Field `EVENTS_CTS` writer - CTS is activated (set low). Clear To Send."] +pub type EVENTS_CTS_W<'a, const O: u8> = + crate::BitWriter<'a, u32, EVENTS_CTS_SPEC, EVENTS_CTS_A, O>; +impl<'a, const O: u8> EVENTS_CTS_W<'a, O> { + #[doc = "Event not generated"] + #[inline(always)] + pub fn not_generated(self) -> &'a mut W { + self.variant(EVENTS_CTS_A::NOT_GENERATED) + } + #[doc = "Event generated"] + #[inline(always)] + pub fn generated(self) -> &'a mut W { + self.variant(EVENTS_CTS_A::GENERATED) + } +} +impl R { + #[doc = "Bit 0 - CTS is activated (set low). Clear To Send."] + #[inline(always)] + pub fn events_cts(&self) -> EVENTS_CTS_R { + EVENTS_CTS_R::new((self.bits & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - CTS is activated (set low). Clear To Send."] + #[inline(always)] + pub fn events_cts(&mut self) -> EVENTS_CTS_W<0> { + EVENTS_CTS_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "CTS is activated (set low). Clear To Send.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [events_cts](index.html) module"] +pub struct EVENTS_CTS_SPEC; +impl crate::RegisterSpec for EVENTS_CTS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [events_cts::R](R) reader structure"] +impl crate::Readable for EVENTS_CTS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [events_cts::W](W) writer structure"] +impl crate::Writable for EVENTS_CTS_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EVENTS_CTS to value 0"] +impl crate::Resettable for EVENTS_CTS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/uarte0_ns/events_endrx.rs b/pacs/nrf9120-pac/src/uarte0_ns/events_endrx.rs new file mode 100644 index 00000000..836e4c24 --- /dev/null +++ b/pacs/nrf9120-pac/src/uarte0_ns/events_endrx.rs @@ -0,0 +1,127 @@ +#[doc = "Register `EVENTS_ENDRX` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVENTS_ENDRX` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `EVENTS_ENDRX` reader - Receive buffer is filled up"] +pub type EVENTS_ENDRX_R = crate::BitReader; +#[doc = "Receive buffer is filled up\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum EVENTS_ENDRX_A { + #[doc = "0: Event not generated"] + NOT_GENERATED = 0, + #[doc = "1: Event generated"] + GENERATED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: EVENTS_ENDRX_A) -> Self { + variant as u8 != 0 + } +} +impl EVENTS_ENDRX_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EVENTS_ENDRX_A { + match self.bits { + false => EVENTS_ENDRX_A::NOT_GENERATED, + true => EVENTS_ENDRX_A::GENERATED, + } + } + #[doc = "Checks if the value of the field is `NOT_GENERATED`"] + #[inline(always)] + pub fn is_not_generated(&self) -> bool { + *self == EVENTS_ENDRX_A::NOT_GENERATED + } + #[doc = "Checks if the value of the field is `GENERATED`"] + #[inline(always)] + pub fn is_generated(&self) -> bool { + *self == EVENTS_ENDRX_A::GENERATED + } +} +#[doc = "Field `EVENTS_ENDRX` writer - Receive buffer is filled up"] +pub type EVENTS_ENDRX_W<'a, const O: u8> = + crate::BitWriter<'a, u32, EVENTS_ENDRX_SPEC, EVENTS_ENDRX_A, O>; +impl<'a, const O: u8> EVENTS_ENDRX_W<'a, O> { + #[doc = "Event not generated"] + #[inline(always)] + pub fn not_generated(self) -> &'a mut W { + self.variant(EVENTS_ENDRX_A::NOT_GENERATED) + } + #[doc = "Event generated"] + #[inline(always)] + pub fn generated(self) -> &'a mut W { + self.variant(EVENTS_ENDRX_A::GENERATED) + } +} +impl R { + #[doc = "Bit 0 - Receive buffer is filled up"] + #[inline(always)] + pub fn events_endrx(&self) -> EVENTS_ENDRX_R { + EVENTS_ENDRX_R::new((self.bits & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Receive buffer is filled up"] + #[inline(always)] + pub fn events_endrx(&mut self) -> EVENTS_ENDRX_W<0> { + EVENTS_ENDRX_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Receive buffer is filled up\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [events_endrx](index.html) module"] +pub struct EVENTS_ENDRX_SPEC; +impl crate::RegisterSpec for EVENTS_ENDRX_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [events_endrx::R](R) reader structure"] +impl crate::Readable for EVENTS_ENDRX_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [events_endrx::W](W) writer structure"] +impl crate::Writable for EVENTS_ENDRX_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EVENTS_ENDRX to value 0"] +impl crate::Resettable for EVENTS_ENDRX_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/uarte0_ns/events_endtx.rs b/pacs/nrf9120-pac/src/uarte0_ns/events_endtx.rs new file mode 100644 index 00000000..02cf190c --- /dev/null +++ b/pacs/nrf9120-pac/src/uarte0_ns/events_endtx.rs @@ -0,0 +1,127 @@ +#[doc = "Register `EVENTS_ENDTX` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVENTS_ENDTX` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `EVENTS_ENDTX` reader - Last TX byte transmitted"] +pub type EVENTS_ENDTX_R = crate::BitReader; +#[doc = "Last TX byte transmitted\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum EVENTS_ENDTX_A { + #[doc = "0: Event not generated"] + NOT_GENERATED = 0, + #[doc = "1: Event generated"] + GENERATED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: EVENTS_ENDTX_A) -> Self { + variant as u8 != 0 + } +} +impl EVENTS_ENDTX_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EVENTS_ENDTX_A { + match self.bits { + false => EVENTS_ENDTX_A::NOT_GENERATED, + true => EVENTS_ENDTX_A::GENERATED, + } + } + #[doc = "Checks if the value of the field is `NOT_GENERATED`"] + #[inline(always)] + pub fn is_not_generated(&self) -> bool { + *self == EVENTS_ENDTX_A::NOT_GENERATED + } + #[doc = "Checks if the value of the field is `GENERATED`"] + #[inline(always)] + pub fn is_generated(&self) -> bool { + *self == EVENTS_ENDTX_A::GENERATED + } +} +#[doc = "Field `EVENTS_ENDTX` writer - Last TX byte transmitted"] +pub type EVENTS_ENDTX_W<'a, const O: u8> = + crate::BitWriter<'a, u32, EVENTS_ENDTX_SPEC, EVENTS_ENDTX_A, O>; +impl<'a, const O: u8> EVENTS_ENDTX_W<'a, O> { + #[doc = "Event not generated"] + #[inline(always)] + pub fn not_generated(self) -> &'a mut W { + self.variant(EVENTS_ENDTX_A::NOT_GENERATED) + } + #[doc = "Event generated"] + #[inline(always)] + pub fn generated(self) -> &'a mut W { + self.variant(EVENTS_ENDTX_A::GENERATED) + } +} +impl R { + #[doc = "Bit 0 - Last TX byte transmitted"] + #[inline(always)] + pub fn events_endtx(&self) -> EVENTS_ENDTX_R { + EVENTS_ENDTX_R::new((self.bits & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Last TX byte transmitted"] + #[inline(always)] + pub fn events_endtx(&mut self) -> EVENTS_ENDTX_W<0> { + EVENTS_ENDTX_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Last TX byte transmitted\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [events_endtx](index.html) module"] +pub struct EVENTS_ENDTX_SPEC; +impl crate::RegisterSpec for EVENTS_ENDTX_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [events_endtx::R](R) reader structure"] +impl crate::Readable for EVENTS_ENDTX_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [events_endtx::W](W) writer structure"] +impl crate::Writable for EVENTS_ENDTX_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EVENTS_ENDTX to value 0"] +impl crate::Resettable for EVENTS_ENDTX_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/uarte0_ns/events_error.rs b/pacs/nrf9120-pac/src/uarte0_ns/events_error.rs new file mode 100644 index 00000000..9c90ac74 --- /dev/null +++ b/pacs/nrf9120-pac/src/uarte0_ns/events_error.rs @@ -0,0 +1,127 @@ +#[doc = "Register `EVENTS_ERROR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVENTS_ERROR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `EVENTS_ERROR` reader - Error detected"] +pub type EVENTS_ERROR_R = crate::BitReader; +#[doc = "Error detected\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum EVENTS_ERROR_A { + #[doc = "0: Event not generated"] + NOT_GENERATED = 0, + #[doc = "1: Event generated"] + GENERATED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: EVENTS_ERROR_A) -> Self { + variant as u8 != 0 + } +} +impl EVENTS_ERROR_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EVENTS_ERROR_A { + match self.bits { + false => EVENTS_ERROR_A::NOT_GENERATED, + true => EVENTS_ERROR_A::GENERATED, + } + } + #[doc = "Checks if the value of the field is `NOT_GENERATED`"] + #[inline(always)] + pub fn is_not_generated(&self) -> bool { + *self == EVENTS_ERROR_A::NOT_GENERATED + } + #[doc = "Checks if the value of the field is `GENERATED`"] + #[inline(always)] + pub fn is_generated(&self) -> bool { + *self == EVENTS_ERROR_A::GENERATED + } +} +#[doc = "Field `EVENTS_ERROR` writer - Error detected"] +pub type EVENTS_ERROR_W<'a, const O: u8> = + crate::BitWriter<'a, u32, EVENTS_ERROR_SPEC, EVENTS_ERROR_A, O>; +impl<'a, const O: u8> EVENTS_ERROR_W<'a, O> { + #[doc = "Event not generated"] + #[inline(always)] + pub fn not_generated(self) -> &'a mut W { + self.variant(EVENTS_ERROR_A::NOT_GENERATED) + } + #[doc = "Event generated"] + #[inline(always)] + pub fn generated(self) -> &'a mut W { + self.variant(EVENTS_ERROR_A::GENERATED) + } +} +impl R { + #[doc = "Bit 0 - Error detected"] + #[inline(always)] + pub fn events_error(&self) -> EVENTS_ERROR_R { + EVENTS_ERROR_R::new((self.bits & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Error detected"] + #[inline(always)] + pub fn events_error(&mut self) -> EVENTS_ERROR_W<0> { + EVENTS_ERROR_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Error detected\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [events_error](index.html) module"] +pub struct EVENTS_ERROR_SPEC; +impl crate::RegisterSpec for EVENTS_ERROR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [events_error::R](R) reader structure"] +impl crate::Readable for EVENTS_ERROR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [events_error::W](W) writer structure"] +impl crate::Writable for EVENTS_ERROR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EVENTS_ERROR to value 0"] +impl crate::Resettable for EVENTS_ERROR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/uarte0_ns/events_ncts.rs b/pacs/nrf9120-pac/src/uarte0_ns/events_ncts.rs new file mode 100644 index 00000000..412d872c --- /dev/null +++ b/pacs/nrf9120-pac/src/uarte0_ns/events_ncts.rs @@ -0,0 +1,127 @@ +#[doc = "Register `EVENTS_NCTS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVENTS_NCTS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `EVENTS_NCTS` reader - CTS is deactivated (set high). Not Clear To Send."] +pub type EVENTS_NCTS_R = crate::BitReader; +#[doc = "CTS is deactivated (set high). Not Clear To Send.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum EVENTS_NCTS_A { + #[doc = "0: Event not generated"] + NOT_GENERATED = 0, + #[doc = "1: Event generated"] + GENERATED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: EVENTS_NCTS_A) -> Self { + variant as u8 != 0 + } +} +impl EVENTS_NCTS_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EVENTS_NCTS_A { + match self.bits { + false => EVENTS_NCTS_A::NOT_GENERATED, + true => EVENTS_NCTS_A::GENERATED, + } + } + #[doc = "Checks if the value of the field is `NOT_GENERATED`"] + #[inline(always)] + pub fn is_not_generated(&self) -> bool { + *self == EVENTS_NCTS_A::NOT_GENERATED + } + #[doc = "Checks if the value of the field is `GENERATED`"] + #[inline(always)] + pub fn is_generated(&self) -> bool { + *self == EVENTS_NCTS_A::GENERATED + } +} +#[doc = "Field `EVENTS_NCTS` writer - CTS is deactivated (set high). Not Clear To Send."] +pub type EVENTS_NCTS_W<'a, const O: u8> = + crate::BitWriter<'a, u32, EVENTS_NCTS_SPEC, EVENTS_NCTS_A, O>; +impl<'a, const O: u8> EVENTS_NCTS_W<'a, O> { + #[doc = "Event not generated"] + #[inline(always)] + pub fn not_generated(self) -> &'a mut W { + self.variant(EVENTS_NCTS_A::NOT_GENERATED) + } + #[doc = "Event generated"] + #[inline(always)] + pub fn generated(self) -> &'a mut W { + self.variant(EVENTS_NCTS_A::GENERATED) + } +} +impl R { + #[doc = "Bit 0 - CTS is deactivated (set high). Not Clear To Send."] + #[inline(always)] + pub fn events_ncts(&self) -> EVENTS_NCTS_R { + EVENTS_NCTS_R::new((self.bits & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - CTS is deactivated (set high). Not Clear To Send."] + #[inline(always)] + pub fn events_ncts(&mut self) -> EVENTS_NCTS_W<0> { + EVENTS_NCTS_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "CTS is deactivated (set high). Not Clear To Send.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [events_ncts](index.html) module"] +pub struct EVENTS_NCTS_SPEC; +impl crate::RegisterSpec for EVENTS_NCTS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [events_ncts::R](R) reader structure"] +impl crate::Readable for EVENTS_NCTS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [events_ncts::W](W) writer structure"] +impl crate::Writable for EVENTS_NCTS_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EVENTS_NCTS to value 0"] +impl crate::Resettable for EVENTS_NCTS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/uarte0_ns/events_rxdrdy.rs b/pacs/nrf9120-pac/src/uarte0_ns/events_rxdrdy.rs new file mode 100644 index 00000000..2710959c --- /dev/null +++ b/pacs/nrf9120-pac/src/uarte0_ns/events_rxdrdy.rs @@ -0,0 +1,127 @@ +#[doc = "Register `EVENTS_RXDRDY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVENTS_RXDRDY` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `EVENTS_RXDRDY` reader - Data received in RXD (but potentially not yet transferred to Data RAM)"] +pub type EVENTS_RXDRDY_R = crate::BitReader; +#[doc = "Data received in RXD (but potentially not yet transferred to Data RAM)\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum EVENTS_RXDRDY_A { + #[doc = "0: Event not generated"] + NOT_GENERATED = 0, + #[doc = "1: Event generated"] + GENERATED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: EVENTS_RXDRDY_A) -> Self { + variant as u8 != 0 + } +} +impl EVENTS_RXDRDY_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EVENTS_RXDRDY_A { + match self.bits { + false => EVENTS_RXDRDY_A::NOT_GENERATED, + true => EVENTS_RXDRDY_A::GENERATED, + } + } + #[doc = "Checks if the value of the field is `NOT_GENERATED`"] + #[inline(always)] + pub fn is_not_generated(&self) -> bool { + *self == EVENTS_RXDRDY_A::NOT_GENERATED + } + #[doc = "Checks if the value of the field is `GENERATED`"] + #[inline(always)] + pub fn is_generated(&self) -> bool { + *self == EVENTS_RXDRDY_A::GENERATED + } +} +#[doc = "Field `EVENTS_RXDRDY` writer - Data received in RXD (but potentially not yet transferred to Data RAM)"] +pub type EVENTS_RXDRDY_W<'a, const O: u8> = + crate::BitWriter<'a, u32, EVENTS_RXDRDY_SPEC, EVENTS_RXDRDY_A, O>; +impl<'a, const O: u8> EVENTS_RXDRDY_W<'a, O> { + #[doc = "Event not generated"] + #[inline(always)] + pub fn not_generated(self) -> &'a mut W { + self.variant(EVENTS_RXDRDY_A::NOT_GENERATED) + } + #[doc = "Event generated"] + #[inline(always)] + pub fn generated(self) -> &'a mut W { + self.variant(EVENTS_RXDRDY_A::GENERATED) + } +} +impl R { + #[doc = "Bit 0 - Data received in RXD (but potentially not yet transferred to Data RAM)"] + #[inline(always)] + pub fn events_rxdrdy(&self) -> EVENTS_RXDRDY_R { + EVENTS_RXDRDY_R::new((self.bits & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Data received in RXD (but potentially not yet transferred to Data RAM)"] + #[inline(always)] + pub fn events_rxdrdy(&mut self) -> EVENTS_RXDRDY_W<0> { + EVENTS_RXDRDY_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Data received in RXD (but potentially not yet transferred to Data RAM)\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [events_rxdrdy](index.html) module"] +pub struct EVENTS_RXDRDY_SPEC; +impl crate::RegisterSpec for EVENTS_RXDRDY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [events_rxdrdy::R](R) reader structure"] +impl crate::Readable for EVENTS_RXDRDY_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [events_rxdrdy::W](W) writer structure"] +impl crate::Writable for EVENTS_RXDRDY_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EVENTS_RXDRDY to value 0"] +impl crate::Resettable for EVENTS_RXDRDY_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/uarte0_ns/events_rxstarted.rs b/pacs/nrf9120-pac/src/uarte0_ns/events_rxstarted.rs new file mode 100644 index 00000000..a3e787d6 --- /dev/null +++ b/pacs/nrf9120-pac/src/uarte0_ns/events_rxstarted.rs @@ -0,0 +1,127 @@ +#[doc = "Register `EVENTS_RXSTARTED` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVENTS_RXSTARTED` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `EVENTS_RXSTARTED` reader - UART receiver has started"] +pub type EVENTS_RXSTARTED_R = crate::BitReader; +#[doc = "UART receiver has started\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum EVENTS_RXSTARTED_A { + #[doc = "0: Event not generated"] + NOT_GENERATED = 0, + #[doc = "1: Event generated"] + GENERATED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: EVENTS_RXSTARTED_A) -> Self { + variant as u8 != 0 + } +} +impl EVENTS_RXSTARTED_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EVENTS_RXSTARTED_A { + match self.bits { + false => EVENTS_RXSTARTED_A::NOT_GENERATED, + true => EVENTS_RXSTARTED_A::GENERATED, + } + } + #[doc = "Checks if the value of the field is `NOT_GENERATED`"] + #[inline(always)] + pub fn is_not_generated(&self) -> bool { + *self == EVENTS_RXSTARTED_A::NOT_GENERATED + } + #[doc = "Checks if the value of the field is `GENERATED`"] + #[inline(always)] + pub fn is_generated(&self) -> bool { + *self == EVENTS_RXSTARTED_A::GENERATED + } +} +#[doc = "Field `EVENTS_RXSTARTED` writer - UART receiver has started"] +pub type EVENTS_RXSTARTED_W<'a, const O: u8> = + crate::BitWriter<'a, u32, EVENTS_RXSTARTED_SPEC, EVENTS_RXSTARTED_A, O>; +impl<'a, const O: u8> EVENTS_RXSTARTED_W<'a, O> { + #[doc = "Event not generated"] + #[inline(always)] + pub fn not_generated(self) -> &'a mut W { + self.variant(EVENTS_RXSTARTED_A::NOT_GENERATED) + } + #[doc = "Event generated"] + #[inline(always)] + pub fn generated(self) -> &'a mut W { + self.variant(EVENTS_RXSTARTED_A::GENERATED) + } +} +impl R { + #[doc = "Bit 0 - UART receiver has started"] + #[inline(always)] + pub fn events_rxstarted(&self) -> EVENTS_RXSTARTED_R { + EVENTS_RXSTARTED_R::new((self.bits & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - UART receiver has started"] + #[inline(always)] + pub fn events_rxstarted(&mut self) -> EVENTS_RXSTARTED_W<0> { + EVENTS_RXSTARTED_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "UART receiver has started\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [events_rxstarted](index.html) module"] +pub struct EVENTS_RXSTARTED_SPEC; +impl crate::RegisterSpec for EVENTS_RXSTARTED_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [events_rxstarted::R](R) reader structure"] +impl crate::Readable for EVENTS_RXSTARTED_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [events_rxstarted::W](W) writer structure"] +impl crate::Writable for EVENTS_RXSTARTED_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EVENTS_RXSTARTED to value 0"] +impl crate::Resettable for EVENTS_RXSTARTED_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/uarte0_ns/events_rxto.rs b/pacs/nrf9120-pac/src/uarte0_ns/events_rxto.rs new file mode 100644 index 00000000..a661e8ff --- /dev/null +++ b/pacs/nrf9120-pac/src/uarte0_ns/events_rxto.rs @@ -0,0 +1,127 @@ +#[doc = "Register `EVENTS_RXTO` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVENTS_RXTO` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `EVENTS_RXTO` reader - Receiver timeout"] +pub type EVENTS_RXTO_R = crate::BitReader; +#[doc = "Receiver timeout\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum EVENTS_RXTO_A { + #[doc = "0: Event not generated"] + NOT_GENERATED = 0, + #[doc = "1: Event generated"] + GENERATED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: EVENTS_RXTO_A) -> Self { + variant as u8 != 0 + } +} +impl EVENTS_RXTO_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EVENTS_RXTO_A { + match self.bits { + false => EVENTS_RXTO_A::NOT_GENERATED, + true => EVENTS_RXTO_A::GENERATED, + } + } + #[doc = "Checks if the value of the field is `NOT_GENERATED`"] + #[inline(always)] + pub fn is_not_generated(&self) -> bool { + *self == EVENTS_RXTO_A::NOT_GENERATED + } + #[doc = "Checks if the value of the field is `GENERATED`"] + #[inline(always)] + pub fn is_generated(&self) -> bool { + *self == EVENTS_RXTO_A::GENERATED + } +} +#[doc = "Field `EVENTS_RXTO` writer - Receiver timeout"] +pub type EVENTS_RXTO_W<'a, const O: u8> = + crate::BitWriter<'a, u32, EVENTS_RXTO_SPEC, EVENTS_RXTO_A, O>; +impl<'a, const O: u8> EVENTS_RXTO_W<'a, O> { + #[doc = "Event not generated"] + #[inline(always)] + pub fn not_generated(self) -> &'a mut W { + self.variant(EVENTS_RXTO_A::NOT_GENERATED) + } + #[doc = "Event generated"] + #[inline(always)] + pub fn generated(self) -> &'a mut W { + self.variant(EVENTS_RXTO_A::GENERATED) + } +} +impl R { + #[doc = "Bit 0 - Receiver timeout"] + #[inline(always)] + pub fn events_rxto(&self) -> EVENTS_RXTO_R { + EVENTS_RXTO_R::new((self.bits & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Receiver timeout"] + #[inline(always)] + pub fn events_rxto(&mut self) -> EVENTS_RXTO_W<0> { + EVENTS_RXTO_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Receiver timeout\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [events_rxto](index.html) module"] +pub struct EVENTS_RXTO_SPEC; +impl crate::RegisterSpec for EVENTS_RXTO_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [events_rxto::R](R) reader structure"] +impl crate::Readable for EVENTS_RXTO_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [events_rxto::W](W) writer structure"] +impl crate::Writable for EVENTS_RXTO_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EVENTS_RXTO to value 0"] +impl crate::Resettable for EVENTS_RXTO_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/uarte0_ns/events_txdrdy.rs b/pacs/nrf9120-pac/src/uarte0_ns/events_txdrdy.rs new file mode 100644 index 00000000..82ebc72c --- /dev/null +++ b/pacs/nrf9120-pac/src/uarte0_ns/events_txdrdy.rs @@ -0,0 +1,127 @@ +#[doc = "Register `EVENTS_TXDRDY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVENTS_TXDRDY` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `EVENTS_TXDRDY` reader - Data sent from TXD"] +pub type EVENTS_TXDRDY_R = crate::BitReader; +#[doc = "Data sent from TXD\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum EVENTS_TXDRDY_A { + #[doc = "0: Event not generated"] + NOT_GENERATED = 0, + #[doc = "1: Event generated"] + GENERATED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: EVENTS_TXDRDY_A) -> Self { + variant as u8 != 0 + } +} +impl EVENTS_TXDRDY_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EVENTS_TXDRDY_A { + match self.bits { + false => EVENTS_TXDRDY_A::NOT_GENERATED, + true => EVENTS_TXDRDY_A::GENERATED, + } + } + #[doc = "Checks if the value of the field is `NOT_GENERATED`"] + #[inline(always)] + pub fn is_not_generated(&self) -> bool { + *self == EVENTS_TXDRDY_A::NOT_GENERATED + } + #[doc = "Checks if the value of the field is `GENERATED`"] + #[inline(always)] + pub fn is_generated(&self) -> bool { + *self == EVENTS_TXDRDY_A::GENERATED + } +} +#[doc = "Field `EVENTS_TXDRDY` writer - Data sent from TXD"] +pub type EVENTS_TXDRDY_W<'a, const O: u8> = + crate::BitWriter<'a, u32, EVENTS_TXDRDY_SPEC, EVENTS_TXDRDY_A, O>; +impl<'a, const O: u8> EVENTS_TXDRDY_W<'a, O> { + #[doc = "Event not generated"] + #[inline(always)] + pub fn not_generated(self) -> &'a mut W { + self.variant(EVENTS_TXDRDY_A::NOT_GENERATED) + } + #[doc = "Event generated"] + #[inline(always)] + pub fn generated(self) -> &'a mut W { + self.variant(EVENTS_TXDRDY_A::GENERATED) + } +} +impl R { + #[doc = "Bit 0 - Data sent from TXD"] + #[inline(always)] + pub fn events_txdrdy(&self) -> EVENTS_TXDRDY_R { + EVENTS_TXDRDY_R::new((self.bits & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Data sent from TXD"] + #[inline(always)] + pub fn events_txdrdy(&mut self) -> EVENTS_TXDRDY_W<0> { + EVENTS_TXDRDY_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Data sent from TXD\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [events_txdrdy](index.html) module"] +pub struct EVENTS_TXDRDY_SPEC; +impl crate::RegisterSpec for EVENTS_TXDRDY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [events_txdrdy::R](R) reader structure"] +impl crate::Readable for EVENTS_TXDRDY_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [events_txdrdy::W](W) writer structure"] +impl crate::Writable for EVENTS_TXDRDY_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EVENTS_TXDRDY to value 0"] +impl crate::Resettable for EVENTS_TXDRDY_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/uarte0_ns/events_txstarted.rs b/pacs/nrf9120-pac/src/uarte0_ns/events_txstarted.rs new file mode 100644 index 00000000..195dbd8f --- /dev/null +++ b/pacs/nrf9120-pac/src/uarte0_ns/events_txstarted.rs @@ -0,0 +1,127 @@ +#[doc = "Register `EVENTS_TXSTARTED` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVENTS_TXSTARTED` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `EVENTS_TXSTARTED` reader - UART transmitter has started"] +pub type EVENTS_TXSTARTED_R = crate::BitReader; +#[doc = "UART transmitter has started\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum EVENTS_TXSTARTED_A { + #[doc = "0: Event not generated"] + NOT_GENERATED = 0, + #[doc = "1: Event generated"] + GENERATED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: EVENTS_TXSTARTED_A) -> Self { + variant as u8 != 0 + } +} +impl EVENTS_TXSTARTED_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EVENTS_TXSTARTED_A { + match self.bits { + false => EVENTS_TXSTARTED_A::NOT_GENERATED, + true => EVENTS_TXSTARTED_A::GENERATED, + } + } + #[doc = "Checks if the value of the field is `NOT_GENERATED`"] + #[inline(always)] + pub fn is_not_generated(&self) -> bool { + *self == EVENTS_TXSTARTED_A::NOT_GENERATED + } + #[doc = "Checks if the value of the field is `GENERATED`"] + #[inline(always)] + pub fn is_generated(&self) -> bool { + *self == EVENTS_TXSTARTED_A::GENERATED + } +} +#[doc = "Field `EVENTS_TXSTARTED` writer - UART transmitter has started"] +pub type EVENTS_TXSTARTED_W<'a, const O: u8> = + crate::BitWriter<'a, u32, EVENTS_TXSTARTED_SPEC, EVENTS_TXSTARTED_A, O>; +impl<'a, const O: u8> EVENTS_TXSTARTED_W<'a, O> { + #[doc = "Event not generated"] + #[inline(always)] + pub fn not_generated(self) -> &'a mut W { + self.variant(EVENTS_TXSTARTED_A::NOT_GENERATED) + } + #[doc = "Event generated"] + #[inline(always)] + pub fn generated(self) -> &'a mut W { + self.variant(EVENTS_TXSTARTED_A::GENERATED) + } +} +impl R { + #[doc = "Bit 0 - UART transmitter has started"] + #[inline(always)] + pub fn events_txstarted(&self) -> EVENTS_TXSTARTED_R { + EVENTS_TXSTARTED_R::new((self.bits & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - UART transmitter has started"] + #[inline(always)] + pub fn events_txstarted(&mut self) -> EVENTS_TXSTARTED_W<0> { + EVENTS_TXSTARTED_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "UART transmitter has started\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [events_txstarted](index.html) module"] +pub struct EVENTS_TXSTARTED_SPEC; +impl crate::RegisterSpec for EVENTS_TXSTARTED_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [events_txstarted::R](R) reader structure"] +impl crate::Readable for EVENTS_TXSTARTED_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [events_txstarted::W](W) writer structure"] +impl crate::Writable for EVENTS_TXSTARTED_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EVENTS_TXSTARTED to value 0"] +impl crate::Resettable for EVENTS_TXSTARTED_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/uarte0_ns/events_txstopped.rs b/pacs/nrf9120-pac/src/uarte0_ns/events_txstopped.rs new file mode 100644 index 00000000..cfc61f76 --- /dev/null +++ b/pacs/nrf9120-pac/src/uarte0_ns/events_txstopped.rs @@ -0,0 +1,127 @@ +#[doc = "Register `EVENTS_TXSTOPPED` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVENTS_TXSTOPPED` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `EVENTS_TXSTOPPED` reader - Transmitter stopped"] +pub type EVENTS_TXSTOPPED_R = crate::BitReader; +#[doc = "Transmitter stopped\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum EVENTS_TXSTOPPED_A { + #[doc = "0: Event not generated"] + NOT_GENERATED = 0, + #[doc = "1: Event generated"] + GENERATED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: EVENTS_TXSTOPPED_A) -> Self { + variant as u8 != 0 + } +} +impl EVENTS_TXSTOPPED_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EVENTS_TXSTOPPED_A { + match self.bits { + false => EVENTS_TXSTOPPED_A::NOT_GENERATED, + true => EVENTS_TXSTOPPED_A::GENERATED, + } + } + #[doc = "Checks if the value of the field is `NOT_GENERATED`"] + #[inline(always)] + pub fn is_not_generated(&self) -> bool { + *self == EVENTS_TXSTOPPED_A::NOT_GENERATED + } + #[doc = "Checks if the value of the field is `GENERATED`"] + #[inline(always)] + pub fn is_generated(&self) -> bool { + *self == EVENTS_TXSTOPPED_A::GENERATED + } +} +#[doc = "Field `EVENTS_TXSTOPPED` writer - Transmitter stopped"] +pub type EVENTS_TXSTOPPED_W<'a, const O: u8> = + crate::BitWriter<'a, u32, EVENTS_TXSTOPPED_SPEC, EVENTS_TXSTOPPED_A, O>; +impl<'a, const O: u8> EVENTS_TXSTOPPED_W<'a, O> { + #[doc = "Event not generated"] + #[inline(always)] + pub fn not_generated(self) -> &'a mut W { + self.variant(EVENTS_TXSTOPPED_A::NOT_GENERATED) + } + #[doc = "Event generated"] + #[inline(always)] + pub fn generated(self) -> &'a mut W { + self.variant(EVENTS_TXSTOPPED_A::GENERATED) + } +} +impl R { + #[doc = "Bit 0 - Transmitter stopped"] + #[inline(always)] + pub fn events_txstopped(&self) -> EVENTS_TXSTOPPED_R { + EVENTS_TXSTOPPED_R::new((self.bits & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Transmitter stopped"] + #[inline(always)] + pub fn events_txstopped(&mut self) -> EVENTS_TXSTOPPED_W<0> { + EVENTS_TXSTOPPED_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Transmitter stopped\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [events_txstopped](index.html) module"] +pub struct EVENTS_TXSTOPPED_SPEC; +impl crate::RegisterSpec for EVENTS_TXSTOPPED_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [events_txstopped::R](R) reader structure"] +impl crate::Readable for EVENTS_TXSTOPPED_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [events_txstopped::W](W) writer structure"] +impl crate::Writable for EVENTS_TXSTOPPED_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EVENTS_TXSTOPPED to value 0"] +impl crate::Resettable for EVENTS_TXSTOPPED_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/uarte0_ns/inten.rs b/pacs/nrf9120-pac/src/uarte0_ns/inten.rs new file mode 100644 index 00000000..4b23d13d --- /dev/null +++ b/pacs/nrf9120-pac/src/uarte0_ns/inten.rs @@ -0,0 +1,726 @@ +#[doc = "Register `INTEN` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTEN` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CTS` reader - Enable or disable interrupt for event CTS"] +pub type CTS_R = crate::BitReader; +#[doc = "Enable or disable interrupt for event CTS\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CTS_A { + #[doc = "0: Disable"] + DISABLED = 0, + #[doc = "1: Enable"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CTS_A) -> Self { + variant as u8 != 0 + } +} +impl CTS_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CTS_A { + match self.bits { + false => CTS_A::DISABLED, + true => CTS_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == CTS_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == CTS_A::ENABLED + } +} +#[doc = "Field `CTS` writer - Enable or disable interrupt for event CTS"] +pub type CTS_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTEN_SPEC, CTS_A, O>; +impl<'a, const O: u8> CTS_W<'a, O> { + #[doc = "Disable"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(CTS_A::DISABLED) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(CTS_A::ENABLED) + } +} +#[doc = "Field `NCTS` reader - Enable or disable interrupt for event NCTS"] +pub type NCTS_R = crate::BitReader; +#[doc = "Enable or disable interrupt for event NCTS\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum NCTS_A { + #[doc = "0: Disable"] + DISABLED = 0, + #[doc = "1: Enable"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: NCTS_A) -> Self { + variant as u8 != 0 + } +} +impl NCTS_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> NCTS_A { + match self.bits { + false => NCTS_A::DISABLED, + true => NCTS_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == NCTS_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == NCTS_A::ENABLED + } +} +#[doc = "Field `NCTS` writer - Enable or disable interrupt for event NCTS"] +pub type NCTS_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTEN_SPEC, NCTS_A, O>; +impl<'a, const O: u8> NCTS_W<'a, O> { + #[doc = "Disable"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(NCTS_A::DISABLED) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(NCTS_A::ENABLED) + } +} +#[doc = "Field `RXDRDY` reader - Enable or disable interrupt for event RXDRDY"] +pub type RXDRDY_R = crate::BitReader; +#[doc = "Enable or disable interrupt for event RXDRDY\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RXDRDY_A { + #[doc = "0: Disable"] + DISABLED = 0, + #[doc = "1: Enable"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RXDRDY_A) -> Self { + variant as u8 != 0 + } +} +impl RXDRDY_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RXDRDY_A { + match self.bits { + false => RXDRDY_A::DISABLED, + true => RXDRDY_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == RXDRDY_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == RXDRDY_A::ENABLED + } +} +#[doc = "Field `RXDRDY` writer - Enable or disable interrupt for event RXDRDY"] +pub type RXDRDY_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTEN_SPEC, RXDRDY_A, O>; +impl<'a, const O: u8> RXDRDY_W<'a, O> { + #[doc = "Disable"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(RXDRDY_A::DISABLED) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(RXDRDY_A::ENABLED) + } +} +#[doc = "Field `ENDRX` reader - Enable or disable interrupt for event ENDRX"] +pub type ENDRX_R = crate::BitReader; +#[doc = "Enable or disable interrupt for event ENDRX\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum ENDRX_A { + #[doc = "0: Disable"] + DISABLED = 0, + #[doc = "1: Enable"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: ENDRX_A) -> Self { + variant as u8 != 0 + } +} +impl ENDRX_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> ENDRX_A { + match self.bits { + false => ENDRX_A::DISABLED, + true => ENDRX_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == ENDRX_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == ENDRX_A::ENABLED + } +} +#[doc = "Field `ENDRX` writer - Enable or disable interrupt for event ENDRX"] +pub type ENDRX_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTEN_SPEC, ENDRX_A, O>; +impl<'a, const O: u8> ENDRX_W<'a, O> { + #[doc = "Disable"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(ENDRX_A::DISABLED) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(ENDRX_A::ENABLED) + } +} +#[doc = "Field `TXDRDY` reader - Enable or disable interrupt for event TXDRDY"] +pub type TXDRDY_R = crate::BitReader; +#[doc = "Enable or disable interrupt for event TXDRDY\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum TXDRDY_A { + #[doc = "0: Disable"] + DISABLED = 0, + #[doc = "1: Enable"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TXDRDY_A) -> Self { + variant as u8 != 0 + } +} +impl TXDRDY_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> TXDRDY_A { + match self.bits { + false => TXDRDY_A::DISABLED, + true => TXDRDY_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == TXDRDY_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == TXDRDY_A::ENABLED + } +} +#[doc = "Field `TXDRDY` writer - Enable or disable interrupt for event TXDRDY"] +pub type TXDRDY_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTEN_SPEC, TXDRDY_A, O>; +impl<'a, const O: u8> TXDRDY_W<'a, O> { + #[doc = "Disable"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(TXDRDY_A::DISABLED) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(TXDRDY_A::ENABLED) + } +} +#[doc = "Field `ENDTX` reader - Enable or disable interrupt for event ENDTX"] +pub type ENDTX_R = crate::BitReader; +#[doc = "Enable or disable interrupt for event ENDTX\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum ENDTX_A { + #[doc = "0: Disable"] + DISABLED = 0, + #[doc = "1: Enable"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: ENDTX_A) -> Self { + variant as u8 != 0 + } +} +impl ENDTX_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> ENDTX_A { + match self.bits { + false => ENDTX_A::DISABLED, + true => ENDTX_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == ENDTX_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == ENDTX_A::ENABLED + } +} +#[doc = "Field `ENDTX` writer - Enable or disable interrupt for event ENDTX"] +pub type ENDTX_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTEN_SPEC, ENDTX_A, O>; +impl<'a, const O: u8> ENDTX_W<'a, O> { + #[doc = "Disable"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(ENDTX_A::DISABLED) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(ENDTX_A::ENABLED) + } +} +#[doc = "Field `ERROR` reader - Enable or disable interrupt for event ERROR"] +pub type ERROR_R = crate::BitReader; +#[doc = "Enable or disable interrupt for event ERROR\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum ERROR_A { + #[doc = "0: Disable"] + DISABLED = 0, + #[doc = "1: Enable"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: ERROR_A) -> Self { + variant as u8 != 0 + } +} +impl ERROR_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> ERROR_A { + match self.bits { + false => ERROR_A::DISABLED, + true => ERROR_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == ERROR_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == ERROR_A::ENABLED + } +} +#[doc = "Field `ERROR` writer - Enable or disable interrupt for event ERROR"] +pub type ERROR_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTEN_SPEC, ERROR_A, O>; +impl<'a, const O: u8> ERROR_W<'a, O> { + #[doc = "Disable"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(ERROR_A::DISABLED) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(ERROR_A::ENABLED) + } +} +#[doc = "Field `RXTO` reader - Enable or disable interrupt for event RXTO"] +pub type RXTO_R = crate::BitReader; +#[doc = "Enable or disable interrupt for event RXTO\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RXTO_A { + #[doc = "0: Disable"] + DISABLED = 0, + #[doc = "1: Enable"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RXTO_A) -> Self { + variant as u8 != 0 + } +} +impl RXTO_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RXTO_A { + match self.bits { + false => RXTO_A::DISABLED, + true => RXTO_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == RXTO_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == RXTO_A::ENABLED + } +} +#[doc = "Field `RXTO` writer - Enable or disable interrupt for event RXTO"] +pub type RXTO_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTEN_SPEC, RXTO_A, O>; +impl<'a, const O: u8> RXTO_W<'a, O> { + #[doc = "Disable"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(RXTO_A::DISABLED) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(RXTO_A::ENABLED) + } +} +#[doc = "Field `RXSTARTED` reader - Enable or disable interrupt for event RXSTARTED"] +pub type RXSTARTED_R = crate::BitReader; +#[doc = "Enable or disable interrupt for event RXSTARTED\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RXSTARTED_A { + #[doc = "0: Disable"] + DISABLED = 0, + #[doc = "1: Enable"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RXSTARTED_A) -> Self { + variant as u8 != 0 + } +} +impl RXSTARTED_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RXSTARTED_A { + match self.bits { + false => RXSTARTED_A::DISABLED, + true => RXSTARTED_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == RXSTARTED_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == RXSTARTED_A::ENABLED + } +} +#[doc = "Field `RXSTARTED` writer - Enable or disable interrupt for event RXSTARTED"] +pub type RXSTARTED_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTEN_SPEC, RXSTARTED_A, O>; +impl<'a, const O: u8> RXSTARTED_W<'a, O> { + #[doc = "Disable"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(RXSTARTED_A::DISABLED) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(RXSTARTED_A::ENABLED) + } +} +#[doc = "Field `TXSTARTED` reader - Enable or disable interrupt for event TXSTARTED"] +pub type TXSTARTED_R = crate::BitReader; +#[doc = "Enable or disable interrupt for event TXSTARTED\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum TXSTARTED_A { + #[doc = "0: Disable"] + DISABLED = 0, + #[doc = "1: Enable"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TXSTARTED_A) -> Self { + variant as u8 != 0 + } +} +impl TXSTARTED_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> TXSTARTED_A { + match self.bits { + false => TXSTARTED_A::DISABLED, + true => TXSTARTED_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == TXSTARTED_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == TXSTARTED_A::ENABLED + } +} +#[doc = "Field `TXSTARTED` writer - Enable or disable interrupt for event TXSTARTED"] +pub type TXSTARTED_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTEN_SPEC, TXSTARTED_A, O>; +impl<'a, const O: u8> TXSTARTED_W<'a, O> { + #[doc = "Disable"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(TXSTARTED_A::DISABLED) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(TXSTARTED_A::ENABLED) + } +} +#[doc = "Field `TXSTOPPED` reader - Enable or disable interrupt for event TXSTOPPED"] +pub type TXSTOPPED_R = crate::BitReader; +#[doc = "Enable or disable interrupt for event TXSTOPPED\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum TXSTOPPED_A { + #[doc = "0: Disable"] + DISABLED = 0, + #[doc = "1: Enable"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TXSTOPPED_A) -> Self { + variant as u8 != 0 + } +} +impl TXSTOPPED_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> TXSTOPPED_A { + match self.bits { + false => TXSTOPPED_A::DISABLED, + true => TXSTOPPED_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == TXSTOPPED_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == TXSTOPPED_A::ENABLED + } +} +#[doc = "Field `TXSTOPPED` writer - Enable or disable interrupt for event TXSTOPPED"] +pub type TXSTOPPED_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTEN_SPEC, TXSTOPPED_A, O>; +impl<'a, const O: u8> TXSTOPPED_W<'a, O> { + #[doc = "Disable"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(TXSTOPPED_A::DISABLED) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(TXSTOPPED_A::ENABLED) + } +} +impl R { + #[doc = "Bit 0 - Enable or disable interrupt for event CTS"] + #[inline(always)] + pub fn cts(&self) -> CTS_R { + CTS_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Enable or disable interrupt for event NCTS"] + #[inline(always)] + pub fn ncts(&self) -> NCTS_R { + NCTS_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Enable or disable interrupt for event RXDRDY"] + #[inline(always)] + pub fn rxdrdy(&self) -> RXDRDY_R { + RXDRDY_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 4 - Enable or disable interrupt for event ENDRX"] + #[inline(always)] + pub fn endrx(&self) -> ENDRX_R { + ENDRX_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 7 - Enable or disable interrupt for event TXDRDY"] + #[inline(always)] + pub fn txdrdy(&self) -> TXDRDY_R { + TXDRDY_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Enable or disable interrupt for event ENDTX"] + #[inline(always)] + pub fn endtx(&self) -> ENDTX_R { + ENDTX_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Enable or disable interrupt for event ERROR"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 17 - Enable or disable interrupt for event RXTO"] + #[inline(always)] + pub fn rxto(&self) -> RXTO_R { + RXTO_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 19 - Enable or disable interrupt for event RXSTARTED"] + #[inline(always)] + pub fn rxstarted(&self) -> RXSTARTED_R { + RXSTARTED_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Enable or disable interrupt for event TXSTARTED"] + #[inline(always)] + pub fn txstarted(&self) -> TXSTARTED_R { + TXSTARTED_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 22 - Enable or disable interrupt for event TXSTOPPED"] + #[inline(always)] + pub fn txstopped(&self) -> TXSTOPPED_R { + TXSTOPPED_R::new(((self.bits >> 22) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Enable or disable interrupt for event CTS"] + #[inline(always)] + pub fn cts(&mut self) -> CTS_W<0> { + CTS_W::new(self) + } + #[doc = "Bit 1 - Enable or disable interrupt for event NCTS"] + #[inline(always)] + pub fn ncts(&mut self) -> NCTS_W<1> { + NCTS_W::new(self) + } + #[doc = "Bit 2 - Enable or disable interrupt for event RXDRDY"] + #[inline(always)] + pub fn rxdrdy(&mut self) -> RXDRDY_W<2> { + RXDRDY_W::new(self) + } + #[doc = "Bit 4 - Enable or disable interrupt for event ENDRX"] + #[inline(always)] + pub fn endrx(&mut self) -> ENDRX_W<4> { + ENDRX_W::new(self) + } + #[doc = "Bit 7 - Enable or disable interrupt for event TXDRDY"] + #[inline(always)] + pub fn txdrdy(&mut self) -> TXDRDY_W<7> { + TXDRDY_W::new(self) + } + #[doc = "Bit 8 - Enable or disable interrupt for event ENDTX"] + #[inline(always)] + pub fn endtx(&mut self) -> ENDTX_W<8> { + ENDTX_W::new(self) + } + #[doc = "Bit 9 - Enable or disable interrupt for event ERROR"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W<9> { + ERROR_W::new(self) + } + #[doc = "Bit 17 - Enable or disable interrupt for event RXTO"] + #[inline(always)] + pub fn rxto(&mut self) -> RXTO_W<17> { + RXTO_W::new(self) + } + #[doc = "Bit 19 - Enable or disable interrupt for event RXSTARTED"] + #[inline(always)] + pub fn rxstarted(&mut self) -> RXSTARTED_W<19> { + RXSTARTED_W::new(self) + } + #[doc = "Bit 20 - Enable or disable interrupt for event TXSTARTED"] + #[inline(always)] + pub fn txstarted(&mut self) -> TXSTARTED_W<20> { + TXSTARTED_W::new(self) + } + #[doc = "Bit 22 - Enable or disable interrupt for event TXSTOPPED"] + #[inline(always)] + pub fn txstopped(&mut self) -> TXSTOPPED_W<22> { + TXSTOPPED_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Enable or disable interrupt\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [inten](index.html) module"] +pub struct INTEN_SPEC; +impl crate::RegisterSpec for INTEN_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [inten::R](R) reader structure"] +impl crate::Readable for INTEN_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [inten::W](W) writer structure"] +impl crate::Writable for INTEN_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTEN to value 0"] +impl crate::Resettable for INTEN_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/uarte0_ns/intenclr.rs b/pacs/nrf9120-pac/src/uarte0_ns/intenclr.rs new file mode 100644 index 00000000..81a06348 --- /dev/null +++ b/pacs/nrf9120-pac/src/uarte0_ns/intenclr.rs @@ -0,0 +1,803 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CTS` reader - Write '1' to disable interrupt for event CTS"] +pub type CTS_R = crate::BitReader; +#[doc = "Write '1' to disable interrupt for event CTS\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CTS_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CTS_A) -> Self { + variant as u8 != 0 + } +} +impl CTS_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CTS_A { + match self.bits { + false => CTS_A::DISABLED, + true => CTS_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == CTS_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == CTS_A::ENABLED + } +} +#[doc = "Write '1' to disable interrupt for event CTS\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CTS_AW { + #[doc = "1: Disable"] + CLEAR = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CTS_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CTS` writer - Write '1' to disable interrupt for event CTS"] +pub type CTS_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENCLR_SPEC, CTS_AW, O>; +impl<'a, const O: u8> CTS_W<'a, O> { + #[doc = "Disable"] + #[inline(always)] + pub fn clear(self) -> &'a mut W { + self.variant(CTS_AW::CLEAR) + } +} +#[doc = "Field `NCTS` reader - Write '1' to disable interrupt for event NCTS"] +pub type NCTS_R = crate::BitReader; +#[doc = "Write '1' to disable interrupt for event NCTS\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum NCTS_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: NCTS_A) -> Self { + variant as u8 != 0 + } +} +impl NCTS_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> NCTS_A { + match self.bits { + false => NCTS_A::DISABLED, + true => NCTS_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == NCTS_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == NCTS_A::ENABLED + } +} +#[doc = "Write '1' to disable interrupt for event NCTS\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum NCTS_AW { + #[doc = "1: Disable"] + CLEAR = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: NCTS_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NCTS` writer - Write '1' to disable interrupt for event NCTS"] +pub type NCTS_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENCLR_SPEC, NCTS_AW, O>; +impl<'a, const O: u8> NCTS_W<'a, O> { + #[doc = "Disable"] + #[inline(always)] + pub fn clear(self) -> &'a mut W { + self.variant(NCTS_AW::CLEAR) + } +} +#[doc = "Field `RXDRDY` reader - Write '1' to disable interrupt for event RXDRDY"] +pub type RXDRDY_R = crate::BitReader; +#[doc = "Write '1' to disable interrupt for event RXDRDY\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RXDRDY_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RXDRDY_A) -> Self { + variant as u8 != 0 + } +} +impl RXDRDY_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RXDRDY_A { + match self.bits { + false => RXDRDY_A::DISABLED, + true => RXDRDY_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == RXDRDY_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == RXDRDY_A::ENABLED + } +} +#[doc = "Write '1' to disable interrupt for event RXDRDY\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RXDRDY_AW { + #[doc = "1: Disable"] + CLEAR = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RXDRDY_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RXDRDY` writer - Write '1' to disable interrupt for event RXDRDY"] +pub type RXDRDY_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENCLR_SPEC, RXDRDY_AW, O>; +impl<'a, const O: u8> RXDRDY_W<'a, O> { + #[doc = "Disable"] + #[inline(always)] + pub fn clear(self) -> &'a mut W { + self.variant(RXDRDY_AW::CLEAR) + } +} +#[doc = "Field `ENDRX` reader - Write '1' to disable interrupt for event ENDRX"] +pub type ENDRX_R = crate::BitReader; +#[doc = "Write '1' to disable interrupt for event ENDRX\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum ENDRX_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: ENDRX_A) -> Self { + variant as u8 != 0 + } +} +impl ENDRX_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> ENDRX_A { + match self.bits { + false => ENDRX_A::DISABLED, + true => ENDRX_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == ENDRX_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == ENDRX_A::ENABLED + } +} +#[doc = "Write '1' to disable interrupt for event ENDRX\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum ENDRX_AW { + #[doc = "1: Disable"] + CLEAR = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: ENDRX_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ENDRX` writer - Write '1' to disable interrupt for event ENDRX"] +pub type ENDRX_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENCLR_SPEC, ENDRX_AW, O>; +impl<'a, const O: u8> ENDRX_W<'a, O> { + #[doc = "Disable"] + #[inline(always)] + pub fn clear(self) -> &'a mut W { + self.variant(ENDRX_AW::CLEAR) + } +} +#[doc = "Field `TXDRDY` reader - Write '1' to disable interrupt for event TXDRDY"] +pub type TXDRDY_R = crate::BitReader; +#[doc = "Write '1' to disable interrupt for event TXDRDY\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum TXDRDY_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TXDRDY_A) -> Self { + variant as u8 != 0 + } +} +impl TXDRDY_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> TXDRDY_A { + match self.bits { + false => TXDRDY_A::DISABLED, + true => TXDRDY_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == TXDRDY_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == TXDRDY_A::ENABLED + } +} +#[doc = "Write '1' to disable interrupt for event TXDRDY\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum TXDRDY_AW { + #[doc = "1: Disable"] + CLEAR = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TXDRDY_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TXDRDY` writer - Write '1' to disable interrupt for event TXDRDY"] +pub type TXDRDY_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENCLR_SPEC, TXDRDY_AW, O>; +impl<'a, const O: u8> TXDRDY_W<'a, O> { + #[doc = "Disable"] + #[inline(always)] + pub fn clear(self) -> &'a mut W { + self.variant(TXDRDY_AW::CLEAR) + } +} +#[doc = "Field `ENDTX` reader - Write '1' to disable interrupt for event ENDTX"] +pub type ENDTX_R = crate::BitReader; +#[doc = "Write '1' to disable interrupt for event ENDTX\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum ENDTX_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: ENDTX_A) -> Self { + variant as u8 != 0 + } +} +impl ENDTX_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> ENDTX_A { + match self.bits { + false => ENDTX_A::DISABLED, + true => ENDTX_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == ENDTX_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == ENDTX_A::ENABLED + } +} +#[doc = "Write '1' to disable interrupt for event ENDTX\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum ENDTX_AW { + #[doc = "1: Disable"] + CLEAR = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: ENDTX_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ENDTX` writer - Write '1' to disable interrupt for event ENDTX"] +pub type ENDTX_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENCLR_SPEC, ENDTX_AW, O>; +impl<'a, const O: u8> ENDTX_W<'a, O> { + #[doc = "Disable"] + #[inline(always)] + pub fn clear(self) -> &'a mut W { + self.variant(ENDTX_AW::CLEAR) + } +} +#[doc = "Field `ERROR` reader - Write '1' to disable interrupt for event ERROR"] +pub type ERROR_R = crate::BitReader; +#[doc = "Write '1' to disable interrupt for event ERROR\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum ERROR_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: ERROR_A) -> Self { + variant as u8 != 0 + } +} +impl ERROR_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> ERROR_A { + match self.bits { + false => ERROR_A::DISABLED, + true => ERROR_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == ERROR_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == ERROR_A::ENABLED + } +} +#[doc = "Write '1' to disable interrupt for event ERROR\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum ERROR_AW { + #[doc = "1: Disable"] + CLEAR = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: ERROR_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ERROR` writer - Write '1' to disable interrupt for event ERROR"] +pub type ERROR_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENCLR_SPEC, ERROR_AW, O>; +impl<'a, const O: u8> ERROR_W<'a, O> { + #[doc = "Disable"] + #[inline(always)] + pub fn clear(self) -> &'a mut W { + self.variant(ERROR_AW::CLEAR) + } +} +#[doc = "Field `RXTO` reader - Write '1' to disable interrupt for event RXTO"] +pub type RXTO_R = crate::BitReader; +#[doc = "Write '1' to disable interrupt for event RXTO\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RXTO_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RXTO_A) -> Self { + variant as u8 != 0 + } +} +impl RXTO_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RXTO_A { + match self.bits { + false => RXTO_A::DISABLED, + true => RXTO_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == RXTO_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == RXTO_A::ENABLED + } +} +#[doc = "Write '1' to disable interrupt for event RXTO\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RXTO_AW { + #[doc = "1: Disable"] + CLEAR = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RXTO_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RXTO` writer - Write '1' to disable interrupt for event RXTO"] +pub type RXTO_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENCLR_SPEC, RXTO_AW, O>; +impl<'a, const O: u8> RXTO_W<'a, O> { + #[doc = "Disable"] + #[inline(always)] + pub fn clear(self) -> &'a mut W { + self.variant(RXTO_AW::CLEAR) + } +} +#[doc = "Field `RXSTARTED` reader - Write '1' to disable interrupt for event RXSTARTED"] +pub type RXSTARTED_R = crate::BitReader; +#[doc = "Write '1' to disable interrupt for event RXSTARTED\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RXSTARTED_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RXSTARTED_A) -> Self { + variant as u8 != 0 + } +} +impl RXSTARTED_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RXSTARTED_A { + match self.bits { + false => RXSTARTED_A::DISABLED, + true => RXSTARTED_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == RXSTARTED_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == RXSTARTED_A::ENABLED + } +} +#[doc = "Write '1' to disable interrupt for event RXSTARTED\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RXSTARTED_AW { + #[doc = "1: Disable"] + CLEAR = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RXSTARTED_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RXSTARTED` writer - Write '1' to disable interrupt for event RXSTARTED"] +pub type RXSTARTED_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENCLR_SPEC, RXSTARTED_AW, O>; +impl<'a, const O: u8> RXSTARTED_W<'a, O> { + #[doc = "Disable"] + #[inline(always)] + pub fn clear(self) -> &'a mut W { + self.variant(RXSTARTED_AW::CLEAR) + } +} +#[doc = "Field `TXSTARTED` reader - Write '1' to disable interrupt for event TXSTARTED"] +pub type TXSTARTED_R = crate::BitReader; +#[doc = "Write '1' to disable interrupt for event TXSTARTED\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum TXSTARTED_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TXSTARTED_A) -> Self { + variant as u8 != 0 + } +} +impl TXSTARTED_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> TXSTARTED_A { + match self.bits { + false => TXSTARTED_A::DISABLED, + true => TXSTARTED_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == TXSTARTED_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == TXSTARTED_A::ENABLED + } +} +#[doc = "Write '1' to disable interrupt for event TXSTARTED\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum TXSTARTED_AW { + #[doc = "1: Disable"] + CLEAR = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TXSTARTED_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TXSTARTED` writer - Write '1' to disable interrupt for event TXSTARTED"] +pub type TXSTARTED_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENCLR_SPEC, TXSTARTED_AW, O>; +impl<'a, const O: u8> TXSTARTED_W<'a, O> { + #[doc = "Disable"] + #[inline(always)] + pub fn clear(self) -> &'a mut W { + self.variant(TXSTARTED_AW::CLEAR) + } +} +#[doc = "Field `TXSTOPPED` reader - Write '1' to disable interrupt for event TXSTOPPED"] +pub type TXSTOPPED_R = crate::BitReader; +#[doc = "Write '1' to disable interrupt for event TXSTOPPED\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum TXSTOPPED_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TXSTOPPED_A) -> Self { + variant as u8 != 0 + } +} +impl TXSTOPPED_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> TXSTOPPED_A { + match self.bits { + false => TXSTOPPED_A::DISABLED, + true => TXSTOPPED_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == TXSTOPPED_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == TXSTOPPED_A::ENABLED + } +} +#[doc = "Write '1' to disable interrupt for event TXSTOPPED\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum TXSTOPPED_AW { + #[doc = "1: Disable"] + CLEAR = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TXSTOPPED_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TXSTOPPED` writer - Write '1' to disable interrupt for event TXSTOPPED"] +pub type TXSTOPPED_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENCLR_SPEC, TXSTOPPED_AW, O>; +impl<'a, const O: u8> TXSTOPPED_W<'a, O> { + #[doc = "Disable"] + #[inline(always)] + pub fn clear(self) -> &'a mut W { + self.variant(TXSTOPPED_AW::CLEAR) + } +} +impl R { + #[doc = "Bit 0 - Write '1' to disable interrupt for event CTS"] + #[inline(always)] + pub fn cts(&self) -> CTS_R { + CTS_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Write '1' to disable interrupt for event NCTS"] + #[inline(always)] + pub fn ncts(&self) -> NCTS_R { + NCTS_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Write '1' to disable interrupt for event RXDRDY"] + #[inline(always)] + pub fn rxdrdy(&self) -> RXDRDY_R { + RXDRDY_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 4 - Write '1' to disable interrupt for event ENDRX"] + #[inline(always)] + pub fn endrx(&self) -> ENDRX_R { + ENDRX_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 7 - Write '1' to disable interrupt for event TXDRDY"] + #[inline(always)] + pub fn txdrdy(&self) -> TXDRDY_R { + TXDRDY_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Write '1' to disable interrupt for event ENDTX"] + #[inline(always)] + pub fn endtx(&self) -> ENDTX_R { + ENDTX_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Write '1' to disable interrupt for event ERROR"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 17 - Write '1' to disable interrupt for event RXTO"] + #[inline(always)] + pub fn rxto(&self) -> RXTO_R { + RXTO_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 19 - Write '1' to disable interrupt for event RXSTARTED"] + #[inline(always)] + pub fn rxstarted(&self) -> RXSTARTED_R { + RXSTARTED_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Write '1' to disable interrupt for event TXSTARTED"] + #[inline(always)] + pub fn txstarted(&self) -> TXSTARTED_R { + TXSTARTED_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 22 - Write '1' to disable interrupt for event TXSTOPPED"] + #[inline(always)] + pub fn txstopped(&self) -> TXSTOPPED_R { + TXSTOPPED_R::new(((self.bits >> 22) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Write '1' to disable interrupt for event CTS"] + #[inline(always)] + pub fn cts(&mut self) -> CTS_W<0> { + CTS_W::new(self) + } + #[doc = "Bit 1 - Write '1' to disable interrupt for event NCTS"] + #[inline(always)] + pub fn ncts(&mut self) -> NCTS_W<1> { + NCTS_W::new(self) + } + #[doc = "Bit 2 - Write '1' to disable interrupt for event RXDRDY"] + #[inline(always)] + pub fn rxdrdy(&mut self) -> RXDRDY_W<2> { + RXDRDY_W::new(self) + } + #[doc = "Bit 4 - Write '1' to disable interrupt for event ENDRX"] + #[inline(always)] + pub fn endrx(&mut self) -> ENDRX_W<4> { + ENDRX_W::new(self) + } + #[doc = "Bit 7 - Write '1' to disable interrupt for event TXDRDY"] + #[inline(always)] + pub fn txdrdy(&mut self) -> TXDRDY_W<7> { + TXDRDY_W::new(self) + } + #[doc = "Bit 8 - Write '1' to disable interrupt for event ENDTX"] + #[inline(always)] + pub fn endtx(&mut self) -> ENDTX_W<8> { + ENDTX_W::new(self) + } + #[doc = "Bit 9 - Write '1' to disable interrupt for event ERROR"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W<9> { + ERROR_W::new(self) + } + #[doc = "Bit 17 - Write '1' to disable interrupt for event RXTO"] + #[inline(always)] + pub fn rxto(&mut self) -> RXTO_W<17> { + RXTO_W::new(self) + } + #[doc = "Bit 19 - Write '1' to disable interrupt for event RXSTARTED"] + #[inline(always)] + pub fn rxstarted(&mut self) -> RXSTARTED_W<19> { + RXSTARTED_W::new(self) + } + #[doc = "Bit 20 - Write '1' to disable interrupt for event TXSTARTED"] + #[inline(always)] + pub fn txstarted(&mut self) -> TXSTARTED_W<20> { + TXSTARTED_W::new(self) + } + #[doc = "Bit 22 - Write '1' to disable interrupt for event TXSTOPPED"] + #[inline(always)] + pub fn txstopped(&mut self) -> TXSTOPPED_W<22> { + TXSTOPPED_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Disable interrupt\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/uarte0_ns/intenset.rs b/pacs/nrf9120-pac/src/uarte0_ns/intenset.rs new file mode 100644 index 00000000..79758c3d --- /dev/null +++ b/pacs/nrf9120-pac/src/uarte0_ns/intenset.rs @@ -0,0 +1,803 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CTS` reader - Write '1' to enable interrupt for event CTS"] +pub type CTS_R = crate::BitReader; +#[doc = "Write '1' to enable interrupt for event CTS\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CTS_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CTS_A) -> Self { + variant as u8 != 0 + } +} +impl CTS_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CTS_A { + match self.bits { + false => CTS_A::DISABLED, + true => CTS_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == CTS_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == CTS_A::ENABLED + } +} +#[doc = "Write '1' to enable interrupt for event CTS\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CTS_AW { + #[doc = "1: Enable"] + SET = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CTS_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CTS` writer - Write '1' to enable interrupt for event CTS"] +pub type CTS_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENSET_SPEC, CTS_AW, O>; +impl<'a, const O: u8> CTS_W<'a, O> { + #[doc = "Enable"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(CTS_AW::SET) + } +} +#[doc = "Field `NCTS` reader - Write '1' to enable interrupt for event NCTS"] +pub type NCTS_R = crate::BitReader; +#[doc = "Write '1' to enable interrupt for event NCTS\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum NCTS_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: NCTS_A) -> Self { + variant as u8 != 0 + } +} +impl NCTS_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> NCTS_A { + match self.bits { + false => NCTS_A::DISABLED, + true => NCTS_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == NCTS_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == NCTS_A::ENABLED + } +} +#[doc = "Write '1' to enable interrupt for event NCTS\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum NCTS_AW { + #[doc = "1: Enable"] + SET = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: NCTS_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NCTS` writer - Write '1' to enable interrupt for event NCTS"] +pub type NCTS_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENSET_SPEC, NCTS_AW, O>; +impl<'a, const O: u8> NCTS_W<'a, O> { + #[doc = "Enable"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(NCTS_AW::SET) + } +} +#[doc = "Field `RXDRDY` reader - Write '1' to enable interrupt for event RXDRDY"] +pub type RXDRDY_R = crate::BitReader; +#[doc = "Write '1' to enable interrupt for event RXDRDY\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RXDRDY_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RXDRDY_A) -> Self { + variant as u8 != 0 + } +} +impl RXDRDY_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RXDRDY_A { + match self.bits { + false => RXDRDY_A::DISABLED, + true => RXDRDY_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == RXDRDY_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == RXDRDY_A::ENABLED + } +} +#[doc = "Write '1' to enable interrupt for event RXDRDY\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RXDRDY_AW { + #[doc = "1: Enable"] + SET = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RXDRDY_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RXDRDY` writer - Write '1' to enable interrupt for event RXDRDY"] +pub type RXDRDY_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENSET_SPEC, RXDRDY_AW, O>; +impl<'a, const O: u8> RXDRDY_W<'a, O> { + #[doc = "Enable"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(RXDRDY_AW::SET) + } +} +#[doc = "Field `ENDRX` reader - Write '1' to enable interrupt for event ENDRX"] +pub type ENDRX_R = crate::BitReader; +#[doc = "Write '1' to enable interrupt for event ENDRX\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum ENDRX_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: ENDRX_A) -> Self { + variant as u8 != 0 + } +} +impl ENDRX_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> ENDRX_A { + match self.bits { + false => ENDRX_A::DISABLED, + true => ENDRX_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == ENDRX_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == ENDRX_A::ENABLED + } +} +#[doc = "Write '1' to enable interrupt for event ENDRX\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum ENDRX_AW { + #[doc = "1: Enable"] + SET = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: ENDRX_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ENDRX` writer - Write '1' to enable interrupt for event ENDRX"] +pub type ENDRX_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENSET_SPEC, ENDRX_AW, O>; +impl<'a, const O: u8> ENDRX_W<'a, O> { + #[doc = "Enable"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(ENDRX_AW::SET) + } +} +#[doc = "Field `TXDRDY` reader - Write '1' to enable interrupt for event TXDRDY"] +pub type TXDRDY_R = crate::BitReader; +#[doc = "Write '1' to enable interrupt for event TXDRDY\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum TXDRDY_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TXDRDY_A) -> Self { + variant as u8 != 0 + } +} +impl TXDRDY_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> TXDRDY_A { + match self.bits { + false => TXDRDY_A::DISABLED, + true => TXDRDY_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == TXDRDY_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == TXDRDY_A::ENABLED + } +} +#[doc = "Write '1' to enable interrupt for event TXDRDY\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum TXDRDY_AW { + #[doc = "1: Enable"] + SET = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TXDRDY_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TXDRDY` writer - Write '1' to enable interrupt for event TXDRDY"] +pub type TXDRDY_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENSET_SPEC, TXDRDY_AW, O>; +impl<'a, const O: u8> TXDRDY_W<'a, O> { + #[doc = "Enable"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(TXDRDY_AW::SET) + } +} +#[doc = "Field `ENDTX` reader - Write '1' to enable interrupt for event ENDTX"] +pub type ENDTX_R = crate::BitReader; +#[doc = "Write '1' to enable interrupt for event ENDTX\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum ENDTX_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: ENDTX_A) -> Self { + variant as u8 != 0 + } +} +impl ENDTX_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> ENDTX_A { + match self.bits { + false => ENDTX_A::DISABLED, + true => ENDTX_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == ENDTX_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == ENDTX_A::ENABLED + } +} +#[doc = "Write '1' to enable interrupt for event ENDTX\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum ENDTX_AW { + #[doc = "1: Enable"] + SET = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: ENDTX_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ENDTX` writer - Write '1' to enable interrupt for event ENDTX"] +pub type ENDTX_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENSET_SPEC, ENDTX_AW, O>; +impl<'a, const O: u8> ENDTX_W<'a, O> { + #[doc = "Enable"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(ENDTX_AW::SET) + } +} +#[doc = "Field `ERROR` reader - Write '1' to enable interrupt for event ERROR"] +pub type ERROR_R = crate::BitReader; +#[doc = "Write '1' to enable interrupt for event ERROR\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum ERROR_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: ERROR_A) -> Self { + variant as u8 != 0 + } +} +impl ERROR_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> ERROR_A { + match self.bits { + false => ERROR_A::DISABLED, + true => ERROR_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == ERROR_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == ERROR_A::ENABLED + } +} +#[doc = "Write '1' to enable interrupt for event ERROR\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum ERROR_AW { + #[doc = "1: Enable"] + SET = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: ERROR_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ERROR` writer - Write '1' to enable interrupt for event ERROR"] +pub type ERROR_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENSET_SPEC, ERROR_AW, O>; +impl<'a, const O: u8> ERROR_W<'a, O> { + #[doc = "Enable"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(ERROR_AW::SET) + } +} +#[doc = "Field `RXTO` reader - Write '1' to enable interrupt for event RXTO"] +pub type RXTO_R = crate::BitReader; +#[doc = "Write '1' to enable interrupt for event RXTO\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RXTO_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RXTO_A) -> Self { + variant as u8 != 0 + } +} +impl RXTO_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RXTO_A { + match self.bits { + false => RXTO_A::DISABLED, + true => RXTO_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == RXTO_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == RXTO_A::ENABLED + } +} +#[doc = "Write '1' to enable interrupt for event RXTO\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RXTO_AW { + #[doc = "1: Enable"] + SET = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RXTO_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RXTO` writer - Write '1' to enable interrupt for event RXTO"] +pub type RXTO_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENSET_SPEC, RXTO_AW, O>; +impl<'a, const O: u8> RXTO_W<'a, O> { + #[doc = "Enable"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(RXTO_AW::SET) + } +} +#[doc = "Field `RXSTARTED` reader - Write '1' to enable interrupt for event RXSTARTED"] +pub type RXSTARTED_R = crate::BitReader; +#[doc = "Write '1' to enable interrupt for event RXSTARTED\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RXSTARTED_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RXSTARTED_A) -> Self { + variant as u8 != 0 + } +} +impl RXSTARTED_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RXSTARTED_A { + match self.bits { + false => RXSTARTED_A::DISABLED, + true => RXSTARTED_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == RXSTARTED_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == RXSTARTED_A::ENABLED + } +} +#[doc = "Write '1' to enable interrupt for event RXSTARTED\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RXSTARTED_AW { + #[doc = "1: Enable"] + SET = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RXSTARTED_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RXSTARTED` writer - Write '1' to enable interrupt for event RXSTARTED"] +pub type RXSTARTED_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENSET_SPEC, RXSTARTED_AW, O>; +impl<'a, const O: u8> RXSTARTED_W<'a, O> { + #[doc = "Enable"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(RXSTARTED_AW::SET) + } +} +#[doc = "Field `TXSTARTED` reader - Write '1' to enable interrupt for event TXSTARTED"] +pub type TXSTARTED_R = crate::BitReader; +#[doc = "Write '1' to enable interrupt for event TXSTARTED\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum TXSTARTED_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TXSTARTED_A) -> Self { + variant as u8 != 0 + } +} +impl TXSTARTED_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> TXSTARTED_A { + match self.bits { + false => TXSTARTED_A::DISABLED, + true => TXSTARTED_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == TXSTARTED_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == TXSTARTED_A::ENABLED + } +} +#[doc = "Write '1' to enable interrupt for event TXSTARTED\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum TXSTARTED_AW { + #[doc = "1: Enable"] + SET = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TXSTARTED_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TXSTARTED` writer - Write '1' to enable interrupt for event TXSTARTED"] +pub type TXSTARTED_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENSET_SPEC, TXSTARTED_AW, O>; +impl<'a, const O: u8> TXSTARTED_W<'a, O> { + #[doc = "Enable"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(TXSTARTED_AW::SET) + } +} +#[doc = "Field `TXSTOPPED` reader - Write '1' to enable interrupt for event TXSTOPPED"] +pub type TXSTOPPED_R = crate::BitReader; +#[doc = "Write '1' to enable interrupt for event TXSTOPPED\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum TXSTOPPED_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TXSTOPPED_A) -> Self { + variant as u8 != 0 + } +} +impl TXSTOPPED_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> TXSTOPPED_A { + match self.bits { + false => TXSTOPPED_A::DISABLED, + true => TXSTOPPED_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == TXSTOPPED_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == TXSTOPPED_A::ENABLED + } +} +#[doc = "Write '1' to enable interrupt for event TXSTOPPED\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum TXSTOPPED_AW { + #[doc = "1: Enable"] + SET = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TXSTOPPED_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TXSTOPPED` writer - Write '1' to enable interrupt for event TXSTOPPED"] +pub type TXSTOPPED_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENSET_SPEC, TXSTOPPED_AW, O>; +impl<'a, const O: u8> TXSTOPPED_W<'a, O> { + #[doc = "Enable"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(TXSTOPPED_AW::SET) + } +} +impl R { + #[doc = "Bit 0 - Write '1' to enable interrupt for event CTS"] + #[inline(always)] + pub fn cts(&self) -> CTS_R { + CTS_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Write '1' to enable interrupt for event NCTS"] + #[inline(always)] + pub fn ncts(&self) -> NCTS_R { + NCTS_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Write '1' to enable interrupt for event RXDRDY"] + #[inline(always)] + pub fn rxdrdy(&self) -> RXDRDY_R { + RXDRDY_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 4 - Write '1' to enable interrupt for event ENDRX"] + #[inline(always)] + pub fn endrx(&self) -> ENDRX_R { + ENDRX_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 7 - Write '1' to enable interrupt for event TXDRDY"] + #[inline(always)] + pub fn txdrdy(&self) -> TXDRDY_R { + TXDRDY_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Write '1' to enable interrupt for event ENDTX"] + #[inline(always)] + pub fn endtx(&self) -> ENDTX_R { + ENDTX_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Write '1' to enable interrupt for event ERROR"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 17 - Write '1' to enable interrupt for event RXTO"] + #[inline(always)] + pub fn rxto(&self) -> RXTO_R { + RXTO_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 19 - Write '1' to enable interrupt for event RXSTARTED"] + #[inline(always)] + pub fn rxstarted(&self) -> RXSTARTED_R { + RXSTARTED_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Write '1' to enable interrupt for event TXSTARTED"] + #[inline(always)] + pub fn txstarted(&self) -> TXSTARTED_R { + TXSTARTED_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 22 - Write '1' to enable interrupt for event TXSTOPPED"] + #[inline(always)] + pub fn txstopped(&self) -> TXSTOPPED_R { + TXSTOPPED_R::new(((self.bits >> 22) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Write '1' to enable interrupt for event CTS"] + #[inline(always)] + pub fn cts(&mut self) -> CTS_W<0> { + CTS_W::new(self) + } + #[doc = "Bit 1 - Write '1' to enable interrupt for event NCTS"] + #[inline(always)] + pub fn ncts(&mut self) -> NCTS_W<1> { + NCTS_W::new(self) + } + #[doc = "Bit 2 - Write '1' to enable interrupt for event RXDRDY"] + #[inline(always)] + pub fn rxdrdy(&mut self) -> RXDRDY_W<2> { + RXDRDY_W::new(self) + } + #[doc = "Bit 4 - Write '1' to enable interrupt for event ENDRX"] + #[inline(always)] + pub fn endrx(&mut self) -> ENDRX_W<4> { + ENDRX_W::new(self) + } + #[doc = "Bit 7 - Write '1' to enable interrupt for event TXDRDY"] + #[inline(always)] + pub fn txdrdy(&mut self) -> TXDRDY_W<7> { + TXDRDY_W::new(self) + } + #[doc = "Bit 8 - Write '1' to enable interrupt for event ENDTX"] + #[inline(always)] + pub fn endtx(&mut self) -> ENDTX_W<8> { + ENDTX_W::new(self) + } + #[doc = "Bit 9 - Write '1' to enable interrupt for event ERROR"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W<9> { + ERROR_W::new(self) + } + #[doc = "Bit 17 - Write '1' to enable interrupt for event RXTO"] + #[inline(always)] + pub fn rxto(&mut self) -> RXTO_W<17> { + RXTO_W::new(self) + } + #[doc = "Bit 19 - Write '1' to enable interrupt for event RXSTARTED"] + #[inline(always)] + pub fn rxstarted(&mut self) -> RXSTARTED_W<19> { + RXSTARTED_W::new(self) + } + #[doc = "Bit 20 - Write '1' to enable interrupt for event TXSTARTED"] + #[inline(always)] + pub fn txstarted(&mut self) -> TXSTARTED_W<20> { + TXSTARTED_W::new(self) + } + #[doc = "Bit 22 - Write '1' to enable interrupt for event TXSTOPPED"] + #[inline(always)] + pub fn txstopped(&mut self) -> TXSTOPPED_W<22> { + TXSTOPPED_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Enable interrupt\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/uarte0_ns/psel.rs b/pacs/nrf9120-pac/src/uarte0_ns/psel.rs new file mode 100644 index 00000000..c25260e3 --- /dev/null +++ b/pacs/nrf9120-pac/src/uarte0_ns/psel.rs @@ -0,0 +1,28 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct PSEL { + #[doc = "0x00 - Pin select for RTS signal"] + pub rts: RTS, + #[doc = "0x04 - Pin select for TXD signal"] + pub txd: TXD, + #[doc = "0x08 - Pin select for CTS signal"] + pub cts: CTS, + #[doc = "0x0c - Pin select for RXD signal"] + pub rxd: RXD, +} +#[doc = "RTS (rw) register accessor: an alias for `Reg`"] +pub type RTS = crate::Reg; +#[doc = "Pin select for RTS signal"] +pub mod rts; +#[doc = "TXD (rw) register accessor: an alias for `Reg`"] +pub type TXD = crate::Reg; +#[doc = "Pin select for TXD signal"] +pub mod txd; +#[doc = "CTS (rw) register accessor: an alias for `Reg`"] +pub type CTS = crate::Reg; +#[doc = "Pin select for CTS signal"] +pub mod cts; +#[doc = "RXD (rw) register accessor: an alias for `Reg`"] +pub type RXD = crate::Reg; +#[doc = "Pin select for RXD signal"] +pub mod rxd; diff --git a/pacs/nrf9120-pac/src/uarte0_ns/psel/cts.rs b/pacs/nrf9120-pac/src/uarte0_ns/psel/cts.rs new file mode 100644 index 00000000..c2ba85b5 --- /dev/null +++ b/pacs/nrf9120-pac/src/uarte0_ns/psel/cts.rs @@ -0,0 +1,140 @@ +#[doc = "Register `CTS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PIN` reader - Pin number"] +pub type PIN_R = crate::FieldReader; +#[doc = "Field `PIN` writer - Pin number"] +pub type PIN_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CTS_SPEC, u8, u8, 5, O>; +#[doc = "Field `CONNECT` reader - Connection"] +pub type CONNECT_R = crate::BitReader; +#[doc = "Connection\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CONNECT_A { + #[doc = "1: Disconnect"] + DISCONNECTED = 1, + #[doc = "0: Connect"] + CONNECTED = 0, +} +impl From for bool { + #[inline(always)] + fn from(variant: CONNECT_A) -> Self { + variant as u8 != 0 + } +} +impl CONNECT_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CONNECT_A { + match self.bits { + true => CONNECT_A::DISCONNECTED, + false => CONNECT_A::CONNECTED, + } + } + #[doc = "Checks if the value of the field is `DISCONNECTED`"] + #[inline(always)] + pub fn is_disconnected(&self) -> bool { + *self == CONNECT_A::DISCONNECTED + } + #[doc = "Checks if the value of the field is `CONNECTED`"] + #[inline(always)] + pub fn is_connected(&self) -> bool { + *self == CONNECT_A::CONNECTED + } +} +#[doc = "Field `CONNECT` writer - Connection"] +pub type CONNECT_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTS_SPEC, CONNECT_A, O>; +impl<'a, const O: u8> CONNECT_W<'a, O> { + #[doc = "Disconnect"] + #[inline(always)] + pub fn disconnected(self) -> &'a mut W { + self.variant(CONNECT_A::DISCONNECTED) + } + #[doc = "Connect"] + #[inline(always)] + pub fn connected(self) -> &'a mut W { + self.variant(CONNECT_A::CONNECTED) + } +} +impl R { + #[doc = "Bits 0:4 - Pin number"] + #[inline(always)] + pub fn pin(&self) -> PIN_R { + PIN_R::new((self.bits & 0x1f) as u8) + } + #[doc = "Bit 31 - Connection"] + #[inline(always)] + pub fn connect(&self) -> CONNECT_R { + CONNECT_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:4 - Pin number"] + #[inline(always)] + pub fn pin(&mut self) -> PIN_W<0> { + PIN_W::new(self) + } + #[doc = "Bit 31 - Connection"] + #[inline(always)] + pub fn connect(&mut self) -> CONNECT_W<31> { + CONNECT_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Pin select for CTS signal\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cts](index.html) module"] +pub struct CTS_SPEC; +impl crate::RegisterSpec for CTS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cts::R](R) reader structure"] +impl crate::Readable for CTS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [cts::W](W) writer structure"] +impl crate::Writable for CTS_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTS to value 0xffff_ffff"] +impl crate::Resettable for CTS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0xffff_ffff + } +} diff --git a/pacs/nrf9120-pac/src/uarte0_ns/psel/rts.rs b/pacs/nrf9120-pac/src/uarte0_ns/psel/rts.rs new file mode 100644 index 00000000..05159d23 --- /dev/null +++ b/pacs/nrf9120-pac/src/uarte0_ns/psel/rts.rs @@ -0,0 +1,140 @@ +#[doc = "Register `RTS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `RTS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PIN` reader - Pin number"] +pub type PIN_R = crate::FieldReader; +#[doc = "Field `PIN` writer - Pin number"] +pub type PIN_W<'a, const O: u8> = crate::FieldWriter<'a, u32, RTS_SPEC, u8, u8, 5, O>; +#[doc = "Field `CONNECT` reader - Connection"] +pub type CONNECT_R = crate::BitReader; +#[doc = "Connection\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CONNECT_A { + #[doc = "1: Disconnect"] + DISCONNECTED = 1, + #[doc = "0: Connect"] + CONNECTED = 0, +} +impl From for bool { + #[inline(always)] + fn from(variant: CONNECT_A) -> Self { + variant as u8 != 0 + } +} +impl CONNECT_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CONNECT_A { + match self.bits { + true => CONNECT_A::DISCONNECTED, + false => CONNECT_A::CONNECTED, + } + } + #[doc = "Checks if the value of the field is `DISCONNECTED`"] + #[inline(always)] + pub fn is_disconnected(&self) -> bool { + *self == CONNECT_A::DISCONNECTED + } + #[doc = "Checks if the value of the field is `CONNECTED`"] + #[inline(always)] + pub fn is_connected(&self) -> bool { + *self == CONNECT_A::CONNECTED + } +} +#[doc = "Field `CONNECT` writer - Connection"] +pub type CONNECT_W<'a, const O: u8> = crate::BitWriter<'a, u32, RTS_SPEC, CONNECT_A, O>; +impl<'a, const O: u8> CONNECT_W<'a, O> { + #[doc = "Disconnect"] + #[inline(always)] + pub fn disconnected(self) -> &'a mut W { + self.variant(CONNECT_A::DISCONNECTED) + } + #[doc = "Connect"] + #[inline(always)] + pub fn connected(self) -> &'a mut W { + self.variant(CONNECT_A::CONNECTED) + } +} +impl R { + #[doc = "Bits 0:4 - Pin number"] + #[inline(always)] + pub fn pin(&self) -> PIN_R { + PIN_R::new((self.bits & 0x1f) as u8) + } + #[doc = "Bit 31 - Connection"] + #[inline(always)] + pub fn connect(&self) -> CONNECT_R { + CONNECT_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:4 - Pin number"] + #[inline(always)] + pub fn pin(&mut self) -> PIN_W<0> { + PIN_W::new(self) + } + #[doc = "Bit 31 - Connection"] + #[inline(always)] + pub fn connect(&mut self) -> CONNECT_W<31> { + CONNECT_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Pin select for RTS signal\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rts](index.html) module"] +pub struct RTS_SPEC; +impl crate::RegisterSpec for RTS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [rts::R](R) reader structure"] +impl crate::Readable for RTS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [rts::W](W) writer structure"] +impl crate::Writable for RTS_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets RTS to value 0xffff_ffff"] +impl crate::Resettable for RTS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0xffff_ffff + } +} diff --git a/pacs/nrf9120-pac/src/uarte0_ns/psel/rxd.rs b/pacs/nrf9120-pac/src/uarte0_ns/psel/rxd.rs new file mode 100644 index 00000000..7d4c0c26 --- /dev/null +++ b/pacs/nrf9120-pac/src/uarte0_ns/psel/rxd.rs @@ -0,0 +1,140 @@ +#[doc = "Register `RXD` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `RXD` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PIN` reader - Pin number"] +pub type PIN_R = crate::FieldReader; +#[doc = "Field `PIN` writer - Pin number"] +pub type PIN_W<'a, const O: u8> = crate::FieldWriter<'a, u32, RXD_SPEC, u8, u8, 5, O>; +#[doc = "Field `CONNECT` reader - Connection"] +pub type CONNECT_R = crate::BitReader; +#[doc = "Connection\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CONNECT_A { + #[doc = "1: Disconnect"] + DISCONNECTED = 1, + #[doc = "0: Connect"] + CONNECTED = 0, +} +impl From for bool { + #[inline(always)] + fn from(variant: CONNECT_A) -> Self { + variant as u8 != 0 + } +} +impl CONNECT_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CONNECT_A { + match self.bits { + true => CONNECT_A::DISCONNECTED, + false => CONNECT_A::CONNECTED, + } + } + #[doc = "Checks if the value of the field is `DISCONNECTED`"] + #[inline(always)] + pub fn is_disconnected(&self) -> bool { + *self == CONNECT_A::DISCONNECTED + } + #[doc = "Checks if the value of the field is `CONNECTED`"] + #[inline(always)] + pub fn is_connected(&self) -> bool { + *self == CONNECT_A::CONNECTED + } +} +#[doc = "Field `CONNECT` writer - Connection"] +pub type CONNECT_W<'a, const O: u8> = crate::BitWriter<'a, u32, RXD_SPEC, CONNECT_A, O>; +impl<'a, const O: u8> CONNECT_W<'a, O> { + #[doc = "Disconnect"] + #[inline(always)] + pub fn disconnected(self) -> &'a mut W { + self.variant(CONNECT_A::DISCONNECTED) + } + #[doc = "Connect"] + #[inline(always)] + pub fn connected(self) -> &'a mut W { + self.variant(CONNECT_A::CONNECTED) + } +} +impl R { + #[doc = "Bits 0:4 - Pin number"] + #[inline(always)] + pub fn pin(&self) -> PIN_R { + PIN_R::new((self.bits & 0x1f) as u8) + } + #[doc = "Bit 31 - Connection"] + #[inline(always)] + pub fn connect(&self) -> CONNECT_R { + CONNECT_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:4 - Pin number"] + #[inline(always)] + pub fn pin(&mut self) -> PIN_W<0> { + PIN_W::new(self) + } + #[doc = "Bit 31 - Connection"] + #[inline(always)] + pub fn connect(&mut self) -> CONNECT_W<31> { + CONNECT_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Pin select for RXD signal\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rxd](index.html) module"] +pub struct RXD_SPEC; +impl crate::RegisterSpec for RXD_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [rxd::R](R) reader structure"] +impl crate::Readable for RXD_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [rxd::W](W) writer structure"] +impl crate::Writable for RXD_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets RXD to value 0xffff_ffff"] +impl crate::Resettable for RXD_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0xffff_ffff + } +} diff --git a/pacs/nrf9120-pac/src/uarte0_ns/psel/txd.rs b/pacs/nrf9120-pac/src/uarte0_ns/psel/txd.rs new file mode 100644 index 00000000..2f456c32 --- /dev/null +++ b/pacs/nrf9120-pac/src/uarte0_ns/psel/txd.rs @@ -0,0 +1,140 @@ +#[doc = "Register `TXD` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `TXD` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PIN` reader - Pin number"] +pub type PIN_R = crate::FieldReader; +#[doc = "Field `PIN` writer - Pin number"] +pub type PIN_W<'a, const O: u8> = crate::FieldWriter<'a, u32, TXD_SPEC, u8, u8, 5, O>; +#[doc = "Field `CONNECT` reader - Connection"] +pub type CONNECT_R = crate::BitReader; +#[doc = "Connection\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CONNECT_A { + #[doc = "1: Disconnect"] + DISCONNECTED = 1, + #[doc = "0: Connect"] + CONNECTED = 0, +} +impl From for bool { + #[inline(always)] + fn from(variant: CONNECT_A) -> Self { + variant as u8 != 0 + } +} +impl CONNECT_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CONNECT_A { + match self.bits { + true => CONNECT_A::DISCONNECTED, + false => CONNECT_A::CONNECTED, + } + } + #[doc = "Checks if the value of the field is `DISCONNECTED`"] + #[inline(always)] + pub fn is_disconnected(&self) -> bool { + *self == CONNECT_A::DISCONNECTED + } + #[doc = "Checks if the value of the field is `CONNECTED`"] + #[inline(always)] + pub fn is_connected(&self) -> bool { + *self == CONNECT_A::CONNECTED + } +} +#[doc = "Field `CONNECT` writer - Connection"] +pub type CONNECT_W<'a, const O: u8> = crate::BitWriter<'a, u32, TXD_SPEC, CONNECT_A, O>; +impl<'a, const O: u8> CONNECT_W<'a, O> { + #[doc = "Disconnect"] + #[inline(always)] + pub fn disconnected(self) -> &'a mut W { + self.variant(CONNECT_A::DISCONNECTED) + } + #[doc = "Connect"] + #[inline(always)] + pub fn connected(self) -> &'a mut W { + self.variant(CONNECT_A::CONNECTED) + } +} +impl R { + #[doc = "Bits 0:4 - Pin number"] + #[inline(always)] + pub fn pin(&self) -> PIN_R { + PIN_R::new((self.bits & 0x1f) as u8) + } + #[doc = "Bit 31 - Connection"] + #[inline(always)] + pub fn connect(&self) -> CONNECT_R { + CONNECT_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:4 - Pin number"] + #[inline(always)] + pub fn pin(&mut self) -> PIN_W<0> { + PIN_W::new(self) + } + #[doc = "Bit 31 - Connection"] + #[inline(always)] + pub fn connect(&mut self) -> CONNECT_W<31> { + CONNECT_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Pin select for TXD signal\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [txd](index.html) module"] +pub struct TXD_SPEC; +impl crate::RegisterSpec for TXD_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [txd::R](R) reader structure"] +impl crate::Readable for TXD_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [txd::W](W) writer structure"] +impl crate::Writable for TXD_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets TXD to value 0xffff_ffff"] +impl crate::Resettable for TXD_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0xffff_ffff + } +} diff --git a/pacs/nrf9120-pac/src/uarte0_ns/publish_cts.rs b/pacs/nrf9120-pac/src/uarte0_ns/publish_cts.rs new file mode 100644 index 00000000..11956e51 --- /dev/null +++ b/pacs/nrf9120-pac/src/uarte0_ns/publish_cts.rs @@ -0,0 +1,140 @@ +#[doc = "Register `PUBLISH_CTS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PUBLISH_CTS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CHIDX` reader - DPPI channel that event CTS will publish to"] +pub type CHIDX_R = crate::FieldReader; +#[doc = "Field `CHIDX` writer - DPPI channel that event CTS will publish to"] +pub type CHIDX_W<'a, const O: u8> = crate::FieldWriter<'a, u32, PUBLISH_CTS_SPEC, u8, u8, 8, O>; +#[doc = "Field `EN` reader - "] +pub type EN_R = crate::BitReader; +#[doc = "\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum EN_A { + #[doc = "0: Disable publishing"] + DISABLED = 0, + #[doc = "1: Enable publishing"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: EN_A) -> Self { + variant as u8 != 0 + } +} +impl EN_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EN_A { + match self.bits { + false => EN_A::DISABLED, + true => EN_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == EN_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == EN_A::ENABLED + } +} +#[doc = "Field `EN` writer - "] +pub type EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, PUBLISH_CTS_SPEC, EN_A, O>; +impl<'a, const O: u8> EN_W<'a, O> { + #[doc = "Disable publishing"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(EN_A::DISABLED) + } + #[doc = "Enable publishing"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(EN_A::ENABLED) + } +} +impl R { + #[doc = "Bits 0:7 - DPPI channel that event CTS will publish to"] + #[inline(always)] + pub fn chidx(&self) -> CHIDX_R { + CHIDX_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&self) -> EN_R { + EN_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:7 - DPPI channel that event CTS will publish to"] + #[inline(always)] + pub fn chidx(&mut self) -> CHIDX_W<0> { + CHIDX_W::new(self) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&mut self) -> EN_W<31> { + EN_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Publish configuration for event CTS\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [publish_cts](index.html) module"] +pub struct PUBLISH_CTS_SPEC; +impl crate::RegisterSpec for PUBLISH_CTS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [publish_cts::R](R) reader structure"] +impl crate::Readable for PUBLISH_CTS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [publish_cts::W](W) writer structure"] +impl crate::Writable for PUBLISH_CTS_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PUBLISH_CTS to value 0"] +impl crate::Resettable for PUBLISH_CTS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/uarte0_ns/publish_endrx.rs b/pacs/nrf9120-pac/src/uarte0_ns/publish_endrx.rs new file mode 100644 index 00000000..1c25570b --- /dev/null +++ b/pacs/nrf9120-pac/src/uarte0_ns/publish_endrx.rs @@ -0,0 +1,140 @@ +#[doc = "Register `PUBLISH_ENDRX` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PUBLISH_ENDRX` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CHIDX` reader - DPPI channel that event ENDRX will publish to"] +pub type CHIDX_R = crate::FieldReader; +#[doc = "Field `CHIDX` writer - DPPI channel that event ENDRX will publish to"] +pub type CHIDX_W<'a, const O: u8> = crate::FieldWriter<'a, u32, PUBLISH_ENDRX_SPEC, u8, u8, 8, O>; +#[doc = "Field `EN` reader - "] +pub type EN_R = crate::BitReader; +#[doc = "\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum EN_A { + #[doc = "0: Disable publishing"] + DISABLED = 0, + #[doc = "1: Enable publishing"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: EN_A) -> Self { + variant as u8 != 0 + } +} +impl EN_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EN_A { + match self.bits { + false => EN_A::DISABLED, + true => EN_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == EN_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == EN_A::ENABLED + } +} +#[doc = "Field `EN` writer - "] +pub type EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, PUBLISH_ENDRX_SPEC, EN_A, O>; +impl<'a, const O: u8> EN_W<'a, O> { + #[doc = "Disable publishing"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(EN_A::DISABLED) + } + #[doc = "Enable publishing"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(EN_A::ENABLED) + } +} +impl R { + #[doc = "Bits 0:7 - DPPI channel that event ENDRX will publish to"] + #[inline(always)] + pub fn chidx(&self) -> CHIDX_R { + CHIDX_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&self) -> EN_R { + EN_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:7 - DPPI channel that event ENDRX will publish to"] + #[inline(always)] + pub fn chidx(&mut self) -> CHIDX_W<0> { + CHIDX_W::new(self) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&mut self) -> EN_W<31> { + EN_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Publish configuration for event ENDRX\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [publish_endrx](index.html) module"] +pub struct PUBLISH_ENDRX_SPEC; +impl crate::RegisterSpec for PUBLISH_ENDRX_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [publish_endrx::R](R) reader structure"] +impl crate::Readable for PUBLISH_ENDRX_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [publish_endrx::W](W) writer structure"] +impl crate::Writable for PUBLISH_ENDRX_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PUBLISH_ENDRX to value 0"] +impl crate::Resettable for PUBLISH_ENDRX_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/uarte0_ns/publish_endtx.rs b/pacs/nrf9120-pac/src/uarte0_ns/publish_endtx.rs new file mode 100644 index 00000000..ebaa02ca --- /dev/null +++ b/pacs/nrf9120-pac/src/uarte0_ns/publish_endtx.rs @@ -0,0 +1,140 @@ +#[doc = "Register `PUBLISH_ENDTX` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PUBLISH_ENDTX` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CHIDX` reader - DPPI channel that event ENDTX will publish to"] +pub type CHIDX_R = crate::FieldReader; +#[doc = "Field `CHIDX` writer - DPPI channel that event ENDTX will publish to"] +pub type CHIDX_W<'a, const O: u8> = crate::FieldWriter<'a, u32, PUBLISH_ENDTX_SPEC, u8, u8, 8, O>; +#[doc = "Field `EN` reader - "] +pub type EN_R = crate::BitReader; +#[doc = "\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum EN_A { + #[doc = "0: Disable publishing"] + DISABLED = 0, + #[doc = "1: Enable publishing"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: EN_A) -> Self { + variant as u8 != 0 + } +} +impl EN_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EN_A { + match self.bits { + false => EN_A::DISABLED, + true => EN_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == EN_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == EN_A::ENABLED + } +} +#[doc = "Field `EN` writer - "] +pub type EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, PUBLISH_ENDTX_SPEC, EN_A, O>; +impl<'a, const O: u8> EN_W<'a, O> { + #[doc = "Disable publishing"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(EN_A::DISABLED) + } + #[doc = "Enable publishing"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(EN_A::ENABLED) + } +} +impl R { + #[doc = "Bits 0:7 - DPPI channel that event ENDTX will publish to"] + #[inline(always)] + pub fn chidx(&self) -> CHIDX_R { + CHIDX_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&self) -> EN_R { + EN_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:7 - DPPI channel that event ENDTX will publish to"] + #[inline(always)] + pub fn chidx(&mut self) -> CHIDX_W<0> { + CHIDX_W::new(self) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&mut self) -> EN_W<31> { + EN_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Publish configuration for event ENDTX\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [publish_endtx](index.html) module"] +pub struct PUBLISH_ENDTX_SPEC; +impl crate::RegisterSpec for PUBLISH_ENDTX_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [publish_endtx::R](R) reader structure"] +impl crate::Readable for PUBLISH_ENDTX_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [publish_endtx::W](W) writer structure"] +impl crate::Writable for PUBLISH_ENDTX_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PUBLISH_ENDTX to value 0"] +impl crate::Resettable for PUBLISH_ENDTX_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/uarte0_ns/publish_error.rs b/pacs/nrf9120-pac/src/uarte0_ns/publish_error.rs new file mode 100644 index 00000000..b8934693 --- /dev/null +++ b/pacs/nrf9120-pac/src/uarte0_ns/publish_error.rs @@ -0,0 +1,140 @@ +#[doc = "Register `PUBLISH_ERROR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PUBLISH_ERROR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CHIDX` reader - DPPI channel that event ERROR will publish to"] +pub type CHIDX_R = crate::FieldReader; +#[doc = "Field `CHIDX` writer - DPPI channel that event ERROR will publish to"] +pub type CHIDX_W<'a, const O: u8> = crate::FieldWriter<'a, u32, PUBLISH_ERROR_SPEC, u8, u8, 8, O>; +#[doc = "Field `EN` reader - "] +pub type EN_R = crate::BitReader; +#[doc = "\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum EN_A { + #[doc = "0: Disable publishing"] + DISABLED = 0, + #[doc = "1: Enable publishing"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: EN_A) -> Self { + variant as u8 != 0 + } +} +impl EN_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EN_A { + match self.bits { + false => EN_A::DISABLED, + true => EN_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == EN_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == EN_A::ENABLED + } +} +#[doc = "Field `EN` writer - "] +pub type EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, PUBLISH_ERROR_SPEC, EN_A, O>; +impl<'a, const O: u8> EN_W<'a, O> { + #[doc = "Disable publishing"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(EN_A::DISABLED) + } + #[doc = "Enable publishing"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(EN_A::ENABLED) + } +} +impl R { + #[doc = "Bits 0:7 - DPPI channel that event ERROR will publish to"] + #[inline(always)] + pub fn chidx(&self) -> CHIDX_R { + CHIDX_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&self) -> EN_R { + EN_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:7 - DPPI channel that event ERROR will publish to"] + #[inline(always)] + pub fn chidx(&mut self) -> CHIDX_W<0> { + CHIDX_W::new(self) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&mut self) -> EN_W<31> { + EN_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Publish configuration for event ERROR\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [publish_error](index.html) module"] +pub struct PUBLISH_ERROR_SPEC; +impl crate::RegisterSpec for PUBLISH_ERROR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [publish_error::R](R) reader structure"] +impl crate::Readable for PUBLISH_ERROR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [publish_error::W](W) writer structure"] +impl crate::Writable for PUBLISH_ERROR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PUBLISH_ERROR to value 0"] +impl crate::Resettable for PUBLISH_ERROR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/uarte0_ns/publish_ncts.rs b/pacs/nrf9120-pac/src/uarte0_ns/publish_ncts.rs new file mode 100644 index 00000000..4acddf37 --- /dev/null +++ b/pacs/nrf9120-pac/src/uarte0_ns/publish_ncts.rs @@ -0,0 +1,140 @@ +#[doc = "Register `PUBLISH_NCTS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PUBLISH_NCTS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CHIDX` reader - DPPI channel that event NCTS will publish to"] +pub type CHIDX_R = crate::FieldReader; +#[doc = "Field `CHIDX` writer - DPPI channel that event NCTS will publish to"] +pub type CHIDX_W<'a, const O: u8> = crate::FieldWriter<'a, u32, PUBLISH_NCTS_SPEC, u8, u8, 8, O>; +#[doc = "Field `EN` reader - "] +pub type EN_R = crate::BitReader; +#[doc = "\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum EN_A { + #[doc = "0: Disable publishing"] + DISABLED = 0, + #[doc = "1: Enable publishing"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: EN_A) -> Self { + variant as u8 != 0 + } +} +impl EN_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EN_A { + match self.bits { + false => EN_A::DISABLED, + true => EN_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == EN_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == EN_A::ENABLED + } +} +#[doc = "Field `EN` writer - "] +pub type EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, PUBLISH_NCTS_SPEC, EN_A, O>; +impl<'a, const O: u8> EN_W<'a, O> { + #[doc = "Disable publishing"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(EN_A::DISABLED) + } + #[doc = "Enable publishing"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(EN_A::ENABLED) + } +} +impl R { + #[doc = "Bits 0:7 - DPPI channel that event NCTS will publish to"] + #[inline(always)] + pub fn chidx(&self) -> CHIDX_R { + CHIDX_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&self) -> EN_R { + EN_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:7 - DPPI channel that event NCTS will publish to"] + #[inline(always)] + pub fn chidx(&mut self) -> CHIDX_W<0> { + CHIDX_W::new(self) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&mut self) -> EN_W<31> { + EN_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Publish configuration for event NCTS\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [publish_ncts](index.html) module"] +pub struct PUBLISH_NCTS_SPEC; +impl crate::RegisterSpec for PUBLISH_NCTS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [publish_ncts::R](R) reader structure"] +impl crate::Readable for PUBLISH_NCTS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [publish_ncts::W](W) writer structure"] +impl crate::Writable for PUBLISH_NCTS_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PUBLISH_NCTS to value 0"] +impl crate::Resettable for PUBLISH_NCTS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/uarte0_ns/publish_rxdrdy.rs b/pacs/nrf9120-pac/src/uarte0_ns/publish_rxdrdy.rs new file mode 100644 index 00000000..ed59bdcf --- /dev/null +++ b/pacs/nrf9120-pac/src/uarte0_ns/publish_rxdrdy.rs @@ -0,0 +1,140 @@ +#[doc = "Register `PUBLISH_RXDRDY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PUBLISH_RXDRDY` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CHIDX` reader - DPPI channel that event RXDRDY will publish to"] +pub type CHIDX_R = crate::FieldReader; +#[doc = "Field `CHIDX` writer - DPPI channel that event RXDRDY will publish to"] +pub type CHIDX_W<'a, const O: u8> = crate::FieldWriter<'a, u32, PUBLISH_RXDRDY_SPEC, u8, u8, 8, O>; +#[doc = "Field `EN` reader - "] +pub type EN_R = crate::BitReader; +#[doc = "\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum EN_A { + #[doc = "0: Disable publishing"] + DISABLED = 0, + #[doc = "1: Enable publishing"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: EN_A) -> Self { + variant as u8 != 0 + } +} +impl EN_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EN_A { + match self.bits { + false => EN_A::DISABLED, + true => EN_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == EN_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == EN_A::ENABLED + } +} +#[doc = "Field `EN` writer - "] +pub type EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, PUBLISH_RXDRDY_SPEC, EN_A, O>; +impl<'a, const O: u8> EN_W<'a, O> { + #[doc = "Disable publishing"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(EN_A::DISABLED) + } + #[doc = "Enable publishing"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(EN_A::ENABLED) + } +} +impl R { + #[doc = "Bits 0:7 - DPPI channel that event RXDRDY will publish to"] + #[inline(always)] + pub fn chidx(&self) -> CHIDX_R { + CHIDX_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&self) -> EN_R { + EN_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:7 - DPPI channel that event RXDRDY will publish to"] + #[inline(always)] + pub fn chidx(&mut self) -> CHIDX_W<0> { + CHIDX_W::new(self) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&mut self) -> EN_W<31> { + EN_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Publish configuration for event RXDRDY\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [publish_rxdrdy](index.html) module"] +pub struct PUBLISH_RXDRDY_SPEC; +impl crate::RegisterSpec for PUBLISH_RXDRDY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [publish_rxdrdy::R](R) reader structure"] +impl crate::Readable for PUBLISH_RXDRDY_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [publish_rxdrdy::W](W) writer structure"] +impl crate::Writable for PUBLISH_RXDRDY_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PUBLISH_RXDRDY to value 0"] +impl crate::Resettable for PUBLISH_RXDRDY_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/uarte0_ns/publish_rxstarted.rs b/pacs/nrf9120-pac/src/uarte0_ns/publish_rxstarted.rs new file mode 100644 index 00000000..c0328382 --- /dev/null +++ b/pacs/nrf9120-pac/src/uarte0_ns/publish_rxstarted.rs @@ -0,0 +1,141 @@ +#[doc = "Register `PUBLISH_RXSTARTED` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PUBLISH_RXSTARTED` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CHIDX` reader - DPPI channel that event RXSTARTED will publish to"] +pub type CHIDX_R = crate::FieldReader; +#[doc = "Field `CHIDX` writer - DPPI channel that event RXSTARTED will publish to"] +pub type CHIDX_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, PUBLISH_RXSTARTED_SPEC, u8, u8, 8, O>; +#[doc = "Field `EN` reader - "] +pub type EN_R = crate::BitReader; +#[doc = "\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum EN_A { + #[doc = "0: Disable publishing"] + DISABLED = 0, + #[doc = "1: Enable publishing"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: EN_A) -> Self { + variant as u8 != 0 + } +} +impl EN_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EN_A { + match self.bits { + false => EN_A::DISABLED, + true => EN_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == EN_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == EN_A::ENABLED + } +} +#[doc = "Field `EN` writer - "] +pub type EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, PUBLISH_RXSTARTED_SPEC, EN_A, O>; +impl<'a, const O: u8> EN_W<'a, O> { + #[doc = "Disable publishing"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(EN_A::DISABLED) + } + #[doc = "Enable publishing"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(EN_A::ENABLED) + } +} +impl R { + #[doc = "Bits 0:7 - DPPI channel that event RXSTARTED will publish to"] + #[inline(always)] + pub fn chidx(&self) -> CHIDX_R { + CHIDX_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&self) -> EN_R { + EN_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:7 - DPPI channel that event RXSTARTED will publish to"] + #[inline(always)] + pub fn chidx(&mut self) -> CHIDX_W<0> { + CHIDX_W::new(self) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&mut self) -> EN_W<31> { + EN_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Publish configuration for event RXSTARTED\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [publish_rxstarted](index.html) module"] +pub struct PUBLISH_RXSTARTED_SPEC; +impl crate::RegisterSpec for PUBLISH_RXSTARTED_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [publish_rxstarted::R](R) reader structure"] +impl crate::Readable for PUBLISH_RXSTARTED_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [publish_rxstarted::W](W) writer structure"] +impl crate::Writable for PUBLISH_RXSTARTED_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PUBLISH_RXSTARTED to value 0"] +impl crate::Resettable for PUBLISH_RXSTARTED_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/uarte0_ns/publish_rxto.rs b/pacs/nrf9120-pac/src/uarte0_ns/publish_rxto.rs new file mode 100644 index 00000000..84c9525a --- /dev/null +++ b/pacs/nrf9120-pac/src/uarte0_ns/publish_rxto.rs @@ -0,0 +1,140 @@ +#[doc = "Register `PUBLISH_RXTO` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PUBLISH_RXTO` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CHIDX` reader - DPPI channel that event RXTO will publish to"] +pub type CHIDX_R = crate::FieldReader; +#[doc = "Field `CHIDX` writer - DPPI channel that event RXTO will publish to"] +pub type CHIDX_W<'a, const O: u8> = crate::FieldWriter<'a, u32, PUBLISH_RXTO_SPEC, u8, u8, 8, O>; +#[doc = "Field `EN` reader - "] +pub type EN_R = crate::BitReader; +#[doc = "\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum EN_A { + #[doc = "0: Disable publishing"] + DISABLED = 0, + #[doc = "1: Enable publishing"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: EN_A) -> Self { + variant as u8 != 0 + } +} +impl EN_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EN_A { + match self.bits { + false => EN_A::DISABLED, + true => EN_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == EN_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == EN_A::ENABLED + } +} +#[doc = "Field `EN` writer - "] +pub type EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, PUBLISH_RXTO_SPEC, EN_A, O>; +impl<'a, const O: u8> EN_W<'a, O> { + #[doc = "Disable publishing"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(EN_A::DISABLED) + } + #[doc = "Enable publishing"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(EN_A::ENABLED) + } +} +impl R { + #[doc = "Bits 0:7 - DPPI channel that event RXTO will publish to"] + #[inline(always)] + pub fn chidx(&self) -> CHIDX_R { + CHIDX_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&self) -> EN_R { + EN_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:7 - DPPI channel that event RXTO will publish to"] + #[inline(always)] + pub fn chidx(&mut self) -> CHIDX_W<0> { + CHIDX_W::new(self) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&mut self) -> EN_W<31> { + EN_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Publish configuration for event RXTO\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [publish_rxto](index.html) module"] +pub struct PUBLISH_RXTO_SPEC; +impl crate::RegisterSpec for PUBLISH_RXTO_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [publish_rxto::R](R) reader structure"] +impl crate::Readable for PUBLISH_RXTO_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [publish_rxto::W](W) writer structure"] +impl crate::Writable for PUBLISH_RXTO_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PUBLISH_RXTO to value 0"] +impl crate::Resettable for PUBLISH_RXTO_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/uarte0_ns/publish_txdrdy.rs b/pacs/nrf9120-pac/src/uarte0_ns/publish_txdrdy.rs new file mode 100644 index 00000000..41213935 --- /dev/null +++ b/pacs/nrf9120-pac/src/uarte0_ns/publish_txdrdy.rs @@ -0,0 +1,140 @@ +#[doc = "Register `PUBLISH_TXDRDY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PUBLISH_TXDRDY` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CHIDX` reader - DPPI channel that event TXDRDY will publish to"] +pub type CHIDX_R = crate::FieldReader; +#[doc = "Field `CHIDX` writer - DPPI channel that event TXDRDY will publish to"] +pub type CHIDX_W<'a, const O: u8> = crate::FieldWriter<'a, u32, PUBLISH_TXDRDY_SPEC, u8, u8, 8, O>; +#[doc = "Field `EN` reader - "] +pub type EN_R = crate::BitReader; +#[doc = "\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum EN_A { + #[doc = "0: Disable publishing"] + DISABLED = 0, + #[doc = "1: Enable publishing"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: EN_A) -> Self { + variant as u8 != 0 + } +} +impl EN_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EN_A { + match self.bits { + false => EN_A::DISABLED, + true => EN_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == EN_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == EN_A::ENABLED + } +} +#[doc = "Field `EN` writer - "] +pub type EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, PUBLISH_TXDRDY_SPEC, EN_A, O>; +impl<'a, const O: u8> EN_W<'a, O> { + #[doc = "Disable publishing"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(EN_A::DISABLED) + } + #[doc = "Enable publishing"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(EN_A::ENABLED) + } +} +impl R { + #[doc = "Bits 0:7 - DPPI channel that event TXDRDY will publish to"] + #[inline(always)] + pub fn chidx(&self) -> CHIDX_R { + CHIDX_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&self) -> EN_R { + EN_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:7 - DPPI channel that event TXDRDY will publish to"] + #[inline(always)] + pub fn chidx(&mut self) -> CHIDX_W<0> { + CHIDX_W::new(self) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&mut self) -> EN_W<31> { + EN_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Publish configuration for event TXDRDY\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [publish_txdrdy](index.html) module"] +pub struct PUBLISH_TXDRDY_SPEC; +impl crate::RegisterSpec for PUBLISH_TXDRDY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [publish_txdrdy::R](R) reader structure"] +impl crate::Readable for PUBLISH_TXDRDY_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [publish_txdrdy::W](W) writer structure"] +impl crate::Writable for PUBLISH_TXDRDY_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PUBLISH_TXDRDY to value 0"] +impl crate::Resettable for PUBLISH_TXDRDY_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/uarte0_ns/publish_txstarted.rs b/pacs/nrf9120-pac/src/uarte0_ns/publish_txstarted.rs new file mode 100644 index 00000000..2d049893 --- /dev/null +++ b/pacs/nrf9120-pac/src/uarte0_ns/publish_txstarted.rs @@ -0,0 +1,141 @@ +#[doc = "Register `PUBLISH_TXSTARTED` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PUBLISH_TXSTARTED` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CHIDX` reader - DPPI channel that event TXSTARTED will publish to"] +pub type CHIDX_R = crate::FieldReader; +#[doc = "Field `CHIDX` writer - DPPI channel that event TXSTARTED will publish to"] +pub type CHIDX_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, PUBLISH_TXSTARTED_SPEC, u8, u8, 8, O>; +#[doc = "Field `EN` reader - "] +pub type EN_R = crate::BitReader; +#[doc = "\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum EN_A { + #[doc = "0: Disable publishing"] + DISABLED = 0, + #[doc = "1: Enable publishing"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: EN_A) -> Self { + variant as u8 != 0 + } +} +impl EN_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EN_A { + match self.bits { + false => EN_A::DISABLED, + true => EN_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == EN_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == EN_A::ENABLED + } +} +#[doc = "Field `EN` writer - "] +pub type EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, PUBLISH_TXSTARTED_SPEC, EN_A, O>; +impl<'a, const O: u8> EN_W<'a, O> { + #[doc = "Disable publishing"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(EN_A::DISABLED) + } + #[doc = "Enable publishing"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(EN_A::ENABLED) + } +} +impl R { + #[doc = "Bits 0:7 - DPPI channel that event TXSTARTED will publish to"] + #[inline(always)] + pub fn chidx(&self) -> CHIDX_R { + CHIDX_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&self) -> EN_R { + EN_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:7 - DPPI channel that event TXSTARTED will publish to"] + #[inline(always)] + pub fn chidx(&mut self) -> CHIDX_W<0> { + CHIDX_W::new(self) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&mut self) -> EN_W<31> { + EN_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Publish configuration for event TXSTARTED\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [publish_txstarted](index.html) module"] +pub struct PUBLISH_TXSTARTED_SPEC; +impl crate::RegisterSpec for PUBLISH_TXSTARTED_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [publish_txstarted::R](R) reader structure"] +impl crate::Readable for PUBLISH_TXSTARTED_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [publish_txstarted::W](W) writer structure"] +impl crate::Writable for PUBLISH_TXSTARTED_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PUBLISH_TXSTARTED to value 0"] +impl crate::Resettable for PUBLISH_TXSTARTED_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/uarte0_ns/publish_txstopped.rs b/pacs/nrf9120-pac/src/uarte0_ns/publish_txstopped.rs new file mode 100644 index 00000000..3acfa9ea --- /dev/null +++ b/pacs/nrf9120-pac/src/uarte0_ns/publish_txstopped.rs @@ -0,0 +1,141 @@ +#[doc = "Register `PUBLISH_TXSTOPPED` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PUBLISH_TXSTOPPED` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CHIDX` reader - DPPI channel that event TXSTOPPED will publish to"] +pub type CHIDX_R = crate::FieldReader; +#[doc = "Field `CHIDX` writer - DPPI channel that event TXSTOPPED will publish to"] +pub type CHIDX_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, PUBLISH_TXSTOPPED_SPEC, u8, u8, 8, O>; +#[doc = "Field `EN` reader - "] +pub type EN_R = crate::BitReader; +#[doc = "\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum EN_A { + #[doc = "0: Disable publishing"] + DISABLED = 0, + #[doc = "1: Enable publishing"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: EN_A) -> Self { + variant as u8 != 0 + } +} +impl EN_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EN_A { + match self.bits { + false => EN_A::DISABLED, + true => EN_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == EN_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == EN_A::ENABLED + } +} +#[doc = "Field `EN` writer - "] +pub type EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, PUBLISH_TXSTOPPED_SPEC, EN_A, O>; +impl<'a, const O: u8> EN_W<'a, O> { + #[doc = "Disable publishing"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(EN_A::DISABLED) + } + #[doc = "Enable publishing"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(EN_A::ENABLED) + } +} +impl R { + #[doc = "Bits 0:7 - DPPI channel that event TXSTOPPED will publish to"] + #[inline(always)] + pub fn chidx(&self) -> CHIDX_R { + CHIDX_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&self) -> EN_R { + EN_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:7 - DPPI channel that event TXSTOPPED will publish to"] + #[inline(always)] + pub fn chidx(&mut self) -> CHIDX_W<0> { + CHIDX_W::new(self) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&mut self) -> EN_W<31> { + EN_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Publish configuration for event TXSTOPPED\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [publish_txstopped](index.html) module"] +pub struct PUBLISH_TXSTOPPED_SPEC; +impl crate::RegisterSpec for PUBLISH_TXSTOPPED_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [publish_txstopped::R](R) reader structure"] +impl crate::Readable for PUBLISH_TXSTOPPED_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [publish_txstopped::W](W) writer structure"] +impl crate::Writable for PUBLISH_TXSTOPPED_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PUBLISH_TXSTOPPED to value 0"] +impl crate::Resettable for PUBLISH_TXSTOPPED_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/uarte0_ns/rxd.rs b/pacs/nrf9120-pac/src/uarte0_ns/rxd.rs new file mode 100644 index 00000000..e4c73ce6 --- /dev/null +++ b/pacs/nrf9120-pac/src/uarte0_ns/rxd.rs @@ -0,0 +1,22 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RXD { + #[doc = "0x00 - Data pointer"] + pub ptr: PTR, + #[doc = "0x04 - Maximum number of bytes in receive buffer"] + pub maxcnt: MAXCNT, + #[doc = "0x08 - Number of bytes transferred in the last transaction"] + pub amount: AMOUNT, +} +#[doc = "PTR (rw) register accessor: an alias for `Reg`"] +pub type PTR = crate::Reg; +#[doc = "Data pointer"] +pub mod ptr; +#[doc = "MAXCNT (rw) register accessor: an alias for `Reg`"] +pub type MAXCNT = crate::Reg; +#[doc = "Maximum number of bytes in receive buffer"] +pub mod maxcnt; +#[doc = "AMOUNT (r) register accessor: an alias for `Reg`"] +pub type AMOUNT = crate::Reg; +#[doc = "Number of bytes transferred in the last transaction"] +pub mod amount; diff --git a/pacs/nrf9120-pac/src/uarte0_ns/rxd/amount.rs b/pacs/nrf9120-pac/src/uarte0_ns/rxd/amount.rs new file mode 100644 index 00000000..b8909afa --- /dev/null +++ b/pacs/nrf9120-pac/src/uarte0_ns/rxd/amount.rs @@ -0,0 +1,40 @@ +#[doc = "Register `AMOUNT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `AMOUNT` reader - Number of bytes transferred in the last transaction"] +pub type AMOUNT_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:12 - Number of bytes transferred in the last transaction"] + #[inline(always)] + pub fn amount(&self) -> AMOUNT_R { + AMOUNT_R::new((self.bits & 0x1fff) as u16) + } +} +#[doc = "Number of bytes transferred in the last transaction\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [amount](index.html) module"] +pub struct AMOUNT_SPEC; +impl crate::RegisterSpec for AMOUNT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [amount::R](R) reader structure"] +impl crate::Readable for AMOUNT_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets AMOUNT to value 0"] +impl crate::Resettable for AMOUNT_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/uarte0_ns/rxd/maxcnt.rs b/pacs/nrf9120-pac/src/uarte0_ns/rxd/maxcnt.rs new file mode 100644 index 00000000..0344ca9e --- /dev/null +++ b/pacs/nrf9120-pac/src/uarte0_ns/rxd/maxcnt.rs @@ -0,0 +1,80 @@ +#[doc = "Register `MAXCNT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `MAXCNT` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `MAXCNT` reader - Maximum number of bytes in receive buffer"] +pub type MAXCNT_R = crate::FieldReader; +#[doc = "Field `MAXCNT` writer - Maximum number of bytes in receive buffer"] +pub type MAXCNT_W<'a, const O: u8> = crate::FieldWriter<'a, u32, MAXCNT_SPEC, u16, u16, 13, O>; +impl R { + #[doc = "Bits 0:12 - Maximum number of bytes in receive buffer"] + #[inline(always)] + pub fn maxcnt(&self) -> MAXCNT_R { + MAXCNT_R::new((self.bits & 0x1fff) as u16) + } +} +impl W { + #[doc = "Bits 0:12 - Maximum number of bytes in receive buffer"] + #[inline(always)] + pub fn maxcnt(&mut self) -> MAXCNT_W<0> { + MAXCNT_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Maximum number of bytes in receive buffer\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [maxcnt](index.html) module"] +pub struct MAXCNT_SPEC; +impl crate::RegisterSpec for MAXCNT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [maxcnt::R](R) reader structure"] +impl crate::Readable for MAXCNT_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [maxcnt::W](W) writer structure"] +impl crate::Writable for MAXCNT_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets MAXCNT to value 0"] +impl crate::Resettable for MAXCNT_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/uarte0_ns/rxd/ptr.rs b/pacs/nrf9120-pac/src/uarte0_ns/rxd/ptr.rs new file mode 100644 index 00000000..d5f98439 --- /dev/null +++ b/pacs/nrf9120-pac/src/uarte0_ns/rxd/ptr.rs @@ -0,0 +1,80 @@ +#[doc = "Register `PTR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PTR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PTR` reader - Data pointer"] +pub type PTR_R = crate::FieldReader; +#[doc = "Field `PTR` writer - Data pointer"] +pub type PTR_W<'a, const O: u8> = crate::FieldWriter<'a, u32, PTR_SPEC, u32, u32, 32, O>; +impl R { + #[doc = "Bits 0:31 - Data pointer"] + #[inline(always)] + pub fn ptr(&self) -> PTR_R { + PTR_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Data pointer"] + #[inline(always)] + pub fn ptr(&mut self) -> PTR_W<0> { + PTR_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Data pointer\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ptr](index.html) module"] +pub struct PTR_SPEC; +impl crate::RegisterSpec for PTR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ptr::R](R) reader structure"] +impl crate::Readable for PTR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ptr::W](W) writer structure"] +impl crate::Writable for PTR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PTR to value 0"] +impl crate::Resettable for PTR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/uarte0_ns/shorts.rs b/pacs/nrf9120-pac/src/uarte0_ns/shorts.rs new file mode 100644 index 00000000..4035f642 --- /dev/null +++ b/pacs/nrf9120-pac/src/uarte0_ns/shorts.rs @@ -0,0 +1,188 @@ +#[doc = "Register `SHORTS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SHORTS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ENDRX_STARTRX` reader - Shortcut between event ENDRX and task STARTRX"] +pub type ENDRX_STARTRX_R = crate::BitReader; +#[doc = "Shortcut between event ENDRX and task STARTRX\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum ENDRX_STARTRX_A { + #[doc = "0: Disable shortcut"] + DISABLED = 0, + #[doc = "1: Enable shortcut"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: ENDRX_STARTRX_A) -> Self { + variant as u8 != 0 + } +} +impl ENDRX_STARTRX_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> ENDRX_STARTRX_A { + match self.bits { + false => ENDRX_STARTRX_A::DISABLED, + true => ENDRX_STARTRX_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == ENDRX_STARTRX_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == ENDRX_STARTRX_A::ENABLED + } +} +#[doc = "Field `ENDRX_STARTRX` writer - Shortcut between event ENDRX and task STARTRX"] +pub type ENDRX_STARTRX_W<'a, const O: u8> = + crate::BitWriter<'a, u32, SHORTS_SPEC, ENDRX_STARTRX_A, O>; +impl<'a, const O: u8> ENDRX_STARTRX_W<'a, O> { + #[doc = "Disable shortcut"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(ENDRX_STARTRX_A::DISABLED) + } + #[doc = "Enable shortcut"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(ENDRX_STARTRX_A::ENABLED) + } +} +#[doc = "Field `ENDRX_STOPRX` reader - Shortcut between event ENDRX and task STOPRX"] +pub type ENDRX_STOPRX_R = crate::BitReader; +#[doc = "Shortcut between event ENDRX and task STOPRX\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum ENDRX_STOPRX_A { + #[doc = "0: Disable shortcut"] + DISABLED = 0, + #[doc = "1: Enable shortcut"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: ENDRX_STOPRX_A) -> Self { + variant as u8 != 0 + } +} +impl ENDRX_STOPRX_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> ENDRX_STOPRX_A { + match self.bits { + false => ENDRX_STOPRX_A::DISABLED, + true => ENDRX_STOPRX_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == ENDRX_STOPRX_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == ENDRX_STOPRX_A::ENABLED + } +} +#[doc = "Field `ENDRX_STOPRX` writer - Shortcut between event ENDRX and task STOPRX"] +pub type ENDRX_STOPRX_W<'a, const O: u8> = + crate::BitWriter<'a, u32, SHORTS_SPEC, ENDRX_STOPRX_A, O>; +impl<'a, const O: u8> ENDRX_STOPRX_W<'a, O> { + #[doc = "Disable shortcut"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(ENDRX_STOPRX_A::DISABLED) + } + #[doc = "Enable shortcut"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(ENDRX_STOPRX_A::ENABLED) + } +} +impl R { + #[doc = "Bit 5 - Shortcut between event ENDRX and task STARTRX"] + #[inline(always)] + pub fn endrx_startrx(&self) -> ENDRX_STARTRX_R { + ENDRX_STARTRX_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Shortcut between event ENDRX and task STOPRX"] + #[inline(always)] + pub fn endrx_stoprx(&self) -> ENDRX_STOPRX_R { + ENDRX_STOPRX_R::new(((self.bits >> 6) & 1) != 0) + } +} +impl W { + #[doc = "Bit 5 - Shortcut between event ENDRX and task STARTRX"] + #[inline(always)] + pub fn endrx_startrx(&mut self) -> ENDRX_STARTRX_W<5> { + ENDRX_STARTRX_W::new(self) + } + #[doc = "Bit 6 - Shortcut between event ENDRX and task STOPRX"] + #[inline(always)] + pub fn endrx_stoprx(&mut self) -> ENDRX_STOPRX_W<6> { + ENDRX_STOPRX_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Shortcuts between local events and tasks\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [shorts](index.html) module"] +pub struct SHORTS_SPEC; +impl crate::RegisterSpec for SHORTS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [shorts::R](R) reader structure"] +impl crate::Readable for SHORTS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [shorts::W](W) writer structure"] +impl crate::Writable for SHORTS_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SHORTS to value 0"] +impl crate::Resettable for SHORTS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/uarte0_ns/subscribe_flushrx.rs b/pacs/nrf9120-pac/src/uarte0_ns/subscribe_flushrx.rs new file mode 100644 index 00000000..7d4efd10 --- /dev/null +++ b/pacs/nrf9120-pac/src/uarte0_ns/subscribe_flushrx.rs @@ -0,0 +1,141 @@ +#[doc = "Register `SUBSCRIBE_FLUSHRX` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SUBSCRIBE_FLUSHRX` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CHIDX` reader - DPPI channel that task FLUSHRX will subscribe to"] +pub type CHIDX_R = crate::FieldReader; +#[doc = "Field `CHIDX` writer - DPPI channel that task FLUSHRX will subscribe to"] +pub type CHIDX_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, SUBSCRIBE_FLUSHRX_SPEC, u8, u8, 8, O>; +#[doc = "Field `EN` reader - "] +pub type EN_R = crate::BitReader; +#[doc = "\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum EN_A { + #[doc = "0: Disable subscription"] + DISABLED = 0, + #[doc = "1: Enable subscription"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: EN_A) -> Self { + variant as u8 != 0 + } +} +impl EN_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EN_A { + match self.bits { + false => EN_A::DISABLED, + true => EN_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == EN_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == EN_A::ENABLED + } +} +#[doc = "Field `EN` writer - "] +pub type EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, SUBSCRIBE_FLUSHRX_SPEC, EN_A, O>; +impl<'a, const O: u8> EN_W<'a, O> { + #[doc = "Disable subscription"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(EN_A::DISABLED) + } + #[doc = "Enable subscription"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(EN_A::ENABLED) + } +} +impl R { + #[doc = "Bits 0:7 - DPPI channel that task FLUSHRX will subscribe to"] + #[inline(always)] + pub fn chidx(&self) -> CHIDX_R { + CHIDX_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&self) -> EN_R { + EN_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:7 - DPPI channel that task FLUSHRX will subscribe to"] + #[inline(always)] + pub fn chidx(&mut self) -> CHIDX_W<0> { + CHIDX_W::new(self) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&mut self) -> EN_W<31> { + EN_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Subscribe configuration for task FLUSHRX\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [subscribe_flushrx](index.html) module"] +pub struct SUBSCRIBE_FLUSHRX_SPEC; +impl crate::RegisterSpec for SUBSCRIBE_FLUSHRX_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [subscribe_flushrx::R](R) reader structure"] +impl crate::Readable for SUBSCRIBE_FLUSHRX_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [subscribe_flushrx::W](W) writer structure"] +impl crate::Writable for SUBSCRIBE_FLUSHRX_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SUBSCRIBE_FLUSHRX to value 0"] +impl crate::Resettable for SUBSCRIBE_FLUSHRX_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/uarte0_ns/subscribe_startrx.rs b/pacs/nrf9120-pac/src/uarte0_ns/subscribe_startrx.rs new file mode 100644 index 00000000..83be54e3 --- /dev/null +++ b/pacs/nrf9120-pac/src/uarte0_ns/subscribe_startrx.rs @@ -0,0 +1,141 @@ +#[doc = "Register `SUBSCRIBE_STARTRX` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SUBSCRIBE_STARTRX` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CHIDX` reader - DPPI channel that task STARTRX will subscribe to"] +pub type CHIDX_R = crate::FieldReader; +#[doc = "Field `CHIDX` writer - DPPI channel that task STARTRX will subscribe to"] +pub type CHIDX_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, SUBSCRIBE_STARTRX_SPEC, u8, u8, 8, O>; +#[doc = "Field `EN` reader - "] +pub type EN_R = crate::BitReader; +#[doc = "\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum EN_A { + #[doc = "0: Disable subscription"] + DISABLED = 0, + #[doc = "1: Enable subscription"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: EN_A) -> Self { + variant as u8 != 0 + } +} +impl EN_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EN_A { + match self.bits { + false => EN_A::DISABLED, + true => EN_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == EN_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == EN_A::ENABLED + } +} +#[doc = "Field `EN` writer - "] +pub type EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, SUBSCRIBE_STARTRX_SPEC, EN_A, O>; +impl<'a, const O: u8> EN_W<'a, O> { + #[doc = "Disable subscription"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(EN_A::DISABLED) + } + #[doc = "Enable subscription"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(EN_A::ENABLED) + } +} +impl R { + #[doc = "Bits 0:7 - DPPI channel that task STARTRX will subscribe to"] + #[inline(always)] + pub fn chidx(&self) -> CHIDX_R { + CHIDX_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&self) -> EN_R { + EN_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:7 - DPPI channel that task STARTRX will subscribe to"] + #[inline(always)] + pub fn chidx(&mut self) -> CHIDX_W<0> { + CHIDX_W::new(self) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&mut self) -> EN_W<31> { + EN_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Subscribe configuration for task STARTRX\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [subscribe_startrx](index.html) module"] +pub struct SUBSCRIBE_STARTRX_SPEC; +impl crate::RegisterSpec for SUBSCRIBE_STARTRX_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [subscribe_startrx::R](R) reader structure"] +impl crate::Readable for SUBSCRIBE_STARTRX_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [subscribe_startrx::W](W) writer structure"] +impl crate::Writable for SUBSCRIBE_STARTRX_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SUBSCRIBE_STARTRX to value 0"] +impl crate::Resettable for SUBSCRIBE_STARTRX_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/uarte0_ns/subscribe_starttx.rs b/pacs/nrf9120-pac/src/uarte0_ns/subscribe_starttx.rs new file mode 100644 index 00000000..fca12315 --- /dev/null +++ b/pacs/nrf9120-pac/src/uarte0_ns/subscribe_starttx.rs @@ -0,0 +1,141 @@ +#[doc = "Register `SUBSCRIBE_STARTTX` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SUBSCRIBE_STARTTX` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CHIDX` reader - DPPI channel that task STARTTX will subscribe to"] +pub type CHIDX_R = crate::FieldReader; +#[doc = "Field `CHIDX` writer - DPPI channel that task STARTTX will subscribe to"] +pub type CHIDX_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, SUBSCRIBE_STARTTX_SPEC, u8, u8, 8, O>; +#[doc = "Field `EN` reader - "] +pub type EN_R = crate::BitReader; +#[doc = "\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum EN_A { + #[doc = "0: Disable subscription"] + DISABLED = 0, + #[doc = "1: Enable subscription"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: EN_A) -> Self { + variant as u8 != 0 + } +} +impl EN_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EN_A { + match self.bits { + false => EN_A::DISABLED, + true => EN_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == EN_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == EN_A::ENABLED + } +} +#[doc = "Field `EN` writer - "] +pub type EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, SUBSCRIBE_STARTTX_SPEC, EN_A, O>; +impl<'a, const O: u8> EN_W<'a, O> { + #[doc = "Disable subscription"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(EN_A::DISABLED) + } + #[doc = "Enable subscription"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(EN_A::ENABLED) + } +} +impl R { + #[doc = "Bits 0:7 - DPPI channel that task STARTTX will subscribe to"] + #[inline(always)] + pub fn chidx(&self) -> CHIDX_R { + CHIDX_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&self) -> EN_R { + EN_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:7 - DPPI channel that task STARTTX will subscribe to"] + #[inline(always)] + pub fn chidx(&mut self) -> CHIDX_W<0> { + CHIDX_W::new(self) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&mut self) -> EN_W<31> { + EN_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Subscribe configuration for task STARTTX\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [subscribe_starttx](index.html) module"] +pub struct SUBSCRIBE_STARTTX_SPEC; +impl crate::RegisterSpec for SUBSCRIBE_STARTTX_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [subscribe_starttx::R](R) reader structure"] +impl crate::Readable for SUBSCRIBE_STARTTX_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [subscribe_starttx::W](W) writer structure"] +impl crate::Writable for SUBSCRIBE_STARTTX_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SUBSCRIBE_STARTTX to value 0"] +impl crate::Resettable for SUBSCRIBE_STARTTX_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/uarte0_ns/subscribe_stoprx.rs b/pacs/nrf9120-pac/src/uarte0_ns/subscribe_stoprx.rs new file mode 100644 index 00000000..dc022e78 --- /dev/null +++ b/pacs/nrf9120-pac/src/uarte0_ns/subscribe_stoprx.rs @@ -0,0 +1,141 @@ +#[doc = "Register `SUBSCRIBE_STOPRX` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SUBSCRIBE_STOPRX` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CHIDX` reader - DPPI channel that task STOPRX will subscribe to"] +pub type CHIDX_R = crate::FieldReader; +#[doc = "Field `CHIDX` writer - DPPI channel that task STOPRX will subscribe to"] +pub type CHIDX_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, SUBSCRIBE_STOPRX_SPEC, u8, u8, 8, O>; +#[doc = "Field `EN` reader - "] +pub type EN_R = crate::BitReader; +#[doc = "\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum EN_A { + #[doc = "0: Disable subscription"] + DISABLED = 0, + #[doc = "1: Enable subscription"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: EN_A) -> Self { + variant as u8 != 0 + } +} +impl EN_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EN_A { + match self.bits { + false => EN_A::DISABLED, + true => EN_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == EN_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == EN_A::ENABLED + } +} +#[doc = "Field `EN` writer - "] +pub type EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, SUBSCRIBE_STOPRX_SPEC, EN_A, O>; +impl<'a, const O: u8> EN_W<'a, O> { + #[doc = "Disable subscription"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(EN_A::DISABLED) + } + #[doc = "Enable subscription"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(EN_A::ENABLED) + } +} +impl R { + #[doc = "Bits 0:7 - DPPI channel that task STOPRX will subscribe to"] + #[inline(always)] + pub fn chidx(&self) -> CHIDX_R { + CHIDX_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&self) -> EN_R { + EN_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:7 - DPPI channel that task STOPRX will subscribe to"] + #[inline(always)] + pub fn chidx(&mut self) -> CHIDX_W<0> { + CHIDX_W::new(self) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&mut self) -> EN_W<31> { + EN_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Subscribe configuration for task STOPRX\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [subscribe_stoprx](index.html) module"] +pub struct SUBSCRIBE_STOPRX_SPEC; +impl crate::RegisterSpec for SUBSCRIBE_STOPRX_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [subscribe_stoprx::R](R) reader structure"] +impl crate::Readable for SUBSCRIBE_STOPRX_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [subscribe_stoprx::W](W) writer structure"] +impl crate::Writable for SUBSCRIBE_STOPRX_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SUBSCRIBE_STOPRX to value 0"] +impl crate::Resettable for SUBSCRIBE_STOPRX_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/uarte0_ns/subscribe_stoptx.rs b/pacs/nrf9120-pac/src/uarte0_ns/subscribe_stoptx.rs new file mode 100644 index 00000000..3971071a --- /dev/null +++ b/pacs/nrf9120-pac/src/uarte0_ns/subscribe_stoptx.rs @@ -0,0 +1,141 @@ +#[doc = "Register `SUBSCRIBE_STOPTX` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SUBSCRIBE_STOPTX` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CHIDX` reader - DPPI channel that task STOPTX will subscribe to"] +pub type CHIDX_R = crate::FieldReader; +#[doc = "Field `CHIDX` writer - DPPI channel that task STOPTX will subscribe to"] +pub type CHIDX_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, SUBSCRIBE_STOPTX_SPEC, u8, u8, 8, O>; +#[doc = "Field `EN` reader - "] +pub type EN_R = crate::BitReader; +#[doc = "\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum EN_A { + #[doc = "0: Disable subscription"] + DISABLED = 0, + #[doc = "1: Enable subscription"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: EN_A) -> Self { + variant as u8 != 0 + } +} +impl EN_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EN_A { + match self.bits { + false => EN_A::DISABLED, + true => EN_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == EN_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == EN_A::ENABLED + } +} +#[doc = "Field `EN` writer - "] +pub type EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, SUBSCRIBE_STOPTX_SPEC, EN_A, O>; +impl<'a, const O: u8> EN_W<'a, O> { + #[doc = "Disable subscription"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(EN_A::DISABLED) + } + #[doc = "Enable subscription"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(EN_A::ENABLED) + } +} +impl R { + #[doc = "Bits 0:7 - DPPI channel that task STOPTX will subscribe to"] + #[inline(always)] + pub fn chidx(&self) -> CHIDX_R { + CHIDX_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&self) -> EN_R { + EN_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:7 - DPPI channel that task STOPTX will subscribe to"] + #[inline(always)] + pub fn chidx(&mut self) -> CHIDX_W<0> { + CHIDX_W::new(self) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&mut self) -> EN_W<31> { + EN_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Subscribe configuration for task STOPTX\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [subscribe_stoptx](index.html) module"] +pub struct SUBSCRIBE_STOPTX_SPEC; +impl crate::RegisterSpec for SUBSCRIBE_STOPTX_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [subscribe_stoptx::R](R) reader structure"] +impl crate::Readable for SUBSCRIBE_STOPTX_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [subscribe_stoptx::W](W) writer structure"] +impl crate::Writable for SUBSCRIBE_STOPTX_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SUBSCRIBE_STOPTX to value 0"] +impl crate::Resettable for SUBSCRIBE_STOPTX_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/uarte0_ns/tasks_flushrx.rs b/pacs/nrf9120-pac/src/uarte0_ns/tasks_flushrx.rs new file mode 100644 index 00000000..5074c6ab --- /dev/null +++ b/pacs/nrf9120-pac/src/uarte0_ns/tasks_flushrx.rs @@ -0,0 +1,72 @@ +#[doc = "Register `TASKS_FLUSHRX` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Flush RX FIFO into RX buffer\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum TASKS_FLUSHRX_AW { + #[doc = "1: Trigger task"] + TRIGGER = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TASKS_FLUSHRX_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TASKS_FLUSHRX` writer - Flush RX FIFO into RX buffer"] +pub type TASKS_FLUSHRX_W<'a, const O: u8> = + crate::BitWriter<'a, u32, TASKS_FLUSHRX_SPEC, TASKS_FLUSHRX_AW, O>; +impl<'a, const O: u8> TASKS_FLUSHRX_W<'a, O> { + #[doc = "Trigger task"] + #[inline(always)] + pub fn trigger(self) -> &'a mut W { + self.variant(TASKS_FLUSHRX_AW::TRIGGER) + } +} +impl W { + #[doc = "Bit 0 - Flush RX FIFO into RX buffer"] + #[inline(always)] + pub fn tasks_flushrx(&mut self) -> TASKS_FLUSHRX_W<0> { + TASKS_FLUSHRX_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Flush RX FIFO into RX buffer\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tasks_flushrx](index.html) module"] +pub struct TASKS_FLUSHRX_SPEC; +impl crate::RegisterSpec for TASKS_FLUSHRX_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [tasks_flushrx::W](W) writer structure"] +impl crate::Writable for TASKS_FLUSHRX_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets TASKS_FLUSHRX to value 0"] +impl crate::Resettable for TASKS_FLUSHRX_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/uarte0_ns/tasks_startrx.rs b/pacs/nrf9120-pac/src/uarte0_ns/tasks_startrx.rs new file mode 100644 index 00000000..a560a4a7 --- /dev/null +++ b/pacs/nrf9120-pac/src/uarte0_ns/tasks_startrx.rs @@ -0,0 +1,72 @@ +#[doc = "Register `TASKS_STARTRX` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Start UART receiver\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum TASKS_STARTRX_AW { + #[doc = "1: Trigger task"] + TRIGGER = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TASKS_STARTRX_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TASKS_STARTRX` writer - Start UART receiver"] +pub type TASKS_STARTRX_W<'a, const O: u8> = + crate::BitWriter<'a, u32, TASKS_STARTRX_SPEC, TASKS_STARTRX_AW, O>; +impl<'a, const O: u8> TASKS_STARTRX_W<'a, O> { + #[doc = "Trigger task"] + #[inline(always)] + pub fn trigger(self) -> &'a mut W { + self.variant(TASKS_STARTRX_AW::TRIGGER) + } +} +impl W { + #[doc = "Bit 0 - Start UART receiver"] + #[inline(always)] + pub fn tasks_startrx(&mut self) -> TASKS_STARTRX_W<0> { + TASKS_STARTRX_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Start UART receiver\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tasks_startrx](index.html) module"] +pub struct TASKS_STARTRX_SPEC; +impl crate::RegisterSpec for TASKS_STARTRX_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [tasks_startrx::W](W) writer structure"] +impl crate::Writable for TASKS_STARTRX_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets TASKS_STARTRX to value 0"] +impl crate::Resettable for TASKS_STARTRX_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/uarte0_ns/tasks_starttx.rs b/pacs/nrf9120-pac/src/uarte0_ns/tasks_starttx.rs new file mode 100644 index 00000000..fd3dc06b --- /dev/null +++ b/pacs/nrf9120-pac/src/uarte0_ns/tasks_starttx.rs @@ -0,0 +1,72 @@ +#[doc = "Register `TASKS_STARTTX` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Start UART transmitter\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum TASKS_STARTTX_AW { + #[doc = "1: Trigger task"] + TRIGGER = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TASKS_STARTTX_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TASKS_STARTTX` writer - Start UART transmitter"] +pub type TASKS_STARTTX_W<'a, const O: u8> = + crate::BitWriter<'a, u32, TASKS_STARTTX_SPEC, TASKS_STARTTX_AW, O>; +impl<'a, const O: u8> TASKS_STARTTX_W<'a, O> { + #[doc = "Trigger task"] + #[inline(always)] + pub fn trigger(self) -> &'a mut W { + self.variant(TASKS_STARTTX_AW::TRIGGER) + } +} +impl W { + #[doc = "Bit 0 - Start UART transmitter"] + #[inline(always)] + pub fn tasks_starttx(&mut self) -> TASKS_STARTTX_W<0> { + TASKS_STARTTX_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Start UART transmitter\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tasks_starttx](index.html) module"] +pub struct TASKS_STARTTX_SPEC; +impl crate::RegisterSpec for TASKS_STARTTX_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [tasks_starttx::W](W) writer structure"] +impl crate::Writable for TASKS_STARTTX_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets TASKS_STARTTX to value 0"] +impl crate::Resettable for TASKS_STARTTX_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/uarte0_ns/tasks_stoprx.rs b/pacs/nrf9120-pac/src/uarte0_ns/tasks_stoprx.rs new file mode 100644 index 00000000..5f51854b --- /dev/null +++ b/pacs/nrf9120-pac/src/uarte0_ns/tasks_stoprx.rs @@ -0,0 +1,72 @@ +#[doc = "Register `TASKS_STOPRX` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Stop UART receiver\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum TASKS_STOPRX_AW { + #[doc = "1: Trigger task"] + TRIGGER = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TASKS_STOPRX_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TASKS_STOPRX` writer - Stop UART receiver"] +pub type TASKS_STOPRX_W<'a, const O: u8> = + crate::BitWriter<'a, u32, TASKS_STOPRX_SPEC, TASKS_STOPRX_AW, O>; +impl<'a, const O: u8> TASKS_STOPRX_W<'a, O> { + #[doc = "Trigger task"] + #[inline(always)] + pub fn trigger(self) -> &'a mut W { + self.variant(TASKS_STOPRX_AW::TRIGGER) + } +} +impl W { + #[doc = "Bit 0 - Stop UART receiver"] + #[inline(always)] + pub fn tasks_stoprx(&mut self) -> TASKS_STOPRX_W<0> { + TASKS_STOPRX_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Stop UART receiver\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tasks_stoprx](index.html) module"] +pub struct TASKS_STOPRX_SPEC; +impl crate::RegisterSpec for TASKS_STOPRX_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [tasks_stoprx::W](W) writer structure"] +impl crate::Writable for TASKS_STOPRX_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets TASKS_STOPRX to value 0"] +impl crate::Resettable for TASKS_STOPRX_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/uarte0_ns/tasks_stoptx.rs b/pacs/nrf9120-pac/src/uarte0_ns/tasks_stoptx.rs new file mode 100644 index 00000000..39bf655c --- /dev/null +++ b/pacs/nrf9120-pac/src/uarte0_ns/tasks_stoptx.rs @@ -0,0 +1,72 @@ +#[doc = "Register `TASKS_STOPTX` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Stop UART transmitter\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum TASKS_STOPTX_AW { + #[doc = "1: Trigger task"] + TRIGGER = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TASKS_STOPTX_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TASKS_STOPTX` writer - Stop UART transmitter"] +pub type TASKS_STOPTX_W<'a, const O: u8> = + crate::BitWriter<'a, u32, TASKS_STOPTX_SPEC, TASKS_STOPTX_AW, O>; +impl<'a, const O: u8> TASKS_STOPTX_W<'a, O> { + #[doc = "Trigger task"] + #[inline(always)] + pub fn trigger(self) -> &'a mut W { + self.variant(TASKS_STOPTX_AW::TRIGGER) + } +} +impl W { + #[doc = "Bit 0 - Stop UART transmitter"] + #[inline(always)] + pub fn tasks_stoptx(&mut self) -> TASKS_STOPTX_W<0> { + TASKS_STOPTX_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Stop UART transmitter\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tasks_stoptx](index.html) module"] +pub struct TASKS_STOPTX_SPEC; +impl crate::RegisterSpec for TASKS_STOPTX_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [tasks_stoptx::W](W) writer structure"] +impl crate::Writable for TASKS_STOPTX_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets TASKS_STOPTX to value 0"] +impl crate::Resettable for TASKS_STOPTX_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/uarte0_ns/txd.rs b/pacs/nrf9120-pac/src/uarte0_ns/txd.rs new file mode 100644 index 00000000..8a19551f --- /dev/null +++ b/pacs/nrf9120-pac/src/uarte0_ns/txd.rs @@ -0,0 +1,22 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct TXD { + #[doc = "0x00 - Data pointer"] + pub ptr: PTR, + #[doc = "0x04 - Maximum number of bytes in transmit buffer"] + pub maxcnt: MAXCNT, + #[doc = "0x08 - Number of bytes transferred in the last transaction"] + pub amount: AMOUNT, +} +#[doc = "PTR (rw) register accessor: an alias for `Reg`"] +pub type PTR = crate::Reg; +#[doc = "Data pointer"] +pub mod ptr; +#[doc = "MAXCNT (rw) register accessor: an alias for `Reg`"] +pub type MAXCNT = crate::Reg; +#[doc = "Maximum number of bytes in transmit buffer"] +pub mod maxcnt; +#[doc = "AMOUNT (r) register accessor: an alias for `Reg`"] +pub type AMOUNT = crate::Reg; +#[doc = "Number of bytes transferred in the last transaction"] +pub mod amount; diff --git a/pacs/nrf9120-pac/src/uarte0_ns/txd/amount.rs b/pacs/nrf9120-pac/src/uarte0_ns/txd/amount.rs new file mode 100644 index 00000000..b8909afa --- /dev/null +++ b/pacs/nrf9120-pac/src/uarte0_ns/txd/amount.rs @@ -0,0 +1,40 @@ +#[doc = "Register `AMOUNT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `AMOUNT` reader - Number of bytes transferred in the last transaction"] +pub type AMOUNT_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:12 - Number of bytes transferred in the last transaction"] + #[inline(always)] + pub fn amount(&self) -> AMOUNT_R { + AMOUNT_R::new((self.bits & 0x1fff) as u16) + } +} +#[doc = "Number of bytes transferred in the last transaction\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [amount](index.html) module"] +pub struct AMOUNT_SPEC; +impl crate::RegisterSpec for AMOUNT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [amount::R](R) reader structure"] +impl crate::Readable for AMOUNT_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets AMOUNT to value 0"] +impl crate::Resettable for AMOUNT_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/uarte0_ns/txd/maxcnt.rs b/pacs/nrf9120-pac/src/uarte0_ns/txd/maxcnt.rs new file mode 100644 index 00000000..7ae96778 --- /dev/null +++ b/pacs/nrf9120-pac/src/uarte0_ns/txd/maxcnt.rs @@ -0,0 +1,80 @@ +#[doc = "Register `MAXCNT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `MAXCNT` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `MAXCNT` reader - Maximum number of bytes in transmit buffer"] +pub type MAXCNT_R = crate::FieldReader; +#[doc = "Field `MAXCNT` writer - Maximum number of bytes in transmit buffer"] +pub type MAXCNT_W<'a, const O: u8> = crate::FieldWriter<'a, u32, MAXCNT_SPEC, u16, u16, 13, O>; +impl R { + #[doc = "Bits 0:12 - Maximum number of bytes in transmit buffer"] + #[inline(always)] + pub fn maxcnt(&self) -> MAXCNT_R { + MAXCNT_R::new((self.bits & 0x1fff) as u16) + } +} +impl W { + #[doc = "Bits 0:12 - Maximum number of bytes in transmit buffer"] + #[inline(always)] + pub fn maxcnt(&mut self) -> MAXCNT_W<0> { + MAXCNT_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Maximum number of bytes in transmit buffer\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [maxcnt](index.html) module"] +pub struct MAXCNT_SPEC; +impl crate::RegisterSpec for MAXCNT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [maxcnt::R](R) reader structure"] +impl crate::Readable for MAXCNT_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [maxcnt::W](W) writer structure"] +impl crate::Writable for MAXCNT_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets MAXCNT to value 0"] +impl crate::Resettable for MAXCNT_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/uarte0_ns/txd/ptr.rs b/pacs/nrf9120-pac/src/uarte0_ns/txd/ptr.rs new file mode 100644 index 00000000..d5f98439 --- /dev/null +++ b/pacs/nrf9120-pac/src/uarte0_ns/txd/ptr.rs @@ -0,0 +1,80 @@ +#[doc = "Register `PTR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PTR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PTR` reader - Data pointer"] +pub type PTR_R = crate::FieldReader; +#[doc = "Field `PTR` writer - Data pointer"] +pub type PTR_W<'a, const O: u8> = crate::FieldWriter<'a, u32, PTR_SPEC, u32, u32, 32, O>; +impl R { + #[doc = "Bits 0:31 - Data pointer"] + #[inline(always)] + pub fn ptr(&self) -> PTR_R { + PTR_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Data pointer"] + #[inline(always)] + pub fn ptr(&mut self) -> PTR_W<0> { + PTR_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Data pointer\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ptr](index.html) module"] +pub struct PTR_SPEC; +impl crate::RegisterSpec for PTR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ptr::R](R) reader structure"] +impl crate::Readable for PTR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ptr::W](W) writer structure"] +impl crate::Writable for PTR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PTR to value 0"] +impl crate::Resettable for PTR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/uicr_s.rs b/pacs/nrf9120-pac/src/uicr_s.rs new file mode 100644 index 00000000..31d2e87b --- /dev/null +++ b/pacs/nrf9120-pac/src/uicr_s.rs @@ -0,0 +1,68 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Access port protection"] + pub approtect: APPROTECT, + _reserved1: [u8; 0x10], + #[doc = "0x14 - Oscillator control"] + pub xosc32m: XOSC32M, + _reserved2: [u8; 0x04], + #[doc = "0x1c - HFXO clock source selection"] + pub hfxosrc: HFXOSRC, + #[doc = "0x20 - HFXO startup counter"] + pub hfxocnt: HFXOCNT, + #[doc = "0x24 - Enable blocking NVM WRITE and aborting NVM ERASE for Application NVM in POFWARN condition ."] + pub appnvmcpofguard: APPNVMCPOFGUARD, + #[doc = "0x28 - Polarity of PMIC polarity configuration signals."] + pub pmicconf: PMICCONF, + #[doc = "0x2c - Secure access port protection"] + pub secureapprotect: SECUREAPPROTECT, + #[doc = "0x30 - Erase protection"] + pub eraseprotect: ERASEPROTECT, + _reserved8: [u8; 0xd4], + #[doc = "0x108..0x400 - Description collection: One time programmable memory"] + pub otp: [OTP; 190], + #[doc = "0x400..0x1000 - Unspecified"] + pub keyslot: KEYSLOT, +} +#[doc = "APPROTECT (rw) register accessor: an alias for `Reg`"] +pub type APPROTECT = crate::Reg; +#[doc = "Access port protection"] +pub mod approtect; +#[doc = "XOSC32M (rw) register accessor: an alias for `Reg`"] +pub type XOSC32M = crate::Reg; +#[doc = "Oscillator control"] +pub mod xosc32m; +#[doc = "HFXOSRC (rw) register accessor: an alias for `Reg`"] +pub type HFXOSRC = crate::Reg; +#[doc = "HFXO clock source selection"] +pub mod hfxosrc; +#[doc = "HFXOCNT (rw) register accessor: an alias for `Reg`"] +pub type HFXOCNT = crate::Reg; +#[doc = "HFXO startup counter"] +pub mod hfxocnt; +#[doc = "APPNVMCPOFGUARD (rw) register accessor: an alias for `Reg`"] +pub type APPNVMCPOFGUARD = crate::Reg; +#[doc = "Enable blocking NVM WRITE and aborting NVM ERASE for Application NVM in POFWARN condition ."] +pub mod appnvmcpofguard; +#[doc = "PMICCONF (rw) register accessor: an alias for `Reg`"] +pub type PMICCONF = crate::Reg; +#[doc = "Polarity of PMIC polarity configuration signals."] +pub mod pmicconf; +#[doc = "SECUREAPPROTECT (rw) register accessor: an alias for `Reg`"] +pub type SECUREAPPROTECT = crate::Reg; +#[doc = "Secure access port protection"] +pub mod secureapprotect; +#[doc = "ERASEPROTECT (rw) register accessor: an alias for `Reg`"] +pub type ERASEPROTECT = crate::Reg; +#[doc = "Erase protection"] +pub mod eraseprotect; +#[doc = "OTP (rw) register accessor: an alias for `Reg`"] +pub type OTP = crate::Reg; +#[doc = "Description collection: One time programmable memory"] +pub mod otp; +#[doc = "Unspecified"] +pub use keyslot::KEYSLOT; +#[doc = r"Cluster"] +#[doc = "Unspecified"] +pub mod keyslot; diff --git a/pacs/nrf9120-pac/src/uicr_s/appnvmcpofguard.rs b/pacs/nrf9120-pac/src/uicr_s/appnvmcpofguard.rs new file mode 100644 index 00000000..11c82ea9 --- /dev/null +++ b/pacs/nrf9120-pac/src/uicr_s/appnvmcpofguard.rs @@ -0,0 +1,127 @@ +#[doc = "Register `APPNVMCPOFGUARD` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `APPNVMCPOFGUARD` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `NVMCPOFGUARDEN` reader - Enable blocking NVM WRITE and aborting NVM ERASE in POFWARN condition"] +pub type NVMCPOFGUARDEN_R = crate::BitReader; +#[doc = "Enable blocking NVM WRITE and aborting NVM ERASE in POFWARN condition\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum NVMCPOFGUARDEN_A { + #[doc = "0: NVM WRITE and NVM ERASE are not blocked in POFWARN condition"] + DISABLED = 0, + #[doc = "1: NVM WRITE and NVM ERASE are blocked in POFWARN condition"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: NVMCPOFGUARDEN_A) -> Self { + variant as u8 != 0 + } +} +impl NVMCPOFGUARDEN_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> NVMCPOFGUARDEN_A { + match self.bits { + false => NVMCPOFGUARDEN_A::DISABLED, + true => NVMCPOFGUARDEN_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == NVMCPOFGUARDEN_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == NVMCPOFGUARDEN_A::ENABLED + } +} +#[doc = "Field `NVMCPOFGUARDEN` writer - Enable blocking NVM WRITE and aborting NVM ERASE in POFWARN condition"] +pub type NVMCPOFGUARDEN_W<'a, const O: u8> = + crate::BitWriter<'a, u32, APPNVMCPOFGUARD_SPEC, NVMCPOFGUARDEN_A, O>; +impl<'a, const O: u8> NVMCPOFGUARDEN_W<'a, O> { + #[doc = "NVM WRITE and NVM ERASE are not blocked in POFWARN condition"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(NVMCPOFGUARDEN_A::DISABLED) + } + #[doc = "NVM WRITE and NVM ERASE are blocked in POFWARN condition"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(NVMCPOFGUARDEN_A::ENABLED) + } +} +impl R { + #[doc = "Bit 0 - Enable blocking NVM WRITE and aborting NVM ERASE in POFWARN condition"] + #[inline(always)] + pub fn nvmcpofguarden(&self) -> NVMCPOFGUARDEN_R { + NVMCPOFGUARDEN_R::new((self.bits & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Enable blocking NVM WRITE and aborting NVM ERASE in POFWARN condition"] + #[inline(always)] + pub fn nvmcpofguarden(&mut self) -> NVMCPOFGUARDEN_W<0> { + NVMCPOFGUARDEN_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Enable blocking NVM WRITE and aborting NVM ERASE for Application NVM in POFWARN condition .\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [appnvmcpofguard](index.html) module"] +pub struct APPNVMCPOFGUARD_SPEC; +impl crate::RegisterSpec for APPNVMCPOFGUARD_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [appnvmcpofguard::R](R) reader structure"] +impl crate::Readable for APPNVMCPOFGUARD_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [appnvmcpofguard::W](W) writer structure"] +impl crate::Writable for APPNVMCPOFGUARD_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets APPNVMCPOFGUARD to value 0xffff_ffff"] +impl crate::Resettable for APPNVMCPOFGUARD_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0xffff_ffff + } +} diff --git a/pacs/nrf9120-pac/src/uicr_s/approtect.rs b/pacs/nrf9120-pac/src/uicr_s/approtect.rs new file mode 100644 index 00000000..5d1d7383 --- /dev/null +++ b/pacs/nrf9120-pac/src/uicr_s/approtect.rs @@ -0,0 +1,128 @@ +#[doc = "Register `APPROTECT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `APPROTECT` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PALL` reader - Blocks debugger read/write access to all CPU registers and memory mapped addresses"] +pub type PALL_R = crate::FieldReader; +#[doc = "Blocks debugger read/write access to all CPU registers and memory mapped addresses\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u32)] +pub enum PALL_A { + #[doc = "1358582010: HwUnprotected"] + HW_UNPROTECTED = 1358582010, + #[doc = "0: Protected"] + PROTECTED = 0, +} +impl From for u32 { + #[inline(always)] + fn from(variant: PALL_A) -> Self { + variant as _ + } +} +impl PALL_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 1358582010 => Some(PALL_A::HW_UNPROTECTED), + 0 => Some(PALL_A::PROTECTED), + _ => None, + } + } + #[doc = "Checks if the value of the field is `HW_UNPROTECTED`"] + #[inline(always)] + pub fn is_hw_unprotected(&self) -> bool { + *self == PALL_A::HW_UNPROTECTED + } + #[doc = "Checks if the value of the field is `PROTECTED`"] + #[inline(always)] + pub fn is_protected(&self) -> bool { + *self == PALL_A::PROTECTED + } +} +#[doc = "Field `PALL` writer - Blocks debugger read/write access to all CPU registers and memory mapped addresses"] +pub type PALL_W<'a, const O: u8> = crate::FieldWriter<'a, u32, APPROTECT_SPEC, u32, PALL_A, 32, O>; +impl<'a, const O: u8> PALL_W<'a, O> { + #[doc = "HwUnprotected"] + #[inline(always)] + pub fn hw_unprotected(self) -> &'a mut W { + self.variant(PALL_A::HW_UNPROTECTED) + } + #[doc = "Protected"] + #[inline(always)] + pub fn protected(self) -> &'a mut W { + self.variant(PALL_A::PROTECTED) + } +} +impl R { + #[doc = "Bits 0:31 - Blocks debugger read/write access to all CPU registers and memory mapped addresses"] + #[inline(always)] + pub fn pall(&self) -> PALL_R { + PALL_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Blocks debugger read/write access to all CPU registers and memory mapped addresses"] + #[inline(always)] + pub fn pall(&mut self) -> PALL_W<0> { + PALL_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Access port protection\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [approtect](index.html) module"] +pub struct APPROTECT_SPEC; +impl crate::RegisterSpec for APPROTECT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [approtect::R](R) reader structure"] +impl crate::Readable for APPROTECT_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [approtect::W](W) writer structure"] +impl crate::Writable for APPROTECT_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets APPROTECT to value 0"] +impl crate::Resettable for APPROTECT_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/uicr_s/eraseprotect.rs b/pacs/nrf9120-pac/src/uicr_s/eraseprotect.rs new file mode 100644 index 00000000..cd4fcc33 --- /dev/null +++ b/pacs/nrf9120-pac/src/uicr_s/eraseprotect.rs @@ -0,0 +1,129 @@ +#[doc = "Register `ERASEPROTECT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `ERASEPROTECT` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PALL` reader - Blocks NVMC ERASEALL and CTRLAP ERASEALL functionality"] +pub type PALL_R = crate::FieldReader; +#[doc = "Blocks NVMC ERASEALL and CTRLAP ERASEALL functionality\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u32)] +pub enum PALL_A { + #[doc = "4294967295: Unprotected"] + UNPROTECTED = 4294967295, + #[doc = "0: Protected"] + PROTECTED = 0, +} +impl From for u32 { + #[inline(always)] + fn from(variant: PALL_A) -> Self { + variant as _ + } +} +impl PALL_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 4294967295 => Some(PALL_A::UNPROTECTED), + 0 => Some(PALL_A::PROTECTED), + _ => None, + } + } + #[doc = "Checks if the value of the field is `UNPROTECTED`"] + #[inline(always)] + pub fn is_unprotected(&self) -> bool { + *self == PALL_A::UNPROTECTED + } + #[doc = "Checks if the value of the field is `PROTECTED`"] + #[inline(always)] + pub fn is_protected(&self) -> bool { + *self == PALL_A::PROTECTED + } +} +#[doc = "Field `PALL` writer - Blocks NVMC ERASEALL and CTRLAP ERASEALL functionality"] +pub type PALL_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, ERASEPROTECT_SPEC, u32, PALL_A, 32, O>; +impl<'a, const O: u8> PALL_W<'a, O> { + #[doc = "Unprotected"] + #[inline(always)] + pub fn unprotected(self) -> &'a mut W { + self.variant(PALL_A::UNPROTECTED) + } + #[doc = "Protected"] + #[inline(always)] + pub fn protected(self) -> &'a mut W { + self.variant(PALL_A::PROTECTED) + } +} +impl R { + #[doc = "Bits 0:31 - Blocks NVMC ERASEALL and CTRLAP ERASEALL functionality"] + #[inline(always)] + pub fn pall(&self) -> PALL_R { + PALL_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Blocks NVMC ERASEALL and CTRLAP ERASEALL functionality"] + #[inline(always)] + pub fn pall(&mut self) -> PALL_W<0> { + PALL_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Erase protection\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [eraseprotect](index.html) module"] +pub struct ERASEPROTECT_SPEC; +impl crate::RegisterSpec for ERASEPROTECT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [eraseprotect::R](R) reader structure"] +impl crate::Readable for ERASEPROTECT_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [eraseprotect::W](W) writer structure"] +impl crate::Writable for ERASEPROTECT_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets ERASEPROTECT to value 0"] +impl crate::Resettable for ERASEPROTECT_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/uicr_s/hfxocnt.rs b/pacs/nrf9120-pac/src/uicr_s/hfxocnt.rs new file mode 100644 index 00000000..7d269274 --- /dev/null +++ b/pacs/nrf9120-pac/src/uicr_s/hfxocnt.rs @@ -0,0 +1,129 @@ +#[doc = "Register `HFXOCNT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `HFXOCNT` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `HFXOCNT` reader - HFXO startup counter. Total debounce time = HFXOCNT*64 us + 0.5 us"] +pub type HFXOCNT_R = crate::FieldReader; +#[doc = "HFXO startup counter. Total debounce time = HFXOCNT*64 us + 0.5 us\n\nValue on reset: 255"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum HFXOCNT_A { + #[doc = "0: Min debounce time = (0*64 us + 0.5 us)"] + MIN_DEBOUNCE_TIME = 0, + #[doc = "255: Max debounce time = (255*64 us + 0.5 us)"] + MAX_DEBOUNCE_TIME = 255, +} +impl From for u8 { + #[inline(always)] + fn from(variant: HFXOCNT_A) -> Self { + variant as _ + } +} +impl HFXOCNT_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(HFXOCNT_A::MIN_DEBOUNCE_TIME), + 255 => Some(HFXOCNT_A::MAX_DEBOUNCE_TIME), + _ => None, + } + } + #[doc = "Checks if the value of the field is `MIN_DEBOUNCE_TIME`"] + #[inline(always)] + pub fn is_min_debounce_time(&self) -> bool { + *self == HFXOCNT_A::MIN_DEBOUNCE_TIME + } + #[doc = "Checks if the value of the field is `MAX_DEBOUNCE_TIME`"] + #[inline(always)] + pub fn is_max_debounce_time(&self) -> bool { + *self == HFXOCNT_A::MAX_DEBOUNCE_TIME + } +} +#[doc = "Field `HFXOCNT` writer - HFXO startup counter. Total debounce time = HFXOCNT*64 us + 0.5 us"] +pub type HFXOCNT_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, HFXOCNT_SPEC, u8, HFXOCNT_A, 8, O>; +impl<'a, const O: u8> HFXOCNT_W<'a, O> { + #[doc = "Min debounce time = (0*64 us + 0.5 us)"] + #[inline(always)] + pub fn min_debounce_time(self) -> &'a mut W { + self.variant(HFXOCNT_A::MIN_DEBOUNCE_TIME) + } + #[doc = "Max debounce time = (255*64 us + 0.5 us)"] + #[inline(always)] + pub fn max_debounce_time(self) -> &'a mut W { + self.variant(HFXOCNT_A::MAX_DEBOUNCE_TIME) + } +} +impl R { + #[doc = "Bits 0:7 - HFXO startup counter. Total debounce time = HFXOCNT*64 us + 0.5 us"] + #[inline(always)] + pub fn hfxocnt(&self) -> HFXOCNT_R { + HFXOCNT_R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - HFXO startup counter. Total debounce time = HFXOCNT*64 us + 0.5 us"] + #[inline(always)] + pub fn hfxocnt(&mut self) -> HFXOCNT_W<0> { + HFXOCNT_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "HFXO startup counter\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hfxocnt](index.html) module"] +pub struct HFXOCNT_SPEC; +impl crate::RegisterSpec for HFXOCNT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [hfxocnt::R](R) reader structure"] +impl crate::Readable for HFXOCNT_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [hfxocnt::W](W) writer structure"] +impl crate::Writable for HFXOCNT_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets HFXOCNT to value 0xffff_ffff"] +impl crate::Resettable for HFXOCNT_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0xffff_ffff + } +} diff --git a/pacs/nrf9120-pac/src/uicr_s/hfxosrc.rs b/pacs/nrf9120-pac/src/uicr_s/hfxosrc.rs new file mode 100644 index 00000000..0fb932c0 --- /dev/null +++ b/pacs/nrf9120-pac/src/uicr_s/hfxosrc.rs @@ -0,0 +1,126 @@ +#[doc = "Register `HFXOSRC` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `HFXOSRC` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `HFXOSRC` reader - HFXO clock source selection"] +pub type HFXOSRC_R = crate::BitReader; +#[doc = "HFXO clock source selection\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum HFXOSRC_A { + #[doc = "1: 32 MHz crystal oscillator"] + XTAL = 1, + #[doc = "0: 32 MHz temperature compensated crystal oscillator (TCXO)"] + TCXO = 0, +} +impl From for bool { + #[inline(always)] + fn from(variant: HFXOSRC_A) -> Self { + variant as u8 != 0 + } +} +impl HFXOSRC_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> HFXOSRC_A { + match self.bits { + true => HFXOSRC_A::XTAL, + false => HFXOSRC_A::TCXO, + } + } + #[doc = "Checks if the value of the field is `XTAL`"] + #[inline(always)] + pub fn is_xtal(&self) -> bool { + *self == HFXOSRC_A::XTAL + } + #[doc = "Checks if the value of the field is `TCXO`"] + #[inline(always)] + pub fn is_tcxo(&self) -> bool { + *self == HFXOSRC_A::TCXO + } +} +#[doc = "Field `HFXOSRC` writer - HFXO clock source selection"] +pub type HFXOSRC_W<'a, const O: u8> = crate::BitWriter<'a, u32, HFXOSRC_SPEC, HFXOSRC_A, O>; +impl<'a, const O: u8> HFXOSRC_W<'a, O> { + #[doc = "32 MHz crystal oscillator"] + #[inline(always)] + pub fn xtal(self) -> &'a mut W { + self.variant(HFXOSRC_A::XTAL) + } + #[doc = "32 MHz temperature compensated crystal oscillator (TCXO)"] + #[inline(always)] + pub fn tcxo(self) -> &'a mut W { + self.variant(HFXOSRC_A::TCXO) + } +} +impl R { + #[doc = "Bit 0 - HFXO clock source selection"] + #[inline(always)] + pub fn hfxosrc(&self) -> HFXOSRC_R { + HFXOSRC_R::new((self.bits & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - HFXO clock source selection"] + #[inline(always)] + pub fn hfxosrc(&mut self) -> HFXOSRC_W<0> { + HFXOSRC_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "HFXO clock source selection\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hfxosrc](index.html) module"] +pub struct HFXOSRC_SPEC; +impl crate::RegisterSpec for HFXOSRC_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [hfxosrc::R](R) reader structure"] +impl crate::Readable for HFXOSRC_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [hfxosrc::W](W) writer structure"] +impl crate::Writable for HFXOSRC_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets HFXOSRC to value 0xffff_ffff"] +impl crate::Resettable for HFXOSRC_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0xffff_ffff + } +} diff --git a/pacs/nrf9120-pac/src/uicr_s/keyslot.rs b/pacs/nrf9120-pac/src/uicr_s/keyslot.rs new file mode 100644 index 00000000..1ed03677 --- /dev/null +++ b/pacs/nrf9120-pac/src/uicr_s/keyslot.rs @@ -0,0 +1,18 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct KEYSLOT { + #[doc = "0x00..0x400 - Unspecified"] + pub config: [CONFIG; 128], + #[doc = "0x400..0xc00 - Unspecified"] + pub key: [KEY; 128], +} +#[doc = "Unspecified"] +pub use config::CONFIG; +#[doc = r"Cluster"] +#[doc = "Unspecified"] +pub mod config; +#[doc = "Unspecified"] +pub use key::KEY; +#[doc = r"Cluster"] +#[doc = "Unspecified"] +pub mod key; diff --git a/pacs/nrf9120-pac/src/uicr_s/keyslot/config.rs b/pacs/nrf9120-pac/src/uicr_s/keyslot/config.rs new file mode 100644 index 00000000..dc1a62fa --- /dev/null +++ b/pacs/nrf9120-pac/src/uicr_s/keyslot/config.rs @@ -0,0 +1,16 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct CONFIG { + #[doc = "0x00 - Description cluster: Destination address where content of the key value registers (KEYSLOT.KEYn.VALUE\\[0-3\\]) will be pushed by KMU. Note that this address must match that of a peripherals APB mapped write-only key registers, else the KMU can push this key value into an address range which the CPU can potentially read."] + pub dest: DEST, + #[doc = "0x04 - Description cluster: Define permissions for the key slot. Bits 0-15 and 16-31 can only be written when equal to 0xFFFF."] + pub perm: PERM, +} +#[doc = "DEST (rw) register accessor: an alias for `Reg`"] +pub type DEST = crate::Reg; +#[doc = "Description cluster: Destination address where content of the key value registers (KEYSLOT.KEYn.VALUE\\[0-3\\]) will be pushed by KMU. Note that this address must match that of a peripherals APB mapped write-only key registers, else the KMU can push this key value into an address range which the CPU can potentially read."] +pub mod dest; +#[doc = "PERM (rw) register accessor: an alias for `Reg`"] +pub type PERM = crate::Reg; +#[doc = "Description cluster: Define permissions for the key slot. Bits 0-15 and 16-31 can only be written when equal to 0xFFFF."] +pub mod perm; diff --git a/pacs/nrf9120-pac/src/uicr_s/keyslot/config/dest.rs b/pacs/nrf9120-pac/src/uicr_s/keyslot/config/dest.rs new file mode 100644 index 00000000..f8743ab0 --- /dev/null +++ b/pacs/nrf9120-pac/src/uicr_s/keyslot/config/dest.rs @@ -0,0 +1,80 @@ +#[doc = "Register `DEST` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DEST` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DEST` reader - Secure APB destination address"] +pub type DEST_R = crate::FieldReader; +#[doc = "Field `DEST` writer - Secure APB destination address"] +pub type DEST_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DEST_SPEC, u32, u32, 32, O>; +impl R { + #[doc = "Bits 0:31 - Secure APB destination address"] + #[inline(always)] + pub fn dest(&self) -> DEST_R { + DEST_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Secure APB destination address"] + #[inline(always)] + pub fn dest(&mut self) -> DEST_W<0> { + DEST_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Description cluster: Destination address where content of the key value registers (KEYSLOT.KEYn.VALUE\\[0-3\\]) will be pushed by KMU. Note that this address must match that of a peripherals APB mapped write-only key registers, else the KMU can push this key value into an address range which the CPU can potentially read.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dest](index.html) module"] +pub struct DEST_SPEC; +impl crate::RegisterSpec for DEST_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dest::R](R) reader structure"] +impl crate::Readable for DEST_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dest::W](W) writer structure"] +impl crate::Writable for DEST_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DEST to value 0xffff_ffff"] +impl crate::Resettable for DEST_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0xffff_ffff + } +} diff --git a/pacs/nrf9120-pac/src/uicr_s/keyslot/config/perm.rs b/pacs/nrf9120-pac/src/uicr_s/keyslot/config/perm.rs new file mode 100644 index 00000000..58c360fa --- /dev/null +++ b/pacs/nrf9120-pac/src/uicr_s/keyslot/config/perm.rs @@ -0,0 +1,306 @@ +#[doc = "Register `PERM` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PERM` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `WRITE` reader - Write permission for key slot"] +pub type WRITE_R = crate::BitReader; +#[doc = "Write permission for key slot\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum WRITE_A { + #[doc = "0: Disable write to the key value registers"] + DISABLED = 0, + #[doc = "1: Enable write to the key value registers"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: WRITE_A) -> Self { + variant as u8 != 0 + } +} +impl WRITE_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> WRITE_A { + match self.bits { + false => WRITE_A::DISABLED, + true => WRITE_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == WRITE_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == WRITE_A::ENABLED + } +} +#[doc = "Field `WRITE` writer - Write permission for key slot"] +pub type WRITE_W<'a, const O: u8> = crate::BitWriter<'a, u32, PERM_SPEC, WRITE_A, O>; +impl<'a, const O: u8> WRITE_W<'a, O> { + #[doc = "Disable write to the key value registers"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(WRITE_A::DISABLED) + } + #[doc = "Enable write to the key value registers"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(WRITE_A::ENABLED) + } +} +#[doc = "Field `READ` reader - Read permission for key slot"] +pub type READ_R = crate::BitReader; +#[doc = "Read permission for key slot\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum READ_A { + #[doc = "0: Disable read from key value registers"] + DISABLED = 0, + #[doc = "1: Enable read from key value registers"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: READ_A) -> Self { + variant as u8 != 0 + } +} +impl READ_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> READ_A { + match self.bits { + false => READ_A::DISABLED, + true => READ_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == READ_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == READ_A::ENABLED + } +} +#[doc = "Field `READ` writer - Read permission for key slot"] +pub type READ_W<'a, const O: u8> = crate::BitWriter<'a, u32, PERM_SPEC, READ_A, O>; +impl<'a, const O: u8> READ_W<'a, O> { + #[doc = "Disable read from key value registers"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(READ_A::DISABLED) + } + #[doc = "Enable read from key value registers"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(READ_A::ENABLED) + } +} +#[doc = "Field `PUSH` reader - Push permission for key slot"] +pub type PUSH_R = crate::BitReader; +#[doc = "Push permission for key slot\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PUSH_A { + #[doc = "0: Disable pushing of key value registers over secure APB, but can be read if field READ is Enabled"] + DISABLED = 0, + #[doc = "1: Enable pushing of key value registers over secure APB. Register KEYSLOT.CONFIGn.DEST must contain a valid destination address!"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PUSH_A) -> Self { + variant as u8 != 0 + } +} +impl PUSH_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PUSH_A { + match self.bits { + false => PUSH_A::DISABLED, + true => PUSH_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == PUSH_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == PUSH_A::ENABLED + } +} +#[doc = "Field `PUSH` writer - Push permission for key slot"] +pub type PUSH_W<'a, const O: u8> = crate::BitWriter<'a, u32, PERM_SPEC, PUSH_A, O>; +impl<'a, const O: u8> PUSH_W<'a, O> { + #[doc = "Disable pushing of key value registers over secure APB, but can be read if field READ is Enabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(PUSH_A::DISABLED) + } + #[doc = "Enable pushing of key value registers over secure APB. Register KEYSLOT.CONFIGn.DEST must contain a valid destination address!"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(PUSH_A::ENABLED) + } +} +#[doc = "Field `STATE` reader - Revocation state for the key slot"] +pub type STATE_R = crate::BitReader; +#[doc = "Revocation state for the key slot\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum STATE_A { + #[doc = "0: Key value registers can no longer be read or pushed"] + REVOKED = 0, + #[doc = "1: Key value registers are readable (if enabled) and can be pushed (if enabled)"] + ACTIVE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: STATE_A) -> Self { + variant as u8 != 0 + } +} +impl STATE_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> STATE_A { + match self.bits { + false => STATE_A::REVOKED, + true => STATE_A::ACTIVE, + } + } + #[doc = "Checks if the value of the field is `REVOKED`"] + #[inline(always)] + pub fn is_revoked(&self) -> bool { + *self == STATE_A::REVOKED + } + #[doc = "Checks if the value of the field is `ACTIVE`"] + #[inline(always)] + pub fn is_active(&self) -> bool { + *self == STATE_A::ACTIVE + } +} +#[doc = "Field `STATE` writer - Revocation state for the key slot"] +pub type STATE_W<'a, const O: u8> = crate::BitWriter<'a, u32, PERM_SPEC, STATE_A, O>; +impl<'a, const O: u8> STATE_W<'a, O> { + #[doc = "Key value registers can no longer be read or pushed"] + #[inline(always)] + pub fn revoked(self) -> &'a mut W { + self.variant(STATE_A::REVOKED) + } + #[doc = "Key value registers are readable (if enabled) and can be pushed (if enabled)"] + #[inline(always)] + pub fn active(self) -> &'a mut W { + self.variant(STATE_A::ACTIVE) + } +} +impl R { + #[doc = "Bit 0 - Write permission for key slot"] + #[inline(always)] + pub fn write(&self) -> WRITE_R { + WRITE_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Read permission for key slot"] + #[inline(always)] + pub fn read(&self) -> READ_R { + READ_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Push permission for key slot"] + #[inline(always)] + pub fn push(&self) -> PUSH_R { + PUSH_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 16 - Revocation state for the key slot"] + #[inline(always)] + pub fn state(&self) -> STATE_R { + STATE_R::new(((self.bits >> 16) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Write permission for key slot"] + #[inline(always)] + pub fn write(&mut self) -> WRITE_W<0> { + WRITE_W::new(self) + } + #[doc = "Bit 1 - Read permission for key slot"] + #[inline(always)] + pub fn read(&mut self) -> READ_W<1> { + READ_W::new(self) + } + #[doc = "Bit 2 - Push permission for key slot"] + #[inline(always)] + pub fn push(&mut self) -> PUSH_W<2> { + PUSH_W::new(self) + } + #[doc = "Bit 16 - Revocation state for the key slot"] + #[inline(always)] + pub fn state(&mut self) -> STATE_W<16> { + STATE_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Description cluster: Define permissions for the key slot. Bits 0-15 and 16-31 can only be written when equal to 0xFFFF.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [perm](index.html) module"] +pub struct PERM_SPEC; +impl crate::RegisterSpec for PERM_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [perm::R](R) reader structure"] +impl crate::Readable for PERM_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [perm::W](W) writer structure"] +impl crate::Writable for PERM_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PERM to value 0xffff_ffff"] +impl crate::Resettable for PERM_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0xffff_ffff + } +} diff --git a/pacs/nrf9120-pac/src/uicr_s/keyslot/key.rs b/pacs/nrf9120-pac/src/uicr_s/keyslot/key.rs new file mode 100644 index 00000000..aa765a6b --- /dev/null +++ b/pacs/nrf9120-pac/src/uicr_s/keyslot/key.rs @@ -0,0 +1,12 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct KEY { + #[doc = "0x00..0x10 - Description collection: Define bits \\[31+o*32:0+o*32\\] +of value assigned to KMU key slot."] + pub value: [VALUE; 4], +} +#[doc = "VALUE (rw) register accessor: an alias for `Reg`"] +pub type VALUE = crate::Reg; +#[doc = "Description collection: Define bits \\[31+o*32:0+o*32\\] +of value assigned to KMU key slot."] +pub mod value; diff --git a/pacs/nrf9120-pac/src/uicr_s/keyslot/key/value.rs b/pacs/nrf9120-pac/src/uicr_s/keyslot/key/value.rs new file mode 100644 index 00000000..5bfa7806 --- /dev/null +++ b/pacs/nrf9120-pac/src/uicr_s/keyslot/key/value.rs @@ -0,0 +1,86 @@ +#[doc = "Register `VALUE[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `VALUE[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `VALUE` reader - Define bits \\[31+o*32:0+o*32\\] +of value assigned to KMU key slot"] +pub type VALUE_R = crate::FieldReader; +#[doc = "Field `VALUE` writer - Define bits \\[31+o*32:0+o*32\\] +of value assigned to KMU key slot"] +pub type VALUE_W<'a, const O: u8> = crate::FieldWriter<'a, u32, VALUE_SPEC, u32, u32, 32, O>; +impl R { + #[doc = "Bits 0:31 - Define bits \\[31+o*32:0+o*32\\] +of value assigned to KMU key slot"] + #[inline(always)] + pub fn value(&self) -> VALUE_R { + VALUE_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Define bits \\[31+o*32:0+o*32\\] +of value assigned to KMU key slot"] + #[inline(always)] + pub fn value(&mut self) -> VALUE_W<0> { + VALUE_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Description collection: Define bits \\[31+o*32:0+o*32\\] +of value assigned to KMU key slot.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [value](index.html) module"] +pub struct VALUE_SPEC; +impl crate::RegisterSpec for VALUE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [value::R](R) reader structure"] +impl crate::Readable for VALUE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [value::W](W) writer structure"] +impl crate::Writable for VALUE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets VALUE[%s] +to value 0xffff_ffff"] +impl crate::Resettable for VALUE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0xffff_ffff + } +} diff --git a/pacs/nrf9120-pac/src/uicr_s/otp.rs b/pacs/nrf9120-pac/src/uicr_s/otp.rs new file mode 100644 index 00000000..700e1df2 --- /dev/null +++ b/pacs/nrf9120-pac/src/uicr_s/otp.rs @@ -0,0 +1,95 @@ +#[doc = "Register `OTP[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `OTP[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `LOWER` reader - Lower half word"] +pub type LOWER_R = crate::FieldReader; +#[doc = "Field `LOWER` writer - Lower half word"] +pub type LOWER_W<'a, const O: u8> = crate::FieldWriter<'a, u32, OTP_SPEC, u16, u16, 16, O>; +#[doc = "Field `UPPER` reader - Upper half word"] +pub type UPPER_R = crate::FieldReader; +#[doc = "Field `UPPER` writer - Upper half word"] +pub type UPPER_W<'a, const O: u8> = crate::FieldWriter<'a, u32, OTP_SPEC, u16, u16, 16, O>; +impl R { + #[doc = "Bits 0:15 - Lower half word"] + #[inline(always)] + pub fn lower(&self) -> LOWER_R { + LOWER_R::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:31 - Upper half word"] + #[inline(always)] + pub fn upper(&self) -> UPPER_R { + UPPER_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Lower half word"] + #[inline(always)] + pub fn lower(&mut self) -> LOWER_W<0> { + LOWER_W::new(self) + } + #[doc = "Bits 16:31 - Upper half word"] + #[inline(always)] + pub fn upper(&mut self) -> UPPER_W<16> { + UPPER_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Description collection: One time programmable memory\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [otp](index.html) module"] +pub struct OTP_SPEC; +impl crate::RegisterSpec for OTP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [otp::R](R) reader structure"] +impl crate::Readable for OTP_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [otp::W](W) writer structure"] +impl crate::Writable for OTP_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets OTP[%s] +to value 0xffff_ffff"] +impl crate::Resettable for OTP_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0xffff_ffff + } +} diff --git a/pacs/nrf9120-pac/src/uicr_s/pmicconf.rs b/pacs/nrf9120-pac/src/uicr_s/pmicconf.rs new file mode 100644 index 00000000..0d42f453 --- /dev/null +++ b/pacs/nrf9120-pac/src/uicr_s/pmicconf.rs @@ -0,0 +1,127 @@ +#[doc = "Register `PMICCONF` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PMICCONF` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PMICFPWMPOL` reader - Polarity of PMIC_FPWM signal."] +pub type PMICFPWMPOL_R = crate::BitReader; +#[doc = "Polarity of PMIC_FPWM signal.\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PMICFPWMPOL_A { + #[doc = "0: PMIC_FPWM output signal is active-low"] + ACTIVE_LOW = 0, + #[doc = "1: PMIC_FPWM output signal is active-high"] + ACTIVE_HIGH = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PMICFPWMPOL_A) -> Self { + variant as u8 != 0 + } +} +impl PMICFPWMPOL_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PMICFPWMPOL_A { + match self.bits { + false => PMICFPWMPOL_A::ACTIVE_LOW, + true => PMICFPWMPOL_A::ACTIVE_HIGH, + } + } + #[doc = "Checks if the value of the field is `ACTIVE_LOW`"] + #[inline(always)] + pub fn is_active_low(&self) -> bool { + *self == PMICFPWMPOL_A::ACTIVE_LOW + } + #[doc = "Checks if the value of the field is `ACTIVE_HIGH`"] + #[inline(always)] + pub fn is_active_high(&self) -> bool { + *self == PMICFPWMPOL_A::ACTIVE_HIGH + } +} +#[doc = "Field `PMICFPWMPOL` writer - Polarity of PMIC_FPWM signal."] +pub type PMICFPWMPOL_W<'a, const O: u8> = + crate::BitWriter<'a, u32, PMICCONF_SPEC, PMICFPWMPOL_A, O>; +impl<'a, const O: u8> PMICFPWMPOL_W<'a, O> { + #[doc = "PMIC_FPWM output signal is active-low"] + #[inline(always)] + pub fn active_low(self) -> &'a mut W { + self.variant(PMICFPWMPOL_A::ACTIVE_LOW) + } + #[doc = "PMIC_FPWM output signal is active-high"] + #[inline(always)] + pub fn active_high(self) -> &'a mut W { + self.variant(PMICFPWMPOL_A::ACTIVE_HIGH) + } +} +impl R { + #[doc = "Bit 0 - Polarity of PMIC_FPWM signal."] + #[inline(always)] + pub fn pmicfpwmpol(&self) -> PMICFPWMPOL_R { + PMICFPWMPOL_R::new((self.bits & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Polarity of PMIC_FPWM signal."] + #[inline(always)] + pub fn pmicfpwmpol(&mut self) -> PMICFPWMPOL_W<0> { + PMICFPWMPOL_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Polarity of PMIC polarity configuration signals.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pmicconf](index.html) module"] +pub struct PMICCONF_SPEC; +impl crate::RegisterSpec for PMICCONF_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pmicconf::R](R) reader structure"] +impl crate::Readable for PMICCONF_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [pmicconf::W](W) writer structure"] +impl crate::Writable for PMICCONF_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PMICCONF to value 0xffff_ffff"] +impl crate::Resettable for PMICCONF_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0xffff_ffff + } +} diff --git a/pacs/nrf9120-pac/src/uicr_s/secureapprotect.rs b/pacs/nrf9120-pac/src/uicr_s/secureapprotect.rs new file mode 100644 index 00000000..db7b5254 --- /dev/null +++ b/pacs/nrf9120-pac/src/uicr_s/secureapprotect.rs @@ -0,0 +1,129 @@ +#[doc = "Register `SECUREAPPROTECT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SECUREAPPROTECT` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PALL` reader - Blocks debugger read/write access to all secure CPU registers and secure memory mapped addresses"] +pub type PALL_R = crate::FieldReader; +#[doc = "Blocks debugger read/write access to all secure CPU registers and secure memory mapped addresses\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u32)] +pub enum PALL_A { + #[doc = "1358582010: HwUnprotected"] + HW_UNPROTECTED = 1358582010, + #[doc = "0: Protected"] + PROTECTED = 0, +} +impl From for u32 { + #[inline(always)] + fn from(variant: PALL_A) -> Self { + variant as _ + } +} +impl PALL_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 1358582010 => Some(PALL_A::HW_UNPROTECTED), + 0 => Some(PALL_A::PROTECTED), + _ => None, + } + } + #[doc = "Checks if the value of the field is `HW_UNPROTECTED`"] + #[inline(always)] + pub fn is_hw_unprotected(&self) -> bool { + *self == PALL_A::HW_UNPROTECTED + } + #[doc = "Checks if the value of the field is `PROTECTED`"] + #[inline(always)] + pub fn is_protected(&self) -> bool { + *self == PALL_A::PROTECTED + } +} +#[doc = "Field `PALL` writer - Blocks debugger read/write access to all secure CPU registers and secure memory mapped addresses"] +pub type PALL_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, SECUREAPPROTECT_SPEC, u32, PALL_A, 32, O>; +impl<'a, const O: u8> PALL_W<'a, O> { + #[doc = "HwUnprotected"] + #[inline(always)] + pub fn hw_unprotected(self) -> &'a mut W { + self.variant(PALL_A::HW_UNPROTECTED) + } + #[doc = "Protected"] + #[inline(always)] + pub fn protected(self) -> &'a mut W { + self.variant(PALL_A::PROTECTED) + } +} +impl R { + #[doc = "Bits 0:31 - Blocks debugger read/write access to all secure CPU registers and secure memory mapped addresses"] + #[inline(always)] + pub fn pall(&self) -> PALL_R { + PALL_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Blocks debugger read/write access to all secure CPU registers and secure memory mapped addresses"] + #[inline(always)] + pub fn pall(&mut self) -> PALL_W<0> { + PALL_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Secure access port protection\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [secureapprotect](index.html) module"] +pub struct SECUREAPPROTECT_SPEC; +impl crate::RegisterSpec for SECUREAPPROTECT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [secureapprotect::R](R) reader structure"] +impl crate::Readable for SECUREAPPROTECT_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [secureapprotect::W](W) writer structure"] +impl crate::Writable for SECUREAPPROTECT_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SECUREAPPROTECT to value 0"] +impl crate::Resettable for SECUREAPPROTECT_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/uicr_s/xosc32m.rs b/pacs/nrf9120-pac/src/uicr_s/xosc32m.rs new file mode 100644 index 00000000..6b193dce --- /dev/null +++ b/pacs/nrf9120-pac/src/uicr_s/xosc32m.rs @@ -0,0 +1,80 @@ +#[doc = "Register `XOSC32M` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `XOSC32M` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CTRL` reader - Pierce current DAC control signals"] +pub type CTRL_R = crate::FieldReader; +#[doc = "Field `CTRL` writer - Pierce current DAC control signals"] +pub type CTRL_W<'a, const O: u8> = crate::FieldWriter<'a, u32, XOSC32M_SPEC, u8, u8, 6, O>; +impl R { + #[doc = "Bits 0:5 - Pierce current DAC control signals"] + #[inline(always)] + pub fn ctrl(&self) -> CTRL_R { + CTRL_R::new((self.bits & 0x3f) as u8) + } +} +impl W { + #[doc = "Bits 0:5 - Pierce current DAC control signals"] + #[inline(always)] + pub fn ctrl(&mut self) -> CTRL_W<0> { + CTRL_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Oscillator control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [xosc32m](index.html) module"] +pub struct XOSC32M_SPEC; +impl crate::RegisterSpec for XOSC32M_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [xosc32m::R](R) reader structure"] +impl crate::Readable for XOSC32M_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [xosc32m::W](W) writer structure"] +impl crate::Writable for XOSC32M_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets XOSC32M to value 0xffff_ffcf"] +impl crate::Resettable for XOSC32M_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0xffff_ffcf + } +} diff --git a/pacs/nrf9120-pac/src/vmc_ns.rs b/pacs/nrf9120-pac/src/vmc_ns.rs new file mode 100644 index 00000000..548c3d06 --- /dev/null +++ b/pacs/nrf9120-pac/src/vmc_ns.rs @@ -0,0 +1,33 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + _reserved0: [u8; 0x0600], + #[doc = "0x600..0x60c - Unspecified"] + pub ram0: RAM, + _reserved1: [u8; 0x04], + #[doc = "0x610..0x61c - Unspecified"] + pub ram1: RAM, + _reserved2: [u8; 0x04], + #[doc = "0x620..0x62c - Unspecified"] + pub ram2: RAM, + _reserved3: [u8; 0x04], + #[doc = "0x630..0x63c - Unspecified"] + pub ram3: RAM, + _reserved4: [u8; 0x04], + #[doc = "0x640..0x64c - Unspecified"] + pub ram4: RAM, + _reserved5: [u8; 0x04], + #[doc = "0x650..0x65c - Unspecified"] + pub ram5: RAM, + _reserved6: [u8; 0x04], + #[doc = "0x660..0x66c - Unspecified"] + pub ram6: RAM, + _reserved7: [u8; 0x04], + #[doc = "0x670..0x67c - Unspecified"] + pub ram7: RAM, +} +#[doc = "Unspecified"] +pub use ram::RAM; +#[doc = r"Cluster"] +#[doc = "Unspecified"] +pub mod ram; diff --git a/pacs/nrf9120-pac/src/vmc_ns/ram.rs b/pacs/nrf9120-pac/src/vmc_ns/ram.rs new file mode 100644 index 00000000..4a7baf8e --- /dev/null +++ b/pacs/nrf9120-pac/src/vmc_ns/ram.rs @@ -0,0 +1,22 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RAM { + #[doc = "0x00 - Description cluster: RAMn power control register"] + pub power: POWER, + #[doc = "0x04 - Description cluster: RAMn power control set register"] + pub powerset: POWERSET, + #[doc = "0x08 - Description cluster: RAMn power control clear register"] + pub powerclr: POWERCLR, +} +#[doc = "POWER (rw) register accessor: an alias for `Reg`"] +pub type POWER = crate::Reg; +#[doc = "Description cluster: RAMn power control register"] +pub mod power; +#[doc = "POWERSET (w) register accessor: an alias for `Reg`"] +pub type POWERSET = crate::Reg; +#[doc = "Description cluster: RAMn power control set register"] +pub mod powerset; +#[doc = "POWERCLR (w) register accessor: an alias for `Reg`"] +pub type POWERCLR = crate::Reg; +#[doc = "Description cluster: RAMn power control clear register"] +pub mod powerclr; diff --git a/pacs/nrf9120-pac/src/vmc_ns/ram/power.rs b/pacs/nrf9120-pac/src/vmc_ns/ram/power.rs new file mode 100644 index 00000000..77af6477 --- /dev/null +++ b/pacs/nrf9120-pac/src/vmc_ns/ram/power.rs @@ -0,0 +1,546 @@ +#[doc = "Register `POWER` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `POWER` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `S0POWER` reader - Keep RAM section S0 of RAM n on or off in System ON mode"] +pub type S0POWER_R = crate::BitReader; +#[doc = "Keep RAM section S0 of RAM n on or off in System ON mode\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum S0POWER_A { + #[doc = "0: Off"] + OFF = 0, + #[doc = "1: On"] + ON = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: S0POWER_A) -> Self { + variant as u8 != 0 + } +} +impl S0POWER_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> S0POWER_A { + match self.bits { + false => S0POWER_A::OFF, + true => S0POWER_A::ON, + } + } + #[doc = "Checks if the value of the field is `OFF`"] + #[inline(always)] + pub fn is_off(&self) -> bool { + *self == S0POWER_A::OFF + } + #[doc = "Checks if the value of the field is `ON`"] + #[inline(always)] + pub fn is_on(&self) -> bool { + *self == S0POWER_A::ON + } +} +#[doc = "Field `S0POWER` writer - Keep RAM section S0 of RAM n on or off in System ON mode"] +pub type S0POWER_W<'a, const O: u8> = crate::BitWriter<'a, u32, POWER_SPEC, S0POWER_A, O>; +impl<'a, const O: u8> S0POWER_W<'a, O> { + #[doc = "Off"] + #[inline(always)] + pub fn off(self) -> &'a mut W { + self.variant(S0POWER_A::OFF) + } + #[doc = "On"] + #[inline(always)] + pub fn on(self) -> &'a mut W { + self.variant(S0POWER_A::ON) + } +} +#[doc = "Field `S1POWER` reader - Keep RAM section S1 of RAM n on or off in System ON mode"] +pub type S1POWER_R = crate::BitReader; +#[doc = "Keep RAM section S1 of RAM n on or off in System ON mode\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum S1POWER_A { + #[doc = "0: Off"] + OFF = 0, + #[doc = "1: On"] + ON = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: S1POWER_A) -> Self { + variant as u8 != 0 + } +} +impl S1POWER_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> S1POWER_A { + match self.bits { + false => S1POWER_A::OFF, + true => S1POWER_A::ON, + } + } + #[doc = "Checks if the value of the field is `OFF`"] + #[inline(always)] + pub fn is_off(&self) -> bool { + *self == S1POWER_A::OFF + } + #[doc = "Checks if the value of the field is `ON`"] + #[inline(always)] + pub fn is_on(&self) -> bool { + *self == S1POWER_A::ON + } +} +#[doc = "Field `S1POWER` writer - Keep RAM section S1 of RAM n on or off in System ON mode"] +pub type S1POWER_W<'a, const O: u8> = crate::BitWriter<'a, u32, POWER_SPEC, S1POWER_A, O>; +impl<'a, const O: u8> S1POWER_W<'a, O> { + #[doc = "Off"] + #[inline(always)] + pub fn off(self) -> &'a mut W { + self.variant(S1POWER_A::OFF) + } + #[doc = "On"] + #[inline(always)] + pub fn on(self) -> &'a mut W { + self.variant(S1POWER_A::ON) + } +} +#[doc = "Field `S2POWER` reader - Keep RAM section S2 of RAM n on or off in System ON mode"] +pub type S2POWER_R = crate::BitReader; +#[doc = "Keep RAM section S2 of RAM n on or off in System ON mode\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum S2POWER_A { + #[doc = "0: Off"] + OFF = 0, + #[doc = "1: On"] + ON = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: S2POWER_A) -> Self { + variant as u8 != 0 + } +} +impl S2POWER_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> S2POWER_A { + match self.bits { + false => S2POWER_A::OFF, + true => S2POWER_A::ON, + } + } + #[doc = "Checks if the value of the field is `OFF`"] + #[inline(always)] + pub fn is_off(&self) -> bool { + *self == S2POWER_A::OFF + } + #[doc = "Checks if the value of the field is `ON`"] + #[inline(always)] + pub fn is_on(&self) -> bool { + *self == S2POWER_A::ON + } +} +#[doc = "Field `S2POWER` writer - Keep RAM section S2 of RAM n on or off in System ON mode"] +pub type S2POWER_W<'a, const O: u8> = crate::BitWriter<'a, u32, POWER_SPEC, S2POWER_A, O>; +impl<'a, const O: u8> S2POWER_W<'a, O> { + #[doc = "Off"] + #[inline(always)] + pub fn off(self) -> &'a mut W { + self.variant(S2POWER_A::OFF) + } + #[doc = "On"] + #[inline(always)] + pub fn on(self) -> &'a mut W { + self.variant(S2POWER_A::ON) + } +} +#[doc = "Field `S3POWER` reader - Keep RAM section S3 of RAM n on or off in System ON mode"] +pub type S3POWER_R = crate::BitReader; +#[doc = "Keep RAM section S3 of RAM n on or off in System ON mode\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum S3POWER_A { + #[doc = "0: Off"] + OFF = 0, + #[doc = "1: On"] + ON = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: S3POWER_A) -> Self { + variant as u8 != 0 + } +} +impl S3POWER_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> S3POWER_A { + match self.bits { + false => S3POWER_A::OFF, + true => S3POWER_A::ON, + } + } + #[doc = "Checks if the value of the field is `OFF`"] + #[inline(always)] + pub fn is_off(&self) -> bool { + *self == S3POWER_A::OFF + } + #[doc = "Checks if the value of the field is `ON`"] + #[inline(always)] + pub fn is_on(&self) -> bool { + *self == S3POWER_A::ON + } +} +#[doc = "Field `S3POWER` writer - Keep RAM section S3 of RAM n on or off in System ON mode"] +pub type S3POWER_W<'a, const O: u8> = crate::BitWriter<'a, u32, POWER_SPEC, S3POWER_A, O>; +impl<'a, const O: u8> S3POWER_W<'a, O> { + #[doc = "Off"] + #[inline(always)] + pub fn off(self) -> &'a mut W { + self.variant(S3POWER_A::OFF) + } + #[doc = "On"] + #[inline(always)] + pub fn on(self) -> &'a mut W { + self.variant(S3POWER_A::ON) + } +} +#[doc = "Field `S0RETENTION` reader - Keep retention on RAM section S0 of RAM n when RAM section is switched off"] +pub type S0RETENTION_R = crate::BitReader; +#[doc = "Keep retention on RAM section S0 of RAM n when RAM section is switched off\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum S0RETENTION_A { + #[doc = "0: Off"] + OFF = 0, + #[doc = "1: On"] + ON = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: S0RETENTION_A) -> Self { + variant as u8 != 0 + } +} +impl S0RETENTION_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> S0RETENTION_A { + match self.bits { + false => S0RETENTION_A::OFF, + true => S0RETENTION_A::ON, + } + } + #[doc = "Checks if the value of the field is `OFF`"] + #[inline(always)] + pub fn is_off(&self) -> bool { + *self == S0RETENTION_A::OFF + } + #[doc = "Checks if the value of the field is `ON`"] + #[inline(always)] + pub fn is_on(&self) -> bool { + *self == S0RETENTION_A::ON + } +} +#[doc = "Field `S0RETENTION` writer - Keep retention on RAM section S0 of RAM n when RAM section is switched off"] +pub type S0RETENTION_W<'a, const O: u8> = crate::BitWriter<'a, u32, POWER_SPEC, S0RETENTION_A, O>; +impl<'a, const O: u8> S0RETENTION_W<'a, O> { + #[doc = "Off"] + #[inline(always)] + pub fn off(self) -> &'a mut W { + self.variant(S0RETENTION_A::OFF) + } + #[doc = "On"] + #[inline(always)] + pub fn on(self) -> &'a mut W { + self.variant(S0RETENTION_A::ON) + } +} +#[doc = "Field `S1RETENTION` reader - Keep retention on RAM section S1 of RAM n when RAM section is switched off"] +pub type S1RETENTION_R = crate::BitReader; +#[doc = "Keep retention on RAM section S1 of RAM n when RAM section is switched off\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum S1RETENTION_A { + #[doc = "0: Off"] + OFF = 0, + #[doc = "1: On"] + ON = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: S1RETENTION_A) -> Self { + variant as u8 != 0 + } +} +impl S1RETENTION_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> S1RETENTION_A { + match self.bits { + false => S1RETENTION_A::OFF, + true => S1RETENTION_A::ON, + } + } + #[doc = "Checks if the value of the field is `OFF`"] + #[inline(always)] + pub fn is_off(&self) -> bool { + *self == S1RETENTION_A::OFF + } + #[doc = "Checks if the value of the field is `ON`"] + #[inline(always)] + pub fn is_on(&self) -> bool { + *self == S1RETENTION_A::ON + } +} +#[doc = "Field `S1RETENTION` writer - Keep retention on RAM section S1 of RAM n when RAM section is switched off"] +pub type S1RETENTION_W<'a, const O: u8> = crate::BitWriter<'a, u32, POWER_SPEC, S1RETENTION_A, O>; +impl<'a, const O: u8> S1RETENTION_W<'a, O> { + #[doc = "Off"] + #[inline(always)] + pub fn off(self) -> &'a mut W { + self.variant(S1RETENTION_A::OFF) + } + #[doc = "On"] + #[inline(always)] + pub fn on(self) -> &'a mut W { + self.variant(S1RETENTION_A::ON) + } +} +#[doc = "Field `S2RETENTION` reader - Keep retention on RAM section S2 of RAM n when RAM section is switched off"] +pub type S2RETENTION_R = crate::BitReader; +#[doc = "Keep retention on RAM section S2 of RAM n when RAM section is switched off\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum S2RETENTION_A { + #[doc = "0: Off"] + OFF = 0, + #[doc = "1: On"] + ON = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: S2RETENTION_A) -> Self { + variant as u8 != 0 + } +} +impl S2RETENTION_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> S2RETENTION_A { + match self.bits { + false => S2RETENTION_A::OFF, + true => S2RETENTION_A::ON, + } + } + #[doc = "Checks if the value of the field is `OFF`"] + #[inline(always)] + pub fn is_off(&self) -> bool { + *self == S2RETENTION_A::OFF + } + #[doc = "Checks if the value of the field is `ON`"] + #[inline(always)] + pub fn is_on(&self) -> bool { + *self == S2RETENTION_A::ON + } +} +#[doc = "Field `S2RETENTION` writer - Keep retention on RAM section S2 of RAM n when RAM section is switched off"] +pub type S2RETENTION_W<'a, const O: u8> = crate::BitWriter<'a, u32, POWER_SPEC, S2RETENTION_A, O>; +impl<'a, const O: u8> S2RETENTION_W<'a, O> { + #[doc = "Off"] + #[inline(always)] + pub fn off(self) -> &'a mut W { + self.variant(S2RETENTION_A::OFF) + } + #[doc = "On"] + #[inline(always)] + pub fn on(self) -> &'a mut W { + self.variant(S2RETENTION_A::ON) + } +} +#[doc = "Field `S3RETENTION` reader - Keep retention on RAM section S3 of RAM n when RAM section is switched off"] +pub type S3RETENTION_R = crate::BitReader; +#[doc = "Keep retention on RAM section S3 of RAM n when RAM section is switched off\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum S3RETENTION_A { + #[doc = "0: Off"] + OFF = 0, + #[doc = "1: On"] + ON = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: S3RETENTION_A) -> Self { + variant as u8 != 0 + } +} +impl S3RETENTION_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> S3RETENTION_A { + match self.bits { + false => S3RETENTION_A::OFF, + true => S3RETENTION_A::ON, + } + } + #[doc = "Checks if the value of the field is `OFF`"] + #[inline(always)] + pub fn is_off(&self) -> bool { + *self == S3RETENTION_A::OFF + } + #[doc = "Checks if the value of the field is `ON`"] + #[inline(always)] + pub fn is_on(&self) -> bool { + *self == S3RETENTION_A::ON + } +} +#[doc = "Field `S3RETENTION` writer - Keep retention on RAM section S3 of RAM n when RAM section is switched off"] +pub type S3RETENTION_W<'a, const O: u8> = crate::BitWriter<'a, u32, POWER_SPEC, S3RETENTION_A, O>; +impl<'a, const O: u8> S3RETENTION_W<'a, O> { + #[doc = "Off"] + #[inline(always)] + pub fn off(self) -> &'a mut W { + self.variant(S3RETENTION_A::OFF) + } + #[doc = "On"] + #[inline(always)] + pub fn on(self) -> &'a mut W { + self.variant(S3RETENTION_A::ON) + } +} +impl R { + #[doc = "Bit 0 - Keep RAM section S0 of RAM n on or off in System ON mode"] + #[inline(always)] + pub fn s0power(&self) -> S0POWER_R { + S0POWER_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Keep RAM section S1 of RAM n on or off in System ON mode"] + #[inline(always)] + pub fn s1power(&self) -> S1POWER_R { + S1POWER_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Keep RAM section S2 of RAM n on or off in System ON mode"] + #[inline(always)] + pub fn s2power(&self) -> S2POWER_R { + S2POWER_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Keep RAM section S3 of RAM n on or off in System ON mode"] + #[inline(always)] + pub fn s3power(&self) -> S3POWER_R { + S3POWER_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 16 - Keep retention on RAM section S0 of RAM n when RAM section is switched off"] + #[inline(always)] + pub fn s0retention(&self) -> S0RETENTION_R { + S0RETENTION_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Keep retention on RAM section S1 of RAM n when RAM section is switched off"] + #[inline(always)] + pub fn s1retention(&self) -> S1RETENTION_R { + S1RETENTION_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Keep retention on RAM section S2 of RAM n when RAM section is switched off"] + #[inline(always)] + pub fn s2retention(&self) -> S2RETENTION_R { + S2RETENTION_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Keep retention on RAM section S3 of RAM n when RAM section is switched off"] + #[inline(always)] + pub fn s3retention(&self) -> S3RETENTION_R { + S3RETENTION_R::new(((self.bits >> 19) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Keep RAM section S0 of RAM n on or off in System ON mode"] + #[inline(always)] + pub fn s0power(&mut self) -> S0POWER_W<0> { + S0POWER_W::new(self) + } + #[doc = "Bit 1 - Keep RAM section S1 of RAM n on or off in System ON mode"] + #[inline(always)] + pub fn s1power(&mut self) -> S1POWER_W<1> { + S1POWER_W::new(self) + } + #[doc = "Bit 2 - Keep RAM section S2 of RAM n on or off in System ON mode"] + #[inline(always)] + pub fn s2power(&mut self) -> S2POWER_W<2> { + S2POWER_W::new(self) + } + #[doc = "Bit 3 - Keep RAM section S3 of RAM n on or off in System ON mode"] + #[inline(always)] + pub fn s3power(&mut self) -> S3POWER_W<3> { + S3POWER_W::new(self) + } + #[doc = "Bit 16 - Keep retention on RAM section S0 of RAM n when RAM section is switched off"] + #[inline(always)] + pub fn s0retention(&mut self) -> S0RETENTION_W<16> { + S0RETENTION_W::new(self) + } + #[doc = "Bit 17 - Keep retention on RAM section S1 of RAM n when RAM section is switched off"] + #[inline(always)] + pub fn s1retention(&mut self) -> S1RETENTION_W<17> { + S1RETENTION_W::new(self) + } + #[doc = "Bit 18 - Keep retention on RAM section S2 of RAM n when RAM section is switched off"] + #[inline(always)] + pub fn s2retention(&mut self) -> S2RETENTION_W<18> { + S2RETENTION_W::new(self) + } + #[doc = "Bit 19 - Keep retention on RAM section S3 of RAM n when RAM section is switched off"] + #[inline(always)] + pub fn s3retention(&mut self) -> S3RETENTION_W<19> { + S3RETENTION_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Description cluster: RAMn power control register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [power](index.html) module"] +pub struct POWER_SPEC; +impl crate::RegisterSpec for POWER_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [power::R](R) reader structure"] +impl crate::Readable for POWER_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [power::W](W) writer structure"] +impl crate::Writable for POWER_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets POWER to value 0xffff"] +impl crate::Resettable for POWER_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0xffff + } +} diff --git a/pacs/nrf9120-pac/src/vmc_ns/ram/powerclr.rs b/pacs/nrf9120-pac/src/vmc_ns/ram/powerclr.rs new file mode 100644 index 00000000..20256f92 --- /dev/null +++ b/pacs/nrf9120-pac/src/vmc_ns/ram/powerclr.rs @@ -0,0 +1,257 @@ +#[doc = "Register `POWERCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Keep RAM section S0 of RAM n on or off in System ON mode\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum S0POWER_AW { + #[doc = "1: Off"] + OFF = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: S0POWER_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `S0POWER` writer - Keep RAM section S0 of RAM n on or off in System ON mode"] +pub type S0POWER_W<'a, const O: u8> = crate::BitWriter<'a, u32, POWERCLR_SPEC, S0POWER_AW, O>; +impl<'a, const O: u8> S0POWER_W<'a, O> { + #[doc = "Off"] + #[inline(always)] + pub fn off(self) -> &'a mut W { + self.variant(S0POWER_AW::OFF) + } +} +#[doc = "Keep RAM section S1 of RAM n on or off in System ON mode\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum S1POWER_AW { + #[doc = "1: Off"] + OFF = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: S1POWER_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `S1POWER` writer - Keep RAM section S1 of RAM n on or off in System ON mode"] +pub type S1POWER_W<'a, const O: u8> = crate::BitWriter<'a, u32, POWERCLR_SPEC, S1POWER_AW, O>; +impl<'a, const O: u8> S1POWER_W<'a, O> { + #[doc = "Off"] + #[inline(always)] + pub fn off(self) -> &'a mut W { + self.variant(S1POWER_AW::OFF) + } +} +#[doc = "Keep RAM section S2 of RAM n on or off in System ON mode\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum S2POWER_AW { + #[doc = "1: Off"] + OFF = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: S2POWER_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `S2POWER` writer - Keep RAM section S2 of RAM n on or off in System ON mode"] +pub type S2POWER_W<'a, const O: u8> = crate::BitWriter<'a, u32, POWERCLR_SPEC, S2POWER_AW, O>; +impl<'a, const O: u8> S2POWER_W<'a, O> { + #[doc = "Off"] + #[inline(always)] + pub fn off(self) -> &'a mut W { + self.variant(S2POWER_AW::OFF) + } +} +#[doc = "Keep RAM section S3 of RAM n on or off in System ON mode\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum S3POWER_AW { + #[doc = "1: Off"] + OFF = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: S3POWER_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `S3POWER` writer - Keep RAM section S3 of RAM n on or off in System ON mode"] +pub type S3POWER_W<'a, const O: u8> = crate::BitWriter<'a, u32, POWERCLR_SPEC, S3POWER_AW, O>; +impl<'a, const O: u8> S3POWER_W<'a, O> { + #[doc = "Off"] + #[inline(always)] + pub fn off(self) -> &'a mut W { + self.variant(S3POWER_AW::OFF) + } +} +#[doc = "Keep retention on RAM section S0 of RAM n when RAM section is switched off\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum S0RETENTION_AW { + #[doc = "1: Off"] + OFF = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: S0RETENTION_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `S0RETENTION` writer - Keep retention on RAM section S0 of RAM n when RAM section is switched off"] +pub type S0RETENTION_W<'a, const O: u8> = + crate::BitWriter<'a, u32, POWERCLR_SPEC, S0RETENTION_AW, O>; +impl<'a, const O: u8> S0RETENTION_W<'a, O> { + #[doc = "Off"] + #[inline(always)] + pub fn off(self) -> &'a mut W { + self.variant(S0RETENTION_AW::OFF) + } +} +#[doc = "Keep retention on RAM section S1 of RAM n when RAM section is switched off\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum S1RETENTION_AW { + #[doc = "1: Off"] + OFF = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: S1RETENTION_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `S1RETENTION` writer - Keep retention on RAM section S1 of RAM n when RAM section is switched off"] +pub type S1RETENTION_W<'a, const O: u8> = + crate::BitWriter<'a, u32, POWERCLR_SPEC, S1RETENTION_AW, O>; +impl<'a, const O: u8> S1RETENTION_W<'a, O> { + #[doc = "Off"] + #[inline(always)] + pub fn off(self) -> &'a mut W { + self.variant(S1RETENTION_AW::OFF) + } +} +#[doc = "Keep retention on RAM section S2 of RAM n when RAM section is switched off\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum S2RETENTION_AW { + #[doc = "1: Off"] + OFF = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: S2RETENTION_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `S2RETENTION` writer - Keep retention on RAM section S2 of RAM n when RAM section is switched off"] +pub type S2RETENTION_W<'a, const O: u8> = + crate::BitWriter<'a, u32, POWERCLR_SPEC, S2RETENTION_AW, O>; +impl<'a, const O: u8> S2RETENTION_W<'a, O> { + #[doc = "Off"] + #[inline(always)] + pub fn off(self) -> &'a mut W { + self.variant(S2RETENTION_AW::OFF) + } +} +#[doc = "Keep retention on RAM section S3 of RAM n when RAM section is switched off\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum S3RETENTION_AW { + #[doc = "1: Off"] + OFF = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: S3RETENTION_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `S3RETENTION` writer - Keep retention on RAM section S3 of RAM n when RAM section is switched off"] +pub type S3RETENTION_W<'a, const O: u8> = + crate::BitWriter<'a, u32, POWERCLR_SPEC, S3RETENTION_AW, O>; +impl<'a, const O: u8> S3RETENTION_W<'a, O> { + #[doc = "Off"] + #[inline(always)] + pub fn off(self) -> &'a mut W { + self.variant(S3RETENTION_AW::OFF) + } +} +impl W { + #[doc = "Bit 0 - Keep RAM section S0 of RAM n on or off in System ON mode"] + #[inline(always)] + pub fn s0power(&mut self) -> S0POWER_W<0> { + S0POWER_W::new(self) + } + #[doc = "Bit 1 - Keep RAM section S1 of RAM n on or off in System ON mode"] + #[inline(always)] + pub fn s1power(&mut self) -> S1POWER_W<1> { + S1POWER_W::new(self) + } + #[doc = "Bit 2 - Keep RAM section S2 of RAM n on or off in System ON mode"] + #[inline(always)] + pub fn s2power(&mut self) -> S2POWER_W<2> { + S2POWER_W::new(self) + } + #[doc = "Bit 3 - Keep RAM section S3 of RAM n on or off in System ON mode"] + #[inline(always)] + pub fn s3power(&mut self) -> S3POWER_W<3> { + S3POWER_W::new(self) + } + #[doc = "Bit 16 - Keep retention on RAM section S0 of RAM n when RAM section is switched off"] + #[inline(always)] + pub fn s0retention(&mut self) -> S0RETENTION_W<16> { + S0RETENTION_W::new(self) + } + #[doc = "Bit 17 - Keep retention on RAM section S1 of RAM n when RAM section is switched off"] + #[inline(always)] + pub fn s1retention(&mut self) -> S1RETENTION_W<17> { + S1RETENTION_W::new(self) + } + #[doc = "Bit 18 - Keep retention on RAM section S2 of RAM n when RAM section is switched off"] + #[inline(always)] + pub fn s2retention(&mut self) -> S2RETENTION_W<18> { + S2RETENTION_W::new(self) + } + #[doc = "Bit 19 - Keep retention on RAM section S3 of RAM n when RAM section is switched off"] + #[inline(always)] + pub fn s3retention(&mut self) -> S3RETENTION_W<19> { + S3RETENTION_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Description cluster: RAMn power control clear register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [powerclr](index.html) module"] +pub struct POWERCLR_SPEC; +impl crate::RegisterSpec for POWERCLR_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [powerclr::W](W) writer structure"] +impl crate::Writable for POWERCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets POWERCLR to value 0xffff"] +impl crate::Resettable for POWERCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0xffff + } +} diff --git a/pacs/nrf9120-pac/src/vmc_ns/ram/powerset.rs b/pacs/nrf9120-pac/src/vmc_ns/ram/powerset.rs new file mode 100644 index 00000000..aca854f0 --- /dev/null +++ b/pacs/nrf9120-pac/src/vmc_ns/ram/powerset.rs @@ -0,0 +1,257 @@ +#[doc = "Register `POWERSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Keep RAM section S0 of RAM n on or off in System ON mode\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum S0POWER_AW { + #[doc = "1: On"] + ON = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: S0POWER_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `S0POWER` writer - Keep RAM section S0 of RAM n on or off in System ON mode"] +pub type S0POWER_W<'a, const O: u8> = crate::BitWriter<'a, u32, POWERSET_SPEC, S0POWER_AW, O>; +impl<'a, const O: u8> S0POWER_W<'a, O> { + #[doc = "On"] + #[inline(always)] + pub fn on(self) -> &'a mut W { + self.variant(S0POWER_AW::ON) + } +} +#[doc = "Keep RAM section S1 of RAM n on or off in System ON mode\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum S1POWER_AW { + #[doc = "1: On"] + ON = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: S1POWER_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `S1POWER` writer - Keep RAM section S1 of RAM n on or off in System ON mode"] +pub type S1POWER_W<'a, const O: u8> = crate::BitWriter<'a, u32, POWERSET_SPEC, S1POWER_AW, O>; +impl<'a, const O: u8> S1POWER_W<'a, O> { + #[doc = "On"] + #[inline(always)] + pub fn on(self) -> &'a mut W { + self.variant(S1POWER_AW::ON) + } +} +#[doc = "Keep RAM section S2 of RAM n on or off in System ON mode\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum S2POWER_AW { + #[doc = "1: On"] + ON = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: S2POWER_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `S2POWER` writer - Keep RAM section S2 of RAM n on or off in System ON mode"] +pub type S2POWER_W<'a, const O: u8> = crate::BitWriter<'a, u32, POWERSET_SPEC, S2POWER_AW, O>; +impl<'a, const O: u8> S2POWER_W<'a, O> { + #[doc = "On"] + #[inline(always)] + pub fn on(self) -> &'a mut W { + self.variant(S2POWER_AW::ON) + } +} +#[doc = "Keep RAM section S3 of RAM n on or off in System ON mode\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum S3POWER_AW { + #[doc = "1: On"] + ON = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: S3POWER_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `S3POWER` writer - Keep RAM section S3 of RAM n on or off in System ON mode"] +pub type S3POWER_W<'a, const O: u8> = crate::BitWriter<'a, u32, POWERSET_SPEC, S3POWER_AW, O>; +impl<'a, const O: u8> S3POWER_W<'a, O> { + #[doc = "On"] + #[inline(always)] + pub fn on(self) -> &'a mut W { + self.variant(S3POWER_AW::ON) + } +} +#[doc = "Keep retention on RAM section S0 of RAM n when RAM section is switched off\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum S0RETENTION_AW { + #[doc = "1: On"] + ON = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: S0RETENTION_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `S0RETENTION` writer - Keep retention on RAM section S0 of RAM n when RAM section is switched off"] +pub type S0RETENTION_W<'a, const O: u8> = + crate::BitWriter<'a, u32, POWERSET_SPEC, S0RETENTION_AW, O>; +impl<'a, const O: u8> S0RETENTION_W<'a, O> { + #[doc = "On"] + #[inline(always)] + pub fn on(self) -> &'a mut W { + self.variant(S0RETENTION_AW::ON) + } +} +#[doc = "Keep retention on RAM section S1 of RAM n when RAM section is switched off\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum S1RETENTION_AW { + #[doc = "1: On"] + ON = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: S1RETENTION_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `S1RETENTION` writer - Keep retention on RAM section S1 of RAM n when RAM section is switched off"] +pub type S1RETENTION_W<'a, const O: u8> = + crate::BitWriter<'a, u32, POWERSET_SPEC, S1RETENTION_AW, O>; +impl<'a, const O: u8> S1RETENTION_W<'a, O> { + #[doc = "On"] + #[inline(always)] + pub fn on(self) -> &'a mut W { + self.variant(S1RETENTION_AW::ON) + } +} +#[doc = "Keep retention on RAM section S2 of RAM n when RAM section is switched off\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum S2RETENTION_AW { + #[doc = "1: On"] + ON = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: S2RETENTION_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `S2RETENTION` writer - Keep retention on RAM section S2 of RAM n when RAM section is switched off"] +pub type S2RETENTION_W<'a, const O: u8> = + crate::BitWriter<'a, u32, POWERSET_SPEC, S2RETENTION_AW, O>; +impl<'a, const O: u8> S2RETENTION_W<'a, O> { + #[doc = "On"] + #[inline(always)] + pub fn on(self) -> &'a mut W { + self.variant(S2RETENTION_AW::ON) + } +} +#[doc = "Keep retention on RAM section S3 of RAM n when RAM section is switched off\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum S3RETENTION_AW { + #[doc = "1: On"] + ON = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: S3RETENTION_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `S3RETENTION` writer - Keep retention on RAM section S3 of RAM n when RAM section is switched off"] +pub type S3RETENTION_W<'a, const O: u8> = + crate::BitWriter<'a, u32, POWERSET_SPEC, S3RETENTION_AW, O>; +impl<'a, const O: u8> S3RETENTION_W<'a, O> { + #[doc = "On"] + #[inline(always)] + pub fn on(self) -> &'a mut W { + self.variant(S3RETENTION_AW::ON) + } +} +impl W { + #[doc = "Bit 0 - Keep RAM section S0 of RAM n on or off in System ON mode"] + #[inline(always)] + pub fn s0power(&mut self) -> S0POWER_W<0> { + S0POWER_W::new(self) + } + #[doc = "Bit 1 - Keep RAM section S1 of RAM n on or off in System ON mode"] + #[inline(always)] + pub fn s1power(&mut self) -> S1POWER_W<1> { + S1POWER_W::new(self) + } + #[doc = "Bit 2 - Keep RAM section S2 of RAM n on or off in System ON mode"] + #[inline(always)] + pub fn s2power(&mut self) -> S2POWER_W<2> { + S2POWER_W::new(self) + } + #[doc = "Bit 3 - Keep RAM section S3 of RAM n on or off in System ON mode"] + #[inline(always)] + pub fn s3power(&mut self) -> S3POWER_W<3> { + S3POWER_W::new(self) + } + #[doc = "Bit 16 - Keep retention on RAM section S0 of RAM n when RAM section is switched off"] + #[inline(always)] + pub fn s0retention(&mut self) -> S0RETENTION_W<16> { + S0RETENTION_W::new(self) + } + #[doc = "Bit 17 - Keep retention on RAM section S1 of RAM n when RAM section is switched off"] + #[inline(always)] + pub fn s1retention(&mut self) -> S1RETENTION_W<17> { + S1RETENTION_W::new(self) + } + #[doc = "Bit 18 - Keep retention on RAM section S2 of RAM n when RAM section is switched off"] + #[inline(always)] + pub fn s2retention(&mut self) -> S2RETENTION_W<18> { + S2RETENTION_W::new(self) + } + #[doc = "Bit 19 - Keep retention on RAM section S3 of RAM n when RAM section is switched off"] + #[inline(always)] + pub fn s3retention(&mut self) -> S3RETENTION_W<19> { + S3RETENTION_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Description cluster: RAMn power control set register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [powerset](index.html) module"] +pub struct POWERSET_SPEC; +impl crate::RegisterSpec for POWERSET_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [powerset::W](W) writer structure"] +impl crate::Writable for POWERSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets POWERSET to value 0xffff"] +impl crate::Resettable for POWERSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0xffff + } +} diff --git a/pacs/nrf9120-pac/src/wdt_ns.rs b/pacs/nrf9120-pac/src/wdt_ns.rs new file mode 100644 index 00000000..dd6516f6 --- /dev/null +++ b/pacs/nrf9120-pac/src/wdt_ns.rs @@ -0,0 +1,83 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Start the watchdog"] + pub tasks_start: TASKS_START, + _reserved1: [u8; 0x7c], + #[doc = "0x80 - Subscribe configuration for task START"] + pub subscribe_start: SUBSCRIBE_START, + _reserved2: [u8; 0x7c], + #[doc = "0x100 - Watchdog timeout"] + pub events_timeout: EVENTS_TIMEOUT, + _reserved3: [u8; 0x7c], + #[doc = "0x180 - Publish configuration for event TIMEOUT"] + pub publish_timeout: PUBLISH_TIMEOUT, + _reserved4: [u8; 0x0180], + #[doc = "0x304 - Enable interrupt"] + pub intenset: INTENSET, + #[doc = "0x308 - Disable interrupt"] + pub intenclr: INTENCLR, + _reserved6: [u8; 0xf4], + #[doc = "0x400 - Run status"] + pub runstatus: RUNSTATUS, + #[doc = "0x404 - Request status"] + pub reqstatus: REQSTATUS, + _reserved8: [u8; 0xfc], + #[doc = "0x504 - Counter reload value"] + pub crv: CRV, + #[doc = "0x508 - Enable register for reload request registers"] + pub rren: RREN, + #[doc = "0x50c - Configuration register"] + pub config: CONFIG, + _reserved11: [u8; 0xf0], + #[doc = "0x600..0x620 - Description collection: Reload request n"] + pub rr: [RR; 8], +} +#[doc = "TASKS_START (w) register accessor: an alias for `Reg`"] +pub type TASKS_START = crate::Reg; +#[doc = "Start the watchdog"] +pub mod tasks_start; +#[doc = "SUBSCRIBE_START (rw) register accessor: an alias for `Reg`"] +pub type SUBSCRIBE_START = crate::Reg; +#[doc = "Subscribe configuration for task START"] +pub mod subscribe_start; +#[doc = "EVENTS_TIMEOUT (rw) register accessor: an alias for `Reg`"] +pub type EVENTS_TIMEOUT = crate::Reg; +#[doc = "Watchdog timeout"] +pub mod events_timeout; +#[doc = "PUBLISH_TIMEOUT (rw) register accessor: an alias for `Reg`"] +pub type PUBLISH_TIMEOUT = crate::Reg; +#[doc = "Publish configuration for event TIMEOUT"] +pub mod publish_timeout; +#[doc = "INTENSET (rw) register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "Enable interrupt"] +pub mod intenset; +#[doc = "INTENCLR (rw) register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "Disable interrupt"] +pub mod intenclr; +#[doc = "RUNSTATUS (r) register accessor: an alias for `Reg`"] +pub type RUNSTATUS = crate::Reg; +#[doc = "Run status"] +pub mod runstatus; +#[doc = "REQSTATUS (r) register accessor: an alias for `Reg`"] +pub type REQSTATUS = crate::Reg; +#[doc = "Request status"] +pub mod reqstatus; +#[doc = "CRV (rw) register accessor: an alias for `Reg`"] +pub type CRV = crate::Reg; +#[doc = "Counter reload value"] +pub mod crv; +#[doc = "RREN (rw) register accessor: an alias for `Reg`"] +pub type RREN = crate::Reg; +#[doc = "Enable register for reload request registers"] +pub mod rren; +#[doc = "CONFIG (rw) register accessor: an alias for `Reg`"] +pub type CONFIG = crate::Reg; +#[doc = "Configuration register"] +pub mod config; +#[doc = "RR (w) register accessor: an alias for `Reg`"] +pub type RR = crate::Reg; +#[doc = "Description collection: Reload request n"] +pub mod rr; diff --git a/pacs/nrf9120-pac/src/wdt_ns/config.rs b/pacs/nrf9120-pac/src/wdt_ns/config.rs new file mode 100644 index 00000000..8abc7445 --- /dev/null +++ b/pacs/nrf9120-pac/src/wdt_ns/config.rs @@ -0,0 +1,186 @@ +#[doc = "Register `CONFIG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CONFIG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SLEEP` reader - Configure the watchdog to either be paused, or kept running, while the CPU is sleeping"] +pub type SLEEP_R = crate::BitReader; +#[doc = "Configure the watchdog to either be paused, or kept running, while the CPU is sleeping\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum SLEEP_A { + #[doc = "0: Pause watchdog while the CPU is sleeping"] + PAUSE = 0, + #[doc = "1: Keep the watchdog running while the CPU is sleeping"] + RUN = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: SLEEP_A) -> Self { + variant as u8 != 0 + } +} +impl SLEEP_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> SLEEP_A { + match self.bits { + false => SLEEP_A::PAUSE, + true => SLEEP_A::RUN, + } + } + #[doc = "Checks if the value of the field is `PAUSE`"] + #[inline(always)] + pub fn is_pause(&self) -> bool { + *self == SLEEP_A::PAUSE + } + #[doc = "Checks if the value of the field is `RUN`"] + #[inline(always)] + pub fn is_run(&self) -> bool { + *self == SLEEP_A::RUN + } +} +#[doc = "Field `SLEEP` writer - Configure the watchdog to either be paused, or kept running, while the CPU is sleeping"] +pub type SLEEP_W<'a, const O: u8> = crate::BitWriter<'a, u32, CONFIG_SPEC, SLEEP_A, O>; +impl<'a, const O: u8> SLEEP_W<'a, O> { + #[doc = "Pause watchdog while the CPU is sleeping"] + #[inline(always)] + pub fn pause(self) -> &'a mut W { + self.variant(SLEEP_A::PAUSE) + } + #[doc = "Keep the watchdog running while the CPU is sleeping"] + #[inline(always)] + pub fn run(self) -> &'a mut W { + self.variant(SLEEP_A::RUN) + } +} +#[doc = "Field `HALT` reader - Configure the watchdog to either be paused, or kept running, while the CPU is halted by the debugger"] +pub type HALT_R = crate::BitReader; +#[doc = "Configure the watchdog to either be paused, or kept running, while the CPU is halted by the debugger\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum HALT_A { + #[doc = "0: Pause watchdog while the CPU is halted by the debugger"] + PAUSE = 0, + #[doc = "1: Keep the watchdog running while the CPU is halted by the debugger"] + RUN = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: HALT_A) -> Self { + variant as u8 != 0 + } +} +impl HALT_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> HALT_A { + match self.bits { + false => HALT_A::PAUSE, + true => HALT_A::RUN, + } + } + #[doc = "Checks if the value of the field is `PAUSE`"] + #[inline(always)] + pub fn is_pause(&self) -> bool { + *self == HALT_A::PAUSE + } + #[doc = "Checks if the value of the field is `RUN`"] + #[inline(always)] + pub fn is_run(&self) -> bool { + *self == HALT_A::RUN + } +} +#[doc = "Field `HALT` writer - Configure the watchdog to either be paused, or kept running, while the CPU is halted by the debugger"] +pub type HALT_W<'a, const O: u8> = crate::BitWriter<'a, u32, CONFIG_SPEC, HALT_A, O>; +impl<'a, const O: u8> HALT_W<'a, O> { + #[doc = "Pause watchdog while the CPU is halted by the debugger"] + #[inline(always)] + pub fn pause(self) -> &'a mut W { + self.variant(HALT_A::PAUSE) + } + #[doc = "Keep the watchdog running while the CPU is halted by the debugger"] + #[inline(always)] + pub fn run(self) -> &'a mut W { + self.variant(HALT_A::RUN) + } +} +impl R { + #[doc = "Bit 0 - Configure the watchdog to either be paused, or kept running, while the CPU is sleeping"] + #[inline(always)] + pub fn sleep(&self) -> SLEEP_R { + SLEEP_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 3 - Configure the watchdog to either be paused, or kept running, while the CPU is halted by the debugger"] + #[inline(always)] + pub fn halt(&self) -> HALT_R { + HALT_R::new(((self.bits >> 3) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Configure the watchdog to either be paused, or kept running, while the CPU is sleeping"] + #[inline(always)] + pub fn sleep(&mut self) -> SLEEP_W<0> { + SLEEP_W::new(self) + } + #[doc = "Bit 3 - Configure the watchdog to either be paused, or kept running, while the CPU is halted by the debugger"] + #[inline(always)] + pub fn halt(&mut self) -> HALT_W<3> { + HALT_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Configuration register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [config](index.html) module"] +pub struct CONFIG_SPEC; +impl crate::RegisterSpec for CONFIG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [config::R](R) reader structure"] +impl crate::Readable for CONFIG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [config::W](W) writer structure"] +impl crate::Writable for CONFIG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CONFIG to value 0x01"] +impl crate::Resettable for CONFIG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x01 + } +} diff --git a/pacs/nrf9120-pac/src/wdt_ns/crv.rs b/pacs/nrf9120-pac/src/wdt_ns/crv.rs new file mode 100644 index 00000000..55547e00 --- /dev/null +++ b/pacs/nrf9120-pac/src/wdt_ns/crv.rs @@ -0,0 +1,80 @@ +#[doc = "Register `CRV` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CRV` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CRV` reader - Counter reload value in number of cycles of the 32.768 kHz clock"] +pub type CRV_R = crate::FieldReader; +#[doc = "Field `CRV` writer - Counter reload value in number of cycles of the 32.768 kHz clock"] +pub type CRV_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CRV_SPEC, u32, u32, 32, O>; +impl R { + #[doc = "Bits 0:31 - Counter reload value in number of cycles of the 32.768 kHz clock"] + #[inline(always)] + pub fn crv(&self) -> CRV_R { + CRV_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Counter reload value in number of cycles of the 32.768 kHz clock"] + #[inline(always)] + pub fn crv(&mut self) -> CRV_W<0> { + CRV_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Counter reload value\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [crv](index.html) module"] +pub struct CRV_SPEC; +impl crate::RegisterSpec for CRV_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [crv::R](R) reader structure"] +impl crate::Readable for CRV_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [crv::W](W) writer structure"] +impl crate::Writable for CRV_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CRV to value 0xffff_ffff"] +impl crate::Resettable for CRV_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0xffff_ffff + } +} diff --git a/pacs/nrf9120-pac/src/wdt_ns/events_timeout.rs b/pacs/nrf9120-pac/src/wdt_ns/events_timeout.rs new file mode 100644 index 00000000..8f538325 --- /dev/null +++ b/pacs/nrf9120-pac/src/wdt_ns/events_timeout.rs @@ -0,0 +1,127 @@ +#[doc = "Register `EVENTS_TIMEOUT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVENTS_TIMEOUT` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `EVENTS_TIMEOUT` reader - Watchdog timeout"] +pub type EVENTS_TIMEOUT_R = crate::BitReader; +#[doc = "Watchdog timeout\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum EVENTS_TIMEOUT_A { + #[doc = "0: Event not generated"] + NOT_GENERATED = 0, + #[doc = "1: Event generated"] + GENERATED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: EVENTS_TIMEOUT_A) -> Self { + variant as u8 != 0 + } +} +impl EVENTS_TIMEOUT_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EVENTS_TIMEOUT_A { + match self.bits { + false => EVENTS_TIMEOUT_A::NOT_GENERATED, + true => EVENTS_TIMEOUT_A::GENERATED, + } + } + #[doc = "Checks if the value of the field is `NOT_GENERATED`"] + #[inline(always)] + pub fn is_not_generated(&self) -> bool { + *self == EVENTS_TIMEOUT_A::NOT_GENERATED + } + #[doc = "Checks if the value of the field is `GENERATED`"] + #[inline(always)] + pub fn is_generated(&self) -> bool { + *self == EVENTS_TIMEOUT_A::GENERATED + } +} +#[doc = "Field `EVENTS_TIMEOUT` writer - Watchdog timeout"] +pub type EVENTS_TIMEOUT_W<'a, const O: u8> = + crate::BitWriter<'a, u32, EVENTS_TIMEOUT_SPEC, EVENTS_TIMEOUT_A, O>; +impl<'a, const O: u8> EVENTS_TIMEOUT_W<'a, O> { + #[doc = "Event not generated"] + #[inline(always)] + pub fn not_generated(self) -> &'a mut W { + self.variant(EVENTS_TIMEOUT_A::NOT_GENERATED) + } + #[doc = "Event generated"] + #[inline(always)] + pub fn generated(self) -> &'a mut W { + self.variant(EVENTS_TIMEOUT_A::GENERATED) + } +} +impl R { + #[doc = "Bit 0 - Watchdog timeout"] + #[inline(always)] + pub fn events_timeout(&self) -> EVENTS_TIMEOUT_R { + EVENTS_TIMEOUT_R::new((self.bits & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Watchdog timeout"] + #[inline(always)] + pub fn events_timeout(&mut self) -> EVENTS_TIMEOUT_W<0> { + EVENTS_TIMEOUT_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Watchdog timeout\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [events_timeout](index.html) module"] +pub struct EVENTS_TIMEOUT_SPEC; +impl crate::RegisterSpec for EVENTS_TIMEOUT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [events_timeout::R](R) reader structure"] +impl crate::Readable for EVENTS_TIMEOUT_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [events_timeout::W](W) writer structure"] +impl crate::Writable for EVENTS_TIMEOUT_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EVENTS_TIMEOUT to value 0"] +impl crate::Resettable for EVENTS_TIMEOUT_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/wdt_ns/intenclr.rs b/pacs/nrf9120-pac/src/wdt_ns/intenclr.rs new file mode 100644 index 00000000..e9a37439 --- /dev/null +++ b/pacs/nrf9120-pac/src/wdt_ns/intenclr.rs @@ -0,0 +1,133 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `TIMEOUT` reader - Write '1' to disable interrupt for event TIMEOUT"] +pub type TIMEOUT_R = crate::BitReader; +#[doc = "Write '1' to disable interrupt for event TIMEOUT\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum TIMEOUT_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TIMEOUT_A) -> Self { + variant as u8 != 0 + } +} +impl TIMEOUT_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> TIMEOUT_A { + match self.bits { + false => TIMEOUT_A::DISABLED, + true => TIMEOUT_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == TIMEOUT_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == TIMEOUT_A::ENABLED + } +} +#[doc = "Write '1' to disable interrupt for event TIMEOUT\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum TIMEOUT_AW { + #[doc = "1: Disable"] + CLEAR = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TIMEOUT_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TIMEOUT` writer - Write '1' to disable interrupt for event TIMEOUT"] +pub type TIMEOUT_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENCLR_SPEC, TIMEOUT_AW, O>; +impl<'a, const O: u8> TIMEOUT_W<'a, O> { + #[doc = "Disable"] + #[inline(always)] + pub fn clear(self) -> &'a mut W { + self.variant(TIMEOUT_AW::CLEAR) + } +} +impl R { + #[doc = "Bit 0 - Write '1' to disable interrupt for event TIMEOUT"] + #[inline(always)] + pub fn timeout(&self) -> TIMEOUT_R { + TIMEOUT_R::new((self.bits & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Write '1' to disable interrupt for event TIMEOUT"] + #[inline(always)] + pub fn timeout(&mut self) -> TIMEOUT_W<0> { + TIMEOUT_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Disable interrupt\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/wdt_ns/intenset.rs b/pacs/nrf9120-pac/src/wdt_ns/intenset.rs new file mode 100644 index 00000000..119df977 --- /dev/null +++ b/pacs/nrf9120-pac/src/wdt_ns/intenset.rs @@ -0,0 +1,133 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `TIMEOUT` reader - Write '1' to enable interrupt for event TIMEOUT"] +pub type TIMEOUT_R = crate::BitReader; +#[doc = "Write '1' to enable interrupt for event TIMEOUT\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum TIMEOUT_A { + #[doc = "0: Read: Disabled"] + DISABLED = 0, + #[doc = "1: Read: Enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TIMEOUT_A) -> Self { + variant as u8 != 0 + } +} +impl TIMEOUT_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> TIMEOUT_A { + match self.bits { + false => TIMEOUT_A::DISABLED, + true => TIMEOUT_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == TIMEOUT_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == TIMEOUT_A::ENABLED + } +} +#[doc = "Write '1' to enable interrupt for event TIMEOUT\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum TIMEOUT_AW { + #[doc = "1: Enable"] + SET = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TIMEOUT_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TIMEOUT` writer - Write '1' to enable interrupt for event TIMEOUT"] +pub type TIMEOUT_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENSET_SPEC, TIMEOUT_AW, O>; +impl<'a, const O: u8> TIMEOUT_W<'a, O> { + #[doc = "Enable"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(TIMEOUT_AW::SET) + } +} +impl R { + #[doc = "Bit 0 - Write '1' to enable interrupt for event TIMEOUT"] + #[inline(always)] + pub fn timeout(&self) -> TIMEOUT_R { + TIMEOUT_R::new((self.bits & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Write '1' to enable interrupt for event TIMEOUT"] + #[inline(always)] + pub fn timeout(&mut self) -> TIMEOUT_W<0> { + TIMEOUT_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Enable interrupt\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/wdt_ns/publish_timeout.rs b/pacs/nrf9120-pac/src/wdt_ns/publish_timeout.rs new file mode 100644 index 00000000..944d0ea6 --- /dev/null +++ b/pacs/nrf9120-pac/src/wdt_ns/publish_timeout.rs @@ -0,0 +1,140 @@ +#[doc = "Register `PUBLISH_TIMEOUT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PUBLISH_TIMEOUT` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CHIDX` reader - DPPI channel that event TIMEOUT will publish to"] +pub type CHIDX_R = crate::FieldReader; +#[doc = "Field `CHIDX` writer - DPPI channel that event TIMEOUT will publish to"] +pub type CHIDX_W<'a, const O: u8> = crate::FieldWriter<'a, u32, PUBLISH_TIMEOUT_SPEC, u8, u8, 8, O>; +#[doc = "Field `EN` reader - "] +pub type EN_R = crate::BitReader; +#[doc = "\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum EN_A { + #[doc = "0: Disable publishing"] + DISABLED = 0, + #[doc = "1: Enable publishing"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: EN_A) -> Self { + variant as u8 != 0 + } +} +impl EN_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EN_A { + match self.bits { + false => EN_A::DISABLED, + true => EN_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == EN_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == EN_A::ENABLED + } +} +#[doc = "Field `EN` writer - "] +pub type EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, PUBLISH_TIMEOUT_SPEC, EN_A, O>; +impl<'a, const O: u8> EN_W<'a, O> { + #[doc = "Disable publishing"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(EN_A::DISABLED) + } + #[doc = "Enable publishing"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(EN_A::ENABLED) + } +} +impl R { + #[doc = "Bits 0:7 - DPPI channel that event TIMEOUT will publish to"] + #[inline(always)] + pub fn chidx(&self) -> CHIDX_R { + CHIDX_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&self) -> EN_R { + EN_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:7 - DPPI channel that event TIMEOUT will publish to"] + #[inline(always)] + pub fn chidx(&mut self) -> CHIDX_W<0> { + CHIDX_W::new(self) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&mut self) -> EN_W<31> { + EN_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Publish configuration for event TIMEOUT\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [publish_timeout](index.html) module"] +pub struct PUBLISH_TIMEOUT_SPEC; +impl crate::RegisterSpec for PUBLISH_TIMEOUT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [publish_timeout::R](R) reader structure"] +impl crate::Readable for PUBLISH_TIMEOUT_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [publish_timeout::W](W) writer structure"] +impl crate::Writable for PUBLISH_TIMEOUT_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PUBLISH_TIMEOUT to value 0"] +impl crate::Resettable for PUBLISH_TIMEOUT_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/wdt_ns/reqstatus.rs b/pacs/nrf9120-pac/src/wdt_ns/reqstatus.rs new file mode 100644 index 00000000..09bf37a4 --- /dev/null +++ b/pacs/nrf9120-pac/src/wdt_ns/reqstatus.rs @@ -0,0 +1,401 @@ +#[doc = "Register `REQSTATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `RR0` reader - Request status for RR\\[0\\] +register"] +pub type RR0_R = crate::BitReader; +#[doc = "Request status for RR\\[0\\] +register\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RR0_A { + #[doc = "0: RR\\[0\\] +register is not enabled, or are already requesting reload"] + DISABLED_OR_REQUESTED = 0, + #[doc = "1: RR\\[0\\] +register is enabled, and are not yet requesting reload"] + ENABLED_AND_UNREQUESTED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RR0_A) -> Self { + variant as u8 != 0 + } +} +impl RR0_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RR0_A { + match self.bits { + false => RR0_A::DISABLED_OR_REQUESTED, + true => RR0_A::ENABLED_AND_UNREQUESTED, + } + } + #[doc = "Checks if the value of the field is `DISABLED_OR_REQUESTED`"] + #[inline(always)] + pub fn is_disabled_or_requested(&self) -> bool { + *self == RR0_A::DISABLED_OR_REQUESTED + } + #[doc = "Checks if the value of the field is `ENABLED_AND_UNREQUESTED`"] + #[inline(always)] + pub fn is_enabled_and_unrequested(&self) -> bool { + *self == RR0_A::ENABLED_AND_UNREQUESTED + } +} +#[doc = "Field `RR1` reader - Request status for RR\\[1\\] +register"] +pub type RR1_R = crate::BitReader; +#[doc = "Request status for RR\\[1\\] +register\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RR1_A { + #[doc = "0: RR\\[1\\] +register is not enabled, or are already requesting reload"] + DISABLED_OR_REQUESTED = 0, + #[doc = "1: RR\\[1\\] +register is enabled, and are not yet requesting reload"] + ENABLED_AND_UNREQUESTED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RR1_A) -> Self { + variant as u8 != 0 + } +} +impl RR1_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RR1_A { + match self.bits { + false => RR1_A::DISABLED_OR_REQUESTED, + true => RR1_A::ENABLED_AND_UNREQUESTED, + } + } + #[doc = "Checks if the value of the field is `DISABLED_OR_REQUESTED`"] + #[inline(always)] + pub fn is_disabled_or_requested(&self) -> bool { + *self == RR1_A::DISABLED_OR_REQUESTED + } + #[doc = "Checks if the value of the field is `ENABLED_AND_UNREQUESTED`"] + #[inline(always)] + pub fn is_enabled_and_unrequested(&self) -> bool { + *self == RR1_A::ENABLED_AND_UNREQUESTED + } +} +#[doc = "Field `RR2` reader - Request status for RR\\[2\\] +register"] +pub type RR2_R = crate::BitReader; +#[doc = "Request status for RR\\[2\\] +register\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RR2_A { + #[doc = "0: RR\\[2\\] +register is not enabled, or are already requesting reload"] + DISABLED_OR_REQUESTED = 0, + #[doc = "1: RR\\[2\\] +register is enabled, and are not yet requesting reload"] + ENABLED_AND_UNREQUESTED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RR2_A) -> Self { + variant as u8 != 0 + } +} +impl RR2_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RR2_A { + match self.bits { + false => RR2_A::DISABLED_OR_REQUESTED, + true => RR2_A::ENABLED_AND_UNREQUESTED, + } + } + #[doc = "Checks if the value of the field is `DISABLED_OR_REQUESTED`"] + #[inline(always)] + pub fn is_disabled_or_requested(&self) -> bool { + *self == RR2_A::DISABLED_OR_REQUESTED + } + #[doc = "Checks if the value of the field is `ENABLED_AND_UNREQUESTED`"] + #[inline(always)] + pub fn is_enabled_and_unrequested(&self) -> bool { + *self == RR2_A::ENABLED_AND_UNREQUESTED + } +} +#[doc = "Field `RR3` reader - Request status for RR\\[3\\] +register"] +pub type RR3_R = crate::BitReader; +#[doc = "Request status for RR\\[3\\] +register\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RR3_A { + #[doc = "0: RR\\[3\\] +register is not enabled, or are already requesting reload"] + DISABLED_OR_REQUESTED = 0, + #[doc = "1: RR\\[3\\] +register is enabled, and are not yet requesting reload"] + ENABLED_AND_UNREQUESTED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RR3_A) -> Self { + variant as u8 != 0 + } +} +impl RR3_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RR3_A { + match self.bits { + false => RR3_A::DISABLED_OR_REQUESTED, + true => RR3_A::ENABLED_AND_UNREQUESTED, + } + } + #[doc = "Checks if the value of the field is `DISABLED_OR_REQUESTED`"] + #[inline(always)] + pub fn is_disabled_or_requested(&self) -> bool { + *self == RR3_A::DISABLED_OR_REQUESTED + } + #[doc = "Checks if the value of the field is `ENABLED_AND_UNREQUESTED`"] + #[inline(always)] + pub fn is_enabled_and_unrequested(&self) -> bool { + *self == RR3_A::ENABLED_AND_UNREQUESTED + } +} +#[doc = "Field `RR4` reader - Request status for RR\\[4\\] +register"] +pub type RR4_R = crate::BitReader; +#[doc = "Request status for RR\\[4\\] +register\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RR4_A { + #[doc = "0: RR\\[4\\] +register is not enabled, or are already requesting reload"] + DISABLED_OR_REQUESTED = 0, + #[doc = "1: RR\\[4\\] +register is enabled, and are not yet requesting reload"] + ENABLED_AND_UNREQUESTED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RR4_A) -> Self { + variant as u8 != 0 + } +} +impl RR4_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RR4_A { + match self.bits { + false => RR4_A::DISABLED_OR_REQUESTED, + true => RR4_A::ENABLED_AND_UNREQUESTED, + } + } + #[doc = "Checks if the value of the field is `DISABLED_OR_REQUESTED`"] + #[inline(always)] + pub fn is_disabled_or_requested(&self) -> bool { + *self == RR4_A::DISABLED_OR_REQUESTED + } + #[doc = "Checks if the value of the field is `ENABLED_AND_UNREQUESTED`"] + #[inline(always)] + pub fn is_enabled_and_unrequested(&self) -> bool { + *self == RR4_A::ENABLED_AND_UNREQUESTED + } +} +#[doc = "Field `RR5` reader - Request status for RR\\[5\\] +register"] +pub type RR5_R = crate::BitReader; +#[doc = "Request status for RR\\[5\\] +register\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RR5_A { + #[doc = "0: RR\\[5\\] +register is not enabled, or are already requesting reload"] + DISABLED_OR_REQUESTED = 0, + #[doc = "1: RR\\[5\\] +register is enabled, and are not yet requesting reload"] + ENABLED_AND_UNREQUESTED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RR5_A) -> Self { + variant as u8 != 0 + } +} +impl RR5_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RR5_A { + match self.bits { + false => RR5_A::DISABLED_OR_REQUESTED, + true => RR5_A::ENABLED_AND_UNREQUESTED, + } + } + #[doc = "Checks if the value of the field is `DISABLED_OR_REQUESTED`"] + #[inline(always)] + pub fn is_disabled_or_requested(&self) -> bool { + *self == RR5_A::DISABLED_OR_REQUESTED + } + #[doc = "Checks if the value of the field is `ENABLED_AND_UNREQUESTED`"] + #[inline(always)] + pub fn is_enabled_and_unrequested(&self) -> bool { + *self == RR5_A::ENABLED_AND_UNREQUESTED + } +} +#[doc = "Field `RR6` reader - Request status for RR\\[6\\] +register"] +pub type RR6_R = crate::BitReader; +#[doc = "Request status for RR\\[6\\] +register\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RR6_A { + #[doc = "0: RR\\[6\\] +register is not enabled, or are already requesting reload"] + DISABLED_OR_REQUESTED = 0, + #[doc = "1: RR\\[6\\] +register is enabled, and are not yet requesting reload"] + ENABLED_AND_UNREQUESTED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RR6_A) -> Self { + variant as u8 != 0 + } +} +impl RR6_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RR6_A { + match self.bits { + false => RR6_A::DISABLED_OR_REQUESTED, + true => RR6_A::ENABLED_AND_UNREQUESTED, + } + } + #[doc = "Checks if the value of the field is `DISABLED_OR_REQUESTED`"] + #[inline(always)] + pub fn is_disabled_or_requested(&self) -> bool { + *self == RR6_A::DISABLED_OR_REQUESTED + } + #[doc = "Checks if the value of the field is `ENABLED_AND_UNREQUESTED`"] + #[inline(always)] + pub fn is_enabled_and_unrequested(&self) -> bool { + *self == RR6_A::ENABLED_AND_UNREQUESTED + } +} +#[doc = "Field `RR7` reader - Request status for RR\\[7\\] +register"] +pub type RR7_R = crate::BitReader; +#[doc = "Request status for RR\\[7\\] +register\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RR7_A { + #[doc = "0: RR\\[7\\] +register is not enabled, or are already requesting reload"] + DISABLED_OR_REQUESTED = 0, + #[doc = "1: RR\\[7\\] +register is enabled, and are not yet requesting reload"] + ENABLED_AND_UNREQUESTED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RR7_A) -> Self { + variant as u8 != 0 + } +} +impl RR7_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RR7_A { + match self.bits { + false => RR7_A::DISABLED_OR_REQUESTED, + true => RR7_A::ENABLED_AND_UNREQUESTED, + } + } + #[doc = "Checks if the value of the field is `DISABLED_OR_REQUESTED`"] + #[inline(always)] + pub fn is_disabled_or_requested(&self) -> bool { + *self == RR7_A::DISABLED_OR_REQUESTED + } + #[doc = "Checks if the value of the field is `ENABLED_AND_UNREQUESTED`"] + #[inline(always)] + pub fn is_enabled_and_unrequested(&self) -> bool { + *self == RR7_A::ENABLED_AND_UNREQUESTED + } +} +impl R { + #[doc = "Bit 0 - Request status for RR\\[0\\] +register"] + #[inline(always)] + pub fn rr0(&self) -> RR0_R { + RR0_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Request status for RR\\[1\\] +register"] + #[inline(always)] + pub fn rr1(&self) -> RR1_R { + RR1_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Request status for RR\\[2\\] +register"] + #[inline(always)] + pub fn rr2(&self) -> RR2_R { + RR2_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Request status for RR\\[3\\] +register"] + #[inline(always)] + pub fn rr3(&self) -> RR3_R { + RR3_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Request status for RR\\[4\\] +register"] + #[inline(always)] + pub fn rr4(&self) -> RR4_R { + RR4_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Request status for RR\\[5\\] +register"] + #[inline(always)] + pub fn rr5(&self) -> RR5_R { + RR5_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Request status for RR\\[6\\] +register"] + #[inline(always)] + pub fn rr6(&self) -> RR6_R { + RR6_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Request status for RR\\[7\\] +register"] + #[inline(always)] + pub fn rr7(&self) -> RR7_R { + RR7_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[doc = "Request status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [reqstatus](index.html) module"] +pub struct REQSTATUS_SPEC; +impl crate::RegisterSpec for REQSTATUS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [reqstatus::R](R) reader structure"] +impl crate::Readable for REQSTATUS_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets REQSTATUS to value 0x01"] +impl crate::Resettable for REQSTATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x01 + } +} diff --git a/pacs/nrf9120-pac/src/wdt_ns/rr.rs b/pacs/nrf9120-pac/src/wdt_ns/rr.rs new file mode 100644 index 00000000..4da07007 --- /dev/null +++ b/pacs/nrf9120-pac/src/wdt_ns/rr.rs @@ -0,0 +1,73 @@ +#[doc = "Register `RR[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Reload request register\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u32)] +pub enum RR_AW { + #[doc = "1850885685: Value to request a reload of the watchdog timer"] + RELOAD = 1850885685, +} +impl From for u32 { + #[inline(always)] + fn from(variant: RR_AW) -> Self { + variant as _ + } +} +#[doc = "Field `RR` writer - Reload request register"] +pub type RR_W<'a, const O: u8> = crate::FieldWriter<'a, u32, RR_SPEC, u32, RR_AW, 32, O>; +impl<'a, const O: u8> RR_W<'a, O> { + #[doc = "Value to request a reload of the watchdog timer"] + #[inline(always)] + pub fn reload(self) -> &'a mut W { + self.variant(RR_AW::RELOAD) + } +} +impl W { + #[doc = "Bits 0:31 - Reload request register"] + #[inline(always)] + pub fn rr(&mut self) -> RR_W<0> { + RR_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Description collection: Reload request n\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rr](index.html) module"] +pub struct RR_SPEC; +impl crate::RegisterSpec for RR_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [rr::W](W) writer structure"] +impl crate::Writable for RR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets RR[%s] +to value 0"] +impl crate::Resettable for RR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/wdt_ns/rren.rs b/pacs/nrf9120-pac/src/wdt_ns/rren.rs new file mode 100644 index 00000000..6670939a --- /dev/null +++ b/pacs/nrf9120-pac/src/wdt_ns/rren.rs @@ -0,0 +1,618 @@ +#[doc = "Register `RREN` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `RREN` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `RR0` reader - Enable or disable RR\\[0\\] +register"] +pub type RR0_R = crate::BitReader; +#[doc = "Enable or disable RR\\[0\\] +register\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RR0_A { + #[doc = "0: Disable RR\\[0\\] +register"] + DISABLED = 0, + #[doc = "1: Enable RR\\[0\\] +register"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RR0_A) -> Self { + variant as u8 != 0 + } +} +impl RR0_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RR0_A { + match self.bits { + false => RR0_A::DISABLED, + true => RR0_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == RR0_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == RR0_A::ENABLED + } +} +#[doc = "Field `RR0` writer - Enable or disable RR\\[0\\] +register"] +pub type RR0_W<'a, const O: u8> = crate::BitWriter<'a, u32, RREN_SPEC, RR0_A, O>; +impl<'a, const O: u8> RR0_W<'a, O> { + #[doc = "Disable RR\\[0\\] +register"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(RR0_A::DISABLED) + } + #[doc = "Enable RR\\[0\\] +register"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(RR0_A::ENABLED) + } +} +#[doc = "Field `RR1` reader - Enable or disable RR\\[1\\] +register"] +pub type RR1_R = crate::BitReader; +#[doc = "Enable or disable RR\\[1\\] +register\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RR1_A { + #[doc = "0: Disable RR\\[1\\] +register"] + DISABLED = 0, + #[doc = "1: Enable RR\\[1\\] +register"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RR1_A) -> Self { + variant as u8 != 0 + } +} +impl RR1_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RR1_A { + match self.bits { + false => RR1_A::DISABLED, + true => RR1_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == RR1_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == RR1_A::ENABLED + } +} +#[doc = "Field `RR1` writer - Enable or disable RR\\[1\\] +register"] +pub type RR1_W<'a, const O: u8> = crate::BitWriter<'a, u32, RREN_SPEC, RR1_A, O>; +impl<'a, const O: u8> RR1_W<'a, O> { + #[doc = "Disable RR\\[1\\] +register"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(RR1_A::DISABLED) + } + #[doc = "Enable RR\\[1\\] +register"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(RR1_A::ENABLED) + } +} +#[doc = "Field `RR2` reader - Enable or disable RR\\[2\\] +register"] +pub type RR2_R = crate::BitReader; +#[doc = "Enable or disable RR\\[2\\] +register\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RR2_A { + #[doc = "0: Disable RR\\[2\\] +register"] + DISABLED = 0, + #[doc = "1: Enable RR\\[2\\] +register"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RR2_A) -> Self { + variant as u8 != 0 + } +} +impl RR2_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RR2_A { + match self.bits { + false => RR2_A::DISABLED, + true => RR2_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == RR2_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == RR2_A::ENABLED + } +} +#[doc = "Field `RR2` writer - Enable or disable RR\\[2\\] +register"] +pub type RR2_W<'a, const O: u8> = crate::BitWriter<'a, u32, RREN_SPEC, RR2_A, O>; +impl<'a, const O: u8> RR2_W<'a, O> { + #[doc = "Disable RR\\[2\\] +register"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(RR2_A::DISABLED) + } + #[doc = "Enable RR\\[2\\] +register"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(RR2_A::ENABLED) + } +} +#[doc = "Field `RR3` reader - Enable or disable RR\\[3\\] +register"] +pub type RR3_R = crate::BitReader; +#[doc = "Enable or disable RR\\[3\\] +register\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RR3_A { + #[doc = "0: Disable RR\\[3\\] +register"] + DISABLED = 0, + #[doc = "1: Enable RR\\[3\\] +register"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RR3_A) -> Self { + variant as u8 != 0 + } +} +impl RR3_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RR3_A { + match self.bits { + false => RR3_A::DISABLED, + true => RR3_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == RR3_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == RR3_A::ENABLED + } +} +#[doc = "Field `RR3` writer - Enable or disable RR\\[3\\] +register"] +pub type RR3_W<'a, const O: u8> = crate::BitWriter<'a, u32, RREN_SPEC, RR3_A, O>; +impl<'a, const O: u8> RR3_W<'a, O> { + #[doc = "Disable RR\\[3\\] +register"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(RR3_A::DISABLED) + } + #[doc = "Enable RR\\[3\\] +register"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(RR3_A::ENABLED) + } +} +#[doc = "Field `RR4` reader - Enable or disable RR\\[4\\] +register"] +pub type RR4_R = crate::BitReader; +#[doc = "Enable or disable RR\\[4\\] +register\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RR4_A { + #[doc = "0: Disable RR\\[4\\] +register"] + DISABLED = 0, + #[doc = "1: Enable RR\\[4\\] +register"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RR4_A) -> Self { + variant as u8 != 0 + } +} +impl RR4_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RR4_A { + match self.bits { + false => RR4_A::DISABLED, + true => RR4_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == RR4_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == RR4_A::ENABLED + } +} +#[doc = "Field `RR4` writer - Enable or disable RR\\[4\\] +register"] +pub type RR4_W<'a, const O: u8> = crate::BitWriter<'a, u32, RREN_SPEC, RR4_A, O>; +impl<'a, const O: u8> RR4_W<'a, O> { + #[doc = "Disable RR\\[4\\] +register"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(RR4_A::DISABLED) + } + #[doc = "Enable RR\\[4\\] +register"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(RR4_A::ENABLED) + } +} +#[doc = "Field `RR5` reader - Enable or disable RR\\[5\\] +register"] +pub type RR5_R = crate::BitReader; +#[doc = "Enable or disable RR\\[5\\] +register\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RR5_A { + #[doc = "0: Disable RR\\[5\\] +register"] + DISABLED = 0, + #[doc = "1: Enable RR\\[5\\] +register"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RR5_A) -> Self { + variant as u8 != 0 + } +} +impl RR5_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RR5_A { + match self.bits { + false => RR5_A::DISABLED, + true => RR5_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == RR5_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == RR5_A::ENABLED + } +} +#[doc = "Field `RR5` writer - Enable or disable RR\\[5\\] +register"] +pub type RR5_W<'a, const O: u8> = crate::BitWriter<'a, u32, RREN_SPEC, RR5_A, O>; +impl<'a, const O: u8> RR5_W<'a, O> { + #[doc = "Disable RR\\[5\\] +register"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(RR5_A::DISABLED) + } + #[doc = "Enable RR\\[5\\] +register"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(RR5_A::ENABLED) + } +} +#[doc = "Field `RR6` reader - Enable or disable RR\\[6\\] +register"] +pub type RR6_R = crate::BitReader; +#[doc = "Enable or disable RR\\[6\\] +register\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RR6_A { + #[doc = "0: Disable RR\\[6\\] +register"] + DISABLED = 0, + #[doc = "1: Enable RR\\[6\\] +register"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RR6_A) -> Self { + variant as u8 != 0 + } +} +impl RR6_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RR6_A { + match self.bits { + false => RR6_A::DISABLED, + true => RR6_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == RR6_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == RR6_A::ENABLED + } +} +#[doc = "Field `RR6` writer - Enable or disable RR\\[6\\] +register"] +pub type RR6_W<'a, const O: u8> = crate::BitWriter<'a, u32, RREN_SPEC, RR6_A, O>; +impl<'a, const O: u8> RR6_W<'a, O> { + #[doc = "Disable RR\\[6\\] +register"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(RR6_A::DISABLED) + } + #[doc = "Enable RR\\[6\\] +register"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(RR6_A::ENABLED) + } +} +#[doc = "Field `RR7` reader - Enable or disable RR\\[7\\] +register"] +pub type RR7_R = crate::BitReader; +#[doc = "Enable or disable RR\\[7\\] +register\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RR7_A { + #[doc = "0: Disable RR\\[7\\] +register"] + DISABLED = 0, + #[doc = "1: Enable RR\\[7\\] +register"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RR7_A) -> Self { + variant as u8 != 0 + } +} +impl RR7_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RR7_A { + match self.bits { + false => RR7_A::DISABLED, + true => RR7_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == RR7_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == RR7_A::ENABLED + } +} +#[doc = "Field `RR7` writer - Enable or disable RR\\[7\\] +register"] +pub type RR7_W<'a, const O: u8> = crate::BitWriter<'a, u32, RREN_SPEC, RR7_A, O>; +impl<'a, const O: u8> RR7_W<'a, O> { + #[doc = "Disable RR\\[7\\] +register"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(RR7_A::DISABLED) + } + #[doc = "Enable RR\\[7\\] +register"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(RR7_A::ENABLED) + } +} +impl R { + #[doc = "Bit 0 - Enable or disable RR\\[0\\] +register"] + #[inline(always)] + pub fn rr0(&self) -> RR0_R { + RR0_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Enable or disable RR\\[1\\] +register"] + #[inline(always)] + pub fn rr1(&self) -> RR1_R { + RR1_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Enable or disable RR\\[2\\] +register"] + #[inline(always)] + pub fn rr2(&self) -> RR2_R { + RR2_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Enable or disable RR\\[3\\] +register"] + #[inline(always)] + pub fn rr3(&self) -> RR3_R { + RR3_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Enable or disable RR\\[4\\] +register"] + #[inline(always)] + pub fn rr4(&self) -> RR4_R { + RR4_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Enable or disable RR\\[5\\] +register"] + #[inline(always)] + pub fn rr5(&self) -> RR5_R { + RR5_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Enable or disable RR\\[6\\] +register"] + #[inline(always)] + pub fn rr6(&self) -> RR6_R { + RR6_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Enable or disable RR\\[7\\] +register"] + #[inline(always)] + pub fn rr7(&self) -> RR7_R { + RR7_R::new(((self.bits >> 7) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Enable or disable RR\\[0\\] +register"] + #[inline(always)] + pub fn rr0(&mut self) -> RR0_W<0> { + RR0_W::new(self) + } + #[doc = "Bit 1 - Enable or disable RR\\[1\\] +register"] + #[inline(always)] + pub fn rr1(&mut self) -> RR1_W<1> { + RR1_W::new(self) + } + #[doc = "Bit 2 - Enable or disable RR\\[2\\] +register"] + #[inline(always)] + pub fn rr2(&mut self) -> RR2_W<2> { + RR2_W::new(self) + } + #[doc = "Bit 3 - Enable or disable RR\\[3\\] +register"] + #[inline(always)] + pub fn rr3(&mut self) -> RR3_W<3> { + RR3_W::new(self) + } + #[doc = "Bit 4 - Enable or disable RR\\[4\\] +register"] + #[inline(always)] + pub fn rr4(&mut self) -> RR4_W<4> { + RR4_W::new(self) + } + #[doc = "Bit 5 - Enable or disable RR\\[5\\] +register"] + #[inline(always)] + pub fn rr5(&mut self) -> RR5_W<5> { + RR5_W::new(self) + } + #[doc = "Bit 6 - Enable or disable RR\\[6\\] +register"] + #[inline(always)] + pub fn rr6(&mut self) -> RR6_W<6> { + RR6_W::new(self) + } + #[doc = "Bit 7 - Enable or disable RR\\[7\\] +register"] + #[inline(always)] + pub fn rr7(&mut self) -> RR7_W<7> { + RR7_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Enable register for reload request registers\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rren](index.html) module"] +pub struct RREN_SPEC; +impl crate::RegisterSpec for RREN_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [rren::R](R) reader structure"] +impl crate::Readable for RREN_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [rren::W](W) writer structure"] +impl crate::Writable for RREN_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets RREN to value 0x01"] +impl crate::Resettable for RREN_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x01 + } +} diff --git a/pacs/nrf9120-pac/src/wdt_ns/runstatus.rs b/pacs/nrf9120-pac/src/wdt_ns/runstatus.rs new file mode 100644 index 00000000..9cea4271 --- /dev/null +++ b/pacs/nrf9120-pac/src/wdt_ns/runstatus.rs @@ -0,0 +1,74 @@ +#[doc = "Register `RUNSTATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `RUNSTATUSWDT` reader - Indicates whether or not the watchdog is running"] +pub type RUNSTATUSWDT_R = crate::BitReader; +#[doc = "Indicates whether or not the watchdog is running\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RUNSTATUSWDT_A { + #[doc = "0: Watchdog not running"] + NOT_RUNNING = 0, + #[doc = "1: Watchdog is running"] + RUNNING = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RUNSTATUSWDT_A) -> Self { + variant as u8 != 0 + } +} +impl RUNSTATUSWDT_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RUNSTATUSWDT_A { + match self.bits { + false => RUNSTATUSWDT_A::NOT_RUNNING, + true => RUNSTATUSWDT_A::RUNNING, + } + } + #[doc = "Checks if the value of the field is `NOT_RUNNING`"] + #[inline(always)] + pub fn is_not_running(&self) -> bool { + *self == RUNSTATUSWDT_A::NOT_RUNNING + } + #[doc = "Checks if the value of the field is `RUNNING`"] + #[inline(always)] + pub fn is_running(&self) -> bool { + *self == RUNSTATUSWDT_A::RUNNING + } +} +impl R { + #[doc = "Bit 0 - Indicates whether or not the watchdog is running"] + #[inline(always)] + pub fn runstatuswdt(&self) -> RUNSTATUSWDT_R { + RUNSTATUSWDT_R::new((self.bits & 1) != 0) + } +} +#[doc = "Run status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [runstatus](index.html) module"] +pub struct RUNSTATUS_SPEC; +impl crate::RegisterSpec for RUNSTATUS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [runstatus::R](R) reader structure"] +impl crate::Readable for RUNSTATUS_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets RUNSTATUS to value 0"] +impl crate::Resettable for RUNSTATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/wdt_ns/subscribe_start.rs b/pacs/nrf9120-pac/src/wdt_ns/subscribe_start.rs new file mode 100644 index 00000000..fb9deced --- /dev/null +++ b/pacs/nrf9120-pac/src/wdt_ns/subscribe_start.rs @@ -0,0 +1,140 @@ +#[doc = "Register `SUBSCRIBE_START` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SUBSCRIBE_START` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CHIDX` reader - DPPI channel that task START will subscribe to"] +pub type CHIDX_R = crate::FieldReader; +#[doc = "Field `CHIDX` writer - DPPI channel that task START will subscribe to"] +pub type CHIDX_W<'a, const O: u8> = crate::FieldWriter<'a, u32, SUBSCRIBE_START_SPEC, u8, u8, 8, O>; +#[doc = "Field `EN` reader - "] +pub type EN_R = crate::BitReader; +#[doc = "\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum EN_A { + #[doc = "0: Disable subscription"] + DISABLED = 0, + #[doc = "1: Enable subscription"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: EN_A) -> Self { + variant as u8 != 0 + } +} +impl EN_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EN_A { + match self.bits { + false => EN_A::DISABLED, + true => EN_A::ENABLED, + } + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == EN_A::DISABLED + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == EN_A::ENABLED + } +} +#[doc = "Field `EN` writer - "] +pub type EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, SUBSCRIBE_START_SPEC, EN_A, O>; +impl<'a, const O: u8> EN_W<'a, O> { + #[doc = "Disable subscription"] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(EN_A::DISABLED) + } + #[doc = "Enable subscription"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(EN_A::ENABLED) + } +} +impl R { + #[doc = "Bits 0:7 - DPPI channel that task START will subscribe to"] + #[inline(always)] + pub fn chidx(&self) -> CHIDX_R { + CHIDX_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&self) -> EN_R { + EN_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:7 - DPPI channel that task START will subscribe to"] + #[inline(always)] + pub fn chidx(&mut self) -> CHIDX_W<0> { + CHIDX_W::new(self) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn en(&mut self) -> EN_W<31> { + EN_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Subscribe configuration for task START\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [subscribe_start](index.html) module"] +pub struct SUBSCRIBE_START_SPEC; +impl crate::RegisterSpec for SUBSCRIBE_START_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [subscribe_start::R](R) reader structure"] +impl crate::Readable for SUBSCRIBE_START_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [subscribe_start::W](W) writer structure"] +impl crate::Writable for SUBSCRIBE_START_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SUBSCRIBE_START to value 0"] +impl crate::Resettable for SUBSCRIBE_START_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9120-pac/src/wdt_ns/tasks_start.rs b/pacs/nrf9120-pac/src/wdt_ns/tasks_start.rs new file mode 100644 index 00000000..75197f3b --- /dev/null +++ b/pacs/nrf9120-pac/src/wdt_ns/tasks_start.rs @@ -0,0 +1,72 @@ +#[doc = "Register `TASKS_START` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Start the watchdog\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum TASKS_START_AW { + #[doc = "1: Trigger task"] + TRIGGER = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TASKS_START_AW) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TASKS_START` writer - Start the watchdog"] +pub type TASKS_START_W<'a, const O: u8> = + crate::BitWriter<'a, u32, TASKS_START_SPEC, TASKS_START_AW, O>; +impl<'a, const O: u8> TASKS_START_W<'a, O> { + #[doc = "Trigger task"] + #[inline(always)] + pub fn trigger(self) -> &'a mut W { + self.variant(TASKS_START_AW::TRIGGER) + } +} +impl W { + #[doc = "Bit 0 - Start the watchdog"] + #[inline(always)] + pub fn tasks_start(&mut self) -> TASKS_START_W<0> { + TASKS_START_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Start the watchdog\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tasks_start](index.html) module"] +pub struct TASKS_START_SPEC; +impl crate::RegisterSpec for TASKS_START_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [tasks_start::W](W) writer structure"] +impl crate::Writable for TASKS_START_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets TASKS_START to value 0"] +impl crate::Resettable for TASKS_START_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pacs/nrf9160-pac/src/lib.rs b/pacs/nrf9160-pac/src/lib.rs index 47f3742d..758f034d 100644 --- a/pacs/nrf9160-pac/src/lib.rs +++ b/pacs/nrf9160-pac/src/lib.rs @@ -1,6 +1,5 @@ #![doc = "Peripheral access API for NRF9160 microcontrollers (generated using svd2rust v0.25.1 ( ))\n\nYou can find an overview of the generated API [here].\n\nAPI features to be included in the [next] svd2rust release can be generated by cloning the svd2rust [repository], checking out the above commit, and running `cargo doc --open`.\n\n[here]: https://docs.rs/svd2rust/0.25.1/svd2rust/#peripheral-api\n[next]: https://github.com/rust-embedded/svd2rust/blob/master/CHANGELOG.md#unreleased\n[repository]: https://github.com/rust-embedded/svd2rust"] -#![deny(const_err)] #![deny(dead_code)] #![deny(improper_ctypes)] #![deny(missing_docs)] @@ -9,7 +8,6 @@ svd2rust release can be generated by cloning the svd2rust [repository], checking #![deny(overflowing_literals)] #![deny(path_statements)] #![deny(patterns_in_fns_without_body)] -#![deny(private_in_public)] #![deny(unconditional_recursion)] #![deny(unused_allocation)] #![deny(unused_comparisons)] diff --git a/svds/nrf9120.svd b/svds/nrf9120.svd new file mode 100644 index 00000000..da7e7c8a --- /dev/null +++ b/svds/nrf9120.svd @@ -0,0 +1,36216 @@ + + + + Nordic Semiconductor + Nordic + nrf9120 + nrf91 + 1 + nrf9120 reference description for radio MCU with ARM 32-bit Cortex-M33 Microcontroller + +Copyright (c) 2010 - 2024, Nordic Semiconductor ASA All rights reserved. + +SPDX-License-Identifier: BSD-3-Clause + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + +1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +3. Neither the name of Nordic Semiconductor ASA nor the names of its + contributors may be used to endorse or promote products derived from this + software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + + 8 + 32 + 32 + 0x00000000 + 0xFFFFFFFF + NRF_ + + CM33 + r0p4 + little + 1 + 1 + 3 + 0 + 69 + 0 + + system_nrf91 + + 240 + + + + FICR_S + Factory Information Configuration Registers + 0x00FF0000 + FICR + + + + 0 + 0x1000 + registers + + FICR + 0x20 + + + SIPINFO + SIP-specific device info + FICR_SIPINFO + read-write + 0x140 + + PARTNO + SIP part number + 0x000 + read-only + 0xFFFFFFFF + + + PARTNO + 0 + 31 + + + 9160 + Device is an nRF9160 sip + 0x00009160 + + + + + + + 0x4 + 0x1 + HWREVISION[%s] + Description collection: SIP hardware revision, encoded in ASCII, ex B0A or B1A + 0x004 + read-only + 0xFF + uint8_t + 0x8 + + + HWREVISION + 0 + 7 + + + + + 0x4 + 0x1 + VARIANT[%s] + Description collection: SIP VARIANT, encoded in ASCII, ex SIAA, SIBA or SICA + 0x008 + read-only + 0xFF + uint8_t + 0x8 + + + VARIANT + 0 + 7 + + + + + + INFO + Device info + FICR_INFO + read-write + 0x200 + + 0x2 + 0x4 + DEVICEID[%s] + Description collection: Device identifier + 0x004 + read-only + 0xFFFFFFFF + + + DEVICEID + 64 bit unique device identifier + 0 + 31 + + + + + PART + Part code + 0x00C + read-only + 0xFFFFFFFF + + + PART + Part code + 0 + 31 + + + N9160 + nRF9160 + 0x00009160 + + + N9120 + nRF9120 + 0x00009120 + + + + + + + VARIANT + Part Variant, Hardware version and Production configuration + 0x010 + read-only + 0x0FFFFFFF + + + VARIANT + Part Variant, Hardware version and Production configuration, encoded as ASCII + 0 + 31 + + + AAAA + AAAA + 0x41414141 + + + AAA0 + AAA0 + 0x41414130 + + + AAB0 + AAB0 + 0x41414230 + + + AAC0 + AAC0 + 0x41414330 + + + + + + + PACKAGE + Package option + 0x014 + read-only + 0x00002000 + + + PACKAGE + Package option + 0 + 31 + + + CF + CFxx - 236 ball wlCSP + 0x00002002 + + + + + + + RAM + RAM variant + 0x018 + read-only + 0x00000100 + + + RAM + RAM variant + 0 + 31 + + + K256 + 256 kByte RAM + 0x00000100 + + + Unspecified + Unspecified + 0xFFFFFFFF + + + + + + + FLASH + Flash variant + 0x01C + read-only + 0x00000400 + + + FLASH + Flash variant + 0 + 31 + + + K1024 + 1 MByte FLASH + 0x00000400 + + + + + + + CODEPAGESIZE + Code memory page size + 0x020 + read-only + 0x00001000 + + + CODEPAGESIZE + Code memory page size + 0 + 31 + + + K4096 + 4 kByte + 0x00001000 + + + + + + + CODESIZE + Code memory size + 0x024 + read-only + 0x00000100 + + + CODESIZE + Code memory size in number of pages Total code space is: CODEPAGESIZE * CODESIZE + 0 + 31 + + + P256 + 256 pages + 0x00000100 + + + + + + + DEVICETYPE + Device type + 0x028 + read-only + 0xFFFFFFFF + + + DEVICETYPE + Device type + 0 + 31 + + + Die + Device is an physical DIE + 0x00000000 + + + FPGA + Device is an FPGA + 0xFFFFFFFF + + + + + + + + 256 + 0x008 + TRIMCNF[%s] + Unspecified + FICR_TRIMCNF + read-write + 0x300 + + ADDR + Description cluster: Address + 0x000 + read-only + 0xFFFFFFFF + + + Address + Address + 0 + 31 + + + + + DATA + Description cluster: Data + 0x004 + read-only + 0xFFFFFFFF + + + Data + Data + 0 + 31 + + + + + + TRNG90B + NIST800-90B RNG calibration data + FICR_TRNG90B + read-write + 0xC00 + + BYTES + Amount of bytes for the required entropy bits + 0x000 + read-only + 0xFFFFFFFF + + + BYTES + Amount of bytes for the required entropy bits + 0 + 31 + + + + + RCCUTOFF + Repetition counter cutoff + 0x004 + read-only + 0xFFFFFFFF + + + RCCUTOFF + Repetition counter cutoff + 0 + 31 + + + + + APCUTOFF + Adaptive proportion cutoff + 0x008 + read-only + 0xFFFFFFFF + + + APCUTOFF + Adaptive proportion cutoff + 0 + 31 + + + + + STARTUP + Amount of bytes for the startup tests + 0x00C + read-only + 0xFFFFFFFF + + + STARTUP + Amount of bytes for the startup tests + 0 + 31 + + + + + ROSC1 + Sample count for ring oscillator 1 + 0x010 + read-only + 0xFFFFFFFF + + + ROSC1 + Sample count for ring oscillator 1 + 0 + 31 + + + + + ROSC2 + Sample count for ring oscillator 2 + 0x014 + read-only + 0xFFFFFFFF + + + ROSC2 + Sample count for ring oscillator 2 + 0 + 31 + + + + + ROSC3 + Sample count for ring oscillator 3 + 0x018 + read-only + 0xFFFFFFFF + + + ROSC3 + Sample count for ring oscillator 3 + 0 + 31 + + + + + ROSC4 + Sample count for ring oscillator 4 + 0x01C + read-only + 0xFFFFFFFF + + + ROSC4 + Sample count for ring oscillator 4 + 0 + 31 + + + + + + + + UICR_S + User information configuration registers User information configuration registers + 0x00FF8000 + UICR + + + + 0 + 0x1000 + registers + + UICR + 0x20 + + + APPROTECT + Access port protection + 0x000 + read-write + 0x00000000 + + + PALL + Blocks debugger read/write access to all CPU registers and + memory mapped addresses + 0 + 31 + + + HwUnprotected + HwUnprotected + 0x50FA50FA + + + Protected + Protected + 0x00000000 + + + + + + + XOSC32M + Oscillator control + 0x014 + read-write + 0xFFFFFFCF + + + CTRL + Pierce current DAC control signals + 0 + 5 + + + + + HFXOSRC + HFXO clock source selection + 0x01C + read-write + 0xFFFFFFFF + + + HFXOSRC + HFXO clock source selection + 0 + 0 + + + XTAL + 32 MHz crystal oscillator + 0x1 + + + TCXO + 32 MHz temperature compensated crystal oscillator (TCXO) + 0x0 + + + + + + + HFXOCNT + HFXO startup counter + 0x020 + read-write + 0xFFFFFFFF + + + HFXOCNT + HFXO startup counter. Total debounce time = HFXOCNT*64 us + 0.5 us + 0 + 7 + + + MinDebounceTime + Min debounce time = (0*64 us + 0.5 us) + 0x00 + + + MaxDebounceTime + Max debounce time = (255*64 us + 0.5 us) + 0xFF + + + + + + + APPNVMCPOFGUARD + Enable blocking NVM WRITE and aborting NVM ERASE for Application NVM in POFWARN condition . + 0x024 + read-write + 0xFFFFFFFF + + + NVMCPOFGUARDEN + Enable blocking NVM WRITE and aborting NVM ERASE in POFWARN condition + 0 + 0 + + + Disabled + NVM WRITE and NVM ERASE are not blocked in POFWARN condition + 0x0 + + + Enabled + NVM WRITE and NVM ERASE are blocked in POFWARN condition + 0x1 + + + + + + + PMICCONF + Polarity of PMIC polarity configuration signals. + 0x028 + read-write + 0xFFFFFFFF + + + PMICFPWMPOL + Polarity of PMIC_FPWM signal. + 0 + 0 + + + ActiveLow + PMIC_FPWM output signal is active-low + 0x0 + + + ActiveHigh + PMIC_FPWM output signal is active-high + 0x1 + + + + + + + SECUREAPPROTECT + Secure access port protection + 0x02C + read-write + 0x00000000 + + + PALL + Blocks debugger read/write access to all secure CPU registers and secure + memory mapped addresses + 0 + 31 + + + HwUnprotected + HwUnprotected + 0x50FA50FA + + + Protected + Protected + 0x00000000 + + + + + + + ERASEPROTECT + Erase protection + 0x030 + read-write + 0x00000000 + + + PALL + Blocks NVMC ERASEALL and CTRLAP ERASEALL functionality + 0 + 31 + + + Unprotected + Unprotected + 0xFFFFFFFF + + + Protected + Protected + 0x00000000 + + + + + + + 0xBE + 0x4 + OTP[%s] + Description collection: One time programmable memory + 0x108 + read-write + 0xFFFFFFFF + + + LOWER + Lower half word + 0 + 15 + read-writeOnce + + + UPPER + Upper half word + 16 + 31 + read-writeOnce + + + + + KEYSLOT + Unspecified + UICR_KEYSLOT + read-write + 0x400 + + 128 + 0x008 + CONFIG[%s] + Unspecified + UICR_KEYSLOT_CONFIG + read-write + 0x000 + + DEST + Description cluster: Destination address where content of the key value registers (KEYSLOT.KEYn.VALUE[0-3]) + will be pushed by KMU. Note that this address must match that of a peripherals + APB mapped write-only key registers, else the KMU can push this key value into + an address range which the CPU can potentially read. + 0x000 + read-write + 0xFFFFFFFF + + + DEST + Secure APB destination address + 0 + 31 + + + + + PERM + Description cluster: Define permissions for the key slot. Bits 0-15 and 16-31 can only be written when equal to 0xFFFF. + 0x004 + read-write + 0xFFFFFFFF + + + WRITE + Write permission for key slot + 0 + 0 + + + Disabled + Disable write to the key value registers + 0x0 + + + Enabled + Enable write to the key value registers + 0x1 + + + + + READ + Read permission for key slot + 1 + 1 + + + Disabled + Disable read from key value registers + 0x0 + + + Enabled + Enable read from key value registers + 0x1 + + + + + PUSH + Push permission for key slot + 2 + 2 + + + Disabled + Disable pushing of key value registers over secure APB, but can be read if field READ is Enabled + 0x0 + + + Enabled + Enable pushing of key value registers over secure APB. Register KEYSLOT.CONFIGn.DEST must contain a valid destination address! + 0x1 + + + + + STATE + Revocation state for the key slot + 16 + 16 + + + Revoked + Key value registers can no longer be read or pushed + 0x0 + + + Active + Key value registers are readable (if enabled) and can be pushed (if enabled) + 0x1 + + + + + + + + 128 + 0x010 + KEY[%s] + Unspecified + UICR_KEYSLOT_KEY + read-write + 0x400 + + 0x4 + 0x4 + VALUE[%s] + Description collection: Define bits [31+o*32:0+o*32] of value assigned to KMU key slot. + 0x000 + read-write + 0xFFFFFFFF + + + VALUE + Define bits [31+o*32:0+o*32] of value assigned to KMU key slot + 0 + 31 + + + + + + + + + TAD_S + Trace and debug control + 0xE0080000 + TAD + + + + 0 + 0x1000 + registers + + TAD + 0x20 + + + TASKS_CLOCKSTART + Start all trace and debug clocks. + 0x000 + write-only + 0x00000000 + + + TASKS_CLOCKSTART + Start all trace and debug clocks. + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_CLOCKSTOP + Stop all trace and debug clocks. + 0x004 + write-only + 0x00000000 + + + TASKS_CLOCKSTOP + Stop all trace and debug clocks. + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + ENABLE + Enable debug domain and aquire selected GPIOs + 0x500 + read-write + 0x00000000 + + + ENABLE + 0 + 0 + + + DISABLED + Disable debug domain and release selected GPIOs + 0x0 + + + ENABLED + Enable debug domain and aquire selected GPIOs + 0x1 + + + + + + + PSEL + Unspecified + TAD_PSEL + read-write + 0x504 + + TRACECLK + Pin configuration for TRACECLK + 0x000 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + Traceclk + TRACECLK pin + 0x15 + + + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 0x1 + + + Connected + Connect + 0x0 + + + + + + + TRACEDATA0 + Pin configuration for TRACEDATA[0] + 0x004 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + Tracedata0 + TRACEDATA0 pin + 0x16 + + + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 0x1 + + + Connected + Connect + 0x0 + + + + + + + TRACEDATA1 + Pin configuration for TRACEDATA[1] + 0x008 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + Tracedata1 + TRACEDATA1 pin + 0x17 + + + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 0x1 + + + Connected + Connect + 0x0 + + + + + + + TRACEDATA2 + Pin configuration for TRACEDATA[2] + 0x00C + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + Tracedata2 + TRACEDATA2 pin + 0x18 + + + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 0x1 + + + Connected + Connect + 0x0 + + + + + + + TRACEDATA3 + Pin configuration for TRACEDATA[3] + 0x010 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + Tracedata3 + TRACEDATA3 pin + 0x19 + + + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 0x1 + + + Connected + Connect + 0x0 + + + + + + + + TRACEPORTSPEED + Clocking options for the Trace Port debug interface Reset behavior is the same as debug components + 0x518 + read-write + 0x00000000 + + + TRACEPORTSPEED + Speed of Trace Port clock. Note that the TRACECLK pin output will be divided again by two from the Trace Port clock. + 0 + 1 + + + 32MHz + Trace Port clock is: 32MHz + 0x0 + + + 16MHz + Trace Port clock is: 16MHz + 0x1 + + + 8MHz + Trace Port clock is: 8MHz + 0x2 + + + 4MHz + Trace Port clock is: 4MHz + 0x3 + + + + + + + + + SPU_S + System protection unit + 0x50003000 + SPU + + + + 0 + 0x1000 + registers + + + SPU + 3 + + SPU + 0x20 + + + EVENTS_RAMACCERR + A security violation has been detected for the RAM memory space + 0x100 + read-write + 0x00000000 + + + EVENTS_RAMACCERR + A security violation has been detected for the RAM memory space + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_FLASHACCERR + A security violation has been detected for the flash memory space + 0x104 + read-write + 0x00000000 + + + EVENTS_FLASHACCERR + A security violation has been detected for the flash memory space + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_PERIPHACCERR + A security violation has been detected on one or several peripherals + 0x108 + read-write + 0x00000000 + + + EVENTS_PERIPHACCERR + A security violation has been detected on one or several peripherals + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + PUBLISH_RAMACCERR + Publish configuration for event RAMACCERR + 0x180 + read-write + 0x00000000 + + + CHIDX + DPPI channel that event RAMACCERR will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_FLASHACCERR + Publish configuration for event FLASHACCERR + 0x184 + read-write + 0x00000000 + + + CHIDX + DPPI channel that event FLASHACCERR will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_PERIPHACCERR + Publish configuration for event PERIPHACCERR + 0x188 + read-write + 0x00000000 + + + CHIDX + DPPI channel that event PERIPHACCERR will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + 0x00000000 + + + RAMACCERR + Enable or disable interrupt for event RAMACCERR + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + FLASHACCERR + Enable or disable interrupt for event FLASHACCERR + 1 + 1 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + PERIPHACCERR + Enable or disable interrupt for event PERIPHACCERR + 2 + 2 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + 0x00000000 + + + RAMACCERR + Write '1' to enable interrupt for event RAMACCERR + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + FLASHACCERR + Write '1' to enable interrupt for event FLASHACCERR + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + PERIPHACCERR + Write '1' to enable interrupt for event PERIPHACCERR + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + 0x00000000 + + + RAMACCERR + Write '1' to disable interrupt for event RAMACCERR + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + FLASHACCERR + Write '1' to disable interrupt for event FLASHACCERR + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + PERIPHACCERR + Write '1' to disable interrupt for event PERIPHACCERR + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + CAP + Show implemented features for the current device + 0x400 + read-only + 0x00000001 + + + TZM + Show ARM TrustZone status + 0 + 0 + + + NotAvailable + ARM TrustZone support not available + 0x0 + + + Enabled + ARM TrustZone support is available + 0x1 + + + + + + + 1 + 0x004 + EXTDOMAIN[%s] + Unspecified + SPU_EXTDOMAIN + read-write + 0x440 + + PERM + Description cluster: Access for bus access generated from the external domain n List capabilities of the external domain n + 0x000 + read-write + 0x00000000 + + + SECUREMAPPING + Define configuration capabilities for TrustZone Cortex-M secure attribute + 0 + 1 + read-only + + + NonSecure + The bus access from this external domain always have the non-secure attribute set + 0x0 + + + Secure + The bus access from this external domain always have the secure attribute set + 0x1 + + + UserSelectable + Non-secure or secure attribute for bus access from this domain is defined by the EXTDOMAIN[n].PERM register + 0x2 + + + + + SECATTR + Peripheral security mapping + 4 + 4 + + + NonSecure + Bus accesses from this domain have the non-secure attribute set + 0x0 + + + Secure + Bus accesses from this domain have secure attribute set + 0x1 + + + + + LOCK + 8 + 8 + + + Unlocked + This register can be updated + 0x0 + + + Locked + The content of this register can't be changed until the next reset + 0x1 + + + + + + + + 1 + 0x008 + DPPI[%s] + Unspecified + SPU_DPPI + read-write + 0x480 + + PERM + Description cluster: Select between secure and non-secure attribute for the DPPI channels. + 0x000 + read-write + 0x0000FFFF + + + CHANNEL0 + Select secure attribute. + 0 + 0 + + + Secure + Channel0 has its secure attribute set + 0x1 + + + NonSecure + Channel0 has its non-secure attribute set + 0x0 + + + + + CHANNEL1 + Select secure attribute. + 1 + 1 + + + Secure + Channel1 has its secure attribute set + 0x1 + + + NonSecure + Channel1 has its non-secure attribute set + 0x0 + + + + + CHANNEL2 + Select secure attribute. + 2 + 2 + + + Secure + Channel2 has its secure attribute set + 0x1 + + + NonSecure + Channel2 has its non-secure attribute set + 0x0 + + + + + CHANNEL3 + Select secure attribute. + 3 + 3 + + + Secure + Channel3 has its secure attribute set + 0x1 + + + NonSecure + Channel3 has its non-secure attribute set + 0x0 + + + + + CHANNEL4 + Select secure attribute. + 4 + 4 + + + Secure + Channel4 has its secure attribute set + 0x1 + + + NonSecure + Channel4 has its non-secure attribute set + 0x0 + + + + + CHANNEL5 + Select secure attribute. + 5 + 5 + + + Secure + Channel5 has its secure attribute set + 0x1 + + + NonSecure + Channel5 has its non-secure attribute set + 0x0 + + + + + CHANNEL6 + Select secure attribute. + 6 + 6 + + + Secure + Channel6 has its secure attribute set + 0x1 + + + NonSecure + Channel6 has its non-secure attribute set + 0x0 + + + + + CHANNEL7 + Select secure attribute. + 7 + 7 + + + Secure + Channel7 has its secure attribute set + 0x1 + + + NonSecure + Channel7 has its non-secure attribute set + 0x0 + + + + + CHANNEL8 + Select secure attribute. + 8 + 8 + + + Secure + Channel8 has its secure attribute set + 0x1 + + + NonSecure + Channel8 has its non-secure attribute set + 0x0 + + + + + CHANNEL9 + Select secure attribute. + 9 + 9 + + + Secure + Channel9 has its secure attribute set + 0x1 + + + NonSecure + Channel9 has its non-secure attribute set + 0x0 + + + + + CHANNEL10 + Select secure attribute. + 10 + 10 + + + Secure + Channel10 has its secure attribute set + 0x1 + + + NonSecure + Channel10 has its non-secure attribute set + 0x0 + + + + + CHANNEL11 + Select secure attribute. + 11 + 11 + + + Secure + Channel11 has its secure attribute set + 0x1 + + + NonSecure + Channel11 has its non-secure attribute set + 0x0 + + + + + CHANNEL12 + Select secure attribute. + 12 + 12 + + + Secure + Channel12 has its secure attribute set + 0x1 + + + NonSecure + Channel12 has its non-secure attribute set + 0x0 + + + + + CHANNEL13 + Select secure attribute. + 13 + 13 + + + Secure + Channel13 has its secure attribute set + 0x1 + + + NonSecure + Channel13 has its non-secure attribute set + 0x0 + + + + + CHANNEL14 + Select secure attribute. + 14 + 14 + + + Secure + Channel14 has its secure attribute set + 0x1 + + + NonSecure + Channel14 has its non-secure attribute set + 0x0 + + + + + CHANNEL15 + Select secure attribute. + 15 + 15 + + + Secure + Channel15 has its secure attribute set + 0x1 + + + NonSecure + Channel15 has its non-secure attribute set + 0x0 + + + + + + + LOCK + Description cluster: Prevent further modification of the corresponding PERM register + 0x004 + read-write + 0x00000000 + + + LOCK + 0 + 0 + + + Locked + DPPI[n].PERM register can't be changed until next reset + 0x1 + + + Unlocked + DPPI[n].PERM register content can be changed + 0x0 + + + + + + + + 1 + 0x008 + GPIOPORT[%s] + Unspecified + SPU_GPIOPORT + read-write + 0x4C0 + + PERM + Description cluster: Select between secure and non-secure attribute for pins 0 to 31 of port n. + 0x000 + read-write + 0xFFFFFFFF + + + PIN0 + Select secure attribute attribute for PIN 0. + 0 + 0 + + + Secure + Pin 0 has its secure attribute set + 0x1 + + + NonSecure + Pin 0 has its non-secure attribute set + 0x0 + + + + + PIN1 + Select secure attribute attribute for PIN 1. + 1 + 1 + + + Secure + Pin 1 has its secure attribute set + 0x1 + + + NonSecure + Pin 1 has its non-secure attribute set + 0x0 + + + + + PIN2 + Select secure attribute attribute for PIN 2. + 2 + 2 + + + Secure + Pin 2 has its secure attribute set + 0x1 + + + NonSecure + Pin 2 has its non-secure attribute set + 0x0 + + + + + PIN3 + Select secure attribute attribute for PIN 3. + 3 + 3 + + + Secure + Pin 3 has its secure attribute set + 0x1 + + + NonSecure + Pin 3 has its non-secure attribute set + 0x0 + + + + + PIN4 + Select secure attribute attribute for PIN 4. + 4 + 4 + + + Secure + Pin 4 has its secure attribute set + 0x1 + + + NonSecure + Pin 4 has its non-secure attribute set + 0x0 + + + + + PIN5 + Select secure attribute attribute for PIN 5. + 5 + 5 + + + Secure + Pin 5 has its secure attribute set + 0x1 + + + NonSecure + Pin 5 has its non-secure attribute set + 0x0 + + + + + PIN6 + Select secure attribute attribute for PIN 6. + 6 + 6 + + + Secure + Pin 6 has its secure attribute set + 0x1 + + + NonSecure + Pin 6 has its non-secure attribute set + 0x0 + + + + + PIN7 + Select secure attribute attribute for PIN 7. + 7 + 7 + + + Secure + Pin 7 has its secure attribute set + 0x1 + + + NonSecure + Pin 7 has its non-secure attribute set + 0x0 + + + + + PIN8 + Select secure attribute attribute for PIN 8. + 8 + 8 + + + Secure + Pin 8 has its secure attribute set + 0x1 + + + NonSecure + Pin 8 has its non-secure attribute set + 0x0 + + + + + PIN9 + Select secure attribute attribute for PIN 9. + 9 + 9 + + + Secure + Pin 9 has its secure attribute set + 0x1 + + + NonSecure + Pin 9 has its non-secure attribute set + 0x0 + + + + + PIN10 + Select secure attribute attribute for PIN 10. + 10 + 10 + + + Secure + Pin 10 has its secure attribute set + 0x1 + + + NonSecure + Pin 10 has its non-secure attribute set + 0x0 + + + + + PIN11 + Select secure attribute attribute for PIN 11. + 11 + 11 + + + Secure + Pin 11 has its secure attribute set + 0x1 + + + NonSecure + Pin 11 has its non-secure attribute set + 0x0 + + + + + PIN12 + Select secure attribute attribute for PIN 12. + 12 + 12 + + + Secure + Pin 12 has its secure attribute set + 0x1 + + + NonSecure + Pin 12 has its non-secure attribute set + 0x0 + + + + + PIN13 + Select secure attribute attribute for PIN 13. + 13 + 13 + + + Secure + Pin 13 has its secure attribute set + 0x1 + + + NonSecure + Pin 13 has its non-secure attribute set + 0x0 + + + + + PIN14 + Select secure attribute attribute for PIN 14. + 14 + 14 + + + Secure + Pin 14 has its secure attribute set + 0x1 + + + NonSecure + Pin 14 has its non-secure attribute set + 0x0 + + + + + PIN15 + Select secure attribute attribute for PIN 15. + 15 + 15 + + + Secure + Pin 15 has its secure attribute set + 0x1 + + + NonSecure + Pin 15 has its non-secure attribute set + 0x0 + + + + + PIN16 + Select secure attribute attribute for PIN 16. + 16 + 16 + + + Secure + Pin 16 has its secure attribute set + 0x1 + + + NonSecure + Pin 16 has its non-secure attribute set + 0x0 + + + + + PIN17 + Select secure attribute attribute for PIN 17. + 17 + 17 + + + Secure + Pin 17 has its secure attribute set + 0x1 + + + NonSecure + Pin 17 has its non-secure attribute set + 0x0 + + + + + PIN18 + Select secure attribute attribute for PIN 18. + 18 + 18 + + + Secure + Pin 18 has its secure attribute set + 0x1 + + + NonSecure + Pin 18 has its non-secure attribute set + 0x0 + + + + + PIN19 + Select secure attribute attribute for PIN 19. + 19 + 19 + + + Secure + Pin 19 has its secure attribute set + 0x1 + + + NonSecure + Pin 19 has its non-secure attribute set + 0x0 + + + + + PIN20 + Select secure attribute attribute for PIN 20. + 20 + 20 + + + Secure + Pin 20 has its secure attribute set + 0x1 + + + NonSecure + Pin 20 has its non-secure attribute set + 0x0 + + + + + PIN21 + Select secure attribute attribute for PIN 21. + 21 + 21 + + + Secure + Pin 21 has its secure attribute set + 0x1 + + + NonSecure + Pin 21 has its non-secure attribute set + 0x0 + + + + + PIN22 + Select secure attribute attribute for PIN 22. + 22 + 22 + + + Secure + Pin 22 has its secure attribute set + 0x1 + + + NonSecure + Pin 22 has its non-secure attribute set + 0x0 + + + + + PIN23 + Select secure attribute attribute for PIN 23. + 23 + 23 + + + Secure + Pin 23 has its secure attribute set + 0x1 + + + NonSecure + Pin 23 has its non-secure attribute set + 0x0 + + + + + PIN24 + Select secure attribute attribute for PIN 24. + 24 + 24 + + + Secure + Pin 24 has its secure attribute set + 0x1 + + + NonSecure + Pin 24 has its non-secure attribute set + 0x0 + + + + + PIN25 + Select secure attribute attribute for PIN 25. + 25 + 25 + + + Secure + Pin 25 has its secure attribute set + 0x1 + + + NonSecure + Pin 25 has its non-secure attribute set + 0x0 + + + + + PIN26 + Select secure attribute attribute for PIN 26. + 26 + 26 + + + Secure + Pin 26 has its secure attribute set + 0x1 + + + NonSecure + Pin 26 has its non-secure attribute set + 0x0 + + + + + PIN27 + Select secure attribute attribute for PIN 27. + 27 + 27 + + + Secure + Pin 27 has its secure attribute set + 0x1 + + + NonSecure + Pin 27 has its non-secure attribute set + 0x0 + + + + + PIN28 + Select secure attribute attribute for PIN 28. + 28 + 28 + + + Secure + Pin 28 has its secure attribute set + 0x1 + + + NonSecure + Pin 28 has its non-secure attribute set + 0x0 + + + + + PIN29 + Select secure attribute attribute for PIN 29. + 29 + 29 + + + Secure + Pin 29 has its secure attribute set + 0x1 + + + NonSecure + Pin 29 has its non-secure attribute set + 0x0 + + + + + PIN30 + Select secure attribute attribute for PIN 30. + 30 + 30 + + + Secure + Pin 30 has its secure attribute set + 0x1 + + + NonSecure + Pin 30 has its non-secure attribute set + 0x0 + + + + + PIN31 + Select secure attribute attribute for PIN 31. + 31 + 31 + + + Secure + Pin 31 has its secure attribute set + 0x1 + + + NonSecure + Pin 31 has its non-secure attribute set + 0x0 + + + + + + + LOCK + Description cluster: Prevent further modification of the corresponding PERM register + 0x004 + read-write + 0x00000000 + + + LOCK + 0 + 0 + + + Locked + GPIOPORT[n].PERM register can't be changed until next reset + 0x1 + + + Unlocked + GPIOPORT[n].PERM register content can be changed + 0x0 + + + + + + + + 2 + 0x008 + FLASHNSC[%s] + Unspecified + SPU_FLASHNSC + read-write + 0x500 + + REGION + Description cluster: Define which flash region can contain the non-secure callable (NSC) region n + 0x000 + read-write + 0x00000000 + + + REGION + Region number + 0 + 4 + + + LOCK + 8 + 8 + + + Unlocked + This register can be updated + 0x0 + + + Locked + The content of this register can't be changed until the next reset + 0x1 + + + + + + + SIZE + Description cluster: Define the size of the non-secure callable (NSC) region n + 0x004 + read-write + 0x00000000 + + + SIZE + Size of the non-secure callable (NSC) region n + 0 + 3 + + + Disabled + The region n is not defined as a non-secure callable region. Normal security attributes (secure or non-secure) are enforced. + 0x0 + + + 32 + The region n is defined as non-secure callable with a 32-byte size + 0x1 + + + 64 + The region n is defined as non-secure callable with a 64-byte size + 0x2 + + + 128 + The region n is defined as non-secure callable with a 128-byte size + 0x3 + + + 256 + The region n is defined as non-secure callable with a 256-byte size + 0x4 + + + 512 + The region n is defined as non-secure callable with a 512-byte size + 0x5 + + + 1024 + The region n is defined as non-secure callable with a 1024-byte size + 0x6 + + + 2048 + The region n is defined as non-secure callable with a 2048-byte size + 0x7 + + + 4096 + The region n is defined as non-secure callable with a 4096-byte size + 0x8 + + + + + LOCK + 8 + 8 + + + Unlocked + This register can be updated + 0x0 + + + Locked + The content of this register can't be changed until the next reset + 0x1 + + + + + + + + 2 + 0x008 + RAMNSC[%s] + Unspecified + SPU_RAMNSC + read-write + 0x540 + + REGION + Description cluster: Define which RAM region can contain the non-secure callable (NSC) region n + 0x000 + read-write + 0x00000000 + + + REGION + Region number + 0 + 4 + + + LOCK + 8 + 8 + + + Unlocked + This register can be updated + 0x0 + + + Locked + The content of this register can't be changed until the next reset + 0x1 + + + + + + + SIZE + Description cluster: Define the size of the non-secure callable (NSC) region n + 0x004 + read-write + 0x00000000 + + + SIZE + Size of the non-secure callable (NSC) region n + 0 + 3 + + + Disabled + The region n is not defined as a non-secure callable region. Normal security attributes (secure or non-secure) are enforced. + 0x0 + + + 32 + The region n is defined as non-secure callable with a 32-byte size + 0x1 + + + 64 + The region n is defined as non-secure callable with a 64-byte size + 0x2 + + + 128 + The region n is defined as non-secure callable with a 128-byte size + 0x3 + + + 256 + The region n is defined as non-secure callable with a 256-byte size + 0x4 + + + 512 + The region n is defined as non-secure callable with a 512-byte size + 0x5 + + + 1024 + The region n is defined as non-secure callable with a 1024-byte size + 0x6 + + + 2048 + The region n is defined as non-secure callable with a 2048-byte size + 0x7 + + + 4096 + The region n is defined as non-secure callable with a 4096-byte size + 0x8 + + + + + LOCK + 8 + 8 + + + Unlocked + This register can be updated + 0x0 + + + Locked + The content of this register can't be changed until the next reset + 0x1 + + + + + + + + 32 + 0x004 + FLASHREGION[%s] + Unspecified + SPU_FLASHREGION + read-write + 0x600 + + PERM + Description cluster: Access permissions for flash region n + 0x000 + read-write + 0x00000017 + + + EXECUTE + Configure instruction fetch permissions from flash region n + 0 + 0 + + + Enable + Allow instruction fetches from flash region n + 0x1 + + + Disable + Block instruction fetches from flash region n + 0x0 + + + + + WRITE + Configure write permission for flash region n + 1 + 1 + + + Enable + Allow write operation to region n + 0x1 + + + Disable + Block write operation to region n + 0x0 + + + + + READ + Configure read permissions for flash region n + 2 + 2 + + + Enable + Allow read operation from flash region n + 0x1 + + + Disable + Block read operation from flash region n + 0x0 + + + + + SECATTR + Security attribute for flash region n + 4 + 4 + + + Non_Secure + Flash region n security attribute is non-secure + 0x0 + + + Secure + Flash region n security attribute is secure + 0x1 + + + + + LOCK + 8 + 8 + + + Unlocked + This register can be updated + 0x0 + + + Locked + The content of this register can't be changed until the next reset + 0x1 + + + + + + + + 32 + 0x004 + RAMREGION[%s] + Unspecified + SPU_RAMREGION + read-write + 0x700 + + PERM + Description cluster: Access permissions for RAM region n + 0x000 + read-write + 0x00000017 + + + EXECUTE + Configure instruction fetch permissions from RAM region n + 0 + 0 + + + Enable + Allow instruction fetches from RAM region n + 0x1 + + + Disable + Block instruction fetches from RAM region n + 0x0 + + + + + WRITE + Configure write permission for RAM region n + 1 + 1 + + + Enable + Allow write operation to RAM region n + 0x1 + + + Disable + Block write operation to RAM region n + 0x0 + + + + + READ + Configure read permissions for RAM region n + 2 + 2 + + + Enable + Allow read operation from RAM region n + 0x1 + + + Disable + Block read operation from RAM region n + 0x0 + + + + + SECATTR + Security attribute for RAM region n + 4 + 4 + + + Non_Secure + RAM region n security attribute is non-secure + 0x0 + + + Secure + RAM region n security attribute is secure + 0x1 + + + + + LOCK + 8 + 8 + + + Unlocked + This register can be updated + 0x0 + + + Locked + The content of this register can't be changed until the next reset + 0x1 + + + + + + + + 67 + 0x004 + PERIPHID[%s] + Unspecified + SPU_PERIPHID + read-write + 0x800 + + PERM + Description cluster: List capabilities and access permissions for the peripheral with ID n + 0x000 + read-write + 0x00000012 + + + SECUREMAPPING + Define configuration capabilities for TrustZone Cortex-M secure attribute + 0 + 1 + read-only + + + NonSecure + This peripheral is always accessible as a non-secure peripheral + 0x0 + + + Secure + This peripheral is always accessible as a secure peripheral + 0x1 + + + UserSelectable + Non-secure or secure attribute for this peripheral is defined by the PERIPHID[n].PERM register + 0x2 + + + Split + This peripheral implements the split security mechanism. Non-secure or secure attribute for this peripheral is defined by the PERIPHID[n].PERM register. + 0x3 + + + + + DMA + Indicate if the peripheral has DMA capabilities and if DMA transfer can be assigned to a different security attribute than the peripheral itself + 2 + 3 + read-only + + + NoDMA + Peripheral has no DMA capability + 0x0 + + + NoSeparateAttribute + Peripheral has DMA and DMA transfers always have the same security attribute as assigned to the peripheral + 0x1 + + + SeparateAttribute + Peripheral has DMA and DMA transfers can have a different security attribute than the one assigned to the peripheral + 0x2 + + + + + SECATTR + Peripheral security mapping + 4 + 4 + + + Secure + Peripheral is mapped in secure peripheral address space + 0x1 + + + NonSecure + If SECUREMAPPING == UserSelectable: Peripheral is mapped in non-secure peripheral address space. If SECUREMAPPING == Split: Peripheral is mapped in non-secure and secure peripheral address space. + 0x0 + + + + + DMASEC + Security attribution for the DMA transfer + 5 + 5 + + + Secure + DMA transfers initiated by this peripheral have the secure attribute set + 0x1 + + + NonSecure + DMA transfers initiated by this peripheral have the non-secure attribute set + 0x0 + + + + + LOCK + 8 + 8 + + + Unlocked + This register can be updated + 0x0 + + + Locked + The content of this register can't be changed until the next reset + 0x1 + + + + + PRESENT + Indicate if a peripheral is present with ID n + 31 + 31 + read-only + + + NotPresent + Peripheral is not present + 0x0 + + + IsPresent + Peripheral is present + 0x1 + + + + + + + + + + REGULATORS_NS + Voltage regulators control 0 + 0x40004000 + REGULATORS + + + + 0 + 0x1000 + registers + + REGULATORS + 0x20 + + + SYSTEMOFF + System OFF register + 0x500 + write-only + 0x00000000 + + + SYSTEMOFF + Enable System OFF mode + 0 + 0 + + + Enable + Enable System OFF mode + 0x1 + + + + + + + EXTPOFCON + External power failure warning configuration + 0x514 + read-write + 0x00000000 + + + POF + Enable or disable external power failure warning + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + DCDCEN + Enable DC/DC mode of the main voltage regulator. + 0x578 + read-write + 0x00000000 + + + DCDCEN + Enable DC/DC converter + 0 + 0 + + + Disabled + DC/DC mode is disabled + 0x0 + + + Enabled + DC/DC mode is enabled + 0x1 + + + + + + + + + REGULATORS_S + Voltage regulators control 1 + 0x50004000 + + + + + CLOCK_NS + Clock management 0 + 0x40005000 + CLOCK + + + + 0 + 0x1000 + registers + + + CLOCK_POWER + 5 + + CLOCK + 0x20 + + + TASKS_HFCLKSTART + Start HFCLK source + 0x000 + write-only + 0x00000000 + + + TASKS_HFCLKSTART + Start HFCLK source + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_HFCLKSTOP + Stop HFCLK source + 0x004 + write-only + 0x00000000 + + + TASKS_HFCLKSTOP + Stop HFCLK source + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_LFCLKSTART + Start LFCLK source + 0x008 + write-only + 0x00000000 + + + TASKS_LFCLKSTART + Start LFCLK source + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_LFCLKSTOP + Stop LFCLK source + 0x00C + write-only + 0x00000000 + + + TASKS_LFCLKSTOP + Stop LFCLK source + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + SUBSCRIBE_HFCLKSTART + Subscribe configuration for task HFCLKSTART + 0x080 + read-write + 0x00000000 + + + CHIDX + DPPI channel that task HFCLKSTART will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_HFCLKSTOP + Subscribe configuration for task HFCLKSTOP + 0x084 + read-write + 0x00000000 + + + CHIDX + DPPI channel that task HFCLKSTOP will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_LFCLKSTART + Subscribe configuration for task LFCLKSTART + 0x088 + read-write + 0x00000000 + + + CHIDX + DPPI channel that task LFCLKSTART will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_LFCLKSTOP + Subscribe configuration for task LFCLKSTOP + 0x08C + read-write + 0x00000000 + + + CHIDX + DPPI channel that task LFCLKSTOP will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + EVENTS_HFCLKSTARTED + HFCLK oscillator started + 0x100 + read-write + 0x00000000 + + + EVENTS_HFCLKSTARTED + HFCLK oscillator started + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_LFCLKSTARTED + LFCLK started + 0x104 + read-write + 0x00000000 + + + EVENTS_LFCLKSTARTED + LFCLK started + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + PUBLISH_HFCLKSTARTED + Publish configuration for event HFCLKSTARTED + 0x180 + read-write + 0x00000000 + + + CHIDX + DPPI channel that event HFCLKSTARTED will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_LFCLKSTARTED + Publish configuration for event LFCLKSTARTED + 0x184 + read-write + 0x00000000 + + + CHIDX + DPPI channel that event LFCLKSTARTED will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + 0x00000000 + + + HFCLKSTARTED + Enable or disable interrupt for event HFCLKSTARTED + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + LFCLKSTARTED + Enable or disable interrupt for event LFCLKSTARTED + 1 + 1 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + 0x00000000 + + + HFCLKSTARTED + Write '1' to enable interrupt for event HFCLKSTARTED + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + LFCLKSTARTED + Write '1' to enable interrupt for event LFCLKSTARTED + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + 0x00000000 + + + HFCLKSTARTED + Write '1' to disable interrupt for event HFCLKSTARTED + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + LFCLKSTARTED + Write '1' to disable interrupt for event LFCLKSTARTED + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + INTPEND + Pending interrupts + 0x30C + read-only + 0x00000000 + + + HFCLKSTARTED + Read pending status of interrupt for event HFCLKSTARTED + 0 + 0 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + LFCLKSTARTED + Read pending status of interrupt for event LFCLKSTARTED + 1 + 1 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + + + HFCLKRUN + Status indicating that HFCLKSTART task has been triggered + 0x408 + read-only + 0x00000000 + + + STATUS + HFCLKSTART task triggered or not + 0 + 0 + + + NotTriggered + Task not triggered + 0x0 + + + Triggered + Task triggered + 0x1 + + + + + + + HFCLKSTAT + The register shows if HFXO has been requested by triggering HFCLKSTART task and if it has been started (STATE) + 0x40C + read-only + 0x00000000 + + + SRC + Active clock source + 0 + 0 + + + HFINT + HFINT - 64 MHz on-chip oscillator + 0x0 + + + HFXO + HFXO - 64 MHz clock derived from external 32 MHz crystal oscillator + 0x1 + + + + + STATE + HFCLK state + 16 + 16 + + + NotRunning + HFXO has not been started or HFCLKSTOP task has been triggered + 0x0 + + + Running + HFXO has been started (HFCLKSTARTED event has been generated) + 0x1 + + + + + + + LFCLKRUN + Status indicating that LFCLKSTART task has been triggered + 0x414 + read-only + 0x00000000 + + + STATUS + LFCLKSTART task triggered or not + 0 + 0 + + + NotTriggered + Task not triggered + 0x0 + + + Triggered + Task triggered + 0x1 + + + + + + + LFCLKSTAT + The register shows which LFCLK source has been requested (SRC) when triggering LFCLKSTART task and if the source has been started (STATE) + 0x418 + read-only + 0x00000000 + + + SRC + Active clock source + 0 + 1 + + + RFU + Reserved for future use + 0x0 + + + LFRC + 32.768 kHz RC oscillator + 0x1 + + + LFXO + 32.768 kHz crystal oscillator + 0x2 + + + + + STATE + LFCLK state + 16 + 16 + + + NotRunning + Requested LFCLK source has not been started or LFCLKSTOP task has been triggered + 0x0 + + + Running + Requested LFCLK source has been started (LFCLKSTARTED event has been generated) + 0x1 + + + + + + + LFCLKSRCCOPY + Copy of LFCLKSRC register, set after LFCLKSTART task has been triggered + 0x41C + read-only + 0x00000001 + + + SRC + Clock source + 0 + 1 + + + RFU + Reserved for future use + 0x0 + + + LFRC + 32.768 kHz RC oscillator + 0x1 + + + LFXO + 32.768 kHz crystal oscillator + 0x2 + + + + + + + LFCLKSRC + Clock source for the LFCLK. LFCLKSTART task starts starts a clock source selected with this register. + 0x518 + read-write + 0x00000001 + + + SRC + Clock source + 0 + 1 + + + RFU + Reserved for future use (equals selecting LFRC) + 0x0 + + + LFRC + 32.768 kHz RC oscillator + 0x1 + + + LFXO + 32.768 kHz crystal oscillator + 0x2 + + + + + + + + + POWER_NS + Power control 0 + 0x40005000 + CLOCK_NS + POWER + + + + 0 + 0x1000 + registers + + + CLOCK_POWER + 5 + + POWER + 0x20 + + + TASKS_PWMREQSTART + Request forcing PWM mode in external DC/DC voltage regulator. (Drives FPWM_DCDC pin high or low depending on a setting in UICR). + 0x70 + write-only + 0x00000000 + + + TASKS_PWMREQSTART + Request forcing PWM mode in external DC/DC voltage regulator. (Drives FPWM_DCDC pin high or low depending on a setting in UICR). + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_PWMREQSTOP + Stop requesting forcing PWM mode in external DC/DC voltage regulator + 0x74 + write-only + 0x00000000 + + + TASKS_PWMREQSTOP + Stop requesting forcing PWM mode in external DC/DC voltage regulator + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_CONSTLAT + Enable constant latency mode. + 0x78 + write-only + 0x00000000 + + + TASKS_CONSTLAT + Enable constant latency mode. + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_LOWPWR + Enable low power mode (variable latency) + 0x7C + write-only + 0x00000000 + + + TASKS_LOWPWR + Enable low power mode (variable latency) + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + SUBSCRIBE_PWMREQSTART + Subscribe configuration for task PWMREQSTART + 0xF0 + read-write + 0x00000000 + + + CHIDX + DPPI channel that task PWMREQSTART will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_PWMREQSTOP + Subscribe configuration for task PWMREQSTOP + 0xF4 + read-write + 0x00000000 + + + CHIDX + DPPI channel that task PWMREQSTOP will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_CONSTLAT + Subscribe configuration for task CONSTLAT + 0xF8 + read-write + 0x00000000 + + + CHIDX + DPPI channel that task CONSTLAT will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_LOWPWR + Subscribe configuration for task LOWPWR + 0xFC + read-write + 0x00000000 + + + CHIDX + DPPI channel that task LOWPWR will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + EVENTS_POFWARN + Power failure warning + 0x108 + read-write + 0x00000000 + + + EVENTS_POFWARN + Power failure warning + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_SLEEPENTER + CPU entered WFI/WFE sleep + 0x114 + read-write + 0x00000000 + + + EVENTS_SLEEPENTER + CPU entered WFI/WFE sleep + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_SLEEPEXIT + CPU exited WFI/WFE sleep + 0x118 + read-write + 0x00000000 + + + EVENTS_SLEEPEXIT + CPU exited WFI/WFE sleep + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + PUBLISH_POFWARN + Publish configuration for event POFWARN + 0x188 + read-write + 0x00000000 + + + CHIDX + DPPI channel that event POFWARN will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_SLEEPENTER + Publish configuration for event SLEEPENTER + 0x194 + read-write + 0x00000000 + + + CHIDX + DPPI channel that event SLEEPENTER will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_SLEEPEXIT + Publish configuration for event SLEEPEXIT + 0x198 + read-write + 0x00000000 + + + CHIDX + DPPI channel that event SLEEPEXIT will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + 0x00000000 + + + POFWARN + Enable or disable interrupt for event POFWARN + 2 + 2 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + SLEEPENTER + Enable or disable interrupt for event SLEEPENTER + 5 + 5 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + SLEEPEXIT + Enable or disable interrupt for event SLEEPEXIT + 6 + 6 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + 0x00000000 + + + POFWARN + Write '1' to enable interrupt for event POFWARN + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + SLEEPENTER + Write '1' to enable interrupt for event SLEEPENTER + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + SLEEPEXIT + Write '1' to enable interrupt for event SLEEPEXIT + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + 0x00000000 + + + POFWARN + Write '1' to disable interrupt for event POFWARN + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + SLEEPENTER + Write '1' to disable interrupt for event SLEEPENTER + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + SLEEPEXIT + Write '1' to disable interrupt for event SLEEPEXIT + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + RESETREAS + Reset reason + 0x400 + read-write + 0x00000000 + + + RESETPIN + Reset from pin reset detected + 0 + 0 + + + NotDetected + Not detected + 0x0 + + + Detected + Detected + 0x1 + + + + + DOG + Reset from global watchdog detected + 1 + 1 + + + NotDetected + Not detected + 0x0 + + + Detected + Detected + 0x1 + + + + + OFF + Reset due to wakeup from System OFF mode, when wakeup is triggered by DETECT signal from GPIO + 2 + 2 + + + NotDetected + Not detected + 0x0 + + + Detected + Detected + 0x1 + + + + + DIF + Reset due to wakeup from System OFF mode, when wakeup is triggered by entering debug interface mode + 4 + 4 + + + NotDetected + Not detected + 0x0 + + + Detected + Detected + 0x1 + + + + + SREQ + Reset from AIRCR.SYSRESETREQ detected + 16 + 16 + + + NotDetected + Not detected + 0x0 + + + Detected + Detected + 0x1 + + + + + LOCKUP + Reset from CPU lock-up detected + 17 + 17 + + + NotDetected + Not detected + 0x0 + + + Detected + Detected + 0x1 + + + + + CTRLAP + Reset triggered through CTRL-AP + 18 + 18 + + + NotDetected + Not detected + 0x0 + + + Detected + Detected + 0x1 + + + + + + + POWERSTATUS + Modem domain power status + 0x440 + read-only + 0x00000000 + + + LTEMODEM + LTE modem domain status + 0 + 0 + + + OFF + LTE modem domain is powered off + 0x0 + + + ON + LTE modem domain is powered on + 0x1 + + + + + + + 0x2 + 0x4 + GPREGRET[%s] + Description collection: General purpose retention register + 0x51C + read-write + 0x00000000 + + + GPREGRET + General purpose retention register + 0 + 7 + + + + + LTEMODEM + LTE Modem + POWER_LTEMODEM + read-write + 0x610 + + STARTN + Start LTE modem + 0x000 + read-write + 0x00000001 + + + STARTN + Start LTE modem + 0 + 0 + + + Start + Start LTE modem + 0x0 + + + Hold + Hold LTE modem disabled + 0x1 + + + + + + + FORCEOFF + Force off LTE modem + 0x004 + read-write + 0x00000000 + + + FORCEOFF + Force off LTE modem + 0 + 0 + + + Release + Release force off + 0x0 + + + Hold + Hold force off active + 0x1 + + + + + + + + + + CLOCK_S + Clock management 1 + 0x50005000 + + + + CLOCK_POWER + 5 + + + + POWER_S + Power control 1 + 0x50005000 + CLOCK_S + + + + CLOCK_POWER + 5 + + + + CTRL_AP_PERI_S + Control access port + 0x50006000 + CTRLAPPERI + + + + 0 + 0x1000 + registers + + CTRLAPPERI + 0x20 + + + MAILBOX + Unspecified + CTRLAPPERI_MAILBOX + read-write + 0x400 + + RXDATA + Data sent from the debugger to the CPU. + 0x000 + read-only + 0x00000000 + + + RXDATA + Data received from debugger + 0 + 31 + + + + + RXSTATUS + This register shows a status that indicates if data sent from the debugger to the CPU has been read. + 0x004 + read-only + 0x00000000 + + + RXSTATUS + Status of data in register RXDATA + 0 + 0 + + + NoDataPending + No data pending in register RXDATA + 0x0 + + + DataPending + Data pending in register RXDATA + 0x1 + + + + + + + TXDATA + Data sent from the CPU to the debugger. + 0x80 + read-write + 0x00000000 + + + TXDATA + Data sent to debugger + 0 + 31 + + + + + TXSTATUS + This register shows a status that indicates if the data sent from the CPU to the debugger has been read. + 0x84 + read-only + 0x00000000 + + + TXSTATUS + Status of data in register TXDATA + 0 + 0 + + + NoDataPending + No data pending in register TXDATA + 0x0 + + + DataPending + Data pending in register TXDATA + 0x1 + + + + + + + + ERASEPROTECT + Unspecified + CTRLAPPERI_ERASEPROTECT + read-write + 0x500 + + LOCK + This register locks the ERASEPROTECT.DISABLE register from being written until next reset. + 0x000 + read-writeOnce + 0x00000000 + + + LOCK + Lock ERASEPROTECT.DISABLE register from being written until next reset + 0 + 0 + + + Unlocked + Register ERASEPROTECT.DISABLE is writeable + 0x0 + + + Locked + Register ERASEPROTECT.DISABLE is read-only + 0x1 + + + + + + + DISABLE + This register disables the ERASEPROTECT register and performs an ERASEALL operation. + 0x004 + read-writeOnce + 0x00000000 + + + KEY + The ERASEALL sequence is initiated if the value of the KEY fields are non-zero and the KEY fields match on both the CPU and debugger sides. + 0 + 31 + + + + + + + + SPIM0_NS + Serial Peripheral Interface Master with EasyDMA 0 + 0x40008000 + SPIM + + + + 0 + 0x1000 + registers + + + SPIM0_SPIS0_TWIM0_TWIS0_UARTE0 + 8 + + SPIM + 0x20 + + + TASKS_START + Start SPI transaction + 0x010 + write-only + 0x00000000 + + + TASKS_START + Start SPI transaction + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_STOP + Stop SPI transaction + 0x014 + write-only + 0x00000000 + + + TASKS_STOP + Stop SPI transaction + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_SUSPEND + Suspend SPI transaction + 0x01C + write-only + 0x00000000 + + + TASKS_SUSPEND + Suspend SPI transaction + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_RESUME + Resume SPI transaction + 0x020 + write-only + 0x00000000 + + + TASKS_RESUME + Resume SPI transaction + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + SUBSCRIBE_START + Subscribe configuration for task START + 0x090 + read-write + 0x00000000 + + + CHIDX + DPPI channel that task START will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_STOP + Subscribe configuration for task STOP + 0x094 + read-write + 0x00000000 + + + CHIDX + DPPI channel that task STOP will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_SUSPEND + Subscribe configuration for task SUSPEND + 0x09C + read-write + 0x00000000 + + + CHIDX + DPPI channel that task SUSPEND will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_RESUME + Subscribe configuration for task RESUME + 0x0A0 + read-write + 0x00000000 + + + CHIDX + DPPI channel that task RESUME will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + EVENTS_STOPPED + SPI transaction has stopped + 0x104 + read-write + 0x00000000 + + + EVENTS_STOPPED + SPI transaction has stopped + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_ENDRX + End of RXD buffer reached + 0x110 + read-write + 0x00000000 + + + EVENTS_ENDRX + End of RXD buffer reached + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_END + End of RXD buffer and TXD buffer reached + 0x118 + read-write + 0x00000000 + + + EVENTS_END + End of RXD buffer and TXD buffer reached + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_ENDTX + End of TXD buffer reached + 0x120 + read-write + 0x00000000 + + + EVENTS_ENDTX + End of TXD buffer reached + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_STARTED + Transaction started + 0x14C + read-write + 0x00000000 + + + EVENTS_STARTED + Transaction started + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + PUBLISH_STOPPED + Publish configuration for event STOPPED + 0x184 + read-write + 0x00000000 + + + CHIDX + DPPI channel that event STOPPED will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_ENDRX + Publish configuration for event ENDRX + 0x190 + read-write + 0x00000000 + + + CHIDX + DPPI channel that event ENDRX will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_END + Publish configuration for event END + 0x198 + read-write + 0x00000000 + + + CHIDX + DPPI channel that event END will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_ENDTX + Publish configuration for event ENDTX + 0x1A0 + read-write + 0x00000000 + + + CHIDX + DPPI channel that event ENDTX will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_STARTED + Publish configuration for event STARTED + 0x1CC + read-write + 0x00000000 + + + CHIDX + DPPI channel that event STARTED will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + 0x00000000 + + + END_START + Shortcut between event END and task START + 17 + 17 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + 0x00000000 + + + STOPPED + Write '1' to enable interrupt for event STOPPED + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + ENDRX + Write '1' to enable interrupt for event ENDRX + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + END + Write '1' to enable interrupt for event END + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + ENDTX + Write '1' to enable interrupt for event ENDTX + 8 + 8 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + STARTED + Write '1' to enable interrupt for event STARTED + 19 + 19 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + 0x00000000 + + + STOPPED + Write '1' to disable interrupt for event STOPPED + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + ENDRX + Write '1' to disable interrupt for event ENDRX + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + END + Write '1' to disable interrupt for event END + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + ENDTX + Write '1' to disable interrupt for event ENDTX + 8 + 8 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + STARTED + Write '1' to disable interrupt for event STARTED + 19 + 19 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + ENABLE + Enable SPIM + 0x500 + read-write + 0x00000000 + + + ENABLE + Enable or disable SPIM + 0 + 3 + + + Disabled + Disable SPIM + 0x0 + + + Enabled + Enable SPIM + 0x7 + + + + + + + PSEL + Unspecified + SPIM_PSEL + read-write + 0x508 + + SCK + Pin select for SCK + 0x000 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 0x1 + + + Connected + Connect + 0x0 + + + + + + + MOSI + Pin select for MOSI signal + 0x004 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 0x1 + + + Connected + Connect + 0x0 + + + + + + + MISO + Pin select for MISO signal + 0x008 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 0x1 + + + Connected + Connect + 0x0 + + + + + + + + FREQUENCY + SPI frequency. Accuracy depends on the HFCLK source selected. + 0x524 + read-write + 0x04000000 + + + FREQUENCY + SPI master data rate + 0 + 31 + + + K125 + 125 kbps + 0x02000000 + + + K250 + 250 kbps + 0x04000000 + + + K500 + 500 kbps + 0x08000000 + + + M1 + 1 Mbps + 0x10000000 + + + M2 + 2 Mbps + 0x20000000 + + + M4 + 4 Mbps + 0x40000000 + + + M8 + 8 Mbps + 0x80000000 + + + + + + + RXD + RXD EasyDMA channel + SPIM_RXD + read-write + 0x534 + + PTR + Data pointer + 0x000 + read-write + 0x00000000 + + + PTR + Data pointer + 0 + 31 + + + + + MAXCNT + Maximum number of bytes in receive buffer + 0x004 + read-write + 0x00000000 + + + MAXCNT + Maximum number of bytes in receive buffer + 0 + 12 + + + + + AMOUNT + Number of bytes transferred in the last transaction + 0x008 + read-only + 0x00000000 + + + AMOUNT + Number of bytes transferred in the last transaction + 0 + 12 + + + + + LIST + EasyDMA list type + 0x00C + read-write + 0x00000000 + + + LIST + List type + 0 + 1 + + + Disabled + Disable EasyDMA list + 0x0 + + + ArrayList + Use array list + 0x1 + + + + + + + + TXD + TXD EasyDMA channel + SPIM_TXD + read-write + 0x544 + + PTR + Data pointer + 0x000 + read-write + 0x00000000 + + + PTR + Data pointer + 0 + 31 + + + + + MAXCNT + Maximum number of bytes in transmit buffer + 0x004 + read-write + 0x00000000 + + + MAXCNT + Maximum number of bytes in transmit buffer + 0 + 12 + + + + + AMOUNT + Number of bytes transferred in the last transaction + 0x008 + read-only + 0x00000000 + + + AMOUNT + Number of bytes transferred in the last transaction + 0 + 12 + + + + + LIST + EasyDMA list type + 0x00C + read-write + 0x00000000 + + + LIST + List type + 0 + 1 + + + Disabled + Disable EasyDMA list + 0x0 + + + ArrayList + Use array list + 0x1 + + + + + + + + CONFIG + Configuration register + 0x554 + read-write + 0x00000000 + + + ORDER + Bit order + 0 + 0 + + + MsbFirst + Most significant bit shifted out first + 0x0 + + + LsbFirst + Least significant bit shifted out first + 0x1 + + + + + CPHA + Serial clock (SCK) phase + 1 + 1 + + + Leading + Sample on leading edge of clock, shift serial data on trailing edge + 0x0 + + + Trailing + Sample on trailing edge of clock, shift serial data on leading edge + 0x1 + + + + + CPOL + Serial clock (SCK) polarity + 2 + 2 + + + ActiveHigh + Active high + 0x0 + + + ActiveLow + Active low + 0x1 + + + + + + + ORC + Over-read character. Character clocked out in case an over-read of the TXD buffer. + 0x5C0 + read-write + 0x00000000 + + + ORC + Over-read character. Character clocked out in case an over-read of the TXD buffer. + 0 + 7 + + + + + + + SPIS0_NS + SPI Slave 0 + 0x40008000 + SPIM0_NS + SPIS + + + + 0 + 0x1000 + registers + + + SPIM0_SPIS0_TWIM0_TWIS0_UARTE0 + 8 + + SPIS + 0x20 + + + TASKS_ACQUIRE + Acquire SPI semaphore + 0x024 + write-only + 0x00000000 + + + TASKS_ACQUIRE + Acquire SPI semaphore + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_RELEASE + Release SPI semaphore, enabling the SPI slave to acquire it + 0x028 + write-only + 0x00000000 + + + TASKS_RELEASE + Release SPI semaphore, enabling the SPI slave to acquire it + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + SUBSCRIBE_ACQUIRE + Subscribe configuration for task ACQUIRE + 0x0A4 + read-write + 0x00000000 + + + CHIDX + DPPI channel that task ACQUIRE will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_RELEASE + Subscribe configuration for task RELEASE + 0x0A8 + read-write + 0x00000000 + + + CHIDX + DPPI channel that task RELEASE will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + EVENTS_END + Granted transaction completed + 0x104 + read-write + 0x00000000 + + + EVENTS_END + Granted transaction completed + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_ENDRX + End of RXD buffer reached + 0x110 + read-write + 0x00000000 + + + EVENTS_ENDRX + End of RXD buffer reached + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_ACQUIRED + Semaphore acquired + 0x128 + read-write + 0x00000000 + + + EVENTS_ACQUIRED + Semaphore acquired + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + PUBLISH_END + Publish configuration for event END + 0x184 + read-write + 0x00000000 + + + CHIDX + DPPI channel that event END will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_ENDRX + Publish configuration for event ENDRX + 0x190 + read-write + 0x00000000 + + + CHIDX + DPPI channel that event ENDRX will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_ACQUIRED + Publish configuration for event ACQUIRED + 0x1A8 + read-write + 0x00000000 + + + CHIDX + DPPI channel that event ACQUIRED will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + 0x00000000 + + + END_ACQUIRE + Shortcut between event END and task ACQUIRE + 2 + 2 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + 0x00000000 + + + END + Write '1' to enable interrupt for event END + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + ENDRX + Write '1' to enable interrupt for event ENDRX + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + ACQUIRED + Write '1' to enable interrupt for event ACQUIRED + 10 + 10 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + 0x00000000 + + + END + Write '1' to disable interrupt for event END + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + ENDRX + Write '1' to disable interrupt for event ENDRX + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + ACQUIRED + Write '1' to disable interrupt for event ACQUIRED + 10 + 10 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + SEMSTAT + Semaphore status register + 0x400 + read-only + 0x00000001 + + + SEMSTAT + Semaphore status + 0 + 1 + + + Free + Semaphore is free + 0x0 + + + CPU + Semaphore is assigned to CPU + 0x1 + + + SPIS + Semaphore is assigned to SPI slave + 0x2 + + + CPUPending + Semaphore is assigned to SPI but a handover to the CPU is pending + 0x3 + + + + + + + STATUS + Status from last transaction + 0x440 + read-write + 0x00000000 + + + OVERREAD + TX buffer over-read detected, and prevented + 0 + 0 + + read + + NotPresent + Read: error not present + 0x0 + + + Present + Read: error present + 0x1 + + + + write + + Clear + Write: clear error on writing '1' + 0x1 + + + + + OVERFLOW + RX buffer overflow detected, and prevented + 1 + 1 + + read + + NotPresent + Read: error not present + 0x0 + + + Present + Read: error present + 0x1 + + + + write + + Clear + Write: clear error on writing '1' + 0x1 + + + + + + + ENABLE + Enable SPI slave + 0x500 + read-write + 0x00000000 + + + ENABLE + Enable or disable SPI slave + 0 + 3 + + + Disabled + Disable SPI slave + 0x0 + + + Enabled + Enable SPI slave + 0x2 + + + + + + + PSEL + Unspecified + SPIS_PSEL + read-write + 0x508 + + SCK + Pin select for SCK + 0x000 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 0x1 + + + Connected + Connect + 0x0 + + + + + + + MISO + Pin select for MISO signal + 0x004 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 0x1 + + + Connected + Connect + 0x0 + + + + + + + MOSI + Pin select for MOSI signal + 0x008 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 0x1 + + + Connected + Connect + 0x0 + + + + + + + CSN + Pin select for CSN signal + 0x00C + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 0x1 + + + Connected + Connect + 0x0 + + + + + + + + RXD + Unspecified + SPIS_RXD + read-write + 0x534 + + PTR + RXD data pointer + 0x000 + read-write + 0x00000000 + + + PTR + RXD data pointer + 0 + 31 + + + + + MAXCNT + Maximum number of bytes in receive buffer + 0x004 + read-write + 0x00000000 + + + MAXCNT + Maximum number of bytes in receive buffer + 0 + 12 + + + + + AMOUNT + Number of bytes received in last granted transaction + 0x008 + read-only + 0x00000000 + + + AMOUNT + Number of bytes received in the last granted transaction + 0 + 12 + + + + + LIST + EasyDMA list type + 0x00C + read-write + 0x00000000 + + + LIST + List type + 0 + 1 + + + Disabled + Disable EasyDMA list + 0x0 + + + ArrayList + Use array list + 0x1 + + + + + + + + TXD + Unspecified + SPIS_TXD + read-write + 0x544 + + PTR + TXD data pointer + 0x000 + read-write + 0x00000000 + + + PTR + TXD data pointer + 0 + 31 + + + + + MAXCNT + Maximum number of bytes in transmit buffer + 0x004 + read-write + 0x00000000 + + + MAXCNT + Maximum number of bytes in transmit buffer + 0 + 12 + + + + + AMOUNT + Number of bytes transmitted in last granted transaction + 0x008 + read-only + 0x00000000 + + + AMOUNT + Number of bytes transmitted in last granted transaction + 0 + 12 + + + + + LIST + EasyDMA list type + 0x00C + read-write + 0x00000000 + + + LIST + List type + 0 + 1 + + + Disabled + Disable EasyDMA list + 0x0 + + + ArrayList + Use array list + 0x1 + + + + + + + + CONFIG + Configuration register + 0x554 + read-write + 0x00000000 + + + ORDER + Bit order + 0 + 0 + + + MsbFirst + Most significant bit shifted out first + 0x0 + + + LsbFirst + Least significant bit shifted out first + 0x1 + + + + + CPHA + Serial clock (SCK) phase + 1 + 1 + + + Leading + Sample on leading edge of clock, shift serial data on trailing edge + 0x0 + + + Trailing + Sample on trailing edge of clock, shift serial data on leading edge + 0x1 + + + + + CPOL + Serial clock (SCK) polarity + 2 + 2 + + + ActiveHigh + Active high + 0x0 + + + ActiveLow + Active low + 0x1 + + + + + + + DEF + Default character. Character clocked out in case of an ignored transaction. + 0x55C + read-write + 0x00000000 + + + DEF + Default character. Character clocked out in case of an ignored transaction. + 0 + 7 + + + + + ORC + Over-read character + 0x5C0 + read-write + 0x00000000 + + + ORC + Over-read character. Character clocked out after an over-read of the transmit buffer. + 0 + 7 + + + + + + + TWIM0_NS + I2C compatible Two-Wire Master Interface with EasyDMA 0 + 0x40008000 + SPIM0_NS + TWIM + + + + 0 + 0x1000 + registers + + + SPIM0_SPIS0_TWIM0_TWIS0_UARTE0 + 8 + + TWIM + 0x20 + + + TASKS_STARTRX + Start TWI receive sequence + 0x000 + write-only + 0x00000000 + + + TASKS_STARTRX + Start TWI receive sequence + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_STARTTX + Start TWI transmit sequence + 0x008 + write-only + 0x00000000 + + + TASKS_STARTTX + Start TWI transmit sequence + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_STOP + Stop TWI transaction. Must be issued while the TWI master is not suspended. + 0x014 + write-only + 0x00000000 + + + TASKS_STOP + Stop TWI transaction. Must be issued while the TWI master is not suspended. + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_SUSPEND + Suspend TWI transaction + 0x01C + write-only + 0x00000000 + + + TASKS_SUSPEND + Suspend TWI transaction + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_RESUME + Resume TWI transaction + 0x020 + write-only + 0x00000000 + + + TASKS_RESUME + Resume TWI transaction + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + SUBSCRIBE_STARTRX + Subscribe configuration for task STARTRX + 0x080 + read-write + 0x00000000 + + + CHIDX + DPPI channel that task STARTRX will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_STARTTX + Subscribe configuration for task STARTTX + 0x088 + read-write + 0x00000000 + + + CHIDX + DPPI channel that task STARTTX will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_STOP + Subscribe configuration for task STOP + 0x094 + read-write + 0x00000000 + + + CHIDX + DPPI channel that task STOP will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_SUSPEND + Subscribe configuration for task SUSPEND + 0x09C + read-write + 0x00000000 + + + CHIDX + DPPI channel that task SUSPEND will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_RESUME + Subscribe configuration for task RESUME + 0x0A0 + read-write + 0x00000000 + + + CHIDX + DPPI channel that task RESUME will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + EVENTS_STOPPED + TWI stopped + 0x104 + read-write + 0x00000000 + + + EVENTS_STOPPED + TWI stopped + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_ERROR + TWI error + 0x124 + read-write + 0x00000000 + + + EVENTS_ERROR + TWI error + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_SUSPENDED + SUSPEND task has been issued, TWI traffic is now suspended. + 0x148 + read-write + 0x00000000 + + + EVENTS_SUSPENDED + SUSPEND task has been issued, TWI traffic is now suspended. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_RXSTARTED + Receive sequence started + 0x14C + read-write + 0x00000000 + + + EVENTS_RXSTARTED + Receive sequence started + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_TXSTARTED + Transmit sequence started + 0x150 + read-write + 0x00000000 + + + EVENTS_TXSTARTED + Transmit sequence started + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_LASTRX + Byte boundary, starting to receive the last byte + 0x15C + read-write + 0x00000000 + + + EVENTS_LASTRX + Byte boundary, starting to receive the last byte + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_LASTTX + Byte boundary, starting to transmit the last byte + 0x160 + read-write + 0x00000000 + + + EVENTS_LASTTX + Byte boundary, starting to transmit the last byte + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + PUBLISH_STOPPED + Publish configuration for event STOPPED + 0x184 + read-write + 0x00000000 + + + CHIDX + DPPI channel that event STOPPED will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_ERROR + Publish configuration for event ERROR + 0x1A4 + read-write + 0x00000000 + + + CHIDX + DPPI channel that event ERROR will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_SUSPENDED + Publish configuration for event SUSPENDED + 0x1C8 + read-write + 0x00000000 + + + CHIDX + DPPI channel that event SUSPENDED will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_RXSTARTED + Publish configuration for event RXSTARTED + 0x1CC + read-write + 0x00000000 + + + CHIDX + DPPI channel that event RXSTARTED will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_TXSTARTED + Publish configuration for event TXSTARTED + 0x1D0 + read-write + 0x00000000 + + + CHIDX + DPPI channel that event TXSTARTED will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_LASTRX + Publish configuration for event LASTRX + 0x1DC + read-write + 0x00000000 + + + CHIDX + DPPI channel that event LASTRX will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_LASTTX + Publish configuration for event LASTTX + 0x1E0 + read-write + 0x00000000 + + + CHIDX + DPPI channel that event LASTTX will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + 0x00000000 + + + LASTTX_STARTRX + Shortcut between event LASTTX and task STARTRX + 7 + 7 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + LASTTX_SUSPEND + Shortcut between event LASTTX and task SUSPEND + 8 + 8 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + LASTTX_STOP + Shortcut between event LASTTX and task STOP + 9 + 9 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + LASTRX_STARTTX + Shortcut between event LASTRX and task STARTTX + 10 + 10 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + LASTRX_STOP + Shortcut between event LASTRX and task STOP + 12 + 12 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + 0x00000000 + + + STOPPED + Enable or disable interrupt for event STOPPED + 1 + 1 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + ERROR + Enable or disable interrupt for event ERROR + 9 + 9 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + SUSPENDED + Enable or disable interrupt for event SUSPENDED + 18 + 18 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + RXSTARTED + Enable or disable interrupt for event RXSTARTED + 19 + 19 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TXSTARTED + Enable or disable interrupt for event TXSTARTED + 20 + 20 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + LASTRX + Enable or disable interrupt for event LASTRX + 23 + 23 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + LASTTX + Enable or disable interrupt for event LASTTX + 24 + 24 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + 0x00000000 + + + STOPPED + Write '1' to enable interrupt for event STOPPED + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + ERROR + Write '1' to enable interrupt for event ERROR + 9 + 9 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + SUSPENDED + Write '1' to enable interrupt for event SUSPENDED + 18 + 18 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + RXSTARTED + Write '1' to enable interrupt for event RXSTARTED + 19 + 19 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TXSTARTED + Write '1' to enable interrupt for event TXSTARTED + 20 + 20 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + LASTRX + Write '1' to enable interrupt for event LASTRX + 23 + 23 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + LASTTX + Write '1' to enable interrupt for event LASTTX + 24 + 24 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + 0x00000000 + + + STOPPED + Write '1' to disable interrupt for event STOPPED + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + ERROR + Write '1' to disable interrupt for event ERROR + 9 + 9 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + SUSPENDED + Write '1' to disable interrupt for event SUSPENDED + 18 + 18 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + RXSTARTED + Write '1' to disable interrupt for event RXSTARTED + 19 + 19 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TXSTARTED + Write '1' to disable interrupt for event TXSTARTED + 20 + 20 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + LASTRX + Write '1' to disable interrupt for event LASTRX + 23 + 23 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + LASTTX + Write '1' to disable interrupt for event LASTTX + 24 + 24 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + ERRORSRC + Error source + 0x4C4 + read-write + 0x00000000 + oneToClear + + + OVERRUN + Overrun error + 0 + 0 + + + NotReceived + Error did not occur + 0x0 + + + Received + Error occurred + 0x1 + + + + + ANACK + NACK received after sending the address (write '1' to clear) + 1 + 1 + + + NotReceived + Error did not occur + 0x0 + + + Received + Error occurred + 0x1 + + + + + DNACK + NACK received after sending a data byte (write '1' to clear) + 2 + 2 + + + NotReceived + Error did not occur + 0x0 + + + Received + Error occurred + 0x1 + + + + + + + ENABLE + Enable TWIM + 0x500 + read-write + 0x00000000 + + + ENABLE + Enable or disable TWIM + 0 + 3 + + + Disabled + Disable TWIM + 0x0 + + + Enabled + Enable TWIM + 0x6 + + + + + + + PSEL + Unspecified + TWIM_PSEL + read-write + 0x508 + + SCL + Pin select for SCL signal + 0x000 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 0x1 + + + Connected + Connect + 0x0 + + + + + + + SDA + Pin select for SDA signal + 0x004 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 0x1 + + + Connected + Connect + 0x0 + + + + + + + + FREQUENCY + TWI frequency. Accuracy depends on the HFCLK source selected. + 0x524 + read-write + 0x04000000 + + + FREQUENCY + TWI master clock frequency + 0 + 31 + + + K100 + 100 kbps + 0x01980000 + + + K250 + 250 kbps + 0x04000000 + + + K400 + 400 kbps + 0x06400000 + + + + + + + RXD + RXD EasyDMA channel + TWIM_RXD + read-write + 0x534 + + PTR + Data pointer + 0x000 + read-write + 0x00000000 + + + PTR + Data pointer + 0 + 31 + + + + + MAXCNT + Maximum number of bytes in receive buffer + 0x004 + read-write + 0x00000000 + + + MAXCNT + Maximum number of bytes in receive buffer + 0 + 12 + + + + + AMOUNT + Number of bytes transferred in the last transaction + 0x008 + read-only + 0x00000000 + + + AMOUNT + Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. + 0 + 12 + + + + + LIST + EasyDMA list type + 0x00C + read-write + 0x00000000 + + + LIST + List type + 0 + 1 + + + Disabled + Disable EasyDMA list + 0x0 + + + ArrayList + Use array list + 0x1 + + + + + + + + TXD + TXD EasyDMA channel + TWIM_TXD + read-write + 0x544 + + PTR + Data pointer + 0x000 + read-write + 0x00000000 + + + PTR + Data pointer + 0 + 31 + + + + + MAXCNT + Maximum number of bytes in transmit buffer + 0x004 + read-write + 0x00000000 + + + MAXCNT + Maximum number of bytes in transmit buffer + 0 + 12 + + + + + AMOUNT + Number of bytes transferred in the last transaction + 0x008 + read-only + 0x00000000 + + + AMOUNT + Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. + 0 + 12 + + + + + LIST + EasyDMA list type + 0x00C + read-write + 0x00000000 + + + LIST + List type + 0 + 1 + + + Disabled + Disable EasyDMA list + 0x0 + + + ArrayList + Use array list + 0x1 + + + + + + + + ADDRESS + Address used in the TWI transfer + 0x588 + read-write + 0x00000000 + + + ADDRESS + Address used in the TWI transfer + 0 + 6 + + + + + + + TWIS0_NS + I2C compatible Two-Wire Slave Interface with EasyDMA 0 + 0x40008000 + SPIM0_NS + TWIS + + + + 0 + 0x1000 + registers + + + SPIM0_SPIS0_TWIM0_TWIS0_UARTE0 + 8 + + TWIS + 0x20 + + + TASKS_STOP + Stop TWI transaction + 0x014 + write-only + 0x00000000 + + + TASKS_STOP + Stop TWI transaction + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_SUSPEND + Suspend TWI transaction + 0x01C + write-only + 0x00000000 + + + TASKS_SUSPEND + Suspend TWI transaction + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_RESUME + Resume TWI transaction + 0x020 + write-only + 0x00000000 + + + TASKS_RESUME + Resume TWI transaction + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_PREPARERX + Prepare the TWI slave to respond to a write command + 0x030 + write-only + 0x00000000 + + + TASKS_PREPARERX + Prepare the TWI slave to respond to a write command + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_PREPARETX + Prepare the TWI slave to respond to a read command + 0x034 + write-only + 0x00000000 + + + TASKS_PREPARETX + Prepare the TWI slave to respond to a read command + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + SUBSCRIBE_STOP + Subscribe configuration for task STOP + 0x094 + read-write + 0x00000000 + + + CHIDX + DPPI channel that task STOP will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_SUSPEND + Subscribe configuration for task SUSPEND + 0x09C + read-write + 0x00000000 + + + CHIDX + DPPI channel that task SUSPEND will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_RESUME + Subscribe configuration for task RESUME + 0x0A0 + read-write + 0x00000000 + + + CHIDX + DPPI channel that task RESUME will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_PREPARERX + Subscribe configuration for task PREPARERX + 0x0B0 + read-write + 0x00000000 + + + CHIDX + DPPI channel that task PREPARERX will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_PREPARETX + Subscribe configuration for task PREPARETX + 0x0B4 + read-write + 0x00000000 + + + CHIDX + DPPI channel that task PREPARETX will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + EVENTS_STOPPED + TWI stopped + 0x104 + read-write + 0x00000000 + + + EVENTS_STOPPED + TWI stopped + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_ERROR + TWI error + 0x124 + read-write + 0x00000000 + + + EVENTS_ERROR + TWI error + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_RXSTARTED + Receive sequence started + 0x14C + read-write + 0x00000000 + + + EVENTS_RXSTARTED + Receive sequence started + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_TXSTARTED + Transmit sequence started + 0x150 + read-write + 0x00000000 + + + EVENTS_TXSTARTED + Transmit sequence started + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_WRITE + Write command received + 0x164 + read-write + 0x00000000 + + + EVENTS_WRITE + Write command received + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_READ + Read command received + 0x168 + read-write + 0x00000000 + + + EVENTS_READ + Read command received + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + PUBLISH_STOPPED + Publish configuration for event STOPPED + 0x184 + read-write + 0x00000000 + + + CHIDX + DPPI channel that event STOPPED will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_ERROR + Publish configuration for event ERROR + 0x1A4 + read-write + 0x00000000 + + + CHIDX + DPPI channel that event ERROR will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_RXSTARTED + Publish configuration for event RXSTARTED + 0x1CC + read-write + 0x00000000 + + + CHIDX + DPPI channel that event RXSTARTED will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_TXSTARTED + Publish configuration for event TXSTARTED + 0x1D0 + read-write + 0x00000000 + + + CHIDX + DPPI channel that event TXSTARTED will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_WRITE + Publish configuration for event WRITE + 0x1E4 + read-write + 0x00000000 + + + CHIDX + DPPI channel that event WRITE will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_READ + Publish configuration for event READ + 0x1E8 + read-write + 0x00000000 + + + CHIDX + DPPI channel that event READ will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + 0x00000000 + + + WRITE_SUSPEND + Shortcut between event WRITE and task SUSPEND + 13 + 13 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + READ_SUSPEND + Shortcut between event READ and task SUSPEND + 14 + 14 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + 0x00000000 + + + STOPPED + Enable or disable interrupt for event STOPPED + 1 + 1 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + ERROR + Enable or disable interrupt for event ERROR + 9 + 9 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + RXSTARTED + Enable or disable interrupt for event RXSTARTED + 19 + 19 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TXSTARTED + Enable or disable interrupt for event TXSTARTED + 20 + 20 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + WRITE + Enable or disable interrupt for event WRITE + 25 + 25 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + READ + Enable or disable interrupt for event READ + 26 + 26 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + 0x00000000 + + + STOPPED + Write '1' to enable interrupt for event STOPPED + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + ERROR + Write '1' to enable interrupt for event ERROR + 9 + 9 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + RXSTARTED + Write '1' to enable interrupt for event RXSTARTED + 19 + 19 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TXSTARTED + Write '1' to enable interrupt for event TXSTARTED + 20 + 20 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + WRITE + Write '1' to enable interrupt for event WRITE + 25 + 25 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + READ + Write '1' to enable interrupt for event READ + 26 + 26 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + 0x00000000 + + + STOPPED + Write '1' to disable interrupt for event STOPPED + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + ERROR + Write '1' to disable interrupt for event ERROR + 9 + 9 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + RXSTARTED + Write '1' to disable interrupt for event RXSTARTED + 19 + 19 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TXSTARTED + Write '1' to disable interrupt for event TXSTARTED + 20 + 20 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + WRITE + Write '1' to disable interrupt for event WRITE + 25 + 25 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + READ + Write '1' to disable interrupt for event READ + 26 + 26 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + ERRORSRC + Error source + 0x4D0 + read-write + 0x00000000 + oneToClear + + + OVERFLOW + RX buffer overflow detected, and prevented + 0 + 0 + + + NotDetected + Error did not occur + 0x0 + + + Detected + Error occurred + 0x1 + + + + + DNACK + NACK sent after receiving a data byte + 2 + 2 + + + NotReceived + Error did not occur + 0x0 + + + Received + Error occurred + 0x1 + + + + + OVERREAD + TX buffer over-read detected, and prevented + 3 + 3 + + + NotDetected + Error did not occur + 0x0 + + + Detected + Error occurred + 0x1 + + + + + + + MATCH + Status register indicating which address had a match + 0x4D4 + read-only + 0x00000000 + + + MATCH + Indication of which address in ADDRESS that matched the incoming address + 0 + 0 + + + + + ENABLE + Enable TWIS + 0x500 + read-write + 0x00000000 + + + ENABLE + Enable or disable TWIS + 0 + 3 + + + Disabled + Disable TWIS + 0x0 + + + Enabled + Enable TWIS + 0x9 + + + + + + + PSEL + Unspecified + TWIS_PSEL + read-write + 0x508 + + SCL + Pin select for SCL signal + 0x000 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 0x1 + + + Connected + Connect + 0x0 + + + + + + + SDA + Pin select for SDA signal + 0x004 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 0x1 + + + Connected + Connect + 0x0 + + + + + + + + RXD + RXD EasyDMA channel + TWIS_RXD + read-write + 0x534 + + PTR + RXD Data pointer + 0x000 + read-write + 0x00000000 + + + PTR + RXD Data pointer + 0 + 31 + + + + + MAXCNT + Maximum number of bytes in RXD buffer + 0x004 + read-write + 0x00000000 + + + MAXCNT + Maximum number of bytes in RXD buffer + 0 + 12 + + + + + AMOUNT + Number of bytes transferred in the last RXD transaction + 0x008 + read-only + 0x00000000 + + + AMOUNT + Number of bytes transferred in the last RXD transaction + 0 + 12 + + + + + LIST + EasyDMA list type + 0x00C + read-write + 0x00000000 + + + LIST + List type + 0 + 1 + + + Disabled + Disable EasyDMA list + 0x0 + + + ArrayList + Use array list + 0x1 + + + + + + + + TXD + TXD EasyDMA channel + TWIS_TXD + read-write + 0x544 + + PTR + TXD Data pointer + 0x000 + read-write + 0x00000000 + + + PTR + TXD Data pointer + 0 + 31 + + + + + MAXCNT + Maximum number of bytes in TXD buffer + 0x004 + read-write + 0x00000000 + + + MAXCNT + Maximum number of bytes in TXD buffer + 0 + 12 + + + + + AMOUNT + Number of bytes transferred in the last TXD transaction + 0x008 + read-only + 0x00000000 + + + AMOUNT + Number of bytes transferred in the last TXD transaction + 0 + 12 + + + + + LIST + EasyDMA list type + 0x00C + read-write + 0x00000000 + + + LIST + List type + 0 + 1 + + + Disabled + Disable EasyDMA list + 0x0 + + + ArrayList + Use array list + 0x1 + + + + + + + + 0x2 + 0x4 + ADDRESS[%s] + Description collection: TWI slave address n + 0x588 + read-write + 0x00000000 + + + ADDRESS + TWI slave address + 0 + 6 + + + + + CONFIG + Configuration register for the address match mechanism + 0x594 + read-write + 0x00000001 + + + ADDRESS0 + Enable or disable address matching on ADDRESS[0] + 0 + 0 + + + Disabled + Disabled + 0x0 + + + Enabled + Enabled + 0x1 + + + + + ADDRESS1 + Enable or disable address matching on ADDRESS[1] + 1 + 1 + + + Disabled + Disabled + 0x0 + + + Enabled + Enabled + 0x1 + + + + + + + ORC + Over-read character. Character sent out in case of an over-read of the transmit buffer. + 0x5C0 + read-write + 0x00000000 + + + ORC + Over-read character. Character sent out in case of an over-read of the transmit buffer. + 0 + 7 + + + + + + + UARTE0_NS + UART with EasyDMA 0 + 0x40008000 + SPIM0_NS + UARTE + + + + 0 + 0x1000 + registers + + + SPIM0_SPIS0_TWIM0_TWIS0_UARTE0 + 8 + + UARTE + 0x20 + + + TASKS_STARTRX + Start UART receiver + 0x000 + write-only + 0x00000000 + + + TASKS_STARTRX + Start UART receiver + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_STOPRX + Stop UART receiver + 0x004 + write-only + 0x00000000 + + + TASKS_STOPRX + Stop UART receiver + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_STARTTX + Start UART transmitter + 0x008 + write-only + 0x00000000 + + + TASKS_STARTTX + Start UART transmitter + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_STOPTX + Stop UART transmitter + 0x00C + write-only + 0x00000000 + + + TASKS_STOPTX + Stop UART transmitter + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_FLUSHRX + Flush RX FIFO into RX buffer + 0x02C + write-only + 0x00000000 + + + TASKS_FLUSHRX + Flush RX FIFO into RX buffer + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + SUBSCRIBE_STARTRX + Subscribe configuration for task STARTRX + 0x080 + read-write + 0x00000000 + + + CHIDX + DPPI channel that task STARTRX will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_STOPRX + Subscribe configuration for task STOPRX + 0x084 + read-write + 0x00000000 + + + CHIDX + DPPI channel that task STOPRX will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_STARTTX + Subscribe configuration for task STARTTX + 0x088 + read-write + 0x00000000 + + + CHIDX + DPPI channel that task STARTTX will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_STOPTX + Subscribe configuration for task STOPTX + 0x08C + read-write + 0x00000000 + + + CHIDX + DPPI channel that task STOPTX will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_FLUSHRX + Subscribe configuration for task FLUSHRX + 0x0AC + read-write + 0x00000000 + + + CHIDX + DPPI channel that task FLUSHRX will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + EVENTS_CTS + CTS is activated (set low). Clear To Send. + 0x100 + read-write + 0x00000000 + + + EVENTS_CTS + CTS is activated (set low). Clear To Send. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_NCTS + CTS is deactivated (set high). Not Clear To Send. + 0x104 + read-write + 0x00000000 + + + EVENTS_NCTS + CTS is deactivated (set high). Not Clear To Send. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_RXDRDY + Data received in RXD (but potentially not yet transferred to Data RAM) + 0x108 + read-write + 0x00000000 + + + EVENTS_RXDRDY + Data received in RXD (but potentially not yet transferred to Data RAM) + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_ENDRX + Receive buffer is filled up + 0x110 + read-write + 0x00000000 + + + EVENTS_ENDRX + Receive buffer is filled up + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_TXDRDY + Data sent from TXD + 0x11C + read-write + 0x00000000 + + + EVENTS_TXDRDY + Data sent from TXD + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_ENDTX + Last TX byte transmitted + 0x120 + read-write + 0x00000000 + + + EVENTS_ENDTX + Last TX byte transmitted + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_ERROR + Error detected + 0x124 + read-write + 0x00000000 + + + EVENTS_ERROR + Error detected + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_RXTO + Receiver timeout + 0x144 + read-write + 0x00000000 + + + EVENTS_RXTO + Receiver timeout + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_RXSTARTED + UART receiver has started + 0x14C + read-write + 0x00000000 + + + EVENTS_RXSTARTED + UART receiver has started + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_TXSTARTED + UART transmitter has started + 0x150 + read-write + 0x00000000 + + + EVENTS_TXSTARTED + UART transmitter has started + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_TXSTOPPED + Transmitter stopped + 0x158 + read-write + 0x00000000 + + + EVENTS_TXSTOPPED + Transmitter stopped + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + PUBLISH_CTS + Publish configuration for event CTS + 0x180 + read-write + 0x00000000 + + + CHIDX + DPPI channel that event CTS will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_NCTS + Publish configuration for event NCTS + 0x184 + read-write + 0x00000000 + + + CHIDX + DPPI channel that event NCTS will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_RXDRDY + Publish configuration for event RXDRDY + 0x188 + read-write + 0x00000000 + + + CHIDX + DPPI channel that event RXDRDY will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_ENDRX + Publish configuration for event ENDRX + 0x190 + read-write + 0x00000000 + + + CHIDX + DPPI channel that event ENDRX will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_TXDRDY + Publish configuration for event TXDRDY + 0x19C + read-write + 0x00000000 + + + CHIDX + DPPI channel that event TXDRDY will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_ENDTX + Publish configuration for event ENDTX + 0x1A0 + read-write + 0x00000000 + + + CHIDX + DPPI channel that event ENDTX will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_ERROR + Publish configuration for event ERROR + 0x1A4 + read-write + 0x00000000 + + + CHIDX + DPPI channel that event ERROR will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_RXTO + Publish configuration for event RXTO + 0x1C4 + read-write + 0x00000000 + + + CHIDX + DPPI channel that event RXTO will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_RXSTARTED + Publish configuration for event RXSTARTED + 0x1CC + read-write + 0x00000000 + + + CHIDX + DPPI channel that event RXSTARTED will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_TXSTARTED + Publish configuration for event TXSTARTED + 0x1D0 + read-write + 0x00000000 + + + CHIDX + DPPI channel that event TXSTARTED will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_TXSTOPPED + Publish configuration for event TXSTOPPED + 0x1D8 + read-write + 0x00000000 + + + CHIDX + DPPI channel that event TXSTOPPED will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + 0x00000000 + + + ENDRX_STARTRX + Shortcut between event ENDRX and task STARTRX + 5 + 5 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + ENDRX_STOPRX + Shortcut between event ENDRX and task STOPRX + 6 + 6 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + 0x00000000 + + + CTS + Enable or disable interrupt for event CTS + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + NCTS + Enable or disable interrupt for event NCTS + 1 + 1 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + RXDRDY + Enable or disable interrupt for event RXDRDY + 2 + 2 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + ENDRX + Enable or disable interrupt for event ENDRX + 4 + 4 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TXDRDY + Enable or disable interrupt for event TXDRDY + 7 + 7 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + ENDTX + Enable or disable interrupt for event ENDTX + 8 + 8 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + ERROR + Enable or disable interrupt for event ERROR + 9 + 9 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + RXTO + Enable or disable interrupt for event RXTO + 17 + 17 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + RXSTARTED + Enable or disable interrupt for event RXSTARTED + 19 + 19 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TXSTARTED + Enable or disable interrupt for event TXSTARTED + 20 + 20 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TXSTOPPED + Enable or disable interrupt for event TXSTOPPED + 22 + 22 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + 0x00000000 + + + CTS + Write '1' to enable interrupt for event CTS + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + NCTS + Write '1' to enable interrupt for event NCTS + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + RXDRDY + Write '1' to enable interrupt for event RXDRDY + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + ENDRX + Write '1' to enable interrupt for event ENDRX + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TXDRDY + Write '1' to enable interrupt for event TXDRDY + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + ENDTX + Write '1' to enable interrupt for event ENDTX + 8 + 8 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + ERROR + Write '1' to enable interrupt for event ERROR + 9 + 9 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + RXTO + Write '1' to enable interrupt for event RXTO + 17 + 17 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + RXSTARTED + Write '1' to enable interrupt for event RXSTARTED + 19 + 19 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TXSTARTED + Write '1' to enable interrupt for event TXSTARTED + 20 + 20 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TXSTOPPED + Write '1' to enable interrupt for event TXSTOPPED + 22 + 22 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + 0x00000000 + + + CTS + Write '1' to disable interrupt for event CTS + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + NCTS + Write '1' to disable interrupt for event NCTS + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + RXDRDY + Write '1' to disable interrupt for event RXDRDY + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + ENDRX + Write '1' to disable interrupt for event ENDRX + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TXDRDY + Write '1' to disable interrupt for event TXDRDY + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + ENDTX + Write '1' to disable interrupt for event ENDTX + 8 + 8 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + ERROR + Write '1' to disable interrupt for event ERROR + 9 + 9 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + RXTO + Write '1' to disable interrupt for event RXTO + 17 + 17 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + RXSTARTED + Write '1' to disable interrupt for event RXSTARTED + 19 + 19 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TXSTARTED + Write '1' to disable interrupt for event TXSTARTED + 20 + 20 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TXSTOPPED + Write '1' to disable interrupt for event TXSTOPPED + 22 + 22 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + ERRORSRC + Error source This register is read/write one to clear. + 0x480 + read-write + 0x00000000 + oneToClear + + + OVERRUN + Overrun error + 0 + 0 + + read + + NotPresent + Read: error not present + 0x0 + + + Present + Read: error present + 0x1 + + + + + PARITY + Parity error + 1 + 1 + + read + + NotPresent + Read: error not present + 0x0 + + + Present + Read: error present + 0x1 + + + + + FRAMING + Framing error occurred + 2 + 2 + + read + + NotPresent + Read: error not present + 0x0 + + + Present + Read: error present + 0x1 + + + + + BREAK + Break condition + 3 + 3 + + read + + NotPresent + Read: error not present + 0x0 + + + Present + Read: error present + 0x1 + + + + + + + ENABLE + Enable UART + 0x500 + read-write + 0x00000000 + + + ENABLE + Enable or disable UARTE + 0 + 3 + + + Disabled + Disable UARTE + 0x0 + + + Enabled + Enable UARTE + 0x8 + + + + + + + PSEL + Unspecified + UARTE_PSEL + read-write + 0x508 + + RTS + Pin select for RTS signal + 0x000 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 0x1 + + + Connected + Connect + 0x0 + + + + + + + TXD + Pin select for TXD signal + 0x004 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 0x1 + + + Connected + Connect + 0x0 + + + + + + + CTS + Pin select for CTS signal + 0x008 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 0x1 + + + Connected + Connect + 0x0 + + + + + + + RXD + Pin select for RXD signal + 0x00C + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 0x1 + + + Connected + Connect + 0x0 + + + + + + + + BAUDRATE + Baud rate. Accuracy depends on the HFCLK source selected. + 0x524 + read-write + 0x04000000 + + + BAUDRATE + Baud rate + 0 + 31 + + + Baud1200 + 1200 baud (actual rate: 1205) + 0x0004F000 + + + Baud2400 + 2400 baud (actual rate: 2396) + 0x0009D000 + + + Baud4800 + 4800 baud (actual rate: 4808) + 0x0013B000 + + + Baud9600 + 9600 baud (actual rate: 9598) + 0x00275000 + + + Baud14400 + 14400 baud (actual rate: 14401) + 0x003AF000 + + + Baud19200 + 19200 baud (actual rate: 19208) + 0x004EA000 + + + Baud28800 + 28800 baud (actual rate: 28777) + 0x0075C000 + + + Baud31250 + 31250 baud + 0x00800000 + + + Baud38400 + 38400 baud (actual rate: 38369) + 0x009D0000 + + + Baud56000 + 56000 baud (actual rate: 55944) + 0x00E50000 + + + Baud57600 + 57600 baud (actual rate: 57554) + 0x00EB0000 + + + Baud76800 + 76800 baud (actual rate: 76923) + 0x013A9000 + + + Baud115200 + 115200 baud (actual rate: 115108) + 0x01D60000 + + + Baud230400 + 230400 baud (actual rate: 231884) + 0x03B00000 + + + Baud250000 + 250000 baud + 0x04000000 + + + Baud460800 + 460800 baud (actual rate: 457143) + 0x07400000 + + + Baud921600 + 921600 baud (actual rate: 941176) + 0x0F000000 + + + Baud1M + 1 megabaud + 0x10000000 + + + + + + + RXD + RXD EasyDMA channel + UARTE_RXD + read-write + 0x534 + + PTR + Data pointer + 0x000 + read-write + 0x00000000 + + + PTR + Data pointer + 0 + 31 + + + + + MAXCNT + Maximum number of bytes in receive buffer + 0x004 + read-write + 0x00000000 + + + MAXCNT + Maximum number of bytes in receive buffer + 0 + 12 + + + + + AMOUNT + Number of bytes transferred in the last transaction + 0x008 + read-only + 0x00000000 + + + AMOUNT + Number of bytes transferred in the last transaction + 0 + 12 + + + + + + TXD + TXD EasyDMA channel + UARTE_TXD + read-write + 0x544 + + PTR + Data pointer + 0x000 + read-write + 0x00000000 + + + PTR + Data pointer + 0 + 31 + + + + + MAXCNT + Maximum number of bytes in transmit buffer + 0x004 + read-write + 0x00000000 + + + MAXCNT + Maximum number of bytes in transmit buffer + 0 + 12 + + + + + AMOUNT + Number of bytes transferred in the last transaction + 0x008 + read-only + 0x00000000 + + + AMOUNT + Number of bytes transferred in the last transaction + 0 + 12 + + + + + + CONFIG + Configuration of parity and hardware flow control + 0x56C + read-write + 0x00000000 + + + HWFC + Hardware flow control + 0 + 0 + + + Disabled + Disabled + 0x0 + + + Enabled + Enabled + 0x1 + + + + + PARITY + Parity + 1 + 3 + + + Excluded + Exclude parity bit + 0x0 + + + Included + Include even parity bit + 0x7 + + + + + STOP + Stop bits + 4 + 4 + + + One + One stop bit + 0x0 + + + Two + Two stop bits + 0x1 + + + + + + + + + SPIM0_S + Serial Peripheral Interface Master with EasyDMA 1 + 0x50008000 + + + + SPIM0_SPIS0_TWIM0_TWIS0_UARTE0 + 8 + + + + SPIS0_S + SPI Slave 1 + 0x50008000 + SPIM0_S + + + + SPIM0_SPIS0_TWIM0_TWIS0_UARTE0 + 8 + + + + TWIM0_S + I2C compatible Two-Wire Master Interface with EasyDMA 1 + 0x50008000 + SPIM0_S + + + + SPIM0_SPIS0_TWIM0_TWIS0_UARTE0 + 8 + + + + TWIS0_S + I2C compatible Two-Wire Slave Interface with EasyDMA 1 + 0x50008000 + SPIM0_S + + + + SPIM0_SPIS0_TWIM0_TWIS0_UARTE0 + 8 + + + + UARTE0_S + UART with EasyDMA 1 + 0x50008000 + SPIM0_S + + + + SPIM0_SPIS0_TWIM0_TWIS0_UARTE0 + 8 + + + + SPIM1_NS + Serial Peripheral Interface Master with EasyDMA 2 + 0x40009000 + + + + SPIM1_SPIS1_TWIM1_TWIS1_UARTE1 + 9 + + + + SPIS1_NS + SPI Slave 2 + 0x40009000 + SPIM1_NS + + + + SPIM1_SPIS1_TWIM1_TWIS1_UARTE1 + 9 + + + + TWIM1_NS + I2C compatible Two-Wire Master Interface with EasyDMA 2 + 0x40009000 + SPIM1_NS + + + + SPIM1_SPIS1_TWIM1_TWIS1_UARTE1 + 9 + + + + TWIS1_NS + I2C compatible Two-Wire Slave Interface with EasyDMA 2 + 0x40009000 + SPIM1_NS + + + + SPIM1_SPIS1_TWIM1_TWIS1_UARTE1 + 9 + + + + UARTE1_NS + UART with EasyDMA 2 + 0x40009000 + SPIM1_NS + + + + SPIM1_SPIS1_TWIM1_TWIS1_UARTE1 + 9 + + + + SPIM1_S + Serial Peripheral Interface Master with EasyDMA 3 + 0x50009000 + + + + SPIM1_SPIS1_TWIM1_TWIS1_UARTE1 + 9 + + + + SPIS1_S + SPI Slave 3 + 0x50009000 + SPIM1_S + + + + SPIM1_SPIS1_TWIM1_TWIS1_UARTE1 + 9 + + + + TWIM1_S + I2C compatible Two-Wire Master Interface with EasyDMA 3 + 0x50009000 + SPIM1_S + + + + SPIM1_SPIS1_TWIM1_TWIS1_UARTE1 + 9 + + + + TWIS1_S + I2C compatible Two-Wire Slave Interface with EasyDMA 3 + 0x50009000 + SPIM1_S + + + + SPIM1_SPIS1_TWIM1_TWIS1_UARTE1 + 9 + + + + UARTE1_S + UART with EasyDMA 3 + 0x50009000 + SPIM1_S + + + + SPIM1_SPIS1_TWIM1_TWIS1_UARTE1 + 9 + + + + SPIM2_NS + Serial Peripheral Interface Master with EasyDMA 4 + 0x4000A000 + + + + SPIM2_SPIS2_TWIM2_TWIS2_UARTE2 + 10 + + + + SPIS2_NS + SPI Slave 4 + 0x4000A000 + SPIM2_NS + + + + SPIM2_SPIS2_TWIM2_TWIS2_UARTE2 + 10 + + + + TWIM2_NS + I2C compatible Two-Wire Master Interface with EasyDMA 4 + 0x4000A000 + SPIM2_NS + + + + SPIM2_SPIS2_TWIM2_TWIS2_UARTE2 + 10 + + + + TWIS2_NS + I2C compatible Two-Wire Slave Interface with EasyDMA 4 + 0x4000A000 + SPIM2_NS + + + + SPIM2_SPIS2_TWIM2_TWIS2_UARTE2 + 10 + + + + UARTE2_NS + UART with EasyDMA 4 + 0x4000A000 + SPIM2_NS + + + + SPIM2_SPIS2_TWIM2_TWIS2_UARTE2 + 10 + + + + SPIM2_S + Serial Peripheral Interface Master with EasyDMA 5 + 0x5000A000 + + + + SPIM2_SPIS2_TWIM2_TWIS2_UARTE2 + 10 + + + + SPIS2_S + SPI Slave 5 + 0x5000A000 + SPIM2_S + + + + SPIM2_SPIS2_TWIM2_TWIS2_UARTE2 + 10 + + + + TWIM2_S + I2C compatible Two-Wire Master Interface with EasyDMA 5 + 0x5000A000 + SPIM2_S + + + + SPIM2_SPIS2_TWIM2_TWIS2_UARTE2 + 10 + + + + TWIS2_S + I2C compatible Two-Wire Slave Interface with EasyDMA 5 + 0x5000A000 + SPIM2_S + + + + SPIM2_SPIS2_TWIM2_TWIS2_UARTE2 + 10 + + + + UARTE2_S + UART with EasyDMA 5 + 0x5000A000 + SPIM2_S + + + + SPIM2_SPIS2_TWIM2_TWIS2_UARTE2 + 10 + + + + SPIM3_NS + Serial Peripheral Interface Master with EasyDMA 6 + 0x4000B000 + + + + SPIM3_SPIS3_TWIM3_TWIS3_UARTE3 + 11 + + + + SPIS3_NS + SPI Slave 6 + 0x4000B000 + SPIM3_NS + + + + SPIM3_SPIS3_TWIM3_TWIS3_UARTE3 + 11 + + + + TWIM3_NS + I2C compatible Two-Wire Master Interface with EasyDMA 6 + 0x4000B000 + SPIM3_NS + + + + SPIM3_SPIS3_TWIM3_TWIS3_UARTE3 + 11 + + + + TWIS3_NS + I2C compatible Two-Wire Slave Interface with EasyDMA 6 + 0x4000B000 + SPIM3_NS + + + + SPIM3_SPIS3_TWIM3_TWIS3_UARTE3 + 11 + + + + UARTE3_NS + UART with EasyDMA 6 + 0x4000B000 + SPIM3_NS + + + + SPIM3_SPIS3_TWIM3_TWIS3_UARTE3 + 11 + + + + SPIM3_S + Serial Peripheral Interface Master with EasyDMA 7 + 0x5000B000 + + + + SPIM3_SPIS3_TWIM3_TWIS3_UARTE3 + 11 + + + + SPIS3_S + SPI Slave 7 + 0x5000B000 + SPIM3_S + + + + SPIM3_SPIS3_TWIM3_TWIS3_UARTE3 + 11 + + + + TWIM3_S + I2C compatible Two-Wire Master Interface with EasyDMA 7 + 0x5000B000 + SPIM3_S + + + + SPIM3_SPIS3_TWIM3_TWIS3_UARTE3 + 11 + + + + TWIS3_S + I2C compatible Two-Wire Slave Interface with EasyDMA 7 + 0x5000B000 + SPIM3_S + + + + SPIM3_SPIS3_TWIM3_TWIS3_UARTE3 + 11 + + + + UARTE3_S + UART with EasyDMA 7 + 0x5000B000 + SPIM3_S + + + + SPIM3_SPIS3_TWIM3_TWIS3_UARTE3 + 11 + + + + GPIOTE0_S + GPIO Tasks and Events 0 + 0x5000D000 + GPIOTE + + + + 0 + 0x1000 + registers + + + GPIOTE0 + 13 + + GPIOTE + 0x20 + + + 0x8 + 0x4 + TASKS_OUT[%s] + Description collection: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is configured in CONFIG[n].POLARITY. + 0x000 + write-only + 0x00000000 + + + TASKS_OUT + Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is configured in CONFIG[n].POLARITY. + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + 0x8 + 0x4 + TASKS_SET[%s] + Description collection: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it high. + 0x030 + write-only + 0x00000000 + + + TASKS_SET + Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it high. + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + 0x8 + 0x4 + TASKS_CLR[%s] + Description collection: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it low. + 0x060 + write-only + 0x00000000 + + + TASKS_CLR + Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it low. + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + 0x8 + 0x4 + SUBSCRIBE_OUT[%s] + Description collection: Subscribe configuration for task OUT[n] + 0x080 + read-write + 0x00000000 + + + CHIDX + DPPI channel that task OUT[n] will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + 0x8 + 0x4 + SUBSCRIBE_SET[%s] + Description collection: Subscribe configuration for task SET[n] + 0x0B0 + read-write + 0x00000000 + + + CHIDX + DPPI channel that task SET[n] will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + 0x8 + 0x4 + SUBSCRIBE_CLR[%s] + Description collection: Subscribe configuration for task CLR[n] + 0x0E0 + read-write + 0x00000000 + + + CHIDX + DPPI channel that task CLR[n] will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + 0x8 + 0x4 + EVENTS_IN[%s] + Description collection: Event generated from pin specified in CONFIG[n].PSEL + 0x100 + read-write + 0x00000000 + + + EVENTS_IN + Event generated from pin specified in CONFIG[n].PSEL + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_PORT + Event generated from multiple input GPIO pins with SENSE mechanism enabled + 0x17C + read-write + 0x00000000 + + + EVENTS_PORT + Event generated from multiple input GPIO pins with SENSE mechanism enabled + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + 0x8 + 0x4 + PUBLISH_IN[%s] + Description collection: Publish configuration for event IN[n] + 0x180 + read-write + 0x00000000 + + + CHIDX + DPPI channel that event IN[n] will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_PORT + Publish configuration for event PORT + 0x1FC + read-write + 0x00000000 + + + CHIDX + DPPI channel that event PORT will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + 0x00000000 + + + IN0 + Write '1' to enable interrupt for event IN[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + IN1 + Write '1' to enable interrupt for event IN[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + IN2 + Write '1' to enable interrupt for event IN[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + IN3 + Write '1' to enable interrupt for event IN[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + IN4 + Write '1' to enable interrupt for event IN[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + IN5 + Write '1' to enable interrupt for event IN[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + IN6 + Write '1' to enable interrupt for event IN[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + IN7 + Write '1' to enable interrupt for event IN[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + PORT + Write '1' to enable interrupt for event PORT + 31 + 31 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + 0x00000000 + + + IN0 + Write '1' to disable interrupt for event IN[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + IN1 + Write '1' to disable interrupt for event IN[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + IN2 + Write '1' to disable interrupt for event IN[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + IN3 + Write '1' to disable interrupt for event IN[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + IN4 + Write '1' to disable interrupt for event IN[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + IN5 + Write '1' to disable interrupt for event IN[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + IN6 + Write '1' to disable interrupt for event IN[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + IN7 + Write '1' to disable interrupt for event IN[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + PORT + Write '1' to disable interrupt for event PORT + 31 + 31 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + 0x8 + 0x4 + CONFIG[%s] + Description collection: Configuration for OUT[n], SET[n], and CLR[n] tasks and IN[n] event + 0x510 + read-write + 0x00000000 + + + MODE + Mode + 0 + 1 + + + Disabled + Disabled. Pin specified by PSEL will not be acquired by the GPIOTE module. + 0x0 + + + Event + Event mode + 0x1 + + + Task + Task mode + 0x3 + + + + + PSEL + GPIO number associated with SET[n], CLR[n], and OUT[n] tasks and IN[n] event + 8 + 12 + + + POLARITY + When In task mode: Operation to be performed on output when OUT[n] task is triggered. When In event mode: Operation on input that shall trigger IN[n] event. + 16 + 17 + + + None + Task mode: No effect on pin from OUT[n] task. Event mode: no IN[n] event generated on pin activity. + 0x0 + + + LoToHi + Task mode: Set pin from OUT[n] task. Event mode: Generate IN[n] event when rising edge on pin. + 0x1 + + + HiToLo + Task mode: Clear pin from OUT[n] task. Event mode: Generate IN[n] event when falling edge on pin. + 0x2 + + + Toggle + Task mode: Toggle pin from OUT[n]. Event mode: Generate IN[n] when any change on pin. + 0x3 + + + + + OUTINIT + When in task mode: Initial value of the output when the GPIOTE channel is configured. When in event mode: No effect. + 20 + 20 + + + Low + Task mode: Initial value of pin before task triggering is low + 0x0 + + + High + Task mode: Initial value of pin before task triggering is high + 0x1 + + + + + + + + + SAADC_NS + Analog to Digital Converter 0 + 0x4000E000 + SAADC + + + + 0 + 0x1000 + registers + + + SAADC + 14 + + SAADC + 0x20 + + + TASKS_START + Start the ADC and prepare the result buffer in RAM + 0x000 + write-only + 0x00000000 + + + TASKS_START + Start the ADC and prepare the result buffer in RAM + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_SAMPLE + Take one ADC sample, if scan is enabled all channels are sampled + 0x004 + write-only + 0x00000000 + + + TASKS_SAMPLE + Take one ADC sample, if scan is enabled all channels are sampled + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_STOP + Stop the ADC and terminate any on-going conversion + 0x008 + write-only + 0x00000000 + + + TASKS_STOP + Stop the ADC and terminate any on-going conversion + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_CALIBRATEOFFSET + Starts offset auto-calibration + 0x00C + write-only + 0x00000000 + + + TASKS_CALIBRATEOFFSET + Starts offset auto-calibration + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + SUBSCRIBE_START + Subscribe configuration for task START + 0x080 + read-write + 0x00000000 + + + CHIDX + DPPI channel that task START will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_SAMPLE + Subscribe configuration for task SAMPLE + 0x084 + read-write + 0x00000000 + + + CHIDX + DPPI channel that task SAMPLE will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_STOP + Subscribe configuration for task STOP + 0x088 + read-write + 0x00000000 + + + CHIDX + DPPI channel that task STOP will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_CALIBRATEOFFSET + Subscribe configuration for task CALIBRATEOFFSET + 0x08C + read-write + 0x00000000 + + + CHIDX + DPPI channel that task CALIBRATEOFFSET will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + EVENTS_STARTED + The ADC has started + 0x100 + read-write + 0x00000000 + + + EVENTS_STARTED + The ADC has started + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_END + The ADC has filled up the Result buffer + 0x104 + read-write + 0x00000000 + + + EVENTS_END + The ADC has filled up the Result buffer + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_DONE + A conversion task has been completed. Depending on the mode, multiple conversions might be needed for a result to be transferred to RAM. + 0x108 + read-write + 0x00000000 + + + EVENTS_DONE + A conversion task has been completed. Depending on the mode, multiple conversions might be needed for a result to be transferred to RAM. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_RESULTDONE + A result is ready to get transferred to RAM. + 0x10C + read-write + 0x00000000 + + + EVENTS_RESULTDONE + A result is ready to get transferred to RAM. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_CALIBRATEDONE + Calibration is complete + 0x110 + read-write + 0x00000000 + + + EVENTS_CALIBRATEDONE + Calibration is complete + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_STOPPED + The ADC has stopped + 0x114 + read-write + 0x00000000 + + + EVENTS_STOPPED + The ADC has stopped + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + 8 + 0x008 + EVENTS_CH[%s] + Peripheral events. + SAADC_EVENTS_CH + read-write + 0x118 + + LIMITH + Description cluster: Last results is equal or above CH[n].LIMIT.HIGH + 0x000 + read-write + 0x00000000 + + + LIMITH + Last results is equal or above CH[n].LIMIT.HIGH + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + LIMITL + Description cluster: Last results is equal or below CH[n].LIMIT.LOW + 0x004 + read-write + 0x00000000 + + + LIMITL + Last results is equal or below CH[n].LIMIT.LOW + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + + PUBLISH_STARTED + Publish configuration for event STARTED + 0x180 + read-write + 0x00000000 + + + CHIDX + DPPI channel that event STARTED will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_END + Publish configuration for event END + 0x184 + read-write + 0x00000000 + + + CHIDX + DPPI channel that event END will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_DONE + Publish configuration for event DONE + 0x188 + read-write + 0x00000000 + + + CHIDX + DPPI channel that event DONE will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_RESULTDONE + Publish configuration for event RESULTDONE + 0x18C + read-write + 0x00000000 + + + CHIDX + DPPI channel that event RESULTDONE will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_CALIBRATEDONE + Publish configuration for event CALIBRATEDONE + 0x190 + read-write + 0x00000000 + + + CHIDX + DPPI channel that event CALIBRATEDONE will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_STOPPED + Publish configuration for event STOPPED + 0x194 + read-write + 0x00000000 + + + CHIDX + DPPI channel that event STOPPED will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + 8 + 0x008 + PUBLISH_CH[%s] + Publish configuration for events + SAADC_PUBLISH_CH + read-write + 0x198 + + LIMITH + Description cluster: Publish configuration for event CH[n].LIMITH + 0x000 + read-write + 0x00000000 + + + CHIDX + DPPI channel that event CH[n].LIMITH will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + LIMITL + Description cluster: Publish configuration for event CH[n].LIMITL + 0x004 + read-write + 0x00000000 + + + CHIDX + DPPI channel that event CH[n].LIMITL will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + 0x00000000 + + + STARTED + Enable or disable interrupt for event STARTED + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + END + Enable or disable interrupt for event END + 1 + 1 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + DONE + Enable or disable interrupt for event DONE + 2 + 2 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + RESULTDONE + Enable or disable interrupt for event RESULTDONE + 3 + 3 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + CALIBRATEDONE + Enable or disable interrupt for event CALIBRATEDONE + 4 + 4 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + STOPPED + Enable or disable interrupt for event STOPPED + 5 + 5 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + CH0LIMITH + Enable or disable interrupt for event CH0LIMITH + 6 + 6 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + CH0LIMITL + Enable or disable interrupt for event CH0LIMITL + 7 + 7 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + CH1LIMITH + Enable or disable interrupt for event CH1LIMITH + 8 + 8 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + CH1LIMITL + Enable or disable interrupt for event CH1LIMITL + 9 + 9 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + CH2LIMITH + Enable or disable interrupt for event CH2LIMITH + 10 + 10 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + CH2LIMITL + Enable or disable interrupt for event CH2LIMITL + 11 + 11 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + CH3LIMITH + Enable or disable interrupt for event CH3LIMITH + 12 + 12 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + CH3LIMITL + Enable or disable interrupt for event CH3LIMITL + 13 + 13 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + CH4LIMITH + Enable or disable interrupt for event CH4LIMITH + 14 + 14 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + CH4LIMITL + Enable or disable interrupt for event CH4LIMITL + 15 + 15 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + CH5LIMITH + Enable or disable interrupt for event CH5LIMITH + 16 + 16 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + CH5LIMITL + Enable or disable interrupt for event CH5LIMITL + 17 + 17 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + CH6LIMITH + Enable or disable interrupt for event CH6LIMITH + 18 + 18 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + CH6LIMITL + Enable or disable interrupt for event CH6LIMITL + 19 + 19 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + CH7LIMITH + Enable or disable interrupt for event CH7LIMITH + 20 + 20 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + CH7LIMITL + Enable or disable interrupt for event CH7LIMITL + 21 + 21 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + 0x00000000 + + + STARTED + Write '1' to enable interrupt for event STARTED + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + END + Write '1' to enable interrupt for event END + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DONE + Write '1' to enable interrupt for event DONE + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + RESULTDONE + Write '1' to enable interrupt for event RESULTDONE + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + CALIBRATEDONE + Write '1' to enable interrupt for event CALIBRATEDONE + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + STOPPED + Write '1' to enable interrupt for event STOPPED + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + CH0LIMITH + Write '1' to enable interrupt for event CH0LIMITH + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + CH0LIMITL + Write '1' to enable interrupt for event CH0LIMITL + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + CH1LIMITH + Write '1' to enable interrupt for event CH1LIMITH + 8 + 8 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + CH1LIMITL + Write '1' to enable interrupt for event CH1LIMITL + 9 + 9 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + CH2LIMITH + Write '1' to enable interrupt for event CH2LIMITH + 10 + 10 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + CH2LIMITL + Write '1' to enable interrupt for event CH2LIMITL + 11 + 11 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + CH3LIMITH + Write '1' to enable interrupt for event CH3LIMITH + 12 + 12 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + CH3LIMITL + Write '1' to enable interrupt for event CH3LIMITL + 13 + 13 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + CH4LIMITH + Write '1' to enable interrupt for event CH4LIMITH + 14 + 14 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + CH4LIMITL + Write '1' to enable interrupt for event CH4LIMITL + 15 + 15 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + CH5LIMITH + Write '1' to enable interrupt for event CH5LIMITH + 16 + 16 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + CH5LIMITL + Write '1' to enable interrupt for event CH5LIMITL + 17 + 17 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + CH6LIMITH + Write '1' to enable interrupt for event CH6LIMITH + 18 + 18 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + CH6LIMITL + Write '1' to enable interrupt for event CH6LIMITL + 19 + 19 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + CH7LIMITH + Write '1' to enable interrupt for event CH7LIMITH + 20 + 20 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + CH7LIMITL + Write '1' to enable interrupt for event CH7LIMITL + 21 + 21 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + 0x00000000 + + + STARTED + Write '1' to disable interrupt for event STARTED + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + END + Write '1' to disable interrupt for event END + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DONE + Write '1' to disable interrupt for event DONE + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + RESULTDONE + Write '1' to disable interrupt for event RESULTDONE + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + CALIBRATEDONE + Write '1' to disable interrupt for event CALIBRATEDONE + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + STOPPED + Write '1' to disable interrupt for event STOPPED + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + CH0LIMITH + Write '1' to disable interrupt for event CH0LIMITH + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + CH0LIMITL + Write '1' to disable interrupt for event CH0LIMITL + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + CH1LIMITH + Write '1' to disable interrupt for event CH1LIMITH + 8 + 8 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + CH1LIMITL + Write '1' to disable interrupt for event CH1LIMITL + 9 + 9 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + CH2LIMITH + Write '1' to disable interrupt for event CH2LIMITH + 10 + 10 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + CH2LIMITL + Write '1' to disable interrupt for event CH2LIMITL + 11 + 11 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + CH3LIMITH + Write '1' to disable interrupt for event CH3LIMITH + 12 + 12 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + CH3LIMITL + Write '1' to disable interrupt for event CH3LIMITL + 13 + 13 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + CH4LIMITH + Write '1' to disable interrupt for event CH4LIMITH + 14 + 14 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + CH4LIMITL + Write '1' to disable interrupt for event CH4LIMITL + 15 + 15 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + CH5LIMITH + Write '1' to disable interrupt for event CH5LIMITH + 16 + 16 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + CH5LIMITL + Write '1' to disable interrupt for event CH5LIMITL + 17 + 17 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + CH6LIMITH + Write '1' to disable interrupt for event CH6LIMITH + 18 + 18 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + CH6LIMITL + Write '1' to disable interrupt for event CH6LIMITL + 19 + 19 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + CH7LIMITH + Write '1' to disable interrupt for event CH7LIMITH + 20 + 20 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + CH7LIMITL + Write '1' to disable interrupt for event CH7LIMITL + 21 + 21 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + STATUS + Status + 0x400 + read-only + 0x00000000 + + + STATUS + Status + 0 + 0 + + + Ready + ADC is ready. No on-going conversion. + 0x0 + + + Busy + ADC is busy. Single conversion in progress. + 0x1 + + + + + + + ENABLE + Enable or disable ADC + 0x500 + read-write + 0x00000000 + + + ENABLE + Enable or disable ADC + 0 + 0 + + + Disabled + Disable ADC + 0x0 + + + Enabled + Enable ADC + 0x1 + + + + + + + 8 + 0x010 + CH[%s] + Unspecified + SAADC_CH + read-write + 0x510 + + PSELP + Description cluster: Input positive pin selection for CH[n] + 0x000 + read-write + 0x00000000 + + + PSELP + Analog positive input channel + 0 + 4 + + + NC + Not connected + 0x00 + + + AnalogInput0 + AIN0 + 0x01 + + + AnalogInput1 + AIN1 + 0x02 + + + AnalogInput2 + AIN2 + 0x03 + + + AnalogInput3 + AIN3 + 0x04 + + + AnalogInput4 + AIN4 + 0x05 + + + AnalogInput5 + AIN5 + 0x06 + + + AnalogInput6 + AIN6 + 0x07 + + + AnalogInput7 + AIN7 + 0x08 + + + VDDGPIO + VDD_GPIO + 0x09 + + + + + + + PSELN + Description cluster: Input negative pin selection for CH[n] + 0x004 + read-write + 0x00000000 + + + PSELN + Analog negative input, enables differential channel + 0 + 4 + + + NC + Not connected + 0x00 + + + AnalogInput0 + AIN0 + 0x01 + + + AnalogInput1 + AIN1 + 0x02 + + + AnalogInput2 + AIN2 + 0x03 + + + AnalogInput3 + AIN3 + 0x04 + + + AnalogInput4 + AIN4 + 0x05 + + + AnalogInput5 + AIN5 + 0x06 + + + AnalogInput6 + AIN6 + 0x07 + + + AnalogInput7 + AIN7 + 0x08 + + + VDD_GPIO + VDD_GPIO + 0x09 + + + + + + + CONFIG + Description cluster: Input configuration for CH[n] + 0x008 + read-write + 0x00020000 + + + RESP + Positive channel resistor control + 0 + 1 + + + Bypass + Bypass resistor ladder + 0x0 + + + Pulldown + Pull-down to GND + 0x1 + + + Pullup + Pull-up to VDD_GPIO + 0x2 + + + VDD1_2 + Set input at VDD_GPIO/2 + 0x3 + + + + + RESN + Negative channel resistor control + 4 + 5 + + + Bypass + Bypass resistor ladder + 0x0 + + + Pulldown + Pull-down to GND + 0x1 + + + Pullup + Pull-up to VDD_GPIO + 0x2 + + + VDD1_2 + Set input at VDD_GPIO/2 + 0x3 + + + + + GAIN + Gain control + 8 + 10 + + + Gain1_6 + 1/6 + 0x0 + + + Gain1_5 + 1/5 + 0x1 + + + Gain1_4 + 1/4 + 0x2 + + + Gain1_3 + 1/3 + 0x3 + + + Gain1_2 + 1/2 + 0x4 + + + Gain1 + 1 + 0x5 + + + Gain2 + 2 + 0x6 + + + Gain4 + 4 + 0x7 + + + + + REFSEL + Reference control + 12 + 12 + + + Internal + Internal reference (0.6 V) + 0x0 + + + VDD1_4 + VDD_GPIO/4 as reference + 0x1 + + + + + TACQ + Acquisition time, the time the ADC uses to sample the input voltage + 16 + 18 + + + 3us + 3 us + 0x0 + + + 5us + 5 us + 0x1 + + + 10us + 10 us + 0x2 + + + 15us + 15 us + 0x3 + + + 20us + 20 us + 0x4 + + + 40us + 40 us + 0x5 + + + + + MODE + Enable differential mode + 20 + 20 + + + SE + Single ended, PSELN will be ignored, negative input to ADC shorted to GND + 0x0 + + + Diff + Differential + 0x1 + + + + + BURST + Enable burst mode + 24 + 24 + + + Disabled + Burst mode is disabled (normal operation) + 0x0 + + + Enabled + Burst mode is enabled. SAADC takes 2^OVERSAMPLE number of samples as fast as it can, and sends the average to Data RAM. + 0x1 + + + + + + + LIMIT + Description cluster: High/low limits for event monitoring a channel + 0x00C + read-write + 0x7FFF8000 + + + LOW + Low level limit + 0 + 15 + + + HIGH + High level limit + 16 + 31 + + + + + + RESOLUTION + Resolution configuration + 0x5F0 + read-write + 0x00000001 + + + VAL + Set the resolution + 0 + 2 + + + 8bit + 8 bit + 0x0 + + + 10bit + 10 bit + 0x1 + + + 12bit + 12 bit + 0x2 + + + 14bit + 14 bit + 0x3 + + + + + + + OVERSAMPLE + Oversampling configuration. OVERSAMPLE should not be combined with SCAN. The RESOLUTION is applied before averaging, thus for high OVERSAMPLE a higher RESOLUTION should be used. + 0x5F4 + read-write + 0x00000000 + + + OVERSAMPLE + Oversample control + 0 + 3 + + + Bypass + Bypass oversampling + 0x0 + + + Over2x + Oversample 2x + 0x1 + + + Over4x + Oversample 4x + 0x2 + + + Over8x + Oversample 8x + 0x3 + + + Over16x + Oversample 16x + 0x4 + + + Over32x + Oversample 32x + 0x5 + + + Over64x + Oversample 64x + 0x6 + + + Over128x + Oversample 128x + 0x7 + + + Over256x + Oversample 256x + 0x8 + + + + + + + SAMPLERATE + Controls normal or continuous sample rate + 0x5F8 + read-write + 0x00000000 + + + CC + Capture and compare value. Sample rate is 16 MHz/CC + 0 + 10 + + + MODE + Select mode for sample rate control + 12 + 12 + + + Task + Rate is controlled from SAMPLE task + 0x0 + + + Timers + Rate is controlled from local timer (use CC to control the rate) + 0x1 + + + + + + + RESULT + RESULT EasyDMA channel + SAADC_RESULT + read-write + 0x62C + + PTR + Data pointer + 0x000 + read-write + 0x00000000 + + + PTR + Data pointer + 0 + 31 + + + + + MAXCNT + Maximum number of buffer words to transfer + 0x004 + read-write + 0x00000000 + + + MAXCNT + Maximum number of buffer words to transfer + 0 + 14 + + + + + AMOUNT + Number of buffer words transferred since last START + 0x008 + read-only + 0x00000000 + + + AMOUNT + Number of buffer words transferred since last START. This register can be read after an END or STOPPED event. + 0 + 14 + + + + + + + + SAADC_S + Analog to Digital Converter 1 + 0x5000E000 + + + + SAADC + 14 + + + + TIMER0_NS + Timer/Counter 0 + 0x4000F000 + TIMER + + + + 0 + 0x1000 + registers + + + TIMER0 + 15 + + TIMER + 0x20 + + + TASKS_START + Start Timer + 0x000 + write-only + 0x00000000 + + + TASKS_START + Start Timer + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_STOP + Stop Timer + 0x004 + write-only + 0x00000000 + + + TASKS_STOP + Stop Timer + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_COUNT + Increment Timer (Counter mode only) + 0x008 + write-only + 0x00000000 + + + TASKS_COUNT + Increment Timer (Counter mode only) + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_CLEAR + Clear time + 0x00C + write-only + 0x00000000 + + + TASKS_CLEAR + Clear time + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_SHUTDOWN + Deprecated register - Shut down timer + 0x010 + write-only + 0x00000000 + + + TASKS_SHUTDOWN + Deprecated field - Shut down timer + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + 0x6 + 0x4 + TASKS_CAPTURE[%s] + Description collection: Capture Timer value to CC[n] register + 0x040 + write-only + 0x00000000 + + + TASKS_CAPTURE + Capture Timer value to CC[n] register + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + SUBSCRIBE_START + Subscribe configuration for task START + 0x080 + read-write + 0x00000000 + + + CHIDX + DPPI channel that task START will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_STOP + Subscribe configuration for task STOP + 0x084 + read-write + 0x00000000 + + + CHIDX + DPPI channel that task STOP will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_COUNT + Subscribe configuration for task COUNT + 0x088 + read-write + 0x00000000 + + + CHIDX + DPPI channel that task COUNT will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_CLEAR + Subscribe configuration for task CLEAR + 0x08C + read-write + 0x00000000 + + + CHIDX + DPPI channel that task CLEAR will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_SHUTDOWN + Deprecated register - Subscribe configuration for task SHUTDOWN + 0x090 + read-write + 0x00000000 + + + CHIDX + DPPI channel that task SHUTDOWN will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + 0x6 + 0x4 + SUBSCRIBE_CAPTURE[%s] + Description collection: Subscribe configuration for task CAPTURE[n] + 0x0C0 + read-write + 0x00000000 + + + CHIDX + DPPI channel that task CAPTURE[n] will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + 0x6 + 0x4 + EVENTS_COMPARE[%s] + Description collection: Compare event on CC[n] match + 0x140 + read-write + 0x00000000 + + + EVENTS_COMPARE + Compare event on CC[n] match + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + 0x6 + 0x4 + PUBLISH_COMPARE[%s] + Description collection: Publish configuration for event COMPARE[n] + 0x1C0 + read-write + 0x00000000 + + + CHIDX + DPPI channel that event COMPARE[n] will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + 0x00000000 + + + COMPARE0_CLEAR + Shortcut between event COMPARE[0] and task CLEAR + 0 + 0 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + COMPARE1_CLEAR + Shortcut between event COMPARE[1] and task CLEAR + 1 + 1 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + COMPARE2_CLEAR + Shortcut between event COMPARE[2] and task CLEAR + 2 + 2 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + COMPARE3_CLEAR + Shortcut between event COMPARE[3] and task CLEAR + 3 + 3 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + COMPARE4_CLEAR + Shortcut between event COMPARE[4] and task CLEAR + 4 + 4 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + COMPARE5_CLEAR + Shortcut between event COMPARE[5] and task CLEAR + 5 + 5 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + COMPARE0_STOP + Shortcut between event COMPARE[0] and task STOP + 8 + 8 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + COMPARE1_STOP + Shortcut between event COMPARE[1] and task STOP + 9 + 9 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + COMPARE2_STOP + Shortcut between event COMPARE[2] and task STOP + 10 + 10 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + COMPARE3_STOP + Shortcut between event COMPARE[3] and task STOP + 11 + 11 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + COMPARE4_STOP + Shortcut between event COMPARE[4] and task STOP + 12 + 12 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + COMPARE5_STOP + Shortcut between event COMPARE[5] and task STOP + 13 + 13 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + 0x00000000 + + + COMPARE0 + Write '1' to enable interrupt for event COMPARE[0] + 16 + 16 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE1 + Write '1' to enable interrupt for event COMPARE[1] + 17 + 17 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE2 + Write '1' to enable interrupt for event COMPARE[2] + 18 + 18 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE3 + Write '1' to enable interrupt for event COMPARE[3] + 19 + 19 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE4 + Write '1' to enable interrupt for event COMPARE[4] + 20 + 20 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE5 + Write '1' to enable interrupt for event COMPARE[5] + 21 + 21 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + 0x00000000 + + + COMPARE0 + Write '1' to disable interrupt for event COMPARE[0] + 16 + 16 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE1 + Write '1' to disable interrupt for event COMPARE[1] + 17 + 17 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE2 + Write '1' to disable interrupt for event COMPARE[2] + 18 + 18 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE3 + Write '1' to disable interrupt for event COMPARE[3] + 19 + 19 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE4 + Write '1' to disable interrupt for event COMPARE[4] + 20 + 20 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE5 + Write '1' to disable interrupt for event COMPARE[5] + 21 + 21 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + MODE + Timer mode selection + 0x504 + read-write + 0x00000000 + + + MODE + Timer mode + 0 + 1 + + + Timer + Select Timer mode + 0x0 + + + Counter + Deprecated enumerator - Select Counter mode + 0x1 + + + LowPowerCounter + Select Low Power Counter mode + 0x2 + + + + + + + BITMODE + Configure the number of bits used by the TIMER + 0x508 + read-write + 0x00000000 + + + BITMODE + Timer bit width + 0 + 1 + + + 16Bit + 16 bit timer bit width + 0x0 + + + 08Bit + 8 bit timer bit width + 0x1 + + + 24Bit + 24 bit timer bit width + 0x2 + + + 32Bit + 32 bit timer bit width + 0x3 + + + + + + + PRESCALER + Timer prescaler register + 0x510 + read-write + 0x00000004 + + + PRESCALER + Prescaler value + 0 + 3 + + + + + 0x6 + 0x4 + ONESHOTEN[%s] + Description collection: Enable one-shot operation for Capture/Compare channel n + 0x514 + read-write + 0x00000000 + + + ONESHOTEN + Enable one-shot operation + 0 + 0 + + + Disable + Disable one-shot operation + 0x0 + + + Enable + Enable one-shot operation + 0x1 + + + + + + + 0x6 + 0x4 + CC[%s] + Description collection: Capture/Compare register n + 0x540 + read-write + 0x00000000 + + + CC + Capture/Compare value + 0 + 31 + + + + + + + TIMER0_S + Timer/Counter 1 + 0x5000F000 + + + + TIMER0 + 15 + + + + TIMER1_NS + Timer/Counter 2 + 0x40010000 + + + + TIMER1 + 16 + + + + TIMER1_S + Timer/Counter 3 + 0x50010000 + + + + TIMER1 + 16 + + + + TIMER2_NS + Timer/Counter 4 + 0x40011000 + + + + TIMER2 + 17 + + + + TIMER2_S + Timer/Counter 5 + 0x50011000 + + + + TIMER2 + 17 + + + + RTC0_NS + Real-time counter 0 + 0x40014000 + RTC + + + + 0 + 0x1000 + registers + + + RTC0 + 20 + + RTC + 0x20 + + + TASKS_START + Start RTC counter + 0x000 + write-only + 0x00000000 + + + TASKS_START + Start RTC counter + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_STOP + Stop RTC counter + 0x004 + write-only + 0x00000000 + + + TASKS_STOP + Stop RTC counter + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_CLEAR + Clear RTC counter + 0x008 + write-only + 0x00000000 + + + TASKS_CLEAR + Clear RTC counter + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_TRIGOVRFLW + Set counter to 0xFFFFF0 + 0x00C + write-only + 0x00000000 + + + TASKS_TRIGOVRFLW + Set counter to 0xFFFFF0 + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + SUBSCRIBE_START + Subscribe configuration for task START + 0x080 + read-write + 0x00000000 + + + CHIDX + DPPI channel that task START will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_STOP + Subscribe configuration for task STOP + 0x084 + read-write + 0x00000000 + + + CHIDX + DPPI channel that task STOP will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_CLEAR + Subscribe configuration for task CLEAR + 0x088 + read-write + 0x00000000 + + + CHIDX + DPPI channel that task CLEAR will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_TRIGOVRFLW + Subscribe configuration for task TRIGOVRFLW + 0x08C + read-write + 0x00000000 + + + CHIDX + DPPI channel that task TRIGOVRFLW will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + EVENTS_TICK + Event on counter increment + 0x100 + read-write + 0x00000000 + + + EVENTS_TICK + Event on counter increment + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_OVRFLW + Event on counter overflow + 0x104 + read-write + 0x00000000 + + + EVENTS_OVRFLW + Event on counter overflow + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + 0x4 + 0x4 + EVENTS_COMPARE[%s] + Description collection: Compare event on CC[n] match + 0x140 + read-write + 0x00000000 + + + EVENTS_COMPARE + Compare event on CC[n] match + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + PUBLISH_TICK + Publish configuration for event TICK + 0x180 + read-write + 0x00000000 + + + CHIDX + DPPI channel that event TICK will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_OVRFLW + Publish configuration for event OVRFLW + 0x184 + read-write + 0x00000000 + + + CHIDX + DPPI channel that event OVRFLW will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + 0x4 + 0x4 + PUBLISH_COMPARE[%s] + Description collection: Publish configuration for event COMPARE[n] + 0x1C0 + read-write + 0x00000000 + + + CHIDX + DPPI channel that event COMPARE[n] will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + 0x00000000 + + + TICK + Write '1' to enable interrupt for event TICK + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + OVRFLW + Write '1' to enable interrupt for event OVRFLW + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE0 + Write '1' to enable interrupt for event COMPARE[0] + 16 + 16 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE1 + Write '1' to enable interrupt for event COMPARE[1] + 17 + 17 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE2 + Write '1' to enable interrupt for event COMPARE[2] + 18 + 18 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE3 + Write '1' to enable interrupt for event COMPARE[3] + 19 + 19 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + 0x00000000 + + + TICK + Write '1' to disable interrupt for event TICK + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + OVRFLW + Write '1' to disable interrupt for event OVRFLW + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE0 + Write '1' to disable interrupt for event COMPARE[0] + 16 + 16 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE1 + Write '1' to disable interrupt for event COMPARE[1] + 17 + 17 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE2 + Write '1' to disable interrupt for event COMPARE[2] + 18 + 18 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE3 + Write '1' to disable interrupt for event COMPARE[3] + 19 + 19 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + EVTEN + Enable or disable event routing + 0x340 + read-write + 0x00000000 + + + TICK + Enable or disable event routing for event TICK + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + OVRFLW + Enable or disable event routing for event OVRFLW + 1 + 1 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE0 + Enable or disable event routing for event COMPARE[0] + 16 + 16 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE1 + Enable or disable event routing for event COMPARE[1] + 17 + 17 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE2 + Enable or disable event routing for event COMPARE[2] + 18 + 18 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE3 + Enable or disable event routing for event COMPARE[3] + 19 + 19 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + EVTENSET + Enable event routing + 0x344 + read-write + 0x00000000 + + + TICK + Write '1' to enable event routing for event TICK + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + OVRFLW + Write '1' to enable event routing for event OVRFLW + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE0 + Write '1' to enable event routing for event COMPARE[0] + 16 + 16 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE1 + Write '1' to enable event routing for event COMPARE[1] + 17 + 17 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE2 + Write '1' to enable event routing for event COMPARE[2] + 18 + 18 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE3 + Write '1' to enable event routing for event COMPARE[3] + 19 + 19 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + EVTENCLR + Disable event routing + 0x348 + read-write + 0x00000000 + + + TICK + Write '1' to disable event routing for event TICK + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + OVRFLW + Write '1' to disable event routing for event OVRFLW + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE0 + Write '1' to disable event routing for event COMPARE[0] + 16 + 16 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE1 + Write '1' to disable event routing for event COMPARE[1] + 17 + 17 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE2 + Write '1' to disable event routing for event COMPARE[2] + 18 + 18 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE3 + Write '1' to disable event routing for event COMPARE[3] + 19 + 19 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + COUNTER + Current counter value + 0x504 + read-only + 0x00000000 + + + COUNTER + Counter value + 0 + 23 + + + + + PRESCALER + 12-bit prescaler for counter frequency (32768/(PRESCALER+1)). Must be written when RTC is stopped. + 0x508 + read-write + 0x00000000 + + + PRESCALER + Prescaler value + 0 + 11 + + + + + 0x4 + 0x4 + CC[%s] + Description collection: Compare register n + 0x540 + read-write + 0x00000000 + + + COMPARE + Compare value + 0 + 23 + + + + + + + RTC0_S + Real-time counter 1 + 0x50014000 + + + + RTC0 + 20 + + + + RTC1_NS + Real-time counter 2 + 0x40015000 + + + + RTC1 + 21 + + + + RTC1_S + Real-time counter 3 + 0x50015000 + + + + RTC1 + 21 + + + + DPPIC_NS + Distributed programmable peripheral interconnect controller 0 + 0x40017000 + DPPIC + + + + + 0 + 0x1000 + registers + + DPPIC + 0x20 + + + 6 + 0x008 + TASKS_CHG[%s] + Channel group tasks + DPPIC_TASKS_CHG + write-only + 0x000 + + EN + Description cluster: Enable channel group n + 0x000 + write-only + 0x00000000 + + + EN + Enable channel group n + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + DIS + Description cluster: Disable channel group n + 0x004 + write-only + 0x00000000 + + + DIS + Disable channel group n + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + + 6 + 0x008 + SUBSCRIBE_CHG[%s] + Subscribe configuration for tasks + DPPIC_SUBSCRIBE_CHG + read-write + 0x080 + + EN + Description cluster: Subscribe configuration for task CHG[n].EN + 0x000 + read-write + 0x00000000 + + + CHIDX + DPPI channel that task CHG[n].EN will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + DIS + Description cluster: Subscribe configuration for task CHG[n].DIS + 0x004 + read-write + 0x00000000 + + + CHIDX + DPPI channel that task CHG[n].DIS will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + + CHEN + Channel enable register + 0x500 + read-write + 0x00000000 + + + CH0 + Enable or disable channel 0 + 0 + 0 + + + Disabled + Disable channel + 0x0 + + + Enabled + Enable channel + 0x1 + + + + + CH1 + Enable or disable channel 1 + 1 + 1 + + + Disabled + Disable channel + 0x0 + + + Enabled + Enable channel + 0x1 + + + + + CH2 + Enable or disable channel 2 + 2 + 2 + + + Disabled + Disable channel + 0x0 + + + Enabled + Enable channel + 0x1 + + + + + CH3 + Enable or disable channel 3 + 3 + 3 + + + Disabled + Disable channel + 0x0 + + + Enabled + Enable channel + 0x1 + + + + + CH4 + Enable or disable channel 4 + 4 + 4 + + + Disabled + Disable channel + 0x0 + + + Enabled + Enable channel + 0x1 + + + + + CH5 + Enable or disable channel 5 + 5 + 5 + + + Disabled + Disable channel + 0x0 + + + Enabled + Enable channel + 0x1 + + + + + CH6 + Enable or disable channel 6 + 6 + 6 + + + Disabled + Disable channel + 0x0 + + + Enabled + Enable channel + 0x1 + + + + + CH7 + Enable or disable channel 7 + 7 + 7 + + + Disabled + Disable channel + 0x0 + + + Enabled + Enable channel + 0x1 + + + + + CH8 + Enable or disable channel 8 + 8 + 8 + + + Disabled + Disable channel + 0x0 + + + Enabled + Enable channel + 0x1 + + + + + CH9 + Enable or disable channel 9 + 9 + 9 + + + Disabled + Disable channel + 0x0 + + + Enabled + Enable channel + 0x1 + + + + + CH10 + Enable or disable channel 10 + 10 + 10 + + + Disabled + Disable channel + 0x0 + + + Enabled + Enable channel + 0x1 + + + + + CH11 + Enable or disable channel 11 + 11 + 11 + + + Disabled + Disable channel + 0x0 + + + Enabled + Enable channel + 0x1 + + + + + CH12 + Enable or disable channel 12 + 12 + 12 + + + Disabled + Disable channel + 0x0 + + + Enabled + Enable channel + 0x1 + + + + + CH13 + Enable or disable channel 13 + 13 + 13 + + + Disabled + Disable channel + 0x0 + + + Enabled + Enable channel + 0x1 + + + + + CH14 + Enable or disable channel 14 + 14 + 14 + + + Disabled + Disable channel + 0x0 + + + Enabled + Enable channel + 0x1 + + + + + CH15 + Enable or disable channel 15 + 15 + 15 + + + Disabled + Disable channel + 0x0 + + + Enabled + Enable channel + 0x1 + + + + + + + CHENSET + Channel enable set register + 0x504 + read-write + 0x00000000 + oneToSet + + + CH0 + Channel 0 enable set register. Writing 0 has no effect. + 0 + 0 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Set + Write: Enable channel + 0x1 + + + + + CH1 + Channel 1 enable set register. Writing 0 has no effect. + 1 + 1 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Set + Write: Enable channel + 0x1 + + + + + CH2 + Channel 2 enable set register. Writing 0 has no effect. + 2 + 2 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Set + Write: Enable channel + 0x1 + + + + + CH3 + Channel 3 enable set register. Writing 0 has no effect. + 3 + 3 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Set + Write: Enable channel + 0x1 + + + + + CH4 + Channel 4 enable set register. Writing 0 has no effect. + 4 + 4 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Set + Write: Enable channel + 0x1 + + + + + CH5 + Channel 5 enable set register. Writing 0 has no effect. + 5 + 5 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Set + Write: Enable channel + 0x1 + + + + + CH6 + Channel 6 enable set register. Writing 0 has no effect. + 6 + 6 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Set + Write: Enable channel + 0x1 + + + + + CH7 + Channel 7 enable set register. Writing 0 has no effect. + 7 + 7 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Set + Write: Enable channel + 0x1 + + + + + CH8 + Channel 8 enable set register. Writing 0 has no effect. + 8 + 8 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Set + Write: Enable channel + 0x1 + + + + + CH9 + Channel 9 enable set register. Writing 0 has no effect. + 9 + 9 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Set + Write: Enable channel + 0x1 + + + + + CH10 + Channel 10 enable set register. Writing 0 has no effect. + 10 + 10 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Set + Write: Enable channel + 0x1 + + + + + CH11 + Channel 11 enable set register. Writing 0 has no effect. + 11 + 11 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Set + Write: Enable channel + 0x1 + + + + + CH12 + Channel 12 enable set register. Writing 0 has no effect. + 12 + 12 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Set + Write: Enable channel + 0x1 + + + + + CH13 + Channel 13 enable set register. Writing 0 has no effect. + 13 + 13 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Set + Write: Enable channel + 0x1 + + + + + CH14 + Channel 14 enable set register. Writing 0 has no effect. + 14 + 14 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Set + Write: Enable channel + 0x1 + + + + + CH15 + Channel 15 enable set register. Writing 0 has no effect. + 15 + 15 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Set + Write: Enable channel + 0x1 + + + + + + + CHENCLR + Channel enable clear register + 0x508 + read-write + 0x00000000 + oneToClear + + + CH0 + Channel 0 enable clear register. Writing 0 has no effect. + 0 + 0 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Clear + Write: Disable channel + 0x1 + + + + + CH1 + Channel 1 enable clear register. Writing 0 has no effect. + 1 + 1 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Clear + Write: Disable channel + 0x1 + + + + + CH2 + Channel 2 enable clear register. Writing 0 has no effect. + 2 + 2 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Clear + Write: Disable channel + 0x1 + + + + + CH3 + Channel 3 enable clear register. Writing 0 has no effect. + 3 + 3 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Clear + Write: Disable channel + 0x1 + + + + + CH4 + Channel 4 enable clear register. Writing 0 has no effect. + 4 + 4 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Clear + Write: Disable channel + 0x1 + + + + + CH5 + Channel 5 enable clear register. Writing 0 has no effect. + 5 + 5 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Clear + Write: Disable channel + 0x1 + + + + + CH6 + Channel 6 enable clear register. Writing 0 has no effect. + 6 + 6 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Clear + Write: Disable channel + 0x1 + + + + + CH7 + Channel 7 enable clear register. Writing 0 has no effect. + 7 + 7 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Clear + Write: Disable channel + 0x1 + + + + + CH8 + Channel 8 enable clear register. Writing 0 has no effect. + 8 + 8 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Clear + Write: Disable channel + 0x1 + + + + + CH9 + Channel 9 enable clear register. Writing 0 has no effect. + 9 + 9 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Clear + Write: Disable channel + 0x1 + + + + + CH10 + Channel 10 enable clear register. Writing 0 has no effect. + 10 + 10 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Clear + Write: Disable channel + 0x1 + + + + + CH11 + Channel 11 enable clear register. Writing 0 has no effect. + 11 + 11 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Clear + Write: Disable channel + 0x1 + + + + + CH12 + Channel 12 enable clear register. Writing 0 has no effect. + 12 + 12 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Clear + Write: Disable channel + 0x1 + + + + + CH13 + Channel 13 enable clear register. Writing 0 has no effect. + 13 + 13 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Clear + Write: Disable channel + 0x1 + + + + + CH14 + Channel 14 enable clear register. Writing 0 has no effect. + 14 + 14 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Clear + Write: Disable channel + 0x1 + + + + + CH15 + Channel 15 enable clear register. Writing 0 has no effect. + 15 + 15 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Clear + Write: Disable channel + 0x1 + + + + + + + 0x6 + 0x4 + CHG[%s] + Description collection: Channel group n Note: Writes to this register are ignored if either SUBSCRIBE_CHG[n].EN or SUBSCRIBE_CHG[n].DIS is enabled + 0x800 + read-write + 0x00000000 + + + CH0 + Include or exclude channel 0 + 0 + 0 + + + Excluded + Exclude + 0x0 + + + Included + Include + 0x1 + + + + + CH1 + Include or exclude channel 1 + 1 + 1 + + + Excluded + Exclude + 0x0 + + + Included + Include + 0x1 + + + + + CH2 + Include or exclude channel 2 + 2 + 2 + + + Excluded + Exclude + 0x0 + + + Included + Include + 0x1 + + + + + CH3 + Include or exclude channel 3 + 3 + 3 + + + Excluded + Exclude + 0x0 + + + Included + Include + 0x1 + + + + + CH4 + Include or exclude channel 4 + 4 + 4 + + + Excluded + Exclude + 0x0 + + + Included + Include + 0x1 + + + + + CH5 + Include or exclude channel 5 + 5 + 5 + + + Excluded + Exclude + 0x0 + + + Included + Include + 0x1 + + + + + CH6 + Include or exclude channel 6 + 6 + 6 + + + Excluded + Exclude + 0x0 + + + Included + Include + 0x1 + + + + + CH7 + Include or exclude channel 7 + 7 + 7 + + + Excluded + Exclude + 0x0 + + + Included + Include + 0x1 + + + + + CH8 + Include or exclude channel 8 + 8 + 8 + + + Excluded + Exclude + 0x0 + + + Included + Include + 0x1 + + + + + CH9 + Include or exclude channel 9 + 9 + 9 + + + Excluded + Exclude + 0x0 + + + Included + Include + 0x1 + + + + + CH10 + Include or exclude channel 10 + 10 + 10 + + + Excluded + Exclude + 0x0 + + + Included + Include + 0x1 + + + + + CH11 + Include or exclude channel 11 + 11 + 11 + + + Excluded + Exclude + 0x0 + + + Included + Include + 0x1 + + + + + CH12 + Include or exclude channel 12 + 12 + 12 + + + Excluded + Exclude + 0x0 + + + Included + Include + 0x1 + + + + + CH13 + Include or exclude channel 13 + 13 + 13 + + + Excluded + Exclude + 0x0 + + + Included + Include + 0x1 + + + + + CH14 + Include or exclude channel 14 + 14 + 14 + + + Excluded + Exclude + 0x0 + + + Included + Include + 0x1 + + + + + CH15 + Include or exclude channel 15 + 15 + 15 + + + Excluded + Exclude + 0x0 + + + Included + Include + 0x1 + + + + + + + + + DPPIC_S + Distributed programmable peripheral interconnect controller 1 + 0x50017000 + + + + + + WDT_NS + Watchdog Timer 0 + 0x40018000 + WDT + + + + 0 + 0x1000 + registers + + + WDT + 24 + + WDT + 0x20 + + + TASKS_START + Start the watchdog + 0x000 + write-only + 0x00000000 + + + TASKS_START + Start the watchdog + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + SUBSCRIBE_START + Subscribe configuration for task START + 0x080 + read-write + 0x00000000 + + + CHIDX + DPPI channel that task START will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + EVENTS_TIMEOUT + Watchdog timeout + 0x100 + read-write + 0x00000000 + + + EVENTS_TIMEOUT + Watchdog timeout + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + PUBLISH_TIMEOUT + Publish configuration for event TIMEOUT + 0x180 + read-write + 0x00000000 + + + CHIDX + DPPI channel that event TIMEOUT will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + 0x00000000 + + + TIMEOUT + Write '1' to enable interrupt for event TIMEOUT + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + 0x00000000 + + + TIMEOUT + Write '1' to disable interrupt for event TIMEOUT + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + RUNSTATUS + Run status + 0x400 + read-only + 0x00000000 + + + RUNSTATUSWDT + Indicates whether or not the watchdog is running + 0 + 0 + + + NotRunning + Watchdog not running + 0x0 + + + Running + Watchdog is running + 0x1 + + + + + + + REQSTATUS + Request status + 0x404 + read-only + 0x00000001 + + + RR0 + Request status for RR[0] register + 0 + 0 + + + DisabledOrRequested + RR[0] register is not enabled, or are already requesting reload + 0x0 + + + EnabledAndUnrequested + RR[0] register is enabled, and are not yet requesting reload + 0x1 + + + + + RR1 + Request status for RR[1] register + 1 + 1 + + + DisabledOrRequested + RR[1] register is not enabled, or are already requesting reload + 0x0 + + + EnabledAndUnrequested + RR[1] register is enabled, and are not yet requesting reload + 0x1 + + + + + RR2 + Request status for RR[2] register + 2 + 2 + + + DisabledOrRequested + RR[2] register is not enabled, or are already requesting reload + 0x0 + + + EnabledAndUnrequested + RR[2] register is enabled, and are not yet requesting reload + 0x1 + + + + + RR3 + Request status for RR[3] register + 3 + 3 + + + DisabledOrRequested + RR[3] register is not enabled, or are already requesting reload + 0x0 + + + EnabledAndUnrequested + RR[3] register is enabled, and are not yet requesting reload + 0x1 + + + + + RR4 + Request status for RR[4] register + 4 + 4 + + + DisabledOrRequested + RR[4] register is not enabled, or are already requesting reload + 0x0 + + + EnabledAndUnrequested + RR[4] register is enabled, and are not yet requesting reload + 0x1 + + + + + RR5 + Request status for RR[5] register + 5 + 5 + + + DisabledOrRequested + RR[5] register is not enabled, or are already requesting reload + 0x0 + + + EnabledAndUnrequested + RR[5] register is enabled, and are not yet requesting reload + 0x1 + + + + + RR6 + Request status for RR[6] register + 6 + 6 + + + DisabledOrRequested + RR[6] register is not enabled, or are already requesting reload + 0x0 + + + EnabledAndUnrequested + RR[6] register is enabled, and are not yet requesting reload + 0x1 + + + + + RR7 + Request status for RR[7] register + 7 + 7 + + + DisabledOrRequested + RR[7] register is not enabled, or are already requesting reload + 0x0 + + + EnabledAndUnrequested + RR[7] register is enabled, and are not yet requesting reload + 0x1 + + + + + + + CRV + Counter reload value + 0x504 + read-write + 0xFFFFFFFF + + + CRV + Counter reload value in number of cycles of the 32.768 kHz clock + 0 + 31 + + + + + RREN + Enable register for reload request registers + 0x508 + read-write + 0x00000001 + + + RR0 + Enable or disable RR[0] register + 0 + 0 + + + Disabled + Disable RR[0] register + 0x0 + + + Enabled + Enable RR[0] register + 0x1 + + + + + RR1 + Enable or disable RR[1] register + 1 + 1 + + + Disabled + Disable RR[1] register + 0x0 + + + Enabled + Enable RR[1] register + 0x1 + + + + + RR2 + Enable or disable RR[2] register + 2 + 2 + + + Disabled + Disable RR[2] register + 0x0 + + + Enabled + Enable RR[2] register + 0x1 + + + + + RR3 + Enable or disable RR[3] register + 3 + 3 + + + Disabled + Disable RR[3] register + 0x0 + + + Enabled + Enable RR[3] register + 0x1 + + + + + RR4 + Enable or disable RR[4] register + 4 + 4 + + + Disabled + Disable RR[4] register + 0x0 + + + Enabled + Enable RR[4] register + 0x1 + + + + + RR5 + Enable or disable RR[5] register + 5 + 5 + + + Disabled + Disable RR[5] register + 0x0 + + + Enabled + Enable RR[5] register + 0x1 + + + + + RR6 + Enable or disable RR[6] register + 6 + 6 + + + Disabled + Disable RR[6] register + 0x0 + + + Enabled + Enable RR[6] register + 0x1 + + + + + RR7 + Enable or disable RR[7] register + 7 + 7 + + + Disabled + Disable RR[7] register + 0x0 + + + Enabled + Enable RR[7] register + 0x1 + + + + + + + CONFIG + Configuration register + 0x50C + read-write + 0x00000001 + + + SLEEP + Configure the watchdog to either be paused, or kept running, while the CPU is sleeping + 0 + 0 + + + Pause + Pause watchdog while the CPU is sleeping + 0x0 + + + Run + Keep the watchdog running while the CPU is sleeping + 0x1 + + + + + HALT + Configure the watchdog to either be paused, or kept running, while the CPU is halted by the debugger + 3 + 3 + + + Pause + Pause watchdog while the CPU is halted by the debugger + 0x0 + + + Run + Keep the watchdog running while the CPU is halted by the debugger + 0x1 + + + + + + + 0x8 + 0x4 + RR[%s] + Description collection: Reload request n + 0x600 + write-only + 0x00000000 + + + RR + Reload request register + 0 + 31 + + + Reload + Value to request a reload of the watchdog timer + 0x6E524635 + + + + + + + + + WDT_S + Watchdog Timer 1 + 0x50018000 + + + + WDT + 24 + + + + EGU0_NS + Event generator unit 0 + 0x4001B000 + EGU + + + + 0 + 0x1000 + registers + + + EGU0 + 27 + + EGU + 0x20 + + + 0x10 + 0x4 + TASKS_TRIGGER[%s] + Description collection: Trigger n for triggering the corresponding TRIGGERED[n] event + 0x000 + write-only + 0x00000000 + + + TASKS_TRIGGER + Trigger n for triggering the corresponding TRIGGERED[n] event + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + 0x10 + 0x4 + SUBSCRIBE_TRIGGER[%s] + Description collection: Subscribe configuration for task TRIGGER[n] + 0x080 + read-write + 0x00000000 + + + CHIDX + DPPI channel that task TRIGGER[n] will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + 0x10 + 0x4 + EVENTS_TRIGGERED[%s] + Description collection: Event number n generated by triggering the corresponding TRIGGER[n] task + 0x100 + read-write + 0x00000000 + + + EVENTS_TRIGGERED + Event number n generated by triggering the corresponding TRIGGER[n] task + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + 0x10 + 0x4 + PUBLISH_TRIGGERED[%s] + Description collection: Publish configuration for event TRIGGERED[n] + 0x180 + read-write + 0x00000000 + + + CHIDX + DPPI channel that event TRIGGERED[n] will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + 0x00000000 + + + TRIGGERED0 + Enable or disable interrupt for event TRIGGERED[0] + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED1 + Enable or disable interrupt for event TRIGGERED[1] + 1 + 1 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED2 + Enable or disable interrupt for event TRIGGERED[2] + 2 + 2 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED3 + Enable or disable interrupt for event TRIGGERED[3] + 3 + 3 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED4 + Enable or disable interrupt for event TRIGGERED[4] + 4 + 4 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED5 + Enable or disable interrupt for event TRIGGERED[5] + 5 + 5 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED6 + Enable or disable interrupt for event TRIGGERED[6] + 6 + 6 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED7 + Enable or disable interrupt for event TRIGGERED[7] + 7 + 7 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED8 + Enable or disable interrupt for event TRIGGERED[8] + 8 + 8 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED9 + Enable or disable interrupt for event TRIGGERED[9] + 9 + 9 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED10 + Enable or disable interrupt for event TRIGGERED[10] + 10 + 10 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED11 + Enable or disable interrupt for event TRIGGERED[11] + 11 + 11 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED12 + Enable or disable interrupt for event TRIGGERED[12] + 12 + 12 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED13 + Enable or disable interrupt for event TRIGGERED[13] + 13 + 13 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED14 + Enable or disable interrupt for event TRIGGERED[14] + 14 + 14 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED15 + Enable or disable interrupt for event TRIGGERED[15] + 15 + 15 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + 0x00000000 + + + TRIGGERED0 + Write '1' to enable interrupt for event TRIGGERED[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED1 + Write '1' to enable interrupt for event TRIGGERED[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED2 + Write '1' to enable interrupt for event TRIGGERED[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED3 + Write '1' to enable interrupt for event TRIGGERED[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED4 + Write '1' to enable interrupt for event TRIGGERED[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED5 + Write '1' to enable interrupt for event TRIGGERED[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED6 + Write '1' to enable interrupt for event TRIGGERED[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED7 + Write '1' to enable interrupt for event TRIGGERED[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED8 + Write '1' to enable interrupt for event TRIGGERED[8] + 8 + 8 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED9 + Write '1' to enable interrupt for event TRIGGERED[9] + 9 + 9 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED10 + Write '1' to enable interrupt for event TRIGGERED[10] + 10 + 10 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED11 + Write '1' to enable interrupt for event TRIGGERED[11] + 11 + 11 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED12 + Write '1' to enable interrupt for event TRIGGERED[12] + 12 + 12 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED13 + Write '1' to enable interrupt for event TRIGGERED[13] + 13 + 13 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED14 + Write '1' to enable interrupt for event TRIGGERED[14] + 14 + 14 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED15 + Write '1' to enable interrupt for event TRIGGERED[15] + 15 + 15 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + 0x00000000 + + + TRIGGERED0 + Write '1' to disable interrupt for event TRIGGERED[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED1 + Write '1' to disable interrupt for event TRIGGERED[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED2 + Write '1' to disable interrupt for event TRIGGERED[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED3 + Write '1' to disable interrupt for event TRIGGERED[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED4 + Write '1' to disable interrupt for event TRIGGERED[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED5 + Write '1' to disable interrupt for event TRIGGERED[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED6 + Write '1' to disable interrupt for event TRIGGERED[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED7 + Write '1' to disable interrupt for event TRIGGERED[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED8 + Write '1' to disable interrupt for event TRIGGERED[8] + 8 + 8 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED9 + Write '1' to disable interrupt for event TRIGGERED[9] + 9 + 9 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED10 + Write '1' to disable interrupt for event TRIGGERED[10] + 10 + 10 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED11 + Write '1' to disable interrupt for event TRIGGERED[11] + 11 + 11 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED12 + Write '1' to disable interrupt for event TRIGGERED[12] + 12 + 12 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED13 + Write '1' to disable interrupt for event TRIGGERED[13] + 13 + 13 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED14 + Write '1' to disable interrupt for event TRIGGERED[14] + 14 + 14 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED15 + Write '1' to disable interrupt for event TRIGGERED[15] + 15 + 15 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + + + EGU0_S + Event generator unit 1 + 0x5001B000 + + + + EGU0 + 27 + + + + EGU1_NS + Event generator unit 2 + 0x4001C000 + + + + EGU1 + 28 + + + + EGU1_S + Event generator unit 3 + 0x5001C000 + + + + EGU1 + 28 + + + + EGU2_NS + Event generator unit 4 + 0x4001D000 + + + + EGU2 + 29 + + + + EGU2_S + Event generator unit 5 + 0x5001D000 + + + + EGU2 + 29 + + + + EGU3_NS + Event generator unit 6 + 0x4001E000 + + + + EGU3 + 30 + + + + EGU3_S + Event generator unit 7 + 0x5001E000 + + + + EGU3 + 30 + + + + EGU4_NS + Event generator unit 8 + 0x4001F000 + + + + EGU4 + 31 + + + + EGU4_S + Event generator unit 9 + 0x5001F000 + + + + EGU4 + 31 + + + + EGU5_NS + Event generator unit 10 + 0x40020000 + + + + EGU5 + 32 + + + + EGU5_S + Event generator unit 11 + 0x50020000 + + + + EGU5 + 32 + + + + PWM0_NS + Pulse width modulation unit 0 + 0x40021000 + PWM + + + + 0 + 0x1000 + registers + + + PWM0 + 33 + + PWM + 0x20 + + + TASKS_STOP + Stops PWM pulse generation on all channels at the end of current PWM period, and stops sequence playback + 0x004 + write-only + 0x00000000 + + + TASKS_STOP + Stops PWM pulse generation on all channels at the end of current PWM period, and stops sequence playback + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + 0x2 + 0x4 + TASKS_SEQSTART[%s] + Description collection: Loads the first PWM value on all enabled channels from sequence n, and starts playing that sequence at the rate defined in SEQ[n]REFRESH and/or DECODER.MODE. Causes PWM generation to start if not running. + 0x008 + write-only + 0x00000000 + + + TASKS_SEQSTART + Loads the first PWM value on all enabled channels from sequence n, and starts playing that sequence at the rate defined in SEQ[n]REFRESH and/or DECODER.MODE. Causes PWM generation to start if not running. + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_NEXTSTEP + Steps by one value in the current sequence on all enabled channels if DECODER.MODE=NextStep. Does not cause PWM generation to start if not running. + 0x010 + write-only + 0x00000000 + + + TASKS_NEXTSTEP + Steps by one value in the current sequence on all enabled channels if DECODER.MODE=NextStep. Does not cause PWM generation to start if not running. + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + SUBSCRIBE_STOP + Subscribe configuration for task STOP + 0x084 + read-write + 0x00000000 + + + CHIDX + DPPI channel that task STOP will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + 0x2 + 0x4 + SUBSCRIBE_SEQSTART[%s] + Description collection: Subscribe configuration for task SEQSTART[n] + 0x088 + read-write + 0x00000000 + + + CHIDX + DPPI channel that task SEQSTART[n] will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_NEXTSTEP + Subscribe configuration for task NEXTSTEP + 0x090 + read-write + 0x00000000 + + + CHIDX + DPPI channel that task NEXTSTEP will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + EVENTS_STOPPED + Response to STOP task, emitted when PWM pulses are no longer generated + 0x104 + read-write + 0x00000000 + + + EVENTS_STOPPED + Response to STOP task, emitted when PWM pulses are no longer generated + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + 0x2 + 0x4 + EVENTS_SEQSTARTED[%s] + Description collection: First PWM period started on sequence n + 0x108 + read-write + 0x00000000 + + + EVENTS_SEQSTARTED + First PWM period started on sequence n + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + 0x2 + 0x4 + EVENTS_SEQEND[%s] + Description collection: Emitted at end of every sequence n, when last value from RAM has been applied to wave counter + 0x110 + read-write + 0x00000000 + + + EVENTS_SEQEND + Emitted at end of every sequence n, when last value from RAM has been applied to wave counter + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_PWMPERIODEND + Emitted at the end of each PWM period + 0x118 + read-write + 0x00000000 + + + EVENTS_PWMPERIODEND + Emitted at the end of each PWM period + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_LOOPSDONE + Concatenated sequences have been played the amount of times defined in LOOP.CNT + 0x11C + read-write + 0x00000000 + + + EVENTS_LOOPSDONE + Concatenated sequences have been played the amount of times defined in LOOP.CNT + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + PUBLISH_STOPPED + Publish configuration for event STOPPED + 0x184 + read-write + 0x00000000 + + + CHIDX + DPPI channel that event STOPPED will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + 0x2 + 0x4 + PUBLISH_SEQSTARTED[%s] + Description collection: Publish configuration for event SEQSTARTED[n] + 0x188 + read-write + 0x00000000 + + + CHIDX + DPPI channel that event SEQSTARTED[n] will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + 0x2 + 0x4 + PUBLISH_SEQEND[%s] + Description collection: Publish configuration for event SEQEND[n] + 0x190 + read-write + 0x00000000 + + + CHIDX + DPPI channel that event SEQEND[n] will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_PWMPERIODEND + Publish configuration for event PWMPERIODEND + 0x198 + read-write + 0x00000000 + + + CHIDX + DPPI channel that event PWMPERIODEND will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_LOOPSDONE + Publish configuration for event LOOPSDONE + 0x19C + read-write + 0x00000000 + + + CHIDX + DPPI channel that event LOOPSDONE will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + 0x00000000 + + + SEQEND0_STOP + Shortcut between event SEQEND[0] and task STOP + 0 + 0 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + SEQEND1_STOP + Shortcut between event SEQEND[1] and task STOP + 1 + 1 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + LOOPSDONE_SEQSTART0 + Shortcut between event LOOPSDONE and task SEQSTART[0] + 2 + 2 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + LOOPSDONE_SEQSTART1 + Shortcut between event LOOPSDONE and task SEQSTART[1] + 3 + 3 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + LOOPSDONE_STOP + Shortcut between event LOOPSDONE and task STOP + 4 + 4 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + 0x00000000 + + + STOPPED + Enable or disable interrupt for event STOPPED + 1 + 1 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + SEQSTARTED0 + Enable or disable interrupt for event SEQSTARTED[0] + 2 + 2 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + SEQSTARTED1 + Enable or disable interrupt for event SEQSTARTED[1] + 3 + 3 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + SEQEND0 + Enable or disable interrupt for event SEQEND[0] + 4 + 4 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + SEQEND1 + Enable or disable interrupt for event SEQEND[1] + 5 + 5 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + PWMPERIODEND + Enable or disable interrupt for event PWMPERIODEND + 6 + 6 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + LOOPSDONE + Enable or disable interrupt for event LOOPSDONE + 7 + 7 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + 0x00000000 + + + STOPPED + Write '1' to enable interrupt for event STOPPED + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + SEQSTARTED0 + Write '1' to enable interrupt for event SEQSTARTED[0] + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + SEQSTARTED1 + Write '1' to enable interrupt for event SEQSTARTED[1] + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + SEQEND0 + Write '1' to enable interrupt for event SEQEND[0] + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + SEQEND1 + Write '1' to enable interrupt for event SEQEND[1] + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + PWMPERIODEND + Write '1' to enable interrupt for event PWMPERIODEND + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + LOOPSDONE + Write '1' to enable interrupt for event LOOPSDONE + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + 0x00000000 + + + STOPPED + Write '1' to disable interrupt for event STOPPED + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + SEQSTARTED0 + Write '1' to disable interrupt for event SEQSTARTED[0] + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + SEQSTARTED1 + Write '1' to disable interrupt for event SEQSTARTED[1] + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + SEQEND0 + Write '1' to disable interrupt for event SEQEND[0] + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + SEQEND1 + Write '1' to disable interrupt for event SEQEND[1] + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + PWMPERIODEND + Write '1' to disable interrupt for event PWMPERIODEND + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + LOOPSDONE + Write '1' to disable interrupt for event LOOPSDONE + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + ENABLE + PWM module enable register + 0x500 + read-write + 0x00000000 + + + ENABLE + Enable or disable PWM module + 0 + 0 + + + Disabled + Disabled + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + MODE + Selects operating mode of the wave counter + 0x504 + read-write + 0x00000000 + + + UPDOWN + Selects up mode or up-and-down mode for the counter + 0 + 0 + + + Up + Up counter, edge-aligned PWM duty cycle + 0x0 + + + UpAndDown + Up and down counter, center-aligned PWM duty cycle + 0x1 + + + + + + + COUNTERTOP + Value up to which the pulse generator counter counts + 0x508 + read-write + 0x000003FF + + + COUNTERTOP + Value up to which the pulse generator counter counts. This register is ignored when DECODER.MODE=WaveForm and only values from RAM are used. + 0 + 14 + + + + + PRESCALER + Configuration for PWM_CLK + 0x50C + read-write + 0x00000000 + + + PRESCALER + Prescaler of PWM_CLK + 0 + 2 + + + DIV_1 + Divide by 1 (16 MHz) + 0x0 + + + DIV_2 + Divide by 2 (8 MHz) + 0x1 + + + DIV_4 + Divide by 4 (4 MHz) + 0x2 + + + DIV_8 + Divide by 8 (2 MHz) + 0x3 + + + DIV_16 + Divide by 16 (1 MHz) + 0x4 + + + DIV_32 + Divide by 32 (500 kHz) + 0x5 + + + DIV_64 + Divide by 64 (250 kHz) + 0x6 + + + DIV_128 + Divide by 128 (125 kHz) + 0x7 + + + + + + + DECODER + Configuration of the decoder + 0x510 + read-write + 0x00000000 + + + LOAD + How a sequence is read from RAM and spread to the compare register + 0 + 1 + + + Common + 1st half word (16-bit) used in all PWM channels 0..3 + 0x0 + + + Grouped + 1st half word (16-bit) used in channel 0..1; 2nd word in channel 2..3 + 0x1 + + + Individual + 1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th in ch.3 + 0x2 + + + WaveForm + 1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th in COUNTERTOP + 0x3 + + + + + MODE + Selects source for advancing the active sequence + 8 + 8 + + + RefreshCount + SEQ[n].REFRESH is used to determine loading internal compare registers + 0x0 + + + NextStep + NEXTSTEP task causes a new value to be loaded to internal compare registers + 0x1 + + + + + + + LOOP + Number of playbacks of a loop + 0x514 + read-write + 0x00000000 + + + CNT + Number of playbacks of pattern cycles + 0 + 15 + + + Disabled + Looping disabled (stop at the end of the sequence) + 0x0000 + + + + + + + 2 + 0x020 + SEQ[%s] + Unspecified + PWM_SEQ + read-write + 0x520 + + PTR + Description cluster: Beginning address in RAM of this sequence + 0x000 + read-write + 0x00000000 + + + PTR + Beginning address in RAM of this sequence + 0 + 31 + + + + + CNT + Description cluster: Number of values (duty cycles) in this sequence + 0x004 + read-write + 0x00000000 + + + CNT + Number of values (duty cycles) in this sequence + 0 + 14 + + + Disabled + Sequence is disabled, and shall not be started as it is empty + 0x0000 + + + + + + + REFRESH + Description cluster: Number of additional PWM periods between samples loaded into compare register + 0x008 + read-write + 0x00000001 + + + CNT + Number of additional PWM periods between samples loaded into compare register (load every REFRESH.CNT+1 PWM periods) + 0 + 23 + + + Continuous + Update every PWM period + 0x000000 + + + + + + + ENDDELAY + Description cluster: Time added after the sequence + 0x00C + read-write + 0x00000000 + + + CNT + Time added after the sequence in PWM periods + 0 + 23 + + + + + + PSEL + Unspecified + PWM_PSEL + read-write + 0x560 + + 0x4 + 0x4 + OUT[%s] + Description collection: Output pin select for PWM channel n + 0x000 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 0x1 + + + Connected + Connect + 0x0 + + + + + + + + + + PWM0_S + Pulse width modulation unit 1 + 0x50021000 + + + + PWM0 + 33 + + + + PWM1_NS + Pulse width modulation unit 2 + 0x40022000 + + + + PWM1 + 34 + + + + PWM1_S + Pulse width modulation unit 3 + 0x50022000 + + + + PWM1 + 34 + + + + PWM2_NS + Pulse width modulation unit 4 + 0x40023000 + + + + PWM2 + 35 + + + + PWM2_S + Pulse width modulation unit 5 + 0x50023000 + + + + PWM2 + 35 + + + + PWM3_NS + Pulse width modulation unit 6 + 0x40024000 + + + + PWM3 + 36 + + + + PWM3_S + Pulse width modulation unit 7 + 0x50024000 + + + + PWM3 + 36 + + + + PDM_NS + Pulse Density Modulation (Digital Microphone) Interface 0 + 0x40026000 + PDM + + + + 0 + 0x1000 + registers + + + PDM + 38 + + PDM + 0x20 + + + TASKS_START + Starts continuous PDM transfer + 0x000 + write-only + 0x00000000 + + + TASKS_START + Starts continuous PDM transfer + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_STOP + Stops PDM transfer + 0x004 + write-only + 0x00000000 + + + TASKS_STOP + Stops PDM transfer + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + SUBSCRIBE_START + Subscribe configuration for task START + 0x080 + read-write + 0x00000000 + + + CHIDX + DPPI channel that task START will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_STOP + Subscribe configuration for task STOP + 0x084 + read-write + 0x00000000 + + + CHIDX + DPPI channel that task STOP will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + EVENTS_STARTED + PDM transfer has started + 0x100 + read-write + 0x00000000 + + + EVENTS_STARTED + PDM transfer has started + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_STOPPED + PDM transfer has finished + 0x104 + read-write + 0x00000000 + + + EVENTS_STOPPED + PDM transfer has finished + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_END + The PDM has written the last sample specified by SAMPLE.MAXCNT (or the last sample after a STOP task has been received) to Data RAM + 0x108 + read-write + 0x00000000 + + + EVENTS_END + The PDM has written the last sample specified by SAMPLE.MAXCNT (or the last sample after a STOP task has been received) to Data RAM + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + PUBLISH_STARTED + Publish configuration for event STARTED + 0x180 + read-write + 0x00000000 + + + CHIDX + DPPI channel that event STARTED will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_STOPPED + Publish configuration for event STOPPED + 0x184 + read-write + 0x00000000 + + + CHIDX + DPPI channel that event STOPPED will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_END + Publish configuration for event END + 0x188 + read-write + 0x00000000 + + + CHIDX + DPPI channel that event END will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + 0x00000000 + + + STARTED + Enable or disable interrupt for event STARTED + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + STOPPED + Enable or disable interrupt for event STOPPED + 1 + 1 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + END + Enable or disable interrupt for event END + 2 + 2 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + 0x00000000 + + + STARTED + Write '1' to enable interrupt for event STARTED + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + STOPPED + Write '1' to enable interrupt for event STOPPED + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + END + Write '1' to enable interrupt for event END + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + 0x00000000 + + + STARTED + Write '1' to disable interrupt for event STARTED + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + STOPPED + Write '1' to disable interrupt for event STOPPED + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + END + Write '1' to disable interrupt for event END + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + ENABLE + PDM module enable register + 0x500 + read-write + 0x00000000 + + + ENABLE + Enable or disable PDM module + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + PDMCLKCTRL + PDM clock generator control + 0x504 + read-write + 0x08400000 + + + FREQ + PDM_CLK frequency configuration. + 0 + 31 + + + 1000K + PDM_CLK = 32 MHz / 32 = 1.000 MHz + 0x08000000 + + + Default + PDM_CLK = 32 MHz / 31 = 1.032 MHz. Nominal clock for RATIO=Ratio64. + 0x08400000 + + + 1067K + PDM_CLK = 32 MHz / 30 = 1.067 MHz + 0x08800000 + + + 1231K + PDM_CLK = 32 MHz / 26 = 1.231 MHz + 0x09800000 + + + 1280K + PDM_CLK = 32 MHz / 25 = 1.280 MHz. Nominal clock for RATIO=Ratio80. + 0x0A000000 + + + 1333K + PDM_CLK = 32 MHz / 24 = 1.333 MHz + 0x0A800000 + + + + + + + MODE + Defines the routing of the connected PDM microphones' signals + 0x508 + read-write + 0x00000000 + + + OPERATION + Mono or stereo operation + 0 + 0 + + + Stereo + Sample and store one pair (left + right) of 16-bit samples per RAM word R=[31:16]; L=[15:0] + 0x0 + + + Mono + Sample and store two successive left samples (16 bits each) per RAM word L1=[31:16]; L0=[15:0] + 0x1 + + + + + EDGE + Defines on which PDM_CLK edge left (or mono) is sampled + 1 + 1 + + + LeftFalling + Left (or mono) is sampled on falling edge of PDM_CLK + 0x0 + + + LeftRising + Left (or mono) is sampled on rising edge of PDM_CLK + 0x1 + + + + + + + GAINL + Left output gain adjustment + 0x518 + read-write + 0x00000028 + + + GAINL + Left output gain adjustment, in 0.5 dB steps, around the default module gain (see electrical parameters) 0x00 -20 dB gain adjust 0x01 -19.5 dB gain adjust (...) 0x27 -0.5 dB gain adjust 0x28 0 dB gain adjust 0x29 +0.5 dB gain adjust (...) 0x4F +19.5 dB gain adjust 0x50 +20 dB gain adjust + 0 + 6 + + + MinGain + -20 dB gain adjustment (minimum) + 0x00 + + + DefaultGain + 0 dB gain adjustment + 0x28 + + + MaxGain + +20 dB gain adjustment (maximum) + 0x50 + + + + + + + GAINR + Right output gain adjustment + 0x51C + read-write + 0x00000028 + + + GAINR + Right output gain adjustment, in 0.5 dB steps, around the default module gain (see electrical parameters) + 0 + 6 + + + MinGain + -20 dB gain adjustment (minimum) + 0x00 + + + DefaultGain + 0 dB gain adjustment + 0x28 + + + MaxGain + +20 dB gain adjustment (maximum) + 0x50 + + + + + + + RATIO + Selects the ratio between PDM_CLK and output sample rate. Change PDMCLKCTRL accordingly. + 0x520 + read-write + 0x00000000 + + + RATIO + Selects the ratio between PDM_CLK and output sample rate + 0 + 0 + + + Ratio64 + Ratio of 64 + 0x0 + + + Ratio80 + Ratio of 80 + 0x1 + + + + + + + PSEL + Unspecified + PDM_PSEL + read-write + 0x540 + + CLK + Pin number configuration for PDM CLK signal + 0x000 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 0x1 + + + Connected + Connect + 0x0 + + + + + + + DIN + Pin number configuration for PDM DIN signal + 0x004 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 0x1 + + + Connected + Connect + 0x0 + + + + + + + + SAMPLE + Unspecified + PDM_SAMPLE + read-write + 0x560 + + PTR + RAM address pointer to write samples to with EasyDMA + 0x000 + read-write + 0x00000000 + + + SAMPLEPTR + Address to write PDM samples to over DMA + 0 + 31 + + + + + MAXCNT + Number of samples to allocate memory for in EasyDMA mode + 0x004 + read-write + 0x00000000 + + + BUFFSIZE + Length of DMA RAM allocation in number of samples + 0 + 14 + + + + + + + + PDM_S + Pulse Density Modulation (Digital Microphone) Interface 1 + 0x50026000 + + + + PDM + 38 + + + + I2S_NS + Inter-IC Sound 0 + 0x40028000 + I2S + + + + 0 + 0x1000 + registers + + + I2S + 40 + + I2S + 0x20 + + + TASKS_START + Starts continuous I2S transfer. Also starts MCK generator when this is enabled. + 0x000 + write-only + 0x00000000 + + + TASKS_START + Starts continuous I2S transfer. Also starts MCK generator when this is enabled. + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_STOP + Stops I2S transfer. Also stops MCK generator. Triggering this task will cause the STOPPED event to be generated. + 0x004 + write-only + 0x00000000 + + + TASKS_STOP + Stops I2S transfer. Also stops MCK generator. Triggering this task will cause the STOPPED event to be generated. + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + SUBSCRIBE_START + Subscribe configuration for task START + 0x080 + read-write + 0x00000000 + + + CHIDX + DPPI channel that task START will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_STOP + Subscribe configuration for task STOP + 0x084 + read-write + 0x00000000 + + + CHIDX + DPPI channel that task STOP will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + EVENTS_RXPTRUPD + The RXD.PTR register has been copied to internal double-buffers. + When the I2S module is started and RX is enabled, this event will be generated for every RXTXD.MAXCNT words that are received on the SDIN pin. + 0x104 + read-write + 0x00000000 + + + EVENTS_RXPTRUPD + The RXD.PTR register has been copied to internal double-buffers. + When the I2S module is started and RX is enabled, this event will be generated for every RXTXD.MAXCNT words that are received on the SDIN pin. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_STOPPED + I2S transfer stopped. + 0x108 + read-write + 0x00000000 + + + EVENTS_STOPPED + I2S transfer stopped. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_TXPTRUPD + The TDX.PTR register has been copied to internal double-buffers. + When the I2S module is started and TX is enabled, this event will be generated for every RXTXD.MAXCNT words that are sent on the SDOUT pin. + 0x114 + read-write + 0x00000000 + + + EVENTS_TXPTRUPD + The TDX.PTR register has been copied to internal double-buffers. + When the I2S module is started and TX is enabled, this event will be generated for every RXTXD.MAXCNT words that are sent on the SDOUT pin. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + PUBLISH_RXPTRUPD + Publish configuration for event RXPTRUPD + 0x184 + read-write + 0x00000000 + + + CHIDX + DPPI channel that event RXPTRUPD will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_STOPPED + Publish configuration for event STOPPED + 0x188 + read-write + 0x00000000 + + + CHIDX + DPPI channel that event STOPPED will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_TXPTRUPD + Publish configuration for event TXPTRUPD + 0x194 + read-write + 0x00000000 + + + CHIDX + DPPI channel that event TXPTRUPD will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + 0x00000000 + + + RXPTRUPD + Enable or disable interrupt for event RXPTRUPD + 1 + 1 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + STOPPED + Enable or disable interrupt for event STOPPED + 2 + 2 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TXPTRUPD + Enable or disable interrupt for event TXPTRUPD + 5 + 5 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + 0x00000000 + + + RXPTRUPD + Write '1' to enable interrupt for event RXPTRUPD + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + STOPPED + Write '1' to enable interrupt for event STOPPED + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TXPTRUPD + Write '1' to enable interrupt for event TXPTRUPD + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + 0x00000000 + + + RXPTRUPD + Write '1' to disable interrupt for event RXPTRUPD + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + STOPPED + Write '1' to disable interrupt for event STOPPED + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TXPTRUPD + Write '1' to disable interrupt for event TXPTRUPD + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + ENABLE + Enable I2S module. + 0x500 + read-write + 0x00000000 + + + ENABLE + Enable I2S module. + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + CONFIG + Unspecified + I2S_CONFIG + read-write + 0x504 + + MODE + I2S mode. + 0x000 + read-write + 0x00000000 + + + MODE + I2S mode. + 0 + 0 + + + Master + Master mode. SCK and LRCK generated from internal master clcok (MCK) and output on pins defined by PSEL.xxx. + 0x0 + + + Slave + Slave mode. SCK and LRCK generated by external master and received on pins defined by PSEL.xxx + 0x1 + + + + + + + RXEN + Reception (RX) enable. + 0x004 + read-write + 0x00000000 + + + RXEN + Reception (RX) enable. + 0 + 0 + + + Disabled + Reception disabled and now data will be written to the RXD.PTR address. + 0x0 + + + Enabled + Reception enabled. + 0x1 + + + + + + + TXEN + Transmission (TX) enable. + 0x008 + read-write + 0x00000001 + + + TXEN + Transmission (TX) enable. + 0 + 0 + + + Disabled + Transmission disabled and now data will be read from the RXD.TXD address. + 0x0 + + + Enabled + Transmission enabled. + 0x1 + + + + + + + MCKEN + Master clock generator enable. + 0x00C + read-write + 0x00000001 + + + MCKEN + Master clock generator enable. + 0 + 0 + + + Disabled + Master clock generator disabled and PSEL.MCK not connected(available as GPIO). + 0x0 + + + Enabled + Master clock generator running and MCK output on PSEL.MCK. + 0x1 + + + + + + + MCKFREQ + Master clock generator frequency. + 0x010 + read-write + 0x20000000 + + + MCKFREQ + Master clock generator frequency. + 0 + 31 + + + 32MDIV8 + 32 MHz / 8 = 4.0 MHz + 0x20000000 + + + 32MDIV10 + 32 MHz / 10 = 3.2 MHz + 0x18000000 + + + 32MDIV11 + 32 MHz / 11 = 2.9090909 MHz + 0x16000000 + + + 32MDIV15 + 32 MHz / 15 = 2.1333333 MHz + 0x11000000 + + + 32MDIV16 + 32 MHz / 16 = 2.0 MHz + 0x10000000 + + + 32MDIV21 + 32 MHz / 21 = 1.5238095 + 0x0C000000 + + + 32MDIV23 + 32 MHz / 23 = 1.3913043 MHz + 0x0B000000 + + + 32MDIV30 + 32 MHz / 30 = 1.0666667 MHz + 0x08800000 + + + 32MDIV31 + 32 MHz / 31 = 1.0322581 MHz + 0x08400000 + + + 32MDIV32 + 32 MHz / 32 = 1.0 MHz + 0x08000000 + + + 32MDIV42 + 32 MHz / 42 = 0.7619048 MHz + 0x06000000 + + + 32MDIV63 + 32 MHz / 63 = 0.5079365 MHz + 0x04100000 + + + 32MDIV125 + 32 MHz / 125 = 0.256 MHz + 0x020C0000 + + + + + + + RATIO + MCK / LRCK ratio. + 0x014 + read-write + 0x00000006 + + + RATIO + MCK / LRCK ratio. + 0 + 3 + + + 32X + LRCK = MCK / 32 + 0x0 + + + 48X + LRCK = MCK / 48 + 0x1 + + + 64X + LRCK = MCK / 64 + 0x2 + + + 96X + LRCK = MCK / 96 + 0x3 + + + 128X + LRCK = MCK / 128 + 0x4 + + + 192X + LRCK = MCK / 192 + 0x5 + + + 256X + LRCK = MCK / 256 + 0x6 + + + 384X + LRCK = MCK / 384 + 0x7 + + + 512X + LRCK = MCK / 512 + 0x8 + + + + + + + SWIDTH + Sample width. + 0x018 + read-write + 0x00000001 + + + SWIDTH + Sample width. + 0 + 1 + + + 8Bit + 8 bit. + 0x0 + + + 16Bit + 16 bit. + 0x1 + + + 24Bit + 24 bit. + 0x2 + + + + + + + ALIGN + Alignment of sample within a frame. + 0x01C + read-write + 0x00000000 + + + ALIGN + Alignment of sample within a frame. + 0 + 0 + + + Left + Left-aligned. + 0x0 + + + Right + Right-aligned. + 0x1 + + + + + + + FORMAT + Frame format. + 0x020 + read-write + 0x00000000 + + + FORMAT + Frame format. + 0 + 0 + + + I2S + Original I2S format. + 0x0 + + + Aligned + Alternate (left- or right-aligned) format. + 0x1 + + + + + + + CHANNELS + Enable channels. + 0x024 + read-write + 0x00000000 + + + CHANNELS + Enable channels. + 0 + 1 + + + Stereo + Stereo. + 0x0 + + + Left + Left only. + 0x1 + + + Right + Right only. + 0x2 + + + + + + + + RXD + Unspecified + I2S_RXD + read-write + 0x538 + + PTR + Receive buffer RAM start address. + 0x000 + read-write + 0x00000000 + + + PTR + Receive buffer Data RAM start address. When receiving, words containing samples will be written to this address. This address is a word aligned Data RAM address. + 0 + 31 + + + + + + TXD + Unspecified + I2S_TXD + read-write + 0x540 + + PTR + Transmit buffer RAM start address. + 0x000 + read-write + 0x00000000 + + + PTR + Transmit buffer Data RAM start address. When transmitting, words containing samples will be fetched from this address. This address is a word aligned Data RAM address. + 0 + 31 + + + + + + RXTXD + Unspecified + I2S_RXTXD + read-write + 0x550 + + MAXCNT + Size of RXD and TXD buffers. + 0x000 + read-write + 0x00000000 + + + MAXCNT + Size of RXD and TXD buffers in number of 32 bit words. + 0 + 13 + + + + + + PSEL + Unspecified + I2S_PSEL + read-write + 0x560 + + MCK + Pin select for MCK signal. + 0x000 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 0x1 + + + Connected + Connect + 0x0 + + + + + + + SCK + Pin select for SCK signal. + 0x004 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 0x1 + + + Connected + Connect + 0x0 + + + + + + + LRCK + Pin select for LRCK signal. + 0x008 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 0x1 + + + Connected + Connect + 0x0 + + + + + + + SDIN + Pin select for SDIN signal. + 0x00C + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 0x1 + + + Connected + Connect + 0x0 + + + + + + + SDOUT + Pin select for SDOUT signal. + 0x010 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 0x1 + + + Connected + Connect + 0x0 + + + + + + + + + + I2S_S + Inter-IC Sound 1 + 0x50028000 + + + + I2S + 40 + + + + IPC_NS + Interprocessor communication 0 + 0x4002A000 + IPC + + + + 0 + 0x1000 + registers + + + IPC + 42 + + IPC + 0x20 + + + 0x8 + 0x4 + TASKS_SEND[%s] + Description collection: Trigger events on IPC channel enabled in SEND_CNF[n] + 0x000 + write-only + 0x00000000 + + + TASKS_SEND + Trigger events on IPC channel enabled in SEND_CNF[n] + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + 0x8 + 0x4 + SUBSCRIBE_SEND[%s] + Description collection: Subscribe configuration for task SEND[n] + 0x080 + read-write + 0x00000000 + + + CHIDX + DPPI channel that task SEND[n] will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + 0x8 + 0x4 + EVENTS_RECEIVE[%s] + Description collection: Event received on one or more of the enabled IPC channels in RECEIVE_CNF[n] + 0x100 + read-write + 0x00000000 + + + EVENTS_RECEIVE + Event received on one or more of the enabled IPC channels in RECEIVE_CNF[n] + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + 0x8 + 0x4 + PUBLISH_RECEIVE[%s] + Description collection: Publish configuration for event RECEIVE[n] + 0x180 + read-write + 0x00000000 + + + CHIDX + DPPI channel that event RECEIVE[n] will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + 0x00000000 + + + RECEIVE0 + Enable or disable interrupt for event RECEIVE[0] + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + RECEIVE1 + Enable or disable interrupt for event RECEIVE[1] + 1 + 1 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + RECEIVE2 + Enable or disable interrupt for event RECEIVE[2] + 2 + 2 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + RECEIVE3 + Enable or disable interrupt for event RECEIVE[3] + 3 + 3 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + RECEIVE4 + Enable or disable interrupt for event RECEIVE[4] + 4 + 4 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + RECEIVE5 + Enable or disable interrupt for event RECEIVE[5] + 5 + 5 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + RECEIVE6 + Enable or disable interrupt for event RECEIVE[6] + 6 + 6 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + RECEIVE7 + Enable or disable interrupt for event RECEIVE[7] + 7 + 7 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + 0x00000000 + + + RECEIVE0 + Write '1' to enable interrupt for event RECEIVE[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + RECEIVE1 + Write '1' to enable interrupt for event RECEIVE[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + RECEIVE2 + Write '1' to enable interrupt for event RECEIVE[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + RECEIVE3 + Write '1' to enable interrupt for event RECEIVE[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + RECEIVE4 + Write '1' to enable interrupt for event RECEIVE[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + RECEIVE5 + Write '1' to enable interrupt for event RECEIVE[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + RECEIVE6 + Write '1' to enable interrupt for event RECEIVE[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + RECEIVE7 + Write '1' to enable interrupt for event RECEIVE[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + 0x00000000 + + + RECEIVE0 + Write '1' to disable interrupt for event RECEIVE[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + RECEIVE1 + Write '1' to disable interrupt for event RECEIVE[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + RECEIVE2 + Write '1' to disable interrupt for event RECEIVE[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + RECEIVE3 + Write '1' to disable interrupt for event RECEIVE[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + RECEIVE4 + Write '1' to disable interrupt for event RECEIVE[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + RECEIVE5 + Write '1' to disable interrupt for event RECEIVE[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + RECEIVE6 + Write '1' to disable interrupt for event RECEIVE[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + RECEIVE7 + Write '1' to disable interrupt for event RECEIVE[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + INTPEND + Pending interrupts + 0x30C + read-only + 0x00000000 + + + RECEIVE0 + Read pending status of interrupt for event RECEIVE[0] + 0 + 0 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + RECEIVE1 + Read pending status of interrupt for event RECEIVE[1] + 1 + 1 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + RECEIVE2 + Read pending status of interrupt for event RECEIVE[2] + 2 + 2 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + RECEIVE3 + Read pending status of interrupt for event RECEIVE[3] + 3 + 3 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + RECEIVE4 + Read pending status of interrupt for event RECEIVE[4] + 4 + 4 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + RECEIVE5 + Read pending status of interrupt for event RECEIVE[5] + 5 + 5 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + RECEIVE6 + Read pending status of interrupt for event RECEIVE[6] + 6 + 6 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + RECEIVE7 + Read pending status of interrupt for event RECEIVE[7] + 7 + 7 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + + + 0x8 + 0x4 + SEND_CNF[%s] + Description collection: Send event configuration for TASKS_SEND[n] + 0x510 + read-write + 0x00000000 + + + CHEN0 + Enable broadcasting on IPC channel 0 + 0 + 0 + + + Disable + Disable broadcast + 0x0 + + + Enable + Enable broadcast + 0x1 + + + + + CHEN1 + Enable broadcasting on IPC channel 1 + 1 + 1 + + + Disable + Disable broadcast + 0x0 + + + Enable + Enable broadcast + 0x1 + + + + + CHEN2 + Enable broadcasting on IPC channel 2 + 2 + 2 + + + Disable + Disable broadcast + 0x0 + + + Enable + Enable broadcast + 0x1 + + + + + CHEN3 + Enable broadcasting on IPC channel 3 + 3 + 3 + + + Disable + Disable broadcast + 0x0 + + + Enable + Enable broadcast + 0x1 + + + + + CHEN4 + Enable broadcasting on IPC channel 4 + 4 + 4 + + + Disable + Disable broadcast + 0x0 + + + Enable + Enable broadcast + 0x1 + + + + + CHEN5 + Enable broadcasting on IPC channel 5 + 5 + 5 + + + Disable + Disable broadcast + 0x0 + + + Enable + Enable broadcast + 0x1 + + + + + CHEN6 + Enable broadcasting on IPC channel 6 + 6 + 6 + + + Disable + Disable broadcast + 0x0 + + + Enable + Enable broadcast + 0x1 + + + + + CHEN7 + Enable broadcasting on IPC channel 7 + 7 + 7 + + + Disable + Disable broadcast + 0x0 + + + Enable + Enable broadcast + 0x1 + + + + + + + 0x8 + 0x4 + RECEIVE_CNF[%s] + Description collection: Receive event configuration for EVENTS_RECEIVE[n] + 0x590 + read-write + 0x00000000 + + + CHEN0 + Enable subscription to IPC channel 0 + 0 + 0 + + + Disable + Disable events + 0x0 + + + Enable + Enable events + 0x1 + + + + + CHEN1 + Enable subscription to IPC channel 1 + 1 + 1 + + + Disable + Disable events + 0x0 + + + Enable + Enable events + 0x1 + + + + + CHEN2 + Enable subscription to IPC channel 2 + 2 + 2 + + + Disable + Disable events + 0x0 + + + Enable + Enable events + 0x1 + + + + + CHEN3 + Enable subscription to IPC channel 3 + 3 + 3 + + + Disable + Disable events + 0x0 + + + Enable + Enable events + 0x1 + + + + + CHEN4 + Enable subscription to IPC channel 4 + 4 + 4 + + + Disable + Disable events + 0x0 + + + Enable + Enable events + 0x1 + + + + + CHEN5 + Enable subscription to IPC channel 5 + 5 + 5 + + + Disable + Disable events + 0x0 + + + Enable + Enable events + 0x1 + + + + + CHEN6 + Enable subscription to IPC channel 6 + 6 + 6 + + + Disable + Disable events + 0x0 + + + Enable + Enable events + 0x1 + + + + + CHEN7 + Enable subscription to IPC channel 7 + 7 + 7 + + + Disable + Disable events + 0x0 + + + Enable + Enable events + 0x1 + + + + + + + 0x4 + 0x4 + GPMEM[%s] + Description collection: General purpose memory + 0x610 + read-write + 0x00000000 + + + GPMEM + General purpose memory + 0 + 31 + + + + + + + IPC_S + Interprocessor communication 1 + 0x5002A000 + + + + IPC + 42 + + + + FPU_NS + FPU + 0x4002C000 + FPU + + + + 0 + 0x1000 + registers + + + FPU + 44 + + FPU + 0x20 + + + UNUSED + Unused. + 0x000 + 0x00000000 + read-only + + + + + GPIOTE1_NS + GPIO Tasks and Events 1 + 0x40031000 + + + + GPIOTE1 + 49 + + + + APPROTECT_NS + Access Port Protection 0 + 0x40039000 + APPROTECT + + + + + 0 + 0x1000 + registers + + APPROTECT + 0x20 + + + SECUREAPPROTECT + Unspecified + APPROTECT_SECUREAPPROTECT + read-write + 0xE00 + + DISABLE + Software disable SECUREAPPROTECT mechanism + 0x000 + read-write + 0x00000001 + + + + DISABLE + Software disable SECUREAPPROTECT mechanism + 0 + 7 + + + SwUnprotected + Software disable SECUREAPPROTECT mechanism + 0x5A + + + + + + + FORCEPROTECT + Software force SECUREAPPROTECT mechanism + 0x000 + read-write + 0x00000001 + DISABLE + + + + FORCEPROTECT + Write 0x1 to force enable SECUREAPPROTECT mechanism + 9 + 9 + oneToSet + + write + + Force + Software force enable SECUREAPPROTECT mechanism + 0x1 + + + + + + + + APPROTECT + Unspecified + APPROTECT_APPROTECT + read-write + 0xE10 + + DISABLE + Software disable APPROTECT mechanism + 0x000 + read-write + 0x00000001 + + + + DISABLE + Software disable APPROTECT mechanism + 0 + 7 + + + SwUnprotected + Software disable APPROTECT mechanism + 0x5A + + + + + + + FORCEPROTECT + Software force APPROTECT mechanism + 0x000 + read-write + 0x00000001 + DISABLE + + + + FORCEPROTECT + Write 0x1 to force enable APPROTECT mechanism + 9 + 9 + oneToSet + + write + + Force + Software force enable APPROTECT mechanism + 0x1 + + + + + + + + + + KMU_NS + Key management unit 0 + 0x40039000 + APPROTECT_NS + KMU + + + + + 0 + 0x1000 + registers + + + KMU + 57 + + KMU + 0x20 + + + TASKS_PUSH_KEYSLOT + Push a key slot over secure APB + 0x0000 + write-only + 0x00000000 + + + TASKS_PUSH_KEYSLOT + Push a key slot over secure APB + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + EVENTS_KEYSLOT_PUSHED + Key slot successfully pushed over secure APB + 0x100 + read-write + 0x00000000 + + + EVENTS_KEYSLOT_PUSHED + Key slot successfully pushed over secure APB + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_KEYSLOT_REVOKED + Key slot has been revoked and cannot be tasked for selection + 0x104 + read-write + 0x00000000 + + + EVENTS_KEYSLOT_REVOKED + Key slot has been revoked and cannot be tasked for selection + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_KEYSLOT_ERROR + No key slot selected, no destination address defined, or error during push operation + 0x108 + read-write + 0x00000000 + + + EVENTS_KEYSLOT_ERROR + No key slot selected, no destination address defined, or error during push operation + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + 0x00000000 + + + KEYSLOT_PUSHED + Enable or disable interrupt for event KEYSLOT_PUSHED + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + KEYSLOT_REVOKED + Enable or disable interrupt for event KEYSLOT_REVOKED + 1 + 1 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + KEYSLOT_ERROR + Enable or disable interrupt for event KEYSLOT_ERROR + 2 + 2 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + 0x00000000 + + + KEYSLOT_PUSHED + Write '1' to enable interrupt for event KEYSLOT_PUSHED + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + KEYSLOT_REVOKED + Write '1' to enable interrupt for event KEYSLOT_REVOKED + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + KEYSLOT_ERROR + Write '1' to enable interrupt for event KEYSLOT_ERROR + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + 0x00000000 + + + KEYSLOT_PUSHED + Write '1' to disable interrupt for event KEYSLOT_PUSHED + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + KEYSLOT_REVOKED + Write '1' to disable interrupt for event KEYSLOT_REVOKED + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + KEYSLOT_ERROR + Write '1' to disable interrupt for event KEYSLOT_ERROR + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + INTPEND + Pending interrupts + 0x30C + read-only + 0x00000000 + + + KEYSLOT_PUSHED + Read pending status of interrupt for event KEYSLOT_PUSHED + 0 + 0 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + KEYSLOT_REVOKED + Read pending status of interrupt for event KEYSLOT_REVOKED + 1 + 1 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + KEYSLOT_ERROR + Read pending status of interrupt for event KEYSLOT_ERROR + 2 + 2 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + + + STATUS + Status bits for KMU operation + 0x40C + read-only + 0x00000000 + + + SELECTED + Key slot ID successfully selected by the KMU + 0 + 0 + + + Disabled + No key slot ID selected by KMU + 0x0 + + + Enabled + Key slot ID successfully selected by KMU + 0x1 + + + + + BLOCKED + Violation status + 1 + 1 + + + Disabled + No access violation detected + 0x0 + + + Enabled + Access violation detected and blocked + 0x1 + + + + + + + SELECTKEYSLOT + Select key slot to be read over AHB or pushed over secure APB when TASKS_PUSH_KEYSLOT is started + 0x500 + read-write + 0x00000000 + + + ID + Select key slot ID to be read over AHB, or pushed over secure APB, when TASKS_PUSH_KEYSLOT is started. NOTE: ID=0 is not a valid key slot ID. The 0 ID should be used when the KMU is idle or not in use. NOTE: Index N in UICR-&gt;KEYSLOT.KEY[N] and UICR-&gt;KEYSLOT.CONFIG[N] corresponds to KMU key slot ID=N+1. + 0 + 7 + + + + + + + NVMC_NS + Non-volatile memory controller 0 + 0x40039000 + APPROTECT_NS + NVMC + + + + + 0 + 0x1000 + registers + + NVMC + 0x20 + + + READY + Ready flag + 0x400 + read-only + 0x00000001 + + + + READY + NVMC is ready or busy + 0 + 0 + + + Busy + NVMC is busy (on-going write or erase operation) + 0x0 + + + Ready + NVMC is ready + 0x1 + + + + + + + READYNEXT + Ready flag + 0x408 + read-only + 0x00000001 + + + + READYNEXT + NVMC can accept a new write operation + 0 + 0 + + + Busy + NVMC cannot accept any write operation + 0x0 + + + Ready + NVMC is ready + 0x1 + + + + + + + CONFIG + Configuration register + 0x504 + read-write + 0x00000000 + + + + WEN + Program memory access mode. It is strongly recommended to only activate erase and write modes when they are actively used. Enabling write or erase will invalidate the cache and keep it invalidated. + 0 + 2 + + + Ren + Read only access + 0x0 + + + Wen + Write enabled + 0x1 + + + Een + Erase enabled + 0x2 + + + PEen + Partial erase enabled + 0x4 + + + + + + + ERASEALL + Register for erasing all non-volatile user memory + 0x50C + write-only + 0x00000000 + + + + ERASEALL + Erase all non-volatile memory including UICR registers. Note that erasing must be enabled by setting CONFIG.WEN = Een before the non-volatile memory can be erased. + 0 + 0 + + + NoOperation + No operation + 0x0 + + + Erase + Start chip erase + 0x1 + + + + + + + ERASEPAGEPARTIALCFG + Register for partial erase configuration + 0x51C + read-write + 0x0000000A + + + + DURATION + Duration of the partial erase in milliseconds + 0 + 6 + + + + + ICACHECNF + I-code cache configuration register + 0x540 + read-write + 0x00000000 + + + + CACHEEN + Cache enable + 0 + 0 + + + Disabled + Disable cache. Invalidates all cache entries. + 0x0 + + + Enabled + Enable cache + 0x1 + + + + + CACHEPROFEN + Cache profiling enable + 8 + 8 + + + Disabled + Disable cache profiling + 0x0 + + + Enabled + Enable cache profiling + 0x1 + + + + + + + IHIT + I-code cache hit counter + 0x548 + read-write + 0x00000000 + + + + HITS + Number of cache hits Write zero to clear + 0 + 31 + + + + + IMISS + I-code cache miss counter + 0x54C + read-write + 0x00000000 + + + + MISSES + Number of cache misses Write zero to clear + 0 + 31 + + + + + CONFIGNS + Unspecified + 0x584 + read-write + 0x00000000 + + + + WEN + Program memory access mode. It is strongly recommended to only activate erase and write modes when they are actively used. Enabling write or erase will invalidate the cache and keep it invalidated. + 0 + 1 + + + Ren + Read only access + 0x0 + + + Wen + Write enabled + 0x1 + + + Een + Erase enabled + 0x2 + + + + + + + WRITEUICRNS + Non-secure APPROTECT enable register + 0x588 + write-only + 0x00000000 + + + + SET + Allow non-secure code to set APPROTECT + 0 + 0 + + + Set + Set value + 0x1 + + + + + KEY + Key to write in order to validate the write operation + 4 + 31 + + + Keyvalid + Key value + 0xAFBE5A7 + + + + + + + + + APPROTECT_S + Access Port Protection 1 + 0x50039000 + + + + + + KMU_S + Key management unit 1 + 0x50039000 + APPROTECT_S + + + + + KMU + 57 + + + + NVMC_S + Non-volatile memory controller 1 + 0x50039000 + APPROTECT_S + + + + + + VMC_NS + Volatile Memory controller 0 + 0x4003A000 + VMC + + + + 0 + 0x1000 + registers + + VMC + 0x20 + + + 8 + 0x010 + RAM[%s] + Unspecified + VMC_RAM + read-write + 0x600 + + POWER + Description cluster: RAMn power control register + 0x000 + read-write + 0x0000FFFF + + + S0POWER + Keep RAM section S0 of RAM n on or off in System ON mode + 0 + 0 + + + Off + Off + 0x0 + + + On + On + 0x1 + + + + + S1POWER + Keep RAM section S1 of RAM n on or off in System ON mode + 1 + 1 + + + Off + Off + 0x0 + + + On + On + 0x1 + + + + + S2POWER + Keep RAM section S2 of RAM n on or off in System ON mode + 2 + 2 + + + Off + Off + 0x0 + + + On + On + 0x1 + + + + + S3POWER + Keep RAM section S3 of RAM n on or off in System ON mode + 3 + 3 + + + Off + Off + 0x0 + + + On + On + 0x1 + + + + + S0RETENTION + Keep retention on RAM section S0 of RAM n when RAM section is switched off + 16 + 16 + + + Off + Off + 0x0 + + + On + On + 0x1 + + + + + S1RETENTION + Keep retention on RAM section S1 of RAM n when RAM section is switched off + 17 + 17 + + + Off + Off + 0x0 + + + On + On + 0x1 + + + + + S2RETENTION + Keep retention on RAM section S2 of RAM n when RAM section is switched off + 18 + 18 + + + Off + Off + 0x0 + + + On + On + 0x1 + + + + + S3RETENTION + Keep retention on RAM section S3 of RAM n when RAM section is switched off + 19 + 19 + + + Off + Off + 0x0 + + + On + On + 0x1 + + + + + + + POWERSET + Description cluster: RAMn power control set register + 0x004 + write-only + 0x0000FFFF + + + S0POWER + Keep RAM section S0 of RAM n on or off in System ON mode + 0 + 0 + + + On + On + 0x1 + + + + + S1POWER + Keep RAM section S1 of RAM n on or off in System ON mode + 1 + 1 + + + On + On + 0x1 + + + + + S2POWER + Keep RAM section S2 of RAM n on or off in System ON mode + 2 + 2 + + + On + On + 0x1 + + + + + S3POWER + Keep RAM section S3 of RAM n on or off in System ON mode + 3 + 3 + + + On + On + 0x1 + + + + + S0RETENTION + Keep retention on RAM section S0 of RAM n when RAM section is switched off + 16 + 16 + + + On + On + 0x1 + + + + + S1RETENTION + Keep retention on RAM section S1 of RAM n when RAM section is switched off + 17 + 17 + + + On + On + 0x1 + + + + + S2RETENTION + Keep retention on RAM section S2 of RAM n when RAM section is switched off + 18 + 18 + + + On + On + 0x1 + + + + + S3RETENTION + Keep retention on RAM section S3 of RAM n when RAM section is switched off + 19 + 19 + + + On + On + 0x1 + + + + + + + POWERCLR + Description cluster: RAMn power control clear register + 0x008 + write-only + 0x0000FFFF + + + S0POWER + Keep RAM section S0 of RAM n on or off in System ON mode + 0 + 0 + + + Off + Off + 0x1 + + + + + S1POWER + Keep RAM section S1 of RAM n on or off in System ON mode + 1 + 1 + + + Off + Off + 0x1 + + + + + S2POWER + Keep RAM section S2 of RAM n on or off in System ON mode + 2 + 2 + + + Off + Off + 0x1 + + + + + S3POWER + Keep RAM section S3 of RAM n on or off in System ON mode + 3 + 3 + + + Off + Off + 0x1 + + + + + S0RETENTION + Keep retention on RAM section S0 of RAM n when RAM section is switched off + 16 + 16 + + + Off + Off + 0x1 + + + + + S1RETENTION + Keep retention on RAM section S1 of RAM n when RAM section is switched off + 17 + 17 + + + Off + Off + 0x1 + + + + + S2RETENTION + Keep retention on RAM section S2 of RAM n when RAM section is switched off + 18 + 18 + + + Off + Off + 0x1 + + + + + S3RETENTION + Keep retention on RAM section S3 of RAM n when RAM section is switched off + 19 + 19 + + + Off + Off + 0x1 + + + + + + + + + + VMC_S + Volatile Memory controller 1 + 0x5003A000 + + + + + CC_HOST_RGF_S + CRYPTOCELL HOST_RGF interface + 0x50840000 + CC_HOST_RGF + + + + 0 + 0x2000 + registers + + CC_HOST_RGF + 0x20 + + + HOST_CRYPTOKEY_SEL + AES hardware key select + 0x1A38 + read-write + 0x00000000 + + + HOST_CRYPTOKEY_SEL + Select the source of the HW key that is used by the AES engine + 0 + 1 + + + K_DR + Use device root key K_DR from CRYPTOCELL AO power domain + 0x0 + + + K_PRTL + Use hard-coded RTL key K_PRTL + 0x1 + + + Session + Use provided session key + 0x2 + + + + + + + HOST_IOT_KPRTL_LOCK + This write-once register is the K_PRTL lock register. When this register is set, K_PRTL cannot be used and a zeroed key will be used instead. The value of this register is saved in the CRYPTOCELL AO power domain. + 0x1A4C + read-write + 0x00000000 + + + HOST_IOT_KPRTL_LOCK + This register is the K_PRTL lock register. When this register is set, K_PRTL cannot be used and a zeroed key will be used instead. The value of this register is saved in the CRYPTOCELL AO power domain. + 0 + 0 + + + Disabled + K_PRTL can be selected for use from register HOST_CRYPTOKEY_SEL + 0x0 + + + Enabled + K_PRTL has been locked until next power-on reset (POR). If K_PRTL is selected anyway, a zeroed key will be used instead. + 0x1 + + + + + + + HOST_IOT_KDR0 + This register holds bits 31:0 of K_DR. The value of this register is saved in the CRYPTOCELL AO power domain. Reading from this address returns the K_DR valid status indicating if K_DR is successfully retained. + 0x1A50 + read-write + 0x00000000 + + + HOST_IOT_KDR0 + Write: K_DR bits 31:0. Read: 0x00000000 when 128-bit K_DR key value is not yet retained in the CRYPTOCELL AO power domain. Read: 0x00000001 when 128-bit K_DR key value is successfully retained in the CRYPTOCELL AO power domain. + 0 + 31 + + + + + HOST_IOT_KDR1 + This register holds bits 63:32 of K_DR. The value of this register is saved in the CRYPTOCELL AO power domain. + 0x1A54 + write-only + 0x00000000 + + + HOST_IOT_KDR1 + K_DR bits 63:32 + 0 + 31 + + + + + HOST_IOT_KDR2 + This register holds bits 95:64 of K_DR. The value of this register is saved in the CRYPTOCELL AO power domain. + 0x1A58 + write-only + 0x00000000 + + + HOST_IOT_KDR2 + K_DR bits 95:64 + 0 + 31 + + + + + HOST_IOT_KDR3 + This register holds bits 127:96 of K_DR. The value of this register is saved in the CRYPTOCELL AO power domain. + 0x1A5C + write-only + 0x00000000 + + + HOST_IOT_KDR3 + K_DR bits 127:96 + 0 + 31 + + + + + HOST_IOT_LCS + Controls lifecycle state (LCS) for CRYPTOCELL subsystem + 0x1A60 + read-write + 0x00000002 + + + LCS + Lifecycle state value. This field is write-once per reset. + 0 + 2 + + + Debug + CC310 operates in debug mode + 0x0 + + + Secure + CC310 operates in secure mode + 0x2 + + + + + LCS_IS_VALID + Read-only field. Indicates if CRYPTOCELL LCS has been successfully configured since last reset. + 8 + 8 + + + Invalid + Valid LCS not yet retained in the CRYPTOCELL AO power domain + 0x0 + + + Valid + Valid LCS successfully retained in the CRYPTOCELL AO power domain + 0x1 + + + + + + + + + CRYPTOCELL_S + ARM TrustZone CryptoCell register interface + 0x50840000 + CC_HOST_RGF_S + CRYPTOCELL + + + + 0 + 0x2000 + registers + + + CRYPTOCELL + 64 + + CRYPTOCELL + 0x20 + + + ENABLE + Enable CRYPTOCELL subsystem + 0x500 + read-write + 0x00000000 + + + ENABLE + Enable or disable the CRYPTOCELL subsystem + 0 + 0 + + + Disabled + CRYPTOCELL subsystem disabled + 0x0 + + + Enabled + CRYPTOCELL subsystem enabled. + 0x1 + + + + + + + + + P0_NS + GPIO Port 0 + 0x40842500 + GPIO + + + + + 0 + 0x300 + registers + + GPIO + 0x20 + + + OUT + Write GPIO port + 0x004 + read-write + 0x00000000 + + + PIN0 + Pin 0 + 0 + 0 + + + Low + Pin driver is low + 0x0 + + + High + Pin driver is high + 0x1 + + + + + PIN1 + Pin 1 + 1 + 1 + + + Low + Pin driver is low + 0x0 + + + High + Pin driver is high + 0x1 + + + + + PIN2 + Pin 2 + 2 + 2 + + + Low + Pin driver is low + 0x0 + + + High + Pin driver is high + 0x1 + + + + + PIN3 + Pin 3 + 3 + 3 + + + Low + Pin driver is low + 0x0 + + + High + Pin driver is high + 0x1 + + + + + PIN4 + Pin 4 + 4 + 4 + + + Low + Pin driver is low + 0x0 + + + High + Pin driver is high + 0x1 + + + + + PIN5 + Pin 5 + 5 + 5 + + + Low + Pin driver is low + 0x0 + + + High + Pin driver is high + 0x1 + + + + + PIN6 + Pin 6 + 6 + 6 + + + Low + Pin driver is low + 0x0 + + + High + Pin driver is high + 0x1 + + + + + PIN7 + Pin 7 + 7 + 7 + + + Low + Pin driver is low + 0x0 + + + High + Pin driver is high + 0x1 + + + + + PIN8 + Pin 8 + 8 + 8 + + + Low + Pin driver is low + 0x0 + + + High + Pin driver is high + 0x1 + + + + + PIN9 + Pin 9 + 9 + 9 + + + Low + Pin driver is low + 0x0 + + + High + Pin driver is high + 0x1 + + + + + PIN10 + Pin 10 + 10 + 10 + + + Low + Pin driver is low + 0x0 + + + High + Pin driver is high + 0x1 + + + + + PIN11 + Pin 11 + 11 + 11 + + + Low + Pin driver is low + 0x0 + + + High + Pin driver is high + 0x1 + + + + + PIN12 + Pin 12 + 12 + 12 + + + Low + Pin driver is low + 0x0 + + + High + Pin driver is high + 0x1 + + + + + PIN13 + Pin 13 + 13 + 13 + + + Low + Pin driver is low + 0x0 + + + High + Pin driver is high + 0x1 + + + + + PIN14 + Pin 14 + 14 + 14 + + + Low + Pin driver is low + 0x0 + + + High + Pin driver is high + 0x1 + + + + + PIN15 + Pin 15 + 15 + 15 + + + Low + Pin driver is low + 0x0 + + + High + Pin driver is high + 0x1 + + + + + PIN16 + Pin 16 + 16 + 16 + + + Low + Pin driver is low + 0x0 + + + High + Pin driver is high + 0x1 + + + + + PIN17 + Pin 17 + 17 + 17 + + + Low + Pin driver is low + 0x0 + + + High + Pin driver is high + 0x1 + + + + + PIN18 + Pin 18 + 18 + 18 + + + Low + Pin driver is low + 0x0 + + + High + Pin driver is high + 0x1 + + + + + PIN19 + Pin 19 + 19 + 19 + + + Low + Pin driver is low + 0x0 + + + High + Pin driver is high + 0x1 + + + + + PIN20 + Pin 20 + 20 + 20 + + + Low + Pin driver is low + 0x0 + + + High + Pin driver is high + 0x1 + + + + + PIN21 + Pin 21 + 21 + 21 + + + Low + Pin driver is low + 0x0 + + + High + Pin driver is high + 0x1 + + + + + PIN22 + Pin 22 + 22 + 22 + + + Low + Pin driver is low + 0x0 + + + High + Pin driver is high + 0x1 + + + + + PIN23 + Pin 23 + 23 + 23 + + + Low + Pin driver is low + 0x0 + + + High + Pin driver is high + 0x1 + + + + + PIN24 + Pin 24 + 24 + 24 + + + Low + Pin driver is low + 0x0 + + + High + Pin driver is high + 0x1 + + + + + PIN25 + Pin 25 + 25 + 25 + + + Low + Pin driver is low + 0x0 + + + High + Pin driver is high + 0x1 + + + + + PIN26 + Pin 26 + 26 + 26 + + + Low + Pin driver is low + 0x0 + + + High + Pin driver is high + 0x1 + + + + + PIN27 + Pin 27 + 27 + 27 + + + Low + Pin driver is low + 0x0 + + + High + Pin driver is high + 0x1 + + + + + PIN28 + Pin 28 + 28 + 28 + + + Low + Pin driver is low + 0x0 + + + High + Pin driver is high + 0x1 + + + + + PIN29 + Pin 29 + 29 + 29 + + + Low + Pin driver is low + 0x0 + + + High + Pin driver is high + 0x1 + + + + + PIN30 + Pin 30 + 30 + 30 + + + Low + Pin driver is low + 0x0 + + + High + Pin driver is high + 0x1 + + + + + PIN31 + Pin 31 + 31 + 31 + + + Low + Pin driver is low + 0x0 + + + High + Pin driver is high + 0x1 + + + + + + + OUTSET + Set individual bits in GPIO port + 0x008 + read-write + 0x00000000 + oneToSet + + + PIN0 + Pin 0 + 0 + 0 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 0x1 + + + + + PIN1 + Pin 1 + 1 + 1 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 0x1 + + + + + PIN2 + Pin 2 + 2 + 2 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 0x1 + + + + + PIN3 + Pin 3 + 3 + 3 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 0x1 + + + + + PIN4 + Pin 4 + 4 + 4 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 0x1 + + + + + PIN5 + Pin 5 + 5 + 5 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 0x1 + + + + + PIN6 + Pin 6 + 6 + 6 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 0x1 + + + + + PIN7 + Pin 7 + 7 + 7 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 0x1 + + + + + PIN8 + Pin 8 + 8 + 8 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 0x1 + + + + + PIN9 + Pin 9 + 9 + 9 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 0x1 + + + + + PIN10 + Pin 10 + 10 + 10 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 0x1 + + + + + PIN11 + Pin 11 + 11 + 11 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 0x1 + + + + + PIN12 + Pin 12 + 12 + 12 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 0x1 + + + + + PIN13 + Pin 13 + 13 + 13 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 0x1 + + + + + PIN14 + Pin 14 + 14 + 14 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 0x1 + + + + + PIN15 + Pin 15 + 15 + 15 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 0x1 + + + + + PIN16 + Pin 16 + 16 + 16 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 0x1 + + + + + PIN17 + Pin 17 + 17 + 17 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 0x1 + + + + + PIN18 + Pin 18 + 18 + 18 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 0x1 + + + + + PIN19 + Pin 19 + 19 + 19 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 0x1 + + + + + PIN20 + Pin 20 + 20 + 20 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 0x1 + + + + + PIN21 + Pin 21 + 21 + 21 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 0x1 + + + + + PIN22 + Pin 22 + 22 + 22 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 0x1 + + + + + PIN23 + Pin 23 + 23 + 23 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 0x1 + + + + + PIN24 + Pin 24 + 24 + 24 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 0x1 + + + + + PIN25 + Pin 25 + 25 + 25 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 0x1 + + + + + PIN26 + Pin 26 + 26 + 26 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 0x1 + + + + + PIN27 + Pin 27 + 27 + 27 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 0x1 + + + + + PIN28 + Pin 28 + 28 + 28 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 0x1 + + + + + PIN29 + Pin 29 + 29 + 29 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 0x1 + + + + + PIN30 + Pin 30 + 30 + 30 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 0x1 + + + + + PIN31 + Pin 31 + 31 + 31 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 0x1 + + + + + + + OUTCLR + Clear individual bits in GPIO port + 0x00C + read-write + 0x00000000 + oneToClear + + + PIN0 + Pin 0 + 0 + 0 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 0x1 + + + + + PIN1 + Pin 1 + 1 + 1 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 0x1 + + + + + PIN2 + Pin 2 + 2 + 2 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 0x1 + + + + + PIN3 + Pin 3 + 3 + 3 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 0x1 + + + + + PIN4 + Pin 4 + 4 + 4 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 0x1 + + + + + PIN5 + Pin 5 + 5 + 5 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 0x1 + + + + + PIN6 + Pin 6 + 6 + 6 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 0x1 + + + + + PIN7 + Pin 7 + 7 + 7 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 0x1 + + + + + PIN8 + Pin 8 + 8 + 8 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 0x1 + + + + + PIN9 + Pin 9 + 9 + 9 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 0x1 + + + + + PIN10 + Pin 10 + 10 + 10 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 0x1 + + + + + PIN11 + Pin 11 + 11 + 11 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 0x1 + + + + + PIN12 + Pin 12 + 12 + 12 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 0x1 + + + + + PIN13 + Pin 13 + 13 + 13 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 0x1 + + + + + PIN14 + Pin 14 + 14 + 14 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 0x1 + + + + + PIN15 + Pin 15 + 15 + 15 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 0x1 + + + + + PIN16 + Pin 16 + 16 + 16 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 0x1 + + + + + PIN17 + Pin 17 + 17 + 17 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 0x1 + + + + + PIN18 + Pin 18 + 18 + 18 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 0x1 + + + + + PIN19 + Pin 19 + 19 + 19 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 0x1 + + + + + PIN20 + Pin 20 + 20 + 20 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 0x1 + + + + + PIN21 + Pin 21 + 21 + 21 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 0x1 + + + + + PIN22 + Pin 22 + 22 + 22 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 0x1 + + + + + PIN23 + Pin 23 + 23 + 23 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 0x1 + + + + + PIN24 + Pin 24 + 24 + 24 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 0x1 + + + + + PIN25 + Pin 25 + 25 + 25 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 0x1 + + + + + PIN26 + Pin 26 + 26 + 26 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 0x1 + + + + + PIN27 + Pin 27 + 27 + 27 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 0x1 + + + + + PIN28 + Pin 28 + 28 + 28 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 0x1 + + + + + PIN29 + Pin 29 + 29 + 29 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 0x1 + + + + + PIN30 + Pin 30 + 30 + 30 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 0x1 + + + + + PIN31 + Pin 31 + 31 + 31 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 0x1 + + + + + + + IN + Read GPIO port + 0x010 + read-only + 0x00000000 + + + PIN0 + Pin 0 + 0 + 0 + + + Low + Pin input is low + 0x0 + + + High + Pin input is high + 0x1 + + + + + PIN1 + Pin 1 + 1 + 1 + + + Low + Pin input is low + 0x0 + + + High + Pin input is high + 0x1 + + + + + PIN2 + Pin 2 + 2 + 2 + + + Low + Pin input is low + 0x0 + + + High + Pin input is high + 0x1 + + + + + PIN3 + Pin 3 + 3 + 3 + + + Low + Pin input is low + 0x0 + + + High + Pin input is high + 0x1 + + + + + PIN4 + Pin 4 + 4 + 4 + + + Low + Pin input is low + 0x0 + + + High + Pin input is high + 0x1 + + + + + PIN5 + Pin 5 + 5 + 5 + + + Low + Pin input is low + 0x0 + + + High + Pin input is high + 0x1 + + + + + PIN6 + Pin 6 + 6 + 6 + + + Low + Pin input is low + 0x0 + + + High + Pin input is high + 0x1 + + + + + PIN7 + Pin 7 + 7 + 7 + + + Low + Pin input is low + 0x0 + + + High + Pin input is high + 0x1 + + + + + PIN8 + Pin 8 + 8 + 8 + + + Low + Pin input is low + 0x0 + + + High + Pin input is high + 0x1 + + + + + PIN9 + Pin 9 + 9 + 9 + + + Low + Pin input is low + 0x0 + + + High + Pin input is high + 0x1 + + + + + PIN10 + Pin 10 + 10 + 10 + + + Low + Pin input is low + 0x0 + + + High + Pin input is high + 0x1 + + + + + PIN11 + Pin 11 + 11 + 11 + + + Low + Pin input is low + 0x0 + + + High + Pin input is high + 0x1 + + + + + PIN12 + Pin 12 + 12 + 12 + + + Low + Pin input is low + 0x0 + + + High + Pin input is high + 0x1 + + + + + PIN13 + Pin 13 + 13 + 13 + + + Low + Pin input is low + 0x0 + + + High + Pin input is high + 0x1 + + + + + PIN14 + Pin 14 + 14 + 14 + + + Low + Pin input is low + 0x0 + + + High + Pin input is high + 0x1 + + + + + PIN15 + Pin 15 + 15 + 15 + + + Low + Pin input is low + 0x0 + + + High + Pin input is high + 0x1 + + + + + PIN16 + Pin 16 + 16 + 16 + + + Low + Pin input is low + 0x0 + + + High + Pin input is high + 0x1 + + + + + PIN17 + Pin 17 + 17 + 17 + + + Low + Pin input is low + 0x0 + + + High + Pin input is high + 0x1 + + + + + PIN18 + Pin 18 + 18 + 18 + + + Low + Pin input is low + 0x0 + + + High + Pin input is high + 0x1 + + + + + PIN19 + Pin 19 + 19 + 19 + + + Low + Pin input is low + 0x0 + + + High + Pin input is high + 0x1 + + + + + PIN20 + Pin 20 + 20 + 20 + + + Low + Pin input is low + 0x0 + + + High + Pin input is high + 0x1 + + + + + PIN21 + Pin 21 + 21 + 21 + + + Low + Pin input is low + 0x0 + + + High + Pin input is high + 0x1 + + + + + PIN22 + Pin 22 + 22 + 22 + + + Low + Pin input is low + 0x0 + + + High + Pin input is high + 0x1 + + + + + PIN23 + Pin 23 + 23 + 23 + + + Low + Pin input is low + 0x0 + + + High + Pin input is high + 0x1 + + + + + PIN24 + Pin 24 + 24 + 24 + + + Low + Pin input is low + 0x0 + + + High + Pin input is high + 0x1 + + + + + PIN25 + Pin 25 + 25 + 25 + + + Low + Pin input is low + 0x0 + + + High + Pin input is high + 0x1 + + + + + PIN26 + Pin 26 + 26 + 26 + + + Low + Pin input is low + 0x0 + + + High + Pin input is high + 0x1 + + + + + PIN27 + Pin 27 + 27 + 27 + + + Low + Pin input is low + 0x0 + + + High + Pin input is high + 0x1 + + + + + PIN28 + Pin 28 + 28 + 28 + + + Low + Pin input is low + 0x0 + + + High + Pin input is high + 0x1 + + + + + PIN29 + Pin 29 + 29 + 29 + + + Low + Pin input is low + 0x0 + + + High + Pin input is high + 0x1 + + + + + PIN30 + Pin 30 + 30 + 30 + + + Low + Pin input is low + 0x0 + + + High + Pin input is high + 0x1 + + + + + PIN31 + Pin 31 + 31 + 31 + + + Low + Pin input is low + 0x0 + + + High + Pin input is high + 0x1 + + + + + + + DIR + Direction of GPIO pins + 0x014 + read-write + 0x00000000 + + + PIN0 + Pin 0 + 0 + 0 + + + Input + Pin set as input + 0x0 + + + Output + Pin set as output + 0x1 + + + + + PIN1 + Pin 1 + 1 + 1 + + + Input + Pin set as input + 0x0 + + + Output + Pin set as output + 0x1 + + + + + PIN2 + Pin 2 + 2 + 2 + + + Input + Pin set as input + 0x0 + + + Output + Pin set as output + 0x1 + + + + + PIN3 + Pin 3 + 3 + 3 + + + Input + Pin set as input + 0x0 + + + Output + Pin set as output + 0x1 + + + + + PIN4 + Pin 4 + 4 + 4 + + + Input + Pin set as input + 0x0 + + + Output + Pin set as output + 0x1 + + + + + PIN5 + Pin 5 + 5 + 5 + + + Input + Pin set as input + 0x0 + + + Output + Pin set as output + 0x1 + + + + + PIN6 + Pin 6 + 6 + 6 + + + Input + Pin set as input + 0x0 + + + Output + Pin set as output + 0x1 + + + + + PIN7 + Pin 7 + 7 + 7 + + + Input + Pin set as input + 0x0 + + + Output + Pin set as output + 0x1 + + + + + PIN8 + Pin 8 + 8 + 8 + + + Input + Pin set as input + 0x0 + + + Output + Pin set as output + 0x1 + + + + + PIN9 + Pin 9 + 9 + 9 + + + Input + Pin set as input + 0x0 + + + Output + Pin set as output + 0x1 + + + + + PIN10 + Pin 10 + 10 + 10 + + + Input + Pin set as input + 0x0 + + + Output + Pin set as output + 0x1 + + + + + PIN11 + Pin 11 + 11 + 11 + + + Input + Pin set as input + 0x0 + + + Output + Pin set as output + 0x1 + + + + + PIN12 + Pin 12 + 12 + 12 + + + Input + Pin set as input + 0x0 + + + Output + Pin set as output + 0x1 + + + + + PIN13 + Pin 13 + 13 + 13 + + + Input + Pin set as input + 0x0 + + + Output + Pin set as output + 0x1 + + + + + PIN14 + Pin 14 + 14 + 14 + + + Input + Pin set as input + 0x0 + + + Output + Pin set as output + 0x1 + + + + + PIN15 + Pin 15 + 15 + 15 + + + Input + Pin set as input + 0x0 + + + Output + Pin set as output + 0x1 + + + + + PIN16 + Pin 16 + 16 + 16 + + + Input + Pin set as input + 0x0 + + + Output + Pin set as output + 0x1 + + + + + PIN17 + Pin 17 + 17 + 17 + + + Input + Pin set as input + 0x0 + + + Output + Pin set as output + 0x1 + + + + + PIN18 + Pin 18 + 18 + 18 + + + Input + Pin set as input + 0x0 + + + Output + Pin set as output + 0x1 + + + + + PIN19 + Pin 19 + 19 + 19 + + + Input + Pin set as input + 0x0 + + + Output + Pin set as output + 0x1 + + + + + PIN20 + Pin 20 + 20 + 20 + + + Input + Pin set as input + 0x0 + + + Output + Pin set as output + 0x1 + + + + + PIN21 + Pin 21 + 21 + 21 + + + Input + Pin set as input + 0x0 + + + Output + Pin set as output + 0x1 + + + + + PIN22 + Pin 22 + 22 + 22 + + + Input + Pin set as input + 0x0 + + + Output + Pin set as output + 0x1 + + + + + PIN23 + Pin 23 + 23 + 23 + + + Input + Pin set as input + 0x0 + + + Output + Pin set as output + 0x1 + + + + + PIN24 + Pin 24 + 24 + 24 + + + Input + Pin set as input + 0x0 + + + Output + Pin set as output + 0x1 + + + + + PIN25 + Pin 25 + 25 + 25 + + + Input + Pin set as input + 0x0 + + + Output + Pin set as output + 0x1 + + + + + PIN26 + Pin 26 + 26 + 26 + + + Input + Pin set as input + 0x0 + + + Output + Pin set as output + 0x1 + + + + + PIN27 + Pin 27 + 27 + 27 + + + Input + Pin set as input + 0x0 + + + Output + Pin set as output + 0x1 + + + + + PIN28 + Pin 28 + 28 + 28 + + + Input + Pin set as input + 0x0 + + + Output + Pin set as output + 0x1 + + + + + PIN29 + Pin 29 + 29 + 29 + + + Input + Pin set as input + 0x0 + + + Output + Pin set as output + 0x1 + + + + + PIN30 + Pin 30 + 30 + 30 + + + Input + Pin set as input + 0x0 + + + Output + Pin set as output + 0x1 + + + + + PIN31 + Pin 31 + 31 + 31 + + + Input + Pin set as input + 0x0 + + + Output + Pin set as output + 0x1 + + + + + + + DIRSET + DIR set register + 0x018 + read-write + 0x00000000 + oneToSet + + + PIN0 + Set as output pin 0 + 0 + 0 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 0x1 + + + + + PIN1 + Set as output pin 1 + 1 + 1 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 0x1 + + + + + PIN2 + Set as output pin 2 + 2 + 2 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 0x1 + + + + + PIN3 + Set as output pin 3 + 3 + 3 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 0x1 + + + + + PIN4 + Set as output pin 4 + 4 + 4 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 0x1 + + + + + PIN5 + Set as output pin 5 + 5 + 5 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 0x1 + + + + + PIN6 + Set as output pin 6 + 6 + 6 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 0x1 + + + + + PIN7 + Set as output pin 7 + 7 + 7 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 0x1 + + + + + PIN8 + Set as output pin 8 + 8 + 8 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 0x1 + + + + + PIN9 + Set as output pin 9 + 9 + 9 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 0x1 + + + + + PIN10 + Set as output pin 10 + 10 + 10 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 0x1 + + + + + PIN11 + Set as output pin 11 + 11 + 11 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 0x1 + + + + + PIN12 + Set as output pin 12 + 12 + 12 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 0x1 + + + + + PIN13 + Set as output pin 13 + 13 + 13 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 0x1 + + + + + PIN14 + Set as output pin 14 + 14 + 14 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 0x1 + + + + + PIN15 + Set as output pin 15 + 15 + 15 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 0x1 + + + + + PIN16 + Set as output pin 16 + 16 + 16 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 0x1 + + + + + PIN17 + Set as output pin 17 + 17 + 17 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 0x1 + + + + + PIN18 + Set as output pin 18 + 18 + 18 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 0x1 + + + + + PIN19 + Set as output pin 19 + 19 + 19 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 0x1 + + + + + PIN20 + Set as output pin 20 + 20 + 20 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 0x1 + + + + + PIN21 + Set as output pin 21 + 21 + 21 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 0x1 + + + + + PIN22 + Set as output pin 22 + 22 + 22 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 0x1 + + + + + PIN23 + Set as output pin 23 + 23 + 23 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 0x1 + + + + + PIN24 + Set as output pin 24 + 24 + 24 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 0x1 + + + + + PIN25 + Set as output pin 25 + 25 + 25 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 0x1 + + + + + PIN26 + Set as output pin 26 + 26 + 26 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 0x1 + + + + + PIN27 + Set as output pin 27 + 27 + 27 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 0x1 + + + + + PIN28 + Set as output pin 28 + 28 + 28 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 0x1 + + + + + PIN29 + Set as output pin 29 + 29 + 29 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 0x1 + + + + + PIN30 + Set as output pin 30 + 30 + 30 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 0x1 + + + + + PIN31 + Set as output pin 31 + 31 + 31 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 0x1 + + + + + + + DIRCLR + DIR clear register + 0x01C + read-write + 0x00000000 + oneToClear + + + PIN0 + Set as input pin 0 + 0 + 0 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 0x1 + + + + + PIN1 + Set as input pin 1 + 1 + 1 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 0x1 + + + + + PIN2 + Set as input pin 2 + 2 + 2 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 0x1 + + + + + PIN3 + Set as input pin 3 + 3 + 3 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 0x1 + + + + + PIN4 + Set as input pin 4 + 4 + 4 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 0x1 + + + + + PIN5 + Set as input pin 5 + 5 + 5 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 0x1 + + + + + PIN6 + Set as input pin 6 + 6 + 6 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 0x1 + + + + + PIN7 + Set as input pin 7 + 7 + 7 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 0x1 + + + + + PIN8 + Set as input pin 8 + 8 + 8 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 0x1 + + + + + PIN9 + Set as input pin 9 + 9 + 9 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 0x1 + + + + + PIN10 + Set as input pin 10 + 10 + 10 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 0x1 + + + + + PIN11 + Set as input pin 11 + 11 + 11 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 0x1 + + + + + PIN12 + Set as input pin 12 + 12 + 12 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 0x1 + + + + + PIN13 + Set as input pin 13 + 13 + 13 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 0x1 + + + + + PIN14 + Set as input pin 14 + 14 + 14 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 0x1 + + + + + PIN15 + Set as input pin 15 + 15 + 15 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 0x1 + + + + + PIN16 + Set as input pin 16 + 16 + 16 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 0x1 + + + + + PIN17 + Set as input pin 17 + 17 + 17 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 0x1 + + + + + PIN18 + Set as input pin 18 + 18 + 18 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 0x1 + + + + + PIN19 + Set as input pin 19 + 19 + 19 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 0x1 + + + + + PIN20 + Set as input pin 20 + 20 + 20 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 0x1 + + + + + PIN21 + Set as input pin 21 + 21 + 21 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 0x1 + + + + + PIN22 + Set as input pin 22 + 22 + 22 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 0x1 + + + + + PIN23 + Set as input pin 23 + 23 + 23 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 0x1 + + + + + PIN24 + Set as input pin 24 + 24 + 24 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 0x1 + + + + + PIN25 + Set as input pin 25 + 25 + 25 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 0x1 + + + + + PIN26 + Set as input pin 26 + 26 + 26 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 0x1 + + + + + PIN27 + Set as input pin 27 + 27 + 27 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 0x1 + + + + + PIN28 + Set as input pin 28 + 28 + 28 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 0x1 + + + + + PIN29 + Set as input pin 29 + 29 + 29 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 0x1 + + + + + PIN30 + Set as input pin 30 + 30 + 30 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 0x1 + + + + + PIN31 + Set as input pin 31 + 31 + 31 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 0x1 + + + + + + + LATCH + Latch register indicating what GPIO pins that have met the criteria set in the PIN_CNF[n].SENSE registers + 0x020 + read-write + 0x00000000 + + + PIN0 + Status on whether PIN[0] has met criteria set in PIN_CNF[0].SENSE register. Write '1' to clear. + 0 + 0 + + + NotLatched + Criteria has not been met + 0x0 + + + Latched + Criteria has been met + 0x1 + + + + + PIN1 + Status on whether PIN[1] has met criteria set in PIN_CNF[1].SENSE register. Write '1' to clear. + 1 + 1 + + + NotLatched + Criteria has not been met + 0x0 + + + Latched + Criteria has been met + 0x1 + + + + + PIN2 + Status on whether PIN[2] has met criteria set in PIN_CNF[2].SENSE register. Write '1' to clear. + 2 + 2 + + + NotLatched + Criteria has not been met + 0x0 + + + Latched + Criteria has been met + 0x1 + + + + + PIN3 + Status on whether PIN[3] has met criteria set in PIN_CNF[3].SENSE register. Write '1' to clear. + 3 + 3 + + + NotLatched + Criteria has not been met + 0x0 + + + Latched + Criteria has been met + 0x1 + + + + + PIN4 + Status on whether PIN[4] has met criteria set in PIN_CNF[4].SENSE register. Write '1' to clear. + 4 + 4 + + + NotLatched + Criteria has not been met + 0x0 + + + Latched + Criteria has been met + 0x1 + + + + + PIN5 + Status on whether PIN[5] has met criteria set in PIN_CNF[5].SENSE register. Write '1' to clear. + 5 + 5 + + + NotLatched + Criteria has not been met + 0x0 + + + Latched + Criteria has been met + 0x1 + + + + + PIN6 + Status on whether PIN[6] has met criteria set in PIN_CNF[6].SENSE register. Write '1' to clear. + 6 + 6 + + + NotLatched + Criteria has not been met + 0x0 + + + Latched + Criteria has been met + 0x1 + + + + + PIN7 + Status on whether PIN[7] has met criteria set in PIN_CNF[7].SENSE register. Write '1' to clear. + 7 + 7 + + + NotLatched + Criteria has not been met + 0x0 + + + Latched + Criteria has been met + 0x1 + + + + + PIN8 + Status on whether PIN[8] has met criteria set in PIN_CNF[8].SENSE register. Write '1' to clear. + 8 + 8 + + + NotLatched + Criteria has not been met + 0x0 + + + Latched + Criteria has been met + 0x1 + + + + + PIN9 + Status on whether PIN[9] has met criteria set in PIN_CNF[9].SENSE register. Write '1' to clear. + 9 + 9 + + + NotLatched + Criteria has not been met + 0x0 + + + Latched + Criteria has been met + 0x1 + + + + + PIN10 + Status on whether PIN[10] has met criteria set in PIN_CNF[10].SENSE register. Write '1' to clear. + 10 + 10 + + + NotLatched + Criteria has not been met + 0x0 + + + Latched + Criteria has been met + 0x1 + + + + + PIN11 + Status on whether PIN[11] has met criteria set in PIN_CNF[11].SENSE register. Write '1' to clear. + 11 + 11 + + + NotLatched + Criteria has not been met + 0x0 + + + Latched + Criteria has been met + 0x1 + + + + + PIN12 + Status on whether PIN[12] has met criteria set in PIN_CNF[12].SENSE register. Write '1' to clear. + 12 + 12 + + + NotLatched + Criteria has not been met + 0x0 + + + Latched + Criteria has been met + 0x1 + + + + + PIN13 + Status on whether PIN[13] has met criteria set in PIN_CNF[13].SENSE register. Write '1' to clear. + 13 + 13 + + + NotLatched + Criteria has not been met + 0x0 + + + Latched + Criteria has been met + 0x1 + + + + + PIN14 + Status on whether PIN[14] has met criteria set in PIN_CNF[14].SENSE register. Write '1' to clear. + 14 + 14 + + + NotLatched + Criteria has not been met + 0x0 + + + Latched + Criteria has been met + 0x1 + + + + + PIN15 + Status on whether PIN[15] has met criteria set in PIN_CNF[15].SENSE register. Write '1' to clear. + 15 + 15 + + + NotLatched + Criteria has not been met + 0x0 + + + Latched + Criteria has been met + 0x1 + + + + + PIN16 + Status on whether PIN[16] has met criteria set in PIN_CNF[16].SENSE register. Write '1' to clear. + 16 + 16 + + + NotLatched + Criteria has not been met + 0x0 + + + Latched + Criteria has been met + 0x1 + + + + + PIN17 + Status on whether PIN[17] has met criteria set in PIN_CNF[17].SENSE register. Write '1' to clear. + 17 + 17 + + + NotLatched + Criteria has not been met + 0x0 + + + Latched + Criteria has been met + 0x1 + + + + + PIN18 + Status on whether PIN[18] has met criteria set in PIN_CNF[18].SENSE register. Write '1' to clear. + 18 + 18 + + + NotLatched + Criteria has not been met + 0x0 + + + Latched + Criteria has been met + 0x1 + + + + + PIN19 + Status on whether PIN[19] has met criteria set in PIN_CNF[19].SENSE register. Write '1' to clear. + 19 + 19 + + + NotLatched + Criteria has not been met + 0x0 + + + Latched + Criteria has been met + 0x1 + + + + + PIN20 + Status on whether PIN[20] has met criteria set in PIN_CNF[20].SENSE register. Write '1' to clear. + 20 + 20 + + + NotLatched + Criteria has not been met + 0x0 + + + Latched + Criteria has been met + 0x1 + + + + + PIN21 + Status on whether PIN[21] has met criteria set in PIN_CNF[21].SENSE register. Write '1' to clear. + 21 + 21 + + + NotLatched + Criteria has not been met + 0x0 + + + Latched + Criteria has been met + 0x1 + + + + + PIN22 + Status on whether PIN[22] has met criteria set in PIN_CNF[22].SENSE register. Write '1' to clear. + 22 + 22 + + + NotLatched + Criteria has not been met + 0x0 + + + Latched + Criteria has been met + 0x1 + + + + + PIN23 + Status on whether PIN[23] has met criteria set in PIN_CNF[23].SENSE register. Write '1' to clear. + 23 + 23 + + + NotLatched + Criteria has not been met + 0x0 + + + Latched + Criteria has been met + 0x1 + + + + + PIN24 + Status on whether PIN[24] has met criteria set in PIN_CNF[24].SENSE register. Write '1' to clear. + 24 + 24 + + + NotLatched + Criteria has not been met + 0x0 + + + Latched + Criteria has been met + 0x1 + + + + + PIN25 + Status on whether PIN[25] has met criteria set in PIN_CNF[25].SENSE register. Write '1' to clear. + 25 + 25 + + + NotLatched + Criteria has not been met + 0x0 + + + Latched + Criteria has been met + 0x1 + + + + + PIN26 + Status on whether PIN[26] has met criteria set in PIN_CNF[26].SENSE register. Write '1' to clear. + 26 + 26 + + + NotLatched + Criteria has not been met + 0x0 + + + Latched + Criteria has been met + 0x1 + + + + + PIN27 + Status on whether PIN[27] has met criteria set in PIN_CNF[27].SENSE register. Write '1' to clear. + 27 + 27 + + + NotLatched + Criteria has not been met + 0x0 + + + Latched + Criteria has been met + 0x1 + + + + + PIN28 + Status on whether PIN[28] has met criteria set in PIN_CNF[28].SENSE register. Write '1' to clear. + 28 + 28 + + + NotLatched + Criteria has not been met + 0x0 + + + Latched + Criteria has been met + 0x1 + + + + + PIN29 + Status on whether PIN[29] has met criteria set in PIN_CNF[29].SENSE register. Write '1' to clear. + 29 + 29 + + + NotLatched + Criteria has not been met + 0x0 + + + Latched + Criteria has been met + 0x1 + + + + + PIN30 + Status on whether PIN[30] has met criteria set in PIN_CNF[30].SENSE register. Write '1' to clear. + 30 + 30 + + + NotLatched + Criteria has not been met + 0x0 + + + Latched + Criteria has been met + 0x1 + + + + + PIN31 + Status on whether PIN[31] has met criteria set in PIN_CNF[31].SENSE register. Write '1' to clear. + 31 + 31 + + + NotLatched + Criteria has not been met + 0x0 + + + Latched + Criteria has been met + 0x1 + + + + + + + DETECTMODE + Select between default DETECT signal behavior and LDETECT mode (For non-secure pin only) + 0x024 + read-write + 0x00000000 + + + DETECTMODE + Select between default DETECT signal behavior and LDETECT mode + 0 + 0 + + + Default + DETECT directly connected to PIN DETECT signals + 0x0 + + + LDETECT + Use the latched LDETECT behavior + 0x1 + + + + + + + DETECTMODE_SEC + Select between default DETECT signal behavior and LDETECT mode (For secure pin only) + 0x028 + read-write + 0x00000000 + + + DETECTMODE + Select between default DETECT signal behavior and LDETECT mode + 0 + 0 + + + Default + DETECT directly connected to PIN DETECT signals + 0x0 + + + LDETECT + Use the latched LDETECT behavior + 0x1 + + + + + + + 0x20 + 0x4 + PIN_CNF[%s] + Description collection: Configuration of GPIO pins + 0x200 + read-write + 0x00000002 + + + DIR + Pin direction. Same physical register as DIR register + 0 + 0 + + + Input + Configure pin as an input pin + 0x0 + + + Output + Configure pin as an output pin + 0x1 + + + + + INPUT + Connect or disconnect input buffer + 1 + 1 + + + Connect + Connect input buffer + 0x0 + + + Disconnect + Disconnect input buffer + 0x1 + + + + + PULL + Pull configuration + 2 + 3 + + + Disabled + No pull + 0x0 + + + Pulldown + Pull down on pin + 0x1 + + + Pullup + Pull up on pin + 0x3 + + + + + DRIVE + Drive configuration + 8 + 10 + + + S0S1 + Standard '0', standard '1' + 0x0 + + + H0S1 + High drive '0', standard '1' + 0x1 + + + S0H1 + Standard '0', high drive '1' + 0x2 + + + H0H1 + High drive '0', high 'drive '1'' + 0x3 + + + D0S1 + Disconnect '0', standard '1' (normally used for wired-or connections) + 0x4 + + + D0H1 + Disconnect '0', high drive '1' (normally used for wired-or connections) + 0x5 + + + S0D1 + Standard '0', disconnect '1' (normally used for wired-and connections) + 0x6 + + + H0D1 + High drive '0', disconnect '1' (normally used for wired-and connections) + 0x7 + + + + + SENSE + Pin sensing mechanism + 16 + 17 + + + Disabled + Disabled + 0x0 + + + High + Sense for high level + 0x2 + + + Low + Sense for low level + 0x3 + + + + + + + + + P0_S + GPIO Port 1 + 0x50842500 + + + + + + \ No newline at end of file diff --git a/xtask/src/lib.rs b/xtask/src/lib.rs index 8087ae1a..693204c9 100644 --- a/xtask/src/lib.rs +++ b/xtask/src/lib.rs @@ -1,3 +1,4 @@ +use std::collections::BTreeMap; use std::fs; use xshell::cmd; @@ -13,6 +14,7 @@ pub static PACS: &[(&str, &str)] = &[ ("nrf5340-app", "thumbv8m.main-none-eabihf"), ("nrf5340-net", "thumbv8m.main-none-eabihf"), ("nrf9160", "thumbv8m.main-none-eabihf"), + ("nrf9120", "thumbv8m.main-none-eabihf"), ]; pub fn install_tools() { @@ -62,6 +64,40 @@ pub fn generate() { } cmd!("cargo fmt").run().unwrap(); + + clean_generation(); +} + +// Remove deprecated lint warnings +pub fn clean_generation() { + for (pac, _target) in PACS { + let crate_dir = format!("pacs/{}-pac", pac); + + cmd!("sed -i '/#!\\[deny(const_err)\\]/d' {crate_dir}/src/lib.rs") + .run() + .unwrap(); + cmd!("sed -i '/#!\\[deny(private_in_public)\\]/d' {crate_dir}/src/lib.rs") + .run() + .unwrap(); + } +} + +pub fn build() { + // We group them by target so that we can have Cargo build some of them in parallel. + // FIXME: With https://github.com/rust-lang/cargo/issues/8176 this could be a single invocation. + let mut target_map: BTreeMap<_, Vec<_>> = BTreeMap::new(); + for (pac, target) in PACS { + target_map.entry(target).or_default().push(pac); + } + + for (target, pacs) in target_map { + let mut cmd = cmd!("cargo build --target {target}"); + for pac in pacs { + let package = format!("{}-pac", pac); + cmd = cmd.args(&["-p", &package]); + } + cmd.run().unwrap(); + } } pub fn is_git_clean() -> bool { diff --git a/xtask/src/main.rs b/xtask/src/main.rs index 27597c42..f6d32a8a 100644 --- a/xtask/src/main.rs +++ b/xtask/src/main.rs @@ -7,6 +7,9 @@ fn main() { Some("generate") => { xtask::generate(); } + Some("build") => { + xtask::build(); + } Some("publish") => { let dry_run = match args.next() { Some(arg) if arg == "--dry-run" => true, @@ -20,6 +23,7 @@ fn main() { eprintln!(); eprintln!("subcommands:"); eprintln!(" generate - regenerate crates"); + eprintln!(" build - build crates"); eprintln!(" publish [--dry-run] - publish crates to crates.io"); } } diff --git a/xtask/tests/ci.rs b/xtask/tests/ci.rs index 718075e3..56a3d033 100644 --- a/xtask/tests/ci.rs +++ b/xtask/tests/ci.rs @@ -1,4 +1,4 @@ -use std::{collections::BTreeMap, env}; +use std::env; use xshell::cmd; use xtask::is_git_clean; @@ -8,7 +8,9 @@ fn main() { // Regenerate PACs and check that nothing has changed. let was_clean = is_git_clean(); + xtask::generate(); + let is_clean = is_git_clean(); if !is_clean { cmd!("git status").run().unwrap(); @@ -18,19 +20,5 @@ fn main() { } // Test that every PAC builds for the intended target. - // We group them by target so that we can have Cargo build some of them in parallel. - // FIXME: With https://github.com/rust-lang/cargo/issues/8176 this could be a single invocation. - let mut target_map: BTreeMap<_, Vec<_>> = BTreeMap::new(); - for (pac, target) in xtask::PACS { - target_map.entry(target).or_default().push(pac); - } - - for (target, pacs) in target_map { - let mut cmd = cmd!("cargo build --target {target}"); - for pac in pacs { - let package = format!("{}-pac", pac); - cmd = cmd.args(&["-p", &package]); - } - cmd.run().unwrap(); - } + xtask::build(); }