diff --git a/edalize/flows/sim.py b/edalize/flows/sim.py index 656d5cfb..4c852707 100644 --- a/edalize/flows/sim.py +++ b/edalize/flows/sim.py @@ -42,7 +42,7 @@ def configure_tools(self, flow): [ "--vpi", "--public-flat-rw --prefix Vtop", - '-LDFLAGS "-Wl,-rpath,`cocotb-config --lib-dir` -L`cocotb-config --lib-dir` -lcocotbvpi_verilator -lgpi -lcocotb -lgpilog -lcocotbutils"', + '-LDFLAGS "-Wl,-rpath,`cocotb-config --lib-dir` -L`cocotb-config --lib-dir` -lcocotbvpi_verilator -lgpi -lcocotb -lgpilog -lcocotbutils -Wl,--unresolved-symbols=ignore-in-shared-libs"', ], ), } diff --git a/tests/flows/sim/with_cocotb/Makefile b/tests/flows/sim/with_cocotb/Makefile new file mode 100644 index 00000000..08c4404e --- /dev/null +++ b/tests/flows/sim/with_cocotb/Makefile @@ -0,0 +1,19 @@ +#Auto generated by Edalize + +all: post_build + +pre_build: + +Vtop.mk: design.vc sv_file.sv vlog_file.v vlog05_file.v vlog_incfile another_sv_file.sv | pre_build + $(EDALIZE_LAUNCHER) verilator -f design.vc `cocotb-config --share`/lib/verilator/verilator.cpp + +Vtop: Vtop.mk c_file.c cpp_file.cpp + $(EDALIZE_LAUNCHER) make -f Vtop.mk + +post_build: Vtop + +pre_run: + +run: pre_run + +post_run: run diff --git a/tests/flows/sim/with_cocotb/design.vc b/tests/flows/sim/with_cocotb/design.vc new file mode 100644 index 00000000..3afb7aa8 --- /dev/null +++ b/tests/flows/sim/with_cocotb/design.vc @@ -0,0 +1,22 @@ +--Mdir . +--cc +--vpi +--public-flat-rw --prefix Vtop +-LDFLAGS "-Wl,-rpath,`cocotb-config --lib-dir` -L`cocotb-config --lib-dir` -lcocotbvpi_verilator -lgpi -lcocotb -lgpilog -lcocotbutils -Wl,--unresolved-symbols=ignore-in-shared-libs" ++incdir+. +-CFLAGS -I. +sv_file.sv +vlog_file.v +vlog05_file.v +another_sv_file.sv +--top-module top_module + +--exe +c_file.c +cpp_file.cpp +-Gvlogparam_bool=1 +-Gvlogparam_int=42 +-Gvlogparam_str=\"hello\" +-Dvlogdefine_bool=1 +-Dvlogdefine_int=42 +-Dvlogdefine_str=hello diff --git a/tests/test_flow_sim.py b/tests/test_flow_sim.py index d1dd6d08..17e115c4 100644 --- a/tests/test_flow_sim.py +++ b/tests/test_flow_sim.py @@ -20,3 +20,16 @@ def test_sim(flow_fixture): "Makefile", ] ) + + +def test_sim_cocotb(flow_fixture): + flow_options = {"tool": "verilator", "cocotb_module": "some_cocotb_module"} + ff = flow_fixture("sim", flow_options=flow_options, ref_subdir="with_cocotb") + + ff.flow.configure() + ff.compare_config_files( + [ + "design.vc", + "Makefile", + ] + )