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Synthesis Bugs in the LSU #160

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rsar97 opened this issue Jan 5, 2025 · 1 comment
Open

Synthesis Bugs in the LSU #160

rsar97 opened this issue Jan 5, 2025 · 1 comment

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@rsar97
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rsar97 commented Jan 5, 2025

Hi,

We found a output mismatch between the RTL and the netlist of the or1200 cpu output port (du_lsu_load_dat) orginating from the LSU module of the port.
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@stffrdhrn
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Hi @rsar97 thanks for the bug report, do you have a solution for this or working on a patch?

What synthesis tool are you using?

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@stffrdhrn @rsar97