VHDL Backend

[VonTum]

Allow outputting VHDL code too

[IBims1NicerTobi]

I would like to do this

[VonTum]

@IBims1NicerTobi I would like to implement #25 such that Tim & Fabian can implement #27 more comprehensively. This would change the Verilog backend, as well as influencing the VHDL backend afterwards. Is that alright with you?

[IBims1NicerTobi]

Sure but should I then just wait until #25 is done so I don't have to implement this twice? There are other things I could work on in the mean time and I would prefer that to doing it twice.

[VonTum]

I wouldn't wait to finish the VHDL backend, as it doesn't change much. It's just a special case for if the submodule is an extern module

[IBims1NicerTobi]

Sure

[VonTum]

I estimate it'll take me a few days to get to it too, since I'm first setting up sus.rocks