From a6d86c229ea1f5ade90a9a3c30fcaf6fac675c4f Mon Sep 17 00:00:00 2001
From: Andrey Zgarbul <zgarbul.andrey@gmail.com>
Date: Mon, 23 Dec 2024 19:43:25 +0300
Subject: [PATCH] bitmask

---
 svd-rs/CHANGELOG.md    |  2 +-
 svd-rs/src/field.rs    | 21 +++++++++++++++++++++
 svd-rs/src/register.rs |  5 +++++
 3 files changed, 27 insertions(+), 1 deletion(-)

diff --git a/svd-rs/CHANGELOG.md b/svd-rs/CHANGELOG.md
index c8af63f..daf3173 100644
--- a/svd-rs/CHANGELOG.md
+++ b/svd-rs/CHANGELOG.md
@@ -8,6 +8,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 ## Unreleased
 
 - Revert the `riscv` elements, as well as the `unstable-riscv` feature.
+- Add `bitmask` for `FieldInfo`, `Field` and `RegisterInfo`
 
 ## [v0.14.9] - 2024-08-20
 
@@ -143,4 +144,3 @@ Previous versions in common [changelog](../CHANGELOG.md).
 [v0.11.2]: https://github.com/rust-embedded/svd/compare/svd-rs-v0.11.1...svd-rs-v0.11.2
 [v0.11.1]: https://github.com/rust-embedded/svd/compare/v0.11.0...svd-rs-v0.11.1
 [v0.11.0]: https://github.com/rust-embedded/svd/compare/v0.10.2...v0.11.0
-
diff --git a/svd-rs/src/field.rs b/svd-rs/src/field.rs
index 5fd3108..7fe336f 100644
--- a/svd-rs/src/field.rs
+++ b/svd-rs/src/field.rs
@@ -375,6 +375,12 @@ impl FieldInfo {
         self.bit_range.msb()
     }
 
+    /// Get bits which is affected by field
+    pub fn bitmask(&self) -> u64 {
+        let BitRange { offset, width, .. } = self.bit_range;
+        (!0u64 >> (64 - width)) << offset
+    }
+
     /// Get enumeratedValues cluster by usage
     pub fn get_enumerated_values(&self, usage: Usage) -> Option<&EnumeratedValues> {
         match self.enumerated_values.len() {
@@ -406,6 +412,21 @@ impl Field {
         }
         self.deref().validate_all(lvl)
     }
+
+    /// Get bits which is affected by field or field array
+    pub fn bitmask(&self) -> u64 {
+        match self {
+            Field::Single(f) => f.bitmask(),
+            Field::Array(f, d) => {
+                let mask = f.bitmask();
+                let mut bits = 0;
+                for i in 0..d.dim {
+                    bits |= mask << (i * d.dim_increment);
+                }
+                bits
+            }
+        }
+    }
 }
 
 impl Name for FieldInfo {
diff --git a/svd-rs/src/register.rs b/svd-rs/src/register.rs
index 0afdf32..b9a8622 100644
--- a/svd-rs/src/register.rs
+++ b/svd-rs/src/register.rs
@@ -420,6 +420,11 @@ impl RegisterInfo {
     pub fn get_mut_field(&mut self, name: &str) -> Option<&mut Field> {
         self.fields_mut().find(|f| f.name == name)
     }
+
+    /// Get bits which is affected by register fields
+    pub fn bitmask(&self) -> u64 {
+        self.fields().fold(0, |mask, f| mask | f.bitmask())
+    }
 }
 
 impl Register {