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Add an explanation why checking compilation time is important
Remove references to red-coloured fragments of text
no color rendering so indicate the field by name
Updated HowTo LCA2018 FPGA Miniconf VexRiscv Renode (markdown)
Add note how to build with Yosys + Vivado
Remove TODO
Fix memory size in DTB
add modified LCA2018 tutorial changed for VexRiscv and Renode