build.js

(function(){function r(e,n,t){function o(i,f){if(!n[i]){if(!e[i]){var c="function"==typeof require&&require;if(!f&&c)return c(i,!0);if(u)return u(i,!0);var a=new Error("Cannot find module '"+i+"'");throw a.code="MODULE_NOT_FOUND",a}var p=n[i]={exports:{}};e[i][0].call(p.exports,function(r){var n=e[i][1][r];return o(n||r)},p,p.exports,r,e,n,t)}return n[i].exports}for(var u="function"==typeof require&&require,i=0;i<t.length;i++)o(t[i]);return o}return r})()({1:[function(require,module,exports){
const fs = require('fs');
const tetris = require('./cartridges/tetris.js');

class CartridgeController{
    constructor(rom_file){
        if(rom_file === "t"){
            this.full_rom = tetris;
            return;
        }

        let s = fs.readFileSync(rom_file, 'hex');
        this.full_rom = [...Array(s.length / 2).keys()].map((_, i) => parseInt(s[i * 2] + s[i * 2 + 1], 16));
    }

    read_byte(addr){
        //TODO: bank switch reading.
        return this.full_rom[addr];
    }

    extract_rom(){
        let s = '';
        for(let i = 0; i < this.full_rom.length; i++){
            s += '0x' + this.full_rom[i].toString(16) + ',';
            if(i % 32 === 0) s += '\n';
        }

        fs.writeFileSync("./temp.rb", s);
    }

    // read_word(addr){
    //     return this.full_rom[addr] + (this.full_rom[addr + 1] << 8);
    // }

    write_byte(addr, v){
        throw "Bank switch not implemented";
    }

    // write_word(addr, v){
    //     throw "Bank switch not implemented";
    // }


}

module.exports = CartridgeController;
},{"./cartridges/tetris.js":2,"fs":9}],2:[function(require,module,exports){
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    0x4e,0xa3,0x48,0x48,0xa2,0x4c,0xa1,0x4c,0x4a,0xa2,0x4c,0x44,0x34,0x4c,0xa3,0x4c,0xa5,0x1,0x0,0x9d,0xe9,0x6e,0x20,0xa2,0x5c,0xa1,0x5c,0x5c,0xa2,0x5c,0xa1,0x5c,
    0x5c,0xa2,0x4e,0x52,0xa1,0x56,0x56,0xa2,0x56,0xa2,0x5c,0xa1,0x5c,0x5c,0xa2,0x5c,0xa1,0x5c,0x5c,0xa2,0x52,0x4c,0xa1,0x44,0x44,0xa2,0x1,0xa5,0x1,0x0,0xe9,0x7a,
    0x0,0x0,0x8,0x7b,0x25,0x7b,0x4f,0x7b,0x9d,0xc2,0x0,0x80,0xa2,0x5c,0xa1,0x5c,0x5a,0xa2,0x5c,0x5c,0x56,0x52,0x4e,0x56,0xa2,0x52,0xa1,0x52,0x50,0xa2,0x52,0x4c,
    0x44,0x52,0xa3,0x5c,0xa4,0x1,0x0,0x9d,0xb2,0x0,0x80,0xa2,0x4e,0xa1,0x4e,0x52,0xa2,0x56,0x4e,0xa3,0x48,0x48,0xa2,0x4c,0xa1,0x4c,0x4a,0xa2,0x4c,0x44,0x34,0x4c,
    0xa3,0x4c,0xa5,0x1,0x9d,0xe9,0x6e,0x20,0xa2,0x5c,0xa1,0x5c,0x5c,0xa2,0x5c,0xa1,0x5c,0x5c,0x4e,0x56,0x5c,0x56,0x4e,0x44,0x3e,0x44,0xa2,0x5c,0xa1,0x5c,0x5c,0xa2,
    0x5c,0xa1,0x5c,0x5c,0x52,0x4c,0x44,0x4c,0x5c,0x1,0xa2,0x1,0xa5,0x1,0xa2,0xb,0xb,0xb,0xb,0xa2,0xb,0xb,0xb,0x1,0xa2,0xb,0xb,0xb,0xb,0xa2,0xb,0xb,
    0xb,0x1,0xa5,0x1,0x77,0x7b,0xce,0x7b,0x0,0x0,0x96,0x7b,0xf2,0x7b,0xa8,0x7b,0x2,0x7c,0xbb,0x7b,0x12,0x7c,0x9d,0xd1,0x0,0x80,0xa2,0x5c,0xa1,0x5c,0x5a,0xa2,
    0x5c,0x5c,0x56,0x52,0x4e,0x56,0xa2,0x52,0xa1,0x52,0x50,0xa2,0x52,0x52,0x4c,0x48,0x44,0xa1,0x4c,0x52,0x0,0xa2,0x52,0xa7,0x1,0xa2,0x44,0x44,0x44,0x1,0x4c,0xa7,
    0x1,0xa2,0x3a,0x3a,0x3a,0x1,0x0,0xa2,0x5c,0xa7,0x1,0xa2,0x4e,0x52,0x56,0x1,0xa2,0x5c,0xa7,0x1,0xa2,0x44,0x48,0x4c,0x1,0x0,0xa2,0x6,0xa7,0x1,0xa2,0xb,
    0xb,0xb,0x1,0xa2,0x6,0xa7,0x1,0xa2,0xb,0xb,0xb,0x1,0x0,0xa2,0x48,0xa1,0x48,0x52,0xa2,0x44,0xa1,0x44,0x52,0xa2,0x42,0xa1,0x42,0x52,0xa2,0x48,0xa1,0x48,
    0x52,0xa2,0x4c,0xa1,0x4c,0x52,0xa2,0x48,0xa1,0x48,0x52,0xa2,0x5c,0x52,0xa3,0x5c,0x0,0x1,0x3a,0x1,0x3a,0x1,0x3a,0x1,0x3a,0x1,0x3a,0x1,0x3a,0x1,0x3a,0xa3,
    0x34,0x1,0x48,0x1,0x48,0x1,0x48,0x1,0x48,0x1,0x44,0x1,0x44,0x1,0x4c,0xa3,0x44,0xa2,0x1,0xb,0x1,0xb,0x1,0xb,0x1,0xb,0x1,0xb,0x1,0xb,0xa2,0x1,
    0xb,0xb,0x1,0x2e,0x7c,0x0,0x0,0x63,0x7c,0x97,0x7c,0xcb,0x7c,0x9d,0xb3,0x0,0x80,0xa6,0x52,0xa1,0x50,0xa6,0x52,0xa1,0x50,0xa6,0x52,0xa1,0x48,0xa3,0x1,0xa6,
    0x4c,0xa1,0x4a,0xa6,0x4c,0xa1,0x4a,0xa6,0x4c,0xa1,0x42,0xa3,0x1,0xa6,0x3e,0xa1,0x42,0xa6,0x44,0xa1,0x48,0xa6,0x4c,0xa1,0x50,0xa6,0x52,0xa1,0x56,0xa6,0x52,0xa1,
    0x6a,0x0,0x9d,0x93,0x0,0xc0,0xa6,0x42,0xa1,0x40,0xa6,0x42,0xa1,0x40,0xa6,0x42,0xa1,0x42,0xa3,0x1,0xa6,0x3a,0xa1,0x38,0xa6,0x3a,0xa1,0x38,0xa6,0x3a,0xa1,0x3a,
    0xa3,0x1,0xa6,0x38,0xa1,0x38,0xa6,0x3a,0xa1,0x3e,0xa6,0x42,0xa1,0x44,0xa6,0x48,0xa1,0x4c,0xa6,0x42,0xa1,0x42,0x9d,0xe9,0x6e,0xa0,0xa6,0x48,0xa1,0x46,0xa6,0x48,
    0xa1,0x46,0xa6,0x48,0xa1,0x52,0xa3,0x1,0xa6,0x44,0xa1,0x42,0xa6,0x44,0xa1,0x42,0xa6,0x44,0xa1,0x4c,0xa3,0x1,0xa6,0x48,0xa1,0x3a,0xa6,0x3e,0xa1,0x42,0xa6,0x44,
    0xa1,0x48,0xa6,0x4c,0xa1,0x50,0xa6,0x52,0xa1,0x3a,0xa6,0xb,0xa1,0x6,0xa6,0xb,0xa1,0x6,0xa6,0xb,0xa1,0x6,0xa3,0x1,0xa6,0xb,0xa1,0x6,0xa6,0xb,0xa1,0x6,
    0xa6,0xb,0xa1,0x6,0xa3,0x1,0xa6,0xb,0xa1,0x6,0xa6,0xb,0xa1,0x6,0xa6,0xb,0xa1,0x6,0xa3,0x1,0xa6,0xb,0xa1,0x6,0x2e,0x7d,0xff,0xff,0x1,0x7d,0x29,0x7d,
    0x35,0x7d,0x5b,0x7d,0x82,0x7d,0x5b,0x7d,0xa4,0x7d,0xc6,0x7d,0xff,0xff,0x3,0x7d,0x3b,0x7d,0x6c,0x7d,0x93,0x7d,0x6c,0x7d,0xb5,0x7d,0x7,0x7e,0xff,0xff,0x13,0x7d,
    0x3e,0x7d,0x41,0x7d,0xff,0xff,0x23,0x7d,0x9d,0x60,0x0,0x81,0x0,0x9d,0x20,0x0,0x81,0xaa,0x1,0x0,0xa3,0x1,0x50,0x54,0x58,0x0,0xa5,0x1,0x0,0xa5,0x1,0x0,
    0xa3,0x1,0x6,0x1,0x6,0x1,0xa2,0x6,0x6,0xa3,0x1,0x6,0xa3,0x1,0x6,0x1,0x6,0x1,0xa2,0x6,0x6,0x1,0x1,0x6,0x6,0x0,0xa7,0x5a,0xa2,0x5e,0xa7,0x5a,
    0xa2,0x58,0xa7,0x58,0xa2,0x54,0xa7,0x58,0xa2,0x54,0x0,0x9d,0xc9,0x6e,0x20,0xa2,0x5a,0x62,0x68,0x70,0x5a,0x62,0x68,0x70,0x5a,0x64,0x66,0x6c,0x5a,0x64,0x66,0x6c,
    0x0,0xa7,0x54,0xa2,0x50,0xa7,0x54,0xa2,0x50,0xa7,0x50,0xa2,0x4c,0xa7,0x4a,0xa2,0x50,0x0,0x58,0x5e,0x64,0x6c,0x58,0x5e,0x64,0x6c,0x50,0x54,0x58,0x5e,0x50,0x58,
    0x5e,0x64,0x0,0xa7,0x54,0xa2,0x50,0xa7,0x54,0xa2,0x50,0xa7,0x50,0xa2,0x4c,0xa7,0x4a,0xa2,0x46,0x0,0x58,0x5e,0x64,0x6c,0x58,0x5e,0x64,0x6c,0x50,0x54,0x58,0x5e,
    0x50,0x58,0x5e,0x64,0x0,0xa7,0x4a,0xa2,0x4c,0xa7,0x4a,0xa2,0x46,0xa7,0x46,0xa2,0x44,0xa7,0x46,0xa2,0x4a,0xa7,0x4c,0xa2,0x50,0xa7,0x4c,0xa2,0x4a,0xa7,0x4a,0xa2,
    0x46,0xa7,0x4a,0xa2,0x4c,0xa7,0x50,0xa2,0x4e,0xa7,0x50,0xa2,0x52,0xa7,0x58,0xa2,0x54,0xa7,0x5a,0xa2,0x54,0xa7,0x52,0xa2,0x50,0xa7,0x4c,0xa2,0x4a,0xa2,0x42,0x38,
    0x3c,0x4a,0xa3,0x42,0x1,0x0,0x4a,0x52,0x58,0x5e,0x4a,0x58,0x5e,0x62,0x54,0x62,0x68,0x6c,0x54,0x62,0x68,0x6c,0x46,0x4c,0x54,0x5e,0x46,0x4c,0x54,0x5a,0x50,0x58,
    0x5e,0x64,0x50,0x5e,0x64,0x6c,0x4a,0x50,0x58,0x5e,0x4a,0x58,0x5e,0x62,0x4e,0x54,0x5a,0x62,0x4e,0x54,0x5a,0x66,0x50,0x58,0x5e,0x64,0x50,0x5e,0x64,0x68,0xa8,0x5a,
    0xa3,0x1,0x0,0x4e,0x7e,0x0,0x0,0x5e,0x7e,0x6d,0x7e,0x7d,0x7e,0x9d,0xb1,0x0,0x80,0xa7,0x1,0xa1,0x5e,0x5e,0xa6,0x68,0xa1,0x5e,0xa4,0x68,0x0,0x9d,0x91,0x0,
    0x80,0xa7,0x1,0xa1,0x54,0x54,0xa6,0x5e,0xa1,0x58,0xa4,0x5e,0x9d,0xe9,0x6e,0x20,0xa7,0x1,0xa1,0x4e,0x4e,0xa6,0x58,0xa1,0x50,0xa3,0x58,0x1,0xa7,0x1,0xa1,0x6,
    0x6,0xa6,0xb,0xa1,0x6,0xa0,0x6,0x6,0x6,0x6,0x6,0x6,0x6,0x6,0xa3,0x1,0xbb,0x7e,0x28,0x7f,0xbb,0x7e,0x73,0x7f,0xff,0xff,0x91,0x7e,0xe5,0x7e,0x4f,0x7f,
    0xe5,0x7e,0x96,0x7f,0xff,0xff,0x9d,0x7e,0xfb,0x7e,0x61,0x7f,0xfb,0x7e,0xae,0x7f,0xff,0xff,0xa9,0x7e,0x11,0x7f,0xff,0xff,0xb5,0x7e,0x9d,0x82,0x0,0x80,0xa2,0x54,
    0xa1,0x54,0x54,0x54,0x4a,0x46,0x4a,0xa2,0x54,0xa1,0x54,0x54,0x54,0x58,0x5c,0x58,0xa2,0x54,0xa1,0x54,0x54,0x58,0x54,0x52,0x54,0xa1,0x58,0x5c,0x58,0x5c,0xa2,0x58,
    0xa1,0x56,0x58,0x0,0x9d,0x62,0x0,0x80,0xa2,0x1,0x44,0x1,0x40,0x1,0x44,0x1,0x46,0x1,0x44,0x1,0x44,0x1,0x40,0x1,0x40,0x0,0x9d,0xe9,0x6e,0x20,0xa2,0x54,
    0x54,0x4a,0x52,0x54,0x54,0x4a,0x58,0x54,0x54,0x52,0x54,0x4e,0x54,0x4a,0x52,0x0,0xa2,0x6,0xb,0x6,0xb,0x6,0xb,0x6,0xb,0x6,0xb,0x6,0xb,0x6,0xa1,0xb,
    0xb,0x6,0xa2,0xb,0xa1,0x6,0x0,0xa2,0x5e,0xa1,0x5e,0x5e,0x5e,0x54,0x50,0x54,0xa2,0x5e,0xa1,0x5e,0x5e,0x5e,0x62,0x66,0x62,0xa2,0x5e,0xa1,0x5e,0x5c,0xa2,0x58,
    0xa1,0x58,0x54,0xa1,0x52,0x54,0x52,0x54,0xa2,0x52,0xa1,0x4e,0x52,0x0,0xa2,0x1,0x46,0x1,0x4a,0x1,0x46,0x1,0x4a,0x1,0x46,0x1,0x46,0x1,0x46,0x1,0x46,0x0,
    0xa2,0x46,0x54,0x54,0x54,0x46,0x54,0x54,0x54,0x46,0x54,0x52,0x58,0x44,0x52,0x4a,0x58,0x0,0xa2,0x62,0xa1,0x62,0x62,0x62,0x5e,0x5a,0x5e,0xa2,0x62,0xa1,0x62,0x62,
    0x62,0x5e,0x5a,0x5e,0xa2,0x62,0xa1,0x4a,0x4e,0xa2,0x52,0xa1,0x4a,0x5c,0xa3,0x58,0xa1,0x54,0xa6,0x6c,0x0,0xa2,0x1,0x4a,0x1,0x4a,0x1,0x4a,0x1,0x4a,0x1,0xa1,
    0x46,0x46,0xa2,0x46,0xa1,0x46,0x46,0xa3,0x46,0xa2,0x44,0x1,0x0,0xa2,0x42,0x5a,0x50,0x5a,0x42,0x5a,0x50,0x5a,0x4a,0xa1,0x52,0x52,0xa2,0x52,0xa1,0x52,0x52,0xa3,
    0x52,0xa2,0x54,0x1,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,
    0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0xc3,0xd3,0x64,0xc3,0xa5,0x69,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0];

module.exports = bin;
},{}],3:[function(require,module,exports){
const ins_handler = require("./cpu_instructions");

class CPU{
    constructor(mmu){
        this.serialid = "haoyan_number_1";
        this.reset();
        this.mmu = mmu;
        this.mmu.cpu = this;
    }

    reset(){
        this.cycles = 0;
        this.ins_count = 0;
        this.regs = {
            //Sorted as the address sequence.
            b: 0, c: 0, //8 bit
            d: 0, e: 0, //8 bit
            h: 0, l: 0, //8 bit
            a: 0, f: 0, //8 bit, f is flag register: Z N H C 0 0 0 0
            sp: 0, //16 bit stack pointer
            pc: 0 //16 bit program counter
        };

        this.reg_keys = Object.keys(this.regs);
    }

    get_reg(addr){
        if(addr < 6) return this.regs[this.reg_keys[addr]];
        switch(addr){
            case 0x6: return (this.regs.h << 8) + this.regs.l;
            case 0x7: return this.regs.a;
        }
    }

    set_reg(addr, v){
        if(typeof v === "undefined") throw "You can't set reg this way"; //DEBUG

        if(addr < 6){
            this.regs[this.reg_keys[addr]] = v;
            return;
        }
        switch (addr) {
            case 0x6:
                this.regs.h = v >> 8;
                this.regs.l = v & 0xff;
                break;
            case 0x7:
                this.regs.a = v;
        }
    }

    f_set_zero(){this.regs.f |= 0x80;}
    f_reset_zero(){this.regs.f &= 0x7f;}
    f_set_sub(){this.regs.f |= 0x40;}
    f_reset_sub(){this.regs.f &= 0xbf;}
    f_set_hcarry(){this.regs.f |= 0x20;}
    f_reset_hcarry(){this.regs.f &= 0xdf;}
    f_set_carry(){this.regs.f |= 0x10;}
    f_reset_carry(){this.regs.f &= 0xef;}
    f_reset(){this.regs.f &= 0xf;}

    f_zero(){return this.regs.f & 0x80;}
    f_carry(){return this.regs.f & 0x10;}

    stack_push_16(v){
        this.regs.sp--;
        this.mmu.write_byte(this.regs.sp, v >> 8);
        this.regs.sp--;
        this.mmu.write_byte(this.regs.sp, v & 0xff);
    }

    stack_pop_16(){
        let v = this.mmu.read_byte(this.regs.sp);
        this.regs.sp++;
        v += this.mmu.read_byte(this.regs.sp) << 8;
        this.regs.sp++;
        return v;
    }

    debug_check_regs(op){
        this.reg_keys.forEach(k => {
            if(typeof this.regs[k] === 'undefined')
                console.log(`Damn ${op}`);
        })
    }

    tick (){
        let op = this.mmu.read_byte(this.regs.pc);
        let rep = ins_handler(this, op);
        this.debug_check_regs(op);
        this.cycles += rep.cycle;
        this.regs.pc += rep.pc;

        this.ins_count++;
        return rep.cycle;
    }

    print_state(){
        console.log({
            reg: this.regs,
            cycles: this.cycles,
            steps: this.ins_count
        });
    }

    print_f_ram(){
        this.mmu.high_speed_ram.forEach(i => console.log(i));
    }

    print_regs(){
        console.log(this.regs);
    }

}

module.exports = CPU;
},{"./cpu_instructions":4}],4:[function(require,module,exports){
const {ext_handler, GET_REG, SET_REG} = require('./cpu_instructions_ext.js');

function NOP(h){ return {pc: 1, cycle: 4};}

function JR(h){
    h.regs.pc = (h.regs.pc + 2 + to_signed_int8(h.mmu.read_byte(h.regs.pc + 1))) & 0xffff;
    return {pc: 0, cycle: 12};}

function JR_NZ(h){ if(h.f_zero()) return {pc: 2, cycle: 8}; h.regs.pc = (h.regs.pc + 2 + to_signed_int8(h.mmu.read_byte(h.regs.pc + 1))) & 0xffff; return {pc: 0, cycle: 12};}
function JR_Z(h){ if(!h.f_zero()) return {pc: 2, cycle: 8}; h.regs.pc = (h.regs.pc + 2 + to_signed_int8(h.mmu.read_byte(h.regs.pc + 1))) & 0xffff; return {pc: 0, cycle: 12};}
function JR_NC(h){ if(h.f_carry()) return {pc: 2, cycle: 8}; h.regs.pc = (h.regs.pc + 2 + to_signed_int8(h.mmu.read_byte(h.regs.pc + 1))) & 0xffff; return {pc: 0, cycle: 12};}
function JR_C(h){ if(!h.f_carry()) return {pc: 2, cycle: 8}; h.regs.pc = (h.regs.pc + 2 + to_signed_int8(h.mmu.read_byte(h.regs.pc + 1))) & 0xffff; return {pc: 0, cycle: 12};}

function CALL_IMM16(h){ h.stack_push_16(h.regs.pc + 3); h.regs.pc = h.mmu.read_word(h.regs.pc + 1); return {pc: 0, cycle: 24};}

function RET(h){ h.regs.pc = h.stack_pop_16(); return {pc: 0, cycle: 16};}

//Memory loads
function LD_BCM_A(h){ h.mmu.write_byte((h.regs.b << 8) + h.regs.c, h.regs.a); return {pc: 1, cycle: 8};}
function LD_DEM_A(h){ h.mmu.write_byte((h.regs.d << 8) + h.regs.e, h.regs.a); return {pc: 1, cycle: 8};}
function LD_HLM_A(h){ h.mmu.write_byte((h.regs.h << 8) + h.regs.l, h.regs.a); return {pc: 1, cycle: 8};}
function LD_A_BCM(h){ h.regs.a = h.mmu.read_byte((h.regs.b << 8) + h.regs.c); return {pc: 1, cycle: 8};}
function LD_A_DEM(h){ h.regs.a = h.mmu.read_byte((h.regs.d << 8) + h.regs.e); return {pc: 1, cycle: 8};}

function LD_HLMI_A(h){ LD_HLM_A(h); INC_HL(h); return {pc: 1, cycle: 8};}
function LD_HLMD_A(h){ LD_HLM_A(h); DEC_HL(h); return {pc: 1, cycle: 8};}
function LD_A_HLMI(h){ h.regs.a = h.mmu.read_byte((h.regs.h << 8) + h.regs.l); INC_HL(h); return {pc: 1, cycle: 8};}
function LD_A_HLMD(h){ h.regs.a = h.mmu.read_byte((h.regs.h << 8) + h.regs.l); DEC_HL(h); return {pc: 1, cycle: 8};}

function LD_A_CM(h){ h.regs.a = h.mmu.read_byte(0xff00 + h.regs.c); return {pc: 1, cycle: 8};}
function LD_CM_A(h){ h.mmu.write_byte(0xff00 + h.regs.c, h.regs.a); return {pc: 1, cycle: 8};}
function LD_HIMM8_A(h){ h.mmu.write_byte(0xff00 + h.mmu.read_byte(h.regs.pc + 1), h.regs.a); return {pc: 2, cycle: 12};}
function LD_A_HIMM8(h){ h.regs.a = h.mmu.read_byte(0xff00 + h.mmu.read_byte(h.regs.pc + 1)); return {pc: 2, cycle: 12};}

//8 bit loads
function LD_C_IMM8(h){ h.regs.c = h.mmu.read_byte(h.regs.pc + 1); return {pc: 2, cycle: 8};}
function LD_E_IMM8(h){ h.regs.e = h.mmu.read_byte(h.regs.pc + 1); return {pc: 2, cycle: 8};}
function LD_L_IMM8(h){ h.regs.l = h.mmu.read_byte(h.regs.pc + 1); return {pc: 2, cycle: 8};}
function LD_A_IMM8(h){ h.regs.a = h.mmu.read_byte(h.regs.pc + 1); return {pc: 2, cycle: 8};}
function LD_B_IMM8(h){ h.regs.b = h.mmu.read_byte(h.regs.pc + 1); return {pc: 2, cycle: 8};}
function LD_D_IMM8(h){ h.regs.d = h.mmu.read_byte(h.regs.pc + 1); return {pc: 2, cycle: 8};}
function LD_H_IMM8(h){ h.regs.h = h.mmu.read_byte(h.regs.pc + 1); return {pc: 2, cycle: 8};}
function LD_HLM_IMM8(h){ h.mmu.write_byte((h.regs.h << 8) + h.regs.l, h.mmu.read_byte(h.regs.pc + 1)); return {pc: 2, cycle: 12};}

function LD_IMM16M_A(h){ h.mmu.write_byte(h.mmu.read_word(h.regs.pc + 1), h.regs.a); return {pc: 3, cycle: 16};}
function LD_A_IMM16M(h){ h.regs.a = h.mmu.read_byte(h.mmu.read_word(h.regs.pc + 1)); return {pc: 3, cycle: 16};}

//16 bit loads
function LD_BC_IMM16(h){ h.regs.c = h.mmu.read_byte(h.regs.pc + 1); h.regs.b = h.mmu.read_byte(h.regs.pc + 2); return {pc: 3, cycle: 12};}
function LD_DE_IMM16(h){ h.regs.e = h.mmu.read_byte(h.regs.pc + 1); h.regs.d = h.mmu.read_byte(h.regs.pc + 2); return {pc: 3, cycle: 12};}
function LD_HL_IMM16(h){ h.regs.l = h.mmu.read_byte(h.regs.pc + 1); h.regs.h = h.mmu.read_byte(h.regs.pc + 2); return {pc: 3, cycle: 12};}
function LD_SP_IMM16(h){ h.regs.sp = h.mmu.read_word(h.regs.pc + 1); return {pc: 3, cycle: 12};}


//Stack
function PUSH_AF(h){ h.stack_push_16((h.regs.a << 8) + h.regs.f); return {pc: 1, cycle: 16};}
function PUSH_BC(h){ h.stack_push_16((h.regs.b << 8) + h.regs.c); return {pc: 1, cycle: 16};}
function PUSH_DE(h){ h.stack_push_16((h.regs.d << 8) + h.regs.e); return {pc: 1, cycle: 16};}
function PUSH_HL(h){ h.stack_push_16((h.regs.h << 8) + h.regs.l); return {pc: 1, cycle: 16};}

function POP_AF(h){ let v = h.stack_pop_16(); h.regs.a = v >> 8; h.regs.f = v & 0xff; return {pc: 1, cycle: 12};}
function POP_BC(h){ let v = h.stack_pop_16(); h.regs.b = v >> 8; h.regs.c = v & 0xff; return {pc: 1, cycle: 12};}
function POP_DE(h){ let v = h.stack_pop_16(); h.regs.d = v >> 8; h.regs.e = v & 0xff; return {pc: 1, cycle: 12};}
function POP_HL(h){ let v = h.stack_pop_16(); h.regs.h = v >> 8; h.regs.l = v & 0xff; return {pc: 1, cycle: 12};}


//8 bit INC, DEC
function INC_B(h){ if(half_carry_add8(h.regs.b, 1)) h.f_set_hcarry(); else h.f_reset_hcarry(); h.regs.b++; h.regs.b &= 0xff; h.f_reset_sub(); if(h.regs.b) h.f_reset_zero(); else h.f_set_zero(); return {pc: 1, cycle: 4};}
function INC_D(h){ if(half_carry_add8(h.regs.d, 1)) h.f_set_hcarry(); else h.f_reset_hcarry(); h.regs.d++; h.regs.d &= 0xff; h.f_reset_sub(); if(h.regs.d) h.f_reset_zero(); else h.f_set_zero(); return {pc: 1, cycle: 4};}
function INC_H(h){ if(half_carry_add8(h.regs.h, 1)) h.f_set_hcarry(); else h.f_reset_hcarry(); h.regs.h++; h.regs.h &= 0xff; h.f_reset_sub(); if(h.regs.h) h.f_reset_zero(); else h.f_set_zero(); return {pc: 1, cycle: 4};}
function INC_HLM(h){ let addr = (h.regs.h << 8) + h.regs.l; let v = h.mmu.read_byte(addr); if(half_carry_add8(v, 1)) h.f_set_hcarry(); else h.f_reset_hcarry(); let nv = (v + 1) & 0xff; h.mmu.write_byte(addr, nv); h.f_reset_sub(); if(nv) h.f_reset_zero(); else h.f_set_zero(); return {pc: 1, cycle: 12};}

function INC_C(h){ if(half_carry_add8(h.regs.c, 1)) h.f_set_hcarry(); else h.f_reset_hcarry(); h.regs.c++; h.regs.c &= 0xff; h.f_reset_sub(); if(h.regs.c) h.f_reset_zero(); else h.f_set_zero(); return {pc: 1, cycle: 4};}
function INC_E(h){ if(half_carry_add8(h.regs.e, 1)) h.f_set_hcarry(); else h.f_reset_hcarry(); h.regs.e++; h.regs.e &= 0xff; h.f_reset_sub(); if(h.regs.e) h.f_reset_zero(); else h.f_set_zero(); return {pc: 1, cycle: 4};}
function INC_L(h){ if(half_carry_add8(h.regs.l, 1)) h.f_set_hcarry(); else h.f_reset_hcarry(); h.regs.l++; h.regs.l &= 0xff; h.f_reset_sub(); if(h.regs.l) h.f_reset_zero(); else h.f_set_zero(); return {pc: 1, cycle: 4};}
function INC_A(h){ if(half_carry_add8(h.regs.a, 1)) h.f_set_hcarry(); else h.f_reset_hcarry(); h.regs.a++; h.regs.a &= 0xff; h.f_reset_sub(); if(h.regs.a) h.f_reset_zero(); else h.f_set_zero(); return {pc: 1, cycle: 4};}

function DEC_B(h){ h.f_set_sub(); if(half_carry_sub8(h.regs.b, 1)) h.f_set_hcarry(); else h.f_reset_hcarry(); h.regs.b--; h.regs.b &= 0xff; if(h.regs.b) h.f_reset_zero(); else h.f_set_zero(); return {pc: 1, cycle: 4};}
function DEC_D(h){ h.f_set_sub(); if(half_carry_sub8(h.regs.d, 1)) h.f_set_hcarry(); else h.f_reset_hcarry(); h.regs.d--; h.regs.d &= 0xff; if(h.regs.d) h.f_reset_zero(); else h.f_set_zero(); return {pc: 1, cycle: 4};}
function DEC_H(h){ h.f_set_sub(); if(half_carry_sub8(h.regs.h, 1)) h.f_set_hcarry(); else h.f_reset_hcarry(); h.regs.h--; h.regs.h &= 0xff; if(h.regs.h) h.f_reset_zero(); else h.f_set_zero(); return {pc: 1, cycle: 4};}
function DEC_HLM(h){ h.f_set_sub(); let addr = (h.regs.h << 8) + h.regs.l; let v = h.mmu.read_byte(addr); if(half_carry_sub8(v, 1)) h.f_set_hcarry(); else h.f_reset_hcarry(); let nv = (v - 1) & 0xff; h.mmu.write_byte(addr, nv); if(nv) h.f_reset_zero(); else h.f_set_zero(); return {pc: 1, cycle: 12};}

function DEC_C(h){ h.f_set_sub(); if(half_carry_sub8(h.regs.c, 1)) h.f_set_hcarry(); else h.f_reset_hcarry(); h.regs.c--; h.regs.c &= 0xff; if(h.regs.c) h.f_reset_zero(); else h.f_set_zero(); return {pc: 1, cycle: 4};}
function DEC_E(h){ h.f_set_sub(); if(half_carry_sub8(h.regs.e, 1)) h.f_set_hcarry(); else h.f_reset_hcarry(); h.regs.e--; h.regs.e &= 0xff; if(h.regs.e) h.f_reset_zero(); else h.f_set_zero(); return {pc: 1, cycle: 4};}
function DEC_L(h){ h.f_set_sub(); if(half_carry_sub8(h.regs.l, 1)) h.f_set_hcarry(); else h.f_reset_hcarry(); h.regs.l--; h.regs.l &= 0xff; if(h.regs.l) h.f_reset_zero(); else h.f_set_zero(); return {pc: 1, cycle: 4};}
function DEC_A(h){ h.f_set_sub(); if(half_carry_sub8(h.regs.a, 1)) h.f_set_hcarry(); else h.f_reset_hcarry(); h.regs.a--; h.regs.a &= 0xff; if(h.regs.a) h.f_reset_zero(); else h.f_set_zero(); return {pc: 1, cycle: 4};}


//XORs
function XOR_A(h){ h.regs.a ^= h.regs.a; h.f_reset(); h.f_set_zero(); return {pc: 1, cycle: 4};}
function XOR_B(h){ h.regs.a ^= h.regs.b; h.f_reset(); if(h.regs.a === 0x0){ h.f_set_zero();} return {pc: 1, cycle: 4};}
function XOR_C(h){ h.regs.a ^= h.regs.c; h.f_reset(); if(h.regs.a === 0x0){ h.f_set_zero();} return {pc: 1, cycle: 4};}
function XOR_D(h){ h.regs.a ^= h.regs.d; h.f_reset(); if(h.regs.a === 0x0){ h.f_set_zero();} return {pc: 1, cycle: 4};}
function XOR_E(h){ h.regs.a ^= h.regs.e; h.f_reset(); if(h.regs.a === 0x0){ h.f_set_zero();} return {pc: 1, cycle: 4};}
function XOR_H(h){ h.regs.a ^= h.regs.h; h.f_reset(); if(h.regs.a === 0x0){ h.f_set_zero();} return {pc: 1, cycle: 4};}
function XOR_L(h){ h.regs.a ^= h.regs.l; h.f_reset(); if(h.regs.a === 0x0){ h.f_set_zero();} return {pc: 1, cycle: 4};}
function XOR_HL(h){h.regs.a ^= h.mmu.read_byte((h.regs.h << 8) + h.regs.l); h.f_reset(); if(h.regs.a === 0x0){ h.f_set_zero();} return {pc: 1, cycle: 8};}
function XOR_IMM8(h){h.regs.a ^= h.mmu.read_byte(h.regs.pc + 1); h.f_reset(); if(h.regs.a === 0x0){ h.f_set_zero();} return {pc: 2, cycle: 8};}

//CP
function CP_IMM8(h){let imm = h.mmu.read_byte(h.regs.pc + 1);if(h.regs.a === imm) h.f_set_zero(); else h.f_reset_zero(); h.f_set_sub(); if(half_carry_sub8(h.regs.a - imm)) h.f_set_hcarry(); else h.f_reset_hcarry(); if(h.regs.a < imm) h.f_set_carry(); else h.f_reset_carry(); return {pc: 2, cycle: 8};}

//16 bit INCs
function INC_BC(h){ if(!(h.regs.c = (h.regs.c + 1) & 0xff)) h.regs.b = (h.regs.b + 1) & 0xff; return {pc: 1, cycle: 8};}
function INC_DE(h){ if(!(h.regs.e = (h.regs.e + 1) & 0xff)) h.regs.d = (h.regs.d + 1) & 0xff; return {pc: 1, cycle: 8};}
function INC_HL(h){ if(!(h.regs.l = (h.regs.l + 1) & 0xff)) h.regs.h = (h.regs.h + 1) & 0xff; return {pc: 1, cycle: 8};}
function INC_SP(h){ h.regs.sp = (h.regs.sp + 1) & 0xffff; return {pc: 1, cycle: 8};}

//16 bit DECs
function DEC_BC(h){ if((h.regs.c = (h.regs.c - 1) & 0xff) === 0xff) h.regs.b = (h.regs.b - 1) & 0xff; return {pc: 1, cycle: 8};}
function DEC_DE(h){ if((h.regs.e = (h.regs.e - 1) & 0xff) === 0xff) h.regs.d = (h.regs.d - 1) & 0xff; return {pc: 1, cycle: 8};}
function DEC_HL(h){ if((h.regs.l = (h.regs.l - 1) & 0xff) === 0xff) h.regs.h = (h.regs.h - 1) & 0xff; return {pc: 1, cycle: 8};}
function DEC_SP(h){ h.regs.sp = (h.regs.sp - 1) & 0xffff; return {pc: 1, cycle: 8};}

//Rotation and Bit shift
function RLCA(h){ h.f_reset(); if(h.regs.a & 0x80) h.f_set_carry(); h.regs.a = rotate(h.regs.a, 1); return {pc: 1, cycle: 4};}
function RLA(h) { let l = h.f_carry();h.f_reset();if(h.regs.a & 0x80) h.f_set_carry();h.regs.a = ((h.regs.a << 1) & 0xff) + l; return {pc: 1, cycle: 4};}
function RRCA(h){h.f_reset();if(h.regs.a & 0x01) h.f_set_carry();h.regs.a = rotate(h.regs.a, -1);return {pc: 1, cycle: 4};}
function RRA(h) {let l = h.f_carry();h.f_reset();if(h.regs.a & 0x01) h.f_set_carry();h.regs.a = ((h.regs.a >> 1) & 0xff) + (l << 7);return {pc: 1, cycle: 4};}

function HALT(h) { throw "CPU Halted :(";}

//Helpers
function to_signed_int8(v) {
    if(v & 0x80) {
        return -(~v & 0xff) - 1;
    }
    else return v & 0xff;
}

function rotate(value, vector){
    let wrapped = vector % 8;
    if(!wrapped) return value;
    if(wrapped < 0) wrapped += 8;
    return ((value << wrapped) | (value >> (8 - wrapped))) & 0xff;
}

function half_carry_add8(a, b){ return ((a & 0xf) + (b & 0xf)) & 0x10 === 0x10;}
function half_carry_add16(a, b){ return ((a & 0xfff) + (b & 0xfff)) & 0x1000 === 0x1000;}
function half_carry_sub8(a, b){ return ((a & 0xf) - (b & 0xf)) < 0;}

function EXT(h){
    let op = h.mmu.read_byte(h.regs.pc + 1);
    return {pc: 2, cycle: ext_handler(h, op)};
}

function handler(h, code){
    switch (code & 0xc0) {
        case 0x40: return general_loads(h, code);
        case 0x80: return general_alu(h, code);
        default:
            if(!(code in map))
                throw `Fatal: 0x${code.toString(16)} not implemented`;
            return map[code](h);
    }
}

function general_loads(h, code){
    let to = (code >> 3) & 0x7;
    let from = code & 0x7;
    if(to === 0x6 && from === 0x6) return map[code](h);
    else if(to === 0x6){
        h.mmu.write_byte(h.get_reg(to), h.get_reg(from));
        return {pc: 1, cycle: 8};
    } else if(from === 0x6){
        h.set_reg(to, h.mmu.read_byte(h.get_reg(from)));
        return {pc: 1, cycle: 8};
    }

    h.set_reg(to, h.get_reg(from));
    return {pc: 1, cycle: 4};
}

function general_alu(h, code){
    let alu_code = (code >> 3) & 0x7;
    let reg_addr = code & 0x7;
    let rf = GET_REG(h, reg_addr);
    h.f_reset(); //Since all ALU instructions reset all flags.
    switch (alu_code) {
        case 0x0: { //ADD
            let t = h.regs.a + rf;
            change_half_carry(h, half_carry_add8(h.regs.a, rf));
            change_carry(h, t > 0xff);
            change_zero(h, t === 0);
            h.f_reset_sub();
            h.regs.a = rf & 0xff;
            break;
        }

        case 0x1: { //ADC
            let t = h.regs.a + rf + (h.f_carry()? 1 : 0);
            change_half_carry(h, half_carry_add8(h.regs.a, rf + (h.f_carry()? 1 : 0)));
            change_carry(h, t > 0xff);
            change_zero(h, t === 0);
            h.f_reset_sub();
            h.regs.a = rf & 0xff;
            break;
        }

        case 0x2: { //SUB
            let t = h.regs.a - rf;
            change_half_carry(h, half_carry_sub8(h.regs.a, rf));
            change_carry(h, t < 0);
            change_zero(h, t === 0);
            h.f_set_sub();
            h.regs.a = rf & 0xff;
            break;
        }

        case 0x3: { //SBC
            let t = h.regs.a - (rf + (h.f_carry()? 1 : 0));
            change_half_carry(h, half_carry_sub8(h.regs.a, (rf + (h.f_carry()? 1 : 0))));
            change_carry(h, t < 0);
            change_zero(h, t === 0);
            h.f_set_sub();
            h.regs.a = rf & 0xff;
            break;
        }

        case 0x4: { //AND
            let t = h.regs.a & rf;
            change_zero(h, t === 0);
            h.f_set_hcarry();
            h.regs.a = t;
            break;
        }

        case 0x5: { //XOR
            let t = h.regs.a ^ rf;
            change_zero(h, t === 0);
            h.regs.a = t;
            break;
        }

        case 0x6: { //OR
            let t = h.regs.a | rf;
            change_zero(h, t === 0);
            h.regs.a = t;
            break;
        }

        case 0x7: { //CP
            let t = h.regs.a - rf;
            change_half_carry(h, half_carry_sub8(h.regs.a, rf));
            change_carry(h, t < 0);
            change_zero(h, t === 0);
            h.f_set_sub();
            break;
        }

        default: throw "Something bad has happened.";
    }

    return reg_addr === 0x6? {pc: 1, cycle: 8} : {pc: 1, cycle: 4};
}

function change_half_carry(h, s){ if(s) h.f_set_hcarry(); else h.f_reset_hcarry();}
function change_carry(h, s){ if(s) h.f_set_carry(); else h.f_reset_carry();}
function change_zero(h, s){ if(s) h.f_set_zero(); else h.f_reset_zero();}

map = {
    0x00: NOP,
    0x07: RLCA, 0x17: RLA, 0x0f: RRCA, 0x1f: RRA,
    0x0a: LD_A_BCM, 0x1a: LD_A_DEM, 0x2a: LD_A_HLMI, 0x3a: LD_A_HLMD,
    0x06: LD_B_IMM8, 0x16: LD_D_IMM8, 0x26: LD_H_IMM8, 0x36: LD_HLM_IMM8,
    0x0e: LD_C_IMM8, 0x1e: LD_E_IMM8, 0x2e: LD_L_IMM8, 0x3e: LD_A_IMM8,
    0x01: LD_BC_IMM16, 0x11: LD_DE_IMM16, 0x21: LD_HL_IMM16, 0x31: LD_SP_IMM16,
    0x02: LD_BCM_A, 0x12: LD_DEM_A, 0x22: LD_HLMI_A, 0x32: LD_HLMD_A,
    0x18: JR,
    0x20: JR_NZ, 0x28: JR_Z, 0x30: JR_NC, 0x38: JR_C,
    0x3c: INC_A, 0x04: INC_B, 0x0c: INC_C, 0x14: INC_D, 0x1c: INC_E, 0x24: INC_H, 0x2c: INC_L, 0x34: INC_HLM,
    0x3d: DEC_A, 0x05: DEC_B, 0x0d: DEC_C, 0x15: DEC_D, 0x1d: DEC_E, 0x25: DEC_H, 0x2d: DEC_L, 0x35: DEC_HLM,
    0x76: HALT,
    0x77: LD_HLM_A,
    0x03: INC_BC, 0x13: INC_DE, 0x23: INC_HL, 0x33: INC_SP,
    0x0b: DEC_BC, 0x1b: DEC_DE, 0x2b: DEC_HL, 0x3b: DEC_SP,
    0xa8: XOR_B, 0xa9: XOR_C, 0xaa: XOR_D, 0xab: XOR_E, 0xac: XOR_H, 0xad: XOR_L, 0xae: XOR_HL, 0xaf: XOR_A, 0xee: XOR_IMM8,
    0xc9: RET,
    0xcd: CALL_IMM16,
    0xe0: LD_HIMM8_A, 0xf0: LD_A_HIMM8,
    0xe2: LD_CM_A, 0xf2: LD_A_CM,
    0xea: LD_IMM16M_A, 0xfa: LD_A_IMM16M,
    0xf1: POP_AF, 0xc1: POP_BC, 0xd1: POP_DE, 0xe1: POP_HL,
    0xf5: PUSH_AF, 0xc5: PUSH_BC, 0xd5: PUSH_DE, 0xe5: PUSH_HL,
    0xfe: CP_IMM8,

    0xcb: EXT
};

module.exports = handler;
},{"./cpu_instructions_ext.js":5}],5:[function(require,module,exports){

function ext_handler(h, extcode){
    
    switch (extcode & 0xc0) {
        case 0x00:
            let fop = (extcode >> 3) & 0x7;
            let reg_addr = extcode & 0x07;
            switch (fop) {
                case 0x00:
                    ROTATE(h, reg_addr, 1);
                    return 8;

                case 0x01:
                    ROTATE(h, reg_addr, -1);
                    return 8;

                case 0x02:
                    let l = h.f_carry();
                    h.f_reset();
                    if(GET_REG(h, reg_addr) & 0x80) h.f_set_carry();
                    let tt = ((GET_REG(h, reg_addr) << 1) & 0xff) + l;
                    SET_REG(h, reg_addr, tt);
                    return 8;

                case 0x03:
                    let r = h.f_carry();
                    h.f_reset();
                    if(GET_REG(h, reg_addr) & 0x01) h.f_set_carry();
                    SET_REG(h, reg_addr, ((GET_REG(h, reg_addr) >> 1) & 0xff) + (r << 7));
                    return 8;

                default:
                    throw `Fatal: EXT_FIRST_ROW$0x${extcode.toString(16)} not implemented`;
            }

        case 0x40: //[xx|xxx|xxx] opcode|b|register
            let addr = extcode & 0x7;
            let b = (extcode >> 3) & 0x7;
            BIT(h, b, addr);
            return addr === 0x6 ? 16 : 8;
    }
    
    throw `Fatal: EXT$0x${extcode.toString(16)} not implemented`;
}


function GET_REG(h, addr){
    if(addr === 0x06) return h.mmu.read_byte(h.get_reg(addr));
    return h.get_reg(addr);
}

function SET_REG(h, addr, v){
    if(addr === 0x06){
        h.mmu.write_byte(h.get_reg(addr), v);
        return;
    }
    h.set_reg(addr, v);
}

/**
 * TODO: refactor with GET_REG and SET_REG
 * @return {number}
 */
function ROTATE(h, addr, vector){
    h.f_reset();
    let value = addr === 0x06? h.mmu.read_byte(h.get_reg(addr)) : h.get_reg(addr);
    if(value & (vector > 0? 0x80 : 0x01)) h.f_set_carry();
    let wrapped = vector % 8;
    if(!wrapped) return value;
    if(wrapped < 0) wrapped += 8;
    let res = ((value << wrapped) | (value >> (8 - wrapped))) & 0xff;
    if(!res) h.f_set_zero();
    if(addr === 0x06) h.mmu.write_byte(h.get_reg(addr), res);
    else h.set_reg(addr, res);
}

/*
 * TODO: refactor with GET_REG and SET_REG
 */
function BIT(h, b, addr){
    let v = addr === 0x06 ? h.mmu.read_byte(h.get_reg(addr)) : h.get_reg(addr);
    let res = v & (0x1 << b);
    if(res === 0) h.f_set_zero();
    else h.f_reset_zero();

    h.f_reset_sub();
    h.f_reset_hcarry();
}

module.exports = {
    ext_handler,
    GET_REG,
    SET_REG
};
},{}],6:[function(require,module,exports){
let array8 = [0,1,2,3,4,5,6,7];

class GPU{
    constructor(){
        this.screen_out = Array(160 * 144).fill(0);

        this.vram = Array(0x2000).fill(0);
        this.lcdc = 0;
        this.stat = 0;

        this.scy = 0; this.scx = 0; //background scroll
        this.ly = 0; // current drawing line
        this.lyc = 0; //line compare
        this.wy = 0; this.wx = 0; //window position

        this.bg_pal = 0;
        this.obj_pal0 = 0;
        this.obj_pal1 = 0;

        this.clock = 0;
        this.frames = 0;
        // this.mode_cycles = [207, 4560, 83, 175]; // HBlank, VBlank, OAM Read, OAM and VRAM Read
    }

    set_lcd_enable(e){let code = e << 7; this.lcdc = (this.lcdc & ~code) | code;}
    lcd_enabled(){return this.lcdc & 0x80;}
    set_window_tilemap(v){ let code = v << 6; this.lcdc = (this.lcdc & ~code) | code; throw "GPU: Window not implemented.";}
    window_tilemap(){ return this.lcdc & 0x40;}
    set_window_enable(e){ let code = e << 5; this.lcdc = (this.lcdc & ~code) | code; throw "GPU: Window not implemented.";}
    window_enabled(){ return this.lcdc & 0x20;}
    set_tile_data_select(v){ let code = v << 4; this.lcdc = (this.lcdc & ~code) | code;}
    tile_data_select(){return this.lcdc & 0x10;}
    set_background_tilemap(v){let code = v << 3; this.lcdc = (this.lcdc & ~code) | code;}
    background_tilemap(){return this.lcdc * 0x8;}
    set_sprite_size(v){let code = v << 2; this.lcdc = (this.lcdc & ~code) | code;}
    sprite_size(){return this.lcdc & 0x4;}
    set_sprite_enable(e){let code = e << 1; this.lcdc = (this.lcdc & ~code) | code; throw "GPU: Sprite not implemented."}
    sprite_enabled(){return this.lcdc & 0x2;}
    set_background_enabled(v){let code = v << 0; this.lcdc = (this.lcdc & ~code) | code;}
    background_enabled(){return this.lcdc & 0x1;}

    mode(){ return this.stat & 0x3;}
    set_mode(m){
        this.stat = (this.stat & 0xfc) | m;
    }

    reset(){
        this.screen_out = Array(160 * 144).fill(0);

        this.vram = Array(0x2000).fill(0);
        this.lcdc = 0;
        this.stat = 0;

        this.scy = 0; this.scx = 0;
        this.ly = 0;
        this.lyc = 0;
        this.wy = 0; this.wx = 0;

        this.bg_pal = 0;
        this.obj_pal0 = 0;
        this.obj_pal1 = 0;

        this.clock = 0;
        this.frames = 0;
    }

    tick(cycles){
        if(!this.lcd_enabled()){
            // this.reset();
            return;
        }

        this.clock += cycles;
        if(this.clock > 456){
            this.clock = this.clock - 456;
            this.ly++;
        }

        this.tick_line();
    }

    tick_line(){
        let should_renderer = false;
        //A cycle is finished
        if(this.ly > 153) this.ly = 0;

        //During VBlank
        if(this.ly > 143 && this.mode() !== 1){
            this.set_mode(1);
            //TODO: VBlank Interrupt
            this.frames++;
            // if(this.frames % 20 === 0) this.print_screen();
            return;
        }
        if(this.ly > 143) return; //If in VBlank, there is nothing to do.

        //Line number is less than 144, normal drawing..
        //During OAM Read
        if(this.clock <= 80 && this.mode() !== 2){
            this.set_mode(2);
            //TODO: OAM STAT Interrupt..
        }

        if(this.clock > 80 && this.clock <= 252 && this.mode() !== 3 && this.mode() !== 1){
            this.set_mode(3);
            //TODO: All Interrupt
            //really ?
        }

        //During HBlank
        if(this.clock > 252 && this.mode() !== 0 && this.mode() !== 1){
            this.set_mode(0);
            //TODO: HBlank Interrupt
            should_renderer = true;
        }

        if(!should_renderer) return;

        if(this.background_enabled()) this.draw_background(this.ly);
        //TODO: draw this line
    }

    draw_background(l){
        let tm_offset = this.background_tilemap()? 0x9800 : 0x9c00;
        let tile_y = ((l + this.scy) & 0xff) >> 3; //warp and divide by 8.
        let y = (l + this.scy) & 0x7;

        for(let x = 0; x < 160; x++){
            let tile_x = ((this.scx + x) & 0xff) >> 3;

            let t_addr = this.read_byte(tm_offset + tile_y * 32 + tile_x);
            let tile = this.tile_at(t_addr);

            this.screen_out[160 * l + x] = this.color_for(this.bg_pal, tile[y][(x + this.scx) & 7]);
        }
    }

    tile_at(addr){
        let offset = this.tile_data_select()? 0x8000 : 0x9000;
        addr = this.tile_data_select()? addr : to_signed_int8(addr);

        let d = [...Array(16).keys()].map(i => bitarray8(this.read_byte(offset + addr + i)));
        return array8.map(i =>
            array8.map(bit =>
               d[i * 2][bit] + d[i * 2 + 1][bit] * 2
           )
        );
    }

    debug_draw_tile1(){
        let sc = Array(256 * 256).fill(0);

    }

    color_for(palette, v){
        let p = bitarray8(palette);
        let b = 3 - v;
        return p[b*2] + (p[b*2+1] << 1);
    }

    read_byte(addr){
        switch (addr & 0xf000) {

            case 0x8000:
            case 0x9000:
                return this.vram[addr & 0x1fff];

            case 0xf000:
                switch(addr){
                    case 0xff40: return this.lcdc;
                    case 0xff41: return this.stat;
                    case 0xff42: return this.scy;
                    case 0xff43: return this.scx;
                    case 0xff44: return this.ly;
                    case 0xff45: return this.lyc;
                    case 0xff4a: return this.wy;
                    case 0xff4b: return this.wx;
                    case 0xff47: return this.bg_pal;
                    case 0xff48: return this.obj_pal0;
                    case 0xff49: return this.obj_pal1;
                    default: throw `GPU: Unknown address ${addr.toString(16)}`;
                }

            default:
                throw `GPU: Unknown address ${addr.toString(16)}`;
        }
    }

    write_byte(addr, v){
        switch (addr & 0xf000) {

            case 0x8000:
            case 0x9000:
                this.vram[addr & 0x1fff] = v;
                break;

            case 0xf000:
                switch (addr) {
                    case 0xff40: this.lcdc = v; break;
                    case 0xff41: throw "GPU: Interrupt select not implemented.";//return this.stat;
                    case 0xff42: this.scy = v; break;
                    case 0xff43: this.scx = v; break;
                    case 0xff44: throw "GPU: Don't fuck with line counter.";
                    case 0xff45: throw "GPU: LYC not implemented.";
                    case 0xff4a: this.wy = v; break;
                    case 0xff4b: this.wx = v; break;
                    case 0xff47: this.bg_pal = v; break;
                    case 0xff48: this.obj_pal0 = v; break;
                    case 0xff49: this.obj_pal1 = v; break;
                    default: throw `GPU: Writing to unknown address ${addr.toString(16)}`;
                }
                break;

            default:
                throw `GPU: Writing to unknown address ${addr.toString(16)}`;
        }
    }

    print_screen(){
        let s = "";
        for(let y = 0; y < 144; y++){
            for(let x = 0; x < 160; x++){
                s += this.screen_out[y * 160 + x].toString();
            }
            s += "\n";
        }
        console.log(s);
    }
}

//Helper
function to_signed_int8(v) {
    if(v & 0x80) {
        return -(~v & 0xff) - 1;
    }

    else return v & 0xff;
}


function bit_at(num, index){ return num & (0x1 << index);}

function bitarray8(v){
    return [...Array(8).keys()].map(i => (v >> (7 - i)) & 1);
}


module.exports = GPU;
},{}],7:[function(require,module,exports){
class MemoryController{
    constructor(cartridge, gpu){
        this.cpu = null;
        this.gpu = gpu;
        this.boot_rom = [
            0x31, 0xFE, 0xFF, 0xAF, 0x21, 0xFF, 0x9F, 0x32, 0xCB, 0x7C, 0x20, 0xFB, 0x21, 0x26, 0xFF, 0x0E, //16
            0x11, 0x3E, 0x80, 0x32, 0xE2, 0x0C, 0x3E, 0xF3, 0xE2, 0x32, 0x3E, 0x77, 0x77, 0x3E, 0xFC, 0xE0, //32
            0x47, 0x11, 0x04, 0x01, 0x21, 0x10, 0x80, 0x1A, 0xCD, 0x95, 0x00, 0xCD, 0x96, 0x00, 0x13, 0x7B, //48
            0xFE, 0x34, 0x20, 0xF3, 0x11, 0xD8, 0x00, 0x06, 0x08, 0x1A, 0x13, 0x22, 0x23, 0x05, 0x20, 0xF9, //64
            0x3E, 0x19, 0xEA, 0x10, 0x99, 0x21, 0x2F, 0x99, 0x0E, 0x0C, 0x3D, 0x28, 0x08, 0x32, 0x0D, 0x20, //80
            0xF9, 0x2E, 0x0F, 0x18, 0xF3, 0x67, 0x3E, 0x64, 0x57, 0xE0, 0x42, 0x3E, 0x91, 0xE0, 0x40, 0x04, //96
            0x1E, 0x02, 0x0E, 0x0C, 0xF0, 0x44, 0xFE, 0x90, 0x20, 0xFA, 0x0D, 0x20, 0xF7, 0x1D, 0x20, 0xF2, //112
            0x0E, 0x13, 0x24, 0x7C, 0x1E, 0x83, 0xFE, 0x62, 0x28, 0x06, 0x1E, 0xC1, 0xFE, 0x64, 0x20, 0x06, //128
            0x7B, 0xE2, 0x0C, 0x3E, 0x87, 0xE2, 0xF0, 0x42, 0x90, 0xE0, 0x42, 0x15, 0x20, 0xD2, 0x05, 0x20, //144
            0x4F, 0x16, 0x20, 0x18, 0xCB, 0x4F, 0x06, 0x04, 0xC5, 0xCB, 0x11, 0x17, 0xC1, 0xCB, 0x11, 0x17,
            0x05, 0x20, 0xF5, 0x22, 0x23, 0x22, 0x23, 0xC9, 0xCE, 0xED, 0x66, 0x66, 0xCC, 0x0D, 0x00, 0x0B,
            0x03, 0x73, 0x00, 0x83, 0x00, 0x0C, 0x00, 0x0D, 0x00, 0x08, 0x11, 0x1F, 0x88, 0x89, 0x00, 0x0E,
            0xDC, 0xCC, 0x6E, 0xE6, 0xDD, 0xDD, 0xD9, 0x99, 0xBB, 0xBB, 0x67, 0x63, 0x6E, 0x0E, 0xEC, 0xCC,
            0xDD, 0xDC, 0x99, 0x9F, 0xBB, 0xB9, 0x33, 0x3E, 0x3c, 0x42, 0xB9, 0xA5, 0xB9, 0xA5, 0x42, 0x4C,
            0x21, 0x04, 0x01, 0x11, 0xA8, 0x00, 0x1A, 0x13, 0xBE, 0x20, 0xFE, 0x23, 0x7D, 0xFE, 0x34, 0x20,
            0xF5, 0x06, 0x19, 0x78, 0x86, 0x23, 0x05, 0x20, 0xFB, 0x86, 0x20, 0xFE, 0x3E, 0x01, 0xE0, 0x50
        ];

        this.cc = cartridge;
        this.boot_rom_mapped = true;
        this.internal_ram = Array(0x2000).fill(0);
        this.high_speed_ram = Array(0x80).fill(0);
    }

    remove_boot_rom(){
        this.boot_rom_mapped = false;
    }

    read_byte(addr){
        if(this.boot_rom_mapped && addr < 0x100)
            return this.boot_rom[addr];

        switch (addr & 0xf000) {
            case 0x0000:
            case 0x1000:
            case 0x2000:
            case 0x3000:
            case 0x4000:
            case 0x5000:
            case 0x6000:
            case 0x7000:
                //ROM in cartridge, forward to cartridge controller :)
                return this.cc.read_byte(addr);

            case 0x8000:
            case 0x9000:
                //GPU VRAM, forward to GPU.
                return this.gpu.read_byte(addr);

            case 0xc000:
            case 0xd000:
            case 0xe000:
                //Access to 8k internal RAM. and first haft of shadow RAM.
                //Shadow RAM is just a waste of address space, a copy of 8k RAM.
                return this.internal_ram[addr & 0x1fff];

            case 0xf000:
                //Interrupt Vector
                if(addr === 0xffff) throw `Interrupt not implemented.`;
                //Interrupt Request
                if(addr === 0xff0f) throw `Interrupt request not implemented.`;

                //Access to last haft of shadow RAM, and I/O, Interrupt, etc
                let mask = addr & 0xf00;
                if(mask < 0xe00) return this.internal_ram[addr & 0x1fff];
                if(mask >= 0xf00){
                    let sec_mask = addr & 0xff;

                    //GPU I/O Registers
                    if(sec_mask >= 0x40 && sec_mask < 0x50) return this.gpu.read_byte(addr);
                    //Zero Page RAM
                    if(sec_mask >= 0x80) return this.high_speed_ram[addr & 0x7f];
                }

                console.warn(`MMU: Reading I/O blocks: ${addr.toString(16)}`);
                break;
            default:
                console.warn(`MMU: Reading from unknown address mapping: ${addr.toString(16)}`);
        }
    }

    read_word(addr){
        return this.read_byte(addr) + (this.read_byte(addr + 1) << 8);
    }

    write_byte(addr, v){
        if(typeof v === "undefined") throw "Man, check your code, cant write invalid byte"; //Debug

        switch (addr & 0xf000) {
            case 0x0000:
            case 0x1000:
            case 0x2000:
            case 0x3000:
            case 0x4000:
            case 0x5000:
            case 0x6000:
            case 0x7000:
                //Write to ROM, sound weird, right? Never mind just forward to cartridge controller :)
                this.cc.write_byte(addr, v);
                break;

            case 0xc000:
            case 0xd000:
            case 0xe000:
                this.internal_ram[addr & 0x1fff] = v;
                break;

            case 0x8000:
            case 0x9000:
                this.gpu.write_byte(addr, v);
                break;

            case 0xf000:
                if(addr === 0xffff) throw `Interrupt not implemented.`;
                if(addr === 0xff0f) throw `Interrupt request not implemented.`;
                let mask = addr & 0xf00;
                if(mask < 0xe00){
                    this.internal_ram[addr & 0x1fff] = v;
                    break;
                }

                if(mask >= 0xf00){
                    let sec_mask = addr & 0xff;

                    //GPU I/O Registers
                    if(sec_mask >= 0x40 && sec_mask < 0x50){
                        this.gpu.write_byte(addr, v);
                        break;
                    }

                    //Zero Page RAM
                    if(sec_mask >= 0x80){
                        this.high_speed_ram[addr & 0x7f] = v;
                        break;
                    }
                }

                console.warn(`MMU: Writing I/O blocks: ${addr.toString(16)}`);
                break;
            default:
                console.warn(`MMU: Writing to unknown address mapping: ${addr.toString(16)}, PC: ${this.cpu.regs.pc.toString(16)}, INS: ${this.read_byte(this.cpu.regs.pc)}`);
        }
    }


    write_word(addr, v){
        this.write_byte(addr, v & 0xff);
        this.write_byte(addr + 1, v >> 8);
    }
}

module.exports = MemoryController;
},{}],8:[function(require,module,exports){
const CPU = require('../cpu/cpu.js');
const GPU = require('../gpu.js');
const MMU = require('../memory_controller.js');
const CC = require('../cartridge_controller.js');

let cartridge = new CC('t');
let gpu = new GPU();
let mmu = new MMU(cartridge, gpu);
let cpu = new CPU(mmu);

let colorMap = {
    3: 255,
    2: 150,
    1: 80,
    0: 0
};

var canvas, ctx, imageData;

window.onload=function(){
    canvas = document.getElementById('screen');
    ctx = canvas.getContext('2d');
    imageData = ctx.createImageData(160,144);

    for(let i=0; i<160*144*4; i++)
        imageData.data[i] = 50;

    ctx.putImageData(imageData, 0, 0);

    // setInterval(tick_frame, 0.01);

    let button = document.getElementById("draw_button");
    button.onclick = function () {
        draw_tile();
    }
};

function tick_frame() {
    let cur_f = gpu.frames;
    while(gpu.frames === cur_f){
        let elapsed = cpu.tick();
        gpu.tick(elapsed);
    }

    for(let i=0; i<160*144; i++){
        let c = colorMap[gpu.screen_out[i]];
        imageData.data[i*4] = c;
        imageData.data[i*4+1] = c;
        imageData.data[i*4+2] = c;
        imageData.data[i*4+3] = 255;
    }

    ctx.putImageData(imageData, 0, 0);

    console.log("frame");
}

function draw_tile(){
    let c = document.createElement('canvas');
    canvas.width = 8;
    canvas.height = 8;
    let ctx = c.getContext('2d');
    ctx.fillStyle = "rgba(255, 0, 0, 1)";
    ctx.fillRect(0,0,8,8);
}

// while(true){
//     let elapsed = cpu.tick();
//     gpu.tick(elapsed);
// };
},{"../cartridge_controller.js":1,"../cpu/cpu.js":3,"../gpu.js":6,"../memory_controller.js":7}],9:[function(require,module,exports){

},{}]},{},[8]);