diff --git a/ArchImpl/RV32IMACFD/CMakeLists.txt b/ArchImpl/RV32IMACFD/CMakeLists.txt
index d879229ee0..b39a43b380 100644
--- a/ArchImpl/RV32IMACFD/CMakeLists.txt
+++ b/ArchImpl/RV32IMACFD/CMakeLists.txt
@@ -1,4 +1,4 @@
-# Generated on Mon, 02 Oct 2023 18:56:15 +0200.
+# Generated on Fri, 03 Nov 2023 13:22:23 +0100.
 #
 # This file contains the CMake build info for the RV32IMACFD core architecture.
 
@@ -11,6 +11,7 @@ ADD_LIBRARY(${PROJECT_NAME} SHARED
 	RV32IMACFDArch.cpp
 	RV32IMACFDArchLib.cpp
 	RV32IMACFDArchSpecificImp.cpp
+	RV32IMACFDFuncs.c
 	RV32IMACFDInstr.cpp
 	RV32IMACFD_RV32IInstr.cpp
 	RV32IMACFD_RV32ICInstr.cpp
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD.h b/ArchImpl/RV32IMACFD/RV32IMACFD.h
index a11f9b4860..82269635a2 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFD.h
+++ b/ArchImpl/RV32IMACFD/RV32IMACFD.h
@@ -1,5 +1,5 @@
 /**
- * Generated on Mon, 02 Oct 2023 18:56:15 +0200.
+ * Generated on Fri, 03 Nov 2023 13:22:23 +0100.
  *
  * This file contains the registers for the RV32IMACFD core architecture.
  */
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFDArch.cpp b/ArchImpl/RV32IMACFD/RV32IMACFDArch.cpp
index a9526b644e..45ac32cd06 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFDArch.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFDArch.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Mon, 02 Oct 2023 18:56:15 +0200.
+ * Generated on Fri, 03 Nov 2023 13:22:23 +0100.
  *
  * This file contains the architecture class for the RV32IMACFD core architecture.
  */
@@ -35,8 +35,6 @@
  *********************************************************************************************************************************/
 
 #include "RV32IMACFDArch.h"
-
-#define ETISS_ARCH_STATIC_FN_ONLY
 #include "RV32IMACFDFuncs.h"
 
 #define RV32IMACFD_DEBUG_CALL 0
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFDArch.h b/ArchImpl/RV32IMACFD/RV32IMACFDArch.h
index 0684724910..f985a923fc 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFDArch.h
+++ b/ArchImpl/RV32IMACFD/RV32IMACFDArch.h
@@ -1,5 +1,5 @@
 /**
- * Generated on Mon, 02 Oct 2023 18:56:15 +0200.
+ * Generated on Fri, 03 Nov 2023 13:22:23 +0100.
  *
  * This file contains the architecture class for the RV32IMACFD core architecture.
  */
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFDArchLib.cpp b/ArchImpl/RV32IMACFD/RV32IMACFDArchLib.cpp
index 1d13aad6a0..83c9616a9a 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFDArchLib.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFDArchLib.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Mon, 02 Oct 2023 18:56:15 +0200.
+ * Generated on Fri, 03 Nov 2023 13:22:23 +0100.
  *
  * This file contains the library interface for the RV32IMACFD core architecture.
  */
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFDArchSpecificImp.cpp b/ArchImpl/RV32IMACFD/RV32IMACFDArchSpecificImp.cpp
index 100d8bc3fd..7d9cccec47 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFDArchSpecificImp.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFDArchSpecificImp.cpp
@@ -12,11 +12,7 @@
 
 #include "RV32IMACFDArch.h"
 #include "RV32IMACFDArchSpecificImp.h"
-
-#define ETISS_ARCH_STATIC_FN_ONLY
-extern "C" {
 #include "RV32IMACFDFuncs.h"
-}
 
 /**
 	@brief This function will be called automatically in order to handling exceptions such as interrupt, system call, illegal instructions
@@ -34,9 +30,8 @@ extern "C" {
 */
 etiss::int32 RV32IMACFDArch::handleException(etiss::int32 cause, ETISS_CPU * cpu)
 {
-    translate_exc_code(cpu, nullptr, nullptr, cause);
+	RV32IMACFD_translate_exc_code(cpu, nullptr, nullptr, cause);
 	cpu->instructionPointer = cpu->nextPc;
-
 	return 0;
 }
 
@@ -126,7 +121,7 @@ error_code += R_error_code_0.read(ba) << 0;
 // -----------------------------------------------------------------------------
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, " + std::to_string(error_code) + "ULL);\n";
+cp.code() += "RV32IMACFD_translate_exc_code(cpu, system, plugin_pointers, " + std::to_string(error_code) + "ULL);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -173,7 +168,7 @@ error_code += R_error_code_0.read(ba) << 0;
 // -----------------------------------------------------------------------------
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, " + std::to_string(error_code) + "ULL);\n";
+cp.code() += "RV32IMACFD_translate_exc_code(cpu, system, plugin_pointers, " + std::to_string(error_code) + "ULL);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFDArchSpecificImp.h b/ArchImpl/RV32IMACFD/RV32IMACFDArchSpecificImp.h
index 558a1ab560..eb94b75582 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFDArchSpecificImp.h
+++ b/ArchImpl/RV32IMACFD/RV32IMACFDArchSpecificImp.h
@@ -1,5 +1,5 @@
 /**
- * Generated on Mon, 02 Oct 2023 18:56:15 +0200.
+ * Generated on Fri, 03 Nov 2023 13:22:23 +0100.
  *
  * This file contains the architecture specific header for the RV32IMACFD
  * core architecture.
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFDFuncs.c b/ArchImpl/RV32IMACFD/RV32IMACFDFuncs.c
new file mode 100644
index 0000000000..bf638e23ba
--- /dev/null
+++ b/ArchImpl/RV32IMACFD/RV32IMACFDFuncs.c
@@ -0,0 +1,344 @@
+/**
+ * Generated on Fri, 03 Nov 2023 13:22:23 +0100.
+ *
+ * This file contains the function implementations for the RV32IMACFD core architecture.
+ */
+
+#include "RV32IMACFDFuncs.h"
+
+etiss_uint8 RV32IMACFD_extension_enabled(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers, etiss_int8 extension)
+{
+{ // block
+return (*((RV32IMACFD*)cpu)->CSR[769LL] >> (extension - 65ULL)) & 1ULL;
+} // block
+}
+
+etiss_uint8 RV32IMACFD_get_rm(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers, etiss_uint8 rm)
+{
+{ // block
+if (rm == 7ULL) { // conditional
+rm = ((((((RV32IMACFD*)cpu)->FCSR) >> (5ULL)) & 7)) & 0x7;
+} // conditional
+if (rm > 4ULL) { // conditional
+RV32IMACFD_raise(cpu, system, plugin_pointers, 0ULL, 2LL);
+} // conditional
+return rm;
+} // block
+}
+
+etiss_uint32 RV32IMACFD_sstatus_mask(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers)
+{
+{ // block
+etiss_uint32 mask = 0ULL;
+if (RV32IMACFD_extension_enabled(cpu, system, plugin_pointers, 83ULL)) { // conditional
+{ // block
+mask = mask | 5767458ULL;
+if (RV32IMACFD_extension_enabled(cpu, system, plugin_pointers, 86ULL)) { // conditional
+mask = mask | 1536LL;
+} // conditional
+if (RV32IMACFD_extension_enabled(cpu, system, plugin_pointers, 70ULL)) { // conditional
+mask = mask | 24576LL;
+} // conditional
+if (RV32IMACFD_extension_enabled(cpu, system, plugin_pointers, 88ULL)) { // conditional
+mask = mask | 98304LL;
+} // conditional
+if ((RV32IMACFD_get_field(*((RV32IMACFD*)cpu)->CSR[384LL], 2147483648ULL))) { // conditional
+mask = mask | 262144LL;
+} // conditional
+} // block
+} // conditional
+return mask;
+} // block
+}
+
+etiss_uint32 RV32IMACFD_mstatus_mask(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers)
+{
+{ // block
+etiss_uint32 mask = 6280ULL;
+return mask | RV32IMACFD_sstatus_mask(cpu, system, plugin_pointers);
+} // block
+}
+
+etiss_uint32 RV32IMACFD_csr_read(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers, etiss_uint32 csr)
+{
+{ // block
+if (csr == 1LL) { // conditional
+return *((RV32IMACFD*)cpu)->CSR[3LL] & 31ULL;
+} // conditional
+if (csr == 2LL) { // conditional
+return (*((RV32IMACFD*)cpu)->CSR[3LL] >> 5ULL) & 7ULL;
+} // conditional
+if (csr == 3072LL) { // conditional
+return etiss_get_cycles(cpu, system, plugin_pointers);
+} // conditional
+if (csr == 3200LL) { // conditional
+return etiss_get_cycles(cpu, system, plugin_pointers) >> 32ULL;
+} // conditional
+if (csr == 3073LL) { // conditional
+return etiss_get_time();
+} // conditional
+if (csr == 3201LL) { // conditional
+return etiss_get_time() >> 32ULL;
+} // conditional
+if (csr == 3074LL) { // conditional
+return etiss_get_instret(cpu, system, plugin_pointers);
+} // conditional
+if (csr == 3202LL) { // conditional
+return etiss_get_instret(cpu, system, plugin_pointers) >> 32ULL;
+} // conditional
+if (csr == 768LL || csr == 256LL) { // conditional
+return *((RV32IMACFD*)cpu)->CSR[768LL] | 8589934592ULL | 34359738368ULL;
+} // conditional
+if (csr == 769LL) { // conditional
+return (((1ULL) << 30) | ((((*((RV32IMACFD*)cpu)->CSR[769LL]) >> (0ULL)) & 1073741823)));
+} // conditional
+return *((RV32IMACFD*)cpu)->CSR[csr];
+} // block
+}
+
+void RV32IMACFD_csr_write(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers, etiss_uint32 csr, etiss_uint32 val)
+{
+{ // block
+if (csr == 1LL) { // conditional
+*((RV32IMACFD*)cpu)->CSR[3LL] = (*((RV32IMACFD*)cpu)->CSR[3LL] & 224ULL) | (val & 31ULL);
+} // conditional
+ else if (csr == 2LL) { // conditional
+*((RV32IMACFD*)cpu)->CSR[3LL] = ((val & 7ULL) << 5ULL) | (*((RV32IMACFD*)cpu)->CSR[3LL] & 31ULL);
+} // conditional
+ else if (csr == 3LL) { // conditional
+*((RV32IMACFD*)cpu)->CSR[3LL] = val & 255ULL;
+} // conditional
+ else if (csr == 768LL) { // conditional
+*((RV32IMACFD*)cpu)->CSR[768LL] = val & RV32IMACFD_mstatus_mask(cpu, system, plugin_pointers);
+} // conditional
+ else if (csr == 256LL) { // conditional
+*((RV32IMACFD*)cpu)->CSR[768LL] = val & RV32IMACFD_sstatus_mask(cpu, system, plugin_pointers);
+} // conditional
+ else if (csr != 769LL) { // conditional
+*((RV32IMACFD*)cpu)->CSR[csr] = val;
+} // conditional
+} // block
+}
+
+etiss_uint64 RV32IMACFD_get_field(etiss_uint64 reg, etiss_uint64 mask)
+{
+{ // block
+return (reg & mask) / (mask & ~((mask << 1ULL)));
+} // block
+}
+
+etiss_uint64 RV32IMACFD_set_field(etiss_uint64 reg, etiss_uint64 mask, etiss_uint64 val)
+{
+{ // block
+return ((reg & ~(mask)) | ((val * (mask & ~((mask << 1ULL)))) & mask));
+} // block
+}
+
+etiss_uint8 RV32IMACFD_ctz(etiss_uint64 val)
+{
+{ // block
+if (!(val)) { // conditional
+return 0ULL;
+} // conditional
+etiss_uint8 res = 0ULL;
+if ((val << 32ULL) == 0ULL) { // conditional
+{ // block
+res = res + 32ULL;
+val = val >> 32ULL;
+} // block
+} // conditional
+if ((val << 48ULL) == 0ULL) { // conditional
+{ // block
+res = res + 16ULL;
+val = val >> 16ULL;
+} // block
+} // conditional
+if ((val << 56ULL) == 0ULL) { // conditional
+{ // block
+res = res + 8ULL;
+val = val >> 8ULL;
+} // block
+} // conditional
+if ((val << 60ULL) == 0ULL) { // conditional
+{ // block
+res = res + 4ULL;
+val = val >> 4ULL;
+} // block
+} // conditional
+if ((val << 62ULL) == 0ULL) { // conditional
+{ // block
+res = res + 2ULL;
+val = val >> 2ULL;
+} // block
+} // conditional
+if ((val << 63ULL) == 0ULL) { // conditional
+{ // block
+res = res + 1ULL;
+val = val >> 1ULL;
+} // block
+} // conditional
+return res;
+} // block
+}
+
+void RV32IMACFD_raise(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers, etiss_int32 irq, etiss_uint32 mcause)
+{
+cpu->return_pending = 1;
+cpu->exception = 0;
+{ // block
+etiss_uint32 epc = cpu->instructionPointer;
+etiss_uint32 deleg = 0ULL;
+etiss_uint32 vector = 0ULL;
+etiss_uint32 bit = mcause;
+etiss_int32 irq2 = (mcause & 2147483648ULL) != 0ULL;
+if (irq2) { // conditional
+{ // block
+deleg = ((((RV32IMACFD*)cpu)->PRIV <= 1LL)) ? (*((RV32IMACFD*)cpu)->CSR[771LL]) : (0ULL);
+bit = bit & 2147483647ULL;
+} // block
+} // conditional
+else { // conditional
+{ // block
+deleg = ((((RV32IMACFD*)cpu)->PRIV <= 1LL)) ? (*((RV32IMACFD*)cpu)->CSR[770LL]) : (0ULL);
+} // block
+} // conditional
+if (((RV32IMACFD*)cpu)->PRIV <= 1LL && (deleg >> bit) & 1ULL) { // conditional
+{ // block
+vector = ((*((RV32IMACFD*)cpu)->CSR[261LL] & 1ULL) && irq2) ? (bit * 4ULL) : (0ULL);
+cpu->nextPc = (*((RV32IMACFD*)cpu)->CSR[261LL] & -2LL) + vector;
+*((RV32IMACFD*)cpu)->CSR[321LL] = epc;
+*((RV32IMACFD*)cpu)->CSR[322LL] = mcause;
+etiss_uint32 s = RV32IMACFD_csr_read(cpu, system, plugin_pointers, 256LL);
+s = RV32IMACFD_set_field(s, 32LL, RV32IMACFD_get_field(s, 2LL));
+s = RV32IMACFD_set_field(s, 256LL, ((RV32IMACFD*)cpu)->PRIV);
+s = RV32IMACFD_set_field(s, 2LL, 0ULL);
+RV32IMACFD_csr_write(cpu, system, plugin_pointers, 256LL, s);
+((RV32IMACFD*)cpu)->PRIV = (1LL) & 0x7;
+} // block
+} // conditional
+else { // conditional
+{ // block
+vector = ((*((RV32IMACFD*)cpu)->CSR[773LL] & 1ULL) && irq2) ? (bit * 4ULL) : (0ULL);
+cpu->nextPc = (*((RV32IMACFD*)cpu)->CSR[773LL] & -2LL) + vector;
+*((RV32IMACFD*)cpu)->CSR[833LL] = epc;
+*((RV32IMACFD*)cpu)->CSR[834LL] = mcause;
+etiss_uint32 s = RV32IMACFD_csr_read(cpu, system, plugin_pointers, 768LL);
+s = RV32IMACFD_set_field(s, 128LL, RV32IMACFD_get_field(s, 8LL));
+s = RV32IMACFD_set_field(s, 6144LL, ((RV32IMACFD*)cpu)->PRIV);
+s = RV32IMACFD_set_field(s, 8LL, 0ULL);
+RV32IMACFD_csr_write(cpu, system, plugin_pointers, 768LL, s);
+((RV32IMACFD*)cpu)->PRIV = (3LL) & 0x7;
+} // block
+} // conditional
+} // block
+}
+
+void RV32IMACFD_translate_exc_code(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers, etiss_int32 cause)
+{
+{ // block
+etiss_uint32 code = 0ULL;
+if (cause == -2147483648LL) { // conditional
+return;
+} // conditional
+ else if (cause == -5LL) { // conditional
+code = 5LL;
+} // conditional
+ else if (cause == -14LL) { // conditional
+code = 13LL;
+} // conditional
+ else if (cause == -6LL) { // conditional
+code = 7LL;
+} // conditional
+ else if (cause == -15LL) { // conditional
+code = 15LL;
+} // conditional
+ else if (cause == -7LL) { // conditional
+code = 1LL;
+} // conditional
+ else if (cause == -9LL) { // conditional
+{ // block
+code = RV32IMACFD_calc_irq_mcause(cpu, system, plugin_pointers);
+if (!(code)) { // conditional
+return;
+} // conditional
+} // block
+} // conditional
+else { // conditional
+code = 2LL;
+} // conditional
+RV32IMACFD_raise(cpu, system, plugin_pointers, 0ULL, code);
+} // block
+}
+
+etiss_uint32 RV32IMACFD_calc_irq_mcause(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers)
+{
+{ // block
+etiss_uint32 pending_interrupts = *((RV32IMACFD*)cpu)->CSR[772LL] & *((RV32IMACFD*)cpu)->CSR[836LL];
+if (!(pending_interrupts)) { // conditional
+return 0ULL;
+} // conditional
+etiss_uint32 mie = RV32IMACFD_get_field(*((RV32IMACFD*)cpu)->CSR[768LL], 8LL);
+etiss_uint32 m_enabled = ((RV32IMACFD*)cpu)->PRIV < 3LL || (((RV32IMACFD*)cpu)->PRIV == 3LL && mie);
+etiss_uint32 enabled_interrupts = pending_interrupts & ~(*((RV32IMACFD*)cpu)->CSR[771LL]) & -(m_enabled);
+if (enabled_interrupts == 0ULL) { // conditional
+{ // block
+etiss_uint32 deleg = *((RV32IMACFD*)cpu)->CSR[771LL];
+etiss_uint32 sie = RV32IMACFD_get_field(RV32IMACFD_csr_read(cpu, system, plugin_pointers, 256LL), 2LL);
+etiss_uint32 s_enabled = ((RV32IMACFD*)cpu)->PRIV < 1LL || (((RV32IMACFD*)cpu)->PRIV == 1LL && sie);
+enabled_interrupts = pending_interrupts & deleg & -(s_enabled);
+} // block
+} // conditional
+if (enabled_interrupts) { // conditional
+{ // block
+if (enabled_interrupts >> 12ULL) { // conditional
+enabled_interrupts = enabled_interrupts >> 12ULL << 12ULL;
+} // conditional
+ else if (enabled_interrupts & 2048LL) { // conditional
+enabled_interrupts = 2048LL;
+} // conditional
+ else if (enabled_interrupts & 8LL) { // conditional
+enabled_interrupts = 8LL;
+} // conditional
+ else if (enabled_interrupts & 128LL) { // conditional
+enabled_interrupts = 128LL;
+} // conditional
+ else if (enabled_interrupts & 512LL) { // conditional
+enabled_interrupts = 512LL;
+} // conditional
+ else if (enabled_interrupts & 2LL) { // conditional
+enabled_interrupts = 2LL;
+} // conditional
+ else if (enabled_interrupts & 32LL) { // conditional
+enabled_interrupts = 32LL;
+} // conditional
+ else if (enabled_interrupts & 8192LL) { // conditional
+enabled_interrupts = 8192LL;
+} // conditional
+ else if (enabled_interrupts & 1024LL) { // conditional
+enabled_interrupts = 1024LL;
+} // conditional
+ else if (enabled_interrupts & 4LL) { // conditional
+enabled_interrupts = 4LL;
+} // conditional
+ else if (enabled_interrupts & 64LL) { // conditional
+enabled_interrupts = 64LL;
+} // conditional
+else { // conditional
+return 0ULL;
+} // conditional
+return 2147483648ULL | RV32IMACFD_ctz(enabled_interrupts);
+} // block
+} // conditional
+return 0ULL;
+} // block
+}
+
+void RV32IMACFD_check_irq(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers)
+{
+{ // block
+etiss_uint32 irq_mcause = RV32IMACFD_calc_irq_mcause(cpu, system, plugin_pointers);
+if (irq_mcause) { // conditional
+RV32IMACFD_raise(cpu, system, plugin_pointers, 1ULL, irq_mcause);
+} // conditional
+} // block
+}
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFDFuncs.h b/ArchImpl/RV32IMACFD/RV32IMACFDFuncs.h
index db0f8900c5..f3384d6883 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFDFuncs.h
+++ b/ArchImpl/RV32IMACFD/RV32IMACFDFuncs.h
@@ -1,449 +1,118 @@
 /**
- * Generated on Mon, 02 Oct 2023 18:56:15 +0200.
+ * Generated on Fri, 03 Nov 2023 13:22:23 +0100.
  *
- * This file contains the function macros for the RV32IMACFD core architecture.
+ * This file contains the function prototypes for the RV32IMACFD core architecture.
  */
 
 #ifndef __RV32IMACFD_FUNCS_H
 #define __RV32IMACFD_FUNCS_H
 
-#ifndef ETISS_ARCH_STATIC_FN_ONLY
-#include "Arch/RV32IMACFD/RV32IMACFD.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "RV32IMACFD.h"
 #include "etiss/jit/CPU.h"
 #include "etiss/jit/System.h"
 #include "etiss/jit/ReturnCode.h"
-#endif
-
-
-
-extern void leave(etiss_int32 priv_lvl);
-
-extern void wait(etiss_int32 flag);
-
-static inline etiss_uint8 extension_enabled(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers, etiss_int8 extension);
-
-extern etiss_uint32 fadd_s(etiss_uint32, etiss_uint32, etiss_uint8);
-
-extern etiss_uint32 fsub_s(etiss_uint32, etiss_uint32, etiss_uint8);
-
-extern etiss_uint32 fmul_s(etiss_uint32, etiss_uint32, etiss_uint8);
-
-extern etiss_uint32 fdiv_s(etiss_uint32, etiss_uint32, etiss_uint8);
-
-extern etiss_uint32 fmadd_s(etiss_uint32, etiss_uint32, etiss_uint32, etiss_uint32, etiss_uint8);
-
-extern etiss_uint32 fsel_s(etiss_uint32, etiss_uint32, etiss_uint32);
 
-extern etiss_uint32 fsqrt_s(etiss_uint32, etiss_uint8);
 
-extern etiss_uint32 fcmp_s(etiss_uint32, etiss_uint32, etiss_uint32);
+void leave(etiss_int32 priv_lvl);
 
-extern etiss_uint32 fcvt_s(etiss_uint32, etiss_uint32, etiss_uint8);
+void wait(etiss_int32 flag);
 
-extern etiss_uint64 fcvt_32_64(etiss_uint32, etiss_uint32, etiss_uint8);
+etiss_uint8 RV32IMACFD_extension_enabled(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers, etiss_int8 extension);
 
-extern etiss_uint32 fcvt_64_32(etiss_uint64, etiss_uint32, etiss_uint8);
+etiss_uint32 fadd_s(etiss_uint32, etiss_uint32, etiss_uint8);
 
-extern etiss_uint32 unbox_s(etiss_uint64);
+etiss_uint32 fsub_s(etiss_uint32, etiss_uint32, etiss_uint8);
 
-extern etiss_uint32 fclass_s(etiss_uint32);
+etiss_uint32 fmul_s(etiss_uint32, etiss_uint32, etiss_uint8);
 
-extern etiss_uint32 fget_flags();
+etiss_uint32 fdiv_s(etiss_uint32, etiss_uint32, etiss_uint8);
 
-static inline etiss_uint8 get_rm(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers, etiss_uint8 rm);
+etiss_uint32 fmadd_s(etiss_uint32, etiss_uint32, etiss_uint32, etiss_uint32, etiss_uint8);
 
-extern etiss_uint64 fadd_d(etiss_uint64, etiss_uint64, etiss_uint8);
+etiss_uint32 fsel_s(etiss_uint32, etiss_uint32, etiss_uint32);
 
-extern etiss_uint64 fsub_d(etiss_uint64, etiss_uint64, etiss_uint8);
+etiss_uint32 fsqrt_s(etiss_uint32, etiss_uint8);
 
-extern etiss_uint64 fmul_d(etiss_uint64, etiss_uint64, etiss_uint8);
+etiss_uint32 fcmp_s(etiss_uint32, etiss_uint32, etiss_uint32);
 
-extern etiss_uint64 fdiv_d(etiss_uint64, etiss_uint64, etiss_uint8);
+etiss_uint32 fcvt_s(etiss_uint32, etiss_uint32, etiss_uint8);
 
-extern etiss_uint64 fmadd_d(etiss_uint64, etiss_uint64, etiss_uint64, etiss_uint32, etiss_uint8);
+etiss_uint64 fcvt_32_64(etiss_uint32, etiss_uint32, etiss_uint8);
 
-extern etiss_uint64 fsel_d(etiss_uint64, etiss_uint64, etiss_uint32);
+etiss_uint32 fcvt_64_32(etiss_uint64, etiss_uint32, etiss_uint8);
 
-extern etiss_uint64 fsqrt_d(etiss_uint64, etiss_uint8);
+etiss_uint32 unbox_s(etiss_uint64);
 
-extern etiss_uint64 fcmp_d(etiss_uint64, etiss_uint64, etiss_uint32);
+etiss_uint32 fclass_s(etiss_uint32);
 
-extern etiss_uint64 fcvt_d(etiss_uint64, etiss_uint32, etiss_uint8);
+etiss_uint32 fget_flags();
 
-extern etiss_uint32 fconv_d2f(etiss_uint64, etiss_uint8);
+etiss_uint8 RV32IMACFD_get_rm(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers, etiss_uint8 rm);
 
-extern etiss_uint64 fconv_f2d(etiss_uint32, etiss_uint8);
+etiss_uint64 fadd_d(etiss_uint64, etiss_uint64, etiss_uint8);
 
-extern etiss_uint64 unbox_d(etiss_uint64);
+etiss_uint64 fsub_d(etiss_uint64, etiss_uint64, etiss_uint8);
 
-extern etiss_uint64 fclass_d(etiss_uint64);
+etiss_uint64 fmul_d(etiss_uint64, etiss_uint64, etiss_uint8);
 
-extern etiss_uint64 etiss_get_cycles(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers);
+etiss_uint64 fdiv_d(etiss_uint64, etiss_uint64, etiss_uint8);
 
-extern etiss_uint64 etiss_get_time();
+etiss_uint64 fmadd_d(etiss_uint64, etiss_uint64, etiss_uint64, etiss_uint32, etiss_uint8);
 
-extern etiss_uint64 etiss_get_instret(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers);
+etiss_uint64 fsel_d(etiss_uint64, etiss_uint64, etiss_uint32);
 
-static inline etiss_uint32 sstatus_mask(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers);
+etiss_uint64 fsqrt_d(etiss_uint64, etiss_uint8);
 
-static inline etiss_uint32 mstatus_mask(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers);
+etiss_uint64 fcmp_d(etiss_uint64, etiss_uint64, etiss_uint32);
 
-static inline etiss_uint32 csr_read(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers, etiss_uint32 csr);
+etiss_uint64 fcvt_d(etiss_uint64, etiss_uint32, etiss_uint8);
 
-static inline void csr_write(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers, etiss_uint32 csr, etiss_uint32 val);
+etiss_uint32 fconv_d2f(etiss_uint64, etiss_uint8);
 
-static inline etiss_uint64 get_field(etiss_uint64 reg, etiss_uint64 mask);
+etiss_uint64 fconv_f2d(etiss_uint32, etiss_uint8);
 
-static inline etiss_uint64 set_field(etiss_uint64 reg, etiss_uint64 mask, etiss_uint64 val);
+etiss_uint64 unbox_d(etiss_uint64);
 
-static inline etiss_uint8 ctz(etiss_uint64 val);
+etiss_uint64 fclass_d(etiss_uint64);
 
-static inline void raise(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers, etiss_int32 irq, etiss_uint32 mcause);
+etiss_uint64 etiss_get_cycles(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers);
 
-static inline void translate_exc_code(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers, etiss_int32 cause);
+etiss_uint64 etiss_get_time();
 
-static inline etiss_uint32 calc_irq_mcause(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers);
+etiss_uint64 etiss_get_instret(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers);
 
-static inline void check_irq(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers);
+etiss_uint32 RV32IMACFD_sstatus_mask(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers);
 
-extern etiss_uint8 etiss_semihost_enabled();
+etiss_uint32 RV32IMACFD_mstatus_mask(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers);
 
-extern etiss_int64 etiss_semihost(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers, etiss_uint32 XLEN, etiss_uint64 operation, etiss_uint64 parameter);
+etiss_uint32 RV32IMACFD_csr_read(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers, etiss_uint32 csr);
 
-static inline etiss_uint8 extension_enabled(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers, etiss_int8 extension)
-{
-{ // block
-return (*((RV32IMACFD*)cpu)->CSR[769LL] >> (extension - 65ULL)) & 1ULL;
-} // block
-}
+void RV32IMACFD_csr_write(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers, etiss_uint32 csr, etiss_uint32 val);
 
-static inline etiss_uint8 get_rm(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers, etiss_uint8 rm)
-{
-{ // block
-if (rm == 7ULL) { // conditional
-rm = ((((((RV32IMACFD*)cpu)->FCSR) >> (5ULL)) & 7)) & 0x7;
-} // conditional
-if (rm > 4ULL) { // conditional
-raise(cpu, system, plugin_pointers, 0ULL, 2LL);
-} // conditional
-return rm;
-} // block
-}
+etiss_uint64 RV32IMACFD_get_field(etiss_uint64 reg, etiss_uint64 mask);
 
-static inline etiss_uint32 sstatus_mask(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers)
-{
-{ // block
-etiss_uint32 mask = 0ULL;
-if (extension_enabled(cpu, system, plugin_pointers, 83ULL)) { // conditional
-{ // block
-mask = mask | 5767458ULL;
-if (extension_enabled(cpu, system, plugin_pointers, 86ULL)) { // conditional
-mask = mask | 1536LL;
-} // conditional
-if (extension_enabled(cpu, system, plugin_pointers, 70ULL)) { // conditional
-mask = mask | 24576LL;
-} // conditional
-if (extension_enabled(cpu, system, plugin_pointers, 88ULL)) { // conditional
-mask = mask | 98304LL;
-} // conditional
-if ((get_field(*((RV32IMACFD*)cpu)->CSR[384LL], 2147483648ULL))) { // conditional
-mask = mask | 262144LL;
-} // conditional
-} // block
-} // conditional
-return mask;
-} // block
-}
+etiss_uint64 RV32IMACFD_set_field(etiss_uint64 reg, etiss_uint64 mask, etiss_uint64 val);
 
-static inline etiss_uint32 mstatus_mask(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers)
-{
-{ // block
-etiss_uint32 mask = 6280ULL;
-return mask | sstatus_mask(cpu, system, plugin_pointers);
-} // block
-}
+etiss_uint8 RV32IMACFD_ctz(etiss_uint64 val);
 
-static inline etiss_uint32 csr_read(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers, etiss_uint32 csr)
-{
-{ // block
-if (csr == 1LL) { // conditional
-return *((RV32IMACFD*)cpu)->CSR[3LL] & 31ULL;
-} // conditional
-if (csr == 2LL) { // conditional
-return (*((RV32IMACFD*)cpu)->CSR[3LL] >> 5ULL) & 7ULL;
-} // conditional
-if (csr == 3072LL) { // conditional
-return etiss_get_cycles(cpu, system, plugin_pointers);
-} // conditional
-if (csr == 3200LL) { // conditional
-return etiss_get_cycles(cpu, system, plugin_pointers) >> 32ULL;
-} // conditional
-if (csr == 3073LL) { // conditional
-return etiss_get_time();
-} // conditional
-if (csr == 3201LL) { // conditional
-return etiss_get_time() >> 32ULL;
-} // conditional
-if (csr == 3074LL) { // conditional
-return etiss_get_instret(cpu, system, plugin_pointers);
-} // conditional
-if (csr == 3202LL) { // conditional
-return etiss_get_instret(cpu, system, plugin_pointers) >> 32ULL;
-} // conditional
-if (csr == 768LL || csr == 256LL) { // conditional
-return *((RV32IMACFD*)cpu)->CSR[768LL] | 8589934592ULL | 34359738368ULL;
-} // conditional
-if (csr == 769LL) { // conditional
-return (((1ULL) << 30) | ((((*((RV32IMACFD*)cpu)->CSR[769LL]) >> (0ULL)) & 1073741823)));
-} // conditional
-return *((RV32IMACFD*)cpu)->CSR[csr];
-} // block
-}
-
-static inline void csr_write(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers, etiss_uint32 csr, etiss_uint32 val)
-{
-{ // block
-if (csr == 1LL) { // conditional
-*((RV32IMACFD*)cpu)->CSR[3LL] = (*((RV32IMACFD*)cpu)->CSR[3LL] & 224ULL) | (val & 31ULL);
-} // conditional
- else if (csr == 2LL) { // conditional
-*((RV32IMACFD*)cpu)->CSR[3LL] = ((val & 7ULL) << 5ULL) | (*((RV32IMACFD*)cpu)->CSR[3LL] & 31ULL);
-} // conditional
- else if (csr == 3LL) { // conditional
-*((RV32IMACFD*)cpu)->CSR[3LL] = val & 255ULL;
-} // conditional
- else if (csr == 768LL) { // conditional
-*((RV32IMACFD*)cpu)->CSR[768LL] = val & mstatus_mask(cpu, system, plugin_pointers);
-} // conditional
- else if (csr == 256LL) { // conditional
-*((RV32IMACFD*)cpu)->CSR[768LL] = val & sstatus_mask(cpu, system, plugin_pointers);
-} // conditional
- else if (csr != 769LL) { // conditional
-*((RV32IMACFD*)cpu)->CSR[csr] = val;
-} // conditional
-} // block
-}
+void RV32IMACFD_raise(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers, etiss_int32 irq, etiss_uint32 mcause);
 
-static inline etiss_uint64 get_field(etiss_uint64 reg, etiss_uint64 mask)
-{
-{ // block
-return (reg & mask) / (mask & ~((mask << 1ULL)));
-} // block
-}
+void RV32IMACFD_translate_exc_code(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers, etiss_int32 cause);
 
-static inline etiss_uint64 set_field(etiss_uint64 reg, etiss_uint64 mask, etiss_uint64 val)
-{
-{ // block
-return ((reg & ~(mask)) | ((val * (mask & ~((mask << 1ULL)))) & mask));
-} // block
-}
+etiss_uint32 RV32IMACFD_calc_irq_mcause(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers);
 
-static inline etiss_uint8 ctz(etiss_uint64 val)
-{
-{ // block
-if (!(val)) { // conditional
-return 0ULL;
-} // conditional
-etiss_uint8 res = 0ULL;
-if ((val << 32ULL) == 0ULL) { // conditional
-{ // block
-res = res + 32ULL;
-val = val >> 32ULL;
-} // block
-} // conditional
-if ((val << 48ULL) == 0ULL) { // conditional
-{ // block
-res = res + 16ULL;
-val = val >> 16ULL;
-} // block
-} // conditional
-if ((val << 56ULL) == 0ULL) { // conditional
-{ // block
-res = res + 8ULL;
-val = val >> 8ULL;
-} // block
-} // conditional
-if ((val << 60ULL) == 0ULL) { // conditional
-{ // block
-res = res + 4ULL;
-val = val >> 4ULL;
-} // block
-} // conditional
-if ((val << 62ULL) == 0ULL) { // conditional
-{ // block
-res = res + 2ULL;
-val = val >> 2ULL;
-} // block
-} // conditional
-if ((val << 63ULL) == 0ULL) { // conditional
-{ // block
-res = res + 1ULL;
-val = val >> 1ULL;
-} // block
-} // conditional
-return res;
-} // block
-}
+void RV32IMACFD_check_irq(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers);
 
-static inline void raise(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers, etiss_int32 irq, etiss_uint32 mcause)
-{
-cpu->return_pending = 1;
-cpu->exception = 0;
-{ // block
-etiss_uint32 epc = cpu->instructionPointer;
-etiss_uint32 deleg = 0ULL;
-etiss_uint32 vector = 0ULL;
-etiss_uint32 bit = mcause;
-etiss_int32 irq2 = (mcause & 2147483648ULL) != 0ULL;
-if (irq2) { // conditional
-{ // block
-deleg = ((((RV32IMACFD*)cpu)->PRIV <= 1LL)) ? (*((RV32IMACFD*)cpu)->CSR[771LL]) : (0ULL);
-bit = bit & 2147483647ULL;
-} // block
-} // conditional
-else { // conditional
-{ // block
-deleg = ((((RV32IMACFD*)cpu)->PRIV <= 1LL)) ? (*((RV32IMACFD*)cpu)->CSR[770LL]) : (0ULL);
-} // block
-} // conditional
-if (((RV32IMACFD*)cpu)->PRIV <= 1LL && (deleg >> bit) & 1ULL) { // conditional
-{ // block
-vector = ((*((RV32IMACFD*)cpu)->CSR[261LL] & 1ULL) && irq2) ? (bit * 4ULL) : (0ULL);
-cpu->nextPc = (*((RV32IMACFD*)cpu)->CSR[261LL] & -2LL) + vector;
-*((RV32IMACFD*)cpu)->CSR[321LL] = epc;
-*((RV32IMACFD*)cpu)->CSR[322LL] = mcause;
-etiss_uint32 s = csr_read(cpu, system, plugin_pointers, 256LL);
-s = set_field(s, 32LL, get_field(s, 2LL));
-s = set_field(s, 256LL, ((RV32IMACFD*)cpu)->PRIV);
-s = set_field(s, 2LL, 0ULL);
-csr_write(cpu, system, plugin_pointers, 256LL, s);
-((RV32IMACFD*)cpu)->PRIV = (1LL) & 0x7;
-} // block
-} // conditional
-else { // conditional
-{ // block
-vector = ((*((RV32IMACFD*)cpu)->CSR[773LL] & 1ULL) && irq2) ? (bit * 4ULL) : (0ULL);
-cpu->nextPc = (*((RV32IMACFD*)cpu)->CSR[773LL] & -2LL) + vector;
-*((RV32IMACFD*)cpu)->CSR[833LL] = epc;
-*((RV32IMACFD*)cpu)->CSR[834LL] = mcause;
-etiss_uint32 s = csr_read(cpu, system, plugin_pointers, 768LL);
-s = set_field(s, 128LL, get_field(s, 8LL));
-s = set_field(s, 6144LL, ((RV32IMACFD*)cpu)->PRIV);
-s = set_field(s, 8LL, 0ULL);
-csr_write(cpu, system, plugin_pointers, 768LL, s);
-((RV32IMACFD*)cpu)->PRIV = (3LL) & 0x7;
-} // block
-} // conditional
-} // block
-}
+etiss_uint8 etiss_semihost_enabled();
 
-static inline void translate_exc_code(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers, etiss_int32 cause)
-{
-{ // block
-etiss_uint32 code = 0ULL;
-if (cause == -2147483648LL) { // conditional
-return;
-} // conditional
- else if (cause == -5LL) { // conditional
-code = 5LL;
-} // conditional
- else if (cause == -14LL) { // conditional
-code = 13LL;
-} // conditional
- else if (cause == -6LL) { // conditional
-code = 7LL;
-} // conditional
- else if (cause == -15LL) { // conditional
-code = 15LL;
-} // conditional
- else if (cause == -7LL) { // conditional
-code = 1LL;
-} // conditional
- else if (cause == -9LL) { // conditional
-{ // block
-code = calc_irq_mcause(cpu, system, plugin_pointers);
-if (!(code)) { // conditional
-return;
-} // conditional
-} // block
-} // conditional
-else { // conditional
-code = 2LL;
-} // conditional
-raise(cpu, system, plugin_pointers, 0ULL, code);
-} // block
-}
+etiss_int64 etiss_semihost(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers, etiss_uint32 XLEN, etiss_uint64 operation, etiss_uint64 parameter);
 
-static inline etiss_uint32 calc_irq_mcause(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers)
-{
-{ // block
-etiss_uint32 pending_interrupts = *((RV32IMACFD*)cpu)->CSR[772LL] & *((RV32IMACFD*)cpu)->CSR[836LL];
-if (!(pending_interrupts)) { // conditional
-return 0ULL;
-} // conditional
-etiss_uint32 mie = get_field(*((RV32IMACFD*)cpu)->CSR[768LL], 8LL);
-etiss_uint32 m_enabled = ((RV32IMACFD*)cpu)->PRIV < 3LL || (((RV32IMACFD*)cpu)->PRIV == 3LL && mie);
-etiss_uint32 enabled_interrupts = pending_interrupts & ~(*((RV32IMACFD*)cpu)->CSR[771LL]) & -(m_enabled);
-if (enabled_interrupts == 0ULL) { // conditional
-{ // block
-etiss_uint32 deleg = *((RV32IMACFD*)cpu)->CSR[771LL];
-etiss_uint32 sie = get_field(csr_read(cpu, system, plugin_pointers, 256LL), 2LL);
-etiss_uint32 s_enabled = ((RV32IMACFD*)cpu)->PRIV < 1LL || (((RV32IMACFD*)cpu)->PRIV == 1LL && sie);
-enabled_interrupts = pending_interrupts & deleg & -(s_enabled);
-} // block
-} // conditional
-if (enabled_interrupts) { // conditional
-{ // block
-if (enabled_interrupts >> 12ULL) { // conditional
-enabled_interrupts = enabled_interrupts >> 12ULL << 12ULL;
-} // conditional
- else if (enabled_interrupts & 2048LL) { // conditional
-enabled_interrupts = 2048LL;
-} // conditional
- else if (enabled_interrupts & 8LL) { // conditional
-enabled_interrupts = 8LL;
-} // conditional
- else if (enabled_interrupts & 128LL) { // conditional
-enabled_interrupts = 128LL;
-} // conditional
- else if (enabled_interrupts & 512LL) { // conditional
-enabled_interrupts = 512LL;
-} // conditional
- else if (enabled_interrupts & 2LL) { // conditional
-enabled_interrupts = 2LL;
-} // conditional
- else if (enabled_interrupts & 32LL) { // conditional
-enabled_interrupts = 32LL;
-} // conditional
- else if (enabled_interrupts & 8192LL) { // conditional
-enabled_interrupts = 8192LL;
-} // conditional
- else if (enabled_interrupts & 1024LL) { // conditional
-enabled_interrupts = 1024LL;
-} // conditional
- else if (enabled_interrupts & 4LL) { // conditional
-enabled_interrupts = 4LL;
-} // conditional
- else if (enabled_interrupts & 64LL) { // conditional
-enabled_interrupts = 64LL;
-} // conditional
-else { // conditional
-return 0ULL;
-} // conditional
-return 2147483648ULL | ctz(enabled_interrupts);
-} // block
-} // conditional
-return 0ULL;
-} // block
+#ifdef __cplusplus
 }
+#endif
 
-static inline void check_irq(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers)
-{
-{ // block
-etiss_uint32 irq_mcause = calc_irq_mcause(cpu, system, plugin_pointers);
-if (irq_mcause) { // conditional
-raise(cpu, system, plugin_pointers, 1ULL, irq_mcause);
-} // conditional
-} // block
-}
 #endif
\ No newline at end of file
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFDGDBCore.h b/ArchImpl/RV32IMACFD/RV32IMACFDGDBCore.h
index bb5746e691..1e42f39f63 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFDGDBCore.h
+++ b/ArchImpl/RV32IMACFD/RV32IMACFDGDBCore.h
@@ -1,5 +1,5 @@
 /**
- * Generated on Mon, 02 Oct 2023 18:56:15 +0200.
+ * Generated on Fri, 03 Nov 2023 13:22:23 +0100.
  *
  * This file contains the GDBCore adapter for the RV32IMACFD core architecture.
  *
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFDInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFDInstr.cpp
index 95800ae5b6..60576e12cf 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFDInstr.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFDInstr.cpp
@@ -1,13 +1,11 @@
 /**
- * Generated on Mon, 02 Oct 2023 18:56:15 +0200.
+ * Generated on Fri, 03 Nov 2023 13:22:23 +0100.
  *
  * This file contains the instruction behavior models of the default
  * instruction set for the RV32IMACFD core architecture.
  */
 
 #include "RV32IMACFDArch.h"
-
-#define ETISS_ARCH_STATIC_FN_ONLY
 #include "RV32IMACFDFuncs.h"
 
 using namespace etiss;
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32AInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32AInstr.cpp
index 20c7af819a..d8a50954a9 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32AInstr.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32AInstr.cpp
@@ -1,13 +1,11 @@
 /**
- * Generated on Wed, 04 Oct 2023 17:01:33 +0200.
+ * Generated on Fri, 03 Nov 2023 13:22:23 +0100.
  *
  * This file contains the instruction behavior models of the RV32A
  * instruction set for the RV32IMACFD core architecture.
  */
 
 #include "RV32IMACFDArch.h"
-
-#define ETISS_ARCH_STATIC_FN_ONLY
 #include "RV32IMACFDFuncs.h"
 
 using namespace etiss;
@@ -66,7 +64,7 @@ cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (e
 cp.code() += "if (cpu->exception) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "RV32IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -79,7 +77,7 @@ cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (
 cp.code() += "if (cpu->exception) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "RV32IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -184,7 +182,7 @@ cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (e
 cp.code() += "if (cpu->exception) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "RV32IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -200,7 +198,7 @@ cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (
 cp.code() += "if (cpu->exception) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "RV32IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -305,7 +303,7 @@ cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (e
 cp.code() += "if (cpu->exception) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "RV32IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -321,7 +319,7 @@ cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (
 cp.code() += "if (cpu->exception) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "RV32IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -426,7 +424,7 @@ cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (e
 cp.code() += "if (cpu->exception) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "RV32IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -442,7 +440,7 @@ cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (
 cp.code() += "if (cpu->exception) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "RV32IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -547,7 +545,7 @@ cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (e
 cp.code() += "if (cpu->exception) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "RV32IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -563,7 +561,7 @@ cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (
 cp.code() += "if (cpu->exception) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "RV32IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -668,7 +666,7 @@ cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (e
 cp.code() += "if (cpu->exception) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "RV32IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -684,7 +682,7 @@ cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (
 cp.code() += "if (cpu->exception) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "RV32IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -789,7 +787,7 @@ cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (e
 cp.code() += "if (cpu->exception) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "RV32IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -805,7 +803,7 @@ cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (
 cp.code() += "if (cpu->exception) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "RV32IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -910,7 +908,7 @@ cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (e
 cp.code() += "if (cpu->exception) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "RV32IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -926,7 +924,7 @@ cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (
 cp.code() += "if (cpu->exception) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "RV32IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -1031,7 +1029,7 @@ cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (e
 cp.code() += "if (cpu->exception) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "RV32IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -1047,7 +1045,7 @@ cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (
 cp.code() += "if (cpu->exception) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "RV32IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32DCInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32DCInstr.cpp
index c7ddf3544f..a1acf2aa56 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32DCInstr.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32DCInstr.cpp
@@ -1,13 +1,11 @@
 /**
- * Generated on Wed, 04 Oct 2023 17:01:33 +0200.
+ * Generated on Fri, 03 Nov 2023 13:22:23 +0100.
  *
  * This file contains the instruction behavior models of the RV32DC
  * instruction set for the RV32IMACFD core architecture.
  */
 
 #include "RV32IMACFDArch.h"
-
-#define ETISS_ARCH_STATIC_FN_ONLY
 #include "RV32IMACFDFuncs.h"
 
 using namespace etiss;
@@ -61,7 +59,7 @@ cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (e
 cp.code() += "if (cpu->exception) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "RV32IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -161,7 +159,7 @@ cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (
 cp.code() += "if (cpu->exception) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "RV32IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -257,7 +255,7 @@ cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (e
 cp.code() += "if (cpu->exception) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "RV32IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -353,7 +351,7 @@ cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (
 cp.code() += "if (cpu->exception) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "RV32IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32DInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32DInstr.cpp
index cff92b29bc..8434b8ecec 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32DInstr.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32DInstr.cpp
@@ -1,13 +1,11 @@
 /**
- * Generated on Wed, 04 Oct 2023 17:01:33 +0200.
+ * Generated on Fri, 03 Nov 2023 13:22:23 +0100.
  *
  * This file contains the instruction behavior models of the RV32D
  * instruction set for the RV32IMACFD core architecture.
  */
 
 #include "RV32IMACFDArch.h"
-
-#define ETISS_ARCH_STATIC_FN_ONLY
 #include "RV32IMACFDFuncs.h"
 
 using namespace etiss;
@@ -59,7 +57,7 @@ cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (e
 cp.code() += "if (cpu->exception) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "RV32IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -157,7 +155,7 @@ cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (
 cp.code() += "if (cpu->exception) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "RV32IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -252,7 +250,7 @@ cp.code() += "} // block\n";
 } // block
 { // block
 cp.code() += "{ // block\n";
-cp.code() += "etiss_uint64 res = fmadd_d((etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs3) + "ULL]), 0ULL, get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
+cp.code() += "etiss_uint64 res = fmadd_d((etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs3) + "ULL]), 0ULL, RV32IMACFD_get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
 cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = res;\n";
 cp.code() += "etiss_uint32 flags = fget_flags();\n";
 cp.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";
@@ -341,7 +339,7 @@ cp.code() += "} // block\n";
 } // block
 { // block
 cp.code() += "{ // block\n";
-cp.code() += "etiss_uint64 res = fmadd_d((etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs3) + "ULL]), 1ULL, get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
+cp.code() += "etiss_uint64 res = fmadd_d((etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs3) + "ULL]), 1ULL, RV32IMACFD_get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
 cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = res;\n";
 cp.code() += "etiss_uint32 flags = fget_flags();\n";
 cp.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";
@@ -430,7 +428,7 @@ cp.code() += "} // block\n";
 } // block
 { // block
 cp.code() += "{ // block\n";
-cp.code() += "etiss_uint64 res = fmadd_d((etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs3) + "ULL]), 2ULL, get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
+cp.code() += "etiss_uint64 res = fmadd_d((etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs3) + "ULL]), 2ULL, RV32IMACFD_get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
 cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = res;\n";
 cp.code() += "etiss_uint32 flags = fget_flags();\n";
 cp.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";
@@ -519,7 +517,7 @@ cp.code() += "} // block\n";
 } // block
 { // block
 cp.code() += "{ // block\n";
-cp.code() += "etiss_uint64 res = fmadd_d((etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs3) + "ULL]), 3ULL, get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
+cp.code() += "etiss_uint64 res = fmadd_d((etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs3) + "ULL]), 3ULL, RV32IMACFD_get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
 cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = res;\n";
 cp.code() += "etiss_uint32 flags = fget_flags();\n";
 cp.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";
@@ -605,7 +603,7 @@ cp.code() += "} // block\n";
 } // block
 { // block
 cp.code() += "{ // block\n";
-cp.code() += "etiss_uint64 res = fadd_d((etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]), get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
+cp.code() += "etiss_uint64 res = fadd_d((etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]), RV32IMACFD_get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
 cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = res;\n";
 cp.code() += "etiss_uint32 flags = fget_flags();\n";
 cp.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";
@@ -688,7 +686,7 @@ cp.code() += "} // block\n";
 } // block
 { // block
 cp.code() += "{ // block\n";
-cp.code() += "etiss_uint64 res = fsub_d((etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]), get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
+cp.code() += "etiss_uint64 res = fsub_d((etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]), RV32IMACFD_get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
 cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = res;\n";
 cp.code() += "etiss_uint32 flags = fget_flags();\n";
 cp.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";
@@ -771,7 +769,7 @@ cp.code() += "} // block\n";
 } // block
 { // block
 cp.code() += "{ // block\n";
-cp.code() += "etiss_uint64 res = fmul_d((etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]), get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
+cp.code() += "etiss_uint64 res = fmul_d((etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]), RV32IMACFD_get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
 cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = res;\n";
 cp.code() += "etiss_uint32 flags = fget_flags();\n";
 cp.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";
@@ -854,7 +852,7 @@ cp.code() += "} // block\n";
 } // block
 { // block
 cp.code() += "{ // block\n";
-cp.code() += "etiss_uint64 res = fdiv_d((etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]), get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
+cp.code() += "etiss_uint64 res = fdiv_d((etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]), RV32IMACFD_get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
 cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = res;\n";
 cp.code() += "etiss_uint32 flags = fget_flags();\n";
 cp.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";
@@ -934,7 +932,7 @@ cp.code() += "} // block\n";
 } // block
 { // block
 cp.code() += "{ // block\n";
-cp.code() += "etiss_uint64 res = fsqrt_d((etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
+cp.code() += "etiss_uint64 res = fsqrt_d((etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), RV32IMACFD_get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
 cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = res;\n";
 cp.code() += "etiss_uint32 flags = fget_flags();\n";
 cp.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32FCInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32FCInstr.cpp
index 66e2f948c1..863c4896c6 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32FCInstr.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32FCInstr.cpp
@@ -1,13 +1,11 @@
 /**
- * Generated on Wed, 04 Oct 2023 17:01:33 +0200.
+ * Generated on Fri, 03 Nov 2023 13:22:23 +0100.
  *
  * This file contains the instruction behavior models of the RV32FC
  * instruction set for the RV32IMACFD core architecture.
  */
 
 #include "RV32IMACFDArch.h"
-
-#define ETISS_ARCH_STATIC_FN_ONLY
 #include "RV32IMACFDFuncs.h"
 
 using namespace etiss;
@@ -63,7 +61,7 @@ cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (e
 cp.code() += "if (cpu->exception) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "RV32IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -171,7 +169,7 @@ cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (
 cp.code() += "if (cpu->exception) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "RV32IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -269,7 +267,7 @@ cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (e
 cp.code() += "if (cpu->exception) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "RV32IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -369,7 +367,7 @@ cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (
 cp.code() += "if (cpu->exception) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "RV32IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32FInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32FInstr.cpp
index 46c8d33eaa..b6b3fd8fb2 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32FInstr.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32FInstr.cpp
@@ -1,13 +1,11 @@
 /**
- * Generated on Wed, 04 Oct 2023 17:01:33 +0200.
+ * Generated on Fri, 03 Nov 2023 13:22:23 +0100.
  *
  * This file contains the instruction behavior models of the RV32F
  * instruction set for the RV32IMACFD core architecture.
  */
 
 #include "RV32IMACFDArch.h"
-
-#define ETISS_ARCH_STATIC_FN_ONLY
 #include "RV32IMACFDFuncs.h"
 
 using namespace etiss;
@@ -59,7 +57,7 @@ cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (e
 cp.code() += "if (cpu->exception) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "RV32IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -161,7 +159,7 @@ cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (
 cp.code() += "if (cpu->exception) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "RV32IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -258,7 +256,7 @@ cp.code() += "} // block\n";
 cp.code() += "{ // block\n";
 { // block
 cp.code() += "{ // block\n";
-cp.code() += "etiss_uint32 res = fmadd_s(unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]), unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs3) + "ULL]), 0ULL, get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
+cp.code() += "etiss_uint32 res = fmadd_s(unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]), unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs3) + "ULL]), 0ULL, RV32IMACFD_get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
 cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = -4294967296LL | (etiss_uint64)(res);\n";
 cp.code() += "} // block\n";
 } // block
@@ -351,7 +349,7 @@ cp.code() += "} // block\n";
 cp.code() += "{ // block\n";
 { // block
 cp.code() += "{ // block\n";
-cp.code() += "etiss_uint32 res = fmadd_s(unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]), unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs3) + "ULL]), 1ULL, get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
+cp.code() += "etiss_uint32 res = fmadd_s(unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]), unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs3) + "ULL]), 1ULL, RV32IMACFD_get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
 cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = -4294967296LL | (etiss_uint64)(res);\n";
 cp.code() += "} // block\n";
 } // block
@@ -447,7 +445,7 @@ cp.code() += "{ // block\n";
 cp.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]);\n";
 cp.code() += "etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]);\n";
 cp.code() += "etiss_uint32 frs3 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs3) + "ULL]);\n";
-cp.code() += "etiss_uint32 res = fmadd_s(frs1, frs2, frs3, 2ULL, get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
+cp.code() += "etiss_uint32 res = fmadd_s(frs1, frs2, frs3, 2ULL, RV32IMACFD_get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
 cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = -4294967296LL | (etiss_uint64)(res);\n";
 cp.code() += "} // block\n";
 } // block
@@ -543,7 +541,7 @@ cp.code() += "{ // block\n";
 cp.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]);\n";
 cp.code() += "etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]);\n";
 cp.code() += "etiss_uint32 frs3 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs3) + "ULL]);\n";
-cp.code() += "etiss_uint32 res = fmadd_s(frs1, frs2, frs3, 3ULL, get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
+cp.code() += "etiss_uint32 res = fmadd_s(frs1, frs2, frs3, 3ULL, RV32IMACFD_get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
 cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = -4294967296LL | (etiss_uint64)(res);\n";
 cp.code() += "} // block\n";
 } // block
@@ -635,7 +633,7 @@ cp.code() += "{ // block\n";
 cp.code() += "{ // block\n";
 cp.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]);\n";
 cp.code() += "etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]);\n";
-cp.code() += "etiss_uint32 res = fadd_s(frs1, frs2, get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
+cp.code() += "etiss_uint32 res = fadd_s(frs1, frs2, RV32IMACFD_get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
 cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = -4294967296LL | (etiss_uint64)(res);\n";
 cp.code() += "} // block\n";
 } // block
@@ -724,7 +722,7 @@ cp.code() += "{ // block\n";
 cp.code() += "{ // block\n";
 cp.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]);\n";
 cp.code() += "etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]);\n";
-cp.code() += "etiss_uint32 res = fsub_s(frs1, frs2, get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
+cp.code() += "etiss_uint32 res = fsub_s(frs1, frs2, RV32IMACFD_get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
 cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = -4294967296LL | (etiss_uint64)(res);\n";
 cp.code() += "} // block\n";
 } // block
@@ -813,7 +811,7 @@ cp.code() += "{ // block\n";
 cp.code() += "{ // block\n";
 cp.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]);\n";
 cp.code() += "etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]);\n";
-cp.code() += "etiss_uint32 res = fmul_s(frs1, frs2, get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
+cp.code() += "etiss_uint32 res = fmul_s(frs1, frs2, RV32IMACFD_get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
 cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = -4294967296LL | (etiss_uint64)(res);\n";
 cp.code() += "} // block\n";
 } // block
@@ -902,7 +900,7 @@ cp.code() += "{ // block\n";
 cp.code() += "{ // block\n";
 cp.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]);\n";
 cp.code() += "etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]);\n";
-cp.code() += "etiss_uint32 res = fdiv_s(frs1, frs2, get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
+cp.code() += "etiss_uint32 res = fdiv_s(frs1, frs2, RV32IMACFD_get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
 cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = -4294967296LL | (etiss_uint64)(res);\n";
 cp.code() += "} // block\n";
 } // block
@@ -987,7 +985,7 @@ cp.code() += "{ // block\n";
 { // block
 cp.code() += "{ // block\n";
 cp.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]);\n";
-cp.code() += "etiss_uint32 res = fsqrt_s(frs1, get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
+cp.code() += "etiss_uint32 res = fsqrt_s(frs1, RV32IMACFD_get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
 cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = -4294967296LL | (etiss_uint64)(res);\n";
 cp.code() += "} // block\n";
 } // block
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32ICInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32ICInstr.cpp
index c5a9542d72..4dd344a5a1 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32ICInstr.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32ICInstr.cpp
@@ -1,13 +1,11 @@
 /**
- * Generated on Wed, 04 Oct 2023 17:01:33 +0200.
+ * Generated on Fri, 03 Nov 2023 13:22:23 +0100.
  *
  * This file contains the instruction behavior models of the RV32IC
  * instruction set for the RV32IMACFD core architecture.
  */
 
 #include "RV32IMACFDArch.h"
-
-#define ETISS_ARCH_STATIC_FN_ONLY
 #include "RV32IMACFDFuncs.h"
 
 using namespace etiss;
@@ -60,7 +58,7 @@ cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd + 8ULL) + "ULL] = *((
 else { // conditional
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "raise(cpu, system, plugin_pointers, 0ULL, 2ULL);\n";
+cp.code() += "RV32IMACFD_raise(cpu, system, plugin_pointers, 0ULL, 2ULL);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -158,7 +156,7 @@ cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, load_add
 cp.code() += "if (cpu->exception) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "RV32IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -261,7 +259,7 @@ cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, load_ad
 cp.code() += "if (cpu->exception) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "RV32IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -663,7 +661,7 @@ cp.code() += "{ // block\n";
 if (imm == 0ULL) { // conditional
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "raise(cpu, system, plugin_pointers, 0ULL, 2ULL);\n";
+cp.code() += "RV32IMACFD_raise(cpu, system, plugin_pointers, 0ULL, 2ULL);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -758,7 +756,7 @@ cp.code() += "*((RV32IMACFD*)cpu)->X[2ULL] = *((RV32IMACFD*)cpu)->X[2ULL] + " +
 else { // conditional
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "raise(cpu, system, plugin_pointers, 0ULL, 2ULL);\n";
+cp.code() += "RV32IMACFD_raise(cpu, system, plugin_pointers, 0ULL, 2ULL);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -839,7 +837,7 @@ cp.code() += "} // block\n";
 } // block
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "raise(cpu, system, plugin_pointers, 0ULL, 2ULL);\n";
+cp.code() += "RV32IMACFD_raise(cpu, system, plugin_pointers, 0ULL, 2ULL);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -1755,7 +1753,7 @@ cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, *((RV32I
 cp.code() += "if (cpu->exception) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "RV32IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -1768,7 +1766,7 @@ cp.code() += "} // block\n";
 else { // conditional
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "raise(cpu, system, plugin_pointers, 0ULL, 2ULL);\n";
+cp.code() += "RV32IMACFD_raise(cpu, system, plugin_pointers, 0ULL, 2ULL);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -1920,7 +1918,7 @@ cp.code() += "cpu->nextPc = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32UL
 else { // conditional
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "raise(cpu, system, plugin_pointers, 0ULL, 2ULL);\n";
+cp.code() += "RV32IMACFD_raise(cpu, system, plugin_pointers, 0ULL, 2ULL);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -1990,7 +1988,7 @@ cp.code() += "} // block\n";
 } // block
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "raise(cpu, system, plugin_pointers, 0ULL, 2ULL);\n";
+cp.code() += "RV32IMACFD_raise(cpu, system, plugin_pointers, 0ULL, 2ULL);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -2195,7 +2193,7 @@ cp.code() += "} // block\n";
 } // block
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "raise(cpu, system, plugin_pointers, 0ULL, 3ULL);\n";
+cp.code() += "RV32IMACFD_raise(cpu, system, plugin_pointers, 0ULL, 3ULL);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -2276,7 +2274,7 @@ cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (
 cp.code() += "if (cpu->exception) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "RV32IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -2353,7 +2351,7 @@ cp.code() += "} // block\n";
 } // block
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "raise(cpu, system, plugin_pointers, 0ULL, 2ULL);\n";
+cp.code() += "RV32IMACFD_raise(cpu, system, plugin_pointers, 0ULL, 2ULL);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32IInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32IInstr.cpp
index 5e286283c2..a99c4d2e67 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32IInstr.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32IInstr.cpp
@@ -1,13 +1,11 @@
 /**
- * Generated on Wed, 04 Oct 2023 17:01:33 +0200.
+ * Generated on Fri, 03 Nov 2023 13:22:23 +0100.
  *
  * This file contains the instruction behavior models of the RV32I
  * instruction set for the RV32IMACFD core architecture.
  */
 
 #include "RV32IMACFDArch.h"
-
-#define ETISS_ARCH_STATIC_FN_ONLY
 #include "RV32IMACFDFuncs.h"
 
 using namespace etiss;
@@ -193,7 +191,7 @@ if (imm % 2ULL) { // conditional
 cp.code() += "{ // block\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "raise(cpu, system, plugin_pointers, 0ULL, 0ULL);\n";
+cp.code() += "RV32IMACFD_raise(cpu, system, plugin_pointers, 0ULL, 0ULL);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -301,7 +299,7 @@ cp.code() += "if (new_pc % 2ULL) { // conditional\n";
 cp.code() += "{ // block\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "raise(cpu, system, plugin_pointers, 0ULL, 0ULL);\n";
+cp.code() += "RV32IMACFD_raise(cpu, system, plugin_pointers, 0ULL, 0ULL);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -414,7 +412,7 @@ if (imm % 2ULL) { // conditional
 cp.code() += "{ // block\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "raise(cpu, system, plugin_pointers, 0ULL, 0ULL);\n";
+cp.code() += "RV32IMACFD_raise(cpu, system, plugin_pointers, 0ULL, 0ULL);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -533,7 +531,7 @@ if (imm % 2ULL) { // conditional
 cp.code() += "{ // block\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "raise(cpu, system, plugin_pointers, 0ULL, 0ULL);\n";
+cp.code() += "RV32IMACFD_raise(cpu, system, plugin_pointers, 0ULL, 0ULL);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -652,7 +650,7 @@ if (imm % 2ULL) { // conditional
 cp.code() += "{ // block\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "raise(cpu, system, plugin_pointers, 0ULL, 0ULL);\n";
+cp.code() += "RV32IMACFD_raise(cpu, system, plugin_pointers, 0ULL, 0ULL);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -771,7 +769,7 @@ if (imm % 2ULL) { // conditional
 cp.code() += "{ // block\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "raise(cpu, system, plugin_pointers, 0ULL, 0ULL);\n";
+cp.code() += "RV32IMACFD_raise(cpu, system, plugin_pointers, 0ULL, 0ULL);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -890,7 +888,7 @@ if (imm % 2ULL) { // conditional
 cp.code() += "{ // block\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "raise(cpu, system, plugin_pointers, 0ULL, 0ULL);\n";
+cp.code() += "RV32IMACFD_raise(cpu, system, plugin_pointers, 0ULL, 0ULL);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -1009,7 +1007,7 @@ if (imm % 2ULL) { // conditional
 cp.code() += "{ // block\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "raise(cpu, system, plugin_pointers, 0ULL, 0ULL);\n";
+cp.code() += "RV32IMACFD_raise(cpu, system, plugin_pointers, 0ULL, 0ULL);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -1120,7 +1118,7 @@ cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, load_add
 cp.code() += "if (cpu->exception) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "RV32IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -1217,7 +1215,7 @@ cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, load_add
 cp.code() += "if (cpu->exception) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "RV32IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -1314,7 +1312,7 @@ cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, load_add
 cp.code() += "if (cpu->exception) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "RV32IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -1411,7 +1409,7 @@ cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, load_add
 cp.code() += "if (cpu->exception) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "RV32IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -1508,7 +1506,7 @@ cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, load_add
 cp.code() += "if (cpu->exception) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "RV32IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -1608,7 +1606,7 @@ cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, store_a
 cp.code() += "if (cpu->exception) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "RV32IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -1706,7 +1704,7 @@ cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, store_a
 cp.code() += "if (cpu->exception) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "RV32IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -1804,7 +1802,7 @@ cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, store_a
 cp.code() += "if (cpu->exception) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "RV32IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32MInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32MInstr.cpp
index 18d4ba3e48..15bfe3c3bb 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32MInstr.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32MInstr.cpp
@@ -1,13 +1,11 @@
 /**
- * Generated on Wed, 04 Oct 2023 17:01:33 +0200.
+ * Generated on Fri, 03 Nov 2023 13:22:23 +0100.
  *
  * This file contains the instruction behavior models of the RV32M
  * instruction set for the RV32IMACFD core architecture.
  */
 
 #include "RV32IMACFDArch.h"
-
-#define ETISS_ARCH_STATIC_FN_ONLY
 #include "RV32IMACFDFuncs.h"
 
 using namespace etiss;
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_ZifenceiInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_ZifenceiInstr.cpp
index 069792cd9b..f33616333d 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFD_ZifenceiInstr.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFD_ZifenceiInstr.cpp
@@ -1,13 +1,11 @@
 /**
- * Generated on Wed, 04 Oct 2023 17:01:33 +0200.
+ * Generated on Fri, 03 Nov 2023 13:22:23 +0100.
  *
  * This file contains the instruction behavior models of the Zifencei
  * instruction set for the RV32IMACFD core architecture.
  */
 
 #include "RV32IMACFDArch.h"
-
-#define ETISS_ARCH_STATIC_FN_ONLY
 #include "RV32IMACFDFuncs.h"
 
 using namespace etiss;
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_tum_csrInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_tum_csrInstr.cpp
index c045d9ea3c..4fb08933b4 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFD_tum_csrInstr.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFD_tum_csrInstr.cpp
@@ -1,13 +1,11 @@
 /**
- * Generated on Wed, 04 Oct 2023 17:01:33 +0200.
+ * Generated on Fri, 03 Nov 2023 13:22:23 +0100.
  *
  * This file contains the instruction behavior models of the tum_csr
  * instruction set for the RV32IMACFD core architecture.
  */
 
 #include "RV32IMACFDArch.h"
-
-#define ETISS_ARCH_STATIC_FN_ONLY
 #include "RV32IMACFDFuncs.h"
 
 using namespace etiss;
@@ -57,8 +55,8 @@ cp.code() += "etiss_uint32 xrs1 = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1
 if ((rd % 32ULL) != 0ULL) { // conditional
 { // block
 cp.code() += "{ // block\n";
-cp.code() += "etiss_uint32 xrd = csr_read(cpu, system, plugin_pointers, " + std::to_string(csr) + "ULL);\n";
-cp.code() += "csr_write(cpu, system, plugin_pointers, " + std::to_string(csr) + "ULL, xrs1);\n";
+cp.code() += "etiss_uint32 xrd = RV32IMACFD_csr_read(cpu, system, plugin_pointers, " + std::to_string(csr) + "ULL);\n";
+cp.code() += "RV32IMACFD_csr_write(cpu, system, plugin_pointers, " + std::to_string(csr) + "ULL, xrs1);\n";
 cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = xrd;\n";
 cp.code() += "} // block\n";
 } // block
@@ -66,7 +64,7 @@ cp.code() += "} // block\n";
 else { // conditional
 { // block
 cp.code() += "{ // block\n";
-cp.code() += "csr_write(cpu, system, plugin_pointers, " + std::to_string(csr) + "ULL, xrs1);\n";
+cp.code() += "RV32IMACFD_csr_write(cpu, system, plugin_pointers, " + std::to_string(csr) + "ULL, xrs1);\n";
 cp.code() += "} // block\n";
 } // block
 } // conditional
@@ -143,10 +141,10 @@ cp.code() += "} // block\n";
 } // block
 { // block
 cp.code() += "{ // block\n";
-cp.code() += "etiss_uint32 xrd = csr_read(cpu, system, plugin_pointers, " + std::to_string(csr) + "ULL);\n";
+cp.code() += "etiss_uint32 xrd = RV32IMACFD_csr_read(cpu, system, plugin_pointers, " + std::to_string(csr) + "ULL);\n";
 cp.code() += "etiss_uint32 xrs1 = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL];\n";
 if (rs1 != 0ULL) { // conditional
-cp.code() += "csr_write(cpu, system, plugin_pointers, " + std::to_string(csr) + "ULL, xrd | xrs1);\n";
+cp.code() += "RV32IMACFD_csr_write(cpu, system, plugin_pointers, " + std::to_string(csr) + "ULL, xrd | xrs1);\n";
 } // conditional
 if ((rd % 32ULL) != 0ULL) { // conditional
 cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = xrd;\n";
@@ -224,10 +222,10 @@ cp.code() += "} // block\n";
 } // block
 { // block
 cp.code() += "{ // block\n";
-cp.code() += "etiss_uint32 xrd = csr_read(cpu, system, plugin_pointers, " + std::to_string(csr) + "ULL);\n";
+cp.code() += "etiss_uint32 xrd = RV32IMACFD_csr_read(cpu, system, plugin_pointers, " + std::to_string(csr) + "ULL);\n";
 cp.code() += "etiss_uint32 xrs1 = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL];\n";
 if (rs1 != 0ULL) { // conditional
-cp.code() += "csr_write(cpu, system, plugin_pointers, " + std::to_string(csr) + "ULL, xrd & ~(xrs1));\n";
+cp.code() += "RV32IMACFD_csr_write(cpu, system, plugin_pointers, " + std::to_string(csr) + "ULL, xrd & ~(xrs1));\n";
 } // conditional
 if ((rd % 32ULL) != 0ULL) { // conditional
 cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = xrd;\n";
@@ -305,8 +303,8 @@ cp.code() += "} // block\n";
 } // block
 { // block
 cp.code() += "{ // block\n";
-cp.code() += "etiss_uint32 xrd = csr_read(cpu, system, plugin_pointers, " + std::to_string(csr) + "ULL);\n";
-cp.code() += "csr_write(cpu, system, plugin_pointers, " + std::to_string(csr) + "ULL, " + std::to_string((etiss_uint32)(zimm)) + "ULL);\n";
+cp.code() += "etiss_uint32 xrd = RV32IMACFD_csr_read(cpu, system, plugin_pointers, " + std::to_string(csr) + "ULL);\n";
+cp.code() += "RV32IMACFD_csr_write(cpu, system, plugin_pointers, " + std::to_string(csr) + "ULL, " + std::to_string((etiss_uint32)(zimm)) + "ULL);\n";
 if ((rd % 32ULL) != 0ULL) { // conditional
 cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = xrd;\n";
 } // conditional
@@ -383,9 +381,9 @@ cp.code() += "} // block\n";
 } // block
 { // block
 cp.code() += "{ // block\n";
-cp.code() += "etiss_uint32 xrd = csr_read(cpu, system, plugin_pointers, " + std::to_string(csr) + "ULL);\n";
+cp.code() += "etiss_uint32 xrd = RV32IMACFD_csr_read(cpu, system, plugin_pointers, " + std::to_string(csr) + "ULL);\n";
 if (zimm != 0ULL) { // conditional
-cp.code() += "csr_write(cpu, system, plugin_pointers, " + std::to_string(csr) + "ULL, xrd | " + std::to_string((etiss_uint32)(zimm)) + "ULL);\n";
+cp.code() += "RV32IMACFD_csr_write(cpu, system, plugin_pointers, " + std::to_string(csr) + "ULL, xrd | " + std::to_string((etiss_uint32)(zimm)) + "ULL);\n";
 } // conditional
 if ((rd % 32ULL) != 0ULL) { // conditional
 cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = xrd;\n";
@@ -463,9 +461,9 @@ cp.code() += "} // block\n";
 } // block
 { // block
 cp.code() += "{ // block\n";
-cp.code() += "etiss_uint32 xrd = csr_read(cpu, system, plugin_pointers, " + std::to_string(csr) + "ULL);\n";
+cp.code() += "etiss_uint32 xrd = RV32IMACFD_csr_read(cpu, system, plugin_pointers, " + std::to_string(csr) + "ULL);\n";
 if (zimm != 0ULL) { // conditional
-cp.code() += "csr_write(cpu, system, plugin_pointers, " + std::to_string(csr) + "ULL, xrd & " + std::to_string(~(((etiss_uint32)(zimm)))) + "ULL);\n";
+cp.code() += "RV32IMACFD_csr_write(cpu, system, plugin_pointers, " + std::to_string(csr) + "ULL, xrd & " + std::to_string(~(((etiss_uint32)(zimm)))) + "ULL);\n";
 } // conditional
 if ((rd % 32ULL) != 0ULL) { // conditional
 cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = xrd;\n";
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_tum_retInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_tum_retInstr.cpp
index 06f64048f1..4dc2310a0b 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFD_tum_retInstr.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFD_tum_retInstr.cpp
@@ -1,13 +1,11 @@
 /**
- * Generated on Wed, 04 Oct 2023 17:01:33 +0200.
+ * Generated on Fri, 03 Nov 2023 13:22:23 +0100.
  *
  * This file contains the instruction behavior models of the tum_ret
  * instruction set for the RV32IMACFD core architecture.
  */
 
 #include "RV32IMACFDArch.h"
-
-#define ETISS_ARCH_STATIC_FN_ONLY
 #include "RV32IMACFDFuncs.h"
 
 using namespace etiss;
@@ -46,7 +44,7 @@ cp.code() += "} // block\n";
 cp.code() += "{ // block\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "raise(cpu, system, plugin_pointers, 0ULL, 8LL + ((RV32IMACFD*)cpu)->PRIV);\n";
+cp.code() += "RV32IMACFD_raise(cpu, system, plugin_pointers, 0ULL, 8LL + ((RV32IMACFD*)cpu)->PRIV);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -117,21 +115,21 @@ cp.code() += "{ // block\n";
 cp.code() += "if (((RV32IMACFD*)cpu)->PRIV < 3LL) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "raise(cpu, system, plugin_pointers, 0ULL, 2LL);\n";
+cp.code() += "RV32IMACFD_raise(cpu, system, plugin_pointers, 0ULL, 2LL);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
 cp.code() += "} // conditional\n";
 cp.code() += "cpu->nextPc = *((RV32IMACFD*)cpu)->CSR[833LL];\n";
-cp.code() += "etiss_uint32 s = csr_read(cpu, system, plugin_pointers, 768LL);\n";
-cp.code() += "etiss_uint32 prev_prv = get_field(s, 6144LL);\n";
+cp.code() += "etiss_uint32 s = RV32IMACFD_csr_read(cpu, system, plugin_pointers, 768LL);\n";
+cp.code() += "etiss_uint32 prev_prv = RV32IMACFD_get_field(s, 6144LL);\n";
 cp.code() += "if (prev_prv != 3LL) { // conditional\n";
-cp.code() += "s = set_field(s, 131072LL, 0ULL);\n";
+cp.code() += "s = RV32IMACFD_set_field(s, 131072LL, 0ULL);\n";
 cp.code() += "} // conditional\n";
-cp.code() += "s = set_field(s, 8LL, get_field(s, 128LL));\n";
-cp.code() += "s = set_field(s, 128LL, 1ULL);\n";
-cp.code() += "s = set_field(s, 6144LL, (extension_enabled(cpu, system, plugin_pointers, 85ULL)) ? (0LL) : (3LL));\n";
-cp.code() += "csr_write(cpu, system, plugin_pointers, 768LL, s);\n";
+cp.code() += "s = RV32IMACFD_set_field(s, 8LL, RV32IMACFD_get_field(s, 128LL));\n";
+cp.code() += "s = RV32IMACFD_set_field(s, 128LL, 1ULL);\n";
+cp.code() += "s = RV32IMACFD_set_field(s, 6144LL, (RV32IMACFD_extension_enabled(cpu, system, plugin_pointers, 85ULL)) ? (0LL) : (3LL));\n";
+cp.code() += "RV32IMACFD_csr_write(cpu, system, plugin_pointers, 768LL, s);\n";
 cp.code() += "((RV32IMACFD*)cpu)->PRIV = (prev_prv) & 0x7;\n";
 cp.code() += "} // block\n";
 } // block
@@ -261,21 +259,21 @@ cp.code() += "} // block\n";
 } // block
 { // block
 cp.code() += "{ // block\n";
-cp.code() += "if (((RV32IMACFD*)cpu)->PRIV < ((get_field(csr_read(cpu, system, plugin_pointers, 768LL), 4194304LL)) ? (3LL) : (1LL))) { // conditional\n";
+cp.code() += "if (((RV32IMACFD*)cpu)->PRIV < ((RV32IMACFD_get_field(RV32IMACFD_csr_read(cpu, system, plugin_pointers, 768LL), 4194304LL)) ? (3LL) : (1LL))) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "raise(cpu, system, plugin_pointers, 0ULL, 2LL);\n";
+cp.code() += "RV32IMACFD_raise(cpu, system, plugin_pointers, 0ULL, 2LL);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
 cp.code() += "} // conditional\n";
 cp.code() += "cpu->nextPc = *((RV32IMACFD*)cpu)->CSR[321LL];\n";
-cp.code() += "etiss_uint32 s = csr_read(cpu, system, plugin_pointers, 256LL);\n";
-cp.code() += "etiss_uint32 prev_prv = get_field(s, 256LL);\n";
-cp.code() += "s = set_field(s, 2LL, get_field(s, 32LL));\n";
-cp.code() += "s = set_field(s, 32LL, 1ULL);\n";
-cp.code() += "s = set_field(s, 256LL, 0LL);\n";
-cp.code() += "csr_write(cpu, system, plugin_pointers, 768LL, s);\n";
+cp.code() += "etiss_uint32 s = RV32IMACFD_csr_read(cpu, system, plugin_pointers, 256LL);\n";
+cp.code() += "etiss_uint32 prev_prv = RV32IMACFD_get_field(s, 256LL);\n";
+cp.code() += "s = RV32IMACFD_set_field(s, 2LL, RV32IMACFD_get_field(s, 32LL));\n";
+cp.code() += "s = RV32IMACFD_set_field(s, 32LL, 1ULL);\n";
+cp.code() += "s = RV32IMACFD_set_field(s, 256LL, 0LL);\n";
+cp.code() += "RV32IMACFD_csr_write(cpu, system, plugin_pointers, 768LL, s);\n";
 cp.code() += "((RV32IMACFD*)cpu)->PRIV = (prev_prv) & 0x7;\n";
 cp.code() += "} // block\n";
 } // block
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_tum_rvaInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_tum_rvaInstr.cpp
index 363476b4df..dced7d903e 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFD_tum_rvaInstr.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFD_tum_rvaInstr.cpp
@@ -1,13 +1,11 @@
 /**
- * Generated on Wed, 04 Oct 2023 17:01:33 +0200.
+ * Generated on Fri, 03 Nov 2023 13:22:23 +0100.
  *
  * This file contains the instruction behavior models of the tum_rva
  * instruction set for the RV32IMACFD core architecture.
  */
 
 #include "RV32IMACFDArch.h"
-
-#define ETISS_ARCH_STATIC_FN_ONLY
 #include "RV32IMACFDFuncs.h"
 
 using namespace etiss;
@@ -62,7 +60,7 @@ cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (e
 cp.code() += "if (cpu->exception) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "RV32IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -171,7 +169,7 @@ cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (
 cp.code() += "if (cpu->exception) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "RV32IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_tum_semihostingInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_tum_semihostingInstr.cpp
index 2aceb3f379..bb39c1fec5 100644
--- a/ArchImpl/RV32IMACFD/RV32IMACFD_tum_semihostingInstr.cpp
+++ b/ArchImpl/RV32IMACFD/RV32IMACFD_tum_semihostingInstr.cpp
@@ -1,13 +1,11 @@
 /**
- * Generated on Wed, 04 Oct 2023 17:01:33 +0200.
+ * Generated on Fri, 03 Nov 2023 13:22:23 +0100.
  *
  * This file contains the instruction behavior models of the tum_semihosting
  * instruction set for the RV32IMACFD core architecture.
  */
 
 #include "RV32IMACFDArch.h"
-
-#define ETISS_ARCH_STATIC_FN_ONLY
 #include "RV32IMACFDFuncs.h"
 
 using namespace etiss;
@@ -52,7 +50,7 @@ cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, " + std:
 cp.code() += "if (cpu->exception) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "RV32IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -63,7 +61,7 @@ cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, " + std:
 cp.code() += "if (cpu->exception) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "RV32IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -74,7 +72,7 @@ cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, " + std:
 cp.code() += "if (cpu->exception) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "RV32IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -94,7 +92,7 @@ cp.code() += "else { // conditional\n";
 cp.code() += "{ // block\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "raise(cpu, system, plugin_pointers, 0ULL, 3LL);\n";
+cp.code() += "RV32IMACFD_raise(cpu, system, plugin_pointers, 0ULL, 3LL);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -109,7 +107,7 @@ cp.code() += "else { // conditional\n";
 cp.code() += "{ // block\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "raise(cpu, system, plugin_pointers, 0ULL, 3LL);\n";
+cp.code() += "RV32IMACFD_raise(cpu, system, plugin_pointers, 0ULL, 3LL);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
diff --git a/ArchImpl/RV64IMACFD/CMakeLists.txt b/ArchImpl/RV64IMACFD/CMakeLists.txt
index 5293cbb995..3a43d02b6e 100644
--- a/ArchImpl/RV64IMACFD/CMakeLists.txt
+++ b/ArchImpl/RV64IMACFD/CMakeLists.txt
@@ -1,4 +1,4 @@
-# Generated on Mon, 02 Oct 2023 18:56:15 +0200.
+# Generated on Fri, 03 Nov 2023 13:22:23 +0100.
 #
 # This file contains the CMake build info for the RV64IMACFD core architecture.
 
@@ -11,6 +11,7 @@ ADD_LIBRARY(${PROJECT_NAME} SHARED
 	RV64IMACFDArch.cpp
 	RV64IMACFDArchLib.cpp
 	RV64IMACFDArchSpecificImp.cpp
+	RV64IMACFDFuncs.c
 	RV64IMACFDInstr.cpp
 	RV64IMACFD_RV32IInstr.cpp
 	RV64IMACFD_RV64IInstr.cpp
@@ -30,6 +31,7 @@ ADD_LIBRARY(${PROJECT_NAME} SHARED
 	RV64IMACFD_tum_retInstr.cpp
 	RV64IMACFD_tum_rvaInstr.cpp
 	RV64IMACFD_tum_rva64Instr.cpp
+	RV64IMACFD_tum_rvmInstr.cpp
 	RV64IMACFD_tum_semihostingInstr.cpp
 )
 
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD.h b/ArchImpl/RV64IMACFD/RV64IMACFD.h
index d88be9a2d7..13349104f5 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD.h
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD.h
@@ -1,5 +1,5 @@
 /**
- * Generated on Mon, 02 Oct 2023 18:56:15 +0200.
+ * Generated on Fri, 03 Nov 2023 13:22:23 +0100.
  *
  * This file contains the registers for the RV64IMACFD core architecture.
  */
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFDArch.cpp b/ArchImpl/RV64IMACFD/RV64IMACFDArch.cpp
index 3876c0ec1f..a2292b9aa8 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFDArch.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFDArch.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Mon, 02 Oct 2023 18:56:15 +0200.
+ * Generated on Fri, 03 Nov 2023 13:22:23 +0100.
  *
  * This file contains the architecture class for the RV64IMACFD core architecture.
  */
@@ -35,8 +35,6 @@
  *********************************************************************************************************************************/
 
 #include "RV64IMACFDArch.h"
-
-#define ETISS_ARCH_STATIC_FN_ONLY
 #include "RV64IMACFDFuncs.h"
 
 #define RV64IMACFD_DEBUG_CALL 0
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFDArch.h b/ArchImpl/RV64IMACFD/RV64IMACFDArch.h
index 5abf67a078..461a1d6b1b 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFDArch.h
+++ b/ArchImpl/RV64IMACFD/RV64IMACFDArch.h
@@ -1,5 +1,5 @@
 /**
- * Generated on Mon, 02 Oct 2023 18:56:15 +0200.
+ * Generated on Fri, 03 Nov 2023 13:22:23 +0100.
  *
  * This file contains the architecture class for the RV64IMACFD core architecture.
  */
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFDArchLib.cpp b/ArchImpl/RV64IMACFD/RV64IMACFDArchLib.cpp
index ae653db6e9..1c05bd91d9 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFDArchLib.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFDArchLib.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Mon, 02 Oct 2023 18:56:15 +0200.
+ * Generated on Fri, 03 Nov 2023 13:22:23 +0100.
  *
  * This file contains the library interface for the RV64IMACFD core architecture.
  */
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFDArchSpecificImp.cpp b/ArchImpl/RV64IMACFD/RV64IMACFDArchSpecificImp.cpp
index 29ce558a57..0a32ab8dd8 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFDArchSpecificImp.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFDArchSpecificImp.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Thu, 24 Feb 2022 17:15:20 +0100.
+ * Generated on Fri, 03 Nov 2023 13:22:23 +0100.
  *
  * This file contains the architecture specific implementation for the RV64IMACFD
  * core architecture.
@@ -12,11 +12,8 @@
 
 #include "RV64IMACFDArch.h"
 #include "RV64IMACFDArchSpecificImp.h"
-
-#define ETISS_ARCH_STATIC_FN_ONLY
-extern "C" {
 #include "RV64IMACFDFuncs.h"
-}
+
 /**
 	@brief This function will be called automatically in order to handling exceptions such as interrupt, system call, illegal instructions
 
@@ -33,9 +30,8 @@ extern "C" {
 */
 etiss::int32 RV64IMACFDArch::handleException(etiss::int32 cause, ETISS_CPU * cpu)
 {
-	translate_exc_code(cpu, nullptr, nullptr, cause);
+	RV64IMACFD_translate_exc_code(cpu, nullptr, nullptr, cause);
 	cpu->instructionPointer = cpu->nextPc;
-
 	return 0;
 }
 
@@ -125,7 +121,7 @@ error_code += R_error_code_0.read(ba) << 0;
 // -----------------------------------------------------------------------------
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, " + std::to_string(error_code) + "ULL);\n";
+cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, " + std::to_string(error_code) + "ULL);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -172,7 +168,7 @@ error_code += R_error_code_0.read(ba) << 0;
 // -----------------------------------------------------------------------------
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, " + std::to_string(error_code) + "ULL);\n";
+cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, " + std::to_string(error_code) + "ULL);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFDArchSpecificImp.h b/ArchImpl/RV64IMACFD/RV64IMACFDArchSpecificImp.h
index 64d12881f8..8b94f7a27d 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFDArchSpecificImp.h
+++ b/ArchImpl/RV64IMACFD/RV64IMACFDArchSpecificImp.h
@@ -1,5 +1,5 @@
 /**
- * Generated on Mon, 02 Oct 2023 18:56:15 +0200.
+ * Generated on Fri, 03 Nov 2023 13:22:23 +0100.
  *
  * This file contains the architecture specific header for the RV64IMACFD
  * core architecture.
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFDFuncs.c b/ArchImpl/RV64IMACFD/RV64IMACFDFuncs.c
new file mode 100644
index 0000000000..d42498b9b2
--- /dev/null
+++ b/ArchImpl/RV64IMACFD/RV64IMACFDFuncs.c
@@ -0,0 +1,368 @@
+/**
+ * Generated on Fri, 03 Nov 2023 13:22:23 +0100.
+ *
+ * This file contains the function implementations for the RV64IMACFD core architecture.
+ */
+
+#include "RV64IMACFDFuncs.h"
+
+etiss_uint8 RV64IMACFD_extension_enabled(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers, etiss_int8 extension)
+{
+{ // block
+return (*((RV64IMACFD*)cpu)->CSR[769LL] >> (extension - 65ULL)) & 1ULL;
+} // block
+}
+
+etiss_uint8 RV64IMACFD_get_rm(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers, etiss_uint8 rm)
+{
+{ // block
+if (rm == 7ULL) { // conditional
+rm = ((((((RV64IMACFD*)cpu)->FCSR) >> (5ULL)) & 7)) & 0x7;
+} // conditional
+if (rm > 4ULL) { // conditional
+RV64IMACFD_raise(cpu, system, plugin_pointers, 0ULL, 2LL);
+} // conditional
+return rm;
+} // block
+}
+
+etiss_uint64 RV64IMACFD_sstatus_mask(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers)
+{
+{ // block
+etiss_uint64 mask = 0ULL;
+if (RV64IMACFD_extension_enabled(cpu, system, plugin_pointers, 83ULL)) { // conditional
+{ // block
+mask = mask | 5767458ULL;
+if (RV64IMACFD_extension_enabled(cpu, system, plugin_pointers, 86ULL)) { // conditional
+mask = mask | 1536LL;
+} // conditional
+if (RV64IMACFD_extension_enabled(cpu, system, plugin_pointers, 70ULL)) { // conditional
+mask = mask | 24576LL;
+} // conditional
+if (RV64IMACFD_extension_enabled(cpu, system, plugin_pointers, 88ULL)) { // conditional
+mask = mask | 98304LL;
+} // conditional
+if ((RV64IMACFD_get_field(*((RV64IMACFD*)cpu)->CSR[384LL], 17293822569102704640ULL))) { // conditional
+mask = mask | 262144LL;
+} // conditional
+} // block
+} // conditional
+return mask;
+} // block
+}
+
+etiss_uint64 RV64IMACFD_mstatus_mask(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers)
+{
+{ // block
+etiss_uint64 mask = 6280ULL;
+return mask | RV64IMACFD_sstatus_mask(cpu, system, plugin_pointers);
+} // block
+}
+
+etiss_uint64 RV64IMACFD_csr_read(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers, etiss_uint32 csr)
+{
+{ // block
+if (csr == 1LL) { // conditional
+return *((RV64IMACFD*)cpu)->CSR[3LL] & 31ULL;
+} // conditional
+if (csr == 2LL) { // conditional
+return (*((RV64IMACFD*)cpu)->CSR[3LL] >> 5ULL) & 7ULL;
+} // conditional
+if (csr == 3072LL) { // conditional
+return etiss_get_cycles(cpu, system, plugin_pointers);
+} // conditional
+if (csr == 3200LL) { // conditional
+return etiss_get_cycles(cpu, system, plugin_pointers) >> 32ULL;
+} // conditional
+if (csr == 3073LL) { // conditional
+return etiss_get_time();
+} // conditional
+if (csr == 3201LL) { // conditional
+return etiss_get_time() >> 32ULL;
+} // conditional
+if (csr == 3074LL) { // conditional
+return etiss_get_instret(cpu, system, plugin_pointers);
+} // conditional
+if (csr == 3202LL) { // conditional
+return etiss_get_instret(cpu, system, plugin_pointers) >> 32ULL;
+} // conditional
+if (csr == 768LL || csr == 256LL) { // conditional
+return *((RV64IMACFD*)cpu)->CSR[768LL] | 8589934592ULL | 34359738368ULL;
+} // conditional
+if (csr == 769LL) { // conditional
+return (((2ULL) << 62) | ((((*((RV64IMACFD*)cpu)->CSR[769LL]) >> (0ULL)) & 4611686018427387903)));
+} // conditional
+return *((RV64IMACFD*)cpu)->CSR[csr];
+} // block
+}
+
+void RV64IMACFD_csr_write(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers, etiss_uint32 csr, etiss_uint64 val)
+{
+{ // block
+if (csr == 1LL) { // conditional
+*((RV64IMACFD*)cpu)->CSR[3LL] = (*((RV64IMACFD*)cpu)->CSR[3LL] & 224ULL) | (val & 31ULL);
+} // conditional
+ else if (csr == 2LL) { // conditional
+*((RV64IMACFD*)cpu)->CSR[3LL] = ((val & 7ULL) << 5ULL) | (*((RV64IMACFD*)cpu)->CSR[3LL] & 31ULL);
+} // conditional
+ else if (csr == 3LL) { // conditional
+*((RV64IMACFD*)cpu)->CSR[3LL] = val & 255ULL;
+} // conditional
+ else if (csr == 768LL) { // conditional
+*((RV64IMACFD*)cpu)->CSR[768LL] = val & RV64IMACFD_mstatus_mask(cpu, system, plugin_pointers);
+} // conditional
+ else if (csr == 256LL) { // conditional
+*((RV64IMACFD*)cpu)->CSR[768LL] = val & RV64IMACFD_sstatus_mask(cpu, system, plugin_pointers);
+} // conditional
+ else if (csr != 769LL) { // conditional
+*((RV64IMACFD*)cpu)->CSR[csr] = val;
+} // conditional
+} // block
+}
+
+etiss_uint64 RV64IMACFD_get_field(etiss_uint64 reg, etiss_uint64 mask)
+{
+{ // block
+return (reg & mask) / (mask & ~((mask << 1ULL)));
+} // block
+}
+
+etiss_uint64 RV64IMACFD_set_field(etiss_uint64 reg, etiss_uint64 mask, etiss_uint64 val)
+{
+{ // block
+return ((reg & ~(mask)) | ((val * (mask & ~((mask << 1ULL)))) & mask));
+} // block
+}
+
+etiss_uint8 RV64IMACFD_ctz(etiss_uint64 val)
+{
+{ // block
+if (!(val)) { // conditional
+return 0ULL;
+} // conditional
+etiss_uint8 res = 0ULL;
+if ((val << 32ULL) == 0ULL) { // conditional
+{ // block
+res = res + 32ULL;
+val = val >> 32ULL;
+} // block
+} // conditional
+if ((val << 48ULL) == 0ULL) { // conditional
+{ // block
+res = res + 16ULL;
+val = val >> 16ULL;
+} // block
+} // conditional
+if ((val << 56ULL) == 0ULL) { // conditional
+{ // block
+res = res + 8ULL;
+val = val >> 8ULL;
+} // block
+} // conditional
+if ((val << 60ULL) == 0ULL) { // conditional
+{ // block
+res = res + 4ULL;
+val = val >> 4ULL;
+} // block
+} // conditional
+if ((val << 62ULL) == 0ULL) { // conditional
+{ // block
+res = res + 2ULL;
+val = val >> 2ULL;
+} // block
+} // conditional
+if ((val << 63ULL) == 0ULL) { // conditional
+{ // block
+res = res + 1ULL;
+val = val >> 1ULL;
+} // block
+} // conditional
+return res;
+} // block
+}
+
+void RV64IMACFD_raise(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers, etiss_int32 irq, etiss_uint64 mcause)
+{
+cpu->return_pending = 1;
+cpu->exception = 0;
+{ // block
+etiss_uint64 epc = cpu->instructionPointer;
+etiss_uint64 deleg = 0ULL;
+etiss_uint64 vector = 0ULL;
+etiss_uint64 bit = mcause;
+etiss_int32 irq2 = (mcause & 9223372036854775808ULL) != 0ULL;
+if (irq2) { // conditional
+{ // block
+deleg = ((((RV64IMACFD*)cpu)->PRIV <= 1LL)) ? (*((RV64IMACFD*)cpu)->CSR[771LL]) : (0ULL);
+bit = bit & 9223372036854775807ULL;
+} // block
+} // conditional
+else { // conditional
+{ // block
+deleg = ((((RV64IMACFD*)cpu)->PRIV <= 1LL)) ? (*((RV64IMACFD*)cpu)->CSR[770LL]) : (0ULL);
+} // block
+} // conditional
+if (((RV64IMACFD*)cpu)->PRIV <= 1LL && (deleg >> bit) & 1ULL) { // conditional
+{ // block
+vector = ((*((RV64IMACFD*)cpu)->CSR[261LL] & 1ULL) && irq2) ? (bit * 4ULL) : (0ULL);
+cpu->nextPc = (*((RV64IMACFD*)cpu)->CSR[261LL] & -2LL) + vector;
+*((RV64IMACFD*)cpu)->CSR[321LL] = epc;
+*((RV64IMACFD*)cpu)->CSR[322LL] = mcause;
+etiss_uint64 s = RV64IMACFD_csr_read(cpu, system, plugin_pointers, 256LL);
+s = RV64IMACFD_set_field(s, 32LL, RV64IMACFD_get_field(s, 2LL));
+s = RV64IMACFD_set_field(s, 256LL, ((RV64IMACFD*)cpu)->PRIV);
+s = RV64IMACFD_set_field(s, 2LL, 0ULL);
+RV64IMACFD_csr_write(cpu, system, plugin_pointers, 256LL, s);
+((RV64IMACFD*)cpu)->PRIV = (1LL) & 0x7;
+} // block
+} // conditional
+else { // conditional
+{ // block
+vector = ((*((RV64IMACFD*)cpu)->CSR[773LL] & 1ULL) && irq2) ? (bit * 4ULL) : (0ULL);
+cpu->nextPc = (*((RV64IMACFD*)cpu)->CSR[773LL] & -2LL) + vector;
+*((RV64IMACFD*)cpu)->CSR[833LL] = epc;
+*((RV64IMACFD*)cpu)->CSR[834LL] = mcause;
+etiss_uint64 s = RV64IMACFD_csr_read(cpu, system, plugin_pointers, 768LL);
+s = RV64IMACFD_set_field(s, 128LL, RV64IMACFD_get_field(s, 8LL));
+s = RV64IMACFD_set_field(s, 6144LL, ((RV64IMACFD*)cpu)->PRIV);
+s = RV64IMACFD_set_field(s, 8LL, 0ULL);
+RV64IMACFD_csr_write(cpu, system, plugin_pointers, 768LL, s);
+((RV64IMACFD*)cpu)->PRIV = (3LL) & 0x7;
+} // block
+} // conditional
+} // block
+}
+
+void RV64IMACFD_translate_exc_code(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers, etiss_int32 cause)
+{
+{ // block
+etiss_uint64 code = 0ULL;
+if (cause == -2147483648LL) { // conditional
+return;
+} // conditional
+ else if (cause == -5LL) { // conditional
+code = 5LL;
+} // conditional
+ else if (cause == -14LL) { // conditional
+code = 13LL;
+} // conditional
+ else if (cause == -6LL) { // conditional
+code = 7LL;
+} // conditional
+ else if (cause == -15LL) { // conditional
+code = 15LL;
+} // conditional
+ else if (cause == -7LL) { // conditional
+code = 1LL;
+} // conditional
+ else if (cause == -9LL) { // conditional
+{ // block
+code = RV64IMACFD_calc_irq_mcause(cpu, system, plugin_pointers);
+if (!(code)) { // conditional
+return;
+} // conditional
+} // block
+} // conditional
+else { // conditional
+code = 2LL;
+} // conditional
+RV64IMACFD_raise(cpu, system, plugin_pointers, 0ULL, code);
+} // block
+}
+
+etiss_uint64 RV64IMACFD_calc_irq_mcause(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers)
+{
+{ // block
+etiss_uint64 pending_interrupts = *((RV64IMACFD*)cpu)->CSR[772LL] & *((RV64IMACFD*)cpu)->CSR[836LL];
+if (!(pending_interrupts)) { // conditional
+return 0ULL;
+} // conditional
+etiss_uint64 mie = RV64IMACFD_get_field(*((RV64IMACFD*)cpu)->CSR[768LL], 8LL);
+etiss_uint64 m_enabled = ((RV64IMACFD*)cpu)->PRIV < 3LL || (((RV64IMACFD*)cpu)->PRIV == 3LL && mie);
+etiss_uint64 enabled_interrupts = pending_interrupts & ~(*((RV64IMACFD*)cpu)->CSR[771LL]) & -(m_enabled);
+if (enabled_interrupts == 0ULL) { // conditional
+{ // block
+etiss_uint64 deleg = *((RV64IMACFD*)cpu)->CSR[771LL];
+etiss_uint64 sie = RV64IMACFD_get_field(RV64IMACFD_csr_read(cpu, system, plugin_pointers, 256LL), 2LL);
+etiss_uint64 s_enabled = ((RV64IMACFD*)cpu)->PRIV < 1LL || (((RV64IMACFD*)cpu)->PRIV == 1LL && sie);
+enabled_interrupts = pending_interrupts & deleg & -(s_enabled);
+} // block
+} // conditional
+if (enabled_interrupts) { // conditional
+{ // block
+if (enabled_interrupts >> 12ULL) { // conditional
+enabled_interrupts = enabled_interrupts >> 12ULL << 12ULL;
+} // conditional
+ else if (enabled_interrupts & 2048LL) { // conditional
+enabled_interrupts = 2048LL;
+} // conditional
+ else if (enabled_interrupts & 8LL) { // conditional
+enabled_interrupts = 8LL;
+} // conditional
+ else if (enabled_interrupts & 128LL) { // conditional
+enabled_interrupts = 128LL;
+} // conditional
+ else if (enabled_interrupts & 512LL) { // conditional
+enabled_interrupts = 512LL;
+} // conditional
+ else if (enabled_interrupts & 2LL) { // conditional
+enabled_interrupts = 2LL;
+} // conditional
+ else if (enabled_interrupts & 32LL) { // conditional
+enabled_interrupts = 32LL;
+} // conditional
+ else if (enabled_interrupts & 8192LL) { // conditional
+enabled_interrupts = 8192LL;
+} // conditional
+ else if (enabled_interrupts & 1024LL) { // conditional
+enabled_interrupts = 1024LL;
+} // conditional
+ else if (enabled_interrupts & 4LL) { // conditional
+enabled_interrupts = 4LL;
+} // conditional
+ else if (enabled_interrupts & 64LL) { // conditional
+enabled_interrupts = 64LL;
+} // conditional
+else { // conditional
+return 0ULL;
+} // conditional
+return 9223372036854775808ULL | RV64IMACFD_ctz(enabled_interrupts);
+} // block
+} // conditional
+return 0ULL;
+} // block
+}
+
+void RV64IMACFD_check_irq(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers)
+{
+{ // block
+etiss_uint64 irq_mcause = RV64IMACFD_calc_irq_mcause(cpu, system, plugin_pointers);
+if (irq_mcause) { // conditional
+RV64IMACFD_raise(cpu, system, plugin_pointers, 1ULL, irq_mcause);
+} // conditional
+} // block
+}
+
+etiss_int64 RV64IMACFD_mulh(etiss_int64 x, etiss_int64 y)
+{
+{ // block
+etiss_int128 res = (etiss_int128)(x) * (etiss_int128)(y);
+return (etiss_int64)((res >> 64ULL));
+} // block
+}
+
+etiss_int64 RV64IMACFD_mulhsu(etiss_int64 x, etiss_uint64 y)
+{
+{ // block
+etiss_int128 res = (etiss_int128)(x) * (etiss_uint128)(y);
+return (etiss_int64)((res >> 64ULL));
+} // block
+}
+
+etiss_uint64 RV64IMACFD_mulhu(etiss_uint64 x, etiss_uint64 y)
+{
+{ // block
+etiss_uint128 res = (etiss_uint128)(x) * (etiss_uint128)(y);
+return (etiss_uint64)((res >> 64ULL));
+} // block
+}
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFDFuncs.h b/ArchImpl/RV64IMACFD/RV64IMACFDFuncs.h
index 097e662ebe..93fec02cf9 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFDFuncs.h
+++ b/ArchImpl/RV64IMACFD/RV64IMACFDFuncs.h
@@ -1,449 +1,124 @@
 /**
- * Generated on Wed, 04 Oct 2023 17:01:33 +0200.
+ * Generated on Fri, 03 Nov 2023 13:22:23 +0100.
  *
- * This file contains the function macros for the RV64IMACFD core architecture.
+ * This file contains the function prototypes for the RV64IMACFD core architecture.
  */
 
 #ifndef __RV64IMACFD_FUNCS_H
 #define __RV64IMACFD_FUNCS_H
 
-#ifndef ETISS_ARCH_STATIC_FN_ONLY
-#include "Arch/RV64IMACFD/RV64IMACFD.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "RV64IMACFD.h"
 #include "etiss/jit/CPU.h"
 #include "etiss/jit/System.h"
 #include "etiss/jit/ReturnCode.h"
-#endif
 
 
+void leave(etiss_int32 priv_lvl);
 
-extern void leave(etiss_int32 priv_lvl);
+void wait(etiss_int32 flag);
 
-extern void wait(etiss_int32 flag);
+etiss_uint8 RV64IMACFD_extension_enabled(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers, etiss_int8 extension);
 
-static inline etiss_uint8 extension_enabled(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers, etiss_int8 extension);
+etiss_uint32 fadd_s(etiss_uint32, etiss_uint32, etiss_uint8);
 
-extern etiss_uint32 fadd_s(etiss_uint32, etiss_uint32, etiss_uint8);
+etiss_uint32 fsub_s(etiss_uint32, etiss_uint32, etiss_uint8);
 
-extern etiss_uint32 fsub_s(etiss_uint32, etiss_uint32, etiss_uint8);
+etiss_uint32 fmul_s(etiss_uint32, etiss_uint32, etiss_uint8);
 
-extern etiss_uint32 fmul_s(etiss_uint32, etiss_uint32, etiss_uint8);
+etiss_uint32 fdiv_s(etiss_uint32, etiss_uint32, etiss_uint8);
 
-extern etiss_uint32 fdiv_s(etiss_uint32, etiss_uint32, etiss_uint8);
+etiss_uint32 fmadd_s(etiss_uint32, etiss_uint32, etiss_uint32, etiss_uint32, etiss_uint8);
 
-extern etiss_uint32 fmadd_s(etiss_uint32, etiss_uint32, etiss_uint32, etiss_uint32, etiss_uint8);
+etiss_uint32 fsel_s(etiss_uint32, etiss_uint32, etiss_uint32);
 
-extern etiss_uint32 fsel_s(etiss_uint32, etiss_uint32, etiss_uint32);
+etiss_uint32 fsqrt_s(etiss_uint32, etiss_uint8);
 
-extern etiss_uint32 fsqrt_s(etiss_uint32, etiss_uint8);
+etiss_uint32 fcmp_s(etiss_uint32, etiss_uint32, etiss_uint32);
 
-extern etiss_uint32 fcmp_s(etiss_uint32, etiss_uint32, etiss_uint32);
+etiss_uint32 fcvt_s(etiss_uint32, etiss_uint32, etiss_uint8);
 
-extern etiss_uint32 fcvt_s(etiss_uint32, etiss_uint32, etiss_uint8);
+etiss_uint64 fcvt_32_64(etiss_uint32, etiss_uint32, etiss_uint8);
 
-extern etiss_uint64 fcvt_32_64(etiss_uint32, etiss_uint32, etiss_uint8);
+etiss_uint32 fcvt_64_32(etiss_uint64, etiss_uint32, etiss_uint8);
 
-extern etiss_uint32 fcvt_64_32(etiss_uint64, etiss_uint32, etiss_uint8);
+etiss_uint32 unbox_s(etiss_uint64);
 
-extern etiss_uint32 unbox_s(etiss_uint64);
+etiss_uint32 fclass_s(etiss_uint32);
 
-extern etiss_uint32 fclass_s(etiss_uint32);
+etiss_uint32 fget_flags();
 
-extern etiss_uint32 fget_flags();
+etiss_uint8 RV64IMACFD_get_rm(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers, etiss_uint8 rm);
 
-static inline etiss_uint8 get_rm(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers, etiss_uint8 rm);
+etiss_uint64 fadd_d(etiss_uint64, etiss_uint64, etiss_uint8);
 
-extern etiss_uint64 fadd_d(etiss_uint64, etiss_uint64, etiss_uint8);
+etiss_uint64 fsub_d(etiss_uint64, etiss_uint64, etiss_uint8);
 
-extern etiss_uint64 fsub_d(etiss_uint64, etiss_uint64, etiss_uint8);
+etiss_uint64 fmul_d(etiss_uint64, etiss_uint64, etiss_uint8);
 
-extern etiss_uint64 fmul_d(etiss_uint64, etiss_uint64, etiss_uint8);
+etiss_uint64 fdiv_d(etiss_uint64, etiss_uint64, etiss_uint8);
 
-extern etiss_uint64 fdiv_d(etiss_uint64, etiss_uint64, etiss_uint8);
+etiss_uint64 fmadd_d(etiss_uint64, etiss_uint64, etiss_uint64, etiss_uint32, etiss_uint8);
 
-extern etiss_uint64 fmadd_d(etiss_uint64, etiss_uint64, etiss_uint64, etiss_uint32, etiss_uint8);
+etiss_uint64 fsel_d(etiss_uint64, etiss_uint64, etiss_uint32);
 
-extern etiss_uint64 fsel_d(etiss_uint64, etiss_uint64, etiss_uint32);
+etiss_uint64 fsqrt_d(etiss_uint64, etiss_uint8);
 
-extern etiss_uint64 fsqrt_d(etiss_uint64, etiss_uint8);
+etiss_uint64 fcmp_d(etiss_uint64, etiss_uint64, etiss_uint32);
 
-extern etiss_uint64 fcmp_d(etiss_uint64, etiss_uint64, etiss_uint32);
+etiss_uint64 fcvt_d(etiss_uint64, etiss_uint32, etiss_uint8);
 
-extern etiss_uint64 fcvt_d(etiss_uint64, etiss_uint32, etiss_uint8);
+etiss_uint32 fconv_d2f(etiss_uint64, etiss_uint8);
 
-extern etiss_uint32 fconv_d2f(etiss_uint64, etiss_uint8);
+etiss_uint64 fconv_f2d(etiss_uint32, etiss_uint8);
 
-extern etiss_uint64 fconv_f2d(etiss_uint32, etiss_uint8);
+etiss_uint64 unbox_d(etiss_uint64);
 
-extern etiss_uint64 unbox_d(etiss_uint64);
+etiss_uint64 fclass_d(etiss_uint64);
 
-extern etiss_uint64 fclass_d(etiss_uint64);
+etiss_uint64 etiss_get_cycles(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers);
 
-extern etiss_uint64 etiss_get_cycles(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers);
+etiss_uint64 etiss_get_time();
 
-extern etiss_uint64 etiss_get_time();
+etiss_uint64 etiss_get_instret(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers);
 
-extern etiss_uint64 etiss_get_instret(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers);
+etiss_uint64 RV64IMACFD_sstatus_mask(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers);
 
-static inline etiss_uint64 sstatus_mask(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers);
+etiss_uint64 RV64IMACFD_mstatus_mask(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers);
 
-static inline etiss_uint64 mstatus_mask(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers);
+etiss_uint64 RV64IMACFD_csr_read(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers, etiss_uint32 csr);
 
-static inline etiss_uint64 csr_read(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers, etiss_uint32 csr);
+void RV64IMACFD_csr_write(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers, etiss_uint32 csr, etiss_uint64 val);
 
-static inline void csr_write(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers, etiss_uint32 csr, etiss_uint64 val);
+etiss_uint64 RV64IMACFD_get_field(etiss_uint64 reg, etiss_uint64 mask);
 
-static inline etiss_uint64 get_field(etiss_uint64 reg, etiss_uint64 mask);
+etiss_uint64 RV64IMACFD_set_field(etiss_uint64 reg, etiss_uint64 mask, etiss_uint64 val);
 
-static inline etiss_uint64 set_field(etiss_uint64 reg, etiss_uint64 mask, etiss_uint64 val);
+etiss_uint8 RV64IMACFD_ctz(etiss_uint64 val);
 
-static inline etiss_uint8 ctz(etiss_uint64 val);
+void RV64IMACFD_raise(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers, etiss_int32 irq, etiss_uint64 mcause);
 
-static inline void raise(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers, etiss_int32 irq, etiss_uint64 mcause);
+void RV64IMACFD_translate_exc_code(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers, etiss_int32 cause);
 
-static inline void translate_exc_code(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers, etiss_int32 cause);
+etiss_uint64 RV64IMACFD_calc_irq_mcause(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers);
 
-static inline etiss_uint64 calc_irq_mcause(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers);
+void RV64IMACFD_check_irq(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers);
 
-static inline void check_irq(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers);
+etiss_int64 RV64IMACFD_mulh(etiss_int64 x, etiss_int64 y);
 
-extern etiss_uint8 etiss_semihost_enabled();
+etiss_int64 RV64IMACFD_mulhsu(etiss_int64 x, etiss_uint64 y);
 
-extern etiss_int64 etiss_semihost(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers, etiss_uint32 XLEN, etiss_uint64 operation, etiss_uint64 parameter);
+etiss_uint64 RV64IMACFD_mulhu(etiss_uint64 x, etiss_uint64 y);
 
-static inline etiss_uint8 extension_enabled(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers, etiss_int8 extension)
-{
-{ // block
-return (*((RV64IMACFD*)cpu)->CSR[769LL] >> (extension - 65ULL)) & 1ULL;
-} // block
-}
+etiss_uint8 etiss_semihost_enabled();
 
-static inline etiss_uint8 get_rm(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers, etiss_uint8 rm)
-{
-{ // block
-if (rm == 7ULL) { // conditional
-rm = ((((((RV64IMACFD*)cpu)->FCSR) >> (5ULL)) & 7)) & 0x7;
-} // conditional
-if (rm > 4ULL) { // conditional
-raise(cpu, system, plugin_pointers, 0ULL, 2LL);
-} // conditional
-return rm;
-} // block
-}
-
-static inline etiss_uint64 sstatus_mask(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers)
-{
-{ // block
-etiss_uint64 mask = 0ULL;
-if (extension_enabled(cpu, system, plugin_pointers, 83ULL)) { // conditional
-{ // block
-mask = mask | 5767458ULL;
-if (extension_enabled(cpu, system, plugin_pointers, 86ULL)) { // conditional
-mask = mask | 1536LL;
-} // conditional
-if (extension_enabled(cpu, system, plugin_pointers, 70ULL)) { // conditional
-mask = mask | 24576LL;
-} // conditional
-if (extension_enabled(cpu, system, plugin_pointers, 88ULL)) { // conditional
-mask = mask | 98304LL;
-} // conditional
-if ((get_field(*((RV64IMACFD*)cpu)->CSR[384LL], 17293822569102704640ULL))) { // conditional
-mask = mask | 262144LL;
-} // conditional
-} // block
-} // conditional
-return mask;
-} // block
-}
-
-static inline etiss_uint64 mstatus_mask(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers)
-{
-{ // block
-etiss_uint64 mask = 6280ULL;
-return mask | sstatus_mask(cpu, system, plugin_pointers);
-} // block
-}
-
-static inline etiss_uint64 csr_read(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers, etiss_uint32 csr)
-{
-{ // block
-if (csr == 1LL) { // conditional
-return *((RV64IMACFD*)cpu)->CSR[3LL] & 31ULL;
-} // conditional
-if (csr == 2LL) { // conditional
-return (*((RV64IMACFD*)cpu)->CSR[3LL] >> 5ULL) & 7ULL;
-} // conditional
-if (csr == 3072LL) { // conditional
-return etiss_get_cycles(cpu, system, plugin_pointers);
-} // conditional
-if (csr == 3200LL) { // conditional
-return etiss_get_cycles(cpu, system, plugin_pointers) >> 32ULL;
-} // conditional
-if (csr == 3073LL) { // conditional
-return etiss_get_time();
-} // conditional
-if (csr == 3201LL) { // conditional
-return etiss_get_time() >> 32ULL;
-} // conditional
-if (csr == 3074LL) { // conditional
-return etiss_get_instret(cpu, system, plugin_pointers);
-} // conditional
-if (csr == 3202LL) { // conditional
-return etiss_get_instret(cpu, system, plugin_pointers) >> 32ULL;
-} // conditional
-if (csr == 768LL || csr == 256LL) { // conditional
-return *((RV64IMACFD*)cpu)->CSR[768LL] | 8589934592ULL | 34359738368ULL;
-} // conditional
-if (csr == 769LL) { // conditional
-return (((2ULL) << 62) | ((((*((RV64IMACFD*)cpu)->CSR[769LL]) >> (0ULL)) & 4611686018427387903)));
-} // conditional
-return *((RV64IMACFD*)cpu)->CSR[csr];
-} // block
-}
-
-static inline void csr_write(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers, etiss_uint32 csr, etiss_uint64 val)
-{
-{ // block
-if (csr == 1LL) { // conditional
-*((RV64IMACFD*)cpu)->CSR[3LL] = (*((RV64IMACFD*)cpu)->CSR[3LL] & 224ULL) | (val & 31ULL);
-} // conditional
- else if (csr == 2LL) { // conditional
-*((RV64IMACFD*)cpu)->CSR[3LL] = ((val & 7ULL) << 5ULL) | (*((RV64IMACFD*)cpu)->CSR[3LL] & 31ULL);
-} // conditional
- else if (csr == 3LL) { // conditional
-*((RV64IMACFD*)cpu)->CSR[3LL] = val & 255ULL;
-} // conditional
- else if (csr == 768LL) { // conditional
-*((RV64IMACFD*)cpu)->CSR[768LL] = val & mstatus_mask(cpu, system, plugin_pointers);
-} // conditional
- else if (csr == 256LL) { // conditional
-*((RV64IMACFD*)cpu)->CSR[768LL] = val & sstatus_mask(cpu, system, plugin_pointers);
-} // conditional
- else if (csr != 769LL) { // conditional
-*((RV64IMACFD*)cpu)->CSR[csr] = val;
-} // conditional
-} // block
-}
+etiss_int64 etiss_semihost(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers, etiss_uint32 XLEN, etiss_uint64 operation, etiss_uint64 parameter);
 
-static inline etiss_uint64 get_field(etiss_uint64 reg, etiss_uint64 mask)
-{
-{ // block
-return (reg & mask) / (mask & ~((mask << 1ULL)));
-} // block
-}
-
-static inline etiss_uint64 set_field(etiss_uint64 reg, etiss_uint64 mask, etiss_uint64 val)
-{
-{ // block
-return ((reg & ~(mask)) | ((val * (mask & ~((mask << 1ULL)))) & mask));
-} // block
-}
-
-static inline etiss_uint8 ctz(etiss_uint64 val)
-{
-{ // block
-if (!(val)) { // conditional
-return 0ULL;
-} // conditional
-etiss_uint8 res = 0ULL;
-if ((val << 32ULL) == 0ULL) { // conditional
-{ // block
-res = res + 32ULL;
-val = val >> 32ULL;
-} // block
-} // conditional
-if ((val << 48ULL) == 0ULL) { // conditional
-{ // block
-res = res + 16ULL;
-val = val >> 16ULL;
-} // block
-} // conditional
-if ((val << 56ULL) == 0ULL) { // conditional
-{ // block
-res = res + 8ULL;
-val = val >> 8ULL;
-} // block
-} // conditional
-if ((val << 60ULL) == 0ULL) { // conditional
-{ // block
-res = res + 4ULL;
-val = val >> 4ULL;
-} // block
-} // conditional
-if ((val << 62ULL) == 0ULL) { // conditional
-{ // block
-res = res + 2ULL;
-val = val >> 2ULL;
-} // block
-} // conditional
-if ((val << 63ULL) == 0ULL) { // conditional
-{ // block
-res = res + 1ULL;
-val = val >> 1ULL;
-} // block
-} // conditional
-return res;
-} // block
-}
-
-static inline void raise(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers, etiss_int32 irq, etiss_uint64 mcause)
-{
-cpu->return_pending = 1;
-cpu->exception = 0;
-{ // block
-etiss_uint64 epc = cpu->instructionPointer;
-etiss_uint64 deleg = 0ULL;
-etiss_uint64 vector = 0ULL;
-etiss_uint64 bit = mcause;
-etiss_int32 irq2 = (mcause & 9223372036854775808ULL) != 0ULL;
-if (irq2) { // conditional
-{ // block
-deleg = ((((RV64IMACFD*)cpu)->PRIV <= 1LL)) ? (*((RV64IMACFD*)cpu)->CSR[771LL]) : (0ULL);
-bit = bit & 9223372036854775807ULL;
-} // block
-} // conditional
-else { // conditional
-{ // block
-deleg = ((((RV64IMACFD*)cpu)->PRIV <= 1LL)) ? (*((RV64IMACFD*)cpu)->CSR[770LL]) : (0ULL);
-} // block
-} // conditional
-if (((RV64IMACFD*)cpu)->PRIV <= 1LL && (deleg >> bit) & 1ULL) { // conditional
-{ // block
-vector = ((*((RV64IMACFD*)cpu)->CSR[261LL] & 1ULL) && irq2) ? (bit * 4ULL) : (0ULL);
-cpu->nextPc = (*((RV64IMACFD*)cpu)->CSR[261LL] & -2LL) + vector;
-*((RV64IMACFD*)cpu)->CSR[321LL] = epc;
-*((RV64IMACFD*)cpu)->CSR[322LL] = mcause;
-etiss_uint64 s = csr_read(cpu, system, plugin_pointers, 256LL);
-s = set_field(s, 32LL, get_field(s, 2LL));
-s = set_field(s, 256LL, ((RV64IMACFD*)cpu)->PRIV);
-s = set_field(s, 2LL, 0ULL);
-csr_write(cpu, system, plugin_pointers, 256LL, s);
-((RV64IMACFD*)cpu)->PRIV = (1LL) & 0x7;
-} // block
-} // conditional
-else { // conditional
-{ // block
-vector = ((*((RV64IMACFD*)cpu)->CSR[773LL] & 1ULL) && irq2) ? (bit * 4ULL) : (0ULL);
-cpu->nextPc = (*((RV64IMACFD*)cpu)->CSR[773LL] & -2LL) + vector;
-*((RV64IMACFD*)cpu)->CSR[833LL] = epc;
-*((RV64IMACFD*)cpu)->CSR[834LL] = mcause;
-etiss_uint64 s = csr_read(cpu, system, plugin_pointers, 768LL);
-s = set_field(s, 128LL, get_field(s, 8LL));
-s = set_field(s, 6144LL, ((RV64IMACFD*)cpu)->PRIV);
-s = set_field(s, 8LL, 0ULL);
-csr_write(cpu, system, plugin_pointers, 768LL, s);
-((RV64IMACFD*)cpu)->PRIV = (3LL) & 0x7;
-} // block
-} // conditional
-} // block
-}
-
-static inline void translate_exc_code(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers, etiss_int32 cause)
-{
-{ // block
-etiss_uint64 code = 0ULL;
-if (cause == -2147483648LL) { // conditional
-return;
-} // conditional
- else if (cause == -5LL) { // conditional
-code = 5LL;
-} // conditional
- else if (cause == -14LL) { // conditional
-code = 13LL;
-} // conditional
- else if (cause == -6LL) { // conditional
-code = 7LL;
-} // conditional
- else if (cause == -15LL) { // conditional
-code = 15LL;
-} // conditional
- else if (cause == -7LL) { // conditional
-code = 1LL;
-} // conditional
- else if (cause == -9LL) { // conditional
-{ // block
-code = calc_irq_mcause(cpu, system, plugin_pointers);
-if (!(code)) { // conditional
-return;
-} // conditional
-} // block
-} // conditional
-else { // conditional
-code = 2LL;
-} // conditional
-raise(cpu, system, plugin_pointers, 0ULL, code);
-} // block
-}
-
-static inline etiss_uint64 calc_irq_mcause(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers)
-{
-{ // block
-etiss_uint64 pending_interrupts = *((RV64IMACFD*)cpu)->CSR[772LL] & *((RV64IMACFD*)cpu)->CSR[836LL];
-if (!(pending_interrupts)) { // conditional
-return 0ULL;
-} // conditional
-etiss_uint64 mie = get_field(*((RV64IMACFD*)cpu)->CSR[768LL], 8LL);
-etiss_uint64 m_enabled = ((RV64IMACFD*)cpu)->PRIV < 3LL || (((RV64IMACFD*)cpu)->PRIV == 3LL && mie);
-etiss_uint64 enabled_interrupts = pending_interrupts & ~(*((RV64IMACFD*)cpu)->CSR[771LL]) & -(m_enabled);
-if (enabled_interrupts == 0ULL) { // conditional
-{ // block
-etiss_uint64 deleg = *((RV64IMACFD*)cpu)->CSR[771LL];
-etiss_uint64 sie = get_field(csr_read(cpu, system, plugin_pointers, 256LL), 2LL);
-etiss_uint64 s_enabled = ((RV64IMACFD*)cpu)->PRIV < 1LL || (((RV64IMACFD*)cpu)->PRIV == 1LL && sie);
-enabled_interrupts = pending_interrupts & deleg & -(s_enabled);
-} // block
-} // conditional
-if (enabled_interrupts) { // conditional
-{ // block
-if (enabled_interrupts >> 12ULL) { // conditional
-enabled_interrupts = enabled_interrupts >> 12ULL << 12ULL;
-} // conditional
- else if (enabled_interrupts & 2048LL) { // conditional
-enabled_interrupts = 2048LL;
-} // conditional
- else if (enabled_interrupts & 8LL) { // conditional
-enabled_interrupts = 8LL;
-} // conditional
- else if (enabled_interrupts & 128LL) { // conditional
-enabled_interrupts = 128LL;
-} // conditional
- else if (enabled_interrupts & 512LL) { // conditional
-enabled_interrupts = 512LL;
-} // conditional
- else if (enabled_interrupts & 2LL) { // conditional
-enabled_interrupts = 2LL;
-} // conditional
- else if (enabled_interrupts & 32LL) { // conditional
-enabled_interrupts = 32LL;
-} // conditional
- else if (enabled_interrupts & 8192LL) { // conditional
-enabled_interrupts = 8192LL;
-} // conditional
- else if (enabled_interrupts & 1024LL) { // conditional
-enabled_interrupts = 1024LL;
-} // conditional
- else if (enabled_interrupts & 4LL) { // conditional
-enabled_interrupts = 4LL;
-} // conditional
- else if (enabled_interrupts & 64LL) { // conditional
-enabled_interrupts = 64LL;
-} // conditional
-else { // conditional
-return 0ULL;
-} // conditional
-return 9223372036854775808ULL | ctz(enabled_interrupts);
-} // block
-} // conditional
-return 0ULL;
-} // block
+#ifdef __cplusplus
 }
+#endif
 
-static inline void check_irq(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers)
-{
-{ // block
-etiss_uint64 irq_mcause = calc_irq_mcause(cpu, system, plugin_pointers);
-if (irq_mcause) { // conditional
-raise(cpu, system, plugin_pointers, 1ULL, irq_mcause);
-} // conditional
-} // block
-}
 #endif
\ No newline at end of file
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFDGDBCore.h b/ArchImpl/RV64IMACFD/RV64IMACFDGDBCore.h
index 8c02edac5a..f79dde2c44 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFDGDBCore.h
+++ b/ArchImpl/RV64IMACFD/RV64IMACFDGDBCore.h
@@ -1,5 +1,5 @@
 /**
- * Generated on Mon, 02 Oct 2023 18:56:15 +0200.
+ * Generated on Fri, 03 Nov 2023 13:22:23 +0100.
  *
  * This file contains the GDBCore adapter for the RV64IMACFD core architecture.
  *
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFDInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFDInstr.cpp
index b77ca4ea85..8340256cd6 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFDInstr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFDInstr.cpp
@@ -1,13 +1,11 @@
 /**
- * Generated on Mon, 02 Oct 2023 18:56:15 +0200.
+ * Generated on Fri, 03 Nov 2023 13:22:23 +0100.
  *
  * This file contains the instruction behavior models of the default
  * instruction set for the RV64IMACFD core architecture.
  */
 
 #include "RV64IMACFDArch.h"
-
-#define ETISS_ARCH_STATIC_FN_ONLY
 #include "RV64IMACFDFuncs.h"
 
 using namespace etiss;
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_RV32AInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_RV32AInstr.cpp
index da84440926..f57eeab8ee 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD_RV32AInstr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_RV32AInstr.cpp
@@ -1,13 +1,11 @@
 /**
- * Generated on Wed, 04 Oct 2023 17:01:33 +0200.
+ * Generated on Fri, 03 Nov 2023 13:22:23 +0100.
  *
  * This file contains the instruction behavior models of the RV32A
  * instruction set for the RV64IMACFD core architecture.
  */
 
 #include "RV64IMACFDArch.h"
-
-#define ETISS_ARCH_STATIC_FN_ONLY
 #include "RV64IMACFDFuncs.h"
 
 using namespace etiss;
@@ -66,7 +64,7 @@ cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (e
 cp.code() += "if (cpu->exception) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -79,7 +77,7 @@ cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (
 cp.code() += "if (cpu->exception) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -184,7 +182,7 @@ cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (e
 cp.code() += "if (cpu->exception) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -200,7 +198,7 @@ cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (
 cp.code() += "if (cpu->exception) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -305,7 +303,7 @@ cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (e
 cp.code() += "if (cpu->exception) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -321,7 +319,7 @@ cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (
 cp.code() += "if (cpu->exception) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -426,7 +424,7 @@ cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (e
 cp.code() += "if (cpu->exception) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -442,7 +440,7 @@ cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (
 cp.code() += "if (cpu->exception) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -547,7 +545,7 @@ cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (e
 cp.code() += "if (cpu->exception) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -563,7 +561,7 @@ cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (
 cp.code() += "if (cpu->exception) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -668,7 +666,7 @@ cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (e
 cp.code() += "if (cpu->exception) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -684,7 +682,7 @@ cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (
 cp.code() += "if (cpu->exception) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -789,7 +787,7 @@ cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (e
 cp.code() += "if (cpu->exception) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -805,7 +803,7 @@ cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (
 cp.code() += "if (cpu->exception) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -910,7 +908,7 @@ cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (e
 cp.code() += "if (cpu->exception) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -926,7 +924,7 @@ cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (
 cp.code() += "if (cpu->exception) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -1031,7 +1029,7 @@ cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (e
 cp.code() += "if (cpu->exception) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -1047,7 +1045,7 @@ cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (
 cp.code() += "if (cpu->exception) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_RV32DCInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_RV32DCInstr.cpp
index 730817c49a..de251037ca 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD_RV32DCInstr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_RV32DCInstr.cpp
@@ -1,13 +1,11 @@
 /**
- * Generated on Wed, 04 Oct 2023 17:01:33 +0200.
+ * Generated on Fri, 03 Nov 2023 13:22:23 +0100.
  *
  * This file contains the instruction behavior models of the RV32DC
  * instruction set for the RV64IMACFD core architecture.
  */
 
 #include "RV64IMACFDArch.h"
-
-#define ETISS_ARCH_STATIC_FN_ONLY
 #include "RV64IMACFDFuncs.h"
 
 using namespace etiss;
@@ -61,7 +59,7 @@ cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (e
 cp.code() += "if (cpu->exception) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -161,7 +159,7 @@ cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (
 cp.code() += "if (cpu->exception) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -257,7 +255,7 @@ cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (e
 cp.code() += "if (cpu->exception) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -353,7 +351,7 @@ cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (
 cp.code() += "if (cpu->exception) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_RV32DInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_RV32DInstr.cpp
index 060dbc736a..e06dbae1e5 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD_RV32DInstr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_RV32DInstr.cpp
@@ -1,13 +1,11 @@
 /**
- * Generated on Wed, 04 Oct 2023 17:01:33 +0200.
+ * Generated on Fri, 03 Nov 2023 13:22:23 +0100.
  *
  * This file contains the instruction behavior models of the RV32D
  * instruction set for the RV64IMACFD core architecture.
  */
 
 #include "RV64IMACFDArch.h"
-
-#define ETISS_ARCH_STATIC_FN_ONLY
 #include "RV64IMACFDFuncs.h"
 
 using namespace etiss;
@@ -59,7 +57,7 @@ cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (e
 cp.code() += "if (cpu->exception) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -157,7 +155,7 @@ cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (
 cp.code() += "if (cpu->exception) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -252,7 +250,7 @@ cp.code() += "} // block\n";
 } // block
 { // block
 cp.code() += "{ // block\n";
-cp.code() += "etiss_uint64 res = fmadd_d((etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]), (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs3) + "ULL]), 0ULL, get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
+cp.code() += "etiss_uint64 res = fmadd_d((etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]), (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs3) + "ULL]), 0ULL, RV64IMACFD_get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
 cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = res;\n";
 cp.code() += "etiss_uint32 flags = fget_flags();\n";
 cp.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";
@@ -341,7 +339,7 @@ cp.code() += "} // block\n";
 } // block
 { // block
 cp.code() += "{ // block\n";
-cp.code() += "etiss_uint64 res = fmadd_d((etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]), (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs3) + "ULL]), 1ULL, get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
+cp.code() += "etiss_uint64 res = fmadd_d((etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]), (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs3) + "ULL]), 1ULL, RV64IMACFD_get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
 cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = res;\n";
 cp.code() += "etiss_uint32 flags = fget_flags();\n";
 cp.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";
@@ -430,7 +428,7 @@ cp.code() += "} // block\n";
 } // block
 { // block
 cp.code() += "{ // block\n";
-cp.code() += "etiss_uint64 res = fmadd_d((etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]), (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs3) + "ULL]), 2ULL, get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
+cp.code() += "etiss_uint64 res = fmadd_d((etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]), (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs3) + "ULL]), 2ULL, RV64IMACFD_get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
 cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = res;\n";
 cp.code() += "etiss_uint32 flags = fget_flags();\n";
 cp.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";
@@ -519,7 +517,7 @@ cp.code() += "} // block\n";
 } // block
 { // block
 cp.code() += "{ // block\n";
-cp.code() += "etiss_uint64 res = fmadd_d((etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]), (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs3) + "ULL]), 3ULL, get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
+cp.code() += "etiss_uint64 res = fmadd_d((etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]), (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs3) + "ULL]), 3ULL, RV64IMACFD_get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
 cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = res;\n";
 cp.code() += "etiss_uint32 flags = fget_flags();\n";
 cp.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";
@@ -605,7 +603,7 @@ cp.code() += "} // block\n";
 } // block
 { // block
 cp.code() += "{ // block\n";
-cp.code() += "etiss_uint64 res = fadd_d((etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]), get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
+cp.code() += "etiss_uint64 res = fadd_d((etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]), RV64IMACFD_get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
 cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = res;\n";
 cp.code() += "etiss_uint32 flags = fget_flags();\n";
 cp.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";
@@ -688,7 +686,7 @@ cp.code() += "} // block\n";
 } // block
 { // block
 cp.code() += "{ // block\n";
-cp.code() += "etiss_uint64 res = fsub_d((etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]), get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
+cp.code() += "etiss_uint64 res = fsub_d((etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]), RV64IMACFD_get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
 cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = res;\n";
 cp.code() += "etiss_uint32 flags = fget_flags();\n";
 cp.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";
@@ -771,7 +769,7 @@ cp.code() += "} // block\n";
 } // block
 { // block
 cp.code() += "{ // block\n";
-cp.code() += "etiss_uint64 res = fmul_d((etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]), get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
+cp.code() += "etiss_uint64 res = fmul_d((etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]), RV64IMACFD_get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
 cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = res;\n";
 cp.code() += "etiss_uint32 flags = fget_flags();\n";
 cp.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";
@@ -854,7 +852,7 @@ cp.code() += "} // block\n";
 } // block
 { // block
 cp.code() += "{ // block\n";
-cp.code() += "etiss_uint64 res = fdiv_d((etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]), get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
+cp.code() += "etiss_uint64 res = fdiv_d((etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]), RV64IMACFD_get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
 cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = res;\n";
 cp.code() += "etiss_uint32 flags = fget_flags();\n";
 cp.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";
@@ -934,7 +932,7 @@ cp.code() += "} // block\n";
 } // block
 { // block
 cp.code() += "{ // block\n";
-cp.code() += "etiss_uint64 res = fsqrt_d((etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
+cp.code() += "etiss_uint64 res = fsqrt_d((etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), RV64IMACFD_get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
 cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = res;\n";
 cp.code() += "etiss_uint32 flags = fget_flags();\n";
 cp.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_RV32FInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_RV32FInstr.cpp
index 7e677499c6..b6bbefeb4e 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD_RV32FInstr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_RV32FInstr.cpp
@@ -1,13 +1,11 @@
 /**
- * Generated on Wed, 04 Oct 2023 17:01:33 +0200.
+ * Generated on Fri, 03 Nov 2023 13:22:23 +0100.
  *
  * This file contains the instruction behavior models of the RV32F
  * instruction set for the RV64IMACFD core architecture.
  */
 
 #include "RV64IMACFDArch.h"
-
-#define ETISS_ARCH_STATIC_FN_ONLY
 #include "RV64IMACFDFuncs.h"
 
 using namespace etiss;
@@ -59,7 +57,7 @@ cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (e
 cp.code() += "if (cpu->exception) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -161,7 +159,7 @@ cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (
 cp.code() += "if (cpu->exception) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -258,7 +256,7 @@ cp.code() += "} // block\n";
 cp.code() += "{ // block\n";
 { // block
 cp.code() += "{ // block\n";
-cp.code() += "etiss_uint32 res = fmadd_s(unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]), unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs3) + "ULL]), 0ULL, get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
+cp.code() += "etiss_uint32 res = fmadd_s(unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]), unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs3) + "ULL]), 0ULL, RV64IMACFD_get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
 cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = -4294967296LL | (etiss_uint64)(res);\n";
 cp.code() += "} // block\n";
 } // block
@@ -351,7 +349,7 @@ cp.code() += "} // block\n";
 cp.code() += "{ // block\n";
 { // block
 cp.code() += "{ // block\n";
-cp.code() += "etiss_uint32 res = fmadd_s(unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]), unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs3) + "ULL]), 1ULL, get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
+cp.code() += "etiss_uint32 res = fmadd_s(unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]), unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs3) + "ULL]), 1ULL, RV64IMACFD_get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
 cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = -4294967296LL | (etiss_uint64)(res);\n";
 cp.code() += "} // block\n";
 } // block
@@ -447,7 +445,7 @@ cp.code() += "{ // block\n";
 cp.code() += "etiss_uint32 frs1 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]);\n";
 cp.code() += "etiss_uint32 frs2 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]);\n";
 cp.code() += "etiss_uint32 frs3 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs3) + "ULL]);\n";
-cp.code() += "etiss_uint32 res = fmadd_s(frs1, frs2, frs3, 2ULL, get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
+cp.code() += "etiss_uint32 res = fmadd_s(frs1, frs2, frs3, 2ULL, RV64IMACFD_get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
 cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = -4294967296LL | (etiss_uint64)(res);\n";
 cp.code() += "} // block\n";
 } // block
@@ -543,7 +541,7 @@ cp.code() += "{ // block\n";
 cp.code() += "etiss_uint32 frs1 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]);\n";
 cp.code() += "etiss_uint32 frs2 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]);\n";
 cp.code() += "etiss_uint32 frs3 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs3) + "ULL]);\n";
-cp.code() += "etiss_uint32 res = fmadd_s(frs1, frs2, frs3, 3ULL, get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
+cp.code() += "etiss_uint32 res = fmadd_s(frs1, frs2, frs3, 3ULL, RV64IMACFD_get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
 cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = -4294967296LL | (etiss_uint64)(res);\n";
 cp.code() += "} // block\n";
 } // block
@@ -635,7 +633,7 @@ cp.code() += "{ // block\n";
 cp.code() += "{ // block\n";
 cp.code() += "etiss_uint32 frs1 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]);\n";
 cp.code() += "etiss_uint32 frs2 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]);\n";
-cp.code() += "etiss_uint32 res = fadd_s(frs1, frs2, get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
+cp.code() += "etiss_uint32 res = fadd_s(frs1, frs2, RV64IMACFD_get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
 cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = -4294967296LL | (etiss_uint64)(res);\n";
 cp.code() += "} // block\n";
 } // block
@@ -724,7 +722,7 @@ cp.code() += "{ // block\n";
 cp.code() += "{ // block\n";
 cp.code() += "etiss_uint32 frs1 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]);\n";
 cp.code() += "etiss_uint32 frs2 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]);\n";
-cp.code() += "etiss_uint32 res = fsub_s(frs1, frs2, get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
+cp.code() += "etiss_uint32 res = fsub_s(frs1, frs2, RV64IMACFD_get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
 cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = -4294967296LL | (etiss_uint64)(res);\n";
 cp.code() += "} // block\n";
 } // block
@@ -813,7 +811,7 @@ cp.code() += "{ // block\n";
 cp.code() += "{ // block\n";
 cp.code() += "etiss_uint32 frs1 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]);\n";
 cp.code() += "etiss_uint32 frs2 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]);\n";
-cp.code() += "etiss_uint32 res = fmul_s(frs1, frs2, get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
+cp.code() += "etiss_uint32 res = fmul_s(frs1, frs2, RV64IMACFD_get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
 cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = -4294967296LL | (etiss_uint64)(res);\n";
 cp.code() += "} // block\n";
 } // block
@@ -902,7 +900,7 @@ cp.code() += "{ // block\n";
 cp.code() += "{ // block\n";
 cp.code() += "etiss_uint32 frs1 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]);\n";
 cp.code() += "etiss_uint32 frs2 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]);\n";
-cp.code() += "etiss_uint32 res = fdiv_s(frs1, frs2, get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
+cp.code() += "etiss_uint32 res = fdiv_s(frs1, frs2, RV64IMACFD_get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
 cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = -4294967296LL | (etiss_uint64)(res);\n";
 cp.code() += "} // block\n";
 } // block
@@ -987,7 +985,7 @@ cp.code() += "{ // block\n";
 { // block
 cp.code() += "{ // block\n";
 cp.code() += "etiss_uint32 frs1 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]);\n";
-cp.code() += "etiss_uint32 res = fsqrt_s(frs1, get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
+cp.code() += "etiss_uint32 res = fsqrt_s(frs1, RV64IMACFD_get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
 cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = -4294967296LL | (etiss_uint64)(res);\n";
 cp.code() += "} // block\n";
 } // block
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_RV32ICInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_RV32ICInstr.cpp
index 793a1824a8..f0994449c2 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD_RV32ICInstr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_RV32ICInstr.cpp
@@ -1,13 +1,11 @@
 /**
- * Generated on Wed, 04 Oct 2023 17:01:33 +0200.
+ * Generated on Fri, 03 Nov 2023 13:22:23 +0100.
  *
  * This file contains the instruction behavior models of the RV32IC
  * instruction set for the RV64IMACFD core architecture.
  */
 
 #include "RV64IMACFDArch.h"
-
-#define ETISS_ARCH_STATIC_FN_ONLY
 #include "RV64IMACFDFuncs.h"
 
 using namespace etiss;
@@ -60,7 +58,7 @@ cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd + 8ULL) + "ULL] = *((
 else { // conditional
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "raise(cpu, system, plugin_pointers, 0ULL, 2ULL);\n";
+cp.code() += "RV64IMACFD_raise(cpu, system, plugin_pointers, 0ULL, 2ULL);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -158,7 +156,7 @@ cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, load_add
 cp.code() += "if (cpu->exception) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -261,7 +259,7 @@ cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, load_ad
 cp.code() += "if (cpu->exception) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -563,7 +561,7 @@ cp.code() += "{ // block\n";
 if (imm == 0ULL) { // conditional
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "raise(cpu, system, plugin_pointers, 0ULL, 2ULL);\n";
+cp.code() += "RV64IMACFD_raise(cpu, system, plugin_pointers, 0ULL, 2ULL);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -658,7 +656,7 @@ cp.code() += "*((RV64IMACFD*)cpu)->X[2ULL] = *((RV64IMACFD*)cpu)->X[2ULL] + " +
 else { // conditional
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "raise(cpu, system, plugin_pointers, 0ULL, 2ULL);\n";
+cp.code() += "RV64IMACFD_raise(cpu, system, plugin_pointers, 0ULL, 2ULL);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -739,7 +737,7 @@ cp.code() += "} // block\n";
 } // block
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "raise(cpu, system, plugin_pointers, 0ULL, 2ULL);\n";
+cp.code() += "RV64IMACFD_raise(cpu, system, plugin_pointers, 0ULL, 2ULL);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -1655,7 +1653,7 @@ cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, *((RV64I
 cp.code() += "if (cpu->exception) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -1668,7 +1666,7 @@ cp.code() += "} // block\n";
 else { // conditional
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "raise(cpu, system, plugin_pointers, 0ULL, 2ULL);\n";
+cp.code() += "RV64IMACFD_raise(cpu, system, plugin_pointers, 0ULL, 2ULL);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -1820,7 +1818,7 @@ cp.code() += "cpu->nextPc = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32UL
 else { // conditional
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "raise(cpu, system, plugin_pointers, 0ULL, 2ULL);\n";
+cp.code() += "RV64IMACFD_raise(cpu, system, plugin_pointers, 0ULL, 2ULL);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -1890,7 +1888,7 @@ cp.code() += "} // block\n";
 } // block
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "raise(cpu, system, plugin_pointers, 0ULL, 2ULL);\n";
+cp.code() += "RV64IMACFD_raise(cpu, system, plugin_pointers, 0ULL, 2ULL);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -2095,7 +2093,7 @@ cp.code() += "} // block\n";
 } // block
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "raise(cpu, system, plugin_pointers, 0ULL, 3ULL);\n";
+cp.code() += "RV64IMACFD_raise(cpu, system, plugin_pointers, 0ULL, 3ULL);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -2176,7 +2174,7 @@ cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (
 cp.code() += "if (cpu->exception) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -2253,7 +2251,7 @@ cp.code() += "} // block\n";
 } // block
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "raise(cpu, system, plugin_pointers, 0ULL, 2ULL);\n";
+cp.code() += "RV64IMACFD_raise(cpu, system, plugin_pointers, 0ULL, 2ULL);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_RV32IInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_RV32IInstr.cpp
index 896c5c5410..d1bbd833c5 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD_RV32IInstr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_RV32IInstr.cpp
@@ -1,13 +1,11 @@
 /**
- * Generated on Wed, 04 Oct 2023 17:01:33 +0200.
+ * Generated on Fri, 03 Nov 2023 13:22:23 +0100.
  *
  * This file contains the instruction behavior models of the RV32I
  * instruction set for the RV64IMACFD core architecture.
  */
 
 #include "RV64IMACFDArch.h"
-
-#define ETISS_ARCH_STATIC_FN_ONLY
 #include "RV64IMACFDFuncs.h"
 
 using namespace etiss;
@@ -193,7 +191,7 @@ if (imm % 2ULL) { // conditional
 cp.code() += "{ // block\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "raise(cpu, system, plugin_pointers, 0ULL, 0ULL);\n";
+cp.code() += "RV64IMACFD_raise(cpu, system, plugin_pointers, 0ULL, 0ULL);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -301,7 +299,7 @@ cp.code() += "if (new_pc % 2ULL) { // conditional\n";
 cp.code() += "{ // block\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "raise(cpu, system, plugin_pointers, 0ULL, 0ULL);\n";
+cp.code() += "RV64IMACFD_raise(cpu, system, plugin_pointers, 0ULL, 0ULL);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -414,7 +412,7 @@ if (imm % 2ULL) { // conditional
 cp.code() += "{ // block\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "raise(cpu, system, plugin_pointers, 0ULL, 0ULL);\n";
+cp.code() += "RV64IMACFD_raise(cpu, system, plugin_pointers, 0ULL, 0ULL);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -533,7 +531,7 @@ if (imm % 2ULL) { // conditional
 cp.code() += "{ // block\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "raise(cpu, system, plugin_pointers, 0ULL, 0ULL);\n";
+cp.code() += "RV64IMACFD_raise(cpu, system, plugin_pointers, 0ULL, 0ULL);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -652,7 +650,7 @@ if (imm % 2ULL) { // conditional
 cp.code() += "{ // block\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "raise(cpu, system, plugin_pointers, 0ULL, 0ULL);\n";
+cp.code() += "RV64IMACFD_raise(cpu, system, plugin_pointers, 0ULL, 0ULL);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -771,7 +769,7 @@ if (imm % 2ULL) { // conditional
 cp.code() += "{ // block\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "raise(cpu, system, plugin_pointers, 0ULL, 0ULL);\n";
+cp.code() += "RV64IMACFD_raise(cpu, system, plugin_pointers, 0ULL, 0ULL);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -890,7 +888,7 @@ if (imm % 2ULL) { // conditional
 cp.code() += "{ // block\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "raise(cpu, system, plugin_pointers, 0ULL, 0ULL);\n";
+cp.code() += "RV64IMACFD_raise(cpu, system, plugin_pointers, 0ULL, 0ULL);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -1009,7 +1007,7 @@ if (imm % 2ULL) { // conditional
 cp.code() += "{ // block\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "raise(cpu, system, plugin_pointers, 0ULL, 0ULL);\n";
+cp.code() += "RV64IMACFD_raise(cpu, system, plugin_pointers, 0ULL, 0ULL);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -1120,7 +1118,7 @@ cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, load_add
 cp.code() += "if (cpu->exception) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -1217,7 +1215,7 @@ cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, load_add
 cp.code() += "if (cpu->exception) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -1314,7 +1312,7 @@ cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, load_add
 cp.code() += "if (cpu->exception) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -1411,7 +1409,7 @@ cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, load_add
 cp.code() += "if (cpu->exception) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -1508,7 +1506,7 @@ cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, load_add
 cp.code() += "if (cpu->exception) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -1608,7 +1606,7 @@ cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, store_a
 cp.code() += "if (cpu->exception) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -1706,7 +1704,7 @@ cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, store_a
 cp.code() += "if (cpu->exception) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -1804,7 +1802,7 @@ cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, store_a
 cp.code() += "if (cpu->exception) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_RV32MInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_RV32MInstr.cpp
index 79f04bfe79..cae51b79ef 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD_RV32MInstr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_RV32MInstr.cpp
@@ -1,343 +1,17 @@
 /**
- * Generated on Wed, 04 Oct 2023 17:01:33 +0200.
+ * Generated on Fri, 03 Nov 2023 13:22:23 +0100.
  *
  * This file contains the instruction behavior models of the RV32M
  * instruction set for the RV64IMACFD core architecture.
  */
 
 #include "RV64IMACFDArch.h"
-
-#define ETISS_ARCH_STATIC_FN_ONLY
 #include "RV64IMACFDFuncs.h"
 
 using namespace etiss;
 using namespace etiss::instr;
 
 
-// MUL -------------------------------------------------------------------------
-static InstructionDefinition mul_rd_rs1_rs2 (
-	ISA32_RV64IMACFD,
-	"mul",
-	(uint32_t) 0x2000033,
-	(uint32_t) 0xfe00707f,
-	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
-	{
-
-// -----------------------------------------------------------------------------
-
-// -----------------------------------------------------------------------------
-
-// -----------------------------------------------------------------------------
-etiss_uint8 rd = 0;
-static BitArrayRange R_rd_0(11, 7);
-rd += R_rd_0.read(ba) << 0;
-etiss_uint8 rs1 = 0;
-static BitArrayRange R_rs1_0(19, 15);
-rs1 += R_rs1_0.read(ba) << 0;
-etiss_uint8 rs2 = 0;
-static BitArrayRange R_rs2_0(24, 20);
-rs2 += R_rs2_0.read(ba) << 0;
-
-// -----------------------------------------------------------------------------
-
-	{
-		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
-
-		cp.code() = std::string("//MUL\n");
-
-// -----------------------------------------------------------------------------
-{ // block
-cp.code() += "{ // block\n";
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
-cp.code() += "} // block\n";
-} // block
-{ // block
-cp.code() += "{ // block\n";
-if ((rd % 32ULL) != 0ULL) { // conditional
-{ // block
-cp.code() += "{ // block\n";
-cp.code() += "etiss_int128 res = (etiss_int128)((etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL])) * (etiss_int128)((etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]));\n";
-cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_uint64)(res);\n";
-cp.code() += "} // block\n";
-} // block
-} // conditional
-cp.code() += "} // block\n";
-} // block
-cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-// -----------------------------------------------------------------------------
-		cp.getAffectedRegisters().add("instructionPointer", 32);
-	}
-
-		return true;
-	},
-	0,
-	[] (BitArray & ba, Instruction & instr)
-	{
-// -----------------------------------------------------------------------------
-etiss_uint8 rd = 0;
-static BitArrayRange R_rd_0(11, 7);
-rd += R_rd_0.read(ba) << 0;
-etiss_uint8 rs1 = 0;
-static BitArrayRange R_rs1_0(19, 15);
-rs1 += R_rs1_0.read(ba) << 0;
-etiss_uint8 rs2 = 0;
-static BitArrayRange R_rs2_0(24, 20);
-rs2 += R_rs2_0.read(ba) << 0;
-
-// -----------------------------------------------------------------------------
-
-		std::stringstream ss;
-// -----------------------------------------------------------------------------
-ss << "mul" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
-// -----------------------------------------------------------------------------
-		return ss.str();
-	}
-);
-
-// MULH ------------------------------------------------------------------------
-static InstructionDefinition mulh_rd_rs1_rs2 (
-	ISA32_RV64IMACFD,
-	"mulh",
-	(uint32_t) 0x2001033,
-	(uint32_t) 0xfe00707f,
-	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
-	{
-
-// -----------------------------------------------------------------------------
-
-// -----------------------------------------------------------------------------
-
-// -----------------------------------------------------------------------------
-etiss_uint8 rd = 0;
-static BitArrayRange R_rd_0(11, 7);
-rd += R_rd_0.read(ba) << 0;
-etiss_uint8 rs1 = 0;
-static BitArrayRange R_rs1_0(19, 15);
-rs1 += R_rs1_0.read(ba) << 0;
-etiss_uint8 rs2 = 0;
-static BitArrayRange R_rs2_0(24, 20);
-rs2 += R_rs2_0.read(ba) << 0;
-
-// -----------------------------------------------------------------------------
-
-	{
-		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
-
-		cp.code() = std::string("//MULH\n");
-
-// -----------------------------------------------------------------------------
-{ // block
-cp.code() += "{ // block\n";
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
-cp.code() += "} // block\n";
-} // block
-{ // block
-cp.code() += "{ // block\n";
-if ((rd % 32ULL) != 0ULL) { // conditional
-{ // block
-cp.code() += "{ // block\n";
-cp.code() += "etiss_int128 res = (etiss_int128)((etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL])) * (etiss_int128)((etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]));\n";
-cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_uint64)((res >> 64ULL));\n";
-cp.code() += "} // block\n";
-} // block
-} // conditional
-cp.code() += "} // block\n";
-} // block
-cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-// -----------------------------------------------------------------------------
-		cp.getAffectedRegisters().add("instructionPointer", 32);
-	}
-
-		return true;
-	},
-	0,
-	[] (BitArray & ba, Instruction & instr)
-	{
-// -----------------------------------------------------------------------------
-etiss_uint8 rd = 0;
-static BitArrayRange R_rd_0(11, 7);
-rd += R_rd_0.read(ba) << 0;
-etiss_uint8 rs1 = 0;
-static BitArrayRange R_rs1_0(19, 15);
-rs1 += R_rs1_0.read(ba) << 0;
-etiss_uint8 rs2 = 0;
-static BitArrayRange R_rs2_0(24, 20);
-rs2 += R_rs2_0.read(ba) << 0;
-
-// -----------------------------------------------------------------------------
-
-		std::stringstream ss;
-// -----------------------------------------------------------------------------
-ss << "mulh" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
-// -----------------------------------------------------------------------------
-		return ss.str();
-	}
-);
-
-// MULHSU ----------------------------------------------------------------------
-static InstructionDefinition mulhsu_rd_rs1_rs2 (
-	ISA32_RV64IMACFD,
-	"mulhsu",
-	(uint32_t) 0x2002033,
-	(uint32_t) 0xfe00707f,
-	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
-	{
-
-// -----------------------------------------------------------------------------
-
-// -----------------------------------------------------------------------------
-
-// -----------------------------------------------------------------------------
-etiss_uint8 rd = 0;
-static BitArrayRange R_rd_0(11, 7);
-rd += R_rd_0.read(ba) << 0;
-etiss_uint8 rs1 = 0;
-static BitArrayRange R_rs1_0(19, 15);
-rs1 += R_rs1_0.read(ba) << 0;
-etiss_uint8 rs2 = 0;
-static BitArrayRange R_rs2_0(24, 20);
-rs2 += R_rs2_0.read(ba) << 0;
-
-// -----------------------------------------------------------------------------
-
-	{
-		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
-
-		cp.code() = std::string("//MULHSU\n");
-
-// -----------------------------------------------------------------------------
-{ // block
-cp.code() += "{ // block\n";
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
-cp.code() += "} // block\n";
-} // block
-{ // block
-cp.code() += "{ // block\n";
-if ((rd % 32ULL) != 0ULL) { // conditional
-{ // block
-cp.code() += "{ // block\n";
-cp.code() += "etiss_int128 res = (etiss_int128)((etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL])) * (etiss_uint128)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]);\n";
-cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_uint64)((res >> 64ULL));\n";
-cp.code() += "} // block\n";
-} // block
-} // conditional
-cp.code() += "} // block\n";
-} // block
-cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-// -----------------------------------------------------------------------------
-		cp.getAffectedRegisters().add("instructionPointer", 32);
-	}
-
-		return true;
-	},
-	0,
-	[] (BitArray & ba, Instruction & instr)
-	{
-// -----------------------------------------------------------------------------
-etiss_uint8 rd = 0;
-static BitArrayRange R_rd_0(11, 7);
-rd += R_rd_0.read(ba) << 0;
-etiss_uint8 rs1 = 0;
-static BitArrayRange R_rs1_0(19, 15);
-rs1 += R_rs1_0.read(ba) << 0;
-etiss_uint8 rs2 = 0;
-static BitArrayRange R_rs2_0(24, 20);
-rs2 += R_rs2_0.read(ba) << 0;
-
-// -----------------------------------------------------------------------------
-
-		std::stringstream ss;
-// -----------------------------------------------------------------------------
-ss << "mulhsu" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
-// -----------------------------------------------------------------------------
-		return ss.str();
-	}
-);
-
-// MULHU -----------------------------------------------------------------------
-static InstructionDefinition mulhu_rd_rs1_rs2 (
-	ISA32_RV64IMACFD,
-	"mulhu",
-	(uint32_t) 0x2003033,
-	(uint32_t) 0xfe00707f,
-	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
-	{
-
-// -----------------------------------------------------------------------------
-
-// -----------------------------------------------------------------------------
-
-// -----------------------------------------------------------------------------
-etiss_uint8 rd = 0;
-static BitArrayRange R_rd_0(11, 7);
-rd += R_rd_0.read(ba) << 0;
-etiss_uint8 rs1 = 0;
-static BitArrayRange R_rs1_0(19, 15);
-rs1 += R_rs1_0.read(ba) << 0;
-etiss_uint8 rs2 = 0;
-static BitArrayRange R_rs2_0(24, 20);
-rs2 += R_rs2_0.read(ba) << 0;
-
-// -----------------------------------------------------------------------------
-
-	{
-		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
-
-		cp.code() = std::string("//MULHU\n");
-
-// -----------------------------------------------------------------------------
-{ // block
-cp.code() += "{ // block\n";
-cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
-cp.code() += "} // block\n";
-} // block
-{ // block
-cp.code() += "{ // block\n";
-if ((rd % 32ULL) != 0ULL) { // conditional
-{ // block
-cp.code() += "{ // block\n";
-cp.code() += "etiss_uint128 res = (etiss_uint128)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL]) * (etiss_uint128)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]);\n";
-cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_uint64)((res >> 64ULL));\n";
-cp.code() += "} // block\n";
-} // block
-} // conditional
-cp.code() += "} // block\n";
-} // block
-cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
-cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
-// -----------------------------------------------------------------------------
-		cp.getAffectedRegisters().add("instructionPointer", 32);
-	}
-
-		return true;
-	},
-	0,
-	[] (BitArray & ba, Instruction & instr)
-	{
-// -----------------------------------------------------------------------------
-etiss_uint8 rd = 0;
-static BitArrayRange R_rd_0(11, 7);
-rd += R_rd_0.read(ba) << 0;
-etiss_uint8 rs1 = 0;
-static BitArrayRange R_rs1_0(19, 15);
-rs1 += R_rs1_0.read(ba) << 0;
-etiss_uint8 rs2 = 0;
-static BitArrayRange R_rs2_0(24, 20);
-rs2 += R_rs2_0.read(ba) << 0;
-
-// -----------------------------------------------------------------------------
-
-		std::stringstream ss;
-// -----------------------------------------------------------------------------
-ss << "mulhu" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
-// -----------------------------------------------------------------------------
-		return ss.str();
-	}
-);
-
 // DIV -------------------------------------------------------------------------
 static InstructionDefinition div_rd_rs1_rs2 (
 	ISA32_RV64IMACFD,
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_RV64AInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_RV64AInstr.cpp
index 1b8c32f1a0..85c896f448 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD_RV64AInstr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_RV64AInstr.cpp
@@ -1,13 +1,11 @@
 /**
- * Generated on Wed, 04 Oct 2023 17:01:33 +0200.
+ * Generated on Fri, 03 Nov 2023 13:22:23 +0100.
  *
  * This file contains the instruction behavior models of the RV64A
  * instruction set for the RV64IMACFD core architecture.
  */
 
 #include "RV64IMACFDArch.h"
-
-#define ETISS_ARCH_STATIC_FN_ONLY
 #include "RV64IMACFDFuncs.h"
 
 using namespace etiss;
@@ -66,7 +64,7 @@ cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (e
 cp.code() += "if (cpu->exception) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -79,7 +77,7 @@ cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (
 cp.code() += "if (cpu->exception) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -184,7 +182,7 @@ cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (e
 cp.code() += "if (cpu->exception) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -200,7 +198,7 @@ cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (
 cp.code() += "if (cpu->exception) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -305,7 +303,7 @@ cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (e
 cp.code() += "if (cpu->exception) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -321,7 +319,7 @@ cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (
 cp.code() += "if (cpu->exception) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -426,7 +424,7 @@ cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (e
 cp.code() += "if (cpu->exception) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -442,7 +440,7 @@ cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (
 cp.code() += "if (cpu->exception) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -547,7 +545,7 @@ cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (e
 cp.code() += "if (cpu->exception) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -563,7 +561,7 @@ cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (
 cp.code() += "if (cpu->exception) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -668,7 +666,7 @@ cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (e
 cp.code() += "if (cpu->exception) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -684,7 +682,7 @@ cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (
 cp.code() += "if (cpu->exception) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -789,7 +787,7 @@ cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (e
 cp.code() += "if (cpu->exception) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -805,7 +803,7 @@ cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (
 cp.code() += "if (cpu->exception) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -910,7 +908,7 @@ cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (e
 cp.code() += "if (cpu->exception) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -926,7 +924,7 @@ cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (
 cp.code() += "if (cpu->exception) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -1031,7 +1029,7 @@ cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (e
 cp.code() += "if (cpu->exception) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -1047,7 +1045,7 @@ cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (
 cp.code() += "if (cpu->exception) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_RV64DInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_RV64DInstr.cpp
index 670c5e31c0..b27658a401 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD_RV64DInstr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_RV64DInstr.cpp
@@ -1,13 +1,11 @@
 /**
- * Generated on Wed, 04 Oct 2023 17:01:33 +0200.
+ * Generated on Fri, 03 Nov 2023 13:22:23 +0100.
  *
  * This file contains the instruction behavior models of the RV64D
  * instruction set for the RV64IMACFD core architecture.
  */
 
 #include "RV64IMACFDArch.h"
-
-#define ETISS_ARCH_STATIC_FN_ONLY
 #include "RV64IMACFDFuncs.h"
 
 using namespace etiss;
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_RV64FInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_RV64FInstr.cpp
index fb8dabf30a..cc9507bb95 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD_RV64FInstr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_RV64FInstr.cpp
@@ -1,13 +1,11 @@
 /**
- * Generated on Wed, 04 Oct 2023 17:01:33 +0200.
+ * Generated on Fri, 03 Nov 2023 13:22:23 +0100.
  *
  * This file contains the instruction behavior models of the RV64F
  * instruction set for the RV64IMACFD core architecture.
  */
 
 #include "RV64IMACFDArch.h"
-
-#define ETISS_ARCH_STATIC_FN_ONLY
 #include "RV64IMACFDFuncs.h"
 
 using namespace etiss;
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_RV64ICInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_RV64ICInstr.cpp
index fe07364274..86711c098e 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD_RV64ICInstr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_RV64ICInstr.cpp
@@ -1,13 +1,11 @@
 /**
- * Generated on Wed, 04 Oct 2023 17:01:33 +0200.
+ * Generated on Fri, 03 Nov 2023 13:22:23 +0100.
  *
  * This file contains the instruction behavior models of the RV64IC
  * instruction set for the RV64IMACFD core architecture.
  */
 
 #include "RV64IMACFDArch.h"
-
-#define ETISS_ARCH_STATIC_FN_ONLY
 #include "RV64IMACFDFuncs.h"
 
 using namespace etiss;
@@ -269,7 +267,7 @@ cp.code() += "{ // block\n";
 if (rs1 == 0ULL) { // conditional
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "raise(cpu, system, plugin_pointers, 0ULL, 2ULL);\n";
+cp.code() += "RV64IMACFD_raise(cpu, system, plugin_pointers, 0ULL, 2ULL);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -364,7 +362,7 @@ cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (e
 cp.code() += "if (cpu->exception) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -463,7 +461,7 @@ cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (
 cp.code() += "if (cpu->exception) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -697,7 +695,7 @@ cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (e
 cp.code() += "if (cpu->exception) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -709,7 +707,7 @@ cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = re
 else { // conditional
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "raise(cpu, system, plugin_pointers, 0ULL, 2ULL);\n";
+cp.code() += "RV64IMACFD_raise(cpu, system, plugin_pointers, 0ULL, 2ULL);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -803,7 +801,7 @@ cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (
 cp.code() += "if (cpu->exception) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_RV64IInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_RV64IInstr.cpp
index 8b2f4f27b3..90b1f0d9e6 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD_RV64IInstr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_RV64IInstr.cpp
@@ -1,13 +1,11 @@
 /**
- * Generated on Wed, 04 Oct 2023 17:01:33 +0200.
+ * Generated on Fri, 03 Nov 2023 13:22:23 +0100.
  *
  * This file contains the instruction behavior models of the RV64I
  * instruction set for the RV64IMACFD core architecture.
  */
 
 #include "RV64IMACFDArch.h"
-
-#define ETISS_ARCH_STATIC_FN_ONLY
 #include "RV64IMACFDFuncs.h"
 
 using namespace etiss;
@@ -59,7 +57,7 @@ cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (e
 cp.code() += "if (cpu->exception) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -156,7 +154,7 @@ cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (e
 cp.code() += "if (cpu->exception) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -256,7 +254,7 @@ cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (
 cp.code() += "if (cpu->exception) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_RV64MInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_RV64MInstr.cpp
index 5219edcc02..8c4709b017 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD_RV64MInstr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_RV64MInstr.cpp
@@ -1,13 +1,11 @@
 /**
- * Generated on Wed, 04 Oct 2023 17:01:33 +0200.
+ * Generated on Fri, 03 Nov 2023 13:22:23 +0100.
  *
  * This file contains the instruction behavior models of the RV64M
  * instruction set for the RV64IMACFD core architecture.
  */
 
 #include "RV64IMACFDArch.h"
-
-#define ETISS_ARCH_STATIC_FN_ONLY
 #include "RV64IMACFDFuncs.h"
 
 using namespace etiss;
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_ZifenceiInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_ZifenceiInstr.cpp
index fdfc3c104f..1b0a8ad3bb 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD_ZifenceiInstr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_ZifenceiInstr.cpp
@@ -1,13 +1,11 @@
 /**
- * Generated on Wed, 04 Oct 2023 17:01:33 +0200.
+ * Generated on Fri, 03 Nov 2023 13:22:23 +0100.
  *
  * This file contains the instruction behavior models of the Zifencei
  * instruction set for the RV64IMACFD core architecture.
  */
 
 #include "RV64IMACFDArch.h"
-
-#define ETISS_ARCH_STATIC_FN_ONLY
 #include "RV64IMACFDFuncs.h"
 
 using namespace etiss;
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_tum_csrInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_tum_csrInstr.cpp
index ed80d4ea58..9e12a54e3c 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD_tum_csrInstr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_tum_csrInstr.cpp
@@ -1,13 +1,11 @@
 /**
- * Generated on Wed, 04 Oct 2023 17:01:33 +0200.
+ * Generated on Fri, 03 Nov 2023 13:22:23 +0100.
  *
  * This file contains the instruction behavior models of the tum_csr
  * instruction set for the RV64IMACFD core architecture.
  */
 
 #include "RV64IMACFDArch.h"
-
-#define ETISS_ARCH_STATIC_FN_ONLY
 #include "RV64IMACFDFuncs.h"
 
 using namespace etiss;
@@ -57,8 +55,8 @@ cp.code() += "etiss_uint64 xrs1 = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1
 if ((rd % 32ULL) != 0ULL) { // conditional
 { // block
 cp.code() += "{ // block\n";
-cp.code() += "etiss_uint64 xrd = csr_read(cpu, system, plugin_pointers, " + std::to_string(csr) + "ULL);\n";
-cp.code() += "csr_write(cpu, system, plugin_pointers, " + std::to_string(csr) + "ULL, xrs1);\n";
+cp.code() += "etiss_uint64 xrd = RV64IMACFD_csr_read(cpu, system, plugin_pointers, " + std::to_string(csr) + "ULL);\n";
+cp.code() += "RV64IMACFD_csr_write(cpu, system, plugin_pointers, " + std::to_string(csr) + "ULL, xrs1);\n";
 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = xrd;\n";
 cp.code() += "} // block\n";
 } // block
@@ -66,7 +64,7 @@ cp.code() += "} // block\n";
 else { // conditional
 { // block
 cp.code() += "{ // block\n";
-cp.code() += "csr_write(cpu, system, plugin_pointers, " + std::to_string(csr) + "ULL, xrs1);\n";
+cp.code() += "RV64IMACFD_csr_write(cpu, system, plugin_pointers, " + std::to_string(csr) + "ULL, xrs1);\n";
 cp.code() += "} // block\n";
 } // block
 } // conditional
@@ -143,10 +141,10 @@ cp.code() += "} // block\n";
 } // block
 { // block
 cp.code() += "{ // block\n";
-cp.code() += "etiss_uint64 xrd = csr_read(cpu, system, plugin_pointers, " + std::to_string(csr) + "ULL);\n";
+cp.code() += "etiss_uint64 xrd = RV64IMACFD_csr_read(cpu, system, plugin_pointers, " + std::to_string(csr) + "ULL);\n";
 cp.code() += "etiss_uint64 xrs1 = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL];\n";
 if (rs1 != 0ULL) { // conditional
-cp.code() += "csr_write(cpu, system, plugin_pointers, " + std::to_string(csr) + "ULL, xrd | xrs1);\n";
+cp.code() += "RV64IMACFD_csr_write(cpu, system, plugin_pointers, " + std::to_string(csr) + "ULL, xrd | xrs1);\n";
 } // conditional
 if ((rd % 32ULL) != 0ULL) { // conditional
 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = xrd;\n";
@@ -224,10 +222,10 @@ cp.code() += "} // block\n";
 } // block
 { // block
 cp.code() += "{ // block\n";
-cp.code() += "etiss_uint64 xrd = csr_read(cpu, system, plugin_pointers, " + std::to_string(csr) + "ULL);\n";
+cp.code() += "etiss_uint64 xrd = RV64IMACFD_csr_read(cpu, system, plugin_pointers, " + std::to_string(csr) + "ULL);\n";
 cp.code() += "etiss_uint64 xrs1 = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL];\n";
 if (rs1 != 0ULL) { // conditional
-cp.code() += "csr_write(cpu, system, plugin_pointers, " + std::to_string(csr) + "ULL, xrd & ~(xrs1));\n";
+cp.code() += "RV64IMACFD_csr_write(cpu, system, plugin_pointers, " + std::to_string(csr) + "ULL, xrd & ~(xrs1));\n";
 } // conditional
 if ((rd % 32ULL) != 0ULL) { // conditional
 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = xrd;\n";
@@ -305,8 +303,8 @@ cp.code() += "} // block\n";
 } // block
 { // block
 cp.code() += "{ // block\n";
-cp.code() += "etiss_uint64 xrd = csr_read(cpu, system, plugin_pointers, " + std::to_string(csr) + "ULL);\n";
-cp.code() += "csr_write(cpu, system, plugin_pointers, " + std::to_string(csr) + "ULL, " + std::to_string((etiss_uint64)(zimm)) + "ULL);\n";
+cp.code() += "etiss_uint64 xrd = RV64IMACFD_csr_read(cpu, system, plugin_pointers, " + std::to_string(csr) + "ULL);\n";
+cp.code() += "RV64IMACFD_csr_write(cpu, system, plugin_pointers, " + std::to_string(csr) + "ULL, " + std::to_string((etiss_uint64)(zimm)) + "ULL);\n";
 if ((rd % 32ULL) != 0ULL) { // conditional
 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = xrd;\n";
 } // conditional
@@ -383,9 +381,9 @@ cp.code() += "} // block\n";
 } // block
 { // block
 cp.code() += "{ // block\n";
-cp.code() += "etiss_uint64 xrd = csr_read(cpu, system, plugin_pointers, " + std::to_string(csr) + "ULL);\n";
+cp.code() += "etiss_uint64 xrd = RV64IMACFD_csr_read(cpu, system, plugin_pointers, " + std::to_string(csr) + "ULL);\n";
 if (zimm != 0ULL) { // conditional
-cp.code() += "csr_write(cpu, system, plugin_pointers, " + std::to_string(csr) + "ULL, xrd | " + std::to_string((etiss_uint64)(zimm)) + "ULL);\n";
+cp.code() += "RV64IMACFD_csr_write(cpu, system, plugin_pointers, " + std::to_string(csr) + "ULL, xrd | " + std::to_string((etiss_uint64)(zimm)) + "ULL);\n";
 } // conditional
 if ((rd % 32ULL) != 0ULL) { // conditional
 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = xrd;\n";
@@ -463,9 +461,9 @@ cp.code() += "} // block\n";
 } // block
 { // block
 cp.code() += "{ // block\n";
-cp.code() += "etiss_uint64 xrd = csr_read(cpu, system, plugin_pointers, " + std::to_string(csr) + "ULL);\n";
+cp.code() += "etiss_uint64 xrd = RV64IMACFD_csr_read(cpu, system, plugin_pointers, " + std::to_string(csr) + "ULL);\n";
 if (zimm != 0ULL) { // conditional
-cp.code() += "csr_write(cpu, system, plugin_pointers, " + std::to_string(csr) + "ULL, xrd & " + std::to_string(~(((etiss_uint64)(zimm)))) + "ULL);\n";
+cp.code() += "RV64IMACFD_csr_write(cpu, system, plugin_pointers, " + std::to_string(csr) + "ULL, xrd & " + std::to_string(~(((etiss_uint64)(zimm)))) + "ULL);\n";
 } // conditional
 if ((rd % 32ULL) != 0ULL) { // conditional
 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = xrd;\n";
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_tum_retInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_tum_retInstr.cpp
index ae78dee27e..66eea9bce8 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD_tum_retInstr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_tum_retInstr.cpp
@@ -1,13 +1,11 @@
 /**
- * Generated on Wed, 04 Oct 2023 17:01:33 +0200.
+ * Generated on Fri, 03 Nov 2023 13:22:23 +0100.
  *
  * This file contains the instruction behavior models of the tum_ret
  * instruction set for the RV64IMACFD core architecture.
  */
 
 #include "RV64IMACFDArch.h"
-
-#define ETISS_ARCH_STATIC_FN_ONLY
 #include "RV64IMACFDFuncs.h"
 
 using namespace etiss;
@@ -46,7 +44,7 @@ cp.code() += "} // block\n";
 cp.code() += "{ // block\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "raise(cpu, system, plugin_pointers, 0ULL, 8LL + ((RV64IMACFD*)cpu)->PRIV);\n";
+cp.code() += "RV64IMACFD_raise(cpu, system, plugin_pointers, 0ULL, 8LL + ((RV64IMACFD*)cpu)->PRIV);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -117,21 +115,21 @@ cp.code() += "{ // block\n";
 cp.code() += "if (((RV64IMACFD*)cpu)->PRIV < 3LL) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "raise(cpu, system, plugin_pointers, 0ULL, 2LL);\n";
+cp.code() += "RV64IMACFD_raise(cpu, system, plugin_pointers, 0ULL, 2LL);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
 cp.code() += "} // conditional\n";
 cp.code() += "cpu->nextPc = *((RV64IMACFD*)cpu)->CSR[833LL];\n";
-cp.code() += "etiss_uint64 s = csr_read(cpu, system, plugin_pointers, 768LL);\n";
-cp.code() += "etiss_uint64 prev_prv = get_field(s, 6144LL);\n";
+cp.code() += "etiss_uint64 s = RV64IMACFD_csr_read(cpu, system, plugin_pointers, 768LL);\n";
+cp.code() += "etiss_uint64 prev_prv = RV64IMACFD_get_field(s, 6144LL);\n";
 cp.code() += "if (prev_prv != 3LL) { // conditional\n";
-cp.code() += "s = set_field(s, 131072LL, 0ULL);\n";
+cp.code() += "s = RV64IMACFD_set_field(s, 131072LL, 0ULL);\n";
 cp.code() += "} // conditional\n";
-cp.code() += "s = set_field(s, 8LL, get_field(s, 128LL));\n";
-cp.code() += "s = set_field(s, 128LL, 1ULL);\n";
-cp.code() += "s = set_field(s, 6144LL, (extension_enabled(cpu, system, plugin_pointers, 85ULL)) ? (0LL) : (3LL));\n";
-cp.code() += "csr_write(cpu, system, plugin_pointers, 768LL, s);\n";
+cp.code() += "s = RV64IMACFD_set_field(s, 8LL, RV64IMACFD_get_field(s, 128LL));\n";
+cp.code() += "s = RV64IMACFD_set_field(s, 128LL, 1ULL);\n";
+cp.code() += "s = RV64IMACFD_set_field(s, 6144LL, (RV64IMACFD_extension_enabled(cpu, system, plugin_pointers, 85ULL)) ? (0LL) : (3LL));\n";
+cp.code() += "RV64IMACFD_csr_write(cpu, system, plugin_pointers, 768LL, s);\n";
 cp.code() += "((RV64IMACFD*)cpu)->PRIV = (prev_prv) & 0x7;\n";
 cp.code() += "} // block\n";
 } // block
@@ -261,21 +259,21 @@ cp.code() += "} // block\n";
 } // block
 { // block
 cp.code() += "{ // block\n";
-cp.code() += "if (((RV64IMACFD*)cpu)->PRIV < ((get_field(csr_read(cpu, system, plugin_pointers, 768LL), 4194304LL)) ? (3LL) : (1LL))) { // conditional\n";
+cp.code() += "if (((RV64IMACFD*)cpu)->PRIV < ((RV64IMACFD_get_field(RV64IMACFD_csr_read(cpu, system, plugin_pointers, 768LL), 4194304LL)) ? (3LL) : (1LL))) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "raise(cpu, system, plugin_pointers, 0ULL, 2LL);\n";
+cp.code() += "RV64IMACFD_raise(cpu, system, plugin_pointers, 0ULL, 2LL);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
 cp.code() += "} // conditional\n";
 cp.code() += "cpu->nextPc = *((RV64IMACFD*)cpu)->CSR[321LL];\n";
-cp.code() += "etiss_uint64 s = csr_read(cpu, system, plugin_pointers, 256LL);\n";
-cp.code() += "etiss_uint64 prev_prv = get_field(s, 256LL);\n";
-cp.code() += "s = set_field(s, 2LL, get_field(s, 32LL));\n";
-cp.code() += "s = set_field(s, 32LL, 1ULL);\n";
-cp.code() += "s = set_field(s, 256LL, 0LL);\n";
-cp.code() += "csr_write(cpu, system, plugin_pointers, 768LL, s);\n";
+cp.code() += "etiss_uint64 s = RV64IMACFD_csr_read(cpu, system, plugin_pointers, 256LL);\n";
+cp.code() += "etiss_uint64 prev_prv = RV64IMACFD_get_field(s, 256LL);\n";
+cp.code() += "s = RV64IMACFD_set_field(s, 2LL, RV64IMACFD_get_field(s, 32LL));\n";
+cp.code() += "s = RV64IMACFD_set_field(s, 32LL, 1ULL);\n";
+cp.code() += "s = RV64IMACFD_set_field(s, 256LL, 0LL);\n";
+cp.code() += "RV64IMACFD_csr_write(cpu, system, plugin_pointers, 768LL, s);\n";
 cp.code() += "((RV64IMACFD*)cpu)->PRIV = (prev_prv) & 0x7;\n";
 cp.code() += "} // block\n";
 } // block
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_tum_rva64Instr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_tum_rva64Instr.cpp
index 51497c6228..2afa8ca8f1 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD_tum_rva64Instr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_tum_rva64Instr.cpp
@@ -1,13 +1,11 @@
 /**
- * Generated on Wed, 04 Oct 2023 17:01:33 +0200.
+ * Generated on Fri, 03 Nov 2023 13:22:23 +0100.
  *
  * This file contains the instruction behavior models of the tum_rva64
  * instruction set for the RV64IMACFD core architecture.
  */
 
 #include "RV64IMACFDArch.h"
-
-#define ETISS_ARCH_STATIC_FN_ONLY
 #include "RV64IMACFDFuncs.h"
 
 using namespace etiss;
@@ -62,7 +60,7 @@ cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (e
 cp.code() += "if (cpu->exception) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -171,7 +169,7 @@ cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (
 cp.code() += "if (cpu->exception) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_tum_rvaInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_tum_rvaInstr.cpp
index 41a384c539..6cdfbc4415 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD_tum_rvaInstr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_tum_rvaInstr.cpp
@@ -1,13 +1,11 @@
 /**
- * Generated on Wed, 04 Oct 2023 17:01:33 +0200.
+ * Generated on Fri, 03 Nov 2023 13:22:23 +0100.
  *
  * This file contains the instruction behavior models of the tum_rva
  * instruction set for the RV64IMACFD core architecture.
  */
 
 #include "RV64IMACFDArch.h"
-
-#define ETISS_ARCH_STATIC_FN_ONLY
 #include "RV64IMACFDFuncs.h"
 
 using namespace etiss;
@@ -62,7 +60,7 @@ cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (e
 cp.code() += "if (cpu->exception) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -171,7 +169,7 @@ cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (
 cp.code() += "if (cpu->exception) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_tum_rvmInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_tum_rvmInstr.cpp
new file mode 100644
index 0000000000..0779aebade
--- /dev/null
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_tum_rvmInstr.cpp
@@ -0,0 +1,334 @@
+/**
+ * Generated on Fri, 03 Nov 2023 13:22:23 +0100.
+ *
+ * This file contains the instruction behavior models of the tum_rvm
+ * instruction set for the RV64IMACFD core architecture.
+ */
+
+#include "RV64IMACFDArch.h"
+#include "RV64IMACFDFuncs.h"
+
+using namespace etiss;
+using namespace etiss::instr;
+
+
+// MUL -------------------------------------------------------------------------
+static InstructionDefinition mul_rd_rs1_rs2 (
+	ISA32_RV64IMACFD,
+	"mul",
+	(uint32_t) 0x2000033,
+	(uint32_t) 0xfe00707f,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint8 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
+
+		cp.code() = std::string("//MUL\n");
+
+// -----------------------------------------------------------------------------
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
+{ // block
+cp.code() += "{ // block\n";
+if ((rd % 32ULL) != 0ULL) { // conditional
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "etiss_int64 res = (etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL]) * (etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]);\n";
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_uint64)(res);\n";
+cp.code() += "} // block\n";
+} // block
+} // conditional
+cp.code() += "} // block\n";
+} // block
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+// -----------------------------------------------------------------------------
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint8 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "mul" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
+
+// MULH ------------------------------------------------------------------------
+static InstructionDefinition mulh_rd_rs1_rs2 (
+	ISA32_RV64IMACFD,
+	"mulh",
+	(uint32_t) 0x2001033,
+	(uint32_t) 0xfe00707f,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint8 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
+
+		cp.code() = std::string("//MULH\n");
+
+// -----------------------------------------------------------------------------
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
+{ // block
+cp.code() += "{ // block\n";
+if ((rd % 32ULL) != 0ULL) { // conditional
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = RV64IMACFD_mulh((etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL]), (etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]));\n";
+cp.code() += "} // block\n";
+} // block
+} // conditional
+cp.code() += "} // block\n";
+} // block
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+// -----------------------------------------------------------------------------
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint8 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "mulh" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
+
+// MULHSU ----------------------------------------------------------------------
+static InstructionDefinition mulhsu_rd_rs1_rs2 (
+	ISA32_RV64IMACFD,
+	"mulhsu",
+	(uint32_t) 0x2002033,
+	(uint32_t) 0xfe00707f,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint8 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
+
+		cp.code() = std::string("//MULHSU\n");
+
+// -----------------------------------------------------------------------------
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
+{ // block
+cp.code() += "{ // block\n";
+if ((rd % 32ULL) != 0ULL) { // conditional
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = RV64IMACFD_mulhsu((etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL]), *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]);\n";
+cp.code() += "} // block\n";
+} // block
+} // conditional
+cp.code() += "} // block\n";
+} // block
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+// -----------------------------------------------------------------------------
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint8 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "mulhsu" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
+
+// MULHU -----------------------------------------------------------------------
+static InstructionDefinition mulhu_rd_rs1_rs2 (
+	ISA32_RV64IMACFD,
+	"mulhu",
+	(uint32_t) 0x2003033,
+	(uint32_t) 0xfe00707f,
+	[] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
+	{
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint8 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+	{
+		CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
+
+		cp.code() = std::string("//MULHU\n");
+
+// -----------------------------------------------------------------------------
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
+cp.code() += "} // block\n";
+} // block
+{ // block
+cp.code() += "{ // block\n";
+if ((rd % 32ULL) != 0ULL) { // conditional
+{ // block
+cp.code() += "{ // block\n";
+cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = RV64IMACFD_mulhu(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL], *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]);\n";
+cp.code() += "} // block\n";
+} // block
+} // conditional
+cp.code() += "} // block\n";
+} // block
+cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
+cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
+// -----------------------------------------------------------------------------
+		cp.getAffectedRegisters().add("instructionPointer", 32);
+	}
+
+		return true;
+	},
+	0,
+	[] (BitArray & ba, Instruction & instr)
+	{
+// -----------------------------------------------------------------------------
+etiss_uint8 rd = 0;
+static BitArrayRange R_rd_0(11, 7);
+rd += R_rd_0.read(ba) << 0;
+etiss_uint8 rs1 = 0;
+static BitArrayRange R_rs1_0(19, 15);
+rs1 += R_rs1_0.read(ba) << 0;
+etiss_uint8 rs2 = 0;
+static BitArrayRange R_rs2_0(24, 20);
+rs2 += R_rs2_0.read(ba) << 0;
+
+// -----------------------------------------------------------------------------
+
+		std::stringstream ss;
+// -----------------------------------------------------------------------------
+ss << "mulhu" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
+// -----------------------------------------------------------------------------
+		return ss.str();
+	}
+);
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_tum_semihostingInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_tum_semihostingInstr.cpp
index adfedfbfa0..d83bdba121 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD_tum_semihostingInstr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_tum_semihostingInstr.cpp
@@ -1,13 +1,11 @@
 /**
- * Generated on Wed, 04 Oct 2023 17:01:33 +0200.
+ * Generated on Fri, 03 Nov 2023 13:22:23 +0100.
  *
  * This file contains the instruction behavior models of the tum_semihosting
  * instruction set for the RV64IMACFD core architecture.
  */
 
 #include "RV64IMACFDArch.h"
-
-#define ETISS_ARCH_STATIC_FN_ONLY
 #include "RV64IMACFDFuncs.h"
 
 using namespace etiss;
@@ -52,7 +50,7 @@ cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, " + std:
 cp.code() += "if (cpu->exception) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -63,7 +61,7 @@ cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, " + std:
 cp.code() += "if (cpu->exception) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -74,7 +72,7 @@ cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, " + std:
 cp.code() += "if (cpu->exception) { // conditional\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
+cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -94,7 +92,7 @@ cp.code() += "else { // conditional\n";
 cp.code() += "{ // block\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "raise(cpu, system, plugin_pointers, 0ULL, 3LL);\n";
+cp.code() += "RV64IMACFD_raise(cpu, system, plugin_pointers, 0ULL, 3LL);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
@@ -109,7 +107,7 @@ cp.code() += "else { // conditional\n";
 cp.code() += "{ // block\n";
 { // procedure
 cp.code() += "{ // procedure\n";
-cp.code() += "raise(cpu, system, plugin_pointers, 0ULL, 3LL);\n";
+cp.code() += "RV64IMACFD_raise(cpu, system, plugin_pointers, 0ULL, 3LL);\n";
 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
 cp.code() += "} // procedure\n";
 } // procedure
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_tum_sfenceInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_tum_sfenceInstr.cpp
index f0d767ba53..6cbe14b891 100644
--- a/ArchImpl/RV64IMACFD/RV64IMACFD_tum_sfenceInstr.cpp
+++ b/ArchImpl/RV64IMACFD/RV64IMACFD_tum_sfenceInstr.cpp
@@ -8,7 +8,9 @@
 #include "RV64IMACFDArch.h"
 
 #define ETISS_ARCH_STATIC_FN_ONLY
+extern "C" {
 #include "RV64IMACFDFuncs.h"
+}
 
 using namespace etiss;
 using namespace etiss::instr;