Merge branch 'master' into zcmt_design

10x-Engineers · Jan 9, 2025 · f1c455a · f1c455a
2 parents dc9d9f3 + 5a484fc
commit f1c455a
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Showing 2 changed files with 2 additions and 2 deletions.
diff --git a/core/cache_subsystem/wt_axi_adapter.sv b/core/cache_subsystem/wt_axi_adapter.sv
@@ -178,7 +178,7 @@ module wt_axi_adapter
       axi_rd_addr = {{CVA6Cfg.AxiAddrWidth - CVA6Cfg.PLEN{1'b0}}, icache_data.paddr};
       axi_rd_size = MaxNumWords[2:0];  // always request max number of words in case of ifill
       if (!icache_data.nc) begin
-        axi_rd_blen = AxiRdBlenDcache[AxiBlenWidth-1:0];
+        axi_rd_blen = AxiRdBlenIcache[AxiBlenWidth-1:0];
       end
     end
 

diff --git a/verif/sim/Makefile b/verif/sim/Makefile
@@ -214,7 +214,7 @@ ALL_UVM_FLAGS   = -lca -sverilog +incdir+$(VCS_HOME)/etc/uvm/src \
 	  $(VCS_HOME)/etc/uvm/src/uvm_pkg.sv -ntb_opts uvm-1.2 -timescale=1ns/1ps \
 	  -assert svaext -race=all -ignore unique_checks -full64 -q +incdir+$(VCS_HOME)/etc/uvm/src \
 	  $(if $(DEBUG), -debug_access+all $(if $(VERDI), -kdb) $(if $(TRACE_COMPACT),+vcs+fsdbon)) \
-	  -cm_seqnoconst -diag noconst \
+	  -cm_seqnoconst -diag noconst -cm_cond arith \
 
 ALL_SIMV_UVM_FLAGS      = +vcs+lic+wait $(issrun_opts) \