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Add 01-07 Uint08 (automatically generated)
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@Obijuan
Obijuan committed Nov 4, 2023
1 parent bd8d482 commit 2433d67
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101 changes: 101 additions & 0 deletions blocks/Uint/Uint08/01-Uint08.ice
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{
"version": "1.2",
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"version": "0.4",
"description": "01-Uint08: 1 bits unsigned integer extension to 8 bits. Verilog implementation",
"author": "Juan González-Gómez (Obijuan)",
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101 changes: 101 additions & 0 deletions blocks/Uint/Uint08/02-Uint08.ice
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Original file line number Diff line number Diff line change
@@ -0,0 +1,101 @@
{
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"code": "//-- Number of input bits\nlocalparam X = 2;\n\n//-- Number of output bits\nlocalparam N = 8;\n\n//-- zeros to add to the input\nwire zeros = {(N-X){1'b0}};\n\n//-- Extend the input with zeros\nassign o = { zeros , i};"
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101 changes: 101 additions & 0 deletions blocks/Uint/Uint08/03-Uint08.ice
View file
Original file line number Diff line number Diff line change
@@ -0,0 +1,101 @@
{
"version": "1.2",
"package": {
"name": "03-Uint08",
"version": "0.4",
"description": "03-Uint08: 3 bits unsigned integer extension to 8 bits. Verilog implementation",
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"code": "//-- Number of input bits\nlocalparam X = 3;\n\n//-- Number of output bits\nlocalparam N = 8;\n\n//-- zeros to add to the input\nwire zeros = {(N-X){1'b0}};\n\n//-- Extend the input with zeros\nassign o = { zeros , i};"
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