This project implements a simple CPU using a controller-datapath architecture in VHDL. It integrates a finite state machine (FSM) controller for instruction sequencing and a structurally designed datapath, handling operations like load, store, arithmetic, and jump instructions. The CPU supports SIMD operations, parallel processing with dual ALUs and accumulators, and uses a 32-word program memory implemented on an FPGA. Enhancements include custom instructions (2's complement instruction which utilized the increment instruction implemented earlier), advanced testbenches, and a detailed RTL-based design validated through simulation.

This project demonstrates a comprehensive understanding of digital logic design and CPU architecture.