test/test_axi/test_axi_width_converter: Switch to DUT.

QuickLogic-Corp · Dec 8, 2022 · 0f95d04 · 0f95d04
1 parent fd12b6b
commit 0f95d04
Showing 1 changed file with 4 additions and 4 deletions.
diff --git a/test/test_axi.py b/test/test_axi.py
@@ -371,7 +371,7 @@ def generator_rd(dut):
             addr = 0x34
             yield axi_port.ar.addr.eq(addr * dut.mem.bus.data_width // 8)
             yield axi_port.ar.valid.eq(1)
-            yield axi_port.ar.burst.eq(0)
+            yield axi_port.ar.burst.eq(0b1) # CHECKME.
             yield axi_port.ar.len.eq(0)
             yield axi_port.ar.size.eq(log2_int(axi_port.data_width // 8))
             yield axi_port.r.ready.eq(1)
@@ -392,7 +392,7 @@ def generator_wr(dut):
             data = 0x98761244
             yield axi_port.aw.addr.eq(addr * 4)
             yield axi_port.aw.valid.eq(1)
-            yield axi_port.aw.burst.eq(0)
+            yield axi_port.aw.burst.eq(0b1) # CHECKME.
             yield axi_port.aw.len.eq(0)
             yield axi_port.aw.size.eq(log2_int(axi_port.data_width // 8))
             yield axi_port.w.strb.eq(2**(len(axi_port.w.data)//8) - 1)
@@ -413,6 +413,6 @@ def generator_wr(dut):
                 i += 1
             assert data == mem_content, (hex(data), hex(mem_content))
 
-        #dut = DUT(64, 32)
-        dut = DUT_ref(64, 32)
+        dut = DUT(64, 32)
+        #dut = DUT_ref(64, 32)
         run_simulation(dut, [generator_rd(dut), generator_wr(dut)], vcd_name="sim.vcd")