Update OpenFPGA to latest (submodule checkout has issues in older ver…

…sions)
QuickLogic-Corp · Feb 4, 2024 · a0ccd48 · a0ccd48
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commit a0ccd48
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diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml
@@ -183,7 +183,8 @@ jobs:
       with:
         access_token: ${{ github.token }}
 
-    - uses: actions/checkout@v3
+    - name: Checkout Repo
+      uses: actions/[email protected]
       with:
         submodules: recursive
         fetch-depth: 0

diff --git a/openfpga b/openfpga
+92 −61		.github/labeler.yml
+3 −6		.github/workflows/build.yml
+4 −1		.github/workflows/labeler.yml
+3 −1		CMakeLists.txt
+1 −1		Makefile
+1 −1		VERSION.md
+48 −1		docs/source/manual/arch_lang/addon_vpr_syntax.rst
+574 −0		docs/source/manual/arch_lang/figures/concat_pass_wire.svg
+580 −0		docs/source/manual/arch_lang/figures/concat_wire.svg
+592 −0		docs/source/manual/arch_lang/figures/opin2all_sides.svg
+18 −0		docs/source/manual/file_formats/repack_design_constraints.rst
+8 −2		docs/source/manual/openfpga_flow/run_fpga_task.rst
+2 −1		docs/source/manual/openfpga_shell/openfpga_commands/fpga_bitstream_commands.rst
+81 −0		docs/source/manual/openfpga_shell/openfpga_commands/fpga_verilog_commands.rst
+5 −1		libs/libpcf/src/base/repack_design_constraints.h
+53 −4		libs/libpcf/src/io/read_xml_repack_design_constraints.cpp
+2 −2		openfpga/src/base/openfpga_pb_pin_fixup.cpp
+152 −0		openfpga/src/base/openfpga_verilog_command_template.h
+98 −0		openfpga/src/base/openfpga_verilog_template.h
+1 −1		openfpga/src/fabric/build_grid_modules.cpp
+6 −1		openfpga/src/fabric/build_memory_modules.cpp
+1 −0		openfpga/src/fabric/build_memory_modules.h
+25 −18		openfpga/src/fabric/build_routing_modules.cpp
+1 −1		openfpga/src/fpga_bitstream/write_text_fabric_bitstream.cpp
+68 −0		openfpga/src/fpga_verilog/verilog_api.cpp
+14 −0		openfpga/src/fpga_verilog/verilog_api.h
+6 −173		openfpga/src/fpga_verilog/verilog_preconfig_top_module.cpp
+190 −0		openfpga/src/fpga_verilog/verilog_preconfig_top_module_utils.cpp
+44 −0		openfpga/src/fpga_verilog/verilog_preconfig_top_module_utils.h
+17 −4		openfpga/src/fpga_verilog/verilog_routing.cpp
+132 −0		openfpga/src/fpga_verilog/verilog_template_testbench.cpp
+30 −0		openfpga/src/fpga_verilog/verilog_template_testbench.h
+111 −0		openfpga/src/fpga_verilog/verilog_testbench_io_connection.cpp
+38 −0		openfpga/src/fpga_verilog/verilog_testbench_io_connection.h
+72 −0		openfpga/src/fpga_verilog/verilog_testbench_options.cpp
+27 −0		openfpga/src/fpga_verilog/verilog_testbench_options.h
+17 −6		openfpga/src/fpga_verilog/verilog_top_testbench.cpp
+16 −8		openfpga/src/fpga_verilog/verilog_top_testbench_memory_bank.cpp
+2 −1		openfpga/src/fpga_verilog/verilog_top_testbench_memory_bank.h
+7 −4		openfpga/src/repack/repack.cpp
+18 −0		openfpga/src/repack/repack_option.cpp
+3 −0		openfpga/src/repack/repack_option.h
+2 −2		openfpga/src/utils/fabric_bitstream_utils.cpp
+1 −3		openfpga_flow/misc/fpgaflow_default_tool_path.conf
+76 −0		openfpga_flow/misc/fpgaflow_default_tool_path_timing.conf
+71 −0		openfpga_flow/openfpga_shell_scripts/write_full_testbench_simulator_support_example_script.openfpga
+57 −0		openfpga_flow/openfpga_shell_scripts/write_testbench_template_example_script.openfpga
+5 −1		openfpga_flow/regression_test_scripts/basic_reg_test.sh
+3 −0		openfpga_flow/regression_test_scripts/fpga_verilog_reg_test.sh
+22 −20		openfpga_flow/scripts/run_fpga_flow.py
+8 −1		openfpga_flow/scripts/run_fpga_task.py
+47 −0		openfpga_flow/tasks/basic_tests/full_testbench/ql_memory_bank_shift_register_vcs/config/task.conf
+12 −0		openfpga_flow/tasks/basic_tests/generate_template_testbench/config/counter8_bus_group.xml
+26 −0		openfpga_flow/tasks/basic_tests/generate_template_testbench/config/mac4_bus_group.xml
+5 −0		openfpga_flow/tasks/basic_tests/generate_template_testbench/config/pin_constraints_dummy.xml
+7 −0		openfpga_flow/tasks/basic_tests/generate_template_testbench/config/pin_constraints_reset.xml
+51 −0		openfpga_flow/tasks/basic_tests/generate_template_testbench/config/task.conf
+5 −0		openfpga_flow/tasks/fpga_bitstream/repack_ignore_nets/config/pin_constraints.xml
+7 −0		openfpga_flow/tasks/fpga_bitstream/repack_ignore_nets/config/repack_design_constraints.xml
+5 −0		openfpga_flow/tasks/fpga_bitstream/repack_ignore_nets/config/rst_on_lut_pc.xml
+8 −0		openfpga_flow/tasks/fpga_bitstream/repack_ignore_nets/config/rst_on_lut_repack_dc.xml
+50 −0		openfpga_flow/tasks/fpga_bitstream/repack_ignore_nets/config/task.conf
+1 −1		openfpga_flow/tasks/fpga_verilog/lut_design/single_mode/config/task.conf
+173 −0		openfpga_flow/tasks/fpga_verilog/rr_concat_wire/config/bus_group_gen.py
+5 −0		openfpga_flow/tasks/fpga_verilog/rr_concat_wire/config/counter8_bus_group_task.yaml
+7 −0		openfpga_flow/tasks/fpga_verilog/rr_concat_wire/config/pin_constraints_reset.xml
+48 −0		openfpga_flow/tasks/fpga_verilog/rr_concat_wire/config/task.conf
+2 −1		openfpga_flow/vpr_arch/README.md
+1 −1		openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml
+1 −1		openfpga_flow/vpr_arch/k4_frac_N4_tileable_adder_chain_40nm.xml
+1 −1		openfpga_flow/vpr_arch/k6_N10_tileable_40nm.xml
+1,239 −0		openfpga_flow/vpr_arch/k6_frac_N10_tileableConcatWire_adder_chain_dpram8K_dsp36_fracff_40nm.xml
+1 −1		openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_40nm.xml
+1 −1		openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_fracff_40nm.xml
+1 −1		openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_register_scan_chain_depop50_40nm.xml
+1 −1		vtr-verilog-to-routing
+1 −1		yosys
+1 −1		yosys-plugins