GitHub - SagiKimhi/nice: A nice-to-have SystemVerilog-UVM verification kit

Name		Name	Last commit message	Last commit date
Latest commit History 3 Commits
ref		ref
scripts		scripts
sim		sim
src/sv		src/sv
.gitignore		.gitignore
.svlint.toml		.svlint.toml
.svls.toml		.svls.toml
Bender.yml		Bender.yml
nice.code-workspace		nice.code-workspace
pyproject.toml		pyproject.toml