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* Merge pull request #99 in CTORISCVFWINFRA/riscv-fw-infrastructure from b-comrv-rtos to master

Squashed commit of the following:

commit dafd770e5a6cc48824635501255ff6c83636b616
Author: [email protected] <[email protected]>
Date:   Thu Aug 6 18:04:05 2020 +0300

    bug fix:
    - when context switch in comrv 3 register were missing when saving to task stack from comrv task stack
    - use D_BIT_MANIPULATION instead of __riscv_bitmanip

commit 64d03f9b3bda042d9eb02de8007121b085eda2e2
Merge: 7b5c487 9188aa6
Author: [email protected] <[email protected]>
Date:   Thu Aug 6 17:12:31 2020 +0300

    Merge remote-tracking branch 'origin/master' into loc/b-comrv-rtos

commit 7b5c4877ec840fa14233bcae2bde311c99a62809
Author: [email protected] <[email protected]>
Date:   Thu Jul 30 20:54:38 2020 +0300

    changes:
    use __riscv_bitmanip define in comrv
    new whisper version - fix registers and CSRs exposed to the end user

commit 9675ce3d03029058a70f1776bb45398ed65ed047
Merge: 371d28f 735067e
Author: [email protected] <[email protected]>
Date:   Thu Jul 30 12:24:21 2020 +0300

    Merge remote-tracking branch 'origin/master' into loc/b-comrv-rtos

commit 371d28fe9ce043f3c5e614856cb477b00f0d00d3
Author: [email protected] <[email protected]>
Date:   Thu Jul 30 11:41:46 2020 +0300

    align to llvm fix:
    I've reported an issue with llvm (07-08-2019): 'riscv inline assembly input operand failure'; this issue was fixed and our llvm has this fix, so I modify the comrv code accordingly. Link to the issue https://bugs.llvm.org/show_bug.cgi?id=42912

commit e1f0cc4a57118b7c5975985cf7a4bc0b64bf0950
Merge: b22329e 09c771a
Author: [email protected] <[email protected]>
Date:   Thu Jul 30 10:44:40 2020 +0300

    Merge remote-tracking branch 'origin/master' into loc/b-comrv-rtos

commit b22329eb0e78adf6e084628881b1078aaaba84e4
Merge: 62b3962 27b7600
Author: [email protected] <[email protected]>
Date:   Tue Jul 28 16:57:48 2020 +0300

    merge

commit 62b3962936db326de6fcd4c7e91421ec1cb1b30d
Author: [email protected] <[email protected]>
Date:   Tue Jul 28 16:55:37 2020 +0300

    new whisper version:
    whisper version with a fix related to sw interrupt
    comrv - empty macro for triggering sw interrupt
    comrv - add missing code (ret) in comrvReset

commit 9b066cb9e9ec673ff2a02a3db062a182a1042b85
Merge: fbefee6 46c26ea
Author: [email protected] <[email protected]>
Date:   Tue Jul 28 13:29:22 2020 +0300

    Merge remote-tracking branch 'origin/master' into loc/b-comrv-rtos

commit fbefee66960b8a27a3bffdac13c24087be189874
Author: [email protected] <[email protected]>
Date:   Tue Jul 28 11:57:20 2020 +0300

    CR changes:
    > rename reset function to comrvReset
    > comrvReset now gets an enum as input
    add call to comrvReset in the baremetal demo
    add critical section protection when resetting comrv control block

commit 529d475ff7ac3e78dc063e24768271d9e8e44b89
Author: [email protected] <[email protected]>
Date:   Sun Jul 26 15:55:34 2020 +0300

    add reset function comrvResetCacheCB()

* Update readme:
* Remove support for lagacy Nexys
* Remove support for unleashed
* Adding support for EH2, EL2
* Adding comments for shallow cloning

* adding link to swerfolf

* Merge pull request #107 in CTORISCVFWINFRA/riscv-fw-infrastructure from static/bitmanip_eh2_el2_to_master to master

* Bitmanip support

Squashed commit of the following:

commit 2961c33ee2c95ab3f225e98bc91ad8b46cb7c443
Author: nati rapaport <[email protected]>
Date:   Tue Aug 25 18:30:10 2020 +0300

    merge 2 static brances, to get rid of unwanted commit's history

* Merge pull request #105 in CTORISCVFWINFRA/riscv-fw-infrastructure from mpmc_haltie_fix_for_ehx1 to master

**** Add 'haltie' option in mpmc CSR when setting core to 'Halted' state. Currently demo fails! since there is no HW support
**** 'haltie' feature is supported only if SweRV EH1 version is bigger than 0.9 and EH2

Squashed commit of the following:

commit ed29a66e3a3ab81180470758c4b9743771f65cac
Merge: 88ff9ab 759c8c6
Author: nati rapaport <[email protected]>
Date:   Tue Sep 1 19:57:22 2020 +0300

    Merge branch 'master' into mpmc_haltie_fix_for_ehx1

commit 88ff9ab6a806a3202b8e651fd5b609c16b0b77b8
Author: nati rapaport <[email protected]>
Date:   Mon Aug 24 14:26:37 2020 +0300

    use string D_EHX1_VER_1_0 and D_EHX1_VER_0_9 to distinguish the EHX1 versions

commit 5c79f15f8b08a19c36f9f69311585a5c9857d284
Author: nati rapaport <[email protected]>
Date:   Sun Aug 23 18:51:09 2020 +0300

    fix the demo function - disable interrupts before starting the 'haltie' test

commit 1b48180a20e29c82dd48a1c1faf51112a53b2e51
Author: nati rapaport <[email protected]>
Date:   Sun Aug 23 15:08:41 2020 +0300

    SweRV EL2 and EH2 are aligned with SweRV EHX1 meaning they both support 'haltie' feature

commit 7da73495bc9610346f4c208d0dd323334e07d50c
Author: nati rapaport <[email protected]>
Date:   Sun Aug 23 14:24:24 2020 +0300

    'haltie' feature is supported only if SweRV EHX1 version is bigger than 0.9

commit a67755c4b2b01a6e4abc6321538ed18a18c8c40f
Author: nati rapaport <[email protected]>
Date:   Thu Aug 20 11:22:48 2020 +0300

    Add 'haltie' option in mpmc CSR when setting core to 'Halted' state. Currently demo fails!

* Merge pull request #109 in CTORISCVFWINFRA/riscv-fw-infrastructure from CSRs_updates_SweRV_EL2_EH2 to master

***** Updated CSRs for SweRV EL2 and EH2

Squashed commit of the following:

commit 51bfb32e1816d71ea3c9091239042bf89b2c71a1
Author: nati rapaport <[email protected]>
Date:   Wed Aug 26 15:04:01 2020 +0300

    CSRs update for EL2 and EH2

* Merge pull request #102 in CTORISCVFWINFRA/riscv-fw-infrastructure from swerv_2nd_gen_timer_feature to master

**** Add 'cascade' feature to 2'nd-gen SweRV
**** Disable/restore interrupts upon timers setup (for all SweRV generations)
**** Some in-code documentation fixes (for all Cores)

Squashed commit of the following:

commit e6df7a2478f3ee6e5d4586b9466ecceed40fae0c
Merge: 992fa75 71aa66a
Author: nati rapaport <[email protected]>
Date:   Wed Sep 2 15:46:24 2020 +0300

    Merge branch 'master' into swerv_2nd_gen_timer_feature

commit 992fa75e834bed301a9f53320152030012276f4d
Author: nati rapaport <[email protected]>
Date:   Tue Aug 25 22:59:17 2020 +0300

    Address PR remarks

commit b5b0227e8a392269688f591a3c89cfe55cba71cd
Author: nati rapaport <[email protected]>
Date:   Wed Aug 19 17:27:35 2020 +0300

    enabe/restore interrupts upon timers setup in Swerv-EH1 also

commit e90e711a80843bbf340c6795cf3f8f2e1c64ec17
Author: nati rapaport <[email protected]>
Date:   Wed Aug 19 17:26:08 2020 +0300

    Add 'cascade' feature to 2'nd-gen SweRV + enabe/restore interrupts upon timers setup + some in-code documentation fixes

* Merge pull request #103 in CTORISCVFWINFRA/riscv-fw-infrastructure from perf_monitor_fix_and_2nd_gen to master

*** fix - performance-monitor to supply 64bit of event counters rather only 32bits
*** add EL2 and EH2 perf-monitor features

Squashed commit of the following:

commit 161c54d6872b255b7498cc1ab8fd1a298a950d10
Author: nati rapaport <[email protected]>
Date:   Thu Sep 3 11:57:51 2020 +0300

    some modifications following the merge with master

commit f71ca683b3620cc4314efb3264f301c16086fbee
Merge: f2c98aa a60ae56
Author: nati rapaport <[email protected]>
Date:   Thu Sep 3 10:02:11 2020 +0300

    Merge branch 'master' into perf_monitor_fix_and_2nd_gen

commit f2c98aaf5bd96dd68ae0ef3928339c712baf852c
Author: nati rapaport <[email protected]>
Date:   Wed Sep 2 09:48:15 2020 +0300

    Address PR comments - give a 0xDEADBEEF default value to returned perf-mon counter. Locate functions in PSP section

commit 430a528561b699b26d21746a67a14f2adf597b4d
Author: nati rapaport <[email protected]>
Date:   Tue Sep 1 12:23:45 2020 +0300

    common base of SeRV eh1 aaaaand el2 in the demo function

commit 4c008956e72ab9b72f94dae243e98eb2b407abc8
Author: nati rapaport <[email protected]>
Date:   Mon Aug 31 21:01:12 2020 +0300

    modify perf-mon demo to control all counters and to enable/disable all. fix a bug in psp - remove wrong CSR definition of timer counter

commit 7cb259f1c01156415b6c95807fe9ca1338548534
Author: nati rapaport <[email protected]>
Date:   Mon Aug 24 15:43:56 2020 +0300

    set/clear all 5 counters in one CSR access rather than 5 accesses

commit 35a6fa6d7e2add1b349a452fe714691dac37f3b3
Author: nati rapaport <[email protected]>
Date:   Mon Aug 24 15:05:59 2020 +0300

    Do not #undef.. events from eh1 to eh2 and el2

commit 6a971d8dc519ba3be19e64994e06e7ecd781694d
Author: nati rapaport <[email protected]>
Date:   Thu Aug 20 19:06:05 2020 +0300

    add EL2 and EH2 perf-monitor features

commit 16f39487694e0b792e7f3b758d367899d5b72baf
Author: nati rapaport <[email protected]>
Date:   Thu Aug 20 16:02:29 2020 +0300

    fix - performance-monitor to supply 64bit of event counters rather only 32bits

* Merge pull request #108 in CTORISCVFWINFRA/riscv-fw-infrastructure from NMIs_el2_eh2 to master

**** NMIs updated features for SweRV EL2 and EH2

Squashed commit of the following:

commit 829f2dbac157806285d956a9f4c3feec6693e25c
Author: nati rapaport <[email protected]>
Date:   Thu Sep 3 13:29:01 2020 +0300

    modify demo/demo_pwr_mgmt_control.c following merge with master

commit 3990c0e4d9a9d11e2072956984d5bede65c28de4
Merge: 90c2d56 67bbb46
Author: nati rapaport <[email protected]>
Date:   Thu Sep 3 13:27:50 2020 +0300

    Merge branch 'master' into NMIs_el2_eh2

commit 90c2d562c8c0d90244f49b0b7ec46c96b9b2cdb2
Merge: e81f63d a60ae56
Author: nati rapaport <[email protected]>
Date:   Thu Sep 3 12:20:07 2020 +0300

    Merge branch 'master' into NMIs_el2_eh2

commit e81f63d2bb57688b6a9e0968a92afe47ec353ab9
Author: nati rapaport <[email protected]>
Date:   Wed Aug 26 14:40:21 2020 +0300

    NMIs changes for EL2 and EH2

* Merge pull request #111 in CTORISCVFWINFRA/riscv-fw-infrastructure from some_cleanup to master

*** Add interrupts-vector registration at bitmanip demo start
*** Rename psp_bitmanip_eh2.h --> psp_bitmanip_el2.h
*** Rename eh2 whisper launcher names to be more clear

Squashed commit of the following:

commit 3b4257d48f6d76751714a35c8af17e69e6b2ffca
Author: nati rapaport <[email protected]>
Date:   Mon Sep 7 17:18:40 2020 +0300

    forgot to commit the eh2 whisper launcher with the new name..

commit bf2e21364e8895379d7953a68093c8fabab5ad47
Author: nati rapaport <[email protected]>
Date:   Mon Sep 7 16:58:55 2020 +0300

    rename psp_bitmanip_eh2.h -> psp_bitmanip_el2.h, add instructions-vector registration at the start of bitmanip demo, rename eh2 whisper launcher names to be clearer

* Merge pull request #101 in CTORISCVFWINFRA/riscv-fw-infrastructure from b-comrv-rtos to master

*** bug fix in comrv - defragmentation implementation was incorrect; fix was tested with cti
*** bug fix in python script - in case a cache entry isn't used, a size of 1 was used for it instead of its real size (fix already pushed to gitlab binutiels)
*** in comrv.c rename comrv_ti -> cti

Squashed commit of the following:

commit 296375be2431d47339d1eb105845e0f92ab362d4
Author: [email protected] <[email protected]>
Date:   Mon Aug 17 10:47:17 2020 +0300

    add CTI defrag mark and rename CTI macros fro D_ to M_

commit 1d305d31dc15259a6625196e6d3634f2f321c01a
Author: [email protected] <[email protected]>
Date:   Sun Aug 16 12:59:58 2020 +0300

    bug fix:
    > bug fix in comrv - defragmentation implementation was incorrect; fix was tested with cti
    > bug fix in python script - in case a cache entry isn't used, a size of 1 was used for it instead of its real size
    > in comrv.c rename comrv_ti -> cti

commit 99056790ac4bcd77925081fe00b8604caba8dd66
Merge: dafd770 474b4b9
Author: [email protected] <[email protected]>
Date:   Sun Aug 9 07:32:08 2020 +0300

    Merge remote-tracking branch 'origin/master' into loc/b-comrv-rtos

commit dafd770e5a6cc48824635501255ff6c83636b616
Author: [email protected] <[email protected]>
Date:   Thu Aug 6 18:04:05 2020 +0300

    bug fix:
    - when context switch in comrv 3 register were missing when saving to task stack from comrv task stack
    - use D_BIT_MANIPULATION instead of __riscv_bitmanip

commit 64d03f9b3bda042d9eb02de8007121b085eda2e2
Merge: 7b5c487 9188aa6
Author: [email protected] <[email protected]>
Date:   Thu Aug 6 17:12:31 2020 +0300

    Merge remote-tracking branch 'origin/master' into loc/b-comrv-rtos

commit 7b5c4877ec840fa14233bcae2bde311c99a62809
Author: [email protected] <[email protected]>
Date:   Thu Jul 30 20:54:38 2020 +0300

    changes:
    use __riscv_bitmanip define in comrv
    new whisper version - fix registers and CSRs exposed to the end user

commit 9675ce3d03029058a70f1776bb45398ed65ed047
Merge: 371d28f 735067e
Author: [email protected] <[email protected]>
Date:   Thu Jul 30 12:24:21 2020 +0300

    Merge remote-tracking branch 'origin/master' into loc/b-comrv-rtos

commit 371d28fe9ce043f3c5e614856cb477b00f0d00d3
Author: [email protected] <[email protected]>
Date:   Thu Jul 30 11:41:46 2020 +0300

    align to llvm fix:
    I've reported an issue with llvm (07-08-2019): 'riscv inline assembly input operand failure'; this issue was fixed and our llvm has this fix, so I modify the comrv code accordingly. Link to the issue https://bugs.llvm.org/show_bug.cgi?id=42912

commit e1f0cc4a57118b7c5975985cf7a4bc0b64bf0950
Merge: b22329e 09c771a
Author: [email protected] <[email protected]>
Date:   Thu Jul 30 10:44:40 2020 +0300

    Merge remote-tracking branch 'origin/master' into loc/b-comrv-rtos

commit b22329eb0e78adf6e084628881b1078aaaba84e4
Merge: 62b3962 27b7600
Author: [email protected] <[email protected]>
Date:   Tue Jul 28 16:57:48 2020 +0300

    merge

commit 62b3962936db326de6fcd4c7e91421ec1cb1b30d
Author: [email protected] <[email protected]>
Date:   Tue Jul 28 16:55:37 2020 +0300

    new whisper version:
    whisper version with a fix related to sw interrupt
    comrv - empty macro for triggering sw interrupt
    comrv - add missing code (ret) in comrvReset

commit 9b066cb9e9ec673ff2a02a3db062a182a1042b85
Merge: fbefee6 46c26ea
Author: [email protected] <[email protected]>
Date:   Tue Jul 28 13:29:22 2020 +0300

    Merge remote-tracking branch 'origin/master' into loc/b-comrv-rtos

commit fbefee66960b8a27a3bffdac13c24087be189874
Author: [email protected] <[email protected]>
Date:   Tue Jul 28 11:57:20 2020 +0300

    CR changes:
    > rename reset function to comrvReset
    > comrvReset now gets an enum as input
    add call to comrvReset in the baremetal demo
    add critical section protection when resetting comrv control block

commit 529d475ff7ac3e78dc063e24768271d9e8e44b89
Author: [email protected] <[email protected]>
Date:   Sun Jul 26 15:55:34 2020 +0300

    add reset function comrvResetCacheCB()

* README.md edited online with Bitbucket

* Merge pull request #112 in CTORISCVFWINFRA/riscv-fw-infrastructure from new-gdb-for-llvm to master

*** New GDB for llvm toolchain
*** Hash #7f102cf34ac

```tar file was checked using beyond compare with old toolchain/llvm folder```
```GDB was tested by debugging various scenarios (foo foo tests)```

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Author: [email protected] <[email protected]>
Date:   Tue Sep 8 18:32:41 2020 +0300

    new gdb for llvm

* Merge pull request #114 in CTORISCVFWINFRA/riscv-fw-infrastructure from software_interrupts_el2_eh2 to master

*** Adding Demo for software-interrupts for EL2 and EH2 (currently supported only by Whisper)

Squashed commit of the following:

commit c2749468472b6269c20a84516d381f7defbeb189
Author: nati rapaport <[email protected]>
Date:   Wed Sep 9 18:48:55 2020 +0300

    simple demo for software-interrupt - el2 & eh2

* rebase from 75231f6 up to 5-Oct ef60b3b0150a596ffb609df22666bff66785b3fb, log history :
-------------------------------------------------------------------------------------------------------------------------
    Merge pull request #125 in CTORISCVFWINFRA/riscv-fw-infrastructure from merge-llvm-comrv-bitmanip to master

    *** unified support for one llvm that include comrv and bitmanip.
    *** the change support scons toolchain change and python change to take the llvm compilation and elfdump
    *** note: missing parsing by gdb for bitmanip commands.

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    commit aec346d6a90252a0188e70379168cbc22b14f566
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    Date:   Sun Oct 4 17:59:36 2020 +0300

        remove unused import

    commit f933979c600ea637a7ecee81cd8149d60a177a5e
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        remove old bitmanip scons tools

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        merging tools between llvm-comrv and llvm-bitmanip

commit 7eb9ce8bafaebc8d12f664ba92d879eb95e3a457
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    Merge pull request #122 in CTORISCVFWINFRA/riscv-fw-infrastructure from llvm-clang-12 to master

    **** new llvm-clang 12 with bitmanip and comrv support

      riscv-binutils
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        gfdc2b818c6
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        adding new llvm

commit a560c73b2a0c0bbc7b6a2069b882c27309d77310
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Date:   Tue Sep 22 11:55:04 2020 +0000

    Merge pull request #121 in CTORISCVFWINFRA/riscv-fw-infrastructure from eh2_align_for_rtos to master

    *** Add rtosal_int_vect_eh2.S file so rtos demos are now built and run for EH2 single-hart on Whisper
    *** note it was missing from merge #116 d23135c

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commit f70759e31c060db9f2fffaa603c4007e50e117ca
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    Merge pull request #120 in CTORISCVFWINFRA/riscv-fw-infrastructure from change_md_readme to master

    *** update readme file

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commit ce26a0a
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Date:   Tue Sep 15 15:11:01 2020 +0000

    Merge pull request #118 in CTORISCVFWINFRA/riscv-fw-infrastructure from fenci_bsp_register_writes to master

    **** Call FENCI upon any write-access to BSP register

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    commit c8d313410b63a3cb48976206eaa297e212fe560a
    Author: nati rapaport <[email protected]>
    Date:   Mon Sep 14 19:29:29 2020 +0300

        fenci any write-access to BSP registers

commit 07b3ff3
Author: Ronen Haen <[email protected]>
Date:   Tue Sep 15 06:34:09 2020 +0000

    Merge pull request #117 in CTORISCVFWINFRA/riscv-fw-infrastructure from comrv-cache-size-4K-bug-fix to master

    Squashed commit of the following:

    commit 7b9b0136f6bc32297c6c84138e5ced5b6e28cd24
    Author: [email protected] <[email protected]>
    Date:   Mon Sep 14 15:00:05 2020 +0300

        bug fix - remove code which cased corruption of the lru list in ases the cache size contains 2 entries only

    commit bdc1f7262d258199bdf372a72fd64518aaee6345
    Author: [email protected] <[email protected]>
    Date:   Sun Sep 13 18:42:42 2020 +0300

        fix the corner case where we have a cache size same as the max group supported - global mru wasn't properly saved

commit 1a2e32a
Author: Ofer Shinaar <[email protected]>
Date:   Sun Sep 13 09:47:01 2020 +0000

    README.md edited online with Bitbucket

    remove link to code convention

commit 65aacc9
Merge: d23135c 74ac59f
Author: Ofer Shinaar <[email protected]>
Date:   Sun Sep 13 09:32:35 2020 +0000

    Merge pull request #113 in CTORISCVFWINFRA/riscv-fw-infrastructure from remove_debug_csrs to master

    **** Remove debug CSRs from PSP

    * commit '74ac59feae0f57dc04e3864c6c3a436d039e25ed':
      remove debug CSRs from PSP

commit d23135c
Author: Ofer Shinaar <[email protected]>
Date:   Sun Sep 13 08:52:39 2020 +0000

    Merge pull request #116 in CTORISCVFWINFRA/riscv-fw-infrastructure from eh2_single_hart_rtos_supported to master

    *** Support RTOS on EH2 - single-hart on Whisper only

    Squashed commit of the following:

    commit 70fd8d5f7e72f2a0a99d556e021cc90883d4d443
    Author: nati rapaport <[email protected]>
    Date:   Thu Sep 10 12:40:55 2020 +0300

        EH2 supports RTOS with single-hart configuration

commit 683b4e9
Author: Ofer Shinaar <[email protected]>
Date:   Sun Sep 13 08:49:18 2020 +0000

    Merge pull request #115 in CTORISCVFWINFRA/riscv-fw-infrastructure from move-to-gcc-10 to master

    *** Move to gcc 10.2 with GDB 9.2

    riscv-gnu-toolchain
    url=https://github.com/westerndigitalcorporation/riscv-gnu-toolchain.git
    branch=gcc-10-2-gdb-9-2
    hash=5d25a757bb8626f22862cab884f445d0b855e28e

    Squashed commit of the following:

    commit 4ea50e2cfa3f3a1f00dd19e0e698ec2dfff07949
    Author: Nidal Faour <[email protected]>
    Date:   Thu Sep 10 12:07:17 2020 +0300

        moving to gcc 10 & gdb 9.2

-------------------------------------------------------------------------------------------------------------------------

* add hash files

* upload prog_mode.png, was removed from rebase

* Merge pull request #128 in CTORISCVFWINFRA/riscv-fw-infrastructure from new_el2_swervolf_after_rebase to master

**** New SweRV EL2 FPGA
support new EL2 build without fast-int

Squashed commit of the following:

commit 4525bdd80a45695e1cfa1ea43a737a3875506956
Author: nati rapaport <[email protected]>
Date:   Mon Oct 5 14:47:23 2020 +0300

    fix README typos

commit 0965c8497e07ea7021693b8fad73f58459d200f9
Author: nati rapaport <[email protected]>
Date:   Mon Oct 5 14:18:02 2020 +0300

    New SweRV EL2 FPGA + modify bsp_printf + align pwr-mngmnt demo+ update README file

* Merge pull request #129 in CTORISCVFWINFRA/riscv-fw-infrastructure from is_whisper_after_rebase to master

*** Check if Swerv or Whisper and run only if demo is supported

relevant to SW-interrupts, ext-interrupts, performance-monitor, power-management, NMI, bit-manipulation and cache-control for now....

Squashed commit of the following:

commit 0bd81a33d6cd707f74ea2b01d1b8f9a489d69075
Author: nati rapaport <[email protected]>
Date:   Mon Oct 5 17:23:57 2020 +0300

    for clarity sake - specify Swerv FPGA Board, rather than merely SweRV

commit 9bf32388aae90869594ec1148107a885ba417fdc
Author: nati rapaport <[email protected]>
Date:   Mon Oct 5 15:54:33 2020 +0300

    Check if Swerv or Whisper and run only if demo is supported

* Merge pull request #130 in CTORISCVFWINFRA/riscv-fw-infrastructure from fix-h51-build to master

*** fix hifive1 build issue
enclose with #ifdef the content of demoIsSwervBoard() function so function won't compile under hifive1
remove eh2 from external interrupts demo as it isn't supported
Tested comrv_baremetal, external_interrupts

Squashed commit of the following:

commit b265a1f632135bc8262c34a1232ce3529fc770bc
Author: [email protected] <[email protected]>
Date:   Tue Oct 6 08:34:58 2020 +0300

    fix hifive1 build issue:
    enclose with #ifdef the content of demoIsSwervBoard() function so function won't compile under hifive1
    remove eh2 from external interrupts demo as it isn't supported

* Merge pull request #131 in CTORISCVFWINFRA/riscv-fw-infrastructure from hash-update to master

**** adding hashes of the gcc in the llvm toolchain.

Squashed commit of the following:

commit 71c209e29e7b7726dedb1eb4821a33afa6c791a0
Author: Nidal Faour <[email protected]>
Date:   Tue Oct 6 12:23:48 2020 +0300

    fixing branches names in hash, need to fix the script to get the correct branches names, and need to update the tars with the correct branches names. in the gcc need to run the hash script and not create it manually

commit a1028d1ea5b354761b450b8b99dcab08e03fa227
Author: Nidal Faour <[email protected]>
Date:   Tue Oct 6 12:12:05 2020 +0300

    adding the gnu hashes to llvm hashes file

Co-authored-by: Ronen Haen <[email protected]>
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99 changes: 44 additions & 55 deletions README.md
100644 → 100755
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Expand Up @@ -3,64 +3,70 @@
![N|Solid](http://riscv.net/wp-content/uploads/2015/01/riscv-logo-retina.png)

# WD RISC-V Firmware Package
This repo is WD RISC-V Firmware package, holds:
This repostority is WD RISC-V Firmware package, holds:

- WD-Firmware
- GCC 9.2.0 Toolchain for RISC-V
- LLVM/Clang 10.0.0 Toolchain for RISC-V ***[along with GCC Binutils 2.32.51.20190122]***
- GCC 10.2.0 Toolchain for RISC-V
- LLVM/Clang 12.0.0 Toolchain for RISC-V ***[along with Custom GCC Binutils COMRV]***
- Eclipse MCU


# Getting the sources
If you dont have git lfs installed, please do the following steps:
This repostority use LFS.
If you dont have git LFS installed, please do the following steps (based on Debian/Ubuntu):

$ curl -s https://packagecloud.io/install/repositories/github/git-lfs/script.deb.sh | sudo bash
$ sudo apt-get install git-lfs

Getting the repository

$ git clone https://github.com/westerndigitalcorporation/riscv-fw-infrastructure.git


Since we use LFS it is adviced to use shallow cloning (without all history)

$ git clone --depth 1 https://github.com/westerndigitalcorporation/riscv-fw-infrastructure.git
[comment]: [] (This repository uses submodules..... )

[comment]: [] ($ git clone --recursiv https://bitbucket.wdc.com/scm/ctoriscvfwinfra/infra-riscv-fw.git)

# Code Convention
See [code convention.htm](https://bitbucket.wdc.com/projects/CTORISCVFWINFRA/repos/infra-riscv-fw/browse)
See [./code convention.htm]

# WD Firmware
The “WD Firmware package” constitutes an SDK FW. It contains Firmware applications and Processor Support Package (PSP) for various cores, alongside demos which support all features.
The following README file describes how to setup a build environment for the WD RISC-V firmware. It guides how to build the program, downloading it, and debugging it on the supported platforms and cores.
The FW-Infra was verified with VMWare player v. 15 hosting Debian 9.6. This demo was based on
The FW-Infra was verified with VMWare player v. 15 hosting Debian 9.6.


#### Current FW support:
- **RTOS-AL**
Abstraction Layer (AL) on embedded small footprint real time operation systems (RTOS). The target is to provide homogenies API for the developer usage, so the kernel can be replaced for several different RTOS’s, without any need from the developer to change its application code.
Currently this AL supports FreeRTOS and ThreadX (only API's, without core) with a real running demo for FreeRTOS.
The structure of WD Firmware package allows quick and easy integration for more RTOS’s, Platforms, boards and new firmware features.
Demos is based on HiFive FW example, by SiFIve. Cuurrently the reference is part of FreeRTOS maintenance
Demos is based on HiFive FW example, by SiFIve. Currently the reference is part of FreeRTOS maintenance

- **Coming soon**: more FW features and more Platform supports

#### Current Platform and Core support:
- **HiFive1**
- **SweRV** - running on *Nexys-A7 FPGA*
- **SweRVolf** - running on *Nexys-A7 FPGA* EH1 with full SoC
- **Whisper** - ISS tool running on SweRVolf EH1
- **SweRVolf** - running on *Nexys-A7 FPGA* EH1, EL2 with full SoC ( [LINK to source](https://github.com/chipsalliance/Cores-SweRVolf) )
- **Whisper** - ISS tool running EH1,EH2,EL2 ( [LINK to source](https://github.com/chipsalliance/SweRV-ISS) )


### Source tree structure
```javascript
WD-Firmware
├── board <-- supported boards
├── hifive-1
├── ihfive-unleashed (not supported yet)
├── nexys_a7_eh1 (Support for SweRV eh1, also support SweRVolf)
├── whisper (Support for SweRV eh1)
├── nexys_a7_eh1 (support for SweRV eh1, running on SweRVolf)
├── nexys_a7_eh2 (upcoming...)
├── nexys_a7_el2 (Support for SweRV el2, running on SweRVolf)
├── whisper (SweRV ISS Support for SweRV eh1, eh2, el2)
├── common <-- common source
├── comrv <-- ComRV - Cacheable Overlay Mangager for RISC-V (core source)
├── demo <-- demos source
├── build <-- example build scripts
├── toolchain <-- container for the unzip toolchains
├── demo_rtosal.c <-- Abstruction Layer (AL) demo on FreeRTOS
├── main.c <-- The main of all demos
├── ....
Expand Down Expand Up @@ -153,7 +159,9 @@ We provide several platforms to work with, please follow the instructions for th
- ***FPGA image file loading***: for loading the FPGA bit file, do the following steps:
- Copy the FPGA bit file /WD-Firmware/board/nexys_a7_eh1/***eh1_reference_design.bit*** to uSD device (locate it at the uSD root)
- Connect the uSD to the Nexys-A7 board (uSD slot is on board's bottom)
- Set the following jumpers: JP1 - connect JTAG & USB/SD pins. JP2 - connect the 2 pins on 'SD' side
- Set the following jumpers: JP1 - USB/SD pins. JP2 - connect the 2 pins on 'SD' side

![](prog_mode.png)
- At power-on the FPGA bit file is loaded to the FPGA. LED 'Busy' should be ORANGE while flushing is done
- Wait for ORANGE led to be off, once off the board is ready to be used

Expand All @@ -163,31 +171,7 @@ We provide several platforms to work with, please follow the instructions for th
- The eclipse IDE Console will display *shutdown command invoked* upon completion

&nbsp;
- #### Setting up Nexys-A7 for SweRV

Since Nexys-A7 is an FPGA platform it need special handling...
- ***Prerequisite***:
Following are prerequisite running SweRV core on Xilinx FPGA on Nexys-A7 board
- To compile the RTL please follow the instruction at this link: [swerv_eh1_fpga](https://github.com/westerndigitalcorporation/swerv_eh1_fpga)
- Our debugger uses the ***Olimex ARM-USB-Tiny-H*** Emulator with OpenOCD
- Pin layout for Nexys Pmod JD header with Olimex:

H4 = TDO
H1 = nTRST
G1 = TCK
H2 = TDI
G4 = TMS
G2 = nRST

- ***FPGA image file loading***:
for loading the FPGA bit file, do the following steps:
- Copy the FPGA bit file /WD-Firmware/board/nexys_a7_eh1/***eh1_reference_design.bit***
to uSD device (locate it at the uSD root)
- Connect the uSD to the Nexys-A7 board (uSD slot is on board's bottom)
- Set the following jumpers: JP1 - connect JTAG & USB/SD pins. JP2 - connect the 2 pins on 'SD' side
- At power-on the FPGA bit file is loaded to the FPGA. LED 'Busy' should be ORANGE while flushing is done.
- Wait for ORANGE led to be off, once off the board is ready to be used
&nbsp;

- #### Setting up ISS (works as simulator for EH1)

There is nothing to set for SweRV ISS, just select debugger luncher (following next)..
Expand All @@ -198,31 +182,36 @@ We provide several platforms to work with, please follow the instructions for th
- Current support:
```javascript
- hifive1 <-- HiFive Eval board
- nexys_a7_eh1 <-- Nexys A7 digilent FPGA board running SweRV EH1
- nexys_a7_eh1_swerolf <-- Nexys A7 digilent FPGA board running SweRV EH1
with full System on chip.
- nexys_a7_el2_swerolf <-- Nexys A7 digilent FPGA board running SweRV EL2
with full System on chip support.
From chipsalliance/Cores-SweRVolf
- whisper_eh1_connect_and_debug <-- SweRV ISS simulator
- whisper_eh1_connect_and_debug <-- SweRV ISS simulator for EH1
- whisper_eh2_connect_and_debug <-- SweRV ISS simulator for RH2
- whisper_el2_connect_and_debug <-- SweRV ISS simulator for EL2
```

### Adding new source modules

The folder WD-Firmware/demo/build/ contains a template file (SConscript_template) which can be used.
&nbsp;
# Supporting GCC Releases
- #### RISCV GCC 8.2
- Initial RISCV official 8.2 GCC release
- #### RISCV GCC 8.3
- RISCV official 8.3 GCC release
- GDB fix for skipping breakpoint at fist line after ASM lable
- lto simple_object fix opening mode in windows (text->bin)
- #### RISCV GCC 9.2
- RISCV official 9.2 GCC release
- WD Code density improvement and optimization patches
- #### RISCV GCC 10.2.0
- RISCV official 10.2.0 GCC release
- Official GDB 9.2.0
- Check gcc-hash.txt for the precise commits of toolchain build


# Supporting LLVM Releases
- #### RISCV LLVM/Clang 10.0.0
- Initial LLVM/Clang official 10.0.0 release
- #### RISCV LLVM/Clang 12.0.0
- Initial LLVM/Clang official 12.0.0 release
- ComRV support modules
- GCC Binutils-gdb 2.32.51.20190122 supporting ComRV
- Check llvm-hash.txt for the precise commits of toolchain build

# Notes and status
This repo is always under work, following are notes and status for items that is still missing or under work.
- #### 05-Oct-2020
- All EH2 demos are working only on Whisper, no fpga
- Currently, Software-Interrupts are not supported in EL2 fpga. Until it will be supported, you can use Whisper for this demo.
- Bitmanip is supported only on LLVM.

101 changes: 54 additions & 47 deletions WD-Firmware/board/nexys_a7_eh1/bsp/bsp_external_interrupts.c
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Expand Up @@ -68,19 +68,22 @@
*/
void bspInitializeGenerationRegister(u32_t uiExtInterruptPolarity)
{
u32_t uiRegisterClear;

/* For Active-High the initial value of uiRegisterClear is 0 */
if (D_PSP_EXT_INT_ACTIVE_HIGH == uiExtInterruptPolarity)
{
uiRegisterClear = 0;
}
else /*(D_PSP_EXT_INT_ACTIVE_LOW == uiExtInterruptPolarity) */
{
uiRegisterClear = 0x22; /* 00100010 */
}

M_PSP_WRITE_REGISTER_32(D_BSP_EXT_INTS_GENERATION_REGISTER, uiRegisterClear);
u32_t uiRegisterClear;

/* For Active-High the initial value of uiRegisterClear is 0 */
if (D_PSP_EXT_INT_ACTIVE_HIGH == uiExtInterruptPolarity)
{
uiRegisterClear = 0;
}
else /*(D_PSP_EXT_INT_ACTIVE_LOW == uiExtInterruptPolarity) */
{
uiRegisterClear = 0x22; /* 00100010 */
}

M_PSP_WRITE_REGISTER_32(D_BSP_EXT_INTS_GENERATION_REGISTER, uiRegisterClear);

/* Sync the output. Make sure not to progress until the write to external register is done */
M_PSP_INST_FENCEI();
}


Expand All @@ -93,34 +96,37 @@ void bspInitializeGenerationRegister(u32_t uiExtInterruptPolarity)
*/
void bspGenerateExtInterrupt(u32_t uiExtInterruptNumber, u32_t uiExtInterruptPolarity, u32_t uiExtInterruptType)
{
u32_t uiExtInterruptBitMap = 0;
u32_t uiExtInterruptBitMap = 0;

if (D_BSP_IRQ_3 == uiExtInterruptNumber)
if (D_BSP_IRQ_3 == uiExtInterruptNumber)
{
if (D_PSP_EXT_INT_ACTIVE_LOW == uiExtInterruptPolarity)
{
uiExtInterruptBitMap |= (1 << D_BSP_IRQ3_POLARITY_BIT); /* bit#1: 1 = Active Low, 0 = Active High */
}
if (D_PSP_EXT_INT_EDGE_TRIG_TYPE == uiExtInterruptType)
{
uiExtInterruptBitMap |= (1 << D_BSP_IRQ3_TYPE_BIT); /* bit#2: 1 = Edge, 0 = Level */
}
uiExtInterruptBitMap |= (1 << D_BSP_IRQ3_ACTIVATE_BIT); /* Set the trigger bit */
}
else if (D_BSP_IRQ_4 == uiExtInterruptNumber)
{
if (D_PSP_EXT_INT_ACTIVE_LOW == uiExtInterruptPolarity)
{
if (D_PSP_EXT_INT_ACTIVE_LOW == uiExtInterruptPolarity)
{
uiExtInterruptBitMap |= (1 << D_BSP_IRQ3_POLARITY_BIT); /* bit#1: 1 = Active Low, 0 = Active High */
}
if (D_PSP_EXT_INT_EDGE_TRIG_TYPE == uiExtInterruptType)
{
uiExtInterruptBitMap |= (1 << D_BSP_IRQ3_TYPE_BIT); /* bit#2: 1 = Edge, 0 = Level */
}
uiExtInterruptBitMap |= (1 << D_BSP_IRQ3_ACTIVATE_BIT); /* Set the trigger bit */
uiExtInterruptBitMap |= (1 << D_BSP_IRQ4_POLARITY_BIT); /* bit#5: 1 = Active Low, 0 = Active High */
}
else if (D_BSP_IRQ_4 == uiExtInterruptNumber)
if (D_PSP_EXT_INT_EDGE_TRIG_TYPE == uiExtInterruptType)
{
if (D_PSP_EXT_INT_ACTIVE_LOW == uiExtInterruptPolarity)
{
uiExtInterruptBitMap |= (1 << D_BSP_IRQ4_POLARITY_BIT); /* bit#5: 1 = Active Low, 0 = Active High */
}
if (D_PSP_EXT_INT_EDGE_TRIG_TYPE == uiExtInterruptType)
{
uiExtInterruptBitMap |= (1 << D_BSP_IRQ4_TYPE_BIT); /* bit#6: 1 = Edge, 0 = Level */
}
uiExtInterruptBitMap |= (1 << D_BSP_IRQ4_ACTIVATE_BIT); /* Set the trigger bit */
uiExtInterruptBitMap |= (1 << D_BSP_IRQ4_TYPE_BIT); /* bit#6: 1 = Edge, 0 = Level */
}
uiExtInterruptBitMap |= (1 << D_BSP_IRQ4_ACTIVATE_BIT); /* Set the trigger bit */
}

M_PSP_WRITE_REGISTER_32(D_BSP_EXT_INTS_GENERATION_REGISTER, uiExtInterruptBitMap);

M_PSP_WRITE_REGISTER_32(D_BSP_EXT_INTS_GENERATION_REGISTER, uiExtInterruptBitMap);
/* Sync the output. Make sure not to progress until the write to external register is done */
M_PSP_INST_FENCEI();
}

/**
Expand All @@ -131,18 +137,19 @@ void bspGenerateExtInterrupt(u32_t uiExtInterruptNumber, u32_t uiExtInterruptPol
*/
void bspClearExtInterrupt(u32_t uiExtInterruptNumber)
{
u32_t uiExtInterruptBitMap = M_PSP_READ_REGISTER_32(D_BSP_EXT_INTS_GENERATION_REGISTER);
u32_t uiExtInterruptBitMap = M_PSP_READ_REGISTER_32(D_BSP_EXT_INTS_GENERATION_REGISTER);

if (D_BSP_IRQ_3 == uiExtInterruptNumber)
{
uiExtInterruptBitMap &= ~(1 << D_BSP_IRQ3_ACTIVATE_BIT);
}
else if (D_BSP_IRQ_4 == uiExtInterruptNumber)
{
uiExtInterruptBitMap &= ~(1 << D_BSP_IRQ4_ACTIVATE_BIT);
}

M_PSP_WRITE_REGISTER_32(D_BSP_EXT_INTS_GENERATION_REGISTER, uiExtInterruptBitMap );
}
if (D_BSP_IRQ_3 == uiExtInterruptNumber)
{
uiExtInterruptBitMap &= ~(1 << D_BSP_IRQ3_ACTIVATE_BIT);
}
else if (D_BSP_IRQ_4 == uiExtInterruptNumber)
{
uiExtInterruptBitMap &= ~(1 << D_BSP_IRQ4_ACTIVATE_BIT);
}

M_PSP_WRITE_REGISTER_32(D_BSP_EXT_INTS_GENERATION_REGISTER, uiExtInterruptBitMap );

/* Sync the output. Make sure not to progress until the write to external register is done */
M_PSP_INST_FENCEI();
}
9 changes: 6 additions & 3 deletions WD-Firmware/board/nexys_a7_eh1/bsp/bsp_printf.c
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Expand Up @@ -20,7 +20,7 @@


#include <stdarg.h>
#include "psp_types.h"
#include "psp_api.h"
#include "bsp_mem_map.h"
#include "bsp_printf.h"

Expand Down Expand Up @@ -135,14 +135,17 @@ int printUartPutchar(char ch)
*/
void uartInit(void)
{
u32_t uiTempDiv;

/* SET LSR to be 1's so Whisper will be happy that ch is ready */
M_UART_WR_REG_LSR(0xff);

/* Set DLAB bit in LCR */
M_UART_WR_REG_LCR(D_UART_DLAB_BIT);

/* Set divisor regs devisor = 27: clock_freq/baud_rate*16 -->> clock = 50MHz, baud=115200*/
M_UART_WR_REG_BRDL((D_CLOCK_RATE/D_BAUD_RATE)/16);
/* Set divisor regs divisor = 27: clock_freq/baud_rate/16 -->> EH1 clock = 50MHz, EH1 URAT baud-rate = 115200 */
uiTempDiv = D_CLOCK_RATE / D_BAUD_RATE;
M_UART_WR_REG_BRDL(M_PSP_DIV_AND_ROUND_FLOOR(uiTempDiv, 16));

/* 8 data bits, 1 stop bit, no parity, clear DLAB */
M_UART_WR_REG_LCR((D_UART_LCR_CS8 | D_UART_LCR_1_STB | D_UART_LCR_PDIS));
Expand Down
13 changes: 13 additions & 0 deletions WD-Firmware/board/nexys_a7_eh1/bsp/bsp_timer.c
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Original file line number Diff line number Diff line change
Expand Up @@ -100,6 +100,10 @@ void bspRoutTimer(eTimerRouting_t eTimerRouting)

/* Set the routing selection */
M_PSP_SET_REGISTER_32(D_BSP_EXT_INTS_GENERATION_REGISTER, uiRoutingValue);

/* Sync the output. Make sure not to progress until the write to external register is done */
M_PSP_INST_FENCEI();

}

/**
Expand All @@ -113,6 +117,9 @@ void bspSetTimerDurationMsec(u32_t uiTimerDurationMsec)
u32_t uiTimerSet = M_MSEC_DURATION_TO_CYCLES(uiTimerDurationMsec);

M_PSP_WRITE_REGISTER_32(D_BSP_TIMER_DURATION_SETUP_REGISTER, uiTimerSet);

/* Sync the output. Make sure not to progress until the write to external register is done */
M_PSP_INST_FENCEI();
}

/**
Expand All @@ -122,6 +129,9 @@ void bspSetTimerDurationMsec(u32_t uiTimerDurationMsec)
void bspStartTimer(void)
{
M_PSP_WRITE_REGISTER_32(D_BSP_TIMER_ACTIVATION_REGISTER, D_TIMER_START);

/* Sync the output. Make sure not to progress until the write to external register is done */
M_PSP_INST_FENCEI();
}

/**
Expand All @@ -131,5 +141,8 @@ void bspStartTimer(void)
void bspStopTimer(void)
{
M_PSP_WRITE_REGISTER_32(D_BSP_TIMER_ACTIVATION_REGISTER, D_TIMER_STOP);

/* Sync the output. Make sure not to progress until the write to external register is done */
M_PSP_INST_FENCEI();
}

4 changes: 0 additions & 4 deletions WD-Firmware/board/nexys_a7_eh1/bsp/bsp_version.c
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Original file line number Diff line number Diff line change
Expand Up @@ -25,7 +25,6 @@
/**
* include files
*/
#include "psp_types.h"
#include "psp_api.h"
#include "bsp_mem_map.h"
#include "bsp_version.h"
Expand All @@ -34,9 +33,6 @@
* definitions
*/

/* The stack used by interrupt service routines */


/**
* macros
*/
Expand Down
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