Fix formatting

Severson-Group · Dec 21, 2023 · 39f0fa9 · 39f0fa9
1 parent 4ed11c4
commit 39f0fa9
Show file tree

Hide file tree

Showing 3 changed files with 21 additions and 25 deletions.
diff --git a/sdk/app_cpu1/common/drv/timing_manager.c b/sdk/app_cpu1/common/drv/timing_manager.c
@@ -42,7 +42,7 @@ uint32_t interrupt_system_init()
 
     // Set priority of IRQ_F2P[0:0] to 0xA0 and a trigger for a rising edge 0x3
     XScuGic_SetPriorityTriggerType(intc_instance_ptr, INTC_INTERRUPT_ID_0, ISR0_PRIORITY, ISR_RISING_EDGE);
-    
+
     // Connect ISR0 to the interrupt controller
     result = XScuGic_Connect(intc_instance_ptr, INTC_INTERRUPT_ID_0, (Xil_ExceptionHandler) isr0, (void *) &intc);
     if (result != XST_SUCCESS) {
@@ -103,7 +103,7 @@ void timing_manager_init()
 
     // Initialize the stats
     for (int i = 0; i < NUM_SENSORS; i++) {
-    	statistics_init(sensor_stats[i]);
+        statistics_init(sensor_stats[i]);
     }
 
     // Disable interrupt 1 - currently not needed
@@ -169,10 +169,10 @@ void timing_manager_select_sensors(uint8_t enable_bits)
  */
 void timing_manager_enable_eddy_1()
 {
-	// Get the current address for the target config register (slv_reg2)
-	uint32_t config_reg_addr = TIMING_MANAGER_BASE_ADDR + (1 * sizeof(uint32_t));
-	// Assign the  to the config register
-	Xil_Out32(config_reg_addr, (Xil_In32(config_reg_addr) | 0x01));
+    // Get the current address for the target config register (slv_reg2)
+    uint32_t config_reg_addr = TIMING_MANAGER_BASE_ADDR + (1 * sizeof(uint32_t));
+    // Assign the  to the config register
+    Xil_Out32(config_reg_addr, (Xil_In32(config_reg_addr) | 0x01));
 }
 
 /*

diff --git a/sdk/app_cpu1/common/drv/timing_manager.h b/sdk/app_cpu1/common/drv/timing_manager.h
@@ -51,6 +51,6 @@ void isr0(void *intc_inst_ptr);
 void isr1(void *intc_inst_ptr);
 uint16_t timing_manager_get_time_per_sensor(sensor_t sensor);
 void timing_manager_sensor_stats();
-statistics_t* timing_manager_get_stats_per_sensor(sensor_t sensor);
+statistics_t *timing_manager_get_stats_per_sensor(sensor_t sensor);
 
 #endif // TIMING_MANAGER_H
diff --git a/sdk/app_cpu1/common/sys/cmd/cmd_hw.c b/sdk/app_cpu1/common/sys/cmd/cmd_hw.c
@@ -208,21 +208,17 @@ int cmd_hw(int argc, char **argv)
 #elif USER_CONFIG_HARDWARE_TARGET == AMDC_REV_E
         if (port == 1) {
             base_addr = EDDY_CURRENT_SENSOR_1_BASE_ADDR;
-        	timing_manager_enable_eddy_1();
-        }
-        else if (port == 2) {
-        	base_addr = EDDY_CURRENT_SENSOR_2_BASE_ADDR;
-        	timing_manager_enable_eddy_2();
-        }
-        else if (port == 3) {
-        	base_addr = EDDY_CURRENT_SENSOR_3_BASE_ADDR;
-        	timing_manager_enable_eddy_3();
-        }
-        else if (port == 4) {
-        	base_addr = EDDY_CURRENT_SENSOR_4_BASE_ADDR;
-        	timing_manager_enable_eddy_4();
-        }
-        else
+            timing_manager_enable_eddy_1();
+        } else if (port == 2) {
+            base_addr = EDDY_CURRENT_SENSOR_2_BASE_ADDR;
+            timing_manager_enable_eddy_2();
+        } else if (port == 3) {
+            base_addr = EDDY_CURRENT_SENSOR_3_BASE_ADDR;
+            timing_manager_enable_eddy_3();
+        } else if (port == 4) {
+            base_addr = EDDY_CURRENT_SENSOR_4_BASE_ADDR;
+            timing_manager_enable_eddy_4();
+        } else
             return CMD_INVALID_ARGUMENTS;
 #endif
 
@@ -231,11 +227,11 @@ int cmd_hw(int argc, char **argv)
             timing_manager_trigger_on_pwm_clear();
 
             if (STREQ("HIGH", argv[4]))
-            	timing_manager_trigger_on_pwm_high();
+                timing_manager_trigger_on_pwm_high();
             else if (STREQ("LOW", argv[4]))
-            	timing_manager_trigger_on_pwm_low();
+                timing_manager_trigger_on_pwm_low();
             else if (STREQ("BOTH", argv[4]))
-            	timing_manager_trigger_on_pwm_both();
+                timing_manager_trigger_on_pwm_both();
             else
                 return CMD_INVALID_ARGUMENTS;