updated indentation

Severson-Group · Dec 6, 2024 · f6a42d5 · f6a42d5
1 parent 17eda02
commit f6a42d5
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Showing 2 changed files with 30 additions and 30 deletions.
diff --git a/sdk/app_cpu1/common/drv/pwm.h b/sdk/app_cpu1/common/drv/pwm.h
@@ -61,9 +61,9 @@ typedef enum {
 } pwm_channel_e;
 
 typedef enum {
-	PWM_LATCH_MODE_TIMING_MANAGER = 0, // Update duty ratios at next timing manager trigger (default)
-	PWM_LATCH_MODE_PWM, // Update duty ratios at next PWM carrier peak/valley
-	PWM_LATCH_MODE_IMMEDIATE // Update duty ratios immediately (next FPGA clock rise)
+    PWM_LATCH_MODE_TIMING_MANAGER = 0, // Update duty ratios at next timing manager trigger (default)
+    PWM_LATCH_MODE_PWM, // Update duty ratios at next PWM carrier peak/valley
+    PWM_LATCH_MODE_IMMEDIATE // Update duty ratios immediately (next FPGA clock rise)
 } pwm_latch_mode;
 
 static inline bool pwm_is_valid_channel(pwm_channel_e channel)

diff --git a/sdk/app_cpu1/common/drv/timing_manager.c b/sdk/app_cpu1/common/drv/timing_manager.c
@@ -445,33 +445,33 @@ double timing_manager_get_time_per_sensor(sensor_e sensor)
  * Get the time since the sensor value was gathered for the requested sensor, in nanoseconds
  */
 double timing_manager_get_time_since_sensor_poll(sensor_e sensor) {
-	uint32_t clock_cycles = Xil_In32(TM_BASE_ADDR + TM_INT_TIME_REG_OFFSET);
-	double time = 0;
-
-	if (sensor == ADC)
-		clock_cycles -= (Xil_In32(TM_BASE_ADDR + TM_ADC_ENC_TIME_REG_OFFSET)) & TM_LOWER_16_MASK;
-	else if (sensor == ENCODER)
-		clock_cycles -= (Xil_In32(TM_BASE_ADDR + TM_ADC_ENC_TIME_REG_OFFSET)) >> TM_UPPER_16_SHIFT;
-	else if (sensor == AMDS_1)
-		clock_cycles -= (Xil_In32(TM_BASE_ADDR + TM_AMDS_01_TIME_REG_OFFSET)) & TM_LOWER_16_MASK;
-	else if (sensor == AMDS_2)
-		clock_cycles -= (Xil_In32(TM_BASE_ADDR + TM_AMDS_01_TIME_REG_OFFSET)) >> TM_UPPER_16_SHIFT;
-	else if (sensor == AMDS_3)
-		clock_cycles -= (Xil_In32(TM_BASE_ADDR + TM_AMDS_23_TIME_REG_OFFSET)) & TM_LOWER_16_MASK;
-	else if (sensor == AMDS_4)
-		clock_cycles -= (Xil_In32(TM_BASE_ADDR + TM_AMDS_23_TIME_REG_OFFSET)) >> TM_UPPER_16_SHIFT;
-	else if (sensor == EDDY_1)
-		clock_cycles -= (Xil_In32(TM_BASE_ADDR + TM_EDDY_01_TIME_REG_OFFSET)) & TM_LOWER_16_MASK;
-	else if (sensor == EDDY_2)
-		clock_cycles -= (Xil_In32(TM_BASE_ADDR + TM_EDDY_01_TIME_REG_OFFSET)) >> TM_UPPER_16_SHIFT;
-	else if (sensor == EDDY_3)
-		clock_cycles -= (Xil_In32(TM_BASE_ADDR + TM_EDDY_23_TIME_REG_OFFSET)) & TM_LOWER_16_MASK;
-	else if (sensor == EDDY_4)
-		clock_cycles -= (Xil_In32(TM_BASE_ADDR + TM_EDDY_23_TIME_REG_OFFSET)) >> TM_UPPER_16_SHIFT;
-
-	// Convert clock cycles to time in us using 200 MHz FPGA clock frequency
-	time = (double) clock_cycles / CLOCK_FPGA_CLK_FREQ_MHZ;
-	return time;
+    uint32_t clock_cycles = Xil_In32(TM_BASE_ADDR + TM_INT_TIME_REG_OFFSET);
+    double time = 0;
+
+    if (sensor == ADC)
+        clock_cycles -= (Xil_In32(TM_BASE_ADDR + TM_ADC_ENC_TIME_REG_OFFSET)) & TM_LOWER_16_MASK;
+    else if (sensor == ENCODER)
+        clock_cycles -= (Xil_In32(TM_BASE_ADDR + TM_ADC_ENC_TIME_REG_OFFSET)) >> TM_UPPER_16_SHIFT;
+    else if (sensor == AMDS_1)
+        clock_cycles -= (Xil_In32(TM_BASE_ADDR + TM_AMDS_01_TIME_REG_OFFSET)) & TM_LOWER_16_MASK;
+    else if (sensor == AMDS_2)
+        clock_cycles -= (Xil_In32(TM_BASE_ADDR + TM_AMDS_01_TIME_REG_OFFSET)) >> TM_UPPER_16_SHIFT;
+    else if (sensor == AMDS_3)
+        clock_cycles -= (Xil_In32(TM_BASE_ADDR + TM_AMDS_23_TIME_REG_OFFSET)) & TM_LOWER_16_MASK;
+    else if (sensor == AMDS_4)
+        clock_cycles -= (Xil_In32(TM_BASE_ADDR + TM_AMDS_23_TIME_REG_OFFSET)) >> TM_UPPER_16_SHIFT;
+    else if (sensor == EDDY_1)
+        clock_cycles -= (Xil_In32(TM_BASE_ADDR + TM_EDDY_01_TIME_REG_OFFSET)) & TM_LOWER_16_MASK;
+    else if (sensor == EDDY_2)
+        clock_cycles -= (Xil_In32(TM_BASE_ADDR + TM_EDDY_01_TIME_REG_OFFSET)) >> TM_UPPER_16_SHIFT;
+    else if (sensor == EDDY_3)
+        clock_cycles -= (Xil_In32(TM_BASE_ADDR + TM_EDDY_23_TIME_REG_OFFSET)) & TM_LOWER_16_MASK;
+    else if (sensor == EDDY_4)
+        clock_cycles -= (Xil_In32(TM_BASE_ADDR + TM_EDDY_23_TIME_REG_OFFSET)) >> TM_UPPER_16_SHIFT;
+
+    // Convert clock cycles to time in us using 200 MHz FPGA clock frequency
+    time = (double) clock_cycles / CLOCK_FPGA_CLK_FREQ_MHZ;
+    return time;
 }
 
 /*