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13,025 changes: 13,025 additions & 0 deletions cores/axis/MSE/MSE.sim/sim_1/behav/xsim/vivado_pid1617.str

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37 changes: 30 additions & 7 deletions cores/axis/MSE/MSE.srcs/component.xml
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Expand Up @@ -140,7 +140,7 @@
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Expand All @@ -156,7 +156,7 @@
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Expand Down Expand Up @@ -403,7 +403,7 @@
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Expand Down Expand Up @@ -501,8 +501,8 @@
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Expand Down Expand Up @@ -540,12 +540,35 @@
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Expand Down
21 changes: 12 additions & 9 deletions cores/axis/MSE/MSE.srcs/sources_1/new/MSE.v
Original file line number Diff line number Diff line change
Expand Up @@ -26,12 +26,13 @@ module MSE #
wire [PARAM_WIDTH - 1 : 0] params [PARAMETERS - 1 : 0];
wire [MAT_WIDTH - 1 : 0] matrix [PARAMETERS - 1 : 0][PARAMETERS - 1 : 0];
wire [AXIS_TDATA_WIDTH - 1 : 0] delay_out;
reg [5 * AXIS_TDATA_WIDTH - 1 : 0] int_inv_cov_mat [$clog2(PARAMETERS) * 2 + 1 : 0][PARAMETERS - 1 : 0][PARAMETERS - 1 : 0]; //Overallocation will be optimized out during synthesis
reg [OUTPUT_WIDTH + 32 - 1 : 0] int_inv_cov_mat [$clog2(PARAMETERS) * 2 + 1 : 0][PARAMETERS - 1 : 0][PARAMETERS - 1 : 0]; //Overallocation will be optimized out during synthesis
reg [BUFFER_LENGTH - 1 : 0] delay [$clog2(DELAYS) : 0][DELAYS - 1 : 0];
reg [BUFFER_LENGTH - 1 : 0] wptr = 0;
reg [2 * AXIS_TDATA_WIDTH - 1 : 0] sum;
reg [2 * AXIS_TDATA_WIDTH - 1 : 0] ysq;
reg [2 * AXIS_TDATA_WIDTH - 1 : 0] delaysq;
reg [OUTPUT_WIDTH - 1 : 0] sum;
reg [OUTPUT_WIDTH - 1 : 0] ysq;
reg [OUTPUT_WIDTH - 1 : 0] delaysq;
reg [OUTPUT_WIDTH - 1 : 0] diff;
genvar i;
genvar j;
genvar k;
Expand All @@ -41,13 +42,15 @@ module MSE #
always @ (posedge aclk) begin
wptr <= wptr + 1;
if (aresetn) begin
ysq <= s_axis_data_tdata*s_axis_data_tdata;
delaysq <= delay_out*delay_out;
sum <= sum + ysq - delaysq;
ysq <= s_axis_data_tdata * s_axis_data_tdata;
delaysq <= delay_out * delay_out;
diff <= ysq - delaysq;
sum <= sum + diff;
end
else begin
sum <= 0;
ysq <= 0;
diff <= 0;
delaysq <= 0;
end
end
Expand Down Expand Up @@ -94,7 +97,7 @@ module MSE #
delay[0][i] = delay_flat[(i + 1) * 16 - 1 : i * 16];
endgenerate

//Multiply and contract lower trangular matrix
//Multiply and contract symmetric matrix using lower trangular packing
//Honestly it would be faster to just rewrite this than attempting to understand this code. Just don't bother...
generate
for (i = 0; i < PARAMETERS; i = i + 1) begin
Expand Down Expand Up @@ -146,6 +149,6 @@ module MSE #
endgenerate

//assign m_axis_tdata = int_inv_cov_mat[2 * $clog2(PARAMETERS) + 1][0][0];
assign m_axis_tdata = sum - int_inv_cov_mat[2 * $clog2(PARAMETERS) + 1][0][0];
assign m_axis_tdata = sum - int_inv_cov_mat[2 * $clog2(PARAMETERS) + 1][0][0] >> 32;

endmodule
Original file line number Diff line number Diff line change
Expand Up @@ -116,7 +116,7 @@
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Expand All @@ -132,7 +132,7 @@
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Expand Down Expand Up @@ -345,7 +345,7 @@
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Expand Down Expand Up @@ -445,8 +445,8 @@
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Expand Down Expand Up @@ -710,12 +710,38 @@
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Expand Down
Original file line number Diff line number Diff line change
Expand Up @@ -30,6 +30,7 @@ module fir_poly #

genvar i;
genvar j;
genvar k;

//Reformatting to arrays
generate
Expand Down Expand Up @@ -57,7 +58,7 @@ module fir_poly #
.enb (1'b1),
.wea (1'b1),
.addra (wptr),
.addrb (wptr - delay[i] + 1'b1),
.addrb (wptr - delay[i]),
.dia (delay_out[i - 1]),
.dob (delay_out[i])
);
Expand All @@ -68,8 +69,8 @@ module fir_poly #
generate
for (i = 0; i < PIECES; i = i + 1) begin : piece
for (j = 0; j < ORDER + 1; j = j + 1) begin : order
wire [OUTPUT_WIDTH - 1 : 0] acc_out;
wire [OUTPUT_WIDTH - 1 : 0] macc_out;
wire [OUTPUT_WIDTH + (j + 1) * BUFFER_LENGTH - 1 : 0] acc_out;
if (j == 0) begin
reg [OUTPUT_WIDTH - 1 : 0] r_macc_out_A;
reg [OUTPUT_WIDTH - 1 : 0] r_macc_out_B;
Expand All @@ -89,7 +90,7 @@ module fir_poly #
r_macc_out_C <= r_macc_out_B;
r_macc_out_D <= r_macc_out_C;
end
end
end
end
end
endgenerate
Expand All @@ -98,10 +99,11 @@ module fir_poly #
for (i = 0; i < PIECES; i = i + 1) begin : macc_piece
for (j = 1; j < ORDER + 1; j = j + 1) begin : macc_order
macc_sum # (
.I_ACC_WIDTH (OUTPUT_WIDTH),
.O_ACC_WIDTH (OUTPUT_WIDTH),
.I_ACC_WIDTH (OUTPUT_WIDTH + j * BUFFER_LENGTH),
.O_ACC_WIDTH (OUTPUT_WIDTH + (j + 1) * BUFFER_LENGTH),
.I_MACC_WIDTH (OUTPUT_WIDTH),
.COEF_WIDTH (COEF_WIDTH)
.COEF_WIDTH (COEF_WIDTH),
.SHIFT (j * BUFFER_LENGTH)
) mac (
.clk (aclk),
.aresetn (aresetn),
Expand Down
Original file line number Diff line number Diff line change
Expand Up @@ -3,7 +3,8 @@ module macc_sum #
parameter integer I_ACC_WIDTH = 32,
parameter integer O_ACC_WIDTH = 32,
parameter integer I_MACC_WIDTH = 32,
parameter integer COEF_WIDTH = 32
parameter integer COEF_WIDTH = 32,
parameter integer SHIFT = 0
)
(
input clk,
Expand Down Expand Up @@ -39,7 +40,7 @@ module macc_sum #
acc_out <= accu;
accu <= $signed(accu) + $signed(acc_in);
macc_del <= macc_in;
macc_mult_A <= $signed(accu) * $signed(coef);
macc_mult_A <= $signed($signed(accu) >> SHIFT) * $signed(coef);
macc_mult_B <= macc_mult_A;
macc_mult_C <= macc_mult_B;
macc_mult_D <= macc_mult_C;
Expand Down
16 changes: 8 additions & 8 deletions cores/axis/Poly_filter/fir_poly_tb.v
Original file line number Diff line number Diff line change
Expand Up @@ -3,12 +3,12 @@ module tb();
reg clk;
reg rst;
reg [16 - 1 : 0] data;
reg [32 * (3 + 1) * 2 - 1 : 0] coef;
reg [32 * (4 + 1) * 2 - 1 : 0] coef;
reg [16 * (2 - 1) - 1 : 0] delay;
wire [16 - 1 : 0] out;
wire signed [32 - 1 : 0] out;
wire valid;
integer cnt = 0;
fir_poly //# (16, 4, 16, 3, 2, 16)
fir_poly #(16, 4, 16, 4, 2, 32)
fir (
.aclk(clk),
.aresetn(rst),
Expand All @@ -32,16 +32,16 @@ module tb();
#1
rst = 0;
data = 0;
coef = {-32'd0,-32'd0,-32'd0,-32'd0,
32'h100, 32'd16, 32'd1, 32'd0};
delay = 4'd5;
coef = {-32'd0,-32'd768,-32'd100,-32'd10, -32'd0,
32'd0, 32'd768, 32'd0, 32'd0, 32'd0};
delay = 4'd10;
#40
rst = 1;
#4
data = 1;
data = 1<<14;
#2
data = 0;
#90 $finish;
#100 $finish;
end

endmodule
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