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ref(riscv): centralize check for sstc extension
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Signed-off-by: Jose Martins <[email protected]>
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josecm committed Nov 17, 2023
1 parent b9a7437 commit 164c13f
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Showing 2 changed files with 15 additions and 3 deletions.
3 changes: 0 additions & 3 deletions src/arch/riscv/vm.c
Original file line number Diff line number Diff line change
Expand Up @@ -44,9 +44,6 @@ void vcpu_arch_reset(struct vcpu* vcpu, vaddr_t entry)

if (CPU_HAS_EXTENSION(CPU_EXT_SSTC)) {
CSRW(CSR_STIMECMP, -1);
CSRS(CSR_HENVCFG, HENVCFG_STCE);
} else {
CSRC(CSR_HENVCFG, HENVCFG_STCE);
}
CSRW(CSR_HCOUNTEREN, HCOUNTEREN_TM);
CSRW(CSR_HTIMEDELTA, 0);
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15 changes: 15 additions & 0 deletions src/arch/riscv/vmm.c
Original file line number Diff line number Diff line change
Expand Up @@ -21,6 +21,21 @@ void vmm_arch_init()
CSRW(CSR_HIDELEG, HIDELEG_VSSI | HIDELEG_VSTI | HIDELEG_VSEI);
CSRW(CSR_HEDELEG, HEDELEG_ECU | HEDELEG_IPF | HEDELEG_LPF | HEDELEG_SPF);

/**
* Enable and sanity check presence of Sstc extension if the hypervisor was
* configured to use it (via the CPU_EXT_SSTC macro). Otherwise, make sure
* it is disabled.
*/
if (CPU_HAS_EXTENSION(CPU_EXT_SSTC)) {
CSRS(CSR_HENVCFG, HENVCFG_STCE);
bool sttc_present = (CSRR(CSR_HENVCFG) & HENVCFG_STCE) != 0;
if (cpu_is_master() && !sttc_present) {
ERROR("Platform configured to use Sstc extension, but extension not present.");
}
} else {
CSRC(CSR_HENVCFG, HENVCFG_STCE);
}

/**
* TODO: consider delegating other exceptions e.g. breakpoint or ins misaligned
*/
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