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Synplify Flow Integration #553

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408d7af
enable abc9 for k6n10
tpagarani Feb 18, 2023
c72a4fc
qlf_k6n10f/cells_sim.v
May 8, 2023
c87c6f3
add correct delays
May 8, 2023
bcaf51a
fix carry chain issue
May 16, 2023
f7bd1e6
add carry attribute to keep carry chain
May 18, 2023
5669bd7
fix crash issues
Jun 1, 2023
b411f22
Merge branch 'main' into abc9
coolbreeze413 Jun 10, 2023
74dd252
memory libmap support, modified instantiation macros
rakeshm75 Jun 14, 2023
955074d
modified bram map, bram final map amd synth_quicklogic files
rakeshm75 Jun 19, 2023
a5c00a3
Merge pull request #3 from QuickLogic-Corp/memory_libmap
rakeshm75 Jun 19, 2023
57b26d8
added wire definition in cell_sim.v file to avoid compilation errors
rakeshm75 Jun 29, 2023
98ea3c2
Merge pull request #4 from QuickLogic-Corp/cell_sim
coolbreeze413 Jun 29, 2023
a8914e1
modified lipmap brams txt to change the init & removed the frac_lut6 …
rakeshm75 Jul 17, 2023
7482ed9
Add generated files(pmgen.py, bram_types_sim.v) to gitignore
coolbreeze413 Jul 19, 2023
e97f8b3
Merge pull request #5 from QuickLogic-Corp/bram_init
rakeshm75 Jul 20, 2023
93bfca7
ram cost reduced to 65 from 257 in libmap_brams.txt
rakeshm75 Jul 20, 2023
18aba5f
Merge pull request #6 from QuickLogic-Corp/memory_libmap_fix
rakeshm75 Jul 20, 2023
774485b
add no_opt support
Sep 12, 2023
5548780
Minor formatting changes in synth_quicklogic.cc
coolbreeze413 Sep 12, 2023
befbcd1
added support for multiple architectures
rakeshm75 Feb 12, 2024
bc017e7
added the updated cell_sim.v file
rakeshm75 Feb 19, 2024
7efcbcf
updated the DSP map file to avoid x on the inputs reset and clock
rakeshm75 Feb 20, 2024
d731711
reverted the cells_sim.v, lipmap_brams_map.v to the default tsmc devi…
rakeshm75 Feb 28, 2024
df029b0
rectified the model for FFs with set
rakeshm75 Mar 22, 2024
2b9146c
Merge pull request #13 from QuickLogic-Corp/rakesh_dev
rakeshm75 Mar 22, 2024
5977bbd
added lut6 behavior into cells_sim to pass synth stage
saaramahmoudi Mar 28, 2024
362539d
Merge branch 'main' into support_blackbox_lut
coolbreeze413 May 10, 2024
9fdedd2
delays for abc9_box was missing for LUT6 blackbox modules, which caus…
saaramahmoudi May 14, 2024
92865b1
ram initialization support
rakeshm75 May 22, 2024
f612a08
Merge pull request #16 from QuickLogic-Corp/ram_init
coolbreeze413 May 23, 2024
74b9d75
rectified sram1024x18.v construct
rakeshm75 May 23, 2024
bd1d16e
changed the shifter register primitive name
rakeshm75 May 31, 2024
ed85bca
temporary fix for assertion failure with DSP packing
rakeshm75 Aug 13, 2024
a49ba3e
Merge pull request #19 from QuickLogic-Corp/dsp_packing_fix
rakeshm75 Aug 13, 2024
ddefc65
modified the RAM Map with respect to addr2, wen2, ren2 for the proper…
rakeshm75 Aug 27, 2024
823d3ef
fix the brams_sim.v file compilation issue
rakeshm75 Aug 27, 2024
fd3faa4
Changed pass, added the synplify map file, and edited makefile
Oct 7, 2024
65ce689
Removed the Synplify flag foor DSP
Oct 18, 2024
c4a8e65
formatting issue resolved
Oct 19, 2024
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added the updated cell_sim.v file
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rakeshm75 committed Feb 19, 2024

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commit bc017e7ebc31fd84f7d0a5a830698414f811e413
112 changes: 110 additions & 2 deletions ql-qlf-plugin/qlf_k6n10f/cells_sim.v
Original file line number Diff line number Diff line change
@@ -184,6 +184,115 @@ module dffn(

endmodule

(* abc9_flop, lib_whitebox *)
module dffre(
output reg Q,
input wire D,
(* clkbuf_sink *)
input wire C,
input wire E,
input wire R
);
initial Q <= 1'b0;

always @(posedge C or negedge R)
if (!R)
Q <= 1'b0;
else if (E)
Q <= D;

specify
(posedge C => (Q +: D)) = 280;
(R => Q) = 0;
$setuphold(posedge C, D, 56, 0);
$setuphold(posedge C, E, 32, 0);
$setuphold(posedge C, R, 0, 0);
$recrem(posedge R, posedge C, 0, 0);
endspecify

endmodule


(* abc9_flop, lib_whitebox *)
module dffnre(
output reg Q,
input wire D,
(* clkbuf_sink *)
input wire C,
input wire E,
input wire R
);
initial Q <= 1'b0;

always @(negedge C or negedge R)
if (!R)
Q <= 1'b0;
else if (E)
Q <= D;

specify
(negedge C => (Q +: D)) = 280;
(R => Q) = 0;
$setuphold(negedge C, D, 56, 0);
$setuphold(negedge C, E, 32, 0);
$setuphold(negedge C, R, 0, 0);
$recrem(posedge R, negedge C, 0, 0);
endspecify

endmodule

(* abc9_flop, lib_whitebox *)
module sdffre(
output reg Q,
input wire D,
(* clkbuf_sink *)
input wire C,
input wire E,
input wire R
);
initial Q <= 1'b0;

always @(posedge C)
if (!R)
Q <= 1'b0;
else if (E)
Q <= D;

specify
(posedge C => (Q +: D)) = 280;
$setuphold(posedge C, D, 56, 0);
$setuphold(posedge C, R, 32, 0);
$setuphold(posedge C, E, 0, 0);
endspecify

endmodule

(* abc9_flop, lib_whitebox *)
module sdffnre(
output reg Q,
input wire D,
(* clkbuf_sink *)
input wire C,
input wire E,
input wire R
);
initial Q <= 1'b0;

always @(negedge C)
if (!R)
Q <= 1'b0;
else if (E)
Q <= D;

specify
(negedge C => (Q +: D)) = 280;
$setuphold(negedge C, D, 56, 0);
$setuphold(negedge C, R, 32, 0);
$setuphold(negedge C, E, 0, 0);
endspecify

endmodule

(* abc9_flop, lib_whitebox *)
module dffsre(
output reg Q,
@@ -372,5 +481,4 @@ module latchnsre (
$setuphold(negedge G, S, 0, 0);
endspecify

endmodule

endmodule