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remove GeneratorCall test
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uduse committed Nov 24, 2023
1 parent 4cb4f00 commit 094d6c5
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Showing 2 changed files with 1 addition and 32 deletions.
2 changes: 1 addition & 1 deletion hdl21/flatten.py
Original file line number Diff line number Diff line change
Expand Up @@ -89,7 +89,7 @@ def _find_signal_or_port(m: h.Module, name: str) -> h.Signal:
def is_flat(m: Union[h.Instance, h.Instantiable]) -> bool:
if isinstance(m, h.Instance):
return is_flat(m.of)
elif isinstance(m, (h.PrimitiveCall, h.GeneratorCall, h.ExternalModuleCall)):
elif isinstance(m, (h.PrimitiveCall, h.ExternalModuleCall)):
return True
elif isinstance(m, h.Module):
insts = m.instances.values()
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31 changes: 0 additions & 31 deletions hdl21/tests/test_flatten.py
Original file line number Diff line number Diff line change
Expand Up @@ -149,34 +149,3 @@ class M:

flattened = flatten(M)


def test_flatten_generator():
"""Flatten a Generator
(And it has Concat too! Kinda. But not by the point flattening happens)."""

@h.paramclass
class Params:
how_many = h.Param(dtype=int, default=5, desc="How many inverters you want?")

@h.generator
def Gen(params: Params) -> h.Module:
if params.how_many < 2:
raise ValueError

@h.module
class M:
vdd, vss, vin, vout = h.Ports(4)
internal_signal = h.Signal(width=params.how_many - 1)
# Array of `how_many` series-connected inverters
invs = params.how_many * Inverter(
vdd=vdd,
vss=vss,
vin=h.Concat(vin, internal_signal),
vout=h.Concat(internal_signal, vout),
)

return M

gen5 = Gen(how_many=5)
assert not is_flat(gen5)
flattened = flatten(gen5)

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