Additional unisims to enable simulation in verilator of BRAMS.

FD.v

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+
+`timescale  1 ps / 1 ps
+
+
+module FD (Q, C, D);
+
+    parameter INIT = 1'b0;
+
+    output Q;
+
+    input  C, D;
+
+    wire Q;
+    reg q_out;
+
+    initial q_out = INIT;
+
+    always @(posedge C)
+       q_out <=  D;
+
+    assign Q = q_out;
+
+endmodule

FDC.v

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+`timescale  1 ps / 1 ps
+
+
+module FDC (Q, C, CLR, D);
+
+    parameter INIT = 1'b0;
+
+    output Q;
+
+    input  C, CLR, D;
+
+    wire Q;
+    reg q_out;
+
+    initial q_out = INIT;
+
+
+    always @(posedge C or posedge CLR)
+       if (CLR) 
+             q_out <= 0;
+       else
+	         q_out <= D;
+
+    assign Q = q_out;
+
+endmodule

FDE.v

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+`timescale  1 ps / 1 ps
+
+module FDE (Q, C, CE, D);
+
+    parameter INIT = 1'b0;
+
+    output Q;
+
+    input  C, CE, D;
+
+    wire Q;
+    reg q_out;
+
+    initial q_out = INIT;
+
+    assign Q = q_out;
+
+
+    always @(posedge C)
+	    if (CE)
+	       q_out <=  D;
+
+endmodule

FDP.v

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+
+`timescale  1 ps / 1 ps
+
+
+module FDP (Q, C, D, PRE);
+
+    parameter INIT = 1'b1;
+
+    output Q;
+
+    input  C, D, PRE;
+
+    wire Q;
+    reg q_out;
+
+    initial q_out = INIT;
+
+    assign Q = q_out;
+
+    always @(posedge C or posedge PRE)
+        if (PRE)
+             q_out <= 1;
+        else
+	         q_out <= D;
+
+endmodule

FDR.v

@@ -0,0 +1,26 @@
+
+`timescale  1 ps / 1 ps
+
+
+module FDR (Q, C, D, R);
+
+    parameter INIT = 1'b0;
+
+    output Q;
+
+    input  C, D, R;
+
+    wire Q;
+    reg q_out;
+
+    initial q_out = INIT;
+
+    assign Q = q_out;
+
+    always @(posedge C )
+         if (R)
+	    q_out <=  0;
+         else
+	    q_out <=  D;
+
+endmodule

FDRE.v

@@ -0,0 +1,26 @@
+
+`timescale  1 ps / 1 ps
+
+
+module FDRE (Q, C, CE, D, R);
+
+    parameter INIT = 1'b0;
+
+    output Q;
+
+    input  C, CE, D, R;
+
+    wire Q;
+    reg q_out;
+
+    initial q_out = INIT;
+
+    assign Q = q_out;
+
+    always @(posedge C )
+        if (R)
+	     q_out <=  0;
+         else if (CE)
+	     q_out <=  D;
+
+endmodule

FDS.v

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+
+`timescale  1 ps / 1 ps
+
+
+module FDS (Q, C, D, S);
+
+    parameter INIT = 1'b1;
+
+    output Q;
+
+    input  C, D, S;
+
+    wire Q;
+    reg q_out;
+
+    initial q_out = INIT;
+
+    assign Q = q_out;
+
+    always @(posedge C )
+         if (S)
+	     q_out <=  1;
+         else
+	     q_out <=  D;
+
+endmodule

FDSE.v

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+`timescale  1 ps / 1 ps
+
+module FDSE (Q, C, CE, D, S);
+
+    parameter INIT = 1'b1;
+
+    output Q;
+
+    input  C, CE, D, S;
+
+    wire Q;
+    reg q_out;
+
+    initial q_out = INIT;
+
+    assign Q = q_out;
+
+    always @(posedge C )
+	  if (S)
+	     q_out <=  1;
+	  else if (CE)
+	     q_out <=  D;
+
+endmodule

GND.v

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+
+`timescale  1 ps / 1 ps
+
+module GND(G);
+
+    output G;
+
+	assign G = 1'b0;
+
+endmodule
+

INV.v

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+
+`timescale  1 ps / 1 ps
+
+
+module INV (O, I);
+
+    output O;
+
+    input  I;
+
+	not N1 (O, I);
+
+endmodule
+

LDC.v

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+// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/LDC.v,v 1.12 2006/04/10 20:46:00 yanx Exp $
+///////////////////////////////////////////////////////////////////////////////
+// Copyright (c) 1995/2004 Xilinx, Inc.
+// All Right Reserved.
+///////////////////////////////////////////////////////////////////////////////
+//   ____  ____
+//  /   /\/   /
+// /___/  \  /    Vendor : Xilinx
+// \   \   \/     Version : 10.1
+//  \   \         Description : Xilinx Functional Simulation Library Component
+//  /   /                  Transparent Data Latch with Asynchronous Clear
+// /___/   /\     Filename : LDC.v
+// \   \  /  \    Timestamp : Thu Mar 25 16:42:52 PST 2004
+//  \___\/\___\
+//
+// Revision:
+//    03/23/04 - Initial version.
+//    02/04/05 - Rev 0.0.1 Remove input/output bufs; Seperate GSR from clock block.
+//    08/09/05 - Add GSR to main block (CR 215196).
+//    03/31/06 - Add specify block for 100ps delay. (CR 228298)
+// End Revision
+
+`timescale  1 ps / 1 ps
+
+
+module LDC (Q, CLR, D, G);
+
+    parameter INIT = 1'b0;
+
+    output Q;
+    wire Q;
+
+    input  CLR, D, G;
+
+    reg q_out;
+
+    initial q_out = INIT;
+
+    assign Q = q_out;
+
+    always @(CLR or D or G)
+	    if (CLR)
+		q_out = 0;
+	    else if (G)
+		q_out = D;
+
+    specify
+	if (!CLR && G)
+	    (D +=> Q) = (100, 100);
+	if (!CLR)
+	    (posedge G => (Q +: D)) = (100, 100);
+	(posedge CLR => (Q +: 1'b0)) = (0, 0);
+    endspecify
+endmodule

LUT1.v

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+
+`timescale  1 ps / 1 ps
+
+
+module LUT1 (O, I0);
+
+    parameter INIT = 2'h0;
+
+    input I0;
+
+    output O;
+
+    wire O;
+
+    assign O = (INIT[0] == INIT[1]) ? INIT[0] : INIT[I0];
+
+endmodule

LUT2.v

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+
+`timescale  1 ps / 1 ps
+
+
+module LUT2 (O, I0, I1);
+
+    parameter INIT = 4'h0;
+
+    input I0, I1;
+
+    output O;
+
+    reg  O;
+    wire [1:0] s;
+
+    assign s = {I1, I0};
+
+    always @(s)
+       if ((s[1]^s[0] ==1) || (s[1]^s[0] ==0))
+           O = INIT[s];
+         else if ((INIT[0] == INIT[1]) && (INIT[2] == INIT[3]) && (INIT[0] == INIT[2])) 
+           O = INIT[0];
+         else if ((s[1] == 0) && (INIT[0] == INIT[1]))
+           O = INIT[0];
+         else if ((s[1] == 1) && (INIT[2] == INIT[3])) 
+           O = INIT[2];
+         else if ((s[0] == 0) && (INIT[0] == INIT[2])) 
+           O = INIT[0];
+         else if ((s[0] == 1) && (INIT[1] == INIT[3]))
+           O = INIT[1];
+         else
+           O = 1'bx;
+endmodule

LUT3.v

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+
+`timescale  1 ps / 1 ps
+
+
+module LUT3 (O, I0, I1, I2);
+
+    parameter INIT = 8'h00;
+
+    input I0, I1, I2;
+
+    output O;
+
+    reg O;
+    reg tmp;
+
+    always @(  I2 or  I1 or  I0 )  begin
+      tmp =  I0 ^ I1  ^ I2;
+      if ( tmp == 0 || tmp == 1)
+           O = INIT[{I2, I1, I0}];
+      else
+           O = lut3_mux4 ( {1'b0, 1'b0, lut3_mux4 (INIT[7:4], {I1, I0}),
+                          lut3_mux4 (INIT[3:0], {I1, I0}) }, {1'b0, I2});
+    end
+
+  function lut3_mux4;
+  input [3:0] d;
+  input [1:0] s;
+
+  begin
+       if ((s[1]^s[0] ==1) || (s[1]^s[0] ==0))
+           lut3_mux4 = d[s];
+         else if ((d[0] === d[1]) && (d[2] === d[3]) && (d[0] === d[2]))
+           lut3_mux4 = d[0];
+         else if ((s[1] == 0) && (d[0] === d[1]))
+           lut3_mux4 = d[0];
+         else if ((s[1] == 1) && (d[2] === d[3]))
+           lut3_mux4 = d[2];
+         else if ((s[0] == 0) && (d[0] === d[2]))
+           lut3_mux4 = d[0];
+         else if ((s[0] == 1) && (d[1] === d[3]))
+           lut3_mux4 = d[1];
+         else
+           lut3_mux4 = 1'bx;
+   end
+   endfunction
+
+endmodule
+
+