improved BUFIO2 and ISERDES2 models

BUFIO2.v

@@ -15,26 +15,27 @@ module BUFIO2 (DIVCLK, IOCLK, SERDESSTROBE, I);
    reg 	     div_clk;
    reg 	     serdes_strobe;
    wire [2:0] next_div_count = div_count + 1;
+
+   /* verilator lint_off WIDTH */
+   wire [2:0] divider = (USE_DOUBLER == "FALSE") ? DIVIDE : DIVIDE/2;
 
    always @(posedge I) begin
-      /* verilator lint_off WIDTH */
-      if(next_div_count == DIVIDE) begin
+      if(next_div_count == divider) begin
 	 div_clk <= 1;
 	 serdes_strobe <= 1;
 	 div_count <= 0;
       end else begin
 	 serdes_strobe <= 0;
 	 div_count <= next_div_count;
-	 if(next_div_count >= (DIVIDE/2)) begin
+	 if(next_div_count >= divider >> 1) begin
 	    div_clk <= 0;
 	 end
       end
-      /* verilator lint_on WIDTH */
    end // always @ (posedge I)
-
-   assign DIVCLK = (DIVIDE == 1) ? I : div_clk;
-   assign SERDESSTROBE = (DIVIDE == 1) ? 1'b0 : serdes_strobe;
-   assign IOCLK = I;
+   assign DIVCLK = (DIVIDE == 1 || DIVIDE_BYPASS == "TRUE") ? I : div_clk;
+   assign SERDESSTROBE = (DIVIDE == 1) ? 1'b0 : serdes_strobe & I;
+   assign IOCLK = (I_INVERT == "FALSE") ? I : !I;
+   /* verilator lint_on WIDTH */
 
 endmodule // BUFIO2
 

ISERDES2.v

@@ -36,11 +36,11 @@ module ISERDES2 (
   output DFB;
   output FABRICOUT;
   output INCDEC;
-  output Q1;
-  output Q2;
-  output Q3;
-  output Q4;
-  output SHIFTOUT;
+  output reg Q1;
+  output reg Q2;
+  output reg Q3;
+  output reg Q4;
+  output reg SHIFTOUT;
   output VALID;
 
   input BITSLIP;
@@ -67,19 +67,21 @@ module ISERDES2 (
 //  assign Q2 = 0;
 //  assign Q3 = 0;
 //  assign Q4 = 0;
-  assign SHIFTOUT = 0;
-  assign VALID = 0;
+   assign VALID = 0;
 
    reg [3:0] srA;
    wire      Din = (SERDES_MODE == "SLAVE") ? SHIFTIN : D;
 
    always @(posedge CLK0 or posedge CLK1) begin
-      srA <= { Din, srA[2:0] };
+      srA <= { Din, srA[3:1] };
+      SHIFTOUT <= srA[0];
+      if(IOCE) begin
+	 Q1 <= srA[0];
+	 Q2 <= srA[1];
+	 Q3 <= srA[2];
+	 Q4 <= srA[3];
+      end
    end
-   assign Q1 = srA[0];
-   assign Q2 = srA[1];
-   assign Q3 = srA[2];
-   assign Q4 = srA[3];
 
 
 endmodule // ISERDES2