cores/video: Simplify VTG/DMA synchronization and re-synchronize on e…

…ach end of frame.
enjoy-digital · Oct 27, 2023 · b5a9106 · b5a9106
1 parent 5842ad7
commit b5a9106
Showing 1 changed file with 7 additions and 10 deletions.
diff --git a/litex/soc/cores/video.py b/litex/soc/cores/video.py
@@ -693,20 +693,14 @@ def __init__(self, dram_port, hres=800, vres=600, base=0x00000000, fifo_depth=65
             video_pipe_source = self.cdc.source
 
         # Video Synchronization/Generation.
-        fsm = FSM(reset_state="VTG-SYNC")
+        fsm = FSM(reset_state="SYNC")
         fsm = ClockDomainsRenamer(clock_domain)(fsm)
         fsm = ResetInserter()(fsm)
         self.submodules += fsm
         self.specials += MultiReg(self.dma.fsm.reset, fsm.reset, clock_domain)
-        fsm.act("VTG-SYNC",
-            vtg_sink.ready.eq(1),
+        fsm.act("SYNC",
+            vtg_sink.ready.eq(~fsm.reset),
             If(vtg_sink.valid & vtg_sink.last,
-                NextState("DMA-SYNC")
-            )
-        )
-        fsm.act("DMA-SYNC",
-            video_pipe_source.ready.eq(1),
-            If(video_pipe_source.valid & video_pipe_source.last,
                 NextState("RUN")
             )
         )
@@ -715,10 +709,13 @@ def __init__(self, dram_port, hres=800, vres=600, base=0x00000000, fifo_depth=65
             If(vtg_sink.valid & vtg_sink.de,
                 video_pipe_source.connect(source, keep={"valid", "ready"}),
                 vtg_sink.ready.eq(source.valid & source.ready),
-
+                If(video_pipe_source.valid & video_pipe_source.last,
+                    NextState("SYNC")
+                )
             ),
             vtg_sink.connect(source, keep={"de", "hsync", "vsync"}),
         )
+
         if (depth == 32):
             self.comb += [
                source.r.eq(video_pipe_source.data[ 0: 8]),