soc/integration/soc: add_jtagbone: pass address_width to UARTBone con…

…structor
enjoy-digital · Dec 9, 2023 · c1871ea · c1871ea
1 parent acd66f1
commit c1871ea
Showing 1 changed file with 5 additions and 1 deletion.
diff --git a/litex/soc/integration/soc.py b/litex/soc/integration/soc.py
@@ -1527,7 +1527,11 @@ def add_jtagbone(self, name="jtagbone", chain=1):
         # Core.
         self.check_if_exists(name)
         jtagbone_phy = JTAGPHY(device=self.platform.device, chain=chain, platform=self.platform)
-        jtagbone = uart.UARTBone(phy=jtagbone_phy, clk_freq=self.sys_clk_freq)
+        jtagbone = uart.UARTBone(
+            phy           = jtagbone_phy,
+            clk_freq      = self.sys_clk_freq,
+            address_width = self.bus.address_width
+        )
         self.add_module(name=f"{name}_phy", module=jtagbone_phy)
         self.add_module(name=name,          module=jtagbone)
         self.bus.add_master(name=name, master=jtagbone.wishbone)