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enable PEs with multiple reg/mem slave interfaces #318

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merged 6 commits into from
Mar 29, 2022
+102 −30
Merged

enable PEs with multiple reg/mem slave interfaces #318

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07379d4
multiple interrupts per PE
StaCu Mar 23, 2022
bf13644
addrmap & statuscore for PEs with many intf and ipec
StaCu Mar 23, 2022
710519b
simplified replacing (vlnv kid)
StaCu Mar 24, 2022
79714d0
fix indentation
StaCu Mar 24, 2022
7e8f313
moved status core interface renaming into plugin
StaCu Mar 24, 2022
e8e3c67
clarifying comment
StaCu Mar 29, 2022
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1 change: 1 addition & 0 deletions toolflow/vivado/arch/axi4mm/axi4mm.tcl
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Original file line number Diff line number Diff line change
Expand Up @@ -360,6 +360,7 @@ namespace eval arch {
set intr_name "PE_${i}_${pe_sub_interrupt}"
puts "Creating interrupt $intr_name"
connect_bd_net $pin [::tapasco::ip::add_interrupt $intr_name "design"]
incr pe_sub_interrupt
}
incr i
}
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85 changes: 55 additions & 30 deletions toolflow/vivado/arch/common/arch.tcl
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Expand Up @@ -35,40 +35,65 @@ namespace eval arch {
set pes [lsort [get_processing_elements]]

foreach pe $pes {
puts " processing $pe registers ..."
set usrs [lsort [get_bd_addr_segs -filter { USAGE == register } $pe/*]]
for {set i 0} {$i < [llength $usrs]} {incr i} {
set seg [lindex $usrs $i]
puts " seg: $seg"
if {[get_property MODE [get_bd_intf_pins -of_objects $seg]] == "Master"} {
puts " skipping master seg $seg"
} else {
set intf [get_bd_intf_pins -of_objects $seg]
set range [get_property RANGE $seg]
set offset [next_valid_address $offset $range]
::platform::addressmap::add_processing_element [llength [dict keys $ret]] $offset $range
dict set ret $intf "interface $intf [format "offset 0x%08x range 0x%08x" $offset $range] kind register"
incr offset $range
set reg_segs [lsort [get_bd_addr_segs -filter { USAGE == register } $pe/*]]
set mem_segs [lsort [get_bd_addr_segs -filter { USAGE == memory } $pe/*]]
if {[llength $reg_segs] <= 1 && [llength $mem_segs] <= 1} {
puts " processing $pe registers ..."
for {set i 0} {$i < [llength $reg_segs]} {incr i} {
set seg [lindex $reg_segs $i]
puts " seg: $seg"
if {[get_property MODE [get_bd_intf_pins -of_objects $seg]] == "Master"} {
puts " skipping master seg $seg"
} else {
set intf [get_bd_intf_pins -of_objects $seg]
set range [get_property RANGE $seg]
set offset [next_valid_address $offset $range]
::platform::addressmap::add_processing_element [llength [dict keys $ret]] $offset $range
dict set ret $intf "interface $intf [format "offset 0x%08x range 0x%08x" $offset $range] kind register"
incr offset $range
}
}
}
puts " processing $pe memories ..."
set usrs [lsort [get_bd_addr_segs -filter { USAGE == memory } $pe/*]]
for {set i 0} {$i < [llength $usrs]} {incr i} {
set seg [lindex $usrs $i]
puts " seg: $seg"
if {[get_property MODE [get_bd_intf_pins -of_objects $seg]] == "Master"} {
puts " skipping master seg $seg"
continue
} else {
set intf [get_bd_intf_pins -of_objects $seg]
set range [get_property RANGE $seg]
set offset [next_valid_address $offset $range]
::platform::addressmap::add_processing_element [llength [dict keys $ret]] $offset $range
dict set ret $intf "interface $intf [format "offset 0x%08x range 0x%08x" $offset $range] kind memory"
incr offset $range
puts " processing $pe memories ..."
for {set i 0} {$i < [llength $mem_segs]} {incr i} {
set seg [lindex $mem_segs $i]
puts " seg: $seg"
if {[get_property MODE [get_bd_intf_pins -of_objects $seg]] == "Master"} {
puts " skipping master seg $seg"
} else {
set intf [get_bd_intf_pins -of_objects $seg]
set range [get_property RANGE $seg]
set offset [next_valid_address $offset $range]
::platform::addressmap::add_processing_element [llength [dict keys $ret]] $offset $range
dict set ret $intf "interface $intf [format "offset 0x%08x range 0x%08x" $offset $range] kind memory"
incr offset $range
}
}
} else {
# if there is more than one reg/mem interface, we assume that the user knows what they are doing and add them in the same order
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puts " processing $pe registers and memories ..."
set all_segs [lsort [get_bd_addr_segs $pe/*]]
for {set i 0} {$i < [llength $all_segs]} {incr i} {
set seg [lindex $all_segs $i]
puts " seg: $seg"
if {[get_property MODE [get_bd_intf_pins -of_objects $seg]] == "Master"} {
puts " skipping master seg $seg"
} else {
set intf [get_bd_intf_pins -of_objects $seg]
set range [get_property RANGE $seg]
set usage [get_property USAGE $seg]
set offset [next_valid_address $offset $range]
::platform::addressmap::add_processing_element [llength [dict keys $ret]] $offset $range
if { $usage == "register" } {
dict set ret $intf "interface $intf [format "offset 0x%08x range 0x%08x" $offset $range] kind register"
} else {
dict set ret $intf "interface $intf [format "offset 0x%08x range 0x%08x" $offset $range] kind memory"
}
incr offset $range
}
}
}
}
return $ret
}

}
9 changes: 9 additions & 0 deletions toolflow/vivado/common/ip.tcl
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Expand Up @@ -540,6 +540,15 @@ namespace eval ::tapasco::ip {
set kid [dict get [::tapasco::get_composition] $kind id]
set vlnv [dict get [::tapasco::get_composition] $kind vlnv]

set ipecfeature [tapasco::get_feature "IPEC"]
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set intfname [lindex [split $intf /] end]
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if {[dict exists $ipecfeature $vlnv $intfname]} {
set kid [dict get $ipecfeature $vlnv $intfname "kid"]
set kid [expr int($kid)]
set vlnv [dict get $ipecfeature $vlnv $intfname "vlnv"]
puts " replaced vlnv $vlnv kid $kid"
}

lappend slots [json::write object "Type" [json::write string "Kernel"] "SlotId" $slot_id "Kernel" $kid \
"Offset" [json::write string [format "0x%016x" [expr "[dict get $addr $intf "offset"] - [::platform::get_pe_base_address]"]]] \
"Size" [json::write string [format "0x%016x" [dict get $addr $intf "range"]]] \
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