added master arm, removed pwm_set_deadtime api

src-app/cli.cpp

@@ -248,7 +248,6 @@ void cli_execute(Cereal* cer, char* str)
     {
         pwm_set_remap(cfg.phase_map);
         pwm_set_period(cfg.pwm_period);
-        pwm_set_deadtime(cfg.pwm_deadtime);
         pwm_set_braking(true);
         pwm_set_all_duty_remapped(0, 0, 0);
 
@@ -330,7 +329,6 @@ void cli_execute(Cereal* cer, char* str)
             if (test_mode == 'd' || test_mode == 'D') {
                 pwr = cfg.pwm_period - cfg.pwm_deadtime;
                 pwr100 = 100;
-                pwm_set_deadtime(cfg.pwm_deadtime);
                 if (test_mode == 'd') {
                     pwm_set_all_duty_remapped(pwr, 0, 0);
                 }

src-app/crsf.cpp

@@ -29,6 +29,7 @@ static uint32_t last_good_time = 0;
 static uint32_t last_any_time  = 0;
 static uint8_t  good_pulse_cnt = 0;
 static uint8_t  bad_pulse_cnt  = 0;
+static uint8_t  master_arm_chan = 0;
 
 #ifdef DEBUG_CRSF_RATE
 static uint32_t data_rate_cnt = 0;
@@ -198,7 +199,9 @@ void CrsfChannel::task(void)
         {
             arming_tick = now; // stage next time to check
 
-            if ((now - last_good_time) <= 100 && read() == 0) { // signal is still valid and reading 0
+            if ((now - last_good_time) <= 100 && (read() == 0
+                || (master_arm_chan > 0 && crsf_readChan(master_arm_chan) > CRSF_CHANNEL_VALUE_MID)))
+            { // signal is still valid and reading 0 or master arm active
                 arming_cnt++;
                 if (arming_cnt >= arm_pulses_required) { // met requirements
                     #ifdef DEBUG_CRSF
@@ -320,6 +323,11 @@ uint16_t crsf_readChan(uint8_t i)
     return crsf_channels[i - 1];
 }
 
+void crsf_setMasterArmChan(uint8_t c)
+{
+    master_arm_chan = c;
+}
+
 #ifdef __cplusplus
 }
 #endif

src-app/crsf.h

@@ -43,6 +43,7 @@ class CrsfChannel : public RcChannel
 extern "C" {
 #endif
 extern uint16_t crsf_readChan(uint8_t i);
+extern void crsf_setMasterArmChan(uint8_t c);
 #ifdef __cplusplus
 }
 #endif

src-app/default_config.h

@@ -25,6 +25,8 @@ const EEPROM_data_t default_eeprom __attribute__((aligned(4))) = {
     .channel_1          = 1,
     .channel_2          = 2,
     .channel_mode       = 0,
+    .channel_brake      = 0,
+    .channel_masterarm  = 0,
 
     .rc_mid             = 1500,
     .rc_range           = 500,

src-app/hw_tests.cpp

@@ -160,7 +160,6 @@ void hwtest_pwm_max(void)
     pwm_all_flt();
     pwm_set_braking(true);
     pwm_set_period(PWM_DEFAULT_PERIOD);
-    pwm_set_deadtime(PWM_DEFAULT_DEADTIME);
     pwm_set_remap(1);
     pwm_set_loadbalance(false);
     while (true)

src-app/main.cpp

@@ -135,6 +135,8 @@ int main(void)
             rc3 = &crsf_3;
         }
 
+        crsf_setMasterArmChan(cfg.channel_masterarm);
+
         dbg_printf("input mode [%u] CRSF\r\n", cfg.input_mode);
     }
     else

src-app/phaseout.h

@@ -13,7 +13,6 @@ extern bool braking;
 
 extern void pwm_init();        // implemented in HAL
 extern void pwm_set_period(uint32_t x);   // used to set frequency from user config
-extern void pwm_set_deadtime(uint32_t x); // used to set deadtime from user config
 
 // implemented in HAL
 extern void pwm_setFlt_A();

src-app/types.h

@@ -75,6 +75,7 @@ typedef struct
     uint8_t channel_2;
     uint8_t channel_mode;  // used for either setting the volt-split mode during run-time, or used as the 3rd channel for direct-PWM mode
     uint8_t channel_brake; // used to enable or disable braking during run-time
+    uint8_t channel_masterarm; // used to instantly arm with a switch on the radio
 
     // RC signal calibration, units are microseconds
     uint16_t rc_mid;       // do not apply to CRSF data

src-app/userconfig.c

@@ -57,6 +57,7 @@ const EEPROM_data_t default_eeprom __attribute__((aligned(4))) = {
     .channel_2          = 2,
     .channel_mode       = 0,
     .channel_brake      = 0,
+    .channel_masterarm  = 0,
 
     .rc_mid             = 1500,
     .rc_range           = 500,
@@ -98,10 +99,10 @@ const EEPROM_data_t default_eeprom __attribute__((aligned(4))) = {
 __attribute__((__section__(".eeprom")))
 const EEPROM_data_t cfge = {
     FOOL_AM32
-    .magic      = EEPROM_MAGIC,
+    .magic      = EEPROM_MAGIC-1, // magic is different, will be restored if a valid write occurs, this is to differentiate between ihex files with or without EEPROM payload
     .write_cnt  = 0,
     .boot_log   = 0,
-    .magic_end  = EEPROM_MAGIC,
+    .magic_end  = EEPROM_MAGIC-1,
 };
 #define cfg_addr    ((uint32_t)(&cfge))
 
@@ -128,7 +129,10 @@ const EEPROM_item_t cfg_items[] __attribute__((aligned(4))) = {
     DCLR_ITM("channel_1"      , channel_1         ),
     DCLR_ITM("channel_2"      , channel_2         ),
     DCLR_ITM("channel_mode"   , channel_mode      ),
+    #ifndef PWM_ENABLE_BRIDGE
     DCLR_ITM("channel_brake"  , channel_brake     ),
+    #endif
+    DCLR_ITM("master_arm"     , channel_masterarm ),
     DCLR_ITM("rc_mid"         , rc_mid            ),
     DCLR_ITM("rc_range"       , rc_range          ),
     DCLR_ITM("rc_deadzone"    , rc_deadzone       ),
@@ -230,13 +234,21 @@ bool eeprom_verify_header(uint32_t* ptr8)
         eeprom_error_log |= 0x04;
         #endif
     }
+    return ret;
+}
+
+bool eeprom_rectify_bootloader_ver(void)
+{
+    volatile EEPROM_data_t* ptre = (volatile EEPROM_data_t*)cfg_addr;
+    bool ret = true;
     #ifndef DEVELOPMENT_BOARD
     if (ptre->fool_am32_bootloader_version != eeprom_get_bootloader_ver()) {
         ret = false;
         dbg_printf("ERR: bootloader version does not match (%u != %u)\r\n", ptre->fool_am32_bootloader_version, eeprom_get_bootloader_ver());
         #ifndef RELEASE_BUILD
         eeprom_error_log |= 0x08;
         #endif
+        eeprom_save();
     }
     #endif
     return ret;
@@ -287,6 +299,8 @@ bool eeprom_load_or_default(void)
         }
         #endif
 
+        eeprom_rectify_bootloader_ver();
+
         return true;
     }
     else
@@ -383,7 +397,6 @@ void eeprom_delay_dirty(void)
 extern uint32_t arm_pulses_required;
 extern uint32_t disarm_timeout;
 extern void pwm_set_period(uint32_t);
-extern void pwm_set_deadtime(uint32_t);
 extern void pwm_set_remap(uint8_t);
 extern void pwm_set_loadbalance(bool);
 extern void pwm_set_braking(bool);
@@ -394,7 +407,6 @@ void load_runtime_configs(void)
     disarm_timeout      = cfg.disarm_timeout;
     pwm_set_braking    (cfg.braking);
     pwm_set_period     (cfg.pwm_period);
-    pwm_set_deadtime   (cfg.pwm_deadtime);
     pwm_set_remap      (cfg.phase_map);
     pwm_set_loadbalance(cfg.load_balance);
     load_config_pid();

src-mcu/at32/phaseout_at32.c

@@ -72,10 +72,5 @@ void pwm_set_period(uint32_t x)
     PWMOUTTIMx->pr = x;
 }
 
-void pwm_set_deadtime(uint32_t x)
-{
-    PWMOUTTIMx->brk_bit.dtc = x;
-}
-
 #include "stm32_at32_compat.h"
 #include "phaseout_shared.h"

src-mcu/stm32/phaseout_stm32.c

@@ -251,11 +251,6 @@ void pwm_set_period(uint32_t x)
     LL_TIM_SetAutoReload(PWMOUTTIMx, x);
 }
 
-void pwm_set_deadtime(uint32_t x)
-{
-    LL_TIM_OC_SetDeadTime(PWMOUTTIMx, x);
-}
-
 #ifdef PWM_NEED_IRQ
 void TIM1_BRK_UP_TRG_COM_IRQHandler(void)
 {