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updated verilator call with top-module specified as testbench (#459)
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Added short change to Verilator template that specifies the top-level
module being used.
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cknizek authored Sep 2, 2024
1 parent 5050fc6 commit 437a49d
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Showing 3 changed files with 5 additions and 2 deletions.
3 changes: 3 additions & 0 deletions bin/simulate_with_verilator.py
Original file line number Diff line number Diff line change
Expand Up @@ -29,6 +29,7 @@ def simulate_with_verilator(
clock_name: Optional[str] = None,
include_dirs: List[Union[str, Path]] = [],
extra_args: List[str] = [],
testbench_module_name: str = "testbench",
max_num_tests=MAX_NUM_TESTS,
ignore_missing_test_module_file: bool = False,
expect_all_zero_outputs: bool = False,
Expand Down Expand Up @@ -96,6 +97,7 @@ def simulate_with_verilator(
testbench_exe_filepath=testbench_exe_filepath,
testbench_inputs_filepath=testbench_inputs_filepath,
obj_dirpath=obj_dirpath,
top_module=testbench_module_name,
extra_verilator_args=" ".join(
[str(path) for path in verilog_filepaths]
+ [f"-I{dir}" for dir in include_dirs]
Expand All @@ -112,6 +114,7 @@ def simulate_with_verilator(
testbench_source = testbench_template_source.format(
max_input_bitwidth=max([bw for _, bw in module_inputs]),
test_module_name=test_module_name,
testbench_module_name=testbench_module_name,
ground_truth_module_name=ground_truth_module_name,
test_module_port_list=",".join(
[f".{name}({name})" for name, _ in module_inputs]
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2 changes: 1 addition & 1 deletion misc/verilator.mk.template
Original file line number Diff line number Diff line change
Expand Up @@ -9,4 +9,4 @@ simulate: {testbench_exe_filepath} {testbench_inputs_filepath}
{testbench_exe_filepath} < {testbench_inputs_filepath}

{testbench_exe_filepath}: {testbench_filepath}
$(VERILATOR) -o {testbench_exe_filepath} --assert --main --timing --Mdir {obj_dirpath} --cc --exe --build $^ {extra_verilator_args}
$(VERILATOR) --top-module {top_module} -o {testbench_exe_filepath} --assert --main --timing --Mdir {obj_dirpath} --cc --exe --build $^ {extra_verilator_args}
2 changes: 1 addition & 1 deletion misc/verilator_testbench.sv.template
Original file line number Diff line number Diff line change
@@ -1,4 +1,4 @@
module testbench;
module {testbench_module_name};

{input_output_declarations}

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