Setup release infrastruture

bin/lakeroad-portfolio.py

@@ -113,7 +113,7 @@
 args, rest = parser.parse_known_args()
 
 # Process the "--" flag which marks the end of the flags for the script.
-rest = rest[1:] if rest[0] == "--" else rest
+rest = rest[1:] if (len(rest) > 0 and rest[0] == "--") else rest
 
 
 def _parse_flag_set(flag_set: str) -> List[str]:

dependencies.sh

@@ -28,5 +28,5 @@ export YICES2_COMMIT_HASH="5326f0d645df6e38ae6e7d944381d01ba7d805ab"
 export BITWUZLA_COMMIT_HASH="b655bc0cde570258367bf8f09a113bc7b95e46e9"
 export RACKET_FMT_COMMIT_HASH="7d0a3dfff3a6cacfb59972a56d476556f89a0b1b"
 export YOSYS_COMMIT_HASH="70d35314dbd7521870047ed607897f22dc48cbc3"
-export CVC5_COMMIT_HASH="ebfdf84d5698eeb83e0fa4e45101fe4a8f4543eb"
+export CVC5_COMMIT_HASH="1d05a49387c041dba17f85f3c4e738b4b388ace2"
 export VERILATOR_COMMIT_HASH="881c6ee6557fbde017466553b2f0918250e9c4bd"

release_files/README.md

@@ -0,0 +1,30 @@
+# Lakeroad
+
+Open issues here:
+<https://github.com/uwsampl/lakeroad/issues/new>
+
+Thanks for downloading a release of Lakeroad.
+
+To install Lakeroad on your system, simply add `./bin` to your `$PATH`.
+
+To run the examples, run
+
+```sh
+./run-examples.sh
+```
+
+Examples are located in `./examples/`.
+
+To see documentation of Lakeroad's flags, run both
+
+```sh
+./bin/lakeroad --help
+```
+
+and
+
+```sh
+./deps/lakeroad/bin/lakeroad-single-solver --help
+```
+
+Note that `./bin/lakeroad` is a wrapper over the core Lakeroad binary, `lakeroad-single-solver`. To see Lakeroad's full options, please run the core Lakeroad binary with `--help`.

release_files/examples/verilog/xilinx_ultrascale_1stage_addmuladd_signed_11bit.sv

@@ -0,0 +1,40 @@
+// RUN: racket $LAKEROAD_DIR/bin/main.rkt \
+// RUN:  --solver bitwuzla \
+// RUN:  --verilog-module-filepath %s \
+// RUN:  --architecture xilinx-ultrascale-plus \
+// RUN:  --template dsp \
+// RUN:  --out-format verilog \
+// RUN:  --top-module-name top \
+// RUN:  --verilog-module-out-signal out:11 \
+// RUN:  --initiation-interval 1 \
+// RUN:  --clock-name clk \
+// RUN:  --module-name out \
+// RUN:  --input-signal a:11 \
+// RUN:  --input-signal b:11 \
+// RUN:  --input-signal c:11 \
+// RUN:  --input-signal d:11 \
+// RUN:  --extra-cycles 3 \
+// RUN:  --timeout 120 \
+// RUN: | FileCheck %s
+
+(* use_dsp = "yes" *) module top(
+	input signed [10:0] a,
+	input signed [10:0] b,
+	input signed [10:0] c,
+	input signed [10:0] d,
+	output [10:0] out,
+	input clk);
+
+	logic signed [21:0] stage0;
+
+	always @(posedge clk) begin
+	stage0 <= ((d + a) * b) + c;
+
+	end
+
+	assign out = stage0;
+endmodule
+
+// CHECK: module out(a, b, c, clk, d, out);
+// CHECK:   DSP48E2 #(
+// CHECK: endmodule

release_files/examples/xilinx_ultrascale_1stage_addmuladd_signed_11bit.sh

@@ -0,0 +1,21 @@
+#!/bin/bash
+
+SCRIPT_DIR=$( cd -- "$( dirname -- "${BASH_SOURCE[0]}" )" &> /dev/null && pwd )
+
+"$SCRIPT_DIR/../bin/lakeroad" \
+ --bitwuzla --stp --yices --cvc5 \
+ --verilog-module-filepath "$SCRIPT_DIR/verilog/xilinx_ultrascale_1stage_addmuladd_signed_11bit.sh" \
+ --architecture xilinx-ultrascale-plus \
+ --template dsp \
+ --out-format verilog \
+ --top-module-name top \
+ --verilog-module-out-signal out:11 \
+ --initiation-interval 1 \
+ --clock-name clk \
+ --module-name out \
+ --input-signal a:11 \
+ --input-signal b:11 \
+ --input-signal c:11 \
+ --input-signal d:11 \
+ --extra-cycles 3 \
+ --timeout 120

release_files/run-examples.sh

@@ -0,0 +1,9 @@
+#!/bin/bash
+
+SCRIPT_DIR=$( cd -- "$( dirname -- "${BASH_SOURCE[0]}" )" &> /dev/null && pwd )
+
+# Run all examples in ./examples
+for example in "$SCRIPT_DIR/examples"/*; do
+  echo "Running example $example"
+  ./"$example"
+done